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1da177e4
LT		 1/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2/*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11*/
1da177e4 12
df950828
K		 13#define DRV_NAME "DL2000/TC902x-based linux driver"
14#define DRV_VERSION "v1.19"
15#define DRV_RELDATE "2007/08/12"
1da177e4 16#include "dl2k.h"
c4694c76 17#include <linux/dma-mapping.h>
1da177e4
LT		 18
19static char version[] __devinitdata =
6aa20a22 20 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
1da177e4
LT		 21#define MAX_UNITS 8
22static int mtu[MAX_UNITS];
23static int vlan[MAX_UNITS];
24static int jumbo[MAX_UNITS];
25static char *media[MAX_UNITS];
26static int tx_flow=-1;
27static int rx_flow=-1;
28static int copy_thresh;
29static int rx_coalesce=10; /* Rx frame count each interrupt */
30static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
31static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
32
33
34MODULE_AUTHOR ("Edward Peng");
35MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
36MODULE_LICENSE("GPL");
37module_param_array(mtu, int, NULL, 0);
38module_param_array(media, charp, NULL, 0);
39module_param_array(vlan, int, NULL, 0);
40module_param_array(jumbo, int, NULL, 0);
41module_param(tx_flow, int, 0);
42module_param(rx_flow, int, 0);
43module_param(copy_thresh, int, 0);
44module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
45module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
46module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
47
48
49/* Enable the default interrupts */
50#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
51 UpdateStats | LinkEvent)
52#define EnableInt() \
53writew(DEFAULT_INTR, ioaddr + IntEnable)
54
f71e1309
AV		 55static const int max_intrloop = 50;
56static const int multicast_filter_limit = 0x40;
1da177e4
LT		 57
58static int rio_open (struct net_device *dev);
59static void rio_timer (unsigned long data);
60static void rio_tx_timeout (struct net_device *dev);
61static void alloc_list (struct net_device *dev);
62static int start_xmit (struct sk_buff *skb, struct net_device *dev);
7d12e780 63static irqreturn_t rio_interrupt (int irq, void *dev_instance);
1da177e4
LT		 64static void rio_free_tx (struct net_device *dev, int irq);
65static void tx_error (struct net_device *dev, int tx_status);
66static int receive_packet (struct net_device *dev);
67static void rio_error (struct net_device *dev, int int_status);
68static int change_mtu (struct net_device *dev, int new_mtu);
69static void set_multicast (struct net_device *dev);
70static struct net_device_stats *get_stats (struct net_device *dev);
71static int clear_stats (struct net_device *dev);
72static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
73static int rio_close (struct net_device *dev);
74static int find_miiphy (struct net_device *dev);
75static int parse_eeprom (struct net_device *dev);
76static int read_eeprom (long ioaddr, int eep_addr);
77static int mii_wait_link (struct net_device *dev, int wait);
78static int mii_set_media (struct net_device *dev);
79static int mii_get_media (struct net_device *dev);
80static int mii_set_media_pcs (struct net_device *dev);
81static int mii_get_media_pcs (struct net_device *dev);
82static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
83static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
84 u16 data);
85
7282d491 86static const struct ethtool_ops ethtool_ops;
1da177e4
LT		 87
88static int __devinit
89rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
90{
91 struct net_device *dev;
92 struct netdev_private *np;
93 static int card_idx;
94 int chip_idx = ent->driver_data;
95 int err, irq;
96 long ioaddr;
97 static int version_printed;
98 void *ring_space;
99 dma_addr_t ring_dma;
100
101 if (!version_printed++)
102 printk ("%s", version);
103
104 err = pci_enable_device (pdev);
105 if (err)
106 return err;
107
108 irq = pdev->irq;
109 err = pci_request_regions (pdev, "dl2k");
110 if (err)
111 goto err_out_disable;
112
113 pci_set_master (pdev);
114 dev = alloc_etherdev (sizeof (*np));
115 if (!dev) {
116 err = -ENOMEM;
117 goto err_out_res;
118 }
1da177e4
LT		 119 SET_NETDEV_DEV(dev, &pdev->dev);
120
121#ifdef MEM_MAPPING
122 ioaddr = pci_resource_start (pdev, 1);
123 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
124 if (!ioaddr) {
125 err = -ENOMEM;
126 goto err_out_dev;
127 }
128#else
129 ioaddr = pci_resource_start (pdev, 0);
130#endif
131 dev->base_addr = ioaddr;
132 dev->irq = irq;
133 np = netdev_priv(dev);
134 np->chip_id = chip_idx;
135 np->pdev = pdev;
136 spin_lock_init (&np->tx_lock);
137 spin_lock_init (&np->rx_lock);
138
139 /* Parse manual configuration */
140 np->an_enable = 1;
141 np->tx_coalesce = 1;
142 if (card_idx < MAX_UNITS) {
143 if (media[card_idx] != NULL) {
144 np->an_enable = 0;
145 if (strcmp (media[card_idx], "auto") == 0 ||
6aa20a22 146 strcmp (media[card_idx], "autosense") == 0 ||
1da177e4 147 strcmp (media[card_idx], "0") == 0 ) {
6aa20a22 148 np->an_enable = 2;
1da177e4
LT		 149 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
150 strcmp (media[card_idx], "4") == 0) {
151 np->speed = 100;
152 np->full_duplex = 1;
153 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
154 || strcmp (media[card_idx], "3") == 0) {
155 np->speed = 100;
156 np->full_duplex = 0;
157 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
158 strcmp (media[card_idx], "2") == 0) {
159 np->speed = 10;
160 np->full_duplex = 1;
161 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
162 strcmp (media[card_idx], "1") == 0) {
163 np->speed = 10;
164 np->full_duplex = 0;
165 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
166 strcmp (media[card_idx], "6") == 0) {
167 np->speed=1000;
168 np->full_duplex=1;
169 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
170 strcmp (media[card_idx], "5") == 0) {
171 np->speed = 1000;
172 np->full_duplex = 0;
173 } else {
174 np->an_enable = 1;
175 }
176 }
177 if (jumbo[card_idx] != 0) {
178 np->jumbo = 1;
179 dev->mtu = MAX_JUMBO;
180 } else {
181 np->jumbo = 0;
182 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
183 dev->mtu = mtu[card_idx];
184 }
185 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
186 vlan[card_idx] : 0;
187 if (rx_coalesce > 0 && rx_timeout > 0) {
188 np->rx_coalesce = rx_coalesce;
189 np->rx_timeout = rx_timeout;
190 np->coalesce = 1;
191 }
192 np->tx_flow = (tx_flow == 0) ? 0 : 1;
193 np->rx_flow = (rx_flow == 0) ? 0 : 1;
194
195 if (tx_coalesce < 1)
196 tx_coalesce = 1;
197 else if (tx_coalesce > TX_RING_SIZE-1)
198 tx_coalesce = TX_RING_SIZE - 1;
199 }
200 dev->open = &rio_open;
201 dev->hard_start_xmit = &start_xmit;
202 dev->stop = &rio_close;
203 dev->get_stats = &get_stats;
204 dev->set_multicast_list = &set_multicast;
205 dev->do_ioctl = &rio_ioctl;
206 dev->tx_timeout = &rio_tx_timeout;
207 dev->watchdog_timeo = TX_TIMEOUT;
208 dev->change_mtu = &change_mtu;
209 SET_ETHTOOL_OPS(dev, &ethtool_ops);
210#if 0
211 dev->features = NETIF_F_IP_CSUM;
212#endif
213 pci_set_drvdata (pdev, dev);
214
215 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
216 if (!ring_space)
217 goto err_out_iounmap;
218 np->tx_ring = (struct netdev_desc *) ring_space;
219 np->tx_ring_dma = ring_dma;
220
221 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
222 if (!ring_space)
223 goto err_out_unmap_tx;
224 np->rx_ring = (struct netdev_desc *) ring_space;
225 np->rx_ring_dma = ring_dma;
226
227 /* Parse eeprom data */
228 parse_eeprom (dev);
229
230 /* Find PHY address */
231 err = find_miiphy (dev);
232 if (err)
233 goto err_out_unmap_rx;
6aa20a22 234
1da177e4
LT		 235 /* Fiber device? */
236 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
237 np->link_status = 0;
238 /* Set media and reset PHY */
239 if (np->phy_media) {
240 /* default Auto-Negotiation for fiber deivices */
241 if (np->an_enable == 2) {
242 np->an_enable = 1;
243 }
244 mii_set_media_pcs (dev);
245 } else {
246 /* Auto-Negotiation is mandatory for 1000BASE-T,
247 IEEE 802.3ab Annex 28D page 14 */
248 if (np->speed == 1000)
249 np->an_enable = 1;
250 mii_set_media (dev);
251 }
1da177e4
LT		 252
253 err = register_netdev (dev);
254 if (err)
255 goto err_out_unmap_rx;
256
257 card_idx++;
258
e174961c
JB		 259 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
260 dev->name, np->name, dev->dev_addr, irq);
1da177e4 261 if (tx_coalesce > 1)
6aa20a22 262 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
1da177e4
LT		 263 tx_coalesce);
264 if (np->coalesce)
265 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
6aa20a22 266 KERN_INFO "rx_timeout: \t%d ns\n",
1da177e4
LT		 267 np->rx_coalesce, np->rx_timeout*640);
268 if (np->vlan)
269 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
270 return 0;
271
272 err_out_unmap_rx:
273 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
274 err_out_unmap_tx:
275 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
276 err_out_iounmap:
277#ifdef MEM_MAPPING
278 iounmap ((void *) ioaddr);
279
280 err_out_dev:
281#endif
282 free_netdev (dev);
283
284 err_out_res:
285 pci_release_regions (pdev);
286
287 err_out_disable:
288 pci_disable_device (pdev);
289 return err;
290}
291
ddfce6bb 292static int
1da177e4
LT		 293find_miiphy (struct net_device *dev)
294{
295 int i, phy_found = 0;
296 struct netdev_private *np;
297 long ioaddr;
298 np = netdev_priv(dev);
299 ioaddr = dev->base_addr;
300 np->phy_addr = 1;
301
302 for (i = 31; i >= 0; i--) {
303 int mii_status = mii_read (dev, i, 1);
304 if (mii_status != 0xffff && mii_status != 0x0000) {
305 np->phy_addr = i;
306 phy_found++;
307 }
308 }
309 if (!phy_found) {
310 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
311 return -ENODEV;
312 }
313 return 0;
314}
315
ddfce6bb 316static int
1da177e4
LT		 317parse_eeprom (struct net_device *dev)
318{
319 int i, j;
320 long ioaddr = dev->base_addr;
321 u8 sromdata[256];
322 u8 *psib;
323 u32 crc;
324 PSROM_t psrom = (PSROM_t) sromdata;
325 struct netdev_private *np = netdev_priv(dev);
326
327 int cid, next;
328
329#ifdef MEM_MAPPING
330 ioaddr = pci_resource_start (np->pdev, 0);
331#endif
332 /* Read eeprom */
333 for (i = 0; i < 128; i++) {
78ce8d3d 334 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
1da177e4
LT		 335 }
336#ifdef MEM_MAPPING
337 ioaddr = dev->base_addr;
6aa20a22 338#endif
df950828
K		 339 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
340 /* Check CRC */
341 crc = ~ether_crc_le (256 - 4, sromdata);
342 if (psrom->crc != crc) {
343 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
344 dev->name);
345 return -1;
346 }
1da177e4
LT		 347 }
348
349 /* Set MAC address */
350 for (i = 0; i < 6; i++)
351 dev->dev_addr[i] = psrom->mac_addr[i];
352
df950828
K		 353 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
354 return 0;
355 }
356
47bdd718 357 /* Parse Software Information Block */
1da177e4
LT		 358 i = 0x30;
359 psib = (u8 *) sromdata;
360 do {
361 cid = psib[i++];
362 next = psib[i++];
363 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
364 printk (KERN_ERR "Cell data error\n");
365 return -1;
366 }
367 switch (cid) {
368 case 0: /* Format version */
369 break;
370 case 1: /* End of cell */
371 return 0;
372 case 2: /* Duplex Polarity */
373 np->duplex_polarity = psib[i];
374 writeb (readb (ioaddr + PhyCtrl) | psib[i],
375 ioaddr + PhyCtrl);
376 break;
377 case 3: /* Wake Polarity */
378 np->wake_polarity = psib[i];
379 break;
380 case 9: /* Adapter description */
381 j = (next - i > 255) ? 255 : next - i;
382 memcpy (np->name, &(psib[i]), j);
383 break;
384 case 4:
385 case 5:
386 case 6:
387 case 7:
388 case 8: /* Reversed */
389 break;
390 default: /* Unknown cell */
391 return -1;
392 }
393 i = next;
394 } while (1);
395
396 return 0;
397}
398
399static int
400rio_open (struct net_device *dev)
401{
402 struct netdev_private *np = netdev_priv(dev);
403 long ioaddr = dev->base_addr;
404 int i;
405 u16 macctrl;
6aa20a22 406
1fb9df5d 407 i = request_irq (dev->irq, &rio_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 408 if (i)
409 return i;
6aa20a22 410
1da177e4
LT		 411 /* Reset all logic functions */
412 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
413 ioaddr + ASICCtrl + 2);
414 mdelay(10);
6aa20a22 415
1da177e4
LT		 416 /* DebugCtrl bit 4, 5, 9 must set */
417 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
418
419 /* Jumbo frame */
420 if (np->jumbo != 0)
421 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
422
423 alloc_list (dev);
424
425 /* Get station address */
426 for (i = 0; i < 6; i++)
427 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
428
429 set_multicast (dev);
430 if (np->coalesce) {
431 writel (np->rx_coalesce | np->rx_timeout << 16,
432 ioaddr + RxDMAIntCtrl);
433 }
434 /* Set RIO to poll every N*320nsec. */
435 writeb (0x20, ioaddr + RxDMAPollPeriod);
436 writeb (0xff, ioaddr + TxDMAPollPeriod);
437 writeb (0x30, ioaddr + RxDMABurstThresh);
438 writeb (0x30, ioaddr + RxDMAUrgentThresh);
439 writel (0x0007ffff, ioaddr + RmonStatMask);
440 /* clear statistics */
441 clear_stats (dev);
442
443 /* VLAN supported */
444 if (np->vlan) {
445 /* priority field in RxDMAIntCtrl */
6aa20a22 446 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
1da177e4
LT		 447 ioaddr + RxDMAIntCtrl);
448 /* VLANId */
449 writew (np->vlan, ioaddr + VLANId);
450 /* Length/Type should be 0x8100 */
451 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
452 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
453 VLAN information tagged by TFC' VID, CFI fields. */
454 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
455 ioaddr + MACCtrl);
456 }
457
458 init_timer (&np->timer);
459 np->timer.expires = jiffies + 1*HZ;
460 np->timer.data = (unsigned long) dev;
461 np->timer.function = &rio_timer;
462 add_timer (&np->timer);
463
464 /* Start Tx/Rx */
6aa20a22 465 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
1da177e4 466 ioaddr + MACCtrl);
6aa20a22 467
1da177e4
LT		 468 macctrl = 0;
469 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
470 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
471 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
472 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
473 writew(macctrl, ioaddr + MACCtrl);
474
475 netif_start_queue (dev);
6aa20a22 476
1da177e4
LT		 477 /* Enable default interrupts */
478 EnableInt ();
479 return 0;
480}
481
6aa20a22 482static void
1da177e4
LT		 483rio_timer (unsigned long data)
484{
485 struct net_device *dev = (struct net_device *)data;
486 struct netdev_private *np = netdev_priv(dev);
487 unsigned int entry;
488 int next_tick = 1*HZ;
489 unsigned long flags;
490
491 spin_lock_irqsave(&np->rx_lock, flags);
492 /* Recover rx ring exhausted error */
493 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
494 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
495 /* Re-allocate skbuffs to fill the descriptor ring */
496 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
497 struct sk_buff *skb;
498 entry = np->old_rx % RX_RING_SIZE;
499 /* Dropped packets don't need to re-allocate */
500 if (np->rx_skbuff[entry] == NULL) {
47f98c7d 501 skb = netdev_alloc_skb (dev, np->rx_buf_sz);
1da177e4
LT		 502 if (skb == NULL) {
503 np->rx_ring[entry].fraginfo = 0;
504 printk (KERN_INFO
505 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
506 dev->name, entry);
507 break;
508 }
509 np->rx_skbuff[entry] = skb;
1da177e4
LT		 510 /* 16 byte align the IP header */
511 skb_reserve (skb, 2);
512 np->rx_ring[entry].fraginfo =
513 cpu_to_le64 (pci_map_single
689be439 514 (np->pdev, skb->data, np->rx_buf_sz,
1da177e4
LT		 515 PCI_DMA_FROMDEVICE));
516 }
517 np->rx_ring[entry].fraginfo |=
78ce8d3d 518 cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 519 np->rx_ring[entry].status = 0;
520 } /* end for */
521 } /* end if */
522 spin_unlock_irqrestore (&np->rx_lock, flags);
523 np->timer.expires = jiffies + next_tick;
524 add_timer(&np->timer);
525}
6aa20a22 526
1da177e4
LT		 527static void
528rio_tx_timeout (struct net_device *dev)
529{
530 long ioaddr = dev->base_addr;
531
532 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
533 dev->name, readl (ioaddr + TxStatus));
534 rio_free_tx(dev, 0);
535 dev->if_port = 0;
536 dev->trans_start = jiffies;
537}
538
539 /* allocate and initialize Tx and Rx descriptors */
540static void
541alloc_list (struct net_device *dev)
542{
543 struct netdev_private *np = netdev_priv(dev);
544 int i;
545
546 np->cur_rx = np->cur_tx = 0;
547 np->old_rx = np->old_tx = 0;
548 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
549
550 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
551 for (i = 0; i < TX_RING_SIZE; i++) {
552 np->tx_skbuff[i] = NULL;
553 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
554 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
555 ((i+1)%TX_RING_SIZE) *
556 sizeof (struct netdev_desc));
557 }
558
559 /* Initialize Rx descriptors */
560 for (i = 0; i < RX_RING_SIZE; i++) {
561 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
562 ((i + 1) % RX_RING_SIZE) *
563 sizeof (struct netdev_desc));
564 np->rx_ring[i].status = 0;
565 np->rx_ring[i].fraginfo = 0;
566 np->rx_skbuff[i] = NULL;
567 }
568
569 /* Allocate the rx buffers */
570 for (i = 0; i < RX_RING_SIZE; i++) {
571 /* Allocated fixed size of skbuff */
47f98c7d 572 struct sk_buff *skb = netdev_alloc_skb (dev, np->rx_buf_sz);
1da177e4
LT		 573 np->rx_skbuff[i] = skb;
574 if (skb == NULL) {
575 printk (KERN_ERR
576 "%s: alloc_list: allocate Rx buffer error! ",
577 dev->name);
578 break;
579 }
1da177e4
LT		 580 skb_reserve (skb, 2); /* 16 byte align the IP header. */
581 /* Rubicon now supports 40 bits of addressing space. */
582 np->rx_ring[i].fraginfo =
583 cpu_to_le64 ( pci_map_single (
689be439 584 np->pdev, skb->data, np->rx_buf_sz,
1da177e4 585 PCI_DMA_FROMDEVICE));
78ce8d3d 586 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 587 }
588
589 /* Set RFDListPtr */
78ce8d3d 590 writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
1da177e4
LT		 591 writel (0, dev->base_addr + RFDListPtr1);
592
593 return;
594}
595
596static int
597start_xmit (struct sk_buff *skb, struct net_device *dev)
598{
599 struct netdev_private *np = netdev_priv(dev);
600 struct netdev_desc *txdesc;
601 unsigned entry;
602 u32 ioaddr;
603 u64 tfc_vlan_tag = 0;
604
605 if (np->link_status == 0) { /* Link Down */
606 dev_kfree_skb(skb);
607 return 0;
608 }
609 ioaddr = dev->base_addr;
610 entry = np->cur_tx % TX_RING_SIZE;
611 np->tx_skbuff[entry] = skb;
612 txdesc = &np->tx_ring[entry];
613
614#if 0
84fa7933 615 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 616 txdesc->status |=
617 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
618 IPChecksumEnable);
619 }
620#endif
621 if (np->vlan) {
78ce8d3d
AV		 622 tfc_vlan_tag = VLANTagInsert |
623 ((u64)np->vlan << 32) |
624 ((u64)skb->priority << 45);
1da177e4
LT		 625 }
626 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
627 skb->len,
628 PCI_DMA_TODEVICE));
78ce8d3d 629 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
1da177e4
LT		 630
631 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
632 * Work around: Always use 1 descriptor in 10Mbps mode */
633 if (entry % np->tx_coalesce == 0 || np->speed == 10)
634 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
6aa20a22 635 WordAlignDisable |
1da177e4
LT		 636 TxDMAIndicate |
637 (1 << FragCountShift));
638 else
639 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
6aa20a22 640 WordAlignDisable |
1da177e4
LT		 641 (1 << FragCountShift));
642
643 /* TxDMAPollNow */
644 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
645 /* Schedule ISR */
646 writel(10000, ioaddr + CountDown);
647 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
648 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
649 < TX_QUEUE_LEN - 1 && np->speed != 10) {
650 /* do nothing */
651 } else if (!netif_queue_stopped(dev)) {
652 netif_stop_queue (dev);
653 }
654
655 /* The first TFDListPtr */
656 if (readl (dev->base_addr + TFDListPtr0) == 0) {
657 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
658 dev->base_addr + TFDListPtr0);
659 writel (0, dev->base_addr + TFDListPtr1);
660 }
6aa20a22 661
1da177e4
LT		 662 /* NETDEV WATCHDOG timer */
663 dev->trans_start = jiffies;
664 return 0;
665}
666
667static irqreturn_t
7d12e780 668rio_interrupt (int irq, void *dev_instance)
1da177e4
LT		 669{
670 struct net_device *dev = dev_instance;
671 struct netdev_private *np;
672 unsigned int_status;
673 long ioaddr;
674 int cnt = max_intrloop;
675 int handled = 0;
676
677 ioaddr = dev->base_addr;
678 np = netdev_priv(dev);
679 while (1) {
6aa20a22 680 int_status = readw (ioaddr + IntStatus);
1da177e4
LT		 681 writew (int_status, ioaddr + IntStatus);
682 int_status &= DEFAULT_INTR;
683 if (int_status == 0 || --cnt < 0)
684 break;
685 handled = 1;
686 /* Processing received packets */
687 if (int_status & RxDMAComplete)
688 receive_packet (dev);
689 /* TxDMAComplete interrupt */
690 if ((int_status & (TxDMAComplete|IntRequested))) {
691 int tx_status;
692 tx_status = readl (ioaddr + TxStatus);
693 if (tx_status & 0x01)
694 tx_error (dev, tx_status);
695 /* Free used tx skbuffs */
6aa20a22 696 rio_free_tx (dev, 1);
1da177e4
LT		 697 }
698
699 /* Handle uncommon events */
700 if (int_status &
701 (HostError | LinkEvent | UpdateStats))
702 rio_error (dev, int_status);
703 }
704 if (np->cur_tx != np->old_tx)
705 writel (100, ioaddr + CountDown);
706 return IRQ_RETVAL(handled);
707}
708
78ce8d3d
AV		 709static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
710{
711 return le64_to_cpu(desc->fraginfo) & DMA_48BIT_MASK;
712}
713
6aa20a22
JG		 714static void
715rio_free_tx (struct net_device *dev, int irq)
1da177e4
LT		 716{
717 struct netdev_private *np = netdev_priv(dev);
718 int entry = np->old_tx % TX_RING_SIZE;
719 int tx_use = 0;
720 unsigned long flag = 0;
6aa20a22 721
1da177e4
LT		 722 if (irq)
723 spin_lock(&np->tx_lock);
724 else
725 spin_lock_irqsave(&np->tx_lock, flag);
6aa20a22 726
1da177e4
LT		 727 /* Free used tx skbuffs */
728 while (entry != np->cur_tx) {
729 struct sk_buff *skb;
730
78ce8d3d 731 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
1da177e4
LT		 732 break;
733 skb = np->tx_skbuff[entry];
734 pci_unmap_single (np->pdev,
78ce8d3d 735 desc_to_dma(&np->tx_ring[entry]),
1da177e4
LT		 736 skb->len, PCI_DMA_TODEVICE);
737 if (irq)
738 dev_kfree_skb_irq (skb);
739 else
740 dev_kfree_skb (skb);
741
742 np->tx_skbuff[entry] = NULL;
743 entry = (entry + 1) % TX_RING_SIZE;
744 tx_use++;
745 }
746 if (irq)
747 spin_unlock(&np->tx_lock);
748 else
749 spin_unlock_irqrestore(&np->tx_lock, flag);
750 np->old_tx = entry;
751
6aa20a22 752 /* If the ring is no longer full, clear tx_full and
1da177e4
LT		 753 call netif_wake_queue() */
754
755 if (netif_queue_stopped(dev) &&
6aa20a22 756 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
1da177e4
LT		 757 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
758 netif_wake_queue (dev);
759 }
760}
761
762static void
763tx_error (struct net_device *dev, int tx_status)
764{
765 struct netdev_private *np;
766 long ioaddr = dev->base_addr;
767 int frame_id;
768 int i;
769
770 np = netdev_priv(dev);
771
772 frame_id = (tx_status & 0xffff0000);
773 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
774 dev->name, tx_status, frame_id);
775 np->stats.tx_errors++;
776 /* Ttransmit Underrun */
777 if (tx_status & 0x10) {
778 np->stats.tx_fifo_errors++;
779 writew (readw (ioaddr + TxStartThresh) + 0x10,
780 ioaddr + TxStartThresh);
781 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
782 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
783 ioaddr + ASICCtrl + 2);
784 /* Wait for ResetBusy bit clear */
785 for (i = 50; i > 0; i--) {
786 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
787 break;
788 mdelay (1);
789 }
790 rio_free_tx (dev, 1);
791 /* Reset TFDListPtr */
792 writel (np->tx_ring_dma +
793 np->old_tx * sizeof (struct netdev_desc),
794 dev->base_addr + TFDListPtr0);
795 writel (0, dev->base_addr + TFDListPtr1);
796
797 /* Let TxStartThresh stay default value */
798 }
799 /* Late Collision */
800 if (tx_status & 0x04) {
801 np->stats.tx_fifo_errors++;
802 /* TxReset and clear FIFO */
803 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
804 /* Wait reset done */
805 for (i = 50; i > 0; i--) {
806 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
807 break;
808 mdelay (1);
809 }
810 /* Let TxStartThresh stay default value */
811 }
812 /* Maximum Collisions */
6aa20a22
JG		 813#ifdef ETHER_STATS
814 if (tx_status & 0x08)
1da177e4
LT		 815 np->stats.collisions16++;
816#else
6aa20a22 817 if (tx_status & 0x08)
1da177e4
LT		 818 np->stats.collisions++;
819#endif
820 /* Restart the Tx */
821 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
822}
823
824static int
825receive_packet (struct net_device *dev)
826{
827 struct netdev_private *np = netdev_priv(dev);
828 int entry = np->cur_rx % RX_RING_SIZE;
829 int cnt = 30;
830
831 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
832 while (1) {
833 struct netdev_desc *desc = &np->rx_ring[entry];
834 int pkt_len;
835 u64 frame_status;
836
78ce8d3d
AV		 837 if (!(desc->status & cpu_to_le64(RFDDone)) ||
838 !(desc->status & cpu_to_le64(FrameStart)) ||
839 !(desc->status & cpu_to_le64(FrameEnd)))
1da177e4
LT		 840 break;
841
842 /* Chip omits the CRC. */
78ce8d3d
AV		 843 frame_status = le64_to_cpu(desc->status);
844 pkt_len = frame_status & 0xffff;
1da177e4
LT		 845 if (--cnt < 0)
846 break;
847 /* Update rx error statistics, drop packet. */
848 if (frame_status & RFS_Errors) {
849 np->stats.rx_errors++;
850 if (frame_status & (RxRuntFrame | RxLengthError))
851 np->stats.rx_length_errors++;
852 if (frame_status & RxFCSError)
853 np->stats.rx_crc_errors++;
854 if (frame_status & RxAlignmentError && np->speed != 1000)
855 np->stats.rx_frame_errors++;
856 if (frame_status & RxFIFOOverrun)
857 np->stats.rx_fifo_errors++;
858 } else {
859 struct sk_buff *skb;
860
861 /* Small skbuffs for short packets */
862 if (pkt_len > copy_thresh) {
9ee09d9c 863 pci_unmap_single (np->pdev,
78ce8d3d 864 desc_to_dma(desc),
1da177e4
LT		 865 np->rx_buf_sz,
866 PCI_DMA_FROMDEVICE);
867 skb_put (skb = np->rx_skbuff[entry], pkt_len);
868 np->rx_skbuff[entry] = NULL;
47f98c7d 869 } else if ((skb = netdev_alloc_skb(dev, pkt_len + 2))) {
1da177e4 870 pci_dma_sync_single_for_cpu(np->pdev,
78ce8d3d 871 desc_to_dma(desc),
1da177e4
LT		 872 np->rx_buf_sz,
873 PCI_DMA_FROMDEVICE);
1da177e4
LT		 874 /* 16 byte align the IP header */
875 skb_reserve (skb, 2);
8c7b7faa 876 skb_copy_to_linear_data (skb,
689be439 877 np->rx_skbuff[entry]->data,
8c7b7faa 878 pkt_len);
1da177e4
LT		 879 skb_put (skb, pkt_len);
880 pci_dma_sync_single_for_device(np->pdev,
78ce8d3d 881 desc_to_dma(desc),
1da177e4
LT		 882 np->rx_buf_sz,
883 PCI_DMA_FROMDEVICE);
884 }
885 skb->protocol = eth_type_trans (skb, dev);
6aa20a22 886#if 0
1da177e4 887 /* Checksum done by hw, but csum value unavailable. */
44c10138 888 if (np->pdev->pci_rev_id >= 0x0c &&
1da177e4
LT		 889 !(frame_status & (TCPError | UDPError | IPError))) {
890 skb->ip_summed = CHECKSUM_UNNECESSARY;
6aa20a22 891 }
1da177e4
LT		 892#endif
893 netif_rx (skb);
894 dev->last_rx = jiffies;
895 }
896 entry = (entry + 1) % RX_RING_SIZE;
897 }
898 spin_lock(&np->rx_lock);
899 np->cur_rx = entry;
900 /* Re-allocate skbuffs to fill the descriptor ring */
901 entry = np->old_rx;
902 while (entry != np->cur_rx) {
903 struct sk_buff *skb;
904 /* Dropped packets don't need to re-allocate */
905 if (np->rx_skbuff[entry] == NULL) {
47f98c7d 906 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1da177e4
LT		 907 if (skb == NULL) {
908 np->rx_ring[entry].fraginfo = 0;
909 printk (KERN_INFO
910 "%s: receive_packet: "
911 "Unable to re-allocate Rx skbuff.#%d\n",
912 dev->name, entry);
913 break;
914 }
915 np->rx_skbuff[entry] = skb;
1da177e4
LT		 916 /* 16 byte align the IP header */
917 skb_reserve (skb, 2);
918 np->rx_ring[entry].fraginfo =
919 cpu_to_le64 (pci_map_single
689be439 920 (np->pdev, skb->data, np->rx_buf_sz,
1da177e4
LT		 921 PCI_DMA_FROMDEVICE));
922 }
923 np->rx_ring[entry].fraginfo |=
78ce8d3d 924 cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 925 np->rx_ring[entry].status = 0;
926 entry = (entry + 1) % RX_RING_SIZE;
927 }
928 np->old_rx = entry;
929 spin_unlock(&np->rx_lock);
930 return 0;
931}
932
933static void
934rio_error (struct net_device *dev, int int_status)
935{
936 long ioaddr = dev->base_addr;
937 struct netdev_private *np = netdev_priv(dev);
938 u16 macctrl;
939
940 /* Link change event */
941 if (int_status & LinkEvent) {
942 if (mii_wait_link (dev, 10) == 0) {
943 printk (KERN_INFO "%s: Link up\n", dev->name);
944 if (np->phy_media)
945 mii_get_media_pcs (dev);
946 else
947 mii_get_media (dev);
948 if (np->speed == 1000)
949 np->tx_coalesce = tx_coalesce;
6aa20a22 950 else
1da177e4
LT		 951 np->tx_coalesce = 1;
952 macctrl = 0;
953 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
954 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
6aa20a22 955 macctrl |= (np->tx_flow) ?
1da177e4 956 TxFlowControlEnable : 0;
6aa20a22 957 macctrl |= (np->rx_flow) ?
1da177e4
LT		 958 RxFlowControlEnable : 0;
959 writew(macctrl, ioaddr + MACCtrl);
960 np->link_status = 1;
961 netif_carrier_on(dev);
962 } else {
963 printk (KERN_INFO "%s: Link off\n", dev->name);
964 np->link_status = 0;
965 netif_carrier_off(dev);
966 }
967 }
968
969 /* UpdateStats statistics registers */
970 if (int_status & UpdateStats) {
971 get_stats (dev);
972 }
973
6aa20a22 974 /* PCI Error, a catastronphic error related to the bus interface
1da177e4
LT		 975 occurs, set GlobalReset and HostReset to reset. */
976 if (int_status & HostError) {
977 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
978 dev->name, int_status);
979 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
980 mdelay (500);
981 }
982}
983
984static struct net_device_stats *
985get_stats (struct net_device *dev)
986{
987 long ioaddr = dev->base_addr;
988 struct netdev_private *np = netdev_priv(dev);
989#ifdef MEM_MAPPING
990 int i;
991#endif
992 unsigned int stat_reg;
993
994 /* All statistics registers need to be acknowledged,
995 else statistic overflow could cause problems */
6aa20a22 996
1da177e4
LT		 997 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
998 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
999 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1000 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1001
1002 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
6aa20a22
JG		 1003 np->stats.collisions += readl (ioaddr + SingleColFrames)
1004 + readl (ioaddr + MultiColFrames);
1005
1da177e4
LT		 1006 /* detailed tx errors */
1007 stat_reg = readw (ioaddr + FramesAbortXSColls);
1008 np->stats.tx_aborted_errors += stat_reg;
1009 np->stats.tx_errors += stat_reg;
1010
1011 stat_reg = readw (ioaddr + CarrierSenseErrors);
1012 np->stats.tx_carrier_errors += stat_reg;
1013 np->stats.tx_errors += stat_reg;
1014
1015 /* Clear all other statistic register. */
1016 readl (ioaddr + McstOctetXmtOk);
1017 readw (ioaddr + BcstFramesXmtdOk);
1018 readl (ioaddr + McstFramesXmtdOk);
1019 readw (ioaddr + BcstFramesRcvdOk);
1020 readw (ioaddr + MacControlFramesRcvd);
1021 readw (ioaddr + FrameTooLongErrors);
1022 readw (ioaddr + InRangeLengthErrors);
1023 readw (ioaddr + FramesCheckSeqErrors);
1024 readw (ioaddr + FramesLostRxErrors);
1025 readl (ioaddr + McstOctetXmtOk);
1026 readl (ioaddr + BcstOctetXmtOk);
1027 readl (ioaddr + McstFramesXmtdOk);
1028 readl (ioaddr + FramesWDeferredXmt);
1029 readl (ioaddr + LateCollisions);
1030 readw (ioaddr + BcstFramesXmtdOk);
1031 readw (ioaddr + MacControlFramesXmtd);
1032 readw (ioaddr + FramesWEXDeferal);
1033
1034#ifdef MEM_MAPPING
1035 for (i = 0x100; i <= 0x150; i += 4)
1036 readl (ioaddr + i);
1037#endif
1038 readw (ioaddr + TxJumboFrames);
1039 readw (ioaddr + RxJumboFrames);
1040 readw (ioaddr + TCPCheckSumErrors);
1041 readw (ioaddr + UDPCheckSumErrors);
1042 readw (ioaddr + IPCheckSumErrors);
1043 return &np->stats;
1044}
1045
1046static int
1047clear_stats (struct net_device *dev)
1048{
1049 long ioaddr = dev->base_addr;
1050#ifdef MEM_MAPPING
1051 int i;
6aa20a22 1052#endif
1da177e4
LT		 1053
1054 /* All statistics registers need to be acknowledged,
1055 else statistic overflow could cause problems */
1056 readl (ioaddr + FramesRcvOk);
1057 readl (ioaddr + FramesXmtOk);
1058 readl (ioaddr + OctetRcvOk);
1059 readl (ioaddr + OctetXmtOk);
1060
1061 readl (ioaddr + McstFramesRcvdOk);
1062 readl (ioaddr + SingleColFrames);
1063 readl (ioaddr + MultiColFrames);
1064 readl (ioaddr + LateCollisions);
6aa20a22 1065 /* detailed rx errors */
1da177e4
LT		 1066 readw (ioaddr + FrameTooLongErrors);
1067 readw (ioaddr + InRangeLengthErrors);
1068 readw (ioaddr + FramesCheckSeqErrors);
1069 readw (ioaddr + FramesLostRxErrors);
1070
1071 /* detailed tx errors */
1072 readw (ioaddr + FramesAbortXSColls);
1073 readw (ioaddr + CarrierSenseErrors);
1074
1075 /* Clear all other statistic register. */
1076 readl (ioaddr + McstOctetXmtOk);
1077 readw (ioaddr + BcstFramesXmtdOk);
1078 readl (ioaddr + McstFramesXmtdOk);
1079 readw (ioaddr + BcstFramesRcvdOk);
1080 readw (ioaddr + MacControlFramesRcvd);
1081 readl (ioaddr + McstOctetXmtOk);
1082 readl (ioaddr + BcstOctetXmtOk);
1083 readl (ioaddr + McstFramesXmtdOk);
1084 readl (ioaddr + FramesWDeferredXmt);
1085 readw (ioaddr + BcstFramesXmtdOk);
1086 readw (ioaddr + MacControlFramesXmtd);
1087 readw (ioaddr + FramesWEXDeferal);
1088#ifdef MEM_MAPPING
1089 for (i = 0x100; i <= 0x150; i += 4)
1090 readl (ioaddr + i);
6aa20a22 1091#endif
1da177e4
LT		 1092 readw (ioaddr + TxJumboFrames);
1093 readw (ioaddr + RxJumboFrames);
1094 readw (ioaddr + TCPCheckSumErrors);
1095 readw (ioaddr + UDPCheckSumErrors);
1096 readw (ioaddr + IPCheckSumErrors);
1097 return 0;
1098}
1099
1100
ddfce6bb 1101static int
1da177e4
LT		 1102change_mtu (struct net_device *dev, int new_mtu)
1103{
1104 struct netdev_private *np = netdev_priv(dev);
1105 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1106
1107 if ((new_mtu < 68) || (new_mtu > max)) {
1108 return -EINVAL;
1109 }
1110
1111 dev->mtu = new_mtu;
1112
1113 return 0;
1114}
1115
1116static void
1117set_multicast (struct net_device *dev)
1118{
1119 long ioaddr = dev->base_addr;
1120 u32 hash_table[2];
1121 u16 rx_mode = 0;
1122 struct netdev_private *np = netdev_priv(dev);
6aa20a22 1123
1da177e4
LT		 1124 hash_table[0] = hash_table[1] = 0;
1125 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
78ce8d3d 1126 hash_table[1] |= 0x02000000;
1da177e4
LT		 1127 if (dev->flags & IFF_PROMISC) {
1128 /* Receive all frames promiscuously. */
1129 rx_mode = ReceiveAllFrames;
6aa20a22 1130 } else if ((dev->flags & IFF_ALLMULTI) ||
1da177e4
LT		 1131 (dev->mc_count > multicast_filter_limit)) {
1132 /* Receive broadcast and multicast frames */
1133 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1134 } else if (dev->mc_count > 0) {
1135 int i;
1136 struct dev_mc_list *mclist;
6aa20a22 1137 /* Receive broadcast frames and multicast frames filtering
1da177e4
LT		 1138 by Hashtable */
1139 rx_mode =
1140 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
6aa20a22
JG		 1141 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1142 i++, mclist=mclist->next)
1da177e4
LT		 1143 {
1144 int bit, index = 0;
1145 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1146 /* The inverted high significant 6 bits of CRC are
1147 used as an index to hashtable */
1148 for (bit = 0; bit < 6; bit++)
1149 if (crc & (1 << (31 - bit)))
1150 index |= (1 << bit);
1151 hash_table[index / 32] |= (1 << (index % 32));
1152 }
1153 } else {
1154 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1155 }
1156 if (np->vlan) {
1157 /* ReceiveVLANMatch field in ReceiveMode */
1158 rx_mode |= ReceiveVLANMatch;
1159 }
1160
1161 writel (hash_table[0], ioaddr + HashTable0);
1162 writel (hash_table[1], ioaddr + HashTable1);
1163 writew (rx_mode, ioaddr + ReceiveMode);
1164}
1165
1166static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1167{
1168 struct netdev_private *np = netdev_priv(dev);
1169 strcpy(info->driver, "dl2k");
1170 strcpy(info->version, DRV_VERSION);
1171 strcpy(info->bus_info, pci_name(np->pdev));
6aa20a22 1172}
1da177e4
LT		 1173
1174static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1175{
1176 struct netdev_private *np = netdev_priv(dev);
1177 if (np->phy_media) {
1178 /* fiber device */
1179 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1180 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1181 cmd->port = PORT_FIBRE;
6aa20a22 1182 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 1183 } else {
1184 /* copper device */
6aa20a22 1185 cmd->supported = SUPPORTED_10baseT_Half |
1da177e4
LT		 1186 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1187 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1188 SUPPORTED_Autoneg | SUPPORTED_MII;
1189 cmd->advertising = ADVERTISED_10baseT_Half |
1190 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1191 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1192 ADVERTISED_Autoneg | ADVERTISED_MII;
1193 cmd->port = PORT_MII;
1194 cmd->transceiver = XCVR_INTERNAL;
1195 }
6aa20a22 1196 if ( np->link_status ) {
1da177e4
LT		 1197 cmd->speed = np->speed;
1198 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1199 } else {
1200 cmd->speed = -1;
1201 cmd->duplex = -1;
1202 }
1203 if ( np->an_enable)
1204 cmd->autoneg = AUTONEG_ENABLE;
1205 else
1206 cmd->autoneg = AUTONEG_DISABLE;
6aa20a22 1207
1da177e4 1208 cmd->phy_address = np->phy_addr;
6aa20a22 1209 return 0;
1da177e4
LT		 1210}
1211
1212static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1213{
1214 struct netdev_private *np = netdev_priv(dev);
1215 netif_carrier_off(dev);
1216 if (cmd->autoneg == AUTONEG_ENABLE) {
1217 if (np->an_enable)
1218 return 0;
1219 else {
1220 np->an_enable = 1;
1221 mii_set_media(dev);
6aa20a22
JG		 1222 return 0;
1223 }
1da177e4
LT		 1224 } else {
1225 np->an_enable = 0;
1226 if (np->speed == 1000) {
6aa20a22 1227 cmd->speed = SPEED_100;
1da177e4
LT		 1228 cmd->duplex = DUPLEX_FULL;
1229 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1230 }
1231 switch(cmd->speed + cmd->duplex) {
6aa20a22 1232
1da177e4
LT		 1233 case SPEED_10 + DUPLEX_HALF:
1234 np->speed = 10;
1235 np->full_duplex = 0;
1236 break;
6aa20a22 1237
1da177e4
LT		 1238 case SPEED_10 + DUPLEX_FULL:
1239 np->speed = 10;
1240 np->full_duplex = 1;
1241 break;
1242 case SPEED_100 + DUPLEX_HALF:
1243 np->speed = 100;
1244 np->full_duplex = 0;
1245 break;
1246 case SPEED_100 + DUPLEX_FULL:
1247 np->speed = 100;
1248 np->full_duplex = 1;
1249 break;
1250 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1251 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1252 default:
6aa20a22 1253 return -EINVAL;
1da177e4
LT		 1254 }
1255 mii_set_media(dev);
1256 }
1257 return 0;
1258}
1259
1260static u32 rio_get_link(struct net_device *dev)
1261{
1262 struct netdev_private *np = netdev_priv(dev);
1263 return np->link_status;
1264}
1265
7282d491 1266static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1267 .get_drvinfo = rio_get_drvinfo,
1268 .get_settings = rio_get_settings,
1269 .set_settings = rio_set_settings,
1270 .get_link = rio_get_link,
1271};
1272
1273static int
1274rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1275{
1276 int phy_addr;
1277 struct netdev_private *np = netdev_priv(dev);
1278 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
6aa20a22 1279
1da177e4
LT		 1280 struct netdev_desc *desc;
1281 int i;
1282
1283 phy_addr = np->phy_addr;
1284 switch (cmd) {
1285 case SIOCDEVPRIVATE:
1286 break;
6aa20a22 1287
1da177e4
LT		 1288 case SIOCDEVPRIVATE + 1:
1289 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1290 break;
1291 case SIOCDEVPRIVATE + 2:
1292 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1293 break;
1294 case SIOCDEVPRIVATE + 3:
1295 break;
1296 case SIOCDEVPRIVATE + 4:
1297 break;
1298 case SIOCDEVPRIVATE + 5:
1299 netif_stop_queue (dev);
1300 break;
1301 case SIOCDEVPRIVATE + 6:
1302 netif_wake_queue (dev);
1303 break;
1304 case SIOCDEVPRIVATE + 7:
1305 printk
1306 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1307 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1308 np->old_rx);
1309 break;
1310 case SIOCDEVPRIVATE + 8:
1311 printk("TX ring:\n");
1312 for (i = 0; i < TX_RING_SIZE; i++) {
1313 desc = &np->tx_ring[i];
1314 printk
1315 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1316 i,
1317 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
0ca5f319
AV		 1318 (u32)le64_to_cpu(desc->next_desc),
1319 (u32)le64_to_cpu(desc->status),
1320 (u32)(le64_to_cpu(desc->fraginfo) >> 32),
1321 (u32)le64_to_cpu(desc->fraginfo));
1da177e4
LT		 1322 printk ("\n");
1323 }
1324 printk ("\n");
1325 break;
1326
1327 default:
1328 return -EOPNOTSUPP;
1329 }
1330 return 0;
1331}
1332
1333#define EEP_READ 0x0200
1334#define EEP_BUSY 0x8000
1335/* Read the EEPROM word */
1336/* We use I/O instruction to read/write eeprom to avoid fail on some machines */
ddfce6bb 1337static int
1da177e4
LT		 1338read_eeprom (long ioaddr, int eep_addr)
1339{
1340 int i = 1000;
1341 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1342 while (i-- > 0) {
1343 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1344 return inw (ioaddr + EepromData);
1345 }
1346 }
1347 return 0;
1348}
1349
1350enum phy_ctrl_bits {
1351 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1352 MII_DUPLEX = 0x08,
1353};
1354
1355#define mii_delay() readb(ioaddr)
1356static void
1357mii_sendbit (struct net_device *dev, u32 data)
1358{
1359 long ioaddr = dev->base_addr + PhyCtrl;
1360 data = (data) ? MII_DATA1 : 0;
1361 data |= MII_WRITE;
1362 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1363 writeb (data, ioaddr);
1364 mii_delay ();
1365 writeb (data | MII_CLK, ioaddr);
1366 mii_delay ();
1367}
1368
1369static int
1370mii_getbit (struct net_device *dev)
1371{
1372 long ioaddr = dev->base_addr + PhyCtrl;
1373 u8 data;
1374
1375 data = (readb (ioaddr) & 0xf8) | MII_READ;
1376 writeb (data, ioaddr);
1377 mii_delay ();
1378 writeb (data | MII_CLK, ioaddr);
1379 mii_delay ();
1380 return ((readb (ioaddr) >> 1) & 1);
1381}
1382
1383static void
1384mii_send_bits (struct net_device *dev, u32 data, int len)
1385{
1386 int i;
1387 for (i = len - 1; i >= 0; i--) {
1388 mii_sendbit (dev, data & (1 << i));
1389 }
1390}
1391
1392static int
1393mii_read (struct net_device *dev, int phy_addr, int reg_num)
1394{
1395 u32 cmd;
1396 int i;
1397 u32 retval = 0;
1398
1399 /* Preamble */
1400 mii_send_bits (dev, 0xffffffff, 32);
1401 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1402 /* ST,OP = 0110'b for read operation */
1403 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1404 mii_send_bits (dev, cmd, 14);
1405 /* Turnaround */
1406 if (mii_getbit (dev))
1407 goto err_out;
1408 /* Read data */
1409 for (i = 0; i < 16; i++) {
1410 retval |= mii_getbit (dev);
1411 retval <<= 1;
1412 }
1413 /* End cycle */
1414 mii_getbit (dev);
1415 return (retval >> 1) & 0xffff;
1416
1417 err_out:
1418 return 0;
1419}
1420static int
1421mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1422{
1423 u32 cmd;
1424
1425 /* Preamble */
1426 mii_send_bits (dev, 0xffffffff, 32);
1427 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1428 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1429 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1430 mii_send_bits (dev, cmd, 32);
1431 /* End cycle */
1432 mii_getbit (dev);
1433 return 0;
1434}
1435static int
1436mii_wait_link (struct net_device *dev, int wait)
1437{
96d76851 1438 __u16 bmsr;
1da177e4
LT		 1439 int phy_addr;
1440 struct netdev_private *np;
1441
1442 np = netdev_priv(dev);
1443 phy_addr = np->phy_addr;
1444
1445 do {
96d76851
AV		 1446 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1447 if (bmsr & MII_BMSR_LINK_STATUS)
1da177e4
LT		 1448 return 0;
1449 mdelay (1);
1450 } while (--wait > 0);
1451 return -1;
1452}
1453static int
1454mii_get_media (struct net_device *dev)
1455{
21b645e4 1456 __u16 negotiate;
96d76851 1457 __u16 bmsr;
5b511916
AV		 1458 __u16 mscr;
1459 __u16 mssr;
1da177e4
LT		 1460 int phy_addr;
1461 struct netdev_private *np;
1462
1463 np = netdev_priv(dev);
1464 phy_addr = np->phy_addr;
1465
96d76851 1466 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1da177e4 1467 if (np->an_enable) {
96d76851 1468 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1da177e4
LT		 1469 /* Auto-Negotiation not completed */
1470 return -1;
1471 }
21b645e4 1472 negotiate = mii_read (dev, phy_addr, MII_ANAR) &
1da177e4 1473 mii_read (dev, phy_addr, MII_ANLPAR);
5b511916
AV		 1474 mscr = mii_read (dev, phy_addr, MII_MSCR);
1475 mssr = mii_read (dev, phy_addr, MII_MSSR);
1476 if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
1da177e4
LT		 1477 np->speed = 1000;
1478 np->full_duplex = 1;
1479 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
5b511916 1480 } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
1da177e4
LT		 1481 np->speed = 1000;
1482 np->full_duplex = 0;
1483 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
21b645e4 1484 } else if (negotiate & MII_ANAR_100BX_FD) {
1da177e4
LT		 1485 np->speed = 100;
1486 np->full_duplex = 1;
1487 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
21b645e4 1488 } else if (negotiate & MII_ANAR_100BX_HD) {
1da177e4
LT		 1489 np->speed = 100;
1490 np->full_duplex = 0;
1491 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
21b645e4 1492 } else if (negotiate & MII_ANAR_10BT_FD) {
1da177e4
LT		 1493 np->speed = 10;
1494 np->full_duplex = 1;
1495 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
21b645e4 1496 } else if (negotiate & MII_ANAR_10BT_HD) {
1da177e4
LT		 1497 np->speed = 10;
1498 np->full_duplex = 0;
1499 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1500 }
21b645e4 1501 if (negotiate & MII_ANAR_PAUSE) {
1da177e4
LT		 1502 np->tx_flow &= 1;
1503 np->rx_flow &= 1;
21b645e4 1504 } else if (negotiate & MII_ANAR_ASYMMETRIC) {
1da177e4
LT		 1505 np->tx_flow = 0;
1506 np->rx_flow &= 1;
1507 }
1508 /* else tx_flow, rx_flow = user select */
1509 } else {
d50956af
AV		 1510 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1511 switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
1512 case MII_BMCR_SPEED_1000:
1513 printk (KERN_INFO "Operating at 1000 Mbps, ");
1514 break;
1515 case MII_BMCR_SPEED_100:
1da177e4 1516 printk (KERN_INFO "Operating at 100 Mbps, ");
d50956af
AV		 1517 break;
1518 case 0:
1da177e4 1519 printk (KERN_INFO "Operating at 10 Mbps, ");
1da177e4 1520 }
d50956af 1521 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1da177e4
LT		 1522 printk ("Full duplex\n");
1523 } else {
1524 printk ("Half duplex\n");
1525 }
1526 }
6aa20a22 1527 if (np->tx_flow)
1da177e4 1528 printk(KERN_INFO "Enable Tx Flow Control\n");
6aa20a22 1529 else
1da177e4
LT		 1530 printk(KERN_INFO "Disable Tx Flow Control\n");
1531 if (np->rx_flow)
1532 printk(KERN_INFO "Enable Rx Flow Control\n");
1533 else
1534 printk(KERN_INFO "Disable Rx Flow Control\n");
1535
1536 return 0;
1537}
1538
1539static int
1540mii_set_media (struct net_device *dev)
1541{
5b511916 1542 __u16 pscr;
d50956af 1543 __u16 bmcr;
96d76851 1544 __u16 bmsr;
21b645e4 1545 __u16 anar;
1da177e4
LT		 1546 int phy_addr;
1547 struct netdev_private *np;
1548 np = netdev_priv(dev);
1549 phy_addr = np->phy_addr;
1550
1551 /* Does user set speed? */
1552 if (np->an_enable) {
1553 /* Advertise capabilities */
96d76851 1554 bmsr = mii_read (dev, phy_addr, MII_BMSR);
21b645e4
AV		 1555 anar = mii_read (dev, phy_addr, MII_ANAR) &
1556 ~MII_ANAR_100BX_FD &
1557 ~MII_ANAR_100BX_HD &
1558 ~MII_ANAR_100BT4 &
1559 ~MII_ANAR_10BT_FD &
1560 ~MII_ANAR_10BT_HD;
96d76851 1561 if (bmsr & MII_BMSR_100BX_FD)
21b645e4 1562 anar |= MII_ANAR_100BX_FD;
96d76851 1563 if (bmsr & MII_BMSR_100BX_HD)
21b645e4 1564 anar |= MII_ANAR_100BX_HD;
96d76851 1565 if (bmsr & MII_BMSR_100BT4)
21b645e4 1566 anar |= MII_ANAR_100BT4;
96d76851 1567 if (bmsr & MII_BMSR_10BT_FD)
21b645e4 1568 anar |= MII_ANAR_10BT_FD;
96d76851 1569 if (bmsr & MII_BMSR_10BT_HD)
21b645e4
AV		 1570 anar |= MII_ANAR_10BT_HD;
1571 anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
1572 mii_write (dev, phy_addr, MII_ANAR, anar);
1da177e4
LT		 1573
1574 /* Enable Auto crossover */
5b511916
AV		 1575 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1576 pscr |= 3 << 5; /* 11'b */
1577 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
6aa20a22 1578
1da177e4
LT		 1579 /* Soft reset PHY */
1580 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
d50956af
AV		 1581 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
1582 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1583 mdelay(1);
1584 } else {
1585 /* Force speed setting */
1586 /* 1) Disable Auto crossover */
5b511916
AV		 1587 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1588 pscr &= ~(3 << 5);
1589 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1da177e4
LT		 1590
1591 /* 2) PHY Reset */
d50956af
AV		 1592 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1593 bmcr |= MII_BMCR_RESET;
1594 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1595
1596 /* 3) Power Down */
d50956af
AV		 1597 bmcr = 0x1940; /* must be 0x1940 */
1598 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1599 mdelay (100); /* wait a certain time */
1600
1601 /* 4) Advertise nothing */
1602 mii_write (dev, phy_addr, MII_ANAR, 0);
1603
1604 /* 5) Set media and Power Up */
d50956af 1605 bmcr = MII_BMCR_POWER_DOWN;
1da177e4 1606 if (np->speed == 100) {
d50956af 1607 bmcr |= MII_BMCR_SPEED_100;
1da177e4
LT		 1608 printk (KERN_INFO "Manual 100 Mbps, ");
1609 } else if (np->speed == 10) {
1da177e4
LT		 1610 printk (KERN_INFO "Manual 10 Mbps, ");
1611 }
1612 if (np->full_duplex) {
d50956af 1613 bmcr |= MII_BMCR_DUPLEX_MODE;
1da177e4
LT		 1614 printk ("Full duplex\n");
1615 } else {
1da177e4
LT		 1616 printk ("Half duplex\n");
1617 }
1618#if 0
1619 /* Set 1000BaseT Master/Slave setting */
5b511916
AV		 1620 mscr = mii_read (dev, phy_addr, MII_MSCR);
1621 mscr |= MII_MSCR_CFG_ENABLE;
1622 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1da177e4 1623#endif
d50956af 1624 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1625 mdelay(10);
1626 }
1627 return 0;
1628}
1629
1630static int
1631mii_get_media_pcs (struct net_device *dev)
1632{
21b645e4 1633 __u16 negotiate;
96d76851 1634 __u16 bmsr;
1da177e4
LT		 1635 int phy_addr;
1636 struct netdev_private *np;
1637
1638 np = netdev_priv(dev);
1639 phy_addr = np->phy_addr;
1640
96d76851 1641 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1da177e4 1642 if (np->an_enable) {
96d76851 1643 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1da177e4
LT		 1644 /* Auto-Negotiation not completed */
1645 return -1;
1646 }
21b645e4 1647 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1da177e4
LT		 1648 mii_read (dev, phy_addr, PCS_ANLPAR);
1649 np->speed = 1000;
21b645e4 1650 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1da177e4
LT		 1651 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1652 np->full_duplex = 1;
1653 } else {
1654 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1655 np->full_duplex = 0;
1656 }
21b645e4 1657 if (negotiate & PCS_ANAR_PAUSE) {
1da177e4
LT		 1658 np->tx_flow &= 1;
1659 np->rx_flow &= 1;
21b645e4 1660 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1da177e4
LT		 1661 np->tx_flow = 0;
1662 np->rx_flow &= 1;
1663 }
1664 /* else tx_flow, rx_flow = user select */
1665 } else {
d50956af 1666 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1da177e4 1667 printk (KERN_INFO "Operating at 1000 Mbps, ");
d50956af 1668 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1da177e4
LT		 1669 printk ("Full duplex\n");
1670 } else {
1671 printk ("Half duplex\n");
1672 }
1673 }
6aa20a22 1674 if (np->tx_flow)
1da177e4 1675 printk(KERN_INFO "Enable Tx Flow Control\n");
6aa20a22 1676 else
1da177e4
LT		 1677 printk(KERN_INFO "Disable Tx Flow Control\n");
1678 if (np->rx_flow)
1679 printk(KERN_INFO "Enable Rx Flow Control\n");
1680 else
1681 printk(KERN_INFO "Disable Rx Flow Control\n");
1682
1683 return 0;
1684}
1685
1686static int
1687mii_set_media_pcs (struct net_device *dev)
1688{
d50956af 1689 __u16 bmcr;
5b511916 1690 __u16 esr;
21b645e4 1691 __u16 anar;
1da177e4
LT		 1692 int phy_addr;
1693 struct netdev_private *np;
1694 np = netdev_priv(dev);
1695 phy_addr = np->phy_addr;
1696
1697 /* Auto-Negotiation? */
1698 if (np->an_enable) {
1699 /* Advertise capabilities */
5b511916 1700 esr = mii_read (dev, phy_addr, PCS_ESR);
21b645e4
AV		 1701 anar = mii_read (dev, phy_addr, MII_ANAR) &
1702 ~PCS_ANAR_HALF_DUPLEX &
1703 ~PCS_ANAR_FULL_DUPLEX;
5b511916 1704 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
21b645e4 1705 anar |= PCS_ANAR_HALF_DUPLEX;
5b511916 1706 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
21b645e4
AV		 1707 anar |= PCS_ANAR_FULL_DUPLEX;
1708 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1709 mii_write (dev, phy_addr, MII_ANAR, anar);
1da177e4
LT		 1710
1711 /* Soft reset PHY */
1712 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
d50956af
AV		 1713 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
1714 MII_BMCR_RESET;
1715 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1716 mdelay(1);
1717 } else {
1718 /* Force speed setting */
1719 /* PHY Reset */
d50956af
AV		 1720 bmcr = MII_BMCR_RESET;
1721 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4 1722 mdelay(10);
1da177e4 1723 if (np->full_duplex) {
d50956af 1724 bmcr = MII_BMCR_DUPLEX_MODE;
1da177e4
LT		 1725 printk (KERN_INFO "Manual full duplex\n");
1726 } else {
d50956af 1727 bmcr = 0;
1da177e4
LT		 1728 printk (KERN_INFO "Manual half duplex\n");
1729 }
d50956af 1730 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1731 mdelay(10);
1732
1733 /* Advertise nothing */
1734 mii_write (dev, phy_addr, MII_ANAR, 0);
1735 }
1736 return 0;
1737}
1738
1739
1740static int
1741rio_close (struct net_device *dev)
1742{
1743 long ioaddr = dev->base_addr;
1744 struct netdev_private *np = netdev_priv(dev);
1745 struct sk_buff *skb;
1746 int i;
1747
1748 netif_stop_queue (dev);
1749
1750 /* Disable interrupts */
1751 writew (0, ioaddr + IntEnable);
1752
1753 /* Stop Tx and Rx logics */
1754 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
be0976be 1755
1da177e4
LT		 1756 free_irq (dev->irq, dev);
1757 del_timer_sync (&np->timer);
6aa20a22 1758
1da177e4
LT		 1759 /* Free all the skbuffs in the queue. */
1760 for (i = 0; i < RX_RING_SIZE; i++) {
1761 np->rx_ring[i].status = 0;
1762 np->rx_ring[i].fraginfo = 0;
1763 skb = np->rx_skbuff[i];
1764 if (skb) {
6aa20a22 1765 pci_unmap_single(np->pdev,
78ce8d3d 1766 desc_to_dma(&np->rx_ring[i]),
9ee09d9c 1767 skb->len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1768 dev_kfree_skb (skb);
1769 np->rx_skbuff[i] = NULL;
1770 }
1771 }
1772 for (i = 0; i < TX_RING_SIZE; i++) {
1773 skb = np->tx_skbuff[i];
1774 if (skb) {
6aa20a22 1775 pci_unmap_single(np->pdev,
78ce8d3d 1776 desc_to_dma(&np->tx_ring[i]),
9ee09d9c 1777 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT		 1778 dev_kfree_skb (skb);
1779 np->tx_skbuff[i] = NULL;
1780 }
1781 }
1782
1783 return 0;
1784}
1785
1786static void __devexit
1787rio_remove1 (struct pci_dev *pdev)
1788{
1789 struct net_device *dev = pci_get_drvdata (pdev);
1790
1791 if (dev) {
1792 struct netdev_private *np = netdev_priv(dev);
1793
1794 unregister_netdev (dev);
1795 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1796 np->rx_ring_dma);
1797 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1798 np->tx_ring_dma);
1799#ifdef MEM_MAPPING
1800 iounmap ((char *) (dev->base_addr));
1801#endif
1802 free_netdev (dev);
1803 pci_release_regions (pdev);
1804 pci_disable_device (pdev);
1805 }
1806 pci_set_drvdata (pdev, NULL);
1807}
1808
1809static struct pci_driver rio_driver = {
1810 .name = "dl2k",
1811 .id_table = rio_pci_tbl,
1812 .probe = rio_probe1,
1813 .remove = __devexit_p(rio_remove1),
1814};
1815
1816static int __init
1817rio_init (void)
1818{
29917620 1819 return pci_register_driver(&rio_driver);
1da177e4
LT		 1820}
1821
1822static void __exit
1823rio_exit (void)
1824{
1825 pci_unregister_driver (&rio_driver);
1826}
1827
1828module_init (rio_init);
1829module_exit (rio_exit);
1830
1831/*
6aa20a22
JG		 1832
1833Compile command:
1834
1da177e4
LT		 1835gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1836
1837Read Documentation/networking/dl2k.txt for details.
1838
1839*/
1840
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