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1da177e4
LT		 1/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2/*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11*/
1da177e4 12
df950828
K		 13#define DRV_NAME "DL2000/TC902x-based linux driver"
14#define DRV_VERSION "v1.19"
15#define DRV_RELDATE "2007/08/12"
1da177e4 16#include "dl2k.h"
c4694c76 17#include <linux/dma-mapping.h>
1da177e4
LT		 18
19static char version[] __devinitdata =
6aa20a22 20 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
1da177e4
LT		 21#define MAX_UNITS 8
22static int mtu[MAX_UNITS];
23static int vlan[MAX_UNITS];
24static int jumbo[MAX_UNITS];
25static char *media[MAX_UNITS];
26static int tx_flow=-1;
27static int rx_flow=-1;
28static int copy_thresh;
29static int rx_coalesce=10; /* Rx frame count each interrupt */
30static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
31static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
32
33
34MODULE_AUTHOR ("Edward Peng");
35MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
36MODULE_LICENSE("GPL");
37module_param_array(mtu, int, NULL, 0);
38module_param_array(media, charp, NULL, 0);
39module_param_array(vlan, int, NULL, 0);
40module_param_array(jumbo, int, NULL, 0);
41module_param(tx_flow, int, 0);
42module_param(rx_flow, int, 0);
43module_param(copy_thresh, int, 0);
44module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
45module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
46module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
47
48
49/* Enable the default interrupts */
50#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
51 UpdateStats | LinkEvent)
52#define EnableInt() \
53writew(DEFAULT_INTR, ioaddr + IntEnable)
54
f71e1309
AV		 55static const int max_intrloop = 50;
56static const int multicast_filter_limit = 0x40;
1da177e4
LT		 57
58static int rio_open (struct net_device *dev);
59static void rio_timer (unsigned long data);
60static void rio_tx_timeout (struct net_device *dev);
61static void alloc_list (struct net_device *dev);
62static int start_xmit (struct sk_buff *skb, struct net_device *dev);
7d12e780 63static irqreturn_t rio_interrupt (int irq, void *dev_instance);
1da177e4
LT		 64static void rio_free_tx (struct net_device *dev, int irq);
65static void tx_error (struct net_device *dev, int tx_status);
66static int receive_packet (struct net_device *dev);
67static void rio_error (struct net_device *dev, int int_status);
68static int change_mtu (struct net_device *dev, int new_mtu);
69static void set_multicast (struct net_device *dev);
70static struct net_device_stats *get_stats (struct net_device *dev);
71static int clear_stats (struct net_device *dev);
72static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
73static int rio_close (struct net_device *dev);
74static int find_miiphy (struct net_device *dev);
75static int parse_eeprom (struct net_device *dev);
76static int read_eeprom (long ioaddr, int eep_addr);
77static int mii_wait_link (struct net_device *dev, int wait);
78static int mii_set_media (struct net_device *dev);
79static int mii_get_media (struct net_device *dev);
80static int mii_set_media_pcs (struct net_device *dev);
81static int mii_get_media_pcs (struct net_device *dev);
82static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
83static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
84 u16 data);
85
7282d491 86static const struct ethtool_ops ethtool_ops;
1da177e4 87
87652644
SH		 88static const struct net_device_ops netdev_ops = {
89 .ndo_open = rio_open,
90 .ndo_start_xmit = start_xmit,
91 .ndo_stop = rio_close,
92 .ndo_get_stats = get_stats,
93 .ndo_validate_addr = eth_validate_addr,
94 .ndo_set_mac_address = eth_mac_addr,
95 .ndo_set_multicast_list = set_multicast,
96 .ndo_do_ioctl = rio_ioctl,
97 .ndo_tx_timeout = rio_tx_timeout,
98 .ndo_change_mtu = change_mtu,
99};
100
1da177e4
LT		 101static int __devinit
102rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
103{
104 struct net_device *dev;
105 struct netdev_private *np;
106 static int card_idx;
107 int chip_idx = ent->driver_data;
108 int err, irq;
109 long ioaddr;
110 static int version_printed;
111 void *ring_space;
112 dma_addr_t ring_dma;
113
114 if (!version_printed++)
115 printk ("%s", version);
116
117 err = pci_enable_device (pdev);
118 if (err)
119 return err;
120
121 irq = pdev->irq;
122 err = pci_request_regions (pdev, "dl2k");
123 if (err)
124 goto err_out_disable;
125
126 pci_set_master (pdev);
127 dev = alloc_etherdev (sizeof (*np));
128 if (!dev) {
129 err = -ENOMEM;
130 goto err_out_res;
131 }
1da177e4
LT		 132 SET_NETDEV_DEV(dev, &pdev->dev);
133
134#ifdef MEM_MAPPING
135 ioaddr = pci_resource_start (pdev, 1);
136 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
137 if (!ioaddr) {
138 err = -ENOMEM;
139 goto err_out_dev;
140 }
141#else
142 ioaddr = pci_resource_start (pdev, 0);
143#endif
144 dev->base_addr = ioaddr;
145 dev->irq = irq;
146 np = netdev_priv(dev);
147 np->chip_id = chip_idx;
148 np->pdev = pdev;
149 spin_lock_init (&np->tx_lock);
150 spin_lock_init (&np->rx_lock);
151
152 /* Parse manual configuration */
153 np->an_enable = 1;
154 np->tx_coalesce = 1;
155 if (card_idx < MAX_UNITS) {
156 if (media[card_idx] != NULL) {
157 np->an_enable = 0;
158 if (strcmp (media[card_idx], "auto") == 0 ||
6aa20a22 159 strcmp (media[card_idx], "autosense") == 0 ||
1da177e4 160 strcmp (media[card_idx], "0") == 0 ) {
6aa20a22 161 np->an_enable = 2;
1da177e4
LT		 162 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
163 strcmp (media[card_idx], "4") == 0) {
164 np->speed = 100;
165 np->full_duplex = 1;
166 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
167 || strcmp (media[card_idx], "3") == 0) {
168 np->speed = 100;
169 np->full_duplex = 0;
170 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
171 strcmp (media[card_idx], "2") == 0) {
172 np->speed = 10;
173 np->full_duplex = 1;
174 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
175 strcmp (media[card_idx], "1") == 0) {
176 np->speed = 10;
177 np->full_duplex = 0;
178 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
179 strcmp (media[card_idx], "6") == 0) {
180 np->speed=1000;
181 np->full_duplex=1;
182 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
183 strcmp (media[card_idx], "5") == 0) {
184 np->speed = 1000;
185 np->full_duplex = 0;
186 } else {
187 np->an_enable = 1;
188 }
189 }
190 if (jumbo[card_idx] != 0) {
191 np->jumbo = 1;
192 dev->mtu = MAX_JUMBO;
193 } else {
194 np->jumbo = 0;
195 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
196 dev->mtu = mtu[card_idx];
197 }
198 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
199 vlan[card_idx] : 0;
200 if (rx_coalesce > 0 && rx_timeout > 0) {
201 np->rx_coalesce = rx_coalesce;
202 np->rx_timeout = rx_timeout;
203 np->coalesce = 1;
204 }
205 np->tx_flow = (tx_flow == 0) ? 0 : 1;
206 np->rx_flow = (rx_flow == 0) ? 0 : 1;
207
208 if (tx_coalesce < 1)
209 tx_coalesce = 1;
210 else if (tx_coalesce > TX_RING_SIZE-1)
211 tx_coalesce = TX_RING_SIZE - 1;
212 }
87652644 213 dev->netdev_ops = &netdev_ops;
1da177e4 214 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 215 SET_ETHTOOL_OPS(dev, &ethtool_ops);
216#if 0
217 dev->features = NETIF_F_IP_CSUM;
218#endif
219 pci_set_drvdata (pdev, dev);
220
221 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
222 if (!ring_space)
223 goto err_out_iounmap;
224 np->tx_ring = (struct netdev_desc *) ring_space;
225 np->tx_ring_dma = ring_dma;
226
227 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
228 if (!ring_space)
229 goto err_out_unmap_tx;
230 np->rx_ring = (struct netdev_desc *) ring_space;
231 np->rx_ring_dma = ring_dma;
232
233 /* Parse eeprom data */
234 parse_eeprom (dev);
235
236 /* Find PHY address */
237 err = find_miiphy (dev);
238 if (err)
239 goto err_out_unmap_rx;
6aa20a22 240
1da177e4
LT		 241 /* Fiber device? */
242 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
243 np->link_status = 0;
244 /* Set media and reset PHY */
245 if (np->phy_media) {
246 /* default Auto-Negotiation for fiber deivices */
247 if (np->an_enable == 2) {
248 np->an_enable = 1;
249 }
250 mii_set_media_pcs (dev);
251 } else {
252 /* Auto-Negotiation is mandatory for 1000BASE-T,
253 IEEE 802.3ab Annex 28D page 14 */
254 if (np->speed == 1000)
255 np->an_enable = 1;
256 mii_set_media (dev);
257 }
1da177e4
LT		 258
259 err = register_netdev (dev);
260 if (err)
261 goto err_out_unmap_rx;
262
263 card_idx++;
264
e174961c
JB		 265 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
266 dev->name, np->name, dev->dev_addr, irq);
1da177e4 267 if (tx_coalesce > 1)
6aa20a22 268 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
1da177e4
LT		 269 tx_coalesce);
270 if (np->coalesce)
271 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
6aa20a22 272 KERN_INFO "rx_timeout: \t%d ns\n",
1da177e4
LT		 273 np->rx_coalesce, np->rx_timeout*640);
274 if (np->vlan)
275 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
276 return 0;
277
278 err_out_unmap_rx:
279 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
280 err_out_unmap_tx:
281 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
282 err_out_iounmap:
283#ifdef MEM_MAPPING
284 iounmap ((void *) ioaddr);
285
286 err_out_dev:
287#endif
288 free_netdev (dev);
289
290 err_out_res:
291 pci_release_regions (pdev);
292
293 err_out_disable:
294 pci_disable_device (pdev);
295 return err;
296}
297
ddfce6bb 298static int
1da177e4
LT		 299find_miiphy (struct net_device *dev)
300{
301 int i, phy_found = 0;
302 struct netdev_private *np;
303 long ioaddr;
304 np = netdev_priv(dev);
305 ioaddr = dev->base_addr;
306 np->phy_addr = 1;
307
308 for (i = 31; i >= 0; i--) {
309 int mii_status = mii_read (dev, i, 1);
310 if (mii_status != 0xffff && mii_status != 0x0000) {
311 np->phy_addr = i;
312 phy_found++;
313 }
314 }
315 if (!phy_found) {
316 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
317 return -ENODEV;
318 }
319 return 0;
320}
321
ddfce6bb 322static int
1da177e4
LT		 323parse_eeprom (struct net_device *dev)
324{
325 int i, j;
326 long ioaddr = dev->base_addr;
327 u8 sromdata[256];
328 u8 *psib;
329 u32 crc;
330 PSROM_t psrom = (PSROM_t) sromdata;
331 struct netdev_private *np = netdev_priv(dev);
332
333 int cid, next;
334
335#ifdef MEM_MAPPING
336 ioaddr = pci_resource_start (np->pdev, 0);
337#endif
338 /* Read eeprom */
339 for (i = 0; i < 128; i++) {
78ce8d3d 340 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
1da177e4
LT		 341 }
342#ifdef MEM_MAPPING
343 ioaddr = dev->base_addr;
6aa20a22 344#endif
df950828
K		 345 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
346 /* Check CRC */
347 crc = ~ether_crc_le (256 - 4, sromdata);
348 if (psrom->crc != crc) {
349 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
350 dev->name);
351 return -1;
352 }
1da177e4
LT		 353 }
354
355 /* Set MAC address */
356 for (i = 0; i < 6; i++)
357 dev->dev_addr[i] = psrom->mac_addr[i];
358
df950828
K		 359 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
360 return 0;
361 }
362
47bdd718 363 /* Parse Software Information Block */
1da177e4
LT		 364 i = 0x30;
365 psib = (u8 *) sromdata;
366 do {
367 cid = psib[i++];
368 next = psib[i++];
369 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
370 printk (KERN_ERR "Cell data error\n");
371 return -1;
372 }
373 switch (cid) {
374 case 0: /* Format version */
375 break;
376 case 1: /* End of cell */
377 return 0;
378 case 2: /* Duplex Polarity */
379 np->duplex_polarity = psib[i];
380 writeb (readb (ioaddr + PhyCtrl) | psib[i],
381 ioaddr + PhyCtrl);
382 break;
383 case 3: /* Wake Polarity */
384 np->wake_polarity = psib[i];
385 break;
386 case 9: /* Adapter description */
387 j = (next - i > 255) ? 255 : next - i;
388 memcpy (np->name, &(psib[i]), j);
389 break;
390 case 4:
391 case 5:
392 case 6:
393 case 7:
394 case 8: /* Reversed */
395 break;
396 default: /* Unknown cell */
397 return -1;
398 }
399 i = next;
400 } while (1);
401
402 return 0;
403}
404
405static int
406rio_open (struct net_device *dev)
407{
408 struct netdev_private *np = netdev_priv(dev);
409 long ioaddr = dev->base_addr;
410 int i;
411 u16 macctrl;
6aa20a22 412
1fb9df5d 413 i = request_irq (dev->irq, &rio_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 414 if (i)
415 return i;
6aa20a22 416
1da177e4
LT		 417 /* Reset all logic functions */
418 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
419 ioaddr + ASICCtrl + 2);
420 mdelay(10);
6aa20a22 421
1da177e4
LT		 422 /* DebugCtrl bit 4, 5, 9 must set */
423 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
424
425 /* Jumbo frame */
426 if (np->jumbo != 0)
427 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
428
429 alloc_list (dev);
430
431 /* Get station address */
432 for (i = 0; i < 6; i++)
433 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
434
435 set_multicast (dev);
436 if (np->coalesce) {
437 writel (np->rx_coalesce | np->rx_timeout << 16,
438 ioaddr + RxDMAIntCtrl);
439 }
440 /* Set RIO to poll every N*320nsec. */
441 writeb (0x20, ioaddr + RxDMAPollPeriod);
442 writeb (0xff, ioaddr + TxDMAPollPeriod);
443 writeb (0x30, ioaddr + RxDMABurstThresh);
444 writeb (0x30, ioaddr + RxDMAUrgentThresh);
445 writel (0x0007ffff, ioaddr + RmonStatMask);
446 /* clear statistics */
447 clear_stats (dev);
448
449 /* VLAN supported */
450 if (np->vlan) {
451 /* priority field in RxDMAIntCtrl */
6aa20a22 452 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
1da177e4
LT		 453 ioaddr + RxDMAIntCtrl);
454 /* VLANId */
455 writew (np->vlan, ioaddr + VLANId);
456 /* Length/Type should be 0x8100 */
457 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
458 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
459 VLAN information tagged by TFC' VID, CFI fields. */
460 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
461 ioaddr + MACCtrl);
462 }
463
464 init_timer (&np->timer);
465 np->timer.expires = jiffies + 1*HZ;
466 np->timer.data = (unsigned long) dev;
467 np->timer.function = &rio_timer;
468 add_timer (&np->timer);
469
470 /* Start Tx/Rx */
6aa20a22 471 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
1da177e4 472 ioaddr + MACCtrl);
6aa20a22 473
1da177e4
LT		 474 macctrl = 0;
475 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
476 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
477 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
478 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
479 writew(macctrl, ioaddr + MACCtrl);
480
481 netif_start_queue (dev);
6aa20a22 482
1da177e4
LT		 483 /* Enable default interrupts */
484 EnableInt ();
485 return 0;
486}
487
6aa20a22 488static void
1da177e4
LT		 489rio_timer (unsigned long data)
490{
491 struct net_device *dev = (struct net_device *)data;
492 struct netdev_private *np = netdev_priv(dev);
493 unsigned int entry;
494 int next_tick = 1*HZ;
495 unsigned long flags;
496
497 spin_lock_irqsave(&np->rx_lock, flags);
498 /* Recover rx ring exhausted error */
499 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
500 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
501 /* Re-allocate skbuffs to fill the descriptor ring */
502 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
503 struct sk_buff *skb;
504 entry = np->old_rx % RX_RING_SIZE;
505 /* Dropped packets don't need to re-allocate */
506 if (np->rx_skbuff[entry] == NULL) {
47f98c7d 507 skb = netdev_alloc_skb (dev, np->rx_buf_sz);
1da177e4
LT		 508 if (skb == NULL) {
509 np->rx_ring[entry].fraginfo = 0;
510 printk (KERN_INFO
511 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
512 dev->name, entry);
513 break;
514 }
515 np->rx_skbuff[entry] = skb;
1da177e4
LT		 516 /* 16 byte align the IP header */
517 skb_reserve (skb, 2);
518 np->rx_ring[entry].fraginfo =
519 cpu_to_le64 (pci_map_single
689be439 520 (np->pdev, skb->data, np->rx_buf_sz,
1da177e4
LT		 521 PCI_DMA_FROMDEVICE));
522 }
523 np->rx_ring[entry].fraginfo |=
78ce8d3d 524 cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 525 np->rx_ring[entry].status = 0;
526 } /* end for */
527 } /* end if */
528 spin_unlock_irqrestore (&np->rx_lock, flags);
529 np->timer.expires = jiffies + next_tick;
530 add_timer(&np->timer);
531}
6aa20a22 532
1da177e4
LT		 533static void
534rio_tx_timeout (struct net_device *dev)
535{
536 long ioaddr = dev->base_addr;
537
538 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
539 dev->name, readl (ioaddr + TxStatus));
540 rio_free_tx(dev, 0);
541 dev->if_port = 0;
cdd0db05 542 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 543}
544
545 /* allocate and initialize Tx and Rx descriptors */
546static void
547alloc_list (struct net_device *dev)
548{
549 struct netdev_private *np = netdev_priv(dev);
550 int i;
551
552 np->cur_rx = np->cur_tx = 0;
553 np->old_rx = np->old_tx = 0;
554 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
555
556 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
557 for (i = 0; i < TX_RING_SIZE; i++) {
558 np->tx_skbuff[i] = NULL;
559 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
560 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
561 ((i+1)%TX_RING_SIZE) *
562 sizeof (struct netdev_desc));
563 }
564
565 /* Initialize Rx descriptors */
566 for (i = 0; i < RX_RING_SIZE; i++) {
567 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
568 ((i + 1) % RX_RING_SIZE) *
569 sizeof (struct netdev_desc));
570 np->rx_ring[i].status = 0;
571 np->rx_ring[i].fraginfo = 0;
572 np->rx_skbuff[i] = NULL;
573 }
574
575 /* Allocate the rx buffers */
576 for (i = 0; i < RX_RING_SIZE; i++) {
577 /* Allocated fixed size of skbuff */
47f98c7d 578 struct sk_buff *skb = netdev_alloc_skb (dev, np->rx_buf_sz);
1da177e4
LT		 579 np->rx_skbuff[i] = skb;
580 if (skb == NULL) {
581 printk (KERN_ERR
582 "%s: alloc_list: allocate Rx buffer error! ",
583 dev->name);
584 break;
585 }
1da177e4
LT		 586 skb_reserve (skb, 2); /* 16 byte align the IP header. */
587 /* Rubicon now supports 40 bits of addressing space. */
588 np->rx_ring[i].fraginfo =
589 cpu_to_le64 ( pci_map_single (
689be439 590 np->pdev, skb->data, np->rx_buf_sz,
1da177e4 591 PCI_DMA_FROMDEVICE));
78ce8d3d 592 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 593 }
594
595 /* Set RFDListPtr */
78ce8d3d 596 writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
1da177e4
LT		 597 writel (0, dev->base_addr + RFDListPtr1);
598
599 return;
600}
601
602static int
603start_xmit (struct sk_buff *skb, struct net_device *dev)
604{
605 struct netdev_private *np = netdev_priv(dev);
606 struct netdev_desc *txdesc;
607 unsigned entry;
608 u32 ioaddr;
609 u64 tfc_vlan_tag = 0;
610
611 if (np->link_status == 0) { /* Link Down */
612 dev_kfree_skb(skb);
cdd0db05 613 return NETDEV_TX_OK;
1da177e4
LT		 614 }
615 ioaddr = dev->base_addr;
616 entry = np->cur_tx % TX_RING_SIZE;
617 np->tx_skbuff[entry] = skb;
618 txdesc = &np->tx_ring[entry];
619
620#if 0
84fa7933 621 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 622 txdesc->status |=
623 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
624 IPChecksumEnable);
625 }
626#endif
627 if (np->vlan) {
78ce8d3d
AV		 628 tfc_vlan_tag = VLANTagInsert |
629 ((u64)np->vlan << 32) |
630 ((u64)skb->priority << 45);
1da177e4
LT		 631 }
632 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
633 skb->len,
634 PCI_DMA_TODEVICE));
78ce8d3d 635 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
1da177e4
LT		 636
637 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
638 * Work around: Always use 1 descriptor in 10Mbps mode */
639 if (entry % np->tx_coalesce == 0 || np->speed == 10)
640 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
6aa20a22 641 WordAlignDisable |
1da177e4
LT		 642 TxDMAIndicate |
643 (1 << FragCountShift));
644 else
645 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
6aa20a22 646 WordAlignDisable |
1da177e4
LT		 647 (1 << FragCountShift));
648
649 /* TxDMAPollNow */
650 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
651 /* Schedule ISR */
652 writel(10000, ioaddr + CountDown);
653 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
654 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
655 < TX_QUEUE_LEN - 1 && np->speed != 10) {
656 /* do nothing */
657 } else if (!netif_queue_stopped(dev)) {
658 netif_stop_queue (dev);
659 }
660
661 /* The first TFDListPtr */
662 if (readl (dev->base_addr + TFDListPtr0) == 0) {
663 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
664 dev->base_addr + TFDListPtr0);
665 writel (0, dev->base_addr + TFDListPtr1);
666 }
6aa20a22 667
cdd0db05 668 return NETDEV_TX_OK;
1da177e4
LT		 669}
670
671static irqreturn_t
7d12e780 672rio_interrupt (int irq, void *dev_instance)
1da177e4
LT		 673{
674 struct net_device *dev = dev_instance;
675 struct netdev_private *np;
676 unsigned int_status;
677 long ioaddr;
678 int cnt = max_intrloop;
679 int handled = 0;
680
681 ioaddr = dev->base_addr;
682 np = netdev_priv(dev);
683 while (1) {
6aa20a22 684 int_status = readw (ioaddr + IntStatus);
1da177e4
LT		 685 writew (int_status, ioaddr + IntStatus);
686 int_status &= DEFAULT_INTR;
687 if (int_status == 0 || --cnt < 0)
688 break;
689 handled = 1;
690 /* Processing received packets */
691 if (int_status & RxDMAComplete)
692 receive_packet (dev);
693 /* TxDMAComplete interrupt */
694 if ((int_status & (TxDMAComplete|IntRequested))) {
695 int tx_status;
696 tx_status = readl (ioaddr + TxStatus);
697 if (tx_status & 0x01)
698 tx_error (dev, tx_status);
699 /* Free used tx skbuffs */
6aa20a22 700 rio_free_tx (dev, 1);
1da177e4
LT		 701 }
702
703 /* Handle uncommon events */
704 if (int_status &
705 (HostError | LinkEvent | UpdateStats))
706 rio_error (dev, int_status);
707 }
708 if (np->cur_tx != np->old_tx)
709 writel (100, ioaddr + CountDown);
710 return IRQ_RETVAL(handled);
711}
712
78ce8d3d
AV		 713static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
714{
e911e0d9 715 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
78ce8d3d
AV		 716}
717
6aa20a22
JG		 718static void
719rio_free_tx (struct net_device *dev, int irq)
1da177e4
LT		 720{
721 struct netdev_private *np = netdev_priv(dev);
722 int entry = np->old_tx % TX_RING_SIZE;
723 int tx_use = 0;
724 unsigned long flag = 0;
6aa20a22 725
1da177e4
LT		 726 if (irq)
727 spin_lock(&np->tx_lock);
728 else
729 spin_lock_irqsave(&np->tx_lock, flag);
6aa20a22 730
1da177e4
LT		 731 /* Free used tx skbuffs */
732 while (entry != np->cur_tx) {
733 struct sk_buff *skb;
734
78ce8d3d 735 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
1da177e4
LT		 736 break;
737 skb = np->tx_skbuff[entry];
738 pci_unmap_single (np->pdev,
78ce8d3d 739 desc_to_dma(&np->tx_ring[entry]),
1da177e4
LT		 740 skb->len, PCI_DMA_TODEVICE);
741 if (irq)
742 dev_kfree_skb_irq (skb);
743 else
744 dev_kfree_skb (skb);
745
746 np->tx_skbuff[entry] = NULL;
747 entry = (entry + 1) % TX_RING_SIZE;
748 tx_use++;
749 }
750 if (irq)
751 spin_unlock(&np->tx_lock);
752 else
753 spin_unlock_irqrestore(&np->tx_lock, flag);
754 np->old_tx = entry;
755
6aa20a22 756 /* If the ring is no longer full, clear tx_full and
1da177e4
LT		 757 call netif_wake_queue() */
758
759 if (netif_queue_stopped(dev) &&
6aa20a22 760 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
1da177e4
LT		 761 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
762 netif_wake_queue (dev);
763 }
764}
765
766static void
767tx_error (struct net_device *dev, int tx_status)
768{
769 struct netdev_private *np;
770 long ioaddr = dev->base_addr;
771 int frame_id;
772 int i;
773
774 np = netdev_priv(dev);
775
776 frame_id = (tx_status & 0xffff0000);
777 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
778 dev->name, tx_status, frame_id);
779 np->stats.tx_errors++;
780 /* Ttransmit Underrun */
781 if (tx_status & 0x10) {
782 np->stats.tx_fifo_errors++;
783 writew (readw (ioaddr + TxStartThresh) + 0x10,
784 ioaddr + TxStartThresh);
785 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
786 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
787 ioaddr + ASICCtrl + 2);
788 /* Wait for ResetBusy bit clear */
789 for (i = 50; i > 0; i--) {
790 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
791 break;
792 mdelay (1);
793 }
794 rio_free_tx (dev, 1);
795 /* Reset TFDListPtr */
796 writel (np->tx_ring_dma +
797 np->old_tx * sizeof (struct netdev_desc),
798 dev->base_addr + TFDListPtr0);
799 writel (0, dev->base_addr + TFDListPtr1);
800
801 /* Let TxStartThresh stay default value */
802 }
803 /* Late Collision */
804 if (tx_status & 0x04) {
805 np->stats.tx_fifo_errors++;
806 /* TxReset and clear FIFO */
807 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
808 /* Wait reset done */
809 for (i = 50; i > 0; i--) {
810 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
811 break;
812 mdelay (1);
813 }
814 /* Let TxStartThresh stay default value */
815 }
816 /* Maximum Collisions */
6aa20a22
JG		 817#ifdef ETHER_STATS
818 if (tx_status & 0x08)
1da177e4
LT		 819 np->stats.collisions16++;
820#else
6aa20a22 821 if (tx_status & 0x08)
1da177e4
LT		 822 np->stats.collisions++;
823#endif
824 /* Restart the Tx */
825 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
826}
827
828static int
829receive_packet (struct net_device *dev)
830{
831 struct netdev_private *np = netdev_priv(dev);
832 int entry = np->cur_rx % RX_RING_SIZE;
833 int cnt = 30;
834
835 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
836 while (1) {
837 struct netdev_desc *desc = &np->rx_ring[entry];
838 int pkt_len;
839 u64 frame_status;
840
78ce8d3d
AV		 841 if (!(desc->status & cpu_to_le64(RFDDone)) ||
842 !(desc->status & cpu_to_le64(FrameStart)) ||
843 !(desc->status & cpu_to_le64(FrameEnd)))
1da177e4
LT		 844 break;
845
846 /* Chip omits the CRC. */
78ce8d3d
AV		 847 frame_status = le64_to_cpu(desc->status);
848 pkt_len = frame_status & 0xffff;
1da177e4
LT		 849 if (--cnt < 0)
850 break;
851 /* Update rx error statistics, drop packet. */
852 if (frame_status & RFS_Errors) {
853 np->stats.rx_errors++;
854 if (frame_status & (RxRuntFrame | RxLengthError))
855 np->stats.rx_length_errors++;
856 if (frame_status & RxFCSError)
857 np->stats.rx_crc_errors++;
858 if (frame_status & RxAlignmentError && np->speed != 1000)
859 np->stats.rx_frame_errors++;
860 if (frame_status & RxFIFOOverrun)
861 np->stats.rx_fifo_errors++;
862 } else {
863 struct sk_buff *skb;
864
865 /* Small skbuffs for short packets */
866 if (pkt_len > copy_thresh) {
9ee09d9c 867 pci_unmap_single (np->pdev,
78ce8d3d 868 desc_to_dma(desc),
1da177e4
LT		 869 np->rx_buf_sz,
870 PCI_DMA_FROMDEVICE);
871 skb_put (skb = np->rx_skbuff[entry], pkt_len);
872 np->rx_skbuff[entry] = NULL;
47f98c7d 873 } else if ((skb = netdev_alloc_skb(dev, pkt_len + 2))) {
1da177e4 874 pci_dma_sync_single_for_cpu(np->pdev,
78ce8d3d 875 desc_to_dma(desc),
1da177e4
LT		 876 np->rx_buf_sz,
877 PCI_DMA_FROMDEVICE);
1da177e4
LT		 878 /* 16 byte align the IP header */
879 skb_reserve (skb, 2);
8c7b7faa 880 skb_copy_to_linear_data (skb,
689be439 881 np->rx_skbuff[entry]->data,
8c7b7faa 882 pkt_len);
1da177e4
LT		 883 skb_put (skb, pkt_len);
884 pci_dma_sync_single_for_device(np->pdev,
78ce8d3d 885 desc_to_dma(desc),
1da177e4
LT		 886 np->rx_buf_sz,
887 PCI_DMA_FROMDEVICE);
888 }
889 skb->protocol = eth_type_trans (skb, dev);
6aa20a22 890#if 0
1da177e4 891 /* Checksum done by hw, but csum value unavailable. */
44c10138 892 if (np->pdev->pci_rev_id >= 0x0c &&
1da177e4
LT		 893 !(frame_status & (TCPError | UDPError | IPError))) {
894 skb->ip_summed = CHECKSUM_UNNECESSARY;
6aa20a22 895 }
1da177e4
LT		 896#endif
897 netif_rx (skb);
1da177e4
LT		 898 }
899 entry = (entry + 1) % RX_RING_SIZE;
900 }
901 spin_lock(&np->rx_lock);
902 np->cur_rx = entry;
903 /* Re-allocate skbuffs to fill the descriptor ring */
904 entry = np->old_rx;
905 while (entry != np->cur_rx) {
906 struct sk_buff *skb;
907 /* Dropped packets don't need to re-allocate */
908 if (np->rx_skbuff[entry] == NULL) {
47f98c7d 909 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
1da177e4
LT		 910 if (skb == NULL) {
911 np->rx_ring[entry].fraginfo = 0;
912 printk (KERN_INFO
913 "%s: receive_packet: "
914 "Unable to re-allocate Rx skbuff.#%d\n",
915 dev->name, entry);
916 break;
917 }
918 np->rx_skbuff[entry] = skb;
1da177e4
LT		 919 /* 16 byte align the IP header */
920 skb_reserve (skb, 2);
921 np->rx_ring[entry].fraginfo =
922 cpu_to_le64 (pci_map_single
689be439 923 (np->pdev, skb->data, np->rx_buf_sz,
1da177e4
LT		 924 PCI_DMA_FROMDEVICE));
925 }
926 np->rx_ring[entry].fraginfo |=
78ce8d3d 927 cpu_to_le64((u64)np->rx_buf_sz << 48);
1da177e4
LT		 928 np->rx_ring[entry].status = 0;
929 entry = (entry + 1) % RX_RING_SIZE;
930 }
931 np->old_rx = entry;
932 spin_unlock(&np->rx_lock);
933 return 0;
934}
935
936static void
937rio_error (struct net_device *dev, int int_status)
938{
939 long ioaddr = dev->base_addr;
940 struct netdev_private *np = netdev_priv(dev);
941 u16 macctrl;
942
943 /* Link change event */
944 if (int_status & LinkEvent) {
945 if (mii_wait_link (dev, 10) == 0) {
946 printk (KERN_INFO "%s: Link up\n", dev->name);
947 if (np->phy_media)
948 mii_get_media_pcs (dev);
949 else
950 mii_get_media (dev);
951 if (np->speed == 1000)
952 np->tx_coalesce = tx_coalesce;
6aa20a22 953 else
1da177e4
LT		 954 np->tx_coalesce = 1;
955 macctrl = 0;
956 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
957 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
6aa20a22 958 macctrl |= (np->tx_flow) ?
1da177e4 959 TxFlowControlEnable : 0;
6aa20a22 960 macctrl |= (np->rx_flow) ?
1da177e4
LT		 961 RxFlowControlEnable : 0;
962 writew(macctrl, ioaddr + MACCtrl);
963 np->link_status = 1;
964 netif_carrier_on(dev);
965 } else {
966 printk (KERN_INFO "%s: Link off\n", dev->name);
967 np->link_status = 0;
968 netif_carrier_off(dev);
969 }
970 }
971
972 /* UpdateStats statistics registers */
973 if (int_status & UpdateStats) {
974 get_stats (dev);
975 }
976
6aa20a22 977 /* PCI Error, a catastronphic error related to the bus interface
1da177e4
LT		 978 occurs, set GlobalReset and HostReset to reset. */
979 if (int_status & HostError) {
980 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
981 dev->name, int_status);
982 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
983 mdelay (500);
984 }
985}
986
987static struct net_device_stats *
988get_stats (struct net_device *dev)
989{
990 long ioaddr = dev->base_addr;
991 struct netdev_private *np = netdev_priv(dev);
992#ifdef MEM_MAPPING
993 int i;
994#endif
995 unsigned int stat_reg;
996
997 /* All statistics registers need to be acknowledged,
998 else statistic overflow could cause problems */
6aa20a22 999
1da177e4
LT		 1000 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1001 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1002 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1003 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1004
1005 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
6aa20a22
JG		 1006 np->stats.collisions += readl (ioaddr + SingleColFrames)
1007 + readl (ioaddr + MultiColFrames);
1008
1da177e4
LT		 1009 /* detailed tx errors */
1010 stat_reg = readw (ioaddr + FramesAbortXSColls);
1011 np->stats.tx_aborted_errors += stat_reg;
1012 np->stats.tx_errors += stat_reg;
1013
1014 stat_reg = readw (ioaddr + CarrierSenseErrors);
1015 np->stats.tx_carrier_errors += stat_reg;
1016 np->stats.tx_errors += stat_reg;
1017
1018 /* Clear all other statistic register. */
1019 readl (ioaddr + McstOctetXmtOk);
1020 readw (ioaddr + BcstFramesXmtdOk);
1021 readl (ioaddr + McstFramesXmtdOk);
1022 readw (ioaddr + BcstFramesRcvdOk);
1023 readw (ioaddr + MacControlFramesRcvd);
1024 readw (ioaddr + FrameTooLongErrors);
1025 readw (ioaddr + InRangeLengthErrors);
1026 readw (ioaddr + FramesCheckSeqErrors);
1027 readw (ioaddr + FramesLostRxErrors);
1028 readl (ioaddr + McstOctetXmtOk);
1029 readl (ioaddr + BcstOctetXmtOk);
1030 readl (ioaddr + McstFramesXmtdOk);
1031 readl (ioaddr + FramesWDeferredXmt);
1032 readl (ioaddr + LateCollisions);
1033 readw (ioaddr + BcstFramesXmtdOk);
1034 readw (ioaddr + MacControlFramesXmtd);
1035 readw (ioaddr + FramesWEXDeferal);
1036
1037#ifdef MEM_MAPPING
1038 for (i = 0x100; i <= 0x150; i += 4)
1039 readl (ioaddr + i);
1040#endif
1041 readw (ioaddr + TxJumboFrames);
1042 readw (ioaddr + RxJumboFrames);
1043 readw (ioaddr + TCPCheckSumErrors);
1044 readw (ioaddr + UDPCheckSumErrors);
1045 readw (ioaddr + IPCheckSumErrors);
1046 return &np->stats;
1047}
1048
1049static int
1050clear_stats (struct net_device *dev)
1051{
1052 long ioaddr = dev->base_addr;
1053#ifdef MEM_MAPPING
1054 int i;
6aa20a22 1055#endif
1da177e4
LT		 1056
1057 /* All statistics registers need to be acknowledged,
1058 else statistic overflow could cause problems */
1059 readl (ioaddr + FramesRcvOk);
1060 readl (ioaddr + FramesXmtOk);
1061 readl (ioaddr + OctetRcvOk);
1062 readl (ioaddr + OctetXmtOk);
1063
1064 readl (ioaddr + McstFramesRcvdOk);
1065 readl (ioaddr + SingleColFrames);
1066 readl (ioaddr + MultiColFrames);
1067 readl (ioaddr + LateCollisions);
6aa20a22 1068 /* detailed rx errors */
1da177e4
LT		 1069 readw (ioaddr + FrameTooLongErrors);
1070 readw (ioaddr + InRangeLengthErrors);
1071 readw (ioaddr + FramesCheckSeqErrors);
1072 readw (ioaddr + FramesLostRxErrors);
1073
1074 /* detailed tx errors */
1075 readw (ioaddr + FramesAbortXSColls);
1076 readw (ioaddr + CarrierSenseErrors);
1077
1078 /* Clear all other statistic register. */
1079 readl (ioaddr + McstOctetXmtOk);
1080 readw (ioaddr + BcstFramesXmtdOk);
1081 readl (ioaddr + McstFramesXmtdOk);
1082 readw (ioaddr + BcstFramesRcvdOk);
1083 readw (ioaddr + MacControlFramesRcvd);
1084 readl (ioaddr + McstOctetXmtOk);
1085 readl (ioaddr + BcstOctetXmtOk);
1086 readl (ioaddr + McstFramesXmtdOk);
1087 readl (ioaddr + FramesWDeferredXmt);
1088 readw (ioaddr + BcstFramesXmtdOk);
1089 readw (ioaddr + MacControlFramesXmtd);
1090 readw (ioaddr + FramesWEXDeferal);
1091#ifdef MEM_MAPPING
1092 for (i = 0x100; i <= 0x150; i += 4)
1093 readl (ioaddr + i);
6aa20a22 1094#endif
1da177e4
LT		 1095 readw (ioaddr + TxJumboFrames);
1096 readw (ioaddr + RxJumboFrames);
1097 readw (ioaddr + TCPCheckSumErrors);
1098 readw (ioaddr + UDPCheckSumErrors);
1099 readw (ioaddr + IPCheckSumErrors);
1100 return 0;
1101}
1102
1103
ddfce6bb 1104static int
1da177e4
LT		 1105change_mtu (struct net_device *dev, int new_mtu)
1106{
1107 struct netdev_private *np = netdev_priv(dev);
1108 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1109
1110 if ((new_mtu < 68) || (new_mtu > max)) {
1111 return -EINVAL;
1112 }
1113
1114 dev->mtu = new_mtu;
1115
1116 return 0;
1117}
1118
1119static void
1120set_multicast (struct net_device *dev)
1121{
1122 long ioaddr = dev->base_addr;
1123 u32 hash_table[2];
1124 u16 rx_mode = 0;
1125 struct netdev_private *np = netdev_priv(dev);
6aa20a22 1126
1da177e4
LT		 1127 hash_table[0] = hash_table[1] = 0;
1128 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
78ce8d3d 1129 hash_table[1] |= 0x02000000;
1da177e4
LT		 1130 if (dev->flags & IFF_PROMISC) {
1131 /* Receive all frames promiscuously. */
1132 rx_mode = ReceiveAllFrames;
6aa20a22 1133 } else if ((dev->flags & IFF_ALLMULTI) ||
1da177e4
LT		 1134 (dev->mc_count > multicast_filter_limit)) {
1135 /* Receive broadcast and multicast frames */
1136 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1137 } else if (dev->mc_count > 0) {
1138 int i;
1139 struct dev_mc_list *mclist;
6aa20a22 1140 /* Receive broadcast frames and multicast frames filtering
1da177e4
LT		 1141 by Hashtable */
1142 rx_mode =
1143 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
6aa20a22
JG		 1144 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1145 i++, mclist=mclist->next)
1da177e4
LT		 1146 {
1147 int bit, index = 0;
1148 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1149 /* The inverted high significant 6 bits of CRC are
1150 used as an index to hashtable */
1151 for (bit = 0; bit < 6; bit++)
1152 if (crc & (1 << (31 - bit)))
1153 index |= (1 << bit);
1154 hash_table[index / 32] |= (1 << (index % 32));
1155 }
1156 } else {
1157 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1158 }
1159 if (np->vlan) {
1160 /* ReceiveVLANMatch field in ReceiveMode */
1161 rx_mode |= ReceiveVLANMatch;
1162 }
1163
1164 writel (hash_table[0], ioaddr + HashTable0);
1165 writel (hash_table[1], ioaddr + HashTable1);
1166 writew (rx_mode, ioaddr + ReceiveMode);
1167}
1168
1169static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1170{
1171 struct netdev_private *np = netdev_priv(dev);
1172 strcpy(info->driver, "dl2k");
1173 strcpy(info->version, DRV_VERSION);
1174 strcpy(info->bus_info, pci_name(np->pdev));
6aa20a22 1175}
1da177e4
LT		 1176
1177static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1178{
1179 struct netdev_private *np = netdev_priv(dev);
1180 if (np->phy_media) {
1181 /* fiber device */
1182 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1183 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1184 cmd->port = PORT_FIBRE;
6aa20a22 1185 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 1186 } else {
1187 /* copper device */
6aa20a22 1188 cmd->supported = SUPPORTED_10baseT_Half |
1da177e4
LT		 1189 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1190 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1191 SUPPORTED_Autoneg | SUPPORTED_MII;
1192 cmd->advertising = ADVERTISED_10baseT_Half |
1193 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1194 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1195 ADVERTISED_Autoneg | ADVERTISED_MII;
1196 cmd->port = PORT_MII;
1197 cmd->transceiver = XCVR_INTERNAL;
1198 }
6aa20a22 1199 if ( np->link_status ) {
1da177e4
LT		 1200 cmd->speed = np->speed;
1201 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1202 } else {
1203 cmd->speed = -1;
1204 cmd->duplex = -1;
1205 }
1206 if ( np->an_enable)
1207 cmd->autoneg = AUTONEG_ENABLE;
1208 else
1209 cmd->autoneg = AUTONEG_DISABLE;
6aa20a22 1210
1da177e4 1211 cmd->phy_address = np->phy_addr;
6aa20a22 1212 return 0;
1da177e4
LT		 1213}
1214
1215static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1216{
1217 struct netdev_private *np = netdev_priv(dev);
1218 netif_carrier_off(dev);
1219 if (cmd->autoneg == AUTONEG_ENABLE) {
1220 if (np->an_enable)
1221 return 0;
1222 else {
1223 np->an_enable = 1;
1224 mii_set_media(dev);
6aa20a22
JG		 1225 return 0;
1226 }
1da177e4
LT		 1227 } else {
1228 np->an_enable = 0;
1229 if (np->speed == 1000) {
6aa20a22 1230 cmd->speed = SPEED_100;
1da177e4
LT		 1231 cmd->duplex = DUPLEX_FULL;
1232 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1233 }
1234 switch(cmd->speed + cmd->duplex) {
6aa20a22 1235
1da177e4
LT		 1236 case SPEED_10 + DUPLEX_HALF:
1237 np->speed = 10;
1238 np->full_duplex = 0;
1239 break;
6aa20a22 1240
1da177e4
LT		 1241 case SPEED_10 + DUPLEX_FULL:
1242 np->speed = 10;
1243 np->full_duplex = 1;
1244 break;
1245 case SPEED_100 + DUPLEX_HALF:
1246 np->speed = 100;
1247 np->full_duplex = 0;
1248 break;
1249 case SPEED_100 + DUPLEX_FULL:
1250 np->speed = 100;
1251 np->full_duplex = 1;
1252 break;
1253 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1254 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1255 default:
6aa20a22 1256 return -EINVAL;
1da177e4
LT		 1257 }
1258 mii_set_media(dev);
1259 }
1260 return 0;
1261}
1262
1263static u32 rio_get_link(struct net_device *dev)
1264{
1265 struct netdev_private *np = netdev_priv(dev);
1266 return np->link_status;
1267}
1268
7282d491 1269static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1270 .get_drvinfo = rio_get_drvinfo,
1271 .get_settings = rio_get_settings,
1272 .set_settings = rio_set_settings,
1273 .get_link = rio_get_link,
1274};
1275
1276static int
1277rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1278{
1279 int phy_addr;
1280 struct netdev_private *np = netdev_priv(dev);
1281 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
6aa20a22 1282
1da177e4
LT		 1283 struct netdev_desc *desc;
1284 int i;
1285
1286 phy_addr = np->phy_addr;
1287 switch (cmd) {
1288 case SIOCDEVPRIVATE:
1289 break;
6aa20a22 1290
1da177e4
LT		 1291 case SIOCDEVPRIVATE + 1:
1292 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1293 break;
1294 case SIOCDEVPRIVATE + 2:
1295 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1296 break;
1297 case SIOCDEVPRIVATE + 3:
1298 break;
1299 case SIOCDEVPRIVATE + 4:
1300 break;
1301 case SIOCDEVPRIVATE + 5:
1302 netif_stop_queue (dev);
1303 break;
1304 case SIOCDEVPRIVATE + 6:
1305 netif_wake_queue (dev);
1306 break;
1307 case SIOCDEVPRIVATE + 7:
1308 printk
1309 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1310 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1311 np->old_rx);
1312 break;
1313 case SIOCDEVPRIVATE + 8:
1314 printk("TX ring:\n");
1315 for (i = 0; i < TX_RING_SIZE; i++) {
1316 desc = &np->tx_ring[i];
1317 printk
1318 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1319 i,
1320 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
0ca5f319
AV		 1321 (u32)le64_to_cpu(desc->next_desc),
1322 (u32)le64_to_cpu(desc->status),
1323 (u32)(le64_to_cpu(desc->fraginfo) >> 32),
1324 (u32)le64_to_cpu(desc->fraginfo));
1da177e4
LT		 1325 printk ("\n");
1326 }
1327 printk ("\n");
1328 break;
1329
1330 default:
1331 return -EOPNOTSUPP;
1332 }
1333 return 0;
1334}
1335
1336#define EEP_READ 0x0200
1337#define EEP_BUSY 0x8000
1338/* Read the EEPROM word */
1339/* We use I/O instruction to read/write eeprom to avoid fail on some machines */
ddfce6bb 1340static int
1da177e4
LT		 1341read_eeprom (long ioaddr, int eep_addr)
1342{
1343 int i = 1000;
1344 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1345 while (i-- > 0) {
1346 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1347 return inw (ioaddr + EepromData);
1348 }
1349 }
1350 return 0;
1351}
1352
1353enum phy_ctrl_bits {
1354 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1355 MII_DUPLEX = 0x08,
1356};
1357
1358#define mii_delay() readb(ioaddr)
1359static void
1360mii_sendbit (struct net_device *dev, u32 data)
1361{
1362 long ioaddr = dev->base_addr + PhyCtrl;
1363 data = (data) ? MII_DATA1 : 0;
1364 data |= MII_WRITE;
1365 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1366 writeb (data, ioaddr);
1367 mii_delay ();
1368 writeb (data | MII_CLK, ioaddr);
1369 mii_delay ();
1370}
1371
1372static int
1373mii_getbit (struct net_device *dev)
1374{
1375 long ioaddr = dev->base_addr + PhyCtrl;
1376 u8 data;
1377
1378 data = (readb (ioaddr) & 0xf8) | MII_READ;
1379 writeb (data, ioaddr);
1380 mii_delay ();
1381 writeb (data | MII_CLK, ioaddr);
1382 mii_delay ();
1383 return ((readb (ioaddr) >> 1) & 1);
1384}
1385
1386static void
1387mii_send_bits (struct net_device *dev, u32 data, int len)
1388{
1389 int i;
1390 for (i = len - 1; i >= 0; i--) {
1391 mii_sendbit (dev, data & (1 << i));
1392 }
1393}
1394
1395static int
1396mii_read (struct net_device *dev, int phy_addr, int reg_num)
1397{
1398 u32 cmd;
1399 int i;
1400 u32 retval = 0;
1401
1402 /* Preamble */
1403 mii_send_bits (dev, 0xffffffff, 32);
1404 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1405 /* ST,OP = 0110'b for read operation */
1406 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1407 mii_send_bits (dev, cmd, 14);
1408 /* Turnaround */
1409 if (mii_getbit (dev))
1410 goto err_out;
1411 /* Read data */
1412 for (i = 0; i < 16; i++) {
1413 retval |= mii_getbit (dev);
1414 retval <<= 1;
1415 }
1416 /* End cycle */
1417 mii_getbit (dev);
1418 return (retval >> 1) & 0xffff;
1419
1420 err_out:
1421 return 0;
1422}
1423static int
1424mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1425{
1426 u32 cmd;
1427
1428 /* Preamble */
1429 mii_send_bits (dev, 0xffffffff, 32);
1430 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1431 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1432 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1433 mii_send_bits (dev, cmd, 32);
1434 /* End cycle */
1435 mii_getbit (dev);
1436 return 0;
1437}
1438static int
1439mii_wait_link (struct net_device *dev, int wait)
1440{
96d76851 1441 __u16 bmsr;
1da177e4
LT		 1442 int phy_addr;
1443 struct netdev_private *np;
1444
1445 np = netdev_priv(dev);
1446 phy_addr = np->phy_addr;
1447
1448 do {
96d76851
AV		 1449 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1450 if (bmsr & MII_BMSR_LINK_STATUS)
1da177e4
LT		 1451 return 0;
1452 mdelay (1);
1453 } while (--wait > 0);
1454 return -1;
1455}
1456static int
1457mii_get_media (struct net_device *dev)
1458{
21b645e4 1459 __u16 negotiate;
96d76851 1460 __u16 bmsr;
5b511916
AV		 1461 __u16 mscr;
1462 __u16 mssr;
1da177e4
LT		 1463 int phy_addr;
1464 struct netdev_private *np;
1465
1466 np = netdev_priv(dev);
1467 phy_addr = np->phy_addr;
1468
96d76851 1469 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1da177e4 1470 if (np->an_enable) {
96d76851 1471 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1da177e4
LT		 1472 /* Auto-Negotiation not completed */
1473 return -1;
1474 }
21b645e4 1475 negotiate = mii_read (dev, phy_addr, MII_ANAR) &
1da177e4 1476 mii_read (dev, phy_addr, MII_ANLPAR);
5b511916
AV		 1477 mscr = mii_read (dev, phy_addr, MII_MSCR);
1478 mssr = mii_read (dev, phy_addr, MII_MSSR);
1479 if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
1da177e4
LT		 1480 np->speed = 1000;
1481 np->full_duplex = 1;
1482 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
5b511916 1483 } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
1da177e4
LT		 1484 np->speed = 1000;
1485 np->full_duplex = 0;
1486 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
21b645e4 1487 } else if (negotiate & MII_ANAR_100BX_FD) {
1da177e4
LT		 1488 np->speed = 100;
1489 np->full_duplex = 1;
1490 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
21b645e4 1491 } else if (negotiate & MII_ANAR_100BX_HD) {
1da177e4
LT		 1492 np->speed = 100;
1493 np->full_duplex = 0;
1494 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
21b645e4 1495 } else if (negotiate & MII_ANAR_10BT_FD) {
1da177e4
LT		 1496 np->speed = 10;
1497 np->full_duplex = 1;
1498 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
21b645e4 1499 } else if (negotiate & MII_ANAR_10BT_HD) {
1da177e4
LT		 1500 np->speed = 10;
1501 np->full_duplex = 0;
1502 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1503 }
21b645e4 1504 if (negotiate & MII_ANAR_PAUSE) {
1da177e4
LT		 1505 np->tx_flow &= 1;
1506 np->rx_flow &= 1;
21b645e4 1507 } else if (negotiate & MII_ANAR_ASYMMETRIC) {
1da177e4
LT		 1508 np->tx_flow = 0;
1509 np->rx_flow &= 1;
1510 }
1511 /* else tx_flow, rx_flow = user select */
1512 } else {
d50956af
AV		 1513 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1514 switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
1515 case MII_BMCR_SPEED_1000:
1516 printk (KERN_INFO "Operating at 1000 Mbps, ");
1517 break;
1518 case MII_BMCR_SPEED_100:
1da177e4 1519 printk (KERN_INFO "Operating at 100 Mbps, ");
d50956af
AV		 1520 break;
1521 case 0:
1da177e4 1522 printk (KERN_INFO "Operating at 10 Mbps, ");
1da177e4 1523 }
d50956af 1524 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1da177e4
LT		 1525 printk ("Full duplex\n");
1526 } else {
1527 printk ("Half duplex\n");
1528 }
1529 }
6aa20a22 1530 if (np->tx_flow)
1da177e4 1531 printk(KERN_INFO "Enable Tx Flow Control\n");
6aa20a22 1532 else
1da177e4
LT		 1533 printk(KERN_INFO "Disable Tx Flow Control\n");
1534 if (np->rx_flow)
1535 printk(KERN_INFO "Enable Rx Flow Control\n");
1536 else
1537 printk(KERN_INFO "Disable Rx Flow Control\n");
1538
1539 return 0;
1540}
1541
1542static int
1543mii_set_media (struct net_device *dev)
1544{
5b511916 1545 __u16 pscr;
d50956af 1546 __u16 bmcr;
96d76851 1547 __u16 bmsr;
21b645e4 1548 __u16 anar;
1da177e4
LT		 1549 int phy_addr;
1550 struct netdev_private *np;
1551 np = netdev_priv(dev);
1552 phy_addr = np->phy_addr;
1553
1554 /* Does user set speed? */
1555 if (np->an_enable) {
1556 /* Advertise capabilities */
96d76851 1557 bmsr = mii_read (dev, phy_addr, MII_BMSR);
21b645e4
AV		 1558 anar = mii_read (dev, phy_addr, MII_ANAR) &
1559 ~MII_ANAR_100BX_FD &
1560 ~MII_ANAR_100BX_HD &
1561 ~MII_ANAR_100BT4 &
1562 ~MII_ANAR_10BT_FD &
1563 ~MII_ANAR_10BT_HD;
96d76851 1564 if (bmsr & MII_BMSR_100BX_FD)
21b645e4 1565 anar |= MII_ANAR_100BX_FD;
96d76851 1566 if (bmsr & MII_BMSR_100BX_HD)
21b645e4 1567 anar |= MII_ANAR_100BX_HD;
96d76851 1568 if (bmsr & MII_BMSR_100BT4)
21b645e4 1569 anar |= MII_ANAR_100BT4;
96d76851 1570 if (bmsr & MII_BMSR_10BT_FD)
21b645e4 1571 anar |= MII_ANAR_10BT_FD;
96d76851 1572 if (bmsr & MII_BMSR_10BT_HD)
21b645e4
AV		 1573 anar |= MII_ANAR_10BT_HD;
1574 anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
1575 mii_write (dev, phy_addr, MII_ANAR, anar);
1da177e4
LT		 1576
1577 /* Enable Auto crossover */
5b511916
AV		 1578 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1579 pscr |= 3 << 5; /* 11'b */
1580 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
6aa20a22 1581
1da177e4
LT		 1582 /* Soft reset PHY */
1583 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
d50956af
AV		 1584 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
1585 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1586 mdelay(1);
1587 } else {
1588 /* Force speed setting */
1589 /* 1) Disable Auto crossover */
5b511916
AV		 1590 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1591 pscr &= ~(3 << 5);
1592 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1da177e4
LT		 1593
1594 /* 2) PHY Reset */
d50956af
AV		 1595 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1596 bmcr |= MII_BMCR_RESET;
1597 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1598
1599 /* 3) Power Down */
d50956af
AV		 1600 bmcr = 0x1940; /* must be 0x1940 */
1601 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1602 mdelay (100); /* wait a certain time */
1603
1604 /* 4) Advertise nothing */
1605 mii_write (dev, phy_addr, MII_ANAR, 0);
1606
1607 /* 5) Set media and Power Up */
d50956af 1608 bmcr = MII_BMCR_POWER_DOWN;
1da177e4 1609 if (np->speed == 100) {
d50956af 1610 bmcr |= MII_BMCR_SPEED_100;
1da177e4
LT		 1611 printk (KERN_INFO "Manual 100 Mbps, ");
1612 } else if (np->speed == 10) {
1da177e4
LT		 1613 printk (KERN_INFO "Manual 10 Mbps, ");
1614 }
1615 if (np->full_duplex) {
d50956af 1616 bmcr |= MII_BMCR_DUPLEX_MODE;
1da177e4
LT		 1617 printk ("Full duplex\n");
1618 } else {
1da177e4
LT		 1619 printk ("Half duplex\n");
1620 }
1621#if 0
1622 /* Set 1000BaseT Master/Slave setting */
5b511916
AV		 1623 mscr = mii_read (dev, phy_addr, MII_MSCR);
1624 mscr |= MII_MSCR_CFG_ENABLE;
1625 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1da177e4 1626#endif
d50956af 1627 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1628 mdelay(10);
1629 }
1630 return 0;
1631}
1632
1633static int
1634mii_get_media_pcs (struct net_device *dev)
1635{
21b645e4 1636 __u16 negotiate;
96d76851 1637 __u16 bmsr;
1da177e4
LT		 1638 int phy_addr;
1639 struct netdev_private *np;
1640
1641 np = netdev_priv(dev);
1642 phy_addr = np->phy_addr;
1643
96d76851 1644 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1da177e4 1645 if (np->an_enable) {
96d76851 1646 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1da177e4
LT		 1647 /* Auto-Negotiation not completed */
1648 return -1;
1649 }
21b645e4 1650 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1da177e4
LT		 1651 mii_read (dev, phy_addr, PCS_ANLPAR);
1652 np->speed = 1000;
21b645e4 1653 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1da177e4
LT		 1654 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1655 np->full_duplex = 1;
1656 } else {
1657 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1658 np->full_duplex = 0;
1659 }
21b645e4 1660 if (negotiate & PCS_ANAR_PAUSE) {
1da177e4
LT		 1661 np->tx_flow &= 1;
1662 np->rx_flow &= 1;
21b645e4 1663 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1da177e4
LT		 1664 np->tx_flow = 0;
1665 np->rx_flow &= 1;
1666 }
1667 /* else tx_flow, rx_flow = user select */
1668 } else {
d50956af 1669 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1da177e4 1670 printk (KERN_INFO "Operating at 1000 Mbps, ");
d50956af 1671 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1da177e4
LT		 1672 printk ("Full duplex\n");
1673 } else {
1674 printk ("Half duplex\n");
1675 }
1676 }
6aa20a22 1677 if (np->tx_flow)
1da177e4 1678 printk(KERN_INFO "Enable Tx Flow Control\n");
6aa20a22 1679 else
1da177e4
LT		 1680 printk(KERN_INFO "Disable Tx Flow Control\n");
1681 if (np->rx_flow)
1682 printk(KERN_INFO "Enable Rx Flow Control\n");
1683 else
1684 printk(KERN_INFO "Disable Rx Flow Control\n");
1685
1686 return 0;
1687}
1688
1689static int
1690mii_set_media_pcs (struct net_device *dev)
1691{
d50956af 1692 __u16 bmcr;
5b511916 1693 __u16 esr;
21b645e4 1694 __u16 anar;
1da177e4
LT		 1695 int phy_addr;
1696 struct netdev_private *np;
1697 np = netdev_priv(dev);
1698 phy_addr = np->phy_addr;
1699
1700 /* Auto-Negotiation? */
1701 if (np->an_enable) {
1702 /* Advertise capabilities */
5b511916 1703 esr = mii_read (dev, phy_addr, PCS_ESR);
21b645e4
AV		 1704 anar = mii_read (dev, phy_addr, MII_ANAR) &
1705 ~PCS_ANAR_HALF_DUPLEX &
1706 ~PCS_ANAR_FULL_DUPLEX;
5b511916 1707 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
21b645e4 1708 anar |= PCS_ANAR_HALF_DUPLEX;
5b511916 1709 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
21b645e4
AV		 1710 anar |= PCS_ANAR_FULL_DUPLEX;
1711 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1712 mii_write (dev, phy_addr, MII_ANAR, anar);
1da177e4
LT		 1713
1714 /* Soft reset PHY */
1715 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
d50956af
AV		 1716 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
1717 MII_BMCR_RESET;
1718 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1719 mdelay(1);
1720 } else {
1721 /* Force speed setting */
1722 /* PHY Reset */
d50956af
AV		 1723 bmcr = MII_BMCR_RESET;
1724 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4 1725 mdelay(10);
1da177e4 1726 if (np->full_duplex) {
d50956af 1727 bmcr = MII_BMCR_DUPLEX_MODE;
1da177e4
LT		 1728 printk (KERN_INFO "Manual full duplex\n");
1729 } else {
d50956af 1730 bmcr = 0;
1da177e4
LT		 1731 printk (KERN_INFO "Manual half duplex\n");
1732 }
d50956af 1733 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1da177e4
LT		 1734 mdelay(10);
1735
1736 /* Advertise nothing */
1737 mii_write (dev, phy_addr, MII_ANAR, 0);
1738 }
1739 return 0;
1740}
1741
1742
1743static int
1744rio_close (struct net_device *dev)
1745{
1746 long ioaddr = dev->base_addr;
1747 struct netdev_private *np = netdev_priv(dev);
1748 struct sk_buff *skb;
1749 int i;
1750
1751 netif_stop_queue (dev);
1752
1753 /* Disable interrupts */
1754 writew (0, ioaddr + IntEnable);
1755
1756 /* Stop Tx and Rx logics */
1757 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
be0976be 1758
1da177e4
LT		 1759 free_irq (dev->irq, dev);
1760 del_timer_sync (&np->timer);
6aa20a22 1761
1da177e4
LT		 1762 /* Free all the skbuffs in the queue. */
1763 for (i = 0; i < RX_RING_SIZE; i++) {
1764 np->rx_ring[i].status = 0;
1765 np->rx_ring[i].fraginfo = 0;
1766 skb = np->rx_skbuff[i];
1767 if (skb) {
6aa20a22 1768 pci_unmap_single(np->pdev,
78ce8d3d 1769 desc_to_dma(&np->rx_ring[i]),
9ee09d9c 1770 skb->len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1771 dev_kfree_skb (skb);
1772 np->rx_skbuff[i] = NULL;
1773 }
1774 }
1775 for (i = 0; i < TX_RING_SIZE; i++) {
1776 skb = np->tx_skbuff[i];
1777 if (skb) {
6aa20a22 1778 pci_unmap_single(np->pdev,
78ce8d3d 1779 desc_to_dma(&np->tx_ring[i]),
9ee09d9c 1780 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT		 1781 dev_kfree_skb (skb);
1782 np->tx_skbuff[i] = NULL;
1783 }
1784 }
1785
1786 return 0;
1787}
1788
1789static void __devexit
1790rio_remove1 (struct pci_dev *pdev)
1791{
1792 struct net_device *dev = pci_get_drvdata (pdev);
1793
1794 if (dev) {
1795 struct netdev_private *np = netdev_priv(dev);
1796
1797 unregister_netdev (dev);
1798 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1799 np->rx_ring_dma);
1800 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1801 np->tx_ring_dma);
1802#ifdef MEM_MAPPING
1803 iounmap ((char *) (dev->base_addr));
1804#endif
1805 free_netdev (dev);
1806 pci_release_regions (pdev);
1807 pci_disable_device (pdev);
1808 }
1809 pci_set_drvdata (pdev, NULL);
1810}
1811
1812static struct pci_driver rio_driver = {
1813 .name = "dl2k",
1814 .id_table = rio_pci_tbl,
1815 .probe = rio_probe1,
1816 .remove = __devexit_p(rio_remove1),
1817};
1818
1819static int __init
1820rio_init (void)
1821{
29917620 1822 return pci_register_driver(&rio_driver);
1da177e4
LT		 1823}
1824
1825static void __exit
1826rio_exit (void)
1827{
1828 pci_unregister_driver (&rio_driver);
1829}
1830
1831module_init (rio_init);
1832module_exit (rio_exit);
1833
1834/*
6aa20a22
JG		 1835
1836Compile command:
1837
1da177e4
LT		 1838gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1839
1840Read Documentation/networking/dl2k.txt for details.
1841
1842*/
1843
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