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a1365275 | 1 | /* |
41c340f0 | 2 | * Davicom DM9000 Fast Ethernet driver for Linux. |
a1365275 SH |
3 | * Copyright (C) 1997 Sten Wang |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
41c340f0 | 15 | * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
9ef9ac51 | 16 | * |
41c340f0 BD |
17 | * Additional updates, Copyright: |
18 | * Ben Dooks <ben@simtec.co.uk> | |
19 | * Sascha Hauer <s.hauer@pengutronix.de> | |
a1365275 SH |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/skbuff.h> | |
a1365275 SH |
28 | #include <linux/spinlock.h> |
29 | #include <linux/crc32.h> | |
30 | #include <linux/mii.h> | |
7da99859 | 31 | #include <linux/ethtool.h> |
a1365275 SH |
32 | #include <linux/dm9000.h> |
33 | #include <linux/delay.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
4e4fc05a | 35 | #include <linux/irq.h> |
a1365275 SH |
36 | |
37 | #include <asm/delay.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include "dm9000.h" | |
42 | ||
43 | /* Board/System/Debug information/definition ---------------- */ | |
44 | ||
45 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
46 | ||
59eae1fa BD |
47 | #define CARDNAME "dm9000" |
48 | #define DRV_VERSION "1.31" | |
a1365275 | 49 | |
f40d24d9 AL |
50 | #ifdef CONFIG_BLACKFIN |
51 | #define readsb insb | |
52 | #define readsw insw | |
53 | #define readsl insl | |
54 | #define writesb outsb | |
55 | #define writesw outsw | |
56 | #define writesl outsl | |
1a5f1c4f | 57 | #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH |
f40d24d9 | 58 | #else |
1a5f1c4f | 59 | #define DEFAULT_TRIGGER (0) |
f40d24d9 AL |
60 | #endif |
61 | ||
a1365275 SH |
62 | /* |
63 | * Transmit timeout, default 5 seconds. | |
64 | */ | |
65 | static int watchdog = 5000; | |
66 | module_param(watchdog, int, 0400); | |
67 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
68 | ||
9a2f037c BD |
69 | /* DM9000 register address locking. |
70 | * | |
71 | * The DM9000 uses an address register to control where data written | |
72 | * to the data register goes. This means that the address register | |
73 | * must be preserved over interrupts or similar calls. | |
74 | * | |
75 | * During interrupt and other critical calls, a spinlock is used to | |
76 | * protect the system, but the calls themselves save the address | |
77 | * in the address register in case they are interrupting another | |
78 | * access to the device. | |
79 | * | |
80 | * For general accesses a lock is provided so that calls which are | |
81 | * allowed to sleep are serialised so that the address register does | |
82 | * not need to be saved. This lock also serves to serialise access | |
83 | * to the EEPROM and PHY access registers which are shared between | |
84 | * these two devices. | |
85 | */ | |
86 | ||
6d406b3c BD |
87 | /* The driver supports the original DM9000E, and now the two newer |
88 | * devices, DM9000A and DM9000B. | |
89 | */ | |
90 | ||
91 | enum dm9000_type { | |
92 | TYPE_DM9000E, /* original DM9000 */ | |
93 | TYPE_DM9000A, | |
94 | TYPE_DM9000B | |
95 | }; | |
96 | ||
a1365275 SH |
97 | /* Structure/enum declaration ------------------------------- */ |
98 | typedef struct board_info { | |
99 | ||
59eae1fa BD |
100 | void __iomem *io_addr; /* Register I/O base address */ |
101 | void __iomem *io_data; /* Data I/O address */ | |
102 | u16 irq; /* IRQ */ | |
a1365275 | 103 | |
59eae1fa BD |
104 | u16 tx_pkt_cnt; |
105 | u16 queue_pkt_len; | |
106 | u16 queue_start_addr; | |
107 | u16 dbug_cnt; | |
108 | u8 io_mode; /* 0:word, 2:byte */ | |
109 | u8 phy_addr; | |
110 | u8 imr_all; | |
111 | ||
112 | unsigned int flags; | |
113 | unsigned int in_suspend :1; | |
114 | int debug_level; | |
a1365275 | 115 | |
6d406b3c | 116 | enum dm9000_type type; |
5b2b4ff0 | 117 | |
a1365275 SH |
118 | void (*inblk)(void __iomem *port, void *data, int length); |
119 | void (*outblk)(void __iomem *port, void *data, int length); | |
120 | void (*dumpblk)(void __iomem *port, int length); | |
121 | ||
a76836f9 BD |
122 | struct device *dev; /* parent device */ |
123 | ||
a1365275 SH |
124 | struct resource *addr_res; /* resources found */ |
125 | struct resource *data_res; | |
126 | struct resource *addr_req; /* resources requested */ | |
127 | struct resource *data_req; | |
128 | struct resource *irq_res; | |
129 | ||
9a2f037c BD |
130 | struct mutex addr_lock; /* phy and eeprom access lock */ |
131 | ||
8f5bf5f2 BD |
132 | struct delayed_work phy_poll; |
133 | struct net_device *ndev; | |
134 | ||
59eae1fa | 135 | spinlock_t lock; |
a1365275 SH |
136 | |
137 | struct mii_if_info mii; | |
59eae1fa | 138 | u32 msg_enable; |
a1365275 SH |
139 | } board_info_t; |
140 | ||
5b2b4ff0 BD |
141 | /* debug code */ |
142 | ||
143 | #define dm9000_dbg(db, lev, msg...) do { \ | |
144 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
145 | (lev) < db->debug_level) { \ | |
146 | dev_dbg(db->dev, msg); \ | |
147 | } \ | |
148 | } while (0) | |
149 | ||
7da99859 BD |
150 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
151 | { | |
152 | return dev->priv; | |
153 | } | |
154 | ||
a1365275 SH |
155 | /* DM9000 network board routine ---------------------------- */ |
156 | ||
157 | static void | |
158 | dm9000_reset(board_info_t * db) | |
159 | { | |
a76836f9 BD |
160 | dev_dbg(db->dev, "resetting device\n"); |
161 | ||
a1365275 SH |
162 | /* RESET device */ |
163 | writeb(DM9000_NCR, db->io_addr); | |
164 | udelay(200); | |
165 | writeb(NCR_RST, db->io_data); | |
166 | udelay(200); | |
167 | } | |
168 | ||
169 | /* | |
170 | * Read a byte from I/O port | |
171 | */ | |
172 | static u8 | |
173 | ior(board_info_t * db, int reg) | |
174 | { | |
175 | writeb(reg, db->io_addr); | |
176 | return readb(db->io_data); | |
177 | } | |
178 | ||
179 | /* | |
180 | * Write a byte to I/O port | |
181 | */ | |
182 | ||
183 | static void | |
184 | iow(board_info_t * db, int reg, int value) | |
185 | { | |
186 | writeb(reg, db->io_addr); | |
187 | writeb(value, db->io_data); | |
188 | } | |
189 | ||
190 | /* routines for sending block to chip */ | |
191 | ||
192 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
193 | { | |
194 | writesb(reg, data, count); | |
195 | } | |
196 | ||
197 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
198 | { | |
199 | writesw(reg, data, (count+1) >> 1); | |
200 | } | |
201 | ||
202 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
203 | { | |
204 | writesl(reg, data, (count+3) >> 2); | |
205 | } | |
206 | ||
207 | /* input block from chip to memory */ | |
208 | ||
209 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
210 | { | |
5f6b5517 | 211 | readsb(reg, data, count); |
a1365275 SH |
212 | } |
213 | ||
214 | ||
215 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
216 | { | |
217 | readsw(reg, data, (count+1) >> 1); | |
218 | } | |
219 | ||
220 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
221 | { | |
222 | readsl(reg, data, (count+3) >> 2); | |
223 | } | |
224 | ||
225 | /* dump block from chip to null */ | |
226 | ||
227 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
228 | { | |
229 | int i; | |
230 | int tmp; | |
231 | ||
232 | for (i = 0; i < count; i++) | |
233 | tmp = readb(reg); | |
234 | } | |
235 | ||
236 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
237 | { | |
238 | int i; | |
239 | int tmp; | |
240 | ||
241 | count = (count + 1) >> 1; | |
242 | ||
243 | for (i = 0; i < count; i++) | |
244 | tmp = readw(reg); | |
245 | } | |
246 | ||
247 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
248 | { | |
249 | int i; | |
250 | int tmp; | |
251 | ||
252 | count = (count + 3) >> 2; | |
253 | ||
254 | for (i = 0; i < count; i++) | |
255 | tmp = readl(reg); | |
256 | } | |
257 | ||
258 | /* dm9000_set_io | |
259 | * | |
260 | * select the specified set of io routines to use with the | |
261 | * device | |
262 | */ | |
263 | ||
264 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
265 | { | |
266 | /* use the size of the data resource to work out what IO | |
267 | * routines we want to use | |
268 | */ | |
269 | ||
270 | switch (byte_width) { | |
271 | case 1: | |
272 | db->dumpblk = dm9000_dumpblk_8bit; | |
273 | db->outblk = dm9000_outblk_8bit; | |
274 | db->inblk = dm9000_inblk_8bit; | |
275 | break; | |
276 | ||
a1365275 SH |
277 | |
278 | case 3: | |
a76836f9 BD |
279 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
280 | case 2: | |
a1365275 SH |
281 | db->dumpblk = dm9000_dumpblk_16bit; |
282 | db->outblk = dm9000_outblk_16bit; | |
283 | db->inblk = dm9000_inblk_16bit; | |
284 | break; | |
285 | ||
286 | case 4: | |
287 | default: | |
288 | db->dumpblk = dm9000_dumpblk_32bit; | |
289 | db->outblk = dm9000_outblk_32bit; | |
290 | db->inblk = dm9000_inblk_32bit; | |
291 | break; | |
292 | } | |
293 | } | |
294 | ||
8f5bf5f2 BD |
295 | static void dm9000_schedule_poll(board_info_t *db) |
296 | { | |
6d406b3c BD |
297 | if (db->type == TYPE_DM9000E) |
298 | schedule_delayed_work(&db->phy_poll, HZ * 2); | |
8f5bf5f2 | 299 | } |
a1365275 | 300 | |
f8d79e79 BD |
301 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
302 | { | |
303 | board_info_t *dm = to_dm9000_board(dev); | |
304 | ||
305 | if (!netif_running(dev)) | |
306 | return -EINVAL; | |
307 | ||
308 | return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); | |
309 | } | |
310 | ||
311 | static unsigned int | |
312 | dm9000_read_locked(board_info_t *db, int reg) | |
a1365275 | 313 | { |
a1365275 | 314 | unsigned long flags; |
f8d79e79 | 315 | unsigned int ret; |
a1365275 | 316 | |
f8d79e79 BD |
317 | spin_lock_irqsave(&db->lock, flags); |
318 | ret = ior(db, reg); | |
319 | spin_unlock_irqrestore(&db->lock, flags); | |
a1365275 | 320 | |
f8d79e79 BD |
321 | return ret; |
322 | } | |
a1365275 | 323 | |
f8d79e79 BD |
324 | static int dm9000_wait_eeprom(board_info_t *db) |
325 | { | |
326 | unsigned int status; | |
327 | int timeout = 8; /* wait max 8msec */ | |
328 | ||
329 | /* The DM9000 data sheets say we should be able to | |
330 | * poll the ERRE bit in EPCR to wait for the EEPROM | |
331 | * operation. From testing several chips, this bit | |
332 | * does not seem to work. | |
333 | * | |
334 | * We attempt to use the bit, but fall back to the | |
335 | * timeout (which is why we do not return an error | |
336 | * on expiry) to say that the EEPROM operation has | |
337 | * completed. | |
338 | */ | |
339 | ||
340 | while (1) { | |
341 | status = dm9000_read_locked(db, DM9000_EPCR); | |
342 | ||
343 | if ((status & EPCR_ERRE) == 0) | |
344 | break; | |
345 | ||
346 | if (timeout-- < 0) { | |
347 | dev_dbg(db->dev, "timeout waiting EEPROM\n"); | |
348 | break; | |
349 | } | |
350 | } | |
351 | ||
352 | return 0; | |
a1365275 SH |
353 | } |
354 | ||
2fd0e33f | 355 | /* |
f8d79e79 | 356 | * Read a word data from EEPROM |
2fd0e33f | 357 | */ |
f8d79e79 BD |
358 | static void |
359 | dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) | |
2fd0e33f | 360 | { |
f8d79e79 BD |
361 | unsigned long flags; |
362 | ||
363 | if (db->flags & DM9000_PLATF_NO_EEPROM) { | |
364 | to[0] = 0xff; | |
365 | to[1] = 0xff; | |
366 | return; | |
367 | } | |
368 | ||
369 | mutex_lock(&db->addr_lock); | |
370 | ||
371 | spin_lock_irqsave(&db->lock, flags); | |
372 | ||
373 | iow(db, DM9000_EPAR, offset); | |
374 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
375 | ||
376 | spin_unlock_irqrestore(&db->lock, flags); | |
377 | ||
378 | dm9000_wait_eeprom(db); | |
379 | ||
380 | /* delay for at-least 150uS */ | |
381 | msleep(1); | |
382 | ||
383 | spin_lock_irqsave(&db->lock, flags); | |
384 | ||
385 | iow(db, DM9000_EPCR, 0x0); | |
386 | ||
387 | to[0] = ior(db, DM9000_EPDRL); | |
388 | to[1] = ior(db, DM9000_EPDRH); | |
389 | ||
390 | spin_unlock_irqrestore(&db->lock, flags); | |
391 | ||
392 | mutex_unlock(&db->addr_lock); | |
2fd0e33f | 393 | } |
a1365275 | 394 | |
f8d79e79 BD |
395 | /* |
396 | * Write a word data to SROM | |
397 | */ | |
398 | static void | |
399 | dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) | |
f42d8aea | 400 | { |
f8d79e79 | 401 | unsigned long flags; |
f42d8aea | 402 | |
f8d79e79 BD |
403 | if (db->flags & DM9000_PLATF_NO_EEPROM) |
404 | return; | |
f42d8aea | 405 | |
f8d79e79 BD |
406 | mutex_lock(&db->addr_lock); |
407 | ||
408 | spin_lock_irqsave(&db->lock, flags); | |
409 | iow(db, DM9000_EPAR, offset); | |
410 | iow(db, DM9000_EPDRH, data[1]); | |
411 | iow(db, DM9000_EPDRL, data[0]); | |
412 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); | |
413 | spin_unlock_irqrestore(&db->lock, flags); | |
414 | ||
415 | dm9000_wait_eeprom(db); | |
416 | ||
417 | mdelay(1); /* wait at least 150uS to clear */ | |
418 | ||
419 | spin_lock_irqsave(&db->lock, flags); | |
420 | iow(db, DM9000_EPCR, 0); | |
421 | spin_unlock_irqrestore(&db->lock, flags); | |
422 | ||
423 | mutex_unlock(&db->addr_lock); | |
f42d8aea BD |
424 | } |
425 | ||
7da99859 BD |
426 | /* ethtool ops */ |
427 | ||
428 | static void dm9000_get_drvinfo(struct net_device *dev, | |
429 | struct ethtool_drvinfo *info) | |
430 | { | |
431 | board_info_t *dm = to_dm9000_board(dev); | |
432 | ||
433 | strcpy(info->driver, CARDNAME); | |
434 | strcpy(info->version, DRV_VERSION); | |
435 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
436 | } | |
437 | ||
e662ee02 BD |
438 | static u32 dm9000_get_msglevel(struct net_device *dev) |
439 | { | |
440 | board_info_t *dm = to_dm9000_board(dev); | |
441 | ||
442 | return dm->msg_enable; | |
443 | } | |
444 | ||
445 | static void dm9000_set_msglevel(struct net_device *dev, u32 value) | |
446 | { | |
447 | board_info_t *dm = to_dm9000_board(dev); | |
448 | ||
449 | dm->msg_enable = value; | |
450 | } | |
451 | ||
7da99859 BD |
452 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
453 | { | |
454 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 455 | |
7da99859 | 456 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
457 | return 0; |
458 | } | |
459 | ||
460 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
461 | { | |
462 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 463 | |
9a2f037c | 464 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
465 | } |
466 | ||
467 | static int dm9000_nway_reset(struct net_device *dev) | |
468 | { | |
469 | board_info_t *dm = to_dm9000_board(dev); | |
470 | return mii_nway_restart(&dm->mii); | |
471 | } | |
472 | ||
473 | static u32 dm9000_get_link(struct net_device *dev) | |
474 | { | |
475 | board_info_t *dm = to_dm9000_board(dev); | |
aa1eb452 BD |
476 | u32 ret; |
477 | ||
478 | if (dm->flags & DM9000_PLATF_EXT_PHY) | |
479 | ret = mii_link_ok(&dm->mii); | |
480 | else | |
481 | ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; | |
482 | ||
483 | return ret; | |
7da99859 BD |
484 | } |
485 | ||
29d52e54 BD |
486 | #define DM_EEPROM_MAGIC (0x444D394B) |
487 | ||
488 | static int dm9000_get_eeprom_len(struct net_device *dev) | |
489 | { | |
490 | return 128; | |
491 | } | |
492 | ||
493 | static int dm9000_get_eeprom(struct net_device *dev, | |
494 | struct ethtool_eeprom *ee, u8 *data) | |
495 | { | |
496 | board_info_t *dm = to_dm9000_board(dev); | |
497 | int offset = ee->offset; | |
498 | int len = ee->len; | |
499 | int i; | |
500 | ||
501 | /* EEPROM access is aligned to two bytes */ | |
502 | ||
503 | if ((len & 1) != 0 || (offset & 1) != 0) | |
504 | return -EINVAL; | |
505 | ||
bb44fb70 BD |
506 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
507 | return -ENOENT; | |
508 | ||
29d52e54 BD |
509 | ee->magic = DM_EEPROM_MAGIC; |
510 | ||
511 | for (i = 0; i < len; i += 2) | |
512 | dm9000_read_eeprom(dm, (offset + i) / 2, data + i); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | static int dm9000_set_eeprom(struct net_device *dev, | |
518 | struct ethtool_eeprom *ee, u8 *data) | |
519 | { | |
520 | board_info_t *dm = to_dm9000_board(dev); | |
521 | int offset = ee->offset; | |
522 | int len = ee->len; | |
523 | int i; | |
524 | ||
525 | /* EEPROM access is aligned to two bytes */ | |
526 | ||
527 | if ((len & 1) != 0 || (offset & 1) != 0) | |
528 | return -EINVAL; | |
529 | ||
bb44fb70 BD |
530 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
531 | return -ENOENT; | |
532 | ||
29d52e54 BD |
533 | if (ee->magic != DM_EEPROM_MAGIC) |
534 | return -EINVAL; | |
535 | ||
536 | for (i = 0; i < len; i += 2) | |
537 | dm9000_write_eeprom(dm, (offset + i) / 2, data + i); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
7da99859 BD |
542 | static const struct ethtool_ops dm9000_ethtool_ops = { |
543 | .get_drvinfo = dm9000_get_drvinfo, | |
544 | .get_settings = dm9000_get_settings, | |
545 | .set_settings = dm9000_set_settings, | |
e662ee02 BD |
546 | .get_msglevel = dm9000_get_msglevel, |
547 | .set_msglevel = dm9000_set_msglevel, | |
7da99859 BD |
548 | .nway_reset = dm9000_nway_reset, |
549 | .get_link = dm9000_get_link, | |
29d52e54 BD |
550 | .get_eeprom_len = dm9000_get_eeprom_len, |
551 | .get_eeprom = dm9000_get_eeprom, | |
552 | .set_eeprom = dm9000_set_eeprom, | |
7da99859 BD |
553 | }; |
554 | ||
f8dd0ecb BD |
555 | static void dm9000_show_carrier(board_info_t *db, |
556 | unsigned carrier, unsigned nsr) | |
557 | { | |
558 | struct net_device *ndev = db->ndev; | |
559 | unsigned ncr = dm9000_read_locked(db, DM9000_NCR); | |
560 | ||
561 | if (carrier) | |
562 | dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n", | |
563 | ndev->name, (nsr & NSR_SPEED) ? 10 : 100, | |
564 | (ncr & NCR_FDX) ? "full" : "half"); | |
565 | else | |
566 | dev_info(db->dev, "%s: link down\n", ndev->name); | |
567 | } | |
568 | ||
8f5bf5f2 BD |
569 | static void |
570 | dm9000_poll_work(struct work_struct *w) | |
571 | { | |
572 | struct delayed_work *dw = container_of(w, struct delayed_work, work); | |
573 | board_info_t *db = container_of(dw, board_info_t, phy_poll); | |
f8dd0ecb BD |
574 | struct net_device *ndev = db->ndev; |
575 | ||
576 | if (db->flags & DM9000_PLATF_SIMPLE_PHY && | |
577 | !(db->flags & DM9000_PLATF_EXT_PHY)) { | |
578 | unsigned nsr = dm9000_read_locked(db, DM9000_NSR); | |
579 | unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0; | |
580 | unsigned new_carrier; | |
8f5bf5f2 | 581 | |
f8dd0ecb BD |
582 | new_carrier = (nsr & NSR_LINKST) ? 1 : 0; |
583 | ||
584 | if (old_carrier != new_carrier) { | |
585 | if (netif_msg_link(db)) | |
586 | dm9000_show_carrier(db, new_carrier, nsr); | |
587 | ||
588 | if (!new_carrier) | |
589 | netif_carrier_off(ndev); | |
590 | else | |
591 | netif_carrier_on(ndev); | |
592 | } | |
593 | } else | |
594 | mii_check_media(&db->mii, netif_msg_link(db), 0); | |
8f5bf5f2 | 595 | |
f8dd0ecb | 596 | if (netif_running(ndev)) |
8f5bf5f2 BD |
597 | dm9000_schedule_poll(db); |
598 | } | |
7da99859 | 599 | |
a1365275 SH |
600 | /* dm9000_release_board |
601 | * | |
602 | * release a board, and any mapped resources | |
603 | */ | |
604 | ||
605 | static void | |
606 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
607 | { | |
a1365275 SH |
608 | /* unmap our resources */ |
609 | ||
610 | iounmap(db->io_addr); | |
611 | iounmap(db->io_data); | |
612 | ||
613 | /* release the resources */ | |
614 | ||
9088fa4f BD |
615 | release_resource(db->data_req); |
616 | kfree(db->data_req); | |
a1365275 | 617 | |
9088fa4f BD |
618 | release_resource(db->addr_req); |
619 | kfree(db->addr_req); | |
a1365275 SH |
620 | } |
621 | ||
6d406b3c BD |
622 | static unsigned char dm9000_type_to_char(enum dm9000_type type) |
623 | { | |
624 | switch (type) { | |
625 | case TYPE_DM9000E: return 'e'; | |
626 | case TYPE_DM9000A: return 'a'; | |
627 | case TYPE_DM9000B: return 'b'; | |
628 | } | |
629 | ||
630 | return '?'; | |
631 | } | |
632 | ||
a1365275 | 633 | /* |
f8d79e79 | 634 | * Set DM9000 multicast address |
a1365275 | 635 | */ |
f8d79e79 BD |
636 | static void |
637 | dm9000_hash_table(struct net_device *dev) | |
a1365275 | 638 | { |
f8d79e79 BD |
639 | board_info_t *db = (board_info_t *) dev->priv; |
640 | struct dev_mc_list *mcptr = dev->mc_list; | |
641 | int mc_cnt = dev->mc_count; | |
642 | int i, oft; | |
643 | u32 hash_val; | |
644 | u16 hash_table[4]; | |
645 | u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; | |
646 | unsigned long flags; | |
a1365275 | 647 | |
f8d79e79 | 648 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 649 | |
f8d79e79 | 650 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 651 | |
f8d79e79 BD |
652 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
653 | iow(db, oft, dev->dev_addr[i]); | |
a1365275 | 654 | |
f8d79e79 BD |
655 | /* Clear Hash Table */ |
656 | for (i = 0; i < 4; i++) | |
657 | hash_table[i] = 0x0; | |
a76836f9 | 658 | |
f8d79e79 BD |
659 | /* broadcast address */ |
660 | hash_table[3] = 0x8000; | |
9ef9ac51 | 661 | |
f8d79e79 BD |
662 | if (dev->flags & IFF_PROMISC) |
663 | rcr |= RCR_PRMSC; | |
8f5bf5f2 | 664 | |
f8d79e79 BD |
665 | if (dev->flags & IFF_ALLMULTI) |
666 | rcr |= RCR_ALL; | |
08c3f57c | 667 | |
f8d79e79 BD |
668 | /* the multicast address in Hash Table : 64 bits */ |
669 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
670 | hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; | |
671 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); | |
08c3f57c LP |
672 | } |
673 | ||
f8d79e79 BD |
674 | /* Write the hash table to MAC MD table */ |
675 | for (i = 0, oft = DM9000_MAR; i < 4; i++) { | |
676 | iow(db, oft++, hash_table[i]); | |
677 | iow(db, oft++, hash_table[i] >> 8); | |
08c3f57c LP |
678 | } |
679 | ||
f8d79e79 BD |
680 | iow(db, DM9000_RCR, rcr); |
681 | spin_unlock_irqrestore(&db->lock, flags); | |
682 | } | |
08c3f57c | 683 | |
f8d79e79 BD |
684 | /* |
685 | * Initilize dm9000 board | |
686 | */ | |
687 | static void | |
688 | dm9000_init_dm9000(struct net_device *dev) | |
689 | { | |
690 | board_info_t *db = dev->priv; | |
691 | unsigned int imr; | |
08c3f57c | 692 | |
f8d79e79 | 693 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
08c3f57c | 694 | |
f8d79e79 BD |
695 | /* I/O mode */ |
696 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
08c3f57c | 697 | |
f8d79e79 BD |
698 | /* GPIO0 on pre-activate PHY */ |
699 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
700 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
701 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
08c3f57c | 702 | |
f8d79e79 BD |
703 | if (db->flags & DM9000_PLATF_EXT_PHY) |
704 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
33ba5091 | 705 | |
a1365275 SH |
706 | /* Program operating register */ |
707 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
708 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
709 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
710 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
711 | /* clear TX status */ | |
712 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
713 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
714 | ||
715 | /* Set address filter table */ | |
716 | dm9000_hash_table(dev); | |
717 | ||
6d406b3c BD |
718 | imr = IMR_PAR | IMR_PTM | IMR_PRM; |
719 | if (db->type != TYPE_DM9000E) | |
720 | imr |= IMR_LNKCHNG; | |
721 | ||
722 | db->imr_all = imr; | |
723 | ||
a1365275 | 724 | /* Enable TX/RX interrupt mask */ |
6d406b3c | 725 | iow(db, DM9000_IMR, imr); |
a1365275 SH |
726 | |
727 | /* Init Driver variable */ | |
728 | db->tx_pkt_cnt = 0; | |
729 | db->queue_pkt_len = 0; | |
730 | dev->trans_start = 0; | |
a1365275 SH |
731 | } |
732 | ||
f8d79e79 BD |
733 | /* Our watchdog timed out. Called by the networking layer */ |
734 | static void dm9000_timeout(struct net_device *dev) | |
735 | { | |
736 | board_info_t *db = (board_info_t *) dev->priv; | |
737 | u8 reg_save; | |
738 | unsigned long flags; | |
739 | ||
740 | /* Save previous register address */ | |
741 | reg_save = readb(db->io_addr); | |
742 | spin_lock_irqsave(&db->lock, flags); | |
743 | ||
744 | netif_stop_queue(dev); | |
745 | dm9000_reset(db); | |
746 | dm9000_init_dm9000(dev); | |
747 | /* We can accept TX packets again */ | |
748 | dev->trans_start = jiffies; | |
749 | netif_wake_queue(dev); | |
750 | ||
751 | /* Restore previous register address */ | |
752 | writeb(reg_save, db->io_addr); | |
753 | spin_unlock_irqrestore(&db->lock, flags); | |
754 | } | |
755 | ||
a1365275 SH |
756 | /* |
757 | * Hardware start transmission. | |
758 | * Send a packet to media from the upper layer. | |
759 | */ | |
760 | static int | |
761 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
762 | { | |
c46ac946 | 763 | unsigned long flags; |
59eae1fa | 764 | board_info_t *db = dev->priv; |
a1365275 | 765 | |
5b2b4ff0 | 766 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
767 | |
768 | if (db->tx_pkt_cnt > 1) | |
769 | return 1; | |
770 | ||
c46ac946 | 771 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
772 | |
773 | /* Move data to DM9000 TX RAM */ | |
774 | writeb(DM9000_MWCMD, db->io_addr); | |
775 | ||
776 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 777 | dev->stats.tx_bytes += skb->len; |
a1365275 | 778 | |
c46ac946 | 779 | db->tx_pkt_cnt++; |
a1365275 | 780 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 781 | if (db->tx_pkt_cnt == 1) { |
a1365275 | 782 | /* Set TX length to DM9000 */ |
073d3f46 BD |
783 | iow(db, DM9000_TXPLL, skb->len); |
784 | iow(db, DM9000_TXPLH, skb->len >> 8); | |
a1365275 SH |
785 | |
786 | /* Issue TX polling command */ | |
787 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
788 | ||
789 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
790 | } else { |
791 | /* Second packet */ | |
a1365275 | 792 | db->queue_pkt_len = skb->len; |
c46ac946 | 793 | netif_stop_queue(dev); |
a1365275 SH |
794 | } |
795 | ||
c46ac946 FW |
796 | spin_unlock_irqrestore(&db->lock, flags); |
797 | ||
a1365275 SH |
798 | /* free this SKB */ |
799 | dev_kfree_skb(skb); | |
800 | ||
a1365275 SH |
801 | return 0; |
802 | } | |
803 | ||
a1365275 | 804 | /* |
f8d79e79 BD |
805 | * DM9000 interrupt handler |
806 | * receive the packet to upper layer, free the transmitted packet | |
a1365275 | 807 | */ |
f8d79e79 BD |
808 | |
809 | static void dm9000_tx_done(struct net_device *dev, board_info_t *db) | |
a1365275 | 810 | { |
f8d79e79 | 811 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ |
a1365275 | 812 | |
f8d79e79 BD |
813 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { |
814 | /* One packet sent complete */ | |
815 | db->tx_pkt_cnt--; | |
816 | dev->stats.tx_packets++; | |
a1365275 | 817 | |
f8d79e79 BD |
818 | if (netif_msg_tx_done(db)) |
819 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
c991d168 | 820 | |
a1365275 SH |
821 | /* Queue packet check & send */ |
822 | if (db->tx_pkt_cnt > 0) { | |
073d3f46 BD |
823 | iow(db, DM9000_TXPLL, db->queue_pkt_len); |
824 | iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); | |
a1365275 SH |
825 | iow(db, DM9000_TCR, TCR_TXREQ); |
826 | dev->trans_start = jiffies; | |
827 | } | |
828 | netif_wake_queue(dev); | |
829 | } | |
830 | } | |
831 | ||
a1365275 | 832 | struct dm9000_rxhdr { |
93116573 BD |
833 | u8 RxPktReady; |
834 | u8 RxStatus; | |
8b9fc8ae | 835 | __le16 RxLen; |
a1365275 SH |
836 | } __attribute__((__packed__)); |
837 | ||
838 | /* | |
839 | * Received a packet and pass to upper layer | |
840 | */ | |
841 | static void | |
842 | dm9000_rx(struct net_device *dev) | |
843 | { | |
844 | board_info_t *db = (board_info_t *) dev->priv; | |
845 | struct dm9000_rxhdr rxhdr; | |
846 | struct sk_buff *skb; | |
847 | u8 rxbyte, *rdptr; | |
6478fac6 | 848 | bool GoodPacket; |
a1365275 SH |
849 | int RxLen; |
850 | ||
851 | /* Check packet ready or not */ | |
852 | do { | |
853 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
854 | ||
855 | /* Get most updated data */ | |
856 | rxbyte = readb(db->io_data); | |
857 | ||
858 | /* Status check: this byte must be 0 or 1 */ | |
859 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 860 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
861 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
862 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
863 | return; | |
864 | } | |
865 | ||
866 | if (rxbyte != DM9000_PKT_RDY) | |
867 | return; | |
868 | ||
869 | /* A packet ready now & Get status/length */ | |
6478fac6 | 870 | GoodPacket = true; |
a1365275 SH |
871 | writeb(DM9000_MRCMD, db->io_addr); |
872 | ||
873 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
874 | ||
93116573 | 875 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 | 876 | |
c991d168 BD |
877 | if (netif_msg_rx_status(db)) |
878 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
879 | rxhdr.RxStatus, RxLen); | |
880 | ||
a1365275 SH |
881 | /* Packet Status check */ |
882 | if (RxLen < 0x40) { | |
6478fac6 | 883 | GoodPacket = false; |
c991d168 BD |
884 | if (netif_msg_rx_err(db)) |
885 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
a1365275 SH |
886 | } |
887 | ||
888 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 889 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
890 | } |
891 | ||
93116573 | 892 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 893 | GoodPacket = false; |
93116573 | 894 | if (rxhdr.RxStatus & 0x01) { |
c991d168 BD |
895 | if (netif_msg_rx_err(db)) |
896 | dev_dbg(db->dev, "fifo error\n"); | |
09f75cd7 | 897 | dev->stats.rx_fifo_errors++; |
a1365275 | 898 | } |
93116573 | 899 | if (rxhdr.RxStatus & 0x02) { |
c991d168 BD |
900 | if (netif_msg_rx_err(db)) |
901 | dev_dbg(db->dev, "crc error\n"); | |
09f75cd7 | 902 | dev->stats.rx_crc_errors++; |
a1365275 | 903 | } |
93116573 | 904 | if (rxhdr.RxStatus & 0x80) { |
c991d168 BD |
905 | if (netif_msg_rx_err(db)) |
906 | dev_dbg(db->dev, "length error\n"); | |
09f75cd7 | 907 | dev->stats.rx_length_errors++; |
a1365275 SH |
908 | } |
909 | } | |
910 | ||
911 | /* Move data from DM9000 */ | |
912 | if (GoodPacket | |
913 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
914 | skb_reserve(skb, 2); |
915 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
916 | ||
917 | /* Read received packet from RX SRAM */ | |
918 | ||
919 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 920 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
921 | |
922 | /* Pass to upper layer */ | |
923 | skb->protocol = eth_type_trans(skb, dev); | |
924 | netif_rx(skb); | |
09f75cd7 | 925 | dev->stats.rx_packets++; |
a1365275 SH |
926 | |
927 | } else { | |
928 | /* need to dump the packet's data */ | |
929 | ||
930 | (db->dumpblk)(db->io_data, RxLen); | |
931 | } | |
932 | } while (rxbyte == DM9000_PKT_RDY); | |
933 | } | |
934 | ||
f8d79e79 | 935 | static irqreturn_t dm9000_interrupt(int irq, void *dev_id) |
39c341a8 | 936 | { |
f8d79e79 BD |
937 | struct net_device *dev = dev_id; |
938 | board_info_t *db = dev->priv; | |
939 | int int_status; | |
940 | u8 reg_save; | |
39c341a8 | 941 | |
f8d79e79 | 942 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
39c341a8 | 943 | |
f8d79e79 | 944 | /* A real interrupt coming */ |
39c341a8 | 945 | |
f8d79e79 | 946 | spin_lock(&db->lock); |
39c341a8 | 947 | |
f8d79e79 BD |
948 | /* Save previous register address */ |
949 | reg_save = readb(db->io_addr); | |
39c341a8 | 950 | |
f8d79e79 BD |
951 | /* Disable all interrupts */ |
952 | iow(db, DM9000_IMR, IMR_PAR); | |
39c341a8 | 953 | |
f8d79e79 BD |
954 | /* Got DM9000 interrupt status */ |
955 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
956 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
39c341a8 | 957 | |
f8d79e79 BD |
958 | if (netif_msg_intr(db)) |
959 | dev_dbg(db->dev, "interrupt status %02x\n", int_status); | |
960 | ||
961 | /* Received the coming packet */ | |
962 | if (int_status & ISR_PRS) | |
963 | dm9000_rx(dev); | |
964 | ||
965 | /* Trnasmit Interrupt check */ | |
966 | if (int_status & ISR_PTS) | |
967 | dm9000_tx_done(dev, db); | |
968 | ||
969 | if (db->type != TYPE_DM9000E) { | |
970 | if (int_status & ISR_LNKCHNG) { | |
971 | /* fire a link-change request */ | |
972 | schedule_delayed_work(&db->phy_poll, 1); | |
39c341a8 BD |
973 | } |
974 | } | |
975 | ||
f8d79e79 BD |
976 | /* Re-enable interrupt mask */ |
977 | iow(db, DM9000_IMR, db->imr_all); | |
978 | ||
979 | /* Restore previous register address */ | |
980 | writeb(reg_save, db->io_addr); | |
981 | ||
982 | spin_unlock(&db->lock); | |
983 | ||
984 | return IRQ_HANDLED; | |
39c341a8 BD |
985 | } |
986 | ||
f8d79e79 | 987 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a1365275 | 988 | /* |
f8d79e79 | 989 | *Used by netconsole |
a1365275 | 990 | */ |
f8d79e79 | 991 | static void dm9000_poll_controller(struct net_device *dev) |
a1365275 | 992 | { |
f8d79e79 BD |
993 | disable_irq(dev->irq); |
994 | dm9000_interrupt(dev->irq, dev); | |
995 | enable_irq(dev->irq); | |
996 | } | |
997 | #endif | |
9a2f037c | 998 | |
f8d79e79 BD |
999 | /* |
1000 | * Open the interface. | |
1001 | * The interface is opened whenever "ifconfig" actives it. | |
1002 | */ | |
1003 | static int | |
1004 | dm9000_open(struct net_device *dev) | |
1005 | { | |
1006 | board_info_t *db = dev->priv; | |
1007 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; | |
621ddcb0 | 1008 | |
f8d79e79 BD |
1009 | if (netif_msg_ifup(db)) |
1010 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
621ddcb0 | 1011 | |
f8d79e79 BD |
1012 | /* If there is no IRQ type specified, default to something that |
1013 | * may work, and tell the user that this is a problem */ | |
621ddcb0 | 1014 | |
f8d79e79 BD |
1015 | if (irqflags == IRQF_TRIGGER_NONE) { |
1016 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); | |
1017 | irqflags = DEFAULT_TRIGGER; | |
1018 | } | |
1019 | ||
1020 | irqflags |= IRQF_SHARED; | |
39c341a8 | 1021 | |
f8d79e79 BD |
1022 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) |
1023 | return -EAGAIN; | |
621ddcb0 | 1024 | |
f8d79e79 BD |
1025 | /* Initialize DM9000 board */ |
1026 | dm9000_reset(db); | |
1027 | dm9000_init_dm9000(dev); | |
621ddcb0 | 1028 | |
f8d79e79 BD |
1029 | /* Init driver variable */ |
1030 | db->dbug_cnt = 0; | |
86c62fab | 1031 | |
f8d79e79 BD |
1032 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
1033 | netif_start_queue(dev); | |
1034 | ||
1035 | dm9000_schedule_poll(db); | |
9a2f037c | 1036 | |
f8d79e79 BD |
1037 | return 0; |
1038 | } | |
621ddcb0 | 1039 | |
f8d79e79 BD |
1040 | /* |
1041 | * Sleep, either by using msleep() or if we are suspending, then | |
1042 | * use mdelay() to sleep. | |
1043 | */ | |
1044 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1045 | { | |
1046 | if (db->in_suspend) | |
1047 | mdelay(ms); | |
1048 | else | |
1049 | msleep(ms); | |
a1365275 SH |
1050 | } |
1051 | ||
a1365275 | 1052 | /* |
f8d79e79 | 1053 | * Read a word from phyxcer |
a1365275 | 1054 | */ |
f8d79e79 BD |
1055 | static int |
1056 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
a1365275 | 1057 | { |
f8d79e79 | 1058 | board_info_t *db = (board_info_t *) dev->priv; |
621ddcb0 | 1059 | unsigned long flags; |
f8d79e79 BD |
1060 | unsigned int reg_save; |
1061 | int ret; | |
bb44fb70 | 1062 | |
9a2f037c BD |
1063 | mutex_lock(&db->addr_lock); |
1064 | ||
f8d79e79 | 1065 | spin_lock_irqsave(&db->lock,flags); |
621ddcb0 | 1066 | |
f8d79e79 BD |
1067 | /* Save previous register address */ |
1068 | reg_save = readb(db->io_addr); | |
39c341a8 | 1069 | |
f8d79e79 BD |
1070 | /* Fill the phyxcer register into REG_0C */ |
1071 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
621ddcb0 | 1072 | |
f8d79e79 | 1073 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ |
9a2f037c | 1074 | |
f8d79e79 BD |
1075 | writeb(reg_save, db->io_addr); |
1076 | spin_unlock_irqrestore(&db->lock,flags); | |
89c8b0e6 | 1077 | |
321f69a4 | 1078 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1079 | |
1080 | spin_lock_irqsave(&db->lock,flags); | |
1081 | reg_save = readb(db->io_addr); | |
1082 | ||
a1365275 SH |
1083 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1084 | ||
1085 | /* The read data keeps on REG_0D & REG_0E */ | |
1086 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1087 | ||
9ef9ac51 BD |
1088 | /* restore the previous address */ |
1089 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1090 | spin_unlock_irqrestore(&db->lock,flags); |
1091 | ||
9a2f037c | 1092 | mutex_unlock(&db->addr_lock); |
37d5dca6 ES |
1093 | |
1094 | dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); | |
a1365275 SH |
1095 | return ret; |
1096 | } | |
1097 | ||
1098 | /* | |
1099 | * Write a word to phyxcer | |
1100 | */ | |
1101 | static void | |
59eae1fa BD |
1102 | dm9000_phy_write(struct net_device *dev, |
1103 | int phyaddr_unused, int reg, int value) | |
a1365275 SH |
1104 | { |
1105 | board_info_t *db = (board_info_t *) dev->priv; | |
1106 | unsigned long flags; | |
9ef9ac51 | 1107 | unsigned long reg_save; |
a1365275 | 1108 | |
37d5dca6 | 1109 | dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); |
9a2f037c BD |
1110 | mutex_lock(&db->addr_lock); |
1111 | ||
a1365275 SH |
1112 | spin_lock_irqsave(&db->lock,flags); |
1113 | ||
9ef9ac51 BD |
1114 | /* Save previous register address */ |
1115 | reg_save = readb(db->io_addr); | |
1116 | ||
a1365275 SH |
1117 | /* Fill the phyxcer register into REG_0C */ |
1118 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1119 | ||
1120 | /* Fill the written data into REG_0D & REG_0E */ | |
073d3f46 BD |
1121 | iow(db, DM9000_EPDRL, value); |
1122 | iow(db, DM9000_EPDRH, value >> 8); | |
a1365275 SH |
1123 | |
1124 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1125 | |
1126 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1127 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1128 | |
321f69a4 | 1129 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1130 | |
1131 | spin_lock_irqsave(&db->lock,flags); | |
1132 | reg_save = readb(db->io_addr); | |
1133 | ||
a1365275 SH |
1134 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1135 | ||
9ef9ac51 BD |
1136 | /* restore the previous address */ |
1137 | writeb(reg_save, db->io_addr); | |
1138 | ||
9a2f037c BD |
1139 | spin_unlock_irqrestore(&db->lock, flags); |
1140 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1141 | } |
1142 | ||
f8d79e79 BD |
1143 | static void |
1144 | dm9000_shutdown(struct net_device *dev) | |
1145 | { | |
1146 | board_info_t *db = dev->priv; | |
1147 | ||
1148 | /* RESET device */ | |
1149 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
1150 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
1151 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
1152 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
1153 | } | |
1154 | ||
1155 | /* | |
1156 | * Stop the interface. | |
1157 | * The interface is stopped when it is brought. | |
1158 | */ | |
1159 | static int | |
1160 | dm9000_stop(struct net_device *ndev) | |
1161 | { | |
1162 | board_info_t *db = ndev->priv; | |
1163 | ||
1164 | if (netif_msg_ifdown(db)) | |
1165 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
1166 | ||
1167 | cancel_delayed_work_sync(&db->phy_poll); | |
1168 | ||
1169 | netif_stop_queue(ndev); | |
1170 | netif_carrier_off(ndev); | |
1171 | ||
1172 | /* free interrupt */ | |
1173 | free_irq(ndev->irq, ndev); | |
1174 | ||
1175 | dm9000_shutdown(ndev); | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
1180 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
1181 | ||
1182 | /* | |
1183 | * Search DM9000 board, allocate space and register it | |
1184 | */ | |
1185 | static int __devinit | |
1186 | dm9000_probe(struct platform_device *pdev) | |
1187 | { | |
1188 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; | |
1189 | struct board_info *db; /* Point a board information structure */ | |
1190 | struct net_device *ndev; | |
1191 | const unsigned char *mac_src; | |
1192 | int ret = 0; | |
1193 | int iosize; | |
1194 | int i; | |
1195 | u32 id_val; | |
1196 | ||
1197 | /* Init network device */ | |
1198 | ndev = alloc_etherdev(sizeof(struct board_info)); | |
1199 | if (!ndev) { | |
1200 | dev_err(&pdev->dev, "could not allocate device.\n"); | |
1201 | return -ENOMEM; | |
1202 | } | |
1203 | ||
1204 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1205 | ||
1206 | dev_dbg(&pdev->dev, "dm9000_probe()\n"); | |
1207 | ||
1208 | /* setup board info structure */ | |
1209 | db = ndev->priv; | |
1210 | memset(db, 0, sizeof(*db)); | |
1211 | ||
1212 | db->dev = &pdev->dev; | |
1213 | db->ndev = ndev; | |
1214 | ||
1215 | spin_lock_init(&db->lock); | |
1216 | mutex_init(&db->addr_lock); | |
1217 | ||
1218 | INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); | |
1219 | ||
1220 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1221 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1222 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1223 | ||
1224 | if (db->addr_res == NULL || db->data_res == NULL || | |
1225 | db->irq_res == NULL) { | |
1226 | dev_err(db->dev, "insufficient resources\n"); | |
1227 | ret = -ENOENT; | |
1228 | goto out; | |
1229 | } | |
1230 | ||
1231 | iosize = res_size(db->addr_res); | |
1232 | db->addr_req = request_mem_region(db->addr_res->start, iosize, | |
1233 | pdev->name); | |
1234 | ||
1235 | if (db->addr_req == NULL) { | |
1236 | dev_err(db->dev, "cannot claim address reg area\n"); | |
1237 | ret = -EIO; | |
1238 | goto out; | |
1239 | } | |
1240 | ||
1241 | db->io_addr = ioremap(db->addr_res->start, iosize); | |
1242 | ||
1243 | if (db->io_addr == NULL) { | |
1244 | dev_err(db->dev, "failed to ioremap address reg\n"); | |
1245 | ret = -EINVAL; | |
1246 | goto out; | |
1247 | } | |
1248 | ||
1249 | iosize = res_size(db->data_res); | |
1250 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
1251 | pdev->name); | |
1252 | ||
1253 | if (db->data_req == NULL) { | |
1254 | dev_err(db->dev, "cannot claim data reg area\n"); | |
1255 | ret = -EIO; | |
1256 | goto out; | |
1257 | } | |
1258 | ||
1259 | db->io_data = ioremap(db->data_res->start, iosize); | |
1260 | ||
1261 | if (db->io_data == NULL) { | |
1262 | dev_err(db->dev, "failed to ioremap data reg\n"); | |
1263 | ret = -EINVAL; | |
1264 | goto out; | |
1265 | } | |
1266 | ||
1267 | /* fill in parameters for net-dev structure */ | |
1268 | ndev->base_addr = (unsigned long)db->io_addr; | |
1269 | ndev->irq = db->irq_res->start; | |
1270 | ||
1271 | /* ensure at least we have a default set of IO routines */ | |
1272 | dm9000_set_io(db, iosize); | |
1273 | ||
1274 | /* check to see if anything is being over-ridden */ | |
1275 | if (pdata != NULL) { | |
1276 | /* check to see if the driver wants to over-ride the | |
1277 | * default IO width */ | |
1278 | ||
1279 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
1280 | dm9000_set_io(db, 1); | |
1281 | ||
1282 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
1283 | dm9000_set_io(db, 2); | |
1284 | ||
1285 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
1286 | dm9000_set_io(db, 4); | |
1287 | ||
1288 | /* check to see if there are any IO routine | |
1289 | * over-rides */ | |
1290 | ||
1291 | if (pdata->inblk != NULL) | |
1292 | db->inblk = pdata->inblk; | |
1293 | ||
1294 | if (pdata->outblk != NULL) | |
1295 | db->outblk = pdata->outblk; | |
1296 | ||
1297 | if (pdata->dumpblk != NULL) | |
1298 | db->dumpblk = pdata->dumpblk; | |
1299 | ||
1300 | db->flags = pdata->flags; | |
1301 | } | |
1302 | ||
f8dd0ecb BD |
1303 | #ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL |
1304 | db->flags |= DM9000_PLATF_SIMPLE_PHY; | |
1305 | #endif | |
1306 | ||
f8d79e79 BD |
1307 | dm9000_reset(db); |
1308 | ||
1309 | /* try multiple times, DM9000 sometimes gets the read wrong */ | |
1310 | for (i = 0; i < 8; i++) { | |
1311 | id_val = ior(db, DM9000_VIDL); | |
1312 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
1313 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
1314 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
1315 | ||
1316 | if (id_val == DM9000_ID) | |
1317 | break; | |
1318 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); | |
1319 | } | |
1320 | ||
1321 | if (id_val != DM9000_ID) { | |
1322 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); | |
1323 | ret = -ENODEV; | |
1324 | goto out; | |
1325 | } | |
1326 | ||
1327 | /* Identify what type of DM9000 we are working on */ | |
1328 | ||
1329 | id_val = ior(db, DM9000_CHIPR); | |
1330 | dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); | |
1331 | ||
1332 | switch (id_val) { | |
1333 | case CHIPR_DM9000A: | |
1334 | db->type = TYPE_DM9000A; | |
1335 | break; | |
1336 | case CHIPR_DM9000B: | |
1337 | db->type = TYPE_DM9000B; | |
1338 | break; | |
1339 | default: | |
1340 | dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); | |
1341 | db->type = TYPE_DM9000E; | |
1342 | } | |
1343 | ||
1344 | /* from this point we assume that we have found a DM9000 */ | |
1345 | ||
1346 | /* driver system function */ | |
1347 | ether_setup(ndev); | |
1348 | ||
1349 | ndev->open = &dm9000_open; | |
1350 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
1351 | ndev->tx_timeout = &dm9000_timeout; | |
1352 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
1353 | ndev->stop = &dm9000_stop; | |
1354 | ndev->set_multicast_list = &dm9000_hash_table; | |
1355 | ndev->ethtool_ops = &dm9000_ethtool_ops; | |
1356 | ndev->do_ioctl = &dm9000_ioctl; | |
1357 | ||
1358 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1359 | ndev->poll_controller = &dm9000_poll_controller; | |
1360 | #endif | |
1361 | ||
1362 | db->msg_enable = NETIF_MSG_LINK; | |
1363 | db->mii.phy_id_mask = 0x1f; | |
1364 | db->mii.reg_num_mask = 0x1f; | |
1365 | db->mii.force_media = 0; | |
1366 | db->mii.full_duplex = 0; | |
1367 | db->mii.dev = ndev; | |
1368 | db->mii.mdio_read = dm9000_phy_read; | |
1369 | db->mii.mdio_write = dm9000_phy_write; | |
1370 | ||
1371 | mac_src = "eeprom"; | |
1372 | ||
1373 | /* try reading the node address from the attached EEPROM */ | |
1374 | for (i = 0; i < 6; i += 2) | |
1375 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
1376 | ||
1377 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
1378 | /* try reading from mac */ | |
1379 | ||
1380 | mac_src = "chip"; | |
1381 | for (i = 0; i < 6; i++) | |
1382 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
1383 | } | |
1384 | ||
1385 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1386 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " | |
1387 | "set using ifconfig\n", ndev->name); | |
1388 | ||
1389 | platform_set_drvdata(pdev, ndev); | |
1390 | ret = register_netdev(ndev); | |
1391 | ||
1392 | if (ret == 0) { | |
1393 | DECLARE_MAC_BUF(mac); | |
1394 | printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n", | |
1395 | ndev->name, dm9000_type_to_char(db->type), | |
1396 | db->io_addr, db->io_data, ndev->irq, | |
1397 | print_mac(mac, ndev->dev_addr), mac_src); | |
1398 | } | |
1399 | return 0; | |
1400 | ||
1401 | out: | |
1402 | dev_err(db->dev, "not found (%d).\n", ret); | |
1403 | ||
1404 | dm9000_release_board(pdev, db); | |
1405 | free_netdev(ndev); | |
1406 | ||
1407 | return ret; | |
1408 | } | |
1409 | ||
a1365275 | 1410 | static int |
3ae5eaec | 1411 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1412 | { |
3ae5eaec | 1413 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1414 | board_info_t *db; |
a1365275 | 1415 | |
9480e307 | 1416 | if (ndev) { |
321f69a4 BD |
1417 | db = (board_info_t *) ndev->priv; |
1418 | db->in_suspend = 1; | |
1419 | ||
a1365275 SH |
1420 | if (netif_running(ndev)) { |
1421 | netif_device_detach(ndev); | |
1422 | dm9000_shutdown(ndev); | |
1423 | } | |
1424 | } | |
1425 | return 0; | |
1426 | } | |
1427 | ||
1428 | static int | |
3ae5eaec | 1429 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1430 | { |
3ae5eaec | 1431 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1432 | board_info_t *db = (board_info_t *) ndev->priv; |
1433 | ||
9480e307 | 1434 | if (ndev) { |
a1365275 SH |
1435 | |
1436 | if (netif_running(ndev)) { | |
1437 | dm9000_reset(db); | |
1438 | dm9000_init_dm9000(ndev); | |
1439 | ||
1440 | netif_device_attach(ndev); | |
1441 | } | |
321f69a4 BD |
1442 | |
1443 | db->in_suspend = 0; | |
a1365275 SH |
1444 | } |
1445 | return 0; | |
1446 | } | |
1447 | ||
e21fd4f0 | 1448 | static int __devexit |
3ae5eaec | 1449 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1450 | { |
3ae5eaec | 1451 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1452 | |
3ae5eaec | 1453 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1454 | |
1455 | unregister_netdev(ndev); | |
1456 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1457 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1458 | |
a76836f9 | 1459 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1460 | return 0; |
1461 | } | |
1462 | ||
3ae5eaec | 1463 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1464 | .driver = { |
1465 | .name = "dm9000", | |
1466 | .owner = THIS_MODULE, | |
1467 | }, | |
a1365275 | 1468 | .probe = dm9000_probe, |
e21fd4f0 | 1469 | .remove = __devexit_p(dm9000_drv_remove), |
a1365275 SH |
1470 | .suspend = dm9000_drv_suspend, |
1471 | .resume = dm9000_drv_resume, | |
1472 | }; | |
1473 | ||
1474 | static int __init | |
1475 | dm9000_init(void) | |
1476 | { | |
7da99859 | 1477 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1478 | |
59eae1fa | 1479 | return platform_driver_register(&dm9000_driver); |
a1365275 SH |
1480 | } |
1481 | ||
1482 | static void __exit | |
1483 | dm9000_cleanup(void) | |
1484 | { | |
3ae5eaec | 1485 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1486 | } |
1487 | ||
1488 | module_init(dm9000_init); | |
1489 | module_exit(dm9000_cleanup); | |
1490 | ||
1491 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1492 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1493 | MODULE_LICENSE("GPL"); | |
72abb461 | 1494 | MODULE_ALIAS("platform:dm9000"); |