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967dd82f FF |
1 | /* |
2 | * B53 switch driver main logic | |
3 | * | |
4 | * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> | |
5 | * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> | |
6 | * | |
7 | * Permission to use, copy, modify, and/or distribute this software for any | |
8 | * purpose with or without fee is hereby granted, provided that the above | |
9 | * copyright notice and this permission notice appear in all copies. | |
10 | * | |
11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
18 | */ | |
19 | ||
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
21 | ||
22 | #include <linux/delay.h> | |
23 | #include <linux/export.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/platform_data/b53.h> | |
28 | #include <linux/phy.h> | |
1da6df85 | 29 | #include <linux/etherdevice.h> |
ff39c2d6 | 30 | #include <linux/if_bridge.h> |
967dd82f | 31 | #include <net/dsa.h> |
1da6df85 | 32 | #include <net/switchdev.h> |
967dd82f FF |
33 | |
34 | #include "b53_regs.h" | |
35 | #include "b53_priv.h" | |
36 | ||
37 | struct b53_mib_desc { | |
38 | u8 size; | |
39 | u8 offset; | |
40 | const char *name; | |
41 | }; | |
42 | ||
43 | /* BCM5365 MIB counters */ | |
44 | static const struct b53_mib_desc b53_mibs_65[] = { | |
45 | { 8, 0x00, "TxOctets" }, | |
46 | { 4, 0x08, "TxDropPkts" }, | |
47 | { 4, 0x10, "TxBroadcastPkts" }, | |
48 | { 4, 0x14, "TxMulticastPkts" }, | |
49 | { 4, 0x18, "TxUnicastPkts" }, | |
50 | { 4, 0x1c, "TxCollisions" }, | |
51 | { 4, 0x20, "TxSingleCollision" }, | |
52 | { 4, 0x24, "TxMultipleCollision" }, | |
53 | { 4, 0x28, "TxDeferredTransmit" }, | |
54 | { 4, 0x2c, "TxLateCollision" }, | |
55 | { 4, 0x30, "TxExcessiveCollision" }, | |
56 | { 4, 0x38, "TxPausePkts" }, | |
57 | { 8, 0x44, "RxOctets" }, | |
58 | { 4, 0x4c, "RxUndersizePkts" }, | |
59 | { 4, 0x50, "RxPausePkts" }, | |
60 | { 4, 0x54, "Pkts64Octets" }, | |
61 | { 4, 0x58, "Pkts65to127Octets" }, | |
62 | { 4, 0x5c, "Pkts128to255Octets" }, | |
63 | { 4, 0x60, "Pkts256to511Octets" }, | |
64 | { 4, 0x64, "Pkts512to1023Octets" }, | |
65 | { 4, 0x68, "Pkts1024to1522Octets" }, | |
66 | { 4, 0x6c, "RxOversizePkts" }, | |
67 | { 4, 0x70, "RxJabbers" }, | |
68 | { 4, 0x74, "RxAlignmentErrors" }, | |
69 | { 4, 0x78, "RxFCSErrors" }, | |
70 | { 8, 0x7c, "RxGoodOctets" }, | |
71 | { 4, 0x84, "RxDropPkts" }, | |
72 | { 4, 0x88, "RxUnicastPkts" }, | |
73 | { 4, 0x8c, "RxMulticastPkts" }, | |
74 | { 4, 0x90, "RxBroadcastPkts" }, | |
75 | { 4, 0x94, "RxSAChanges" }, | |
76 | { 4, 0x98, "RxFragments" }, | |
77 | }; | |
78 | ||
79 | #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) | |
80 | ||
81 | /* BCM63xx MIB counters */ | |
82 | static const struct b53_mib_desc b53_mibs_63xx[] = { | |
83 | { 8, 0x00, "TxOctets" }, | |
84 | { 4, 0x08, "TxDropPkts" }, | |
85 | { 4, 0x0c, "TxQoSPkts" }, | |
86 | { 4, 0x10, "TxBroadcastPkts" }, | |
87 | { 4, 0x14, "TxMulticastPkts" }, | |
88 | { 4, 0x18, "TxUnicastPkts" }, | |
89 | { 4, 0x1c, "TxCollisions" }, | |
90 | { 4, 0x20, "TxSingleCollision" }, | |
91 | { 4, 0x24, "TxMultipleCollision" }, | |
92 | { 4, 0x28, "TxDeferredTransmit" }, | |
93 | { 4, 0x2c, "TxLateCollision" }, | |
94 | { 4, 0x30, "TxExcessiveCollision" }, | |
95 | { 4, 0x38, "TxPausePkts" }, | |
96 | { 8, 0x3c, "TxQoSOctets" }, | |
97 | { 8, 0x44, "RxOctets" }, | |
98 | { 4, 0x4c, "RxUndersizePkts" }, | |
99 | { 4, 0x50, "RxPausePkts" }, | |
100 | { 4, 0x54, "Pkts64Octets" }, | |
101 | { 4, 0x58, "Pkts65to127Octets" }, | |
102 | { 4, 0x5c, "Pkts128to255Octets" }, | |
103 | { 4, 0x60, "Pkts256to511Octets" }, | |
104 | { 4, 0x64, "Pkts512to1023Octets" }, | |
105 | { 4, 0x68, "Pkts1024to1522Octets" }, | |
106 | { 4, 0x6c, "RxOversizePkts" }, | |
107 | { 4, 0x70, "RxJabbers" }, | |
108 | { 4, 0x74, "RxAlignmentErrors" }, | |
109 | { 4, 0x78, "RxFCSErrors" }, | |
110 | { 8, 0x7c, "RxGoodOctets" }, | |
111 | { 4, 0x84, "RxDropPkts" }, | |
112 | { 4, 0x88, "RxUnicastPkts" }, | |
113 | { 4, 0x8c, "RxMulticastPkts" }, | |
114 | { 4, 0x90, "RxBroadcastPkts" }, | |
115 | { 4, 0x94, "RxSAChanges" }, | |
116 | { 4, 0x98, "RxFragments" }, | |
117 | { 4, 0xa0, "RxSymbolErrors" }, | |
118 | { 4, 0xa4, "RxQoSPkts" }, | |
119 | { 8, 0xa8, "RxQoSOctets" }, | |
120 | { 4, 0xb0, "Pkts1523to2047Octets" }, | |
121 | { 4, 0xb4, "Pkts2048to4095Octets" }, | |
122 | { 4, 0xb8, "Pkts4096to8191Octets" }, | |
123 | { 4, 0xbc, "Pkts8192to9728Octets" }, | |
124 | { 4, 0xc0, "RxDiscarded" }, | |
125 | }; | |
126 | ||
127 | #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) | |
128 | ||
129 | /* MIB counters */ | |
130 | static const struct b53_mib_desc b53_mibs[] = { | |
131 | { 8, 0x00, "TxOctets" }, | |
132 | { 4, 0x08, "TxDropPkts" }, | |
133 | { 4, 0x10, "TxBroadcastPkts" }, | |
134 | { 4, 0x14, "TxMulticastPkts" }, | |
135 | { 4, 0x18, "TxUnicastPkts" }, | |
136 | { 4, 0x1c, "TxCollisions" }, | |
137 | { 4, 0x20, "TxSingleCollision" }, | |
138 | { 4, 0x24, "TxMultipleCollision" }, | |
139 | { 4, 0x28, "TxDeferredTransmit" }, | |
140 | { 4, 0x2c, "TxLateCollision" }, | |
141 | { 4, 0x30, "TxExcessiveCollision" }, | |
142 | { 4, 0x38, "TxPausePkts" }, | |
143 | { 8, 0x50, "RxOctets" }, | |
144 | { 4, 0x58, "RxUndersizePkts" }, | |
145 | { 4, 0x5c, "RxPausePkts" }, | |
146 | { 4, 0x60, "Pkts64Octets" }, | |
147 | { 4, 0x64, "Pkts65to127Octets" }, | |
148 | { 4, 0x68, "Pkts128to255Octets" }, | |
149 | { 4, 0x6c, "Pkts256to511Octets" }, | |
150 | { 4, 0x70, "Pkts512to1023Octets" }, | |
151 | { 4, 0x74, "Pkts1024to1522Octets" }, | |
152 | { 4, 0x78, "RxOversizePkts" }, | |
153 | { 4, 0x7c, "RxJabbers" }, | |
154 | { 4, 0x80, "RxAlignmentErrors" }, | |
155 | { 4, 0x84, "RxFCSErrors" }, | |
156 | { 8, 0x88, "RxGoodOctets" }, | |
157 | { 4, 0x90, "RxDropPkts" }, | |
158 | { 4, 0x94, "RxUnicastPkts" }, | |
159 | { 4, 0x98, "RxMulticastPkts" }, | |
160 | { 4, 0x9c, "RxBroadcastPkts" }, | |
161 | { 4, 0xa0, "RxSAChanges" }, | |
162 | { 4, 0xa4, "RxFragments" }, | |
163 | { 4, 0xa8, "RxJumboPkts" }, | |
164 | { 4, 0xac, "RxSymbolErrors" }, | |
165 | { 4, 0xc0, "RxDiscarded" }, | |
166 | }; | |
167 | ||
168 | #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) | |
169 | ||
170 | static int b53_do_vlan_op(struct b53_device *dev, u8 op) | |
171 | { | |
172 | unsigned int i; | |
173 | ||
174 | b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); | |
175 | ||
176 | for (i = 0; i < 10; i++) { | |
177 | u8 vta; | |
178 | ||
179 | b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); | |
180 | if (!(vta & VTA_START_CMD)) | |
181 | return 0; | |
182 | ||
183 | usleep_range(100, 200); | |
184 | } | |
185 | ||
186 | return -EIO; | |
187 | } | |
188 | ||
a2482d2c FF |
189 | static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, |
190 | struct b53_vlan *vlan) | |
967dd82f FF |
191 | { |
192 | if (is5325(dev)) { | |
193 | u32 entry = 0; | |
194 | ||
a2482d2c FF |
195 | if (vlan->members) { |
196 | entry = ((vlan->untag & VA_UNTAG_MASK_25) << | |
197 | VA_UNTAG_S_25) | vlan->members; | |
967dd82f FF |
198 | if (dev->core_rev >= 3) |
199 | entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; | |
200 | else | |
201 | entry |= VA_VALID_25; | |
202 | } | |
203 | ||
204 | b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); | |
205 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | | |
206 | VTA_RW_STATE_WR | VTA_RW_OP_EN); | |
207 | } else if (is5365(dev)) { | |
208 | u16 entry = 0; | |
209 | ||
a2482d2c FF |
210 | if (vlan->members) |
211 | entry = ((vlan->untag & VA_UNTAG_MASK_65) << | |
212 | VA_UNTAG_S_65) | vlan->members | VA_VALID_65; | |
967dd82f FF |
213 | |
214 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); | |
215 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | | |
216 | VTA_RW_STATE_WR | VTA_RW_OP_EN); | |
217 | } else { | |
218 | b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); | |
219 | b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], | |
a2482d2c | 220 | (vlan->untag << VTE_UNTAG_S) | vlan->members); |
967dd82f FF |
221 | |
222 | b53_do_vlan_op(dev, VTA_CMD_WRITE); | |
223 | } | |
a2482d2c FF |
224 | |
225 | dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", | |
226 | vid, vlan->members, vlan->untag); | |
227 | } | |
228 | ||
229 | static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, | |
230 | struct b53_vlan *vlan) | |
231 | { | |
232 | if (is5325(dev)) { | |
233 | u32 entry = 0; | |
234 | ||
235 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | | |
236 | VTA_RW_STATE_RD | VTA_RW_OP_EN); | |
237 | b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); | |
238 | ||
239 | if (dev->core_rev >= 3) | |
240 | vlan->valid = !!(entry & VA_VALID_25_R4); | |
241 | else | |
242 | vlan->valid = !!(entry & VA_VALID_25); | |
243 | vlan->members = entry & VA_MEMBER_MASK; | |
244 | vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; | |
245 | ||
246 | } else if (is5365(dev)) { | |
247 | u16 entry = 0; | |
248 | ||
249 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | | |
250 | VTA_RW_STATE_WR | VTA_RW_OP_EN); | |
251 | b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); | |
252 | ||
253 | vlan->valid = !!(entry & VA_VALID_65); | |
254 | vlan->members = entry & VA_MEMBER_MASK; | |
255 | vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; | |
256 | } else { | |
257 | u32 entry = 0; | |
258 | ||
259 | b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); | |
260 | b53_do_vlan_op(dev, VTA_CMD_READ); | |
261 | b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); | |
262 | vlan->members = entry & VTE_MEMBERS; | |
263 | vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; | |
264 | vlan->valid = true; | |
265 | } | |
967dd82f FF |
266 | } |
267 | ||
a2482d2c | 268 | static void b53_set_forwarding(struct b53_device *dev, int enable) |
967dd82f FF |
269 | { |
270 | u8 mgmt; | |
271 | ||
272 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
273 | ||
274 | if (enable) | |
275 | mgmt |= SM_SW_FWD_EN; | |
276 | else | |
277 | mgmt &= ~SM_SW_FWD_EN; | |
278 | ||
279 | b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); | |
280 | } | |
281 | ||
a2482d2c | 282 | static void b53_enable_vlan(struct b53_device *dev, bool enable) |
967dd82f FF |
283 | { |
284 | u8 mgmt, vc0, vc1, vc4 = 0, vc5; | |
285 | ||
286 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
287 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); | |
288 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); | |
289 | ||
290 | if (is5325(dev) || is5365(dev)) { | |
291 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); | |
292 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); | |
293 | } else if (is63xx(dev)) { | |
294 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); | |
295 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); | |
296 | } else { | |
297 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); | |
298 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); | |
299 | } | |
300 | ||
301 | mgmt &= ~SM_SW_FWD_MODE; | |
302 | ||
303 | if (enable) { | |
304 | vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; | |
305 | vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; | |
306 | vc4 &= ~VC4_ING_VID_CHECK_MASK; | |
307 | vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; | |
308 | vc5 |= VC5_DROP_VTABLE_MISS; | |
309 | ||
310 | if (is5325(dev)) | |
311 | vc0 &= ~VC0_RESERVED_1; | |
312 | ||
313 | if (is5325(dev) || is5365(dev)) | |
314 | vc1 |= VC1_RX_MCST_TAG_EN; | |
315 | ||
967dd82f FF |
316 | } else { |
317 | vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); | |
318 | vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); | |
319 | vc4 &= ~VC4_ING_VID_CHECK_MASK; | |
320 | vc5 &= ~VC5_DROP_VTABLE_MISS; | |
321 | ||
322 | if (is5325(dev) || is5365(dev)) | |
323 | vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; | |
324 | else | |
325 | vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; | |
326 | ||
327 | if (is5325(dev) || is5365(dev)) | |
328 | vc1 &= ~VC1_RX_MCST_TAG_EN; | |
967dd82f FF |
329 | } |
330 | ||
a2482d2c FF |
331 | if (!is5325(dev) && !is5365(dev)) |
332 | vc5 &= ~VC5_VID_FFF_EN; | |
333 | ||
967dd82f FF |
334 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); |
335 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); | |
336 | ||
337 | if (is5325(dev) || is5365(dev)) { | |
338 | /* enable the high 8 bit vid check on 5325 */ | |
339 | if (is5325(dev) && enable) | |
340 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, | |
341 | VC3_HIGH_8BIT_EN); | |
342 | else | |
343 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); | |
344 | ||
345 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); | |
346 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); | |
347 | } else if (is63xx(dev)) { | |
348 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); | |
349 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); | |
350 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); | |
351 | } else { | |
352 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); | |
353 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); | |
354 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); | |
355 | } | |
356 | ||
357 | b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); | |
358 | } | |
359 | ||
360 | static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) | |
361 | { | |
362 | u32 port_mask = 0; | |
363 | u16 max_size = JMS_MIN_SIZE; | |
364 | ||
365 | if (is5325(dev) || is5365(dev)) | |
366 | return -EINVAL; | |
367 | ||
368 | if (enable) { | |
369 | port_mask = dev->enabled_ports; | |
370 | max_size = JMS_MAX_SIZE; | |
371 | if (allow_10_100) | |
372 | port_mask |= JPM_10_100_JUMBO_EN; | |
373 | } | |
374 | ||
375 | b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); | |
376 | return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); | |
377 | } | |
378 | ||
ff39c2d6 | 379 | static int b53_flush_arl(struct b53_device *dev, u8 mask) |
967dd82f FF |
380 | { |
381 | unsigned int i; | |
382 | ||
383 | b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, | |
ff39c2d6 | 384 | FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); |
967dd82f FF |
385 | |
386 | for (i = 0; i < 10; i++) { | |
387 | u8 fast_age_ctrl; | |
388 | ||
389 | b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, | |
390 | &fast_age_ctrl); | |
391 | ||
392 | if (!(fast_age_ctrl & FAST_AGE_DONE)) | |
393 | goto out; | |
394 | ||
395 | msleep(1); | |
396 | } | |
397 | ||
398 | return -ETIMEDOUT; | |
399 | out: | |
400 | /* Only age dynamic entries (default behavior) */ | |
401 | b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); | |
402 | return 0; | |
403 | } | |
404 | ||
ff39c2d6 FF |
405 | static int b53_fast_age_port(struct b53_device *dev, int port) |
406 | { | |
407 | b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); | |
408 | ||
409 | return b53_flush_arl(dev, FAST_AGE_PORT); | |
410 | } | |
411 | ||
a2482d2c FF |
412 | static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) |
413 | { | |
414 | b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); | |
415 | ||
416 | return b53_flush_arl(dev, FAST_AGE_VLAN); | |
417 | } | |
418 | ||
ff39c2d6 FF |
419 | static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) |
420 | { | |
421 | struct b53_device *dev = ds_to_priv(ds); | |
422 | unsigned int i; | |
423 | u16 pvlan; | |
424 | ||
425 | /* Enable the IMP port to be in the same VLAN as the other ports | |
426 | * on a per-port basis such that we only have Port i and IMP in | |
427 | * the same VLAN. | |
428 | */ | |
429 | b53_for_each_port(dev, i) { | |
430 | b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); | |
431 | pvlan |= BIT(cpu_port); | |
432 | b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); | |
433 | } | |
434 | } | |
435 | ||
967dd82f FF |
436 | static int b53_enable_port(struct dsa_switch *ds, int port, |
437 | struct phy_device *phy) | |
438 | { | |
439 | struct b53_device *dev = ds_to_priv(ds); | |
ff39c2d6 FF |
440 | unsigned int cpu_port = dev->cpu_port; |
441 | u16 pvlan; | |
967dd82f FF |
442 | |
443 | /* Clear the Rx and Tx disable bits and set to no spanning tree */ | |
444 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); | |
445 | ||
ff39c2d6 FF |
446 | /* Set this port, and only this one to be in the default VLAN, |
447 | * if member of a bridge, restore its membership prior to | |
448 | * bringing down this port. | |
449 | */ | |
450 | b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); | |
451 | pvlan &= ~0x1ff; | |
452 | pvlan |= BIT(port); | |
453 | pvlan |= dev->ports[port].vlan_ctl_mask; | |
454 | b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); | |
455 | ||
456 | b53_imp_vlan_setup(ds, cpu_port); | |
457 | ||
967dd82f FF |
458 | return 0; |
459 | } | |
460 | ||
461 | static void b53_disable_port(struct dsa_switch *ds, int port, | |
462 | struct phy_device *phy) | |
463 | { | |
464 | struct b53_device *dev = ds_to_priv(ds); | |
465 | u8 reg; | |
466 | ||
467 | /* Disable Tx/Rx for the port */ | |
468 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); | |
469 | reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; | |
470 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); | |
471 | } | |
472 | ||
473 | static void b53_enable_cpu_port(struct b53_device *dev) | |
474 | { | |
475 | unsigned int cpu_port = dev->cpu_port; | |
476 | u8 port_ctrl; | |
477 | ||
478 | /* BCM5325 CPU port is at 8 */ | |
479 | if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25) | |
480 | cpu_port = B53_CPU_PORT; | |
481 | ||
482 | port_ctrl = PORT_CTRL_RX_BCST_EN | | |
483 | PORT_CTRL_RX_MCST_EN | | |
484 | PORT_CTRL_RX_UCST_EN; | |
485 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl); | |
486 | } | |
487 | ||
488 | static void b53_enable_mib(struct b53_device *dev) | |
489 | { | |
490 | u8 gc; | |
491 | ||
492 | b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); | |
493 | gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); | |
494 | b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); | |
495 | } | |
496 | ||
497 | static int b53_configure_vlan(struct b53_device *dev) | |
498 | { | |
a2482d2c | 499 | struct b53_vlan vl = { 0 }; |
967dd82f FF |
500 | int i; |
501 | ||
502 | /* clear all vlan entries */ | |
503 | if (is5325(dev) || is5365(dev)) { | |
504 | for (i = 1; i < dev->num_vlans; i++) | |
a2482d2c | 505 | b53_set_vlan_entry(dev, i, &vl); |
967dd82f FF |
506 | } else { |
507 | b53_do_vlan_op(dev, VTA_CMD_CLEAR); | |
508 | } | |
509 | ||
510 | b53_enable_vlan(dev, false); | |
511 | ||
512 | b53_for_each_port(dev, i) | |
513 | b53_write16(dev, B53_VLAN_PAGE, | |
514 | B53_VLAN_PORT_DEF_TAG(i), 1); | |
515 | ||
516 | if (!is5325(dev) && !is5365(dev)) | |
517 | b53_set_jumbo(dev, dev->enable_jumbo, false); | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static void b53_switch_reset_gpio(struct b53_device *dev) | |
523 | { | |
524 | int gpio = dev->reset_gpio; | |
525 | ||
526 | if (gpio < 0) | |
527 | return; | |
528 | ||
529 | /* Reset sequence: RESET low(50ms)->high(20ms) | |
530 | */ | |
531 | gpio_set_value(gpio, 0); | |
532 | mdelay(50); | |
533 | ||
534 | gpio_set_value(gpio, 1); | |
535 | mdelay(20); | |
536 | ||
537 | dev->current_page = 0xff; | |
538 | } | |
539 | ||
540 | static int b53_switch_reset(struct b53_device *dev) | |
541 | { | |
542 | u8 mgmt; | |
543 | ||
544 | b53_switch_reset_gpio(dev); | |
545 | ||
546 | if (is539x(dev)) { | |
547 | b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); | |
548 | b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); | |
549 | } | |
550 | ||
551 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
552 | ||
553 | if (!(mgmt & SM_SW_FWD_EN)) { | |
554 | mgmt &= ~SM_SW_FWD_MODE; | |
555 | mgmt |= SM_SW_FWD_EN; | |
556 | ||
557 | b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); | |
558 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
559 | ||
560 | if (!(mgmt & SM_SW_FWD_EN)) { | |
561 | dev_err(dev->dev, "Failed to enable switch!\n"); | |
562 | return -EINVAL; | |
563 | } | |
564 | } | |
565 | ||
566 | b53_enable_mib(dev); | |
567 | ||
ff39c2d6 | 568 | return b53_flush_arl(dev, FAST_AGE_STATIC); |
967dd82f FF |
569 | } |
570 | ||
571 | static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) | |
572 | { | |
573 | struct b53_device *priv = ds_to_priv(ds); | |
574 | u16 value = 0; | |
575 | int ret; | |
576 | ||
577 | if (priv->ops->phy_read16) | |
578 | ret = priv->ops->phy_read16(priv, addr, reg, &value); | |
579 | else | |
580 | ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), | |
581 | reg * 2, &value); | |
582 | ||
583 | return ret ? ret : value; | |
584 | } | |
585 | ||
586 | static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) | |
587 | { | |
588 | struct b53_device *priv = ds_to_priv(ds); | |
589 | ||
590 | if (priv->ops->phy_write16) | |
591 | return priv->ops->phy_write16(priv, addr, reg, val); | |
592 | ||
593 | return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); | |
594 | } | |
595 | ||
596 | static int b53_reset_switch(struct b53_device *priv) | |
597 | { | |
598 | /* reset vlans */ | |
599 | priv->enable_jumbo = false; | |
600 | ||
a2482d2c | 601 | memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); |
967dd82f FF |
602 | memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); |
603 | ||
604 | return b53_switch_reset(priv); | |
605 | } | |
606 | ||
607 | static int b53_apply_config(struct b53_device *priv) | |
608 | { | |
609 | /* disable switching */ | |
610 | b53_set_forwarding(priv, 0); | |
611 | ||
612 | b53_configure_vlan(priv); | |
613 | ||
614 | /* enable switching */ | |
615 | b53_set_forwarding(priv, 1); | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | static void b53_reset_mib(struct b53_device *priv) | |
621 | { | |
622 | u8 gc; | |
623 | ||
624 | b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); | |
625 | ||
626 | b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); | |
627 | msleep(1); | |
628 | b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); | |
629 | msleep(1); | |
630 | } | |
631 | ||
632 | static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) | |
633 | { | |
634 | if (is5365(dev)) | |
635 | return b53_mibs_65; | |
636 | else if (is63xx(dev)) | |
637 | return b53_mibs_63xx; | |
638 | else | |
639 | return b53_mibs; | |
640 | } | |
641 | ||
642 | static unsigned int b53_get_mib_size(struct b53_device *dev) | |
643 | { | |
644 | if (is5365(dev)) | |
645 | return B53_MIBS_65_SIZE; | |
646 | else if (is63xx(dev)) | |
647 | return B53_MIBS_63XX_SIZE; | |
648 | else | |
649 | return B53_MIBS_SIZE; | |
650 | } | |
651 | ||
652 | static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
653 | { | |
654 | struct b53_device *dev = ds_to_priv(ds); | |
655 | const struct b53_mib_desc *mibs = b53_get_mib(dev); | |
656 | unsigned int mib_size = b53_get_mib_size(dev); | |
657 | unsigned int i; | |
658 | ||
659 | for (i = 0; i < mib_size; i++) | |
660 | memcpy(data + i * ETH_GSTRING_LEN, | |
661 | mibs[i].name, ETH_GSTRING_LEN); | |
662 | } | |
663 | ||
664 | static void b53_get_ethtool_stats(struct dsa_switch *ds, int port, | |
665 | uint64_t *data) | |
666 | { | |
667 | struct b53_device *dev = ds_to_priv(ds); | |
668 | const struct b53_mib_desc *mibs = b53_get_mib(dev); | |
669 | unsigned int mib_size = b53_get_mib_size(dev); | |
670 | const struct b53_mib_desc *s; | |
671 | unsigned int i; | |
672 | u64 val = 0; | |
673 | ||
674 | if (is5365(dev) && port == 5) | |
675 | port = 8; | |
676 | ||
677 | mutex_lock(&dev->stats_mutex); | |
678 | ||
679 | for (i = 0; i < mib_size; i++) { | |
680 | s = &mibs[i]; | |
681 | ||
51dca8a1 | 682 | if (s->size == 8) { |
967dd82f FF |
683 | b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); |
684 | } else { | |
685 | u32 val32; | |
686 | ||
687 | b53_read32(dev, B53_MIB_PAGE(port), s->offset, | |
688 | &val32); | |
689 | val = val32; | |
690 | } | |
691 | data[i] = (u64)val; | |
692 | } | |
693 | ||
694 | mutex_unlock(&dev->stats_mutex); | |
695 | } | |
696 | ||
697 | static int b53_get_sset_count(struct dsa_switch *ds) | |
698 | { | |
699 | struct b53_device *dev = ds_to_priv(ds); | |
700 | ||
701 | return b53_get_mib_size(dev); | |
702 | } | |
703 | ||
704 | static int b53_set_addr(struct dsa_switch *ds, u8 *addr) | |
705 | { | |
706 | return 0; | |
707 | } | |
708 | ||
709 | static int b53_setup(struct dsa_switch *ds) | |
710 | { | |
711 | struct b53_device *dev = ds_to_priv(ds); | |
712 | unsigned int port; | |
713 | int ret; | |
714 | ||
715 | ret = b53_reset_switch(dev); | |
716 | if (ret) { | |
717 | dev_err(ds->dev, "failed to reset switch\n"); | |
718 | return ret; | |
719 | } | |
720 | ||
721 | b53_reset_mib(dev); | |
722 | ||
723 | ret = b53_apply_config(dev); | |
724 | if (ret) | |
725 | dev_err(ds->dev, "failed to apply configuration\n"); | |
726 | ||
727 | for (port = 0; port < dev->num_ports; port++) { | |
728 | if (BIT(port) & ds->enabled_port_mask) | |
729 | b53_enable_port(ds, port, NULL); | |
730 | else if (dsa_is_cpu_port(ds, port)) | |
731 | b53_enable_cpu_port(dev); | |
732 | else | |
733 | b53_disable_port(ds, port, NULL); | |
734 | } | |
735 | ||
736 | return ret; | |
737 | } | |
738 | ||
739 | static void b53_adjust_link(struct dsa_switch *ds, int port, | |
740 | struct phy_device *phydev) | |
741 | { | |
742 | struct b53_device *dev = ds_to_priv(ds); | |
743 | u8 rgmii_ctrl = 0, reg = 0, off; | |
744 | ||
745 | if (!phy_is_pseudo_fixed_link(phydev)) | |
746 | return; | |
747 | ||
748 | /* Override the port settings */ | |
749 | if (port == dev->cpu_port) { | |
750 | off = B53_PORT_OVERRIDE_CTRL; | |
751 | reg = PORT_OVERRIDE_EN; | |
752 | } else { | |
753 | off = B53_GMII_PORT_OVERRIDE_CTRL(port); | |
754 | reg = GMII_PO_EN; | |
755 | } | |
756 | ||
757 | /* Set the link UP */ | |
758 | if (phydev->link) | |
759 | reg |= PORT_OVERRIDE_LINK; | |
760 | ||
761 | if (phydev->duplex == DUPLEX_FULL) | |
762 | reg |= PORT_OVERRIDE_FULL_DUPLEX; | |
763 | ||
764 | switch (phydev->speed) { | |
765 | case 2000: | |
766 | reg |= PORT_OVERRIDE_SPEED_2000M; | |
767 | /* fallthrough */ | |
768 | case SPEED_1000: | |
769 | reg |= PORT_OVERRIDE_SPEED_1000M; | |
770 | break; | |
771 | case SPEED_100: | |
772 | reg |= PORT_OVERRIDE_SPEED_100M; | |
773 | break; | |
774 | case SPEED_10: | |
775 | reg |= PORT_OVERRIDE_SPEED_10M; | |
776 | break; | |
777 | default: | |
778 | dev_err(ds->dev, "unknown speed: %d\n", phydev->speed); | |
779 | return; | |
780 | } | |
781 | ||
782 | /* Enable flow control on BCM5301x's CPU port */ | |
783 | if (is5301x(dev) && port == dev->cpu_port) | |
784 | reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW; | |
785 | ||
786 | if (phydev->pause) { | |
787 | if (phydev->asym_pause) | |
788 | reg |= PORT_OVERRIDE_TX_FLOW; | |
789 | reg |= PORT_OVERRIDE_RX_FLOW; | |
790 | } | |
791 | ||
792 | b53_write8(dev, B53_CTRL_PAGE, off, reg); | |
793 | ||
794 | if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { | |
795 | if (port == 8) | |
796 | off = B53_RGMII_CTRL_IMP; | |
797 | else | |
798 | off = B53_RGMII_CTRL_P(port); | |
799 | ||
800 | /* Configure the port RGMII clock delay by DLL disabled and | |
801 | * tx_clk aligned timing (restoring to reset defaults) | |
802 | */ | |
803 | b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); | |
804 | rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | | |
805 | RGMII_CTRL_TIMING_SEL); | |
806 | ||
807 | /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make | |
808 | * sure that we enable the port TX clock internal delay to | |
809 | * account for this internal delay that is inserted, otherwise | |
810 | * the switch won't be able to receive correctly. | |
811 | * | |
812 | * PHY_INTERFACE_MODE_RGMII means that we are not introducing | |
813 | * any delay neither on transmission nor reception, so the | |
814 | * BCM53125 must also be configured accordingly to account for | |
815 | * the lack of delay and introduce | |
816 | * | |
817 | * The BCM53125 switch has its RX clock and TX clock control | |
818 | * swapped, hence the reason why we modify the TX clock path in | |
819 | * the "RGMII" case | |
820 | */ | |
821 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
822 | rgmii_ctrl |= RGMII_CTRL_DLL_TXC; | |
823 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII) | |
824 | rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; | |
825 | rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; | |
826 | b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); | |
827 | ||
828 | dev_info(ds->dev, "Configured port %d for %s\n", port, | |
829 | phy_modes(phydev->interface)); | |
830 | } | |
831 | ||
832 | /* configure MII port if necessary */ | |
833 | if (is5325(dev)) { | |
834 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, | |
835 | ®); | |
836 | ||
837 | /* reverse mii needs to be enabled */ | |
838 | if (!(reg & PORT_OVERRIDE_RV_MII_25)) { | |
839 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, | |
840 | reg | PORT_OVERRIDE_RV_MII_25); | |
841 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, | |
842 | ®); | |
843 | ||
844 | if (!(reg & PORT_OVERRIDE_RV_MII_25)) { | |
845 | dev_err(ds->dev, | |
846 | "Failed to enable reverse MII mode\n"); | |
847 | return; | |
848 | } | |
849 | } | |
850 | } else if (is5301x(dev)) { | |
851 | if (port != dev->cpu_port) { | |
852 | u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port); | |
853 | u8 gmii_po; | |
854 | ||
855 | b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); | |
856 | gmii_po |= GMII_PO_LINK | | |
857 | GMII_PO_RX_FLOW | | |
858 | GMII_PO_TX_FLOW | | |
859 | GMII_PO_EN | | |
860 | GMII_PO_SPEED_2000M; | |
861 | b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); | |
862 | } | |
863 | } | |
864 | } | |
865 | ||
a2482d2c FF |
866 | static int b53_vlan_filtering(struct dsa_switch *ds, int port, |
867 | bool vlan_filtering) | |
868 | { | |
869 | return 0; | |
870 | } | |
871 | ||
872 | static int b53_vlan_prepare(struct dsa_switch *ds, int port, | |
873 | const struct switchdev_obj_port_vlan *vlan, | |
874 | struct switchdev_trans *trans) | |
875 | { | |
876 | struct b53_device *dev = ds_to_priv(ds); | |
877 | ||
878 | if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) | |
879 | return -EOPNOTSUPP; | |
880 | ||
881 | if (vlan->vid_end > dev->num_vlans) | |
882 | return -ERANGE; | |
883 | ||
884 | b53_enable_vlan(dev, true); | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
889 | static void b53_vlan_add(struct dsa_switch *ds, int port, | |
890 | const struct switchdev_obj_port_vlan *vlan, | |
891 | struct switchdev_trans *trans) | |
892 | { | |
893 | struct b53_device *dev = ds_to_priv(ds); | |
894 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
895 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
896 | unsigned int cpu_port = dev->cpu_port; | |
897 | struct b53_vlan *vl; | |
898 | u16 vid; | |
899 | ||
900 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { | |
901 | vl = &dev->vlans[vid]; | |
902 | ||
903 | b53_get_vlan_entry(dev, vid, vl); | |
904 | ||
905 | vl->members |= BIT(port) | BIT(cpu_port); | |
906 | if (untagged) | |
907 | vl->untag |= BIT(port) | BIT(cpu_port); | |
908 | else | |
909 | vl->untag &= ~(BIT(port) | BIT(cpu_port)); | |
910 | ||
911 | b53_set_vlan_entry(dev, vid, vl); | |
912 | b53_fast_age_vlan(dev, vid); | |
913 | } | |
914 | ||
915 | if (pvid) { | |
916 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), | |
917 | vlan->vid_end); | |
918 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), | |
919 | vlan->vid_end); | |
920 | b53_fast_age_vlan(dev, vid); | |
921 | } | |
922 | } | |
923 | ||
924 | static int b53_vlan_del(struct dsa_switch *ds, int port, | |
925 | const struct switchdev_obj_port_vlan *vlan) | |
926 | { | |
927 | struct b53_device *dev = ds_to_priv(ds); | |
928 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
929 | unsigned int cpu_port = dev->cpu_port; | |
930 | struct b53_vlan *vl; | |
931 | u16 vid; | |
932 | u16 pvid; | |
933 | ||
934 | b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); | |
935 | ||
936 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { | |
937 | vl = &dev->vlans[vid]; | |
938 | ||
939 | b53_get_vlan_entry(dev, vid, vl); | |
940 | ||
941 | vl->members &= ~BIT(port); | |
942 | if ((vl->members & BIT(cpu_port)) == BIT(cpu_port)) | |
943 | vl->members = 0; | |
944 | ||
945 | if (pvid == vid) { | |
946 | if (is5325(dev) || is5365(dev)) | |
947 | pvid = 1; | |
948 | else | |
949 | pvid = 0; | |
950 | } | |
951 | ||
952 | if (untagged) { | |
953 | vl->untag &= ~(BIT(port)); | |
954 | if ((vl->untag & BIT(cpu_port)) == BIT(cpu_port)) | |
955 | vl->untag = 0; | |
956 | } | |
957 | ||
958 | b53_set_vlan_entry(dev, vid, vl); | |
959 | b53_fast_age_vlan(dev, vid); | |
960 | } | |
961 | ||
962 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); | |
963 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), pvid); | |
964 | b53_fast_age_vlan(dev, pvid); | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
969 | static int b53_vlan_dump(struct dsa_switch *ds, int port, | |
970 | struct switchdev_obj_port_vlan *vlan, | |
971 | int (*cb)(struct switchdev_obj *obj)) | |
972 | { | |
973 | struct b53_device *dev = ds_to_priv(ds); | |
974 | u16 vid, vid_start = 0, pvid; | |
975 | struct b53_vlan *vl; | |
976 | int err = 0; | |
977 | ||
978 | if (is5325(dev) || is5365(dev)) | |
979 | vid_start = 1; | |
980 | ||
981 | b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); | |
982 | ||
983 | /* Use our software cache for dumps, since we do not have any HW | |
984 | * operation returning only the used/valid VLANs | |
985 | */ | |
986 | for (vid = vid_start; vid < dev->num_vlans; vid++) { | |
987 | vl = &dev->vlans[vid]; | |
988 | ||
989 | if (!vl->valid) | |
990 | continue; | |
991 | ||
992 | if (!(vl->members & BIT(port))) | |
993 | continue; | |
994 | ||
995 | vlan->vid_begin = vlan->vid_end = vid; | |
996 | vlan->flags = 0; | |
997 | ||
998 | if (vl->untag & BIT(port)) | |
999 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; | |
1000 | if (pvid == vid) | |
1001 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
1002 | ||
1003 | err = cb(&vlan->obj); | |
1004 | if (err) | |
1005 | break; | |
1006 | } | |
1007 | ||
1008 | return err; | |
1009 | } | |
1010 | ||
1da6df85 FF |
1011 | /* Address Resolution Logic routines */ |
1012 | static int b53_arl_op_wait(struct b53_device *dev) | |
1013 | { | |
1014 | unsigned int timeout = 10; | |
1015 | u8 reg; | |
1016 | ||
1017 | do { | |
1018 | b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); | |
1019 | if (!(reg & ARLTBL_START_DONE)) | |
1020 | return 0; | |
1021 | ||
1022 | usleep_range(1000, 2000); | |
1023 | } while (timeout--); | |
1024 | ||
1025 | dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); | |
1026 | ||
1027 | return -ETIMEDOUT; | |
1028 | } | |
1029 | ||
1030 | static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) | |
1031 | { | |
1032 | u8 reg; | |
1033 | ||
1034 | if (op > ARLTBL_RW) | |
1035 | return -EINVAL; | |
1036 | ||
1037 | b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); | |
1038 | reg |= ARLTBL_START_DONE; | |
1039 | if (op) | |
1040 | reg |= ARLTBL_RW; | |
1041 | else | |
1042 | reg &= ~ARLTBL_RW; | |
1043 | b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); | |
1044 | ||
1045 | return b53_arl_op_wait(dev); | |
1046 | } | |
1047 | ||
1048 | static int b53_arl_read(struct b53_device *dev, u64 mac, | |
1049 | u16 vid, struct b53_arl_entry *ent, u8 *idx, | |
1050 | bool is_valid) | |
1051 | { | |
1052 | unsigned int i; | |
1053 | int ret; | |
1054 | ||
1055 | ret = b53_arl_op_wait(dev); | |
1056 | if (ret) | |
1057 | return ret; | |
1058 | ||
1059 | /* Read the bins */ | |
1060 | for (i = 0; i < dev->num_arl_entries; i++) { | |
1061 | u64 mac_vid; | |
1062 | u32 fwd_entry; | |
1063 | ||
1064 | b53_read64(dev, B53_ARLIO_PAGE, | |
1065 | B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); | |
1066 | b53_read32(dev, B53_ARLIO_PAGE, | |
1067 | B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); | |
1068 | b53_arl_to_entry(ent, mac_vid, fwd_entry); | |
1069 | ||
1070 | if (!(fwd_entry & ARLTBL_VALID)) | |
1071 | continue; | |
1072 | if ((mac_vid & ARLTBL_MAC_MASK) != mac) | |
1073 | continue; | |
1074 | *idx = i; | |
1075 | } | |
1076 | ||
1077 | return -ENOENT; | |
1078 | } | |
1079 | ||
1080 | static int b53_arl_op(struct b53_device *dev, int op, int port, | |
1081 | const unsigned char *addr, u16 vid, bool is_valid) | |
1082 | { | |
1083 | struct b53_arl_entry ent; | |
1084 | u32 fwd_entry; | |
1085 | u64 mac, mac_vid = 0; | |
1086 | u8 idx = 0; | |
1087 | int ret; | |
1088 | ||
1089 | /* Convert the array into a 64-bit MAC */ | |
1090 | mac = b53_mac_to_u64(addr); | |
1091 | ||
1092 | /* Perform a read for the given MAC and VID */ | |
1093 | b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); | |
1094 | b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); | |
1095 | ||
1096 | /* Issue a read operation for this MAC */ | |
1097 | ret = b53_arl_rw_op(dev, 1); | |
1098 | if (ret) | |
1099 | return ret; | |
1100 | ||
1101 | ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); | |
1102 | /* If this is a read, just finish now */ | |
1103 | if (op) | |
1104 | return ret; | |
1105 | ||
1106 | /* We could not find a matching MAC, so reset to a new entry */ | |
1107 | if (ret) { | |
1108 | fwd_entry = 0; | |
1109 | idx = 1; | |
1110 | } | |
1111 | ||
1112 | memset(&ent, 0, sizeof(ent)); | |
1113 | ent.port = port; | |
1114 | ent.is_valid = is_valid; | |
1115 | ent.vid = vid; | |
1116 | ent.is_static = true; | |
1117 | memcpy(ent.mac, addr, ETH_ALEN); | |
1118 | b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); | |
1119 | ||
1120 | b53_write64(dev, B53_ARLIO_PAGE, | |
1121 | B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); | |
1122 | b53_write32(dev, B53_ARLIO_PAGE, | |
1123 | B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); | |
1124 | ||
1125 | return b53_arl_rw_op(dev, 0); | |
1126 | } | |
1127 | ||
1128 | static int b53_fdb_prepare(struct dsa_switch *ds, int port, | |
1129 | const struct switchdev_obj_port_fdb *fdb, | |
1130 | struct switchdev_trans *trans) | |
1131 | { | |
1132 | struct b53_device *priv = ds_to_priv(ds); | |
1133 | ||
1134 | /* 5325 and 5365 require some more massaging, but could | |
1135 | * be supported eventually | |
1136 | */ | |
1137 | if (is5325(priv) || is5365(priv)) | |
1138 | return -EOPNOTSUPP; | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static void b53_fdb_add(struct dsa_switch *ds, int port, | |
1144 | const struct switchdev_obj_port_fdb *fdb, | |
1145 | struct switchdev_trans *trans) | |
1146 | { | |
1147 | struct b53_device *priv = ds_to_priv(ds); | |
1148 | ||
1149 | if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true)) | |
1150 | pr_err("%s: failed to add MAC address\n", __func__); | |
1151 | } | |
1152 | ||
1153 | static int b53_fdb_del(struct dsa_switch *ds, int port, | |
1154 | const struct switchdev_obj_port_fdb *fdb) | |
1155 | { | |
1156 | struct b53_device *priv = ds_to_priv(ds); | |
1157 | ||
1158 | return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false); | |
1159 | } | |
1160 | ||
1161 | static int b53_arl_search_wait(struct b53_device *dev) | |
1162 | { | |
1163 | unsigned int timeout = 1000; | |
1164 | u8 reg; | |
1165 | ||
1166 | do { | |
1167 | b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); | |
1168 | if (!(reg & ARL_SRCH_STDN)) | |
1169 | return 0; | |
1170 | ||
1171 | if (reg & ARL_SRCH_VLID) | |
1172 | return 0; | |
1173 | ||
1174 | usleep_range(1000, 2000); | |
1175 | } while (timeout--); | |
1176 | ||
1177 | return -ETIMEDOUT; | |
1178 | } | |
1179 | ||
1180 | static void b53_arl_search_rd(struct b53_device *dev, u8 idx, | |
1181 | struct b53_arl_entry *ent) | |
1182 | { | |
1183 | u64 mac_vid; | |
1184 | u32 fwd_entry; | |
1185 | ||
1186 | b53_read64(dev, B53_ARLIO_PAGE, | |
1187 | B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); | |
1188 | b53_read32(dev, B53_ARLIO_PAGE, | |
1189 | B53_ARL_SRCH_RSTL(idx), &fwd_entry); | |
1190 | b53_arl_to_entry(ent, mac_vid, fwd_entry); | |
1191 | } | |
1192 | ||
1193 | static int b53_fdb_copy(struct net_device *dev, int port, | |
1194 | const struct b53_arl_entry *ent, | |
1195 | struct switchdev_obj_port_fdb *fdb, | |
1196 | int (*cb)(struct switchdev_obj *obj)) | |
1197 | { | |
1198 | if (!ent->is_valid) | |
1199 | return 0; | |
1200 | ||
1201 | if (port != ent->port) | |
1202 | return 0; | |
1203 | ||
1204 | ether_addr_copy(fdb->addr, ent->mac); | |
1205 | fdb->vid = ent->vid; | |
1206 | fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE; | |
1207 | ||
1208 | return cb(&fdb->obj); | |
1209 | } | |
1210 | ||
1211 | static int b53_fdb_dump(struct dsa_switch *ds, int port, | |
1212 | struct switchdev_obj_port_fdb *fdb, | |
1213 | int (*cb)(struct switchdev_obj *obj)) | |
1214 | { | |
1215 | struct b53_device *priv = ds_to_priv(ds); | |
1216 | struct net_device *dev = ds->ports[port].netdev; | |
1217 | struct b53_arl_entry results[2]; | |
1218 | unsigned int count = 0; | |
1219 | int ret; | |
1220 | u8 reg; | |
1221 | ||
1222 | /* Start search operation */ | |
1223 | reg = ARL_SRCH_STDN; | |
1224 | b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); | |
1225 | ||
1226 | do { | |
1227 | ret = b53_arl_search_wait(priv); | |
1228 | if (ret) | |
1229 | return ret; | |
1230 | ||
1231 | b53_arl_search_rd(priv, 0, &results[0]); | |
1232 | ret = b53_fdb_copy(dev, port, &results[0], fdb, cb); | |
1233 | if (ret) | |
1234 | return ret; | |
1235 | ||
1236 | if (priv->num_arl_entries > 2) { | |
1237 | b53_arl_search_rd(priv, 1, &results[1]); | |
1238 | ret = b53_fdb_copy(dev, port, &results[1], fdb, cb); | |
1239 | if (ret) | |
1240 | return ret; | |
1241 | ||
1242 | if (!results[0].is_valid && !results[1].is_valid) | |
1243 | break; | |
1244 | } | |
1245 | ||
1246 | } while (count++ < 1024); | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
ff39c2d6 FF |
1251 | static int b53_br_join(struct dsa_switch *ds, int port, |
1252 | struct net_device *bridge) | |
1253 | { | |
1254 | struct b53_device *dev = ds_to_priv(ds); | |
1255 | u16 pvlan, reg; | |
1256 | unsigned int i; | |
1257 | ||
1258 | dev->ports[port].bridge_dev = bridge; | |
1259 | b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); | |
1260 | ||
1261 | b53_for_each_port(dev, i) { | |
1262 | if (dev->ports[i].bridge_dev != bridge) | |
1263 | continue; | |
1264 | ||
1265 | /* Add this local port to the remote port VLAN control | |
1266 | * membership and update the remote port bitmask | |
1267 | */ | |
1268 | b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); | |
1269 | reg |= BIT(port); | |
1270 | b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); | |
1271 | dev->ports[i].vlan_ctl_mask = reg; | |
1272 | ||
1273 | pvlan |= BIT(i); | |
1274 | } | |
1275 | ||
1276 | /* Configure the local port VLAN control membership to include | |
1277 | * remote ports and update the local port bitmask | |
1278 | */ | |
1279 | b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); | |
1280 | dev->ports[port].vlan_ctl_mask = pvlan; | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static void b53_br_leave(struct dsa_switch *ds, int port) | |
1286 | { | |
1287 | struct b53_device *dev = ds_to_priv(ds); | |
1288 | struct net_device *bridge = dev->ports[port].bridge_dev; | |
a2482d2c | 1289 | struct b53_vlan *vl = &dev->vlans[0]; |
ff39c2d6 | 1290 | unsigned int i; |
a2482d2c | 1291 | u16 pvlan, reg, pvid; |
ff39c2d6 FF |
1292 | |
1293 | b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); | |
1294 | ||
1295 | b53_for_each_port(dev, i) { | |
1296 | /* Don't touch the remaining ports */ | |
1297 | if (dev->ports[i].bridge_dev != bridge) | |
1298 | continue; | |
1299 | ||
1300 | b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); | |
1301 | reg &= ~BIT(port); | |
1302 | b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); | |
1303 | dev->ports[port].vlan_ctl_mask = reg; | |
1304 | ||
1305 | /* Prevent self removal to preserve isolation */ | |
1306 | if (port != i) | |
1307 | pvlan &= ~BIT(i); | |
1308 | } | |
1309 | ||
1310 | b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); | |
1311 | dev->ports[port].vlan_ctl_mask = pvlan; | |
1312 | dev->ports[port].bridge_dev = NULL; | |
a2482d2c FF |
1313 | |
1314 | if (is5325(dev) || is5365(dev)) | |
1315 | pvid = 1; | |
1316 | else | |
1317 | pvid = 0; | |
1318 | ||
1319 | b53_get_vlan_entry(dev, pvid, vl); | |
1320 | vl->members |= BIT(port) | BIT(dev->cpu_port); | |
1321 | vl->untag |= BIT(port) | BIT(dev->cpu_port); | |
1322 | b53_set_vlan_entry(dev, pvid, vl); | |
ff39c2d6 FF |
1323 | } |
1324 | ||
1325 | static void b53_br_set_stp_state(struct dsa_switch *ds, int port, | |
1326 | u8 state) | |
1327 | { | |
1328 | struct b53_device *dev = ds_to_priv(ds); | |
1329 | u8 hw_state, cur_hw_state; | |
1330 | u8 reg; | |
1331 | ||
1332 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); | |
1333 | cur_hw_state = reg & PORT_CTRL_STP_STATE_MASK; | |
1334 | ||
1335 | switch (state) { | |
1336 | case BR_STATE_DISABLED: | |
1337 | hw_state = PORT_CTRL_DIS_STATE; | |
1338 | break; | |
1339 | case BR_STATE_LISTENING: | |
1340 | hw_state = PORT_CTRL_LISTEN_STATE; | |
1341 | break; | |
1342 | case BR_STATE_LEARNING: | |
1343 | hw_state = PORT_CTRL_LEARN_STATE; | |
1344 | break; | |
1345 | case BR_STATE_FORWARDING: | |
1346 | hw_state = PORT_CTRL_FWD_STATE; | |
1347 | break; | |
1348 | case BR_STATE_BLOCKING: | |
1349 | hw_state = PORT_CTRL_BLOCK_STATE; | |
1350 | break; | |
1351 | default: | |
1352 | dev_err(ds->dev, "invalid STP state: %d\n", state); | |
1353 | return; | |
1354 | } | |
1355 | ||
1356 | /* Fast-age ARL entries if we are moving a port from Learning or | |
1357 | * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening | |
1358 | * state (hw_state) | |
1359 | */ | |
1360 | if (cur_hw_state != hw_state) { | |
1361 | if (cur_hw_state >= PORT_CTRL_LEARN_STATE && | |
1362 | hw_state <= PORT_CTRL_LISTEN_STATE) { | |
1363 | if (b53_fast_age_port(dev, port)) { | |
1364 | dev_err(ds->dev, "fast ageing failed\n"); | |
1365 | return; | |
1366 | } | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); | |
1371 | reg &= ~PORT_CTRL_STP_STATE_MASK; | |
1372 | reg |= hw_state; | |
1373 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); | |
1374 | } | |
1375 | ||
7b314362 AL |
1376 | static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds) |
1377 | { | |
1378 | return DSA_TAG_PROTO_NONE; | |
1379 | } | |
1380 | ||
9d490b4e | 1381 | static struct dsa_switch_ops b53_switch_ops = { |
7b314362 | 1382 | .get_tag_protocol = b53_get_tag_protocol, |
967dd82f FF |
1383 | .setup = b53_setup, |
1384 | .set_addr = b53_set_addr, | |
1385 | .get_strings = b53_get_strings, | |
1386 | .get_ethtool_stats = b53_get_ethtool_stats, | |
1387 | .get_sset_count = b53_get_sset_count, | |
1388 | .phy_read = b53_phy_read16, | |
1389 | .phy_write = b53_phy_write16, | |
1390 | .adjust_link = b53_adjust_link, | |
1391 | .port_enable = b53_enable_port, | |
1392 | .port_disable = b53_disable_port, | |
ff39c2d6 FF |
1393 | .port_bridge_join = b53_br_join, |
1394 | .port_bridge_leave = b53_br_leave, | |
1395 | .port_stp_state_set = b53_br_set_stp_state, | |
a2482d2c FF |
1396 | .port_vlan_filtering = b53_vlan_filtering, |
1397 | .port_vlan_prepare = b53_vlan_prepare, | |
1398 | .port_vlan_add = b53_vlan_add, | |
1399 | .port_vlan_del = b53_vlan_del, | |
1400 | .port_vlan_dump = b53_vlan_dump, | |
1da6df85 FF |
1401 | .port_fdb_prepare = b53_fdb_prepare, |
1402 | .port_fdb_dump = b53_fdb_dump, | |
1403 | .port_fdb_add = b53_fdb_add, | |
1404 | .port_fdb_del = b53_fdb_del, | |
967dd82f FF |
1405 | }; |
1406 | ||
1407 | struct b53_chip_data { | |
1408 | u32 chip_id; | |
1409 | const char *dev_name; | |
1410 | u16 vlans; | |
1411 | u16 enabled_ports; | |
1412 | u8 cpu_port; | |
1413 | u8 vta_regs[3]; | |
1da6df85 | 1414 | u8 arl_entries; |
967dd82f FF |
1415 | u8 duplex_reg; |
1416 | u8 jumbo_pm_reg; | |
1417 | u8 jumbo_size_reg; | |
1418 | }; | |
1419 | ||
1420 | #define B53_VTA_REGS \ | |
1421 | { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } | |
1422 | #define B53_VTA_REGS_9798 \ | |
1423 | { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } | |
1424 | #define B53_VTA_REGS_63XX \ | |
1425 | { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } | |
1426 | ||
1427 | static const struct b53_chip_data b53_switch_chips[] = { | |
1428 | { | |
1429 | .chip_id = BCM5325_DEVICE_ID, | |
1430 | .dev_name = "BCM5325", | |
1431 | .vlans = 16, | |
1432 | .enabled_ports = 0x1f, | |
1da6df85 | 1433 | .arl_entries = 2, |
967dd82f FF |
1434 | .cpu_port = B53_CPU_PORT_25, |
1435 | .duplex_reg = B53_DUPLEX_STAT_FE, | |
1436 | }, | |
1437 | { | |
1438 | .chip_id = BCM5365_DEVICE_ID, | |
1439 | .dev_name = "BCM5365", | |
1440 | .vlans = 256, | |
1441 | .enabled_ports = 0x1f, | |
1da6df85 | 1442 | .arl_entries = 2, |
967dd82f FF |
1443 | .cpu_port = B53_CPU_PORT_25, |
1444 | .duplex_reg = B53_DUPLEX_STAT_FE, | |
1445 | }, | |
1446 | { | |
1447 | .chip_id = BCM5395_DEVICE_ID, | |
1448 | .dev_name = "BCM5395", | |
1449 | .vlans = 4096, | |
1450 | .enabled_ports = 0x1f, | |
1da6df85 | 1451 | .arl_entries = 4, |
967dd82f FF |
1452 | .cpu_port = B53_CPU_PORT, |
1453 | .vta_regs = B53_VTA_REGS, | |
1454 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1455 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1456 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1457 | }, | |
1458 | { | |
1459 | .chip_id = BCM5397_DEVICE_ID, | |
1460 | .dev_name = "BCM5397", | |
1461 | .vlans = 4096, | |
1462 | .enabled_ports = 0x1f, | |
1da6df85 | 1463 | .arl_entries = 4, |
967dd82f FF |
1464 | .cpu_port = B53_CPU_PORT, |
1465 | .vta_regs = B53_VTA_REGS_9798, | |
1466 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1467 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1468 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1469 | }, | |
1470 | { | |
1471 | .chip_id = BCM5398_DEVICE_ID, | |
1472 | .dev_name = "BCM5398", | |
1473 | .vlans = 4096, | |
1474 | .enabled_ports = 0x7f, | |
1da6df85 | 1475 | .arl_entries = 4, |
967dd82f FF |
1476 | .cpu_port = B53_CPU_PORT, |
1477 | .vta_regs = B53_VTA_REGS_9798, | |
1478 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1479 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1480 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1481 | }, | |
1482 | { | |
1483 | .chip_id = BCM53115_DEVICE_ID, | |
1484 | .dev_name = "BCM53115", | |
1485 | .vlans = 4096, | |
1486 | .enabled_ports = 0x1f, | |
1da6df85 | 1487 | .arl_entries = 4, |
967dd82f FF |
1488 | .vta_regs = B53_VTA_REGS, |
1489 | .cpu_port = B53_CPU_PORT, | |
1490 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1491 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1492 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1493 | }, | |
1494 | { | |
1495 | .chip_id = BCM53125_DEVICE_ID, | |
1496 | .dev_name = "BCM53125", | |
1497 | .vlans = 4096, | |
1498 | .enabled_ports = 0xff, | |
1499 | .cpu_port = B53_CPU_PORT, | |
1500 | .vta_regs = B53_VTA_REGS, | |
1501 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1502 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1503 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1504 | }, | |
1505 | { | |
1506 | .chip_id = BCM53128_DEVICE_ID, | |
1507 | .dev_name = "BCM53128", | |
1508 | .vlans = 4096, | |
1509 | .enabled_ports = 0x1ff, | |
1da6df85 | 1510 | .arl_entries = 4, |
967dd82f FF |
1511 | .cpu_port = B53_CPU_PORT, |
1512 | .vta_regs = B53_VTA_REGS, | |
1513 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1514 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1515 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1516 | }, | |
1517 | { | |
1518 | .chip_id = BCM63XX_DEVICE_ID, | |
1519 | .dev_name = "BCM63xx", | |
1520 | .vlans = 4096, | |
1521 | .enabled_ports = 0, /* pdata must provide them */ | |
1da6df85 | 1522 | .arl_entries = 4, |
967dd82f FF |
1523 | .cpu_port = B53_CPU_PORT, |
1524 | .vta_regs = B53_VTA_REGS_63XX, | |
1525 | .duplex_reg = B53_DUPLEX_STAT_63XX, | |
1526 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, | |
1527 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, | |
1528 | }, | |
1529 | { | |
1530 | .chip_id = BCM53010_DEVICE_ID, | |
1531 | .dev_name = "BCM53010", | |
1532 | .vlans = 4096, | |
1533 | .enabled_ports = 0x1f, | |
1da6df85 | 1534 | .arl_entries = 4, |
967dd82f FF |
1535 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ |
1536 | .vta_regs = B53_VTA_REGS, | |
1537 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1538 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1539 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1540 | }, | |
1541 | { | |
1542 | .chip_id = BCM53011_DEVICE_ID, | |
1543 | .dev_name = "BCM53011", | |
1544 | .vlans = 4096, | |
1545 | .enabled_ports = 0x1bf, | |
1da6df85 | 1546 | .arl_entries = 4, |
967dd82f FF |
1547 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ |
1548 | .vta_regs = B53_VTA_REGS, | |
1549 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1550 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1551 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1552 | }, | |
1553 | { | |
1554 | .chip_id = BCM53012_DEVICE_ID, | |
1555 | .dev_name = "BCM53012", | |
1556 | .vlans = 4096, | |
1557 | .enabled_ports = 0x1bf, | |
1da6df85 | 1558 | .arl_entries = 4, |
967dd82f FF |
1559 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ |
1560 | .vta_regs = B53_VTA_REGS, | |
1561 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1562 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1563 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1564 | }, | |
1565 | { | |
1566 | .chip_id = BCM53018_DEVICE_ID, | |
1567 | .dev_name = "BCM53018", | |
1568 | .vlans = 4096, | |
1569 | .enabled_ports = 0x1f, | |
1da6df85 | 1570 | .arl_entries = 4, |
967dd82f FF |
1571 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ |
1572 | .vta_regs = B53_VTA_REGS, | |
1573 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1574 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1575 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1576 | }, | |
1577 | { | |
1578 | .chip_id = BCM53019_DEVICE_ID, | |
1579 | .dev_name = "BCM53019", | |
1580 | .vlans = 4096, | |
1581 | .enabled_ports = 0x1f, | |
1da6df85 | 1582 | .arl_entries = 4, |
967dd82f FF |
1583 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ |
1584 | .vta_regs = B53_VTA_REGS, | |
1585 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1586 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1587 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1588 | }, | |
991a36bb FF |
1589 | { |
1590 | .chip_id = BCM58XX_DEVICE_ID, | |
1591 | .dev_name = "BCM585xx/586xx/88312", | |
1592 | .vlans = 4096, | |
1593 | .enabled_ports = 0x1ff, | |
1594 | .arl_entries = 4, | |
1595 | .cpu_port = B53_CPU_PORT_25, | |
1596 | .vta_regs = B53_VTA_REGS, | |
1597 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1598 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1599 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1600 | }, | |
130401d9 FF |
1601 | { |
1602 | .chip_id = BCM7445_DEVICE_ID, | |
1603 | .dev_name = "BCM7445", | |
1604 | .vlans = 4096, | |
1605 | .enabled_ports = 0x1ff, | |
1606 | .arl_entries = 4, | |
1607 | .cpu_port = B53_CPU_PORT, | |
1608 | .vta_regs = B53_VTA_REGS, | |
1609 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
1610 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
1611 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
1612 | }, | |
967dd82f FF |
1613 | }; |
1614 | ||
1615 | static int b53_switch_init(struct b53_device *dev) | |
1616 | { | |
967dd82f FF |
1617 | unsigned int i; |
1618 | int ret; | |
1619 | ||
1620 | for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { | |
1621 | const struct b53_chip_data *chip = &b53_switch_chips[i]; | |
1622 | ||
1623 | if (chip->chip_id == dev->chip_id) { | |
1624 | if (!dev->enabled_ports) | |
1625 | dev->enabled_ports = chip->enabled_ports; | |
1626 | dev->name = chip->dev_name; | |
1627 | dev->duplex_reg = chip->duplex_reg; | |
1628 | dev->vta_regs[0] = chip->vta_regs[0]; | |
1629 | dev->vta_regs[1] = chip->vta_regs[1]; | |
1630 | dev->vta_regs[2] = chip->vta_regs[2]; | |
1631 | dev->jumbo_pm_reg = chip->jumbo_pm_reg; | |
967dd82f FF |
1632 | dev->cpu_port = chip->cpu_port; |
1633 | dev->num_vlans = chip->vlans; | |
1da6df85 | 1634 | dev->num_arl_entries = chip->arl_entries; |
967dd82f FF |
1635 | break; |
1636 | } | |
1637 | } | |
1638 | ||
1639 | /* check which BCM5325x version we have */ | |
1640 | if (is5325(dev)) { | |
1641 | u8 vc4; | |
1642 | ||
1643 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); | |
1644 | ||
1645 | /* check reserved bits */ | |
1646 | switch (vc4 & 3) { | |
1647 | case 1: | |
1648 | /* BCM5325E */ | |
1649 | break; | |
1650 | case 3: | |
1651 | /* BCM5325F - do not use port 4 */ | |
1652 | dev->enabled_ports &= ~BIT(4); | |
1653 | break; | |
1654 | default: | |
1655 | /* On the BCM47XX SoCs this is the supported internal switch.*/ | |
1656 | #ifndef CONFIG_BCM47XX | |
1657 | /* BCM5325M */ | |
1658 | return -EINVAL; | |
1659 | #else | |
1660 | break; | |
1661 | #endif | |
1662 | } | |
1663 | } else if (dev->chip_id == BCM53115_DEVICE_ID) { | |
1664 | u64 strap_value; | |
1665 | ||
1666 | b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); | |
1667 | /* use second IMP port if GMII is enabled */ | |
1668 | if (strap_value & SV_GMII_CTRL_115) | |
1669 | dev->cpu_port = 5; | |
1670 | } | |
1671 | ||
1672 | /* cpu port is always last */ | |
1673 | dev->num_ports = dev->cpu_port + 1; | |
1674 | dev->enabled_ports |= BIT(dev->cpu_port); | |
1675 | ||
1676 | dev->ports = devm_kzalloc(dev->dev, | |
1677 | sizeof(struct b53_port) * dev->num_ports, | |
1678 | GFP_KERNEL); | |
1679 | if (!dev->ports) | |
1680 | return -ENOMEM; | |
1681 | ||
a2482d2c FF |
1682 | dev->vlans = devm_kzalloc(dev->dev, |
1683 | sizeof(struct b53_vlan) * dev->num_vlans, | |
1684 | GFP_KERNEL); | |
1685 | if (!dev->vlans) | |
1686 | return -ENOMEM; | |
1687 | ||
967dd82f FF |
1688 | dev->reset_gpio = b53_switch_get_reset_gpio(dev); |
1689 | if (dev->reset_gpio >= 0) { | |
1690 | ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, | |
1691 | GPIOF_OUT_INIT_HIGH, "robo_reset"); | |
1692 | if (ret) | |
1693 | return ret; | |
1694 | } | |
1695 | ||
1696 | return 0; | |
1697 | } | |
1698 | ||
0dff88d3 JL |
1699 | struct b53_device *b53_switch_alloc(struct device *base, |
1700 | const struct b53_io_ops *ops, | |
967dd82f FF |
1701 | void *priv) |
1702 | { | |
1703 | struct dsa_switch *ds; | |
1704 | struct b53_device *dev; | |
1705 | ||
1706 | ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL); | |
1707 | if (!ds) | |
1708 | return NULL; | |
1709 | ||
1710 | dev = (struct b53_device *)(ds + 1); | |
1711 | ||
1712 | ds->priv = dev; | |
1713 | ds->dev = base; | |
1714 | dev->dev = base; | |
1715 | ||
1716 | dev->ds = ds; | |
1717 | dev->priv = priv; | |
1718 | dev->ops = ops; | |
485ebd61 | 1719 | ds->ops = &b53_switch_ops; |
967dd82f FF |
1720 | mutex_init(&dev->reg_mutex); |
1721 | mutex_init(&dev->stats_mutex); | |
1722 | ||
1723 | return dev; | |
1724 | } | |
1725 | EXPORT_SYMBOL(b53_switch_alloc); | |
1726 | ||
1727 | int b53_switch_detect(struct b53_device *dev) | |
1728 | { | |
1729 | u32 id32; | |
1730 | u16 tmp; | |
1731 | u8 id8; | |
1732 | int ret; | |
1733 | ||
1734 | ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); | |
1735 | if (ret) | |
1736 | return ret; | |
1737 | ||
1738 | switch (id8) { | |
1739 | case 0: | |
1740 | /* BCM5325 and BCM5365 do not have this register so reads | |
1741 | * return 0. But the read operation did succeed, so assume this | |
1742 | * is one of them. | |
1743 | * | |
1744 | * Next check if we can write to the 5325's VTA register; for | |
1745 | * 5365 it is read only. | |
1746 | */ | |
1747 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); | |
1748 | b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); | |
1749 | ||
1750 | if (tmp == 0xf) | |
1751 | dev->chip_id = BCM5325_DEVICE_ID; | |
1752 | else | |
1753 | dev->chip_id = BCM5365_DEVICE_ID; | |
1754 | break; | |
1755 | case BCM5395_DEVICE_ID: | |
1756 | case BCM5397_DEVICE_ID: | |
1757 | case BCM5398_DEVICE_ID: | |
1758 | dev->chip_id = id8; | |
1759 | break; | |
1760 | default: | |
1761 | ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); | |
1762 | if (ret) | |
1763 | return ret; | |
1764 | ||
1765 | switch (id32) { | |
1766 | case BCM53115_DEVICE_ID: | |
1767 | case BCM53125_DEVICE_ID: | |
1768 | case BCM53128_DEVICE_ID: | |
1769 | case BCM53010_DEVICE_ID: | |
1770 | case BCM53011_DEVICE_ID: | |
1771 | case BCM53012_DEVICE_ID: | |
1772 | case BCM53018_DEVICE_ID: | |
1773 | case BCM53019_DEVICE_ID: | |
1774 | dev->chip_id = id32; | |
1775 | break; | |
1776 | default: | |
1777 | pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", | |
1778 | id8, id32); | |
1779 | return -ENODEV; | |
1780 | } | |
1781 | } | |
1782 | ||
1783 | if (dev->chip_id == BCM5325_DEVICE_ID) | |
1784 | return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, | |
1785 | &dev->core_rev); | |
1786 | else | |
1787 | return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, | |
1788 | &dev->core_rev); | |
1789 | } | |
1790 | EXPORT_SYMBOL(b53_switch_detect); | |
1791 | ||
1792 | int b53_switch_register(struct b53_device *dev) | |
1793 | { | |
1794 | int ret; | |
1795 | ||
1796 | if (dev->pdata) { | |
1797 | dev->chip_id = dev->pdata->chip_id; | |
1798 | dev->enabled_ports = dev->pdata->enabled_ports; | |
1799 | } | |
1800 | ||
1801 | if (!dev->chip_id && b53_switch_detect(dev)) | |
1802 | return -EINVAL; | |
1803 | ||
1804 | ret = b53_switch_init(dev); | |
1805 | if (ret) | |
1806 | return ret; | |
1807 | ||
1808 | pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); | |
1809 | ||
1810 | return dsa_register_switch(dev->ds, dev->ds->dev->of_node); | |
1811 | } | |
1812 | EXPORT_SYMBOL(b53_switch_register); | |
1813 | ||
1814 | MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); | |
1815 | MODULE_DESCRIPTION("B53 switch library"); | |
1816 | MODULE_LICENSE("Dual BSD/GPL"); |