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net: dsa: b53: Implement ARL add/del/dump operations
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
967dd82f 30#include <net/dsa.h>
1da6df85 31#include <net/switchdev.h>
967dd82f
FF		 32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
169static int b53_do_vlan_op(struct b53_device *dev, u8 op)
170{
171 unsigned int i;
172
173 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
174
175 for (i = 0; i < 10; i++) {
176 u8 vta;
177
178 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
179 if (!(vta & VTA_START_CMD))
180 return 0;
181
182 usleep_range(100, 200);
183 }
184
185 return -EIO;
186}
187
188static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
189 u16 untag)
190{
191 if (is5325(dev)) {
192 u32 entry = 0;
193
194 if (members) {
195 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
196 members;
197 if (dev->core_rev >= 3)
198 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
199 else
200 entry |= VA_VALID_25;
201 }
202
203 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
204 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
205 VTA_RW_STATE_WR | VTA_RW_OP_EN);
206 } else if (is5365(dev)) {
207 u16 entry = 0;
208
209 if (members)
210 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
211 members | VA_VALID_65;
212
213 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
214 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
215 VTA_RW_STATE_WR | VTA_RW_OP_EN);
216 } else {
217 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
218 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
219 (untag << VTE_UNTAG_S) | members);
220
221 b53_do_vlan_op(dev, VTA_CMD_WRITE);
222 }
223}
224
225void b53_set_forwarding(struct b53_device *dev, int enable)
226{
227 u8 mgmt;
228
229 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
230
231 if (enable)
232 mgmt |= SM_SW_FWD_EN;
233 else
234 mgmt &= ~SM_SW_FWD_EN;
235
236 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
237}
238
239static void b53_enable_vlan(struct b53_device *dev, int enable)
240{
241 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
242
243 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
244 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
246
247 if (is5325(dev) || is5365(dev)) {
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
250 } else if (is63xx(dev)) {
251 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
253 } else {
254 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
255 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
256 }
257
258 mgmt &= ~SM_SW_FWD_MODE;
259
260 if (enable) {
261 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
262 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
263 vc4 &= ~VC4_ING_VID_CHECK_MASK;
264 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
265 vc5 |= VC5_DROP_VTABLE_MISS;
266
267 if (is5325(dev))
268 vc0 &= ~VC0_RESERVED_1;
269
270 if (is5325(dev) || is5365(dev))
271 vc1 |= VC1_RX_MCST_TAG_EN;
272
273 if (!is5325(dev) && !is5365(dev)) {
274 if (dev->allow_vid_4095)
275 vc5 |= VC5_VID_FFF_EN;
276 else
277 vc5 &= ~VC5_VID_FFF_EN;
278 }
279 } else {
280 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
281 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
282 vc4 &= ~VC4_ING_VID_CHECK_MASK;
283 vc5 &= ~VC5_DROP_VTABLE_MISS;
284
285 if (is5325(dev) || is5365(dev))
286 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
287 else
288 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
289
290 if (is5325(dev) || is5365(dev))
291 vc1 &= ~VC1_RX_MCST_TAG_EN;
292
293 if (!is5325(dev) && !is5365(dev))
294 vc5 &= ~VC5_VID_FFF_EN;
295 }
296
297 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
298 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
299
300 if (is5325(dev) || is5365(dev)) {
301 /* enable the high 8 bit vid check on 5325 */
302 if (is5325(dev) && enable)
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
304 VC3_HIGH_8BIT_EN);
305 else
306 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
307
308 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
309 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
310 } else if (is63xx(dev)) {
311 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
312 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
314 } else {
315 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
316 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
317 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
318 }
319
320 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
321}
322
323static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
324{
325 u32 port_mask = 0;
326 u16 max_size = JMS_MIN_SIZE;
327
328 if (is5325(dev) || is5365(dev))
329 return -EINVAL;
330
331 if (enable) {
332 port_mask = dev->enabled_ports;
333 max_size = JMS_MAX_SIZE;
334 if (allow_10_100)
335 port_mask |= JPM_10_100_JUMBO_EN;
336 }
337
338 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
339 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
340}
341
342static int b53_flush_arl(struct b53_device *dev)
343{
344 unsigned int i;
345
346 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
347 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
348
349 for (i = 0; i < 10; i++) {
350 u8 fast_age_ctrl;
351
352 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
353 &fast_age_ctrl);
354
355 if (!(fast_age_ctrl & FAST_AGE_DONE))
356 goto out;
357
358 msleep(1);
359 }
360
361 return -ETIMEDOUT;
362out:
363 /* Only age dynamic entries (default behavior) */
364 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
365 return 0;
366}
367
368static int b53_enable_port(struct dsa_switch *ds, int port,
369 struct phy_device *phy)
370{
371 struct b53_device *dev = ds_to_priv(ds);
372
373 /* Clear the Rx and Tx disable bits and set to no spanning tree */
374 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
375
376 return 0;
377}
378
379static void b53_disable_port(struct dsa_switch *ds, int port,
380 struct phy_device *phy)
381{
382 struct b53_device *dev = ds_to_priv(ds);
383 u8 reg;
384
385 /* Disable Tx/Rx for the port */
386 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
387 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
388 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
389}
390
391static void b53_enable_cpu_port(struct b53_device *dev)
392{
393 unsigned int cpu_port = dev->cpu_port;
394 u8 port_ctrl;
395
396 /* BCM5325 CPU port is at 8 */
397 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
398 cpu_port = B53_CPU_PORT;
399
400 port_ctrl = PORT_CTRL_RX_BCST_EN |
401 PORT_CTRL_RX_MCST_EN |
402 PORT_CTRL_RX_UCST_EN;
403 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
404}
405
406static void b53_enable_mib(struct b53_device *dev)
407{
408 u8 gc;
409
410 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
411 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
412 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
413}
414
415static int b53_configure_vlan(struct b53_device *dev)
416{
417 int i;
418
419 /* clear all vlan entries */
420 if (is5325(dev) || is5365(dev)) {
421 for (i = 1; i < dev->num_vlans; i++)
422 b53_set_vlan_entry(dev, i, 0, 0);
423 } else {
424 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
425 }
426
427 b53_enable_vlan(dev, false);
428
429 b53_for_each_port(dev, i)
430 b53_write16(dev, B53_VLAN_PAGE,
431 B53_VLAN_PORT_DEF_TAG(i), 1);
432
433 if (!is5325(dev) && !is5365(dev))
434 b53_set_jumbo(dev, dev->enable_jumbo, false);
435
436 return 0;
437}
438
439static void b53_switch_reset_gpio(struct b53_device *dev)
440{
441 int gpio = dev->reset_gpio;
442
443 if (gpio < 0)
444 return;
445
446 /* Reset sequence: RESET low(50ms)->high(20ms)
447 */
448 gpio_set_value(gpio, 0);
449 mdelay(50);
450
451 gpio_set_value(gpio, 1);
452 mdelay(20);
453
454 dev->current_page = 0xff;
455}
456
457static int b53_switch_reset(struct b53_device *dev)
458{
459 u8 mgmt;
460
461 b53_switch_reset_gpio(dev);
462
463 if (is539x(dev)) {
464 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
465 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
466 }
467
468 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
469
470 if (!(mgmt & SM_SW_FWD_EN)) {
471 mgmt &= ~SM_SW_FWD_MODE;
472 mgmt |= SM_SW_FWD_EN;
473
474 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
475 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
476
477 if (!(mgmt & SM_SW_FWD_EN)) {
478 dev_err(dev->dev, "Failed to enable switch!\n");
479 return -EINVAL;
480 }
481 }
482
483 b53_enable_mib(dev);
484
485 return b53_flush_arl(dev);
486}
487
488static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
489{
490 struct b53_device *priv = ds_to_priv(ds);
491 u16 value = 0;
492 int ret;
493
494 if (priv->ops->phy_read16)
495 ret = priv->ops->phy_read16(priv, addr, reg, &value);
496 else
497 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
498 reg * 2, &value);
499
500 return ret ? ret : value;
501}
502
503static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
504{
505 struct b53_device *priv = ds_to_priv(ds);
506
507 if (priv->ops->phy_write16)
508 return priv->ops->phy_write16(priv, addr, reg, val);
509
510 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
511}
512
513static int b53_reset_switch(struct b53_device *priv)
514{
515 /* reset vlans */
516 priv->enable_jumbo = false;
517
518 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
519
520 return b53_switch_reset(priv);
521}
522
523static int b53_apply_config(struct b53_device *priv)
524{
525 /* disable switching */
526 b53_set_forwarding(priv, 0);
527
528 b53_configure_vlan(priv);
529
530 /* enable switching */
531 b53_set_forwarding(priv, 1);
532
533 return 0;
534}
535
536static void b53_reset_mib(struct b53_device *priv)
537{
538 u8 gc;
539
540 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
541
542 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
543 msleep(1);
544 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
545 msleep(1);
546}
547
548static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
549{
550 if (is5365(dev))
551 return b53_mibs_65;
552 else if (is63xx(dev))
553 return b53_mibs_63xx;
554 else
555 return b53_mibs;
556}
557
558static unsigned int b53_get_mib_size(struct b53_device *dev)
559{
560 if (is5365(dev))
561 return B53_MIBS_65_SIZE;
562 else if (is63xx(dev))
563 return B53_MIBS_63XX_SIZE;
564 else
565 return B53_MIBS_SIZE;
566}
567
568static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
569{
570 struct b53_device *dev = ds_to_priv(ds);
571 const struct b53_mib_desc *mibs = b53_get_mib(dev);
572 unsigned int mib_size = b53_get_mib_size(dev);
573 unsigned int i;
574
575 for (i = 0; i < mib_size; i++)
576 memcpy(data + i * ETH_GSTRING_LEN,
577 mibs[i].name, ETH_GSTRING_LEN);
578}
579
580static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
581 uint64_t *data)
582{
583 struct b53_device *dev = ds_to_priv(ds);
584 const struct b53_mib_desc *mibs = b53_get_mib(dev);
585 unsigned int mib_size = b53_get_mib_size(dev);
586 const struct b53_mib_desc *s;
587 unsigned int i;
588 u64 val = 0;
589
590 if (is5365(dev) && port == 5)
591 port = 8;
592
593 mutex_lock(&dev->stats_mutex);
594
595 for (i = 0; i < mib_size; i++) {
596 s = &mibs[i];
597
598 if (mibs->size == 8) {
599 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
600 } else {
601 u32 val32;
602
603 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
604 &val32);
605 val = val32;
606 }
607 data[i] = (u64)val;
608 }
609
610 mutex_unlock(&dev->stats_mutex);
611}
612
613static int b53_get_sset_count(struct dsa_switch *ds)
614{
615 struct b53_device *dev = ds_to_priv(ds);
616
617 return b53_get_mib_size(dev);
618}
619
620static int b53_set_addr(struct dsa_switch *ds, u8 *addr)
621{
622 return 0;
623}
624
625static int b53_setup(struct dsa_switch *ds)
626{
627 struct b53_device *dev = ds_to_priv(ds);
628 unsigned int port;
629 int ret;
630
631 ret = b53_reset_switch(dev);
632 if (ret) {
633 dev_err(ds->dev, "failed to reset switch\n");
634 return ret;
635 }
636
637 b53_reset_mib(dev);
638
639 ret = b53_apply_config(dev);
640 if (ret)
641 dev_err(ds->dev, "failed to apply configuration\n");
642
643 for (port = 0; port < dev->num_ports; port++) {
644 if (BIT(port) & ds->enabled_port_mask)
645 b53_enable_port(ds, port, NULL);
646 else if (dsa_is_cpu_port(ds, port))
647 b53_enable_cpu_port(dev);
648 else
649 b53_disable_port(ds, port, NULL);
650 }
651
652 return ret;
653}
654
655static void b53_adjust_link(struct dsa_switch *ds, int port,
656 struct phy_device *phydev)
657{
658 struct b53_device *dev = ds_to_priv(ds);
659 u8 rgmii_ctrl = 0, reg = 0, off;
660
661 if (!phy_is_pseudo_fixed_link(phydev))
662 return;
663
664 /* Override the port settings */
665 if (port == dev->cpu_port) {
666 off = B53_PORT_OVERRIDE_CTRL;
667 reg = PORT_OVERRIDE_EN;
668 } else {
669 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
670 reg = GMII_PO_EN;
671 }
672
673 /* Set the link UP */
674 if (phydev->link)
675 reg |= PORT_OVERRIDE_LINK;
676
677 if (phydev->duplex == DUPLEX_FULL)
678 reg |= PORT_OVERRIDE_FULL_DUPLEX;
679
680 switch (phydev->speed) {
681 case 2000:
682 reg |= PORT_OVERRIDE_SPEED_2000M;
683 /* fallthrough */
684 case SPEED_1000:
685 reg |= PORT_OVERRIDE_SPEED_1000M;
686 break;
687 case SPEED_100:
688 reg |= PORT_OVERRIDE_SPEED_100M;
689 break;
690 case SPEED_10:
691 reg |= PORT_OVERRIDE_SPEED_10M;
692 break;
693 default:
694 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
695 return;
696 }
697
698 /* Enable flow control on BCM5301x's CPU port */
699 if (is5301x(dev) && port == dev->cpu_port)
700 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
701
702 if (phydev->pause) {
703 if (phydev->asym_pause)
704 reg |= PORT_OVERRIDE_TX_FLOW;
705 reg |= PORT_OVERRIDE_RX_FLOW;
706 }
707
708 b53_write8(dev, B53_CTRL_PAGE, off, reg);
709
710 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
711 if (port == 8)
712 off = B53_RGMII_CTRL_IMP;
713 else
714 off = B53_RGMII_CTRL_P(port);
715
716 /* Configure the port RGMII clock delay by DLL disabled and
717 * tx_clk aligned timing (restoring to reset defaults)
718 */
719 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
720 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
721 RGMII_CTRL_TIMING_SEL);
722
723 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
724 * sure that we enable the port TX clock internal delay to
725 * account for this internal delay that is inserted, otherwise
726 * the switch won't be able to receive correctly.
727 *
728 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
729 * any delay neither on transmission nor reception, so the
730 * BCM53125 must also be configured accordingly to account for
731 * the lack of delay and introduce
732 *
733 * The BCM53125 switch has its RX clock and TX clock control
734 * swapped, hence the reason why we modify the TX clock path in
735 * the "RGMII" case
736 */
737 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
738 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
739 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
740 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
741 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
742 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
743
744 dev_info(ds->dev, "Configured port %d for %s\n", port,
745 phy_modes(phydev->interface));
746 }
747
748 /* configure MII port if necessary */
749 if (is5325(dev)) {
750 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
751 &reg);
752
753 /* reverse mii needs to be enabled */
754 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
755 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
756 reg | PORT_OVERRIDE_RV_MII_25);
757 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
758 &reg);
759
760 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
761 dev_err(ds->dev,
762 "Failed to enable reverse MII mode\n");
763 return;
764 }
765 }
766 } else if (is5301x(dev)) {
767 if (port != dev->cpu_port) {
768 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
769 u8 gmii_po;
770
771 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
772 gmii_po |= GMII_PO_LINK |
773 GMII_PO_RX_FLOW |
774 GMII_PO_TX_FLOW |
775 GMII_PO_EN |
776 GMII_PO_SPEED_2000M;
777 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
778 }
779 }
780}
781
1da6df85
FF		 782/* Address Resolution Logic routines */
783static int b53_arl_op_wait(struct b53_device *dev)
784{
785 unsigned int timeout = 10;
786 u8 reg;
787
788 do {
789 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
790 if (!(reg & ARLTBL_START_DONE))
791 return 0;
792
793 usleep_range(1000, 2000);
794 } while (timeout--);
795
796 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
797
798 return -ETIMEDOUT;
799}
800
801static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
802{
803 u8 reg;
804
805 if (op > ARLTBL_RW)
806 return -EINVAL;
807
808 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
809 reg |= ARLTBL_START_DONE;
810 if (op)
811 reg |= ARLTBL_RW;
812 else
813 reg &= ~ARLTBL_RW;
814 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
815
816 return b53_arl_op_wait(dev);
817}
818
819static int b53_arl_read(struct b53_device *dev, u64 mac,
820 u16 vid, struct b53_arl_entry *ent, u8 *idx,
821 bool is_valid)
822{
823 unsigned int i;
824 int ret;
825
826 ret = b53_arl_op_wait(dev);
827 if (ret)
828 return ret;
829
830 /* Read the bins */
831 for (i = 0; i < dev->num_arl_entries; i++) {
832 u64 mac_vid;
833 u32 fwd_entry;
834
835 b53_read64(dev, B53_ARLIO_PAGE,
836 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
837 b53_read32(dev, B53_ARLIO_PAGE,
838 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
839 b53_arl_to_entry(ent, mac_vid, fwd_entry);
840
841 if (!(fwd_entry & ARLTBL_VALID))
842 continue;
843 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
844 continue;
845 *idx = i;
846 }
847
848 return -ENOENT;
849}
850
851static int b53_arl_op(struct b53_device *dev, int op, int port,
852 const unsigned char *addr, u16 vid, bool is_valid)
853{
854 struct b53_arl_entry ent;
855 u32 fwd_entry;
856 u64 mac, mac_vid = 0;
857 u8 idx = 0;
858 int ret;
859
860 /* Convert the array into a 64-bit MAC */
861 mac = b53_mac_to_u64(addr);
862
863 /* Perform a read for the given MAC and VID */
864 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
865 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
866
867 /* Issue a read operation for this MAC */
868 ret = b53_arl_rw_op(dev, 1);
869 if (ret)
870 return ret;
871
872 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
873 /* If this is a read, just finish now */
874 if (op)
875 return ret;
876
877 /* We could not find a matching MAC, so reset to a new entry */
878 if (ret) {
879 fwd_entry = 0;
880 idx = 1;
881 }
882
883 memset(&ent, 0, sizeof(ent));
884 ent.port = port;
885 ent.is_valid = is_valid;
886 ent.vid = vid;
887 ent.is_static = true;
888 memcpy(ent.mac, addr, ETH_ALEN);
889 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
890
891 b53_write64(dev, B53_ARLIO_PAGE,
892 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
893 b53_write32(dev, B53_ARLIO_PAGE,
894 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
895
896 return b53_arl_rw_op(dev, 0);
897}
898
899static int b53_fdb_prepare(struct dsa_switch *ds, int port,
900 const struct switchdev_obj_port_fdb *fdb,
901 struct switchdev_trans *trans)
902{
903 struct b53_device *priv = ds_to_priv(ds);
904
905 /* 5325 and 5365 require some more massaging, but could
906 * be supported eventually
907 */
908 if (is5325(priv) || is5365(priv))
909 return -EOPNOTSUPP;
910
911 return 0;
912}
913
914static void b53_fdb_add(struct dsa_switch *ds, int port,
915 const struct switchdev_obj_port_fdb *fdb,
916 struct switchdev_trans *trans)
917{
918 struct b53_device *priv = ds_to_priv(ds);
919
920 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
921 pr_err("%s: failed to add MAC address\n", __func__);
922}
923
924static int b53_fdb_del(struct dsa_switch *ds, int port,
925 const struct switchdev_obj_port_fdb *fdb)
926{
927 struct b53_device *priv = ds_to_priv(ds);
928
929 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
930}
931
932static int b53_arl_search_wait(struct b53_device *dev)
933{
934 unsigned int timeout = 1000;
935 u8 reg;
936
937 do {
938 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
939 if (!(reg & ARL_SRCH_STDN))
940 return 0;
941
942 if (reg & ARL_SRCH_VLID)
943 return 0;
944
945 usleep_range(1000, 2000);
946 } while (timeout--);
947
948 return -ETIMEDOUT;
949}
950
951static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
952 struct b53_arl_entry *ent)
953{
954 u64 mac_vid;
955 u32 fwd_entry;
956
957 b53_read64(dev, B53_ARLIO_PAGE,
958 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
959 b53_read32(dev, B53_ARLIO_PAGE,
960 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
961 b53_arl_to_entry(ent, mac_vid, fwd_entry);
962}
963
964static int b53_fdb_copy(struct net_device *dev, int port,
965 const struct b53_arl_entry *ent,
966 struct switchdev_obj_port_fdb *fdb,
967 int (*cb)(struct switchdev_obj *obj))
968{
969 if (!ent->is_valid)
970 return 0;
971
972 if (port != ent->port)
973 return 0;
974
975 ether_addr_copy(fdb->addr, ent->mac);
976 fdb->vid = ent->vid;
977 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
978
979 return cb(&fdb->obj);
980}
981
982static int b53_fdb_dump(struct dsa_switch *ds, int port,
983 struct switchdev_obj_port_fdb *fdb,
984 int (*cb)(struct switchdev_obj *obj))
985{
986 struct b53_device *priv = ds_to_priv(ds);
987 struct net_device *dev = ds->ports[port].netdev;
988 struct b53_arl_entry results[2];
989 unsigned int count = 0;
990 int ret;
991 u8 reg;
992
993 /* Start search operation */
994 reg = ARL_SRCH_STDN;
995 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
996
997 do {
998 ret = b53_arl_search_wait(priv);
999 if (ret)
1000 return ret;
1001
1002 b53_arl_search_rd(priv, 0, &results[0]);
1003 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1004 if (ret)
1005 return ret;
1006
1007 if (priv->num_arl_entries > 2) {
1008 b53_arl_search_rd(priv, 1, &results[1]);
1009 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1010 if (ret)
1011 return ret;
1012
1013 if (!results[0].is_valid && !results[1].is_valid)
1014 break;
1015 }
1016
1017 } while (count++ < 1024);
1018
1019 return 0;
1020}
1021
967dd82f
FF		 1022static struct dsa_switch_driver b53_switch_ops = {
1023 .tag_protocol = DSA_TAG_PROTO_NONE,
1024 .setup = b53_setup,
1025 .set_addr = b53_set_addr,
1026 .get_strings = b53_get_strings,
1027 .get_ethtool_stats = b53_get_ethtool_stats,
1028 .get_sset_count = b53_get_sset_count,
1029 .phy_read = b53_phy_read16,
1030 .phy_write = b53_phy_write16,
1031 .adjust_link = b53_adjust_link,
1032 .port_enable = b53_enable_port,
1033 .port_disable = b53_disable_port,
1da6df85
FF		 1034 .port_fdb_prepare = b53_fdb_prepare,
1035 .port_fdb_dump = b53_fdb_dump,
1036 .port_fdb_add = b53_fdb_add,
1037 .port_fdb_del = b53_fdb_del,
967dd82f
FF		 1038};
1039
1040struct b53_chip_data {
1041 u32 chip_id;
1042 const char *dev_name;
1043 u16 vlans;
1044 u16 enabled_ports;
1045 u8 cpu_port;
1046 u8 vta_regs[3];
1da6df85 1047 u8 arl_entries;
967dd82f
FF		 1048 u8 duplex_reg;
1049 u8 jumbo_pm_reg;
1050 u8 jumbo_size_reg;
1051};
1052
1053#define B53_VTA_REGS \
1054 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1055#define B53_VTA_REGS_9798 \
1056 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1057#define B53_VTA_REGS_63XX \
1058 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1059
1060static const struct b53_chip_data b53_switch_chips[] = {
1061 {
1062 .chip_id = BCM5325_DEVICE_ID,
1063 .dev_name = "BCM5325",
1064 .vlans = 16,
1065 .enabled_ports = 0x1f,
1da6df85 1066 .arl_entries = 2,
967dd82f
FF		 1067 .cpu_port = B53_CPU_PORT_25,
1068 .duplex_reg = B53_DUPLEX_STAT_FE,
1069 },
1070 {
1071 .chip_id = BCM5365_DEVICE_ID,
1072 .dev_name = "BCM5365",
1073 .vlans = 256,
1074 .enabled_ports = 0x1f,
1da6df85 1075 .arl_entries = 2,
967dd82f
FF		 1076 .cpu_port = B53_CPU_PORT_25,
1077 .duplex_reg = B53_DUPLEX_STAT_FE,
1078 },
1079 {
1080 .chip_id = BCM5395_DEVICE_ID,
1081 .dev_name = "BCM5395",
1082 .vlans = 4096,
1083 .enabled_ports = 0x1f,
1da6df85 1084 .arl_entries = 4,
967dd82f
FF		 1085 .cpu_port = B53_CPU_PORT,
1086 .vta_regs = B53_VTA_REGS,
1087 .duplex_reg = B53_DUPLEX_STAT_GE,
1088 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1089 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1090 },
1091 {
1092 .chip_id = BCM5397_DEVICE_ID,
1093 .dev_name = "BCM5397",
1094 .vlans = 4096,
1095 .enabled_ports = 0x1f,
1da6df85 1096 .arl_entries = 4,
967dd82f
FF		 1097 .cpu_port = B53_CPU_PORT,
1098 .vta_regs = B53_VTA_REGS_9798,
1099 .duplex_reg = B53_DUPLEX_STAT_GE,
1100 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1101 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1102 },
1103 {
1104 .chip_id = BCM5398_DEVICE_ID,
1105 .dev_name = "BCM5398",
1106 .vlans = 4096,
1107 .enabled_ports = 0x7f,
1da6df85 1108 .arl_entries = 4,
967dd82f
FF		 1109 .cpu_port = B53_CPU_PORT,
1110 .vta_regs = B53_VTA_REGS_9798,
1111 .duplex_reg = B53_DUPLEX_STAT_GE,
1112 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1113 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1114 },
1115 {
1116 .chip_id = BCM53115_DEVICE_ID,
1117 .dev_name = "BCM53115",
1118 .vlans = 4096,
1119 .enabled_ports = 0x1f,
1da6df85 1120 .arl_entries = 4,
967dd82f
FF		 1121 .vta_regs = B53_VTA_REGS,
1122 .cpu_port = B53_CPU_PORT,
1123 .duplex_reg = B53_DUPLEX_STAT_GE,
1124 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1125 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1126 },
1127 {
1128 .chip_id = BCM53125_DEVICE_ID,
1129 .dev_name = "BCM53125",
1130 .vlans = 4096,
1131 .enabled_ports = 0xff,
1132 .cpu_port = B53_CPU_PORT,
1133 .vta_regs = B53_VTA_REGS,
1134 .duplex_reg = B53_DUPLEX_STAT_GE,
1135 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1136 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1137 },
1138 {
1139 .chip_id = BCM53128_DEVICE_ID,
1140 .dev_name = "BCM53128",
1141 .vlans = 4096,
1142 .enabled_ports = 0x1ff,
1da6df85 1143 .arl_entries = 4,
967dd82f
FF		 1144 .cpu_port = B53_CPU_PORT,
1145 .vta_regs = B53_VTA_REGS,
1146 .duplex_reg = B53_DUPLEX_STAT_GE,
1147 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1148 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1149 },
1150 {
1151 .chip_id = BCM63XX_DEVICE_ID,
1152 .dev_name = "BCM63xx",
1153 .vlans = 4096,
1154 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1155 .arl_entries = 4,
967dd82f
FF		 1156 .cpu_port = B53_CPU_PORT,
1157 .vta_regs = B53_VTA_REGS_63XX,
1158 .duplex_reg = B53_DUPLEX_STAT_63XX,
1159 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1160 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1161 },
1162 {
1163 .chip_id = BCM53010_DEVICE_ID,
1164 .dev_name = "BCM53010",
1165 .vlans = 4096,
1166 .enabled_ports = 0x1f,
1da6df85 1167 .arl_entries = 4,
967dd82f
FF		 1168 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1169 .vta_regs = B53_VTA_REGS,
1170 .duplex_reg = B53_DUPLEX_STAT_GE,
1171 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1172 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1173 },
1174 {
1175 .chip_id = BCM53011_DEVICE_ID,
1176 .dev_name = "BCM53011",
1177 .vlans = 4096,
1178 .enabled_ports = 0x1bf,
1da6df85 1179 .arl_entries = 4,
967dd82f
FF		 1180 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1181 .vta_regs = B53_VTA_REGS,
1182 .duplex_reg = B53_DUPLEX_STAT_GE,
1183 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1184 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1185 },
1186 {
1187 .chip_id = BCM53012_DEVICE_ID,
1188 .dev_name = "BCM53012",
1189 .vlans = 4096,
1190 .enabled_ports = 0x1bf,
1da6df85 1191 .arl_entries = 4,
967dd82f
FF		 1192 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1193 .vta_regs = B53_VTA_REGS,
1194 .duplex_reg = B53_DUPLEX_STAT_GE,
1195 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1196 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1197 },
1198 {
1199 .chip_id = BCM53018_DEVICE_ID,
1200 .dev_name = "BCM53018",
1201 .vlans = 4096,
1202 .enabled_ports = 0x1f,
1da6df85 1203 .arl_entries = 4,
967dd82f
FF		 1204 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1205 .vta_regs = B53_VTA_REGS,
1206 .duplex_reg = B53_DUPLEX_STAT_GE,
1207 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1208 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1209 },
1210 {
1211 .chip_id = BCM53019_DEVICE_ID,
1212 .dev_name = "BCM53019",
1213 .vlans = 4096,
1214 .enabled_ports = 0x1f,
1da6df85 1215 .arl_entries = 4,
967dd82f
FF		 1216 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1217 .vta_regs = B53_VTA_REGS,
1218 .duplex_reg = B53_DUPLEX_STAT_GE,
1219 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1220 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1221 },
1222};
1223
1224static int b53_switch_init(struct b53_device *dev)
1225{
1226 struct dsa_switch *ds = dev->ds;
1227 unsigned int i;
1228 int ret;
1229
1230 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1231 const struct b53_chip_data *chip = &b53_switch_chips[i];
1232
1233 if (chip->chip_id == dev->chip_id) {
1234 if (!dev->enabled_ports)
1235 dev->enabled_ports = chip->enabled_ports;
1236 dev->name = chip->dev_name;
1237 dev->duplex_reg = chip->duplex_reg;
1238 dev->vta_regs[0] = chip->vta_regs[0];
1239 dev->vta_regs[1] = chip->vta_regs[1];
1240 dev->vta_regs[2] = chip->vta_regs[2];
1241 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1242 ds->drv = &b53_switch_ops;
1243 dev->cpu_port = chip->cpu_port;
1244 dev->num_vlans = chip->vlans;
1da6df85 1245 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1246 break;
1247 }
1248 }
1249
1250 /* check which BCM5325x version we have */
1251 if (is5325(dev)) {
1252 u8 vc4;
1253
1254 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1255
1256 /* check reserved bits */
1257 switch (vc4 & 3) {
1258 case 1:
1259 /* BCM5325E */
1260 break;
1261 case 3:
1262 /* BCM5325F - do not use port 4 */
1263 dev->enabled_ports &= ~BIT(4);
1264 break;
1265 default:
1266/* On the BCM47XX SoCs this is the supported internal switch.*/
1267#ifndef CONFIG_BCM47XX
1268 /* BCM5325M */
1269 return -EINVAL;
1270#else
1271 break;
1272#endif
1273 }
1274 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1275 u64 strap_value;
1276
1277 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1278 /* use second IMP port if GMII is enabled */
1279 if (strap_value & SV_GMII_CTRL_115)
1280 dev->cpu_port = 5;
1281 }
1282
1283 /* cpu port is always last */
1284 dev->num_ports = dev->cpu_port + 1;
1285 dev->enabled_ports |= BIT(dev->cpu_port);
1286
1287 dev->ports = devm_kzalloc(dev->dev,
1288 sizeof(struct b53_port) * dev->num_ports,
1289 GFP_KERNEL);
1290 if (!dev->ports)
1291 return -ENOMEM;
1292
1293 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1294 if (dev->reset_gpio >= 0) {
1295 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1296 GPIOF_OUT_INIT_HIGH, "robo_reset");
1297 if (ret)
1298 return ret;
1299 }
1300
1301 return 0;
1302}
1303
1304struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1305 void *priv)
1306{
1307 struct dsa_switch *ds;
1308 struct b53_device *dev;
1309
1310 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1311 if (!ds)
1312 return NULL;
1313
1314 dev = (struct b53_device *)(ds + 1);
1315
1316 ds->priv = dev;
1317 ds->dev = base;
1318 dev->dev = base;
1319
1320 dev->ds = ds;
1321 dev->priv = priv;
1322 dev->ops = ops;
1323 mutex_init(&dev->reg_mutex);
1324 mutex_init(&dev->stats_mutex);
1325
1326 return dev;
1327}
1328EXPORT_SYMBOL(b53_switch_alloc);
1329
1330int b53_switch_detect(struct b53_device *dev)
1331{
1332 u32 id32;
1333 u16 tmp;
1334 u8 id8;
1335 int ret;
1336
1337 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1338 if (ret)
1339 return ret;
1340
1341 switch (id8) {
1342 case 0:
1343 /* BCM5325 and BCM5365 do not have this register so reads
1344 * return 0. But the read operation did succeed, so assume this
1345 * is one of them.
1346 *
1347 * Next check if we can write to the 5325's VTA register; for
1348 * 5365 it is read only.
1349 */
1350 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1351 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1352
1353 if (tmp == 0xf)
1354 dev->chip_id = BCM5325_DEVICE_ID;
1355 else
1356 dev->chip_id = BCM5365_DEVICE_ID;
1357 break;
1358 case BCM5395_DEVICE_ID:
1359 case BCM5397_DEVICE_ID:
1360 case BCM5398_DEVICE_ID:
1361 dev->chip_id = id8;
1362 break;
1363 default:
1364 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1365 if (ret)
1366 return ret;
1367
1368 switch (id32) {
1369 case BCM53115_DEVICE_ID:
1370 case BCM53125_DEVICE_ID:
1371 case BCM53128_DEVICE_ID:
1372 case BCM53010_DEVICE_ID:
1373 case BCM53011_DEVICE_ID:
1374 case BCM53012_DEVICE_ID:
1375 case BCM53018_DEVICE_ID:
1376 case BCM53019_DEVICE_ID:
1377 dev->chip_id = id32;
1378 break;
1379 default:
1380 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1381 id8, id32);
1382 return -ENODEV;
1383 }
1384 }
1385
1386 if (dev->chip_id == BCM5325_DEVICE_ID)
1387 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1388 &dev->core_rev);
1389 else
1390 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1391 &dev->core_rev);
1392}
1393EXPORT_SYMBOL(b53_switch_detect);
1394
1395int b53_switch_register(struct b53_device *dev)
1396{
1397 int ret;
1398
1399 if (dev->pdata) {
1400 dev->chip_id = dev->pdata->chip_id;
1401 dev->enabled_ports = dev->pdata->enabled_ports;
1402 }
1403
1404 if (!dev->chip_id && b53_switch_detect(dev))
1405 return -EINVAL;
1406
1407 ret = b53_switch_init(dev);
1408 if (ret)
1409 return ret;
1410
1411 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1412
1413 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1414}
1415EXPORT_SYMBOL(b53_switch_register);
1416
1417MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1418MODULE_DESCRIPTION("B53 switch library");
1419MODULE_LICENSE("Dual BSD/GPL");
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