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[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f
FF		 31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
bde5d132
FF		 169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
967dd82f
FF		 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
a2482d2c
FF		 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
967dd82f
FF		 249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
a2482d2c
FF		 253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
a2482d2c
FF		 268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
a2482d2c
FF		 282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
967dd82f
FF		 324}
325
a2482d2c 326static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f 327{
a424f0de 328 struct dsa_switch *ds = dev->ds;
967dd82f
FF		 329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de
FF		 339
340 /* Include IMP port in dumb forwarding mode when no tagging protocol is
341 * set
342 */
343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
347 }
967dd82f
FF		 348}
349
a2482d2c 350static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 351{
352 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
353
354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
357
358 if (is5325(dev) || is5365(dev)) {
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
361 } else if (is63xx(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
364 } else {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
367 }
368
369 mgmt &= ~SM_SW_FWD_MODE;
370
371 if (enable) {
372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
374 vc4 &= ~VC4_ING_VID_CHECK_MASK;
375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
376 vc5 |= VC5_DROP_VTABLE_MISS;
377
378 if (is5325(dev))
379 vc0 &= ~VC0_RESERVED_1;
380
381 if (is5325(dev) || is5365(dev))
382 vc1 |= VC1_RX_MCST_TAG_EN;
383
967dd82f
FF		 384 } else {
385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
387 vc4 &= ~VC4_ING_VID_CHECK_MASK;
388 vc5 &= ~VC5_DROP_VTABLE_MISS;
389
390 if (is5325(dev) || is5365(dev))
391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
392 else
393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
394
395 if (is5325(dev) || is5365(dev))
396 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 397 }
398
a2482d2c
FF		 399 if (!is5325(dev) && !is5365(dev))
400 vc5 &= ~VC5_VID_FFF_EN;
401
967dd82f
FF		 402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
404
405 if (is5325(dev) || is5365(dev)) {
406 /* enable the high 8 bit vid check on 5325 */
407 if (is5325(dev) && enable)
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
409 VC3_HIGH_8BIT_EN);
410 else
411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
412
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
415 } else if (is63xx(dev)) {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
419 } else {
420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
423 }
424
425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
426}
427
428static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
429{
430 u32 port_mask = 0;
431 u16 max_size = JMS_MIN_SIZE;
432
433 if (is5325(dev) || is5365(dev))
434 return -EINVAL;
435
436 if (enable) {
437 port_mask = dev->enabled_ports;
438 max_size = JMS_MAX_SIZE;
439 if (allow_10_100)
440 port_mask |= JPM_10_100_JUMBO_EN;
441 }
442
443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
445}
446
ff39c2d6 447static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 448{
449 unsigned int i;
450
451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 453
454 for (i = 0; i < 10; i++) {
455 u8 fast_age_ctrl;
456
457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
458 &fast_age_ctrl);
459
460 if (!(fast_age_ctrl & FAST_AGE_DONE))
461 goto out;
462
463 msleep(1);
464 }
465
466 return -ETIMEDOUT;
467out:
468 /* Only age dynamic entries (default behavior) */
469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
470 return 0;
471}
472
ff39c2d6
FF		 473static int b53_fast_age_port(struct b53_device *dev, int port)
474{
475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
476
477 return b53_flush_arl(dev, FAST_AGE_PORT);
478}
479
a2482d2c
FF		 480static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
481{
482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
483
484 return b53_flush_arl(dev, FAST_AGE_VLAN);
485}
486
aac02867 487void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 488{
04bed143 489 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 490 unsigned int i;
491 u16 pvlan;
492
493 /* Enable the IMP port to be in the same VLAN as the other ports
494 * on a per-port basis such that we only have Port i and IMP in
495 * the same VLAN.
496 */
497 b53_for_each_port(dev, i) {
498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
499 pvlan |= BIT(cpu_port);
500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
501 }
502}
aac02867 503EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 504
f86ad77f 505int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 506{
04bed143 507 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 508 unsigned int cpu_port = dev->cpu_port;
509 u16 pvlan;
967dd82f
FF		 510
511 /* Clear the Rx and Tx disable bits and set to no spanning tree */
512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
513
ff39c2d6
FF		 514 /* Set this port, and only this one to be in the default VLAN,
515 * if member of a bridge, restore its membership prior to
516 * bringing down this port.
517 */
518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
519 pvlan &= ~0x1ff;
520 pvlan |= BIT(port);
521 pvlan |= dev->ports[port].vlan_ctl_mask;
522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
523
524 b53_imp_vlan_setup(ds, cpu_port);
525
f43a2dbe
FF		 526 /* If EEE was enabled, restore it */
527 if (dev->ports[port].eee.eee_enabled)
528 b53_eee_enable_set(ds, port, true);
529
967dd82f
FF		 530 return 0;
531}
f86ad77f 532EXPORT_SYMBOL(b53_enable_port);
967dd82f 533
f86ad77f 534void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 535{
04bed143 536 struct b53_device *dev = ds->priv;
967dd82f
FF		 537 u8 reg;
538
539 /* Disable Tx/Rx for the port */
540 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
541 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
542 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
543}
f86ad77f 544EXPORT_SYMBOL(b53_disable_port);
967dd82f 545
b409a9ef
FF		 546void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
547{
cdb583cf 548 bool tag_en = !!(ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_BRCM);
b409a9ef
FF		 549 struct b53_device *dev = ds->priv;
550 u8 hdr_ctl, val;
551 u16 reg;
552
553 /* Resolve which bit controls the Broadcom tag */
554 switch (port) {
555 case 8:
556 val = BRCM_HDR_P8_EN;
557 break;
558 case 7:
559 val = BRCM_HDR_P7_EN;
560 break;
561 case 5:
562 val = BRCM_HDR_P5_EN;
563 break;
564 default:
565 val = 0;
566 break;
567 }
568
569 /* Enable Broadcom tags for IMP port */
570 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
cdb583cf
FF		 571 if (tag_en)
572 hdr_ctl |= val;
573 else
574 hdr_ctl &= ~val;
b409a9ef
FF		 575 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
576
577 /* Registers below are only accessible on newer devices */
578 if (!is58xx(dev))
579 return;
580
581 /* Enable reception Broadcom tag for CPU TX (switch RX) to
582 * allow us to tag outgoing frames
583 */
584 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
cdb583cf
FF		 585 if (tag_en)
586 reg &= ~BIT(port);
587 else
588 reg |= BIT(port);
b409a9ef
FF		 589 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
590
591 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
592 * allow delivering frames to the per-port net_devices
593 */
594 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
cdb583cf
FF		 595 if (tag_en)
596 reg &= ~BIT(port);
597 else
598 reg |= BIT(port);
b409a9ef
FF		 599 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
600}
601EXPORT_SYMBOL(b53_brcm_hdr_setup);
602
299752a7 603static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 604{
967dd82f
FF		 605 u8 port_ctrl;
606
607 /* BCM5325 CPU port is at 8 */
299752a7
FF		 608 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
609 port = B53_CPU_PORT;
967dd82f
FF		 610
611 port_ctrl = PORT_CTRL_RX_BCST_EN |
612 PORT_CTRL_RX_MCST_EN |
613 PORT_CTRL_RX_UCST_EN;
299752a7 614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
967dd82f
FF		 615}
616
617static void b53_enable_mib(struct b53_device *dev)
618{
619 u8 gc;
620
621 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
622 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
623 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
624}
625
5c1a6eaf 626int b53_configure_vlan(struct dsa_switch *ds)
967dd82f 627{
5c1a6eaf 628 struct b53_device *dev = ds->priv;
a2482d2c 629 struct b53_vlan vl = { 0 };
967dd82f
FF		 630 int i;
631
632 /* clear all vlan entries */
633 if (is5325(dev) || is5365(dev)) {
634 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 635 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 636 } else {
637 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
638 }
639
640 b53_enable_vlan(dev, false);
641
642 b53_for_each_port(dev, i)
643 b53_write16(dev, B53_VLAN_PAGE,
644 B53_VLAN_PORT_DEF_TAG(i), 1);
645
646 if (!is5325(dev) && !is5365(dev))
647 b53_set_jumbo(dev, dev->enable_jumbo, false);
648
649 return 0;
650}
5c1a6eaf 651EXPORT_SYMBOL(b53_configure_vlan);
967dd82f
FF		 652
653static void b53_switch_reset_gpio(struct b53_device *dev)
654{
655 int gpio = dev->reset_gpio;
656
657 if (gpio < 0)
658 return;
659
660 /* Reset sequence: RESET low(50ms)->high(20ms)
661 */
662 gpio_set_value(gpio, 0);
663 mdelay(50);
664
665 gpio_set_value(gpio, 1);
666 mdelay(20);
667
668 dev->current_page = 0xff;
669}
670
671static int b53_switch_reset(struct b53_device *dev)
672{
3fb22b05
FF		 673 unsigned int timeout = 1000;
674 u8 mgmt, reg;
967dd82f
FF		 675
676 b53_switch_reset_gpio(dev);
677
678 if (is539x(dev)) {
679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
680 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
681 }
682
3fb22b05
FF		 683 /* This is specific to 58xx devices here, do not use is58xx() which
684 * covers the larger Starfigther 2 family, including 7445/7278 which
685 * still use this driver as a library and need to perform the reset
686 * earlier.
687 */
688 if (dev->chip_id == BCM58XX_DEVICE_ID) {
689 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
690 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
691 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
692
693 do {
694 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
695 if (!(reg & SW_RST))
696 break;
697
698 usleep_range(1000, 2000);
699 } while (timeout-- > 0);
700
701 if (timeout == 0)
702 return -ETIMEDOUT;
703 }
704
967dd82f
FF		 705 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
706
707 if (!(mgmt & SM_SW_FWD_EN)) {
708 mgmt &= ~SM_SW_FWD_MODE;
709 mgmt |= SM_SW_FWD_EN;
710
711 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
712 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
713
714 if (!(mgmt & SM_SW_FWD_EN)) {
715 dev_err(dev->dev, "Failed to enable switch!\n");
716 return -EINVAL;
717 }
718 }
719
720 b53_enable_mib(dev);
721
ff39c2d6 722 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 723}
724
725static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
726{
04bed143 727 struct b53_device *priv = ds->priv;
967dd82f
FF		 728 u16 value = 0;
729 int ret;
730
731 if (priv->ops->phy_read16)
732 ret = priv->ops->phy_read16(priv, addr, reg, &value);
733 else
734 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
735 reg * 2, &value);
736
737 return ret ? ret : value;
738}
739
740static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
741{
04bed143 742 struct b53_device *priv = ds->priv;
967dd82f
FF		 743
744 if (priv->ops->phy_write16)
745 return priv->ops->phy_write16(priv, addr, reg, val);
746
747 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
748}
749
750static int b53_reset_switch(struct b53_device *priv)
751{
752 /* reset vlans */
753 priv->enable_jumbo = false;
754
a2482d2c 755 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 756 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
757
758 return b53_switch_reset(priv);
759}
760
761static int b53_apply_config(struct b53_device *priv)
762{
763 /* disable switching */
764 b53_set_forwarding(priv, 0);
765
5c1a6eaf 766 b53_configure_vlan(priv->ds);
967dd82f
FF		 767
768 /* enable switching */
769 b53_set_forwarding(priv, 1);
770
771 return 0;
772}
773
774static void b53_reset_mib(struct b53_device *priv)
775{
776 u8 gc;
777
778 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
779
780 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
781 msleep(1);
782 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
783 msleep(1);
784}
785
786static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
787{
788 if (is5365(dev))
789 return b53_mibs_65;
790 else if (is63xx(dev))
791 return b53_mibs_63xx;
bde5d132
FF		 792 else if (is58xx(dev))
793 return b53_mibs_58xx;
967dd82f
FF		 794 else
795 return b53_mibs;
796}
797
798static unsigned int b53_get_mib_size(struct b53_device *dev)
799{
800 if (is5365(dev))
801 return B53_MIBS_65_SIZE;
802 else if (is63xx(dev))
803 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 804 else if (is58xx(dev))
805 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 806 else
807 return B53_MIBS_SIZE;
808}
809
3117455d 810void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
967dd82f 811{
04bed143 812 struct b53_device *dev = ds->priv;
967dd82f
FF		 813 const struct b53_mib_desc *mibs = b53_get_mib(dev);
814 unsigned int mib_size = b53_get_mib_size(dev);
815 unsigned int i;
816
817 for (i = 0; i < mib_size; i++)
818 memcpy(data + i * ETH_GSTRING_LEN,
819 mibs[i].name, ETH_GSTRING_LEN);
820}
3117455d 821EXPORT_SYMBOL(b53_get_strings);
967dd82f 822
3117455d 823void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 824{
04bed143 825 struct b53_device *dev = ds->priv;
967dd82f
FF		 826 const struct b53_mib_desc *mibs = b53_get_mib(dev);
827 unsigned int mib_size = b53_get_mib_size(dev);
828 const struct b53_mib_desc *s;
829 unsigned int i;
830 u64 val = 0;
831
832 if (is5365(dev) && port == 5)
833 port = 8;
834
835 mutex_lock(&dev->stats_mutex);
836
837 for (i = 0; i < mib_size; i++) {
838 s = &mibs[i];
839
51dca8a1 840 if (s->size == 8) {
967dd82f
FF		 841 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
842 } else {
843 u32 val32;
844
845 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
846 &val32);
847 val = val32;
848 }
849 data[i] = (u64)val;
850 }
851
852 mutex_unlock(&dev->stats_mutex);
853}
3117455d 854EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 855
3117455d 856int b53_get_sset_count(struct dsa_switch *ds)
967dd82f 857{
04bed143 858 struct b53_device *dev = ds->priv;
967dd82f
FF		 859
860 return b53_get_mib_size(dev);
861}
3117455d 862EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 863
967dd82f
FF		 864static int b53_setup(struct dsa_switch *ds)
865{
04bed143 866 struct b53_device *dev = ds->priv;
967dd82f
FF		 867 unsigned int port;
868 int ret;
869
870 ret = b53_reset_switch(dev);
871 if (ret) {
872 dev_err(ds->dev, "failed to reset switch\n");
873 return ret;
874 }
875
876 b53_reset_mib(dev);
877
878 ret = b53_apply_config(dev);
879 if (ret)
880 dev_err(ds->dev, "failed to apply configuration\n");
881
34c8befd
FF		 882 /* Configure IMP/CPU port, disable unused ports. Enabled
883 * ports will be configured with .port_enable
884 */
967dd82f 885 for (port = 0; port < dev->num_ports; port++) {
34c8befd 886 if (dsa_is_cpu_port(ds, port))
299752a7 887 b53_enable_cpu_port(dev, port);
bff7b688 888 else if (dsa_is_unused_port(ds, port))
967dd82f
FF		 889 b53_disable_port(ds, port, NULL);
890 }
891
892 return ret;
893}
894
895static void b53_adjust_link(struct dsa_switch *ds, int port,
896 struct phy_device *phydev)
897{
04bed143 898 struct b53_device *dev = ds->priv;
f43a2dbe 899 struct ethtool_eee *p = &dev->ports[port].eee;
967dd82f
FF		 900 u8 rgmii_ctrl = 0, reg = 0, off;
901
902 if (!phy_is_pseudo_fixed_link(phydev))
903 return;
904
905 /* Override the port settings */
906 if (port == dev->cpu_port) {
907 off = B53_PORT_OVERRIDE_CTRL;
908 reg = PORT_OVERRIDE_EN;
909 } else {
910 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
911 reg = GMII_PO_EN;
912 }
913
914 /* Set the link UP */
915 if (phydev->link)
916 reg |= PORT_OVERRIDE_LINK;
917
918 if (phydev->duplex == DUPLEX_FULL)
919 reg |= PORT_OVERRIDE_FULL_DUPLEX;
920
921 switch (phydev->speed) {
922 case 2000:
923 reg |= PORT_OVERRIDE_SPEED_2000M;
924 /* fallthrough */
925 case SPEED_1000:
926 reg |= PORT_OVERRIDE_SPEED_1000M;
927 break;
928 case SPEED_100:
929 reg |= PORT_OVERRIDE_SPEED_100M;
930 break;
931 case SPEED_10:
932 reg |= PORT_OVERRIDE_SPEED_10M;
933 break;
934 default:
935 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
936 return;
937 }
938
939 /* Enable flow control on BCM5301x's CPU port */
940 if (is5301x(dev) && port == dev->cpu_port)
941 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
942
943 if (phydev->pause) {
944 if (phydev->asym_pause)
945 reg |= PORT_OVERRIDE_TX_FLOW;
946 reg |= PORT_OVERRIDE_RX_FLOW;
947 }
948
949 b53_write8(dev, B53_CTRL_PAGE, off, reg);
950
951 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
952 if (port == 8)
953 off = B53_RGMII_CTRL_IMP;
954 else
955 off = B53_RGMII_CTRL_P(port);
956
957 /* Configure the port RGMII clock delay by DLL disabled and
958 * tx_clk aligned timing (restoring to reset defaults)
959 */
960 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
961 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
962 RGMII_CTRL_TIMING_SEL);
963
964 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
965 * sure that we enable the port TX clock internal delay to
966 * account for this internal delay that is inserted, otherwise
967 * the switch won't be able to receive correctly.
968 *
969 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
970 * any delay neither on transmission nor reception, so the
971 * BCM53125 must also be configured accordingly to account for
972 * the lack of delay and introduce
973 *
974 * The BCM53125 switch has its RX clock and TX clock control
975 * swapped, hence the reason why we modify the TX clock path in
976 * the "RGMII" case
977 */
978 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
979 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
980 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
981 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
982 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
983 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
984
985 dev_info(ds->dev, "Configured port %d for %s\n", port,
986 phy_modes(phydev->interface));
987 }
988
989 /* configure MII port if necessary */
990 if (is5325(dev)) {
991 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
992 &reg);
993
994 /* reverse mii needs to be enabled */
995 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
996 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
997 reg | PORT_OVERRIDE_RV_MII_25);
998 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
999 &reg);
1000
1001 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1002 dev_err(ds->dev,
1003 "Failed to enable reverse MII mode\n");
1004 return;
1005 }
1006 }
1007 } else if (is5301x(dev)) {
1008 if (port != dev->cpu_port) {
1009 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1010 u8 gmii_po;
1011
1012 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1013 gmii_po |= GMII_PO_LINK |
1014 GMII_PO_RX_FLOW |
1015 GMII_PO_TX_FLOW |
1016 GMII_PO_EN |
1017 GMII_PO_SPEED_2000M;
1018 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1019 }
1020 }
f43a2dbe
FF		 1021
1022 /* Re-negotiate EEE if it was enabled already */
1023 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1024}
1025
3117455d 1026int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 1027{
1028 return 0;
1029}
3117455d 1030EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1031
3117455d
FF		 1032int b53_vlan_prepare(struct dsa_switch *ds, int port,
1033 const struct switchdev_obj_port_vlan *vlan,
1034 struct switchdev_trans *trans)
a2482d2c 1035{
04bed143 1036 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1037
1038 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1039 return -EOPNOTSUPP;
1040
1041 if (vlan->vid_end > dev->num_vlans)
1042 return -ERANGE;
1043
1044 b53_enable_vlan(dev, true);
1045
1046 return 0;
1047}
3117455d 1048EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 1049
3117455d
FF		 1050void b53_vlan_add(struct dsa_switch *ds, int port,
1051 const struct switchdev_obj_port_vlan *vlan,
1052 struct switchdev_trans *trans)
a2482d2c 1053{
04bed143 1054 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1055 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1056 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1057 unsigned int cpu_port = dev->cpu_port;
1058 struct b53_vlan *vl;
1059 u16 vid;
1060
1061 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1062 vl = &dev->vlans[vid];
1063
1064 b53_get_vlan_entry(dev, vid, vl);
1065
1066 vl->members |= BIT(port) | BIT(cpu_port);
1067 if (untagged)
e47112d9 1068 vl->untag |= BIT(port);
a2482d2c 1069 else
e47112d9
FF		 1070 vl->untag &= ~BIT(port);
1071 vl->untag &= ~BIT(cpu_port);
a2482d2c
FF		 1072
1073 b53_set_vlan_entry(dev, vid, vl);
1074 b53_fast_age_vlan(dev, vid);
1075 }
1076
1077 if (pvid) {
1078 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1079 vlan->vid_end);
a2482d2c
FF		 1080 b53_fast_age_vlan(dev, vid);
1081 }
1082}
3117455d 1083EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1084
3117455d
FF		 1085int b53_vlan_del(struct dsa_switch *ds, int port,
1086 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1087{
04bed143 1088 struct b53_device *dev = ds->priv;
a2482d2c 1089 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1090 struct b53_vlan *vl;
1091 u16 vid;
1092 u16 pvid;
1093
1094 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1095
1096 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1097 vl = &dev->vlans[vid];
1098
1099 b53_get_vlan_entry(dev, vid, vl);
1100
1101 vl->members &= ~BIT(port);
a2482d2c
FF		 1102
1103 if (pvid == vid) {
1104 if (is5325(dev) || is5365(dev))
1105 pvid = 1;
1106 else
1107 pvid = 0;
1108 }
1109
e47112d9 1110 if (untagged)
a2482d2c 1111 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1112
1113 b53_set_vlan_entry(dev, vid, vl);
1114 b53_fast_age_vlan(dev, vid);
1115 }
1116
1117 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1118 b53_fast_age_vlan(dev, pvid);
1119
1120 return 0;
1121}
3117455d 1122EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1123
1da6df85
FF		 1124/* Address Resolution Logic routines */
1125static int b53_arl_op_wait(struct b53_device *dev)
1126{
1127 unsigned int timeout = 10;
1128 u8 reg;
1129
1130 do {
1131 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1132 if (!(reg & ARLTBL_START_DONE))
1133 return 0;
1134
1135 usleep_range(1000, 2000);
1136 } while (timeout--);
1137
1138 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1139
1140 return -ETIMEDOUT;
1141}
1142
1143static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1144{
1145 u8 reg;
1146
1147 if (op > ARLTBL_RW)
1148 return -EINVAL;
1149
1150 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1151 reg |= ARLTBL_START_DONE;
1152 if (op)
1153 reg |= ARLTBL_RW;
1154 else
1155 reg &= ~ARLTBL_RW;
1156 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1157
1158 return b53_arl_op_wait(dev);
1159}
1160
1161static int b53_arl_read(struct b53_device *dev, u64 mac,
1162 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1163 bool is_valid)
1164{
1165 unsigned int i;
1166 int ret;
1167
1168 ret = b53_arl_op_wait(dev);
1169 if (ret)
1170 return ret;
1171
1172 /* Read the bins */
1173 for (i = 0; i < dev->num_arl_entries; i++) {
1174 u64 mac_vid;
1175 u32 fwd_entry;
1176
1177 b53_read64(dev, B53_ARLIO_PAGE,
1178 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1179 b53_read32(dev, B53_ARLIO_PAGE,
1180 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1181 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1182
1183 if (!(fwd_entry & ARLTBL_VALID))
1184 continue;
1185 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1186 continue;
1187 *idx = i;
1188 }
1189
1190 return -ENOENT;
1191}
1192
1193static int b53_arl_op(struct b53_device *dev, int op, int port,
1194 const unsigned char *addr, u16 vid, bool is_valid)
1195{
1196 struct b53_arl_entry ent;
1197 u32 fwd_entry;
1198 u64 mac, mac_vid = 0;
1199 u8 idx = 0;
1200 int ret;
1201
1202 /* Convert the array into a 64-bit MAC */
4b92ea81 1203 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1204
1205 /* Perform a read for the given MAC and VID */
1206 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1207 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1208
1209 /* Issue a read operation for this MAC */
1210 ret = b53_arl_rw_op(dev, 1);
1211 if (ret)
1212 return ret;
1213
1214 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1215 /* If this is a read, just finish now */
1216 if (op)
1217 return ret;
1218
1219 /* We could not find a matching MAC, so reset to a new entry */
1220 if (ret) {
1221 fwd_entry = 0;
1222 idx = 1;
1223 }
1224
1225 memset(&ent, 0, sizeof(ent));
1226 ent.port = port;
1227 ent.is_valid = is_valid;
1228 ent.vid = vid;
1229 ent.is_static = true;
1230 memcpy(ent.mac, addr, ETH_ALEN);
1231 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1232
1233 b53_write64(dev, B53_ARLIO_PAGE,
1234 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1235 b53_write32(dev, B53_ARLIO_PAGE,
1236 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1237
1238 return b53_arl_rw_op(dev, 0);
1239}
1240
1b6dd556
AS		 1241int b53_fdb_add(struct dsa_switch *ds, int port,
1242 const unsigned char *addr, u16 vid)
1da6df85 1243{
04bed143 1244 struct b53_device *priv = ds->priv;
1da6df85
FF		 1245
1246 /* 5325 and 5365 require some more massaging, but could
1247 * be supported eventually
1248 */
1249 if (is5325(priv) || is5365(priv))
1250 return -EOPNOTSUPP;
1251
1b6dd556 1252 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1253}
3117455d 1254EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1255
3117455d 1256int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1257 const unsigned char *addr, u16 vid)
1da6df85 1258{
04bed143 1259 struct b53_device *priv = ds->priv;
1da6df85 1260
6c2c1dcb 1261 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1262}
3117455d 1263EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1264
1265static int b53_arl_search_wait(struct b53_device *dev)
1266{
1267 unsigned int timeout = 1000;
1268 u8 reg;
1269
1270 do {
1271 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1272 if (!(reg & ARL_SRCH_STDN))
1273 return 0;
1274
1275 if (reg & ARL_SRCH_VLID)
1276 return 0;
1277
1278 usleep_range(1000, 2000);
1279 } while (timeout--);
1280
1281 return -ETIMEDOUT;
1282}
1283
1284static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1285 struct b53_arl_entry *ent)
1286{
1287 u64 mac_vid;
1288 u32 fwd_entry;
1289
1290 b53_read64(dev, B53_ARLIO_PAGE,
1291 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1292 b53_read32(dev, B53_ARLIO_PAGE,
1293 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1294 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1295}
1296
e6cbef0c 1297static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1298 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1299{
1300 if (!ent->is_valid)
1301 return 0;
1302
1303 if (port != ent->port)
1304 return 0;
1305
2bedde1a 1306 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1307}
1308
3117455d 1309int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1310 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1311{
04bed143 1312 struct b53_device *priv = ds->priv;
1da6df85
FF		 1313 struct b53_arl_entry results[2];
1314 unsigned int count = 0;
1315 int ret;
1316 u8 reg;
1317
1318 /* Start search operation */
1319 reg = ARL_SRCH_STDN;
1320 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1321
1322 do {
1323 ret = b53_arl_search_wait(priv);
1324 if (ret)
1325 return ret;
1326
1327 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1328 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1329 if (ret)
1330 return ret;
1331
1332 if (priv->num_arl_entries > 2) {
1333 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1334 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1335 if (ret)
1336 return ret;
1337
1338 if (!results[0].is_valid && !results[1].is_valid)
1339 break;
1340 }
1341
1342 } while (count++ < 1024);
1343
1344 return 0;
1345}
3117455d 1346EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1347
ddd3a0c8 1348int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1349{
04bed143 1350 struct b53_device *dev = ds->priv;
0abfd494 1351 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6
FF		 1352 u16 pvlan, reg;
1353 unsigned int i;
1354
48aea33a
FF		 1355 /* Make this port leave the all VLANs join since we will have proper
1356 * VLAN entries from now on
1357 */
1358 if (is58xx(dev)) {
1359 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1360 reg &= ~BIT(port);
1361 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1362 reg &= ~BIT(cpu_port);
1363 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1364 }
1365
ff39c2d6
FF		 1366 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1367
1368 b53_for_each_port(dev, i) {
c8652c83 1369 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1370 continue;
1371
1372 /* Add this local port to the remote port VLAN control
1373 * membership and update the remote port bitmask
1374 */
1375 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1376 reg |= BIT(port);
1377 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1378 dev->ports[i].vlan_ctl_mask = reg;
1379
1380 pvlan |= BIT(i);
1381 }
1382
1383 /* Configure the local port VLAN control membership to include
1384 * remote ports and update the local port bitmask
1385 */
1386 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1387 dev->ports[port].vlan_ctl_mask = pvlan;
1388
1389 return 0;
1390}
3117455d 1391EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1392
f123f2fb 1393void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1394{
04bed143 1395 struct b53_device *dev = ds->priv;
a2482d2c 1396 struct b53_vlan *vl = &dev->vlans[0];
0abfd494 1397 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 1398 unsigned int i;
a2482d2c 1399 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1400
1401 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1402
1403 b53_for_each_port(dev, i) {
1404 /* Don't touch the remaining ports */
c8652c83 1405 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1406 continue;
1407
1408 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1409 reg &= ~BIT(port);
1410 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1411 dev->ports[port].vlan_ctl_mask = reg;
1412
1413 /* Prevent self removal to preserve isolation */
1414 if (port != i)
1415 pvlan &= ~BIT(i);
1416 }
1417
1418 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1419 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1420
1421 if (is5325(dev) || is5365(dev))
1422 pvid = 1;
1423 else
1424 pvid = 0;
1425
48aea33a
FF		 1426 /* Make this port join all VLANs without VLAN entries */
1427 if (is58xx(dev)) {
1428 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1429 reg |= BIT(port);
1430 if (!(reg & BIT(cpu_port)))
1431 reg |= BIT(cpu_port);
1432 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1433 } else {
1434 b53_get_vlan_entry(dev, pvid, vl);
1435 vl->members |= BIT(port) | BIT(dev->cpu_port);
1436 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1437 b53_set_vlan_entry(dev, pvid, vl);
1438 }
ff39c2d6 1439}
3117455d 1440EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1441
3117455d 1442void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1443{
04bed143 1444 struct b53_device *dev = ds->priv;
597698f1 1445 u8 hw_state;
ff39c2d6
FF		 1446 u8 reg;
1447
ff39c2d6
FF		 1448 switch (state) {
1449 case BR_STATE_DISABLED:
1450 hw_state = PORT_CTRL_DIS_STATE;
1451 break;
1452 case BR_STATE_LISTENING:
1453 hw_state = PORT_CTRL_LISTEN_STATE;
1454 break;
1455 case BR_STATE_LEARNING:
1456 hw_state = PORT_CTRL_LEARN_STATE;
1457 break;
1458 case BR_STATE_FORWARDING:
1459 hw_state = PORT_CTRL_FWD_STATE;
1460 break;
1461 case BR_STATE_BLOCKING:
1462 hw_state = PORT_CTRL_BLOCK_STATE;
1463 break;
1464 default:
1465 dev_err(ds->dev, "invalid STP state: %d\n", state);
1466 return;
1467 }
1468
ff39c2d6
FF		 1469 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1470 reg &= ~PORT_CTRL_STP_STATE_MASK;
1471 reg |= hw_state;
1472 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1473}
3117455d 1474EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1475
3117455d 1476void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1477{
1478 struct b53_device *dev = ds->priv;
1479
1480 if (b53_fast_age_port(dev, port))
1481 dev_err(ds->dev, "fast ageing failed\n");
1482}
3117455d 1483EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1484
7b314362
AL		 1485static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1486{
1487 return DSA_TAG_PROTO_NONE;
1488}
1489
ed3af5fd
FF		 1490int b53_mirror_add(struct dsa_switch *ds, int port,
1491 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1492{
1493 struct b53_device *dev = ds->priv;
1494 u16 reg, loc;
1495
1496 if (ingress)
1497 loc = B53_IG_MIR_CTL;
1498 else
1499 loc = B53_EG_MIR_CTL;
1500
1501 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1502 reg &= ~MIRROR_MASK;
1503 reg |= BIT(port);
1504 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1505
1506 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1507 reg &= ~CAP_PORT_MASK;
1508 reg |= mirror->to_local_port;
1509 reg |= MIRROR_EN;
1510 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1511
1512 return 0;
1513}
1514EXPORT_SYMBOL(b53_mirror_add);
1515
1516void b53_mirror_del(struct dsa_switch *ds, int port,
1517 struct dsa_mall_mirror_tc_entry *mirror)
1518{
1519 struct b53_device *dev = ds->priv;
1520 bool loc_disable = false, other_loc_disable = false;
1521 u16 reg, loc;
1522
1523 if (mirror->ingress)
1524 loc = B53_IG_MIR_CTL;
1525 else
1526 loc = B53_EG_MIR_CTL;
1527
1528 /* Update the desired ingress/egress register */
1529 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1530 reg &= ~BIT(port);
1531 if (!(reg & MIRROR_MASK))
1532 loc_disable = true;
1533 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1534
1535 /* Now look at the other one to know if we can disable mirroring
1536 * entirely
1537 */
1538 if (mirror->ingress)
1539 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1540 else
1541 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1542 if (!(reg & MIRROR_MASK))
1543 other_loc_disable = true;
1544
1545 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1546 /* Both no longer have ports, let's disable mirroring */
1547 if (loc_disable && other_loc_disable) {
1548 reg &= ~MIRROR_EN;
1549 reg &= ~mirror->to_local_port;
1550 }
1551 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1552}
1553EXPORT_SYMBOL(b53_mirror_del);
1554
22256b0a
FF		 1555void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1556{
1557 struct b53_device *dev = ds->priv;
1558 u16 reg;
1559
1560 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1561 if (enable)
1562 reg |= BIT(port);
1563 else
1564 reg &= ~BIT(port);
1565 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1566}
1567EXPORT_SYMBOL(b53_eee_enable_set);
1568
1569
1570/* Returns 0 if EEE was not enabled, or 1 otherwise
1571 */
1572int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1573{
1574 int ret;
1575
1576 ret = phy_init_eee(phy, 0);
1577 if (ret)
1578 return 0;
1579
1580 b53_eee_enable_set(ds, port, true);
1581
1582 return 1;
1583}
1584EXPORT_SYMBOL(b53_eee_init);
1585
1586int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1587{
1588 struct b53_device *dev = ds->priv;
1589 struct ethtool_eee *p = &dev->ports[port].eee;
1590 u16 reg;
1591
1592 if (is5325(dev) || is5365(dev))
1593 return -EOPNOTSUPP;
1594
1595 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1596 e->eee_enabled = p->eee_enabled;
1597 e->eee_active = !!(reg & BIT(port));
1598
1599 return 0;
1600}
1601EXPORT_SYMBOL(b53_get_mac_eee);
1602
1603int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1604{
1605 struct b53_device *dev = ds->priv;
1606 struct ethtool_eee *p = &dev->ports[port].eee;
1607
1608 if (is5325(dev) || is5365(dev))
1609 return -EOPNOTSUPP;
1610
1611 p->eee_enabled = e->eee_enabled;
1612 b53_eee_enable_set(ds, port, e->eee_enabled);
1613
1614 return 0;
1615}
1616EXPORT_SYMBOL(b53_set_mac_eee);
1617
a82f67af 1618static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1619 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1620 .setup = b53_setup,
967dd82f
FF		 1621 .get_strings = b53_get_strings,
1622 .get_ethtool_stats = b53_get_ethtool_stats,
1623 .get_sset_count = b53_get_sset_count,
1624 .phy_read = b53_phy_read16,
1625 .phy_write = b53_phy_write16,
1626 .adjust_link = b53_adjust_link,
1627 .port_enable = b53_enable_port,
1628 .port_disable = b53_disable_port,
f43a2dbe
FF		 1629 .get_mac_eee = b53_get_mac_eee,
1630 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 1631 .port_bridge_join = b53_br_join,
1632 .port_bridge_leave = b53_br_leave,
1633 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1634 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1635 .port_vlan_filtering = b53_vlan_filtering,
1636 .port_vlan_prepare = b53_vlan_prepare,
1637 .port_vlan_add = b53_vlan_add,
1638 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 1639 .port_fdb_dump = b53_fdb_dump,
1640 .port_fdb_add = b53_fdb_add,
1641 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1642 .port_mirror_add = b53_mirror_add,
1643 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1644};
1645
1646struct b53_chip_data {
1647 u32 chip_id;
1648 const char *dev_name;
1649 u16 vlans;
1650 u16 enabled_ports;
1651 u8 cpu_port;
1652 u8 vta_regs[3];
1da6df85 1653 u8 arl_entries;
967dd82f
FF		 1654 u8 duplex_reg;
1655 u8 jumbo_pm_reg;
1656 u8 jumbo_size_reg;
1657};
1658
1659#define B53_VTA_REGS \
1660 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1661#define B53_VTA_REGS_9798 \
1662 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1663#define B53_VTA_REGS_63XX \
1664 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1665
1666static const struct b53_chip_data b53_switch_chips[] = {
1667 {
1668 .chip_id = BCM5325_DEVICE_ID,
1669 .dev_name = "BCM5325",
1670 .vlans = 16,
1671 .enabled_ports = 0x1f,
1da6df85 1672 .arl_entries = 2,
967dd82f
FF		 1673 .cpu_port = B53_CPU_PORT_25,
1674 .duplex_reg = B53_DUPLEX_STAT_FE,
1675 },
1676 {
1677 .chip_id = BCM5365_DEVICE_ID,
1678 .dev_name = "BCM5365",
1679 .vlans = 256,
1680 .enabled_ports = 0x1f,
1da6df85 1681 .arl_entries = 2,
967dd82f
FF		 1682 .cpu_port = B53_CPU_PORT_25,
1683 .duplex_reg = B53_DUPLEX_STAT_FE,
1684 },
1685 {
1686 .chip_id = BCM5395_DEVICE_ID,
1687 .dev_name = "BCM5395",
1688 .vlans = 4096,
1689 .enabled_ports = 0x1f,
1da6df85 1690 .arl_entries = 4,
967dd82f
FF		 1691 .cpu_port = B53_CPU_PORT,
1692 .vta_regs = B53_VTA_REGS,
1693 .duplex_reg = B53_DUPLEX_STAT_GE,
1694 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1695 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1696 },
1697 {
1698 .chip_id = BCM5397_DEVICE_ID,
1699 .dev_name = "BCM5397",
1700 .vlans = 4096,
1701 .enabled_ports = 0x1f,
1da6df85 1702 .arl_entries = 4,
967dd82f
FF		 1703 .cpu_port = B53_CPU_PORT,
1704 .vta_regs = B53_VTA_REGS_9798,
1705 .duplex_reg = B53_DUPLEX_STAT_GE,
1706 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1707 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1708 },
1709 {
1710 .chip_id = BCM5398_DEVICE_ID,
1711 .dev_name = "BCM5398",
1712 .vlans = 4096,
1713 .enabled_ports = 0x7f,
1da6df85 1714 .arl_entries = 4,
967dd82f
FF		 1715 .cpu_port = B53_CPU_PORT,
1716 .vta_regs = B53_VTA_REGS_9798,
1717 .duplex_reg = B53_DUPLEX_STAT_GE,
1718 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1719 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1720 },
1721 {
1722 .chip_id = BCM53115_DEVICE_ID,
1723 .dev_name = "BCM53115",
1724 .vlans = 4096,
1725 .enabled_ports = 0x1f,
1da6df85 1726 .arl_entries = 4,
967dd82f
FF		 1727 .vta_regs = B53_VTA_REGS,
1728 .cpu_port = B53_CPU_PORT,
1729 .duplex_reg = B53_DUPLEX_STAT_GE,
1730 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1731 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1732 },
1733 {
1734 .chip_id = BCM53125_DEVICE_ID,
1735 .dev_name = "BCM53125",
1736 .vlans = 4096,
1737 .enabled_ports = 0xff,
be35e8c5 1738 .arl_entries = 4,
967dd82f
FF		 1739 .cpu_port = B53_CPU_PORT,
1740 .vta_regs = B53_VTA_REGS,
1741 .duplex_reg = B53_DUPLEX_STAT_GE,
1742 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1743 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1744 },
1745 {
1746 .chip_id = BCM53128_DEVICE_ID,
1747 .dev_name = "BCM53128",
1748 .vlans = 4096,
1749 .enabled_ports = 0x1ff,
1da6df85 1750 .arl_entries = 4,
967dd82f
FF		 1751 .cpu_port = B53_CPU_PORT,
1752 .vta_regs = B53_VTA_REGS,
1753 .duplex_reg = B53_DUPLEX_STAT_GE,
1754 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1755 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1756 },
1757 {
1758 .chip_id = BCM63XX_DEVICE_ID,
1759 .dev_name = "BCM63xx",
1760 .vlans = 4096,
1761 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1762 .arl_entries = 4,
967dd82f
FF		 1763 .cpu_port = B53_CPU_PORT,
1764 .vta_regs = B53_VTA_REGS_63XX,
1765 .duplex_reg = B53_DUPLEX_STAT_63XX,
1766 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1767 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1768 },
1769 {
1770 .chip_id = BCM53010_DEVICE_ID,
1771 .dev_name = "BCM53010",
1772 .vlans = 4096,
1773 .enabled_ports = 0x1f,
1da6df85 1774 .arl_entries = 4,
967dd82f
FF		 1775 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1776 .vta_regs = B53_VTA_REGS,
1777 .duplex_reg = B53_DUPLEX_STAT_GE,
1778 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1779 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1780 },
1781 {
1782 .chip_id = BCM53011_DEVICE_ID,
1783 .dev_name = "BCM53011",
1784 .vlans = 4096,
1785 .enabled_ports = 0x1bf,
1da6df85 1786 .arl_entries = 4,
967dd82f
FF		 1787 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1788 .vta_regs = B53_VTA_REGS,
1789 .duplex_reg = B53_DUPLEX_STAT_GE,
1790 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1791 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1792 },
1793 {
1794 .chip_id = BCM53012_DEVICE_ID,
1795 .dev_name = "BCM53012",
1796 .vlans = 4096,
1797 .enabled_ports = 0x1bf,
1da6df85 1798 .arl_entries = 4,
967dd82f
FF		 1799 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1800 .vta_regs = B53_VTA_REGS,
1801 .duplex_reg = B53_DUPLEX_STAT_GE,
1802 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1803 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1804 },
1805 {
1806 .chip_id = BCM53018_DEVICE_ID,
1807 .dev_name = "BCM53018",
1808 .vlans = 4096,
1809 .enabled_ports = 0x1f,
1da6df85 1810 .arl_entries = 4,
967dd82f
FF		 1811 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1812 .vta_regs = B53_VTA_REGS,
1813 .duplex_reg = B53_DUPLEX_STAT_GE,
1814 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1815 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1816 },
1817 {
1818 .chip_id = BCM53019_DEVICE_ID,
1819 .dev_name = "BCM53019",
1820 .vlans = 4096,
1821 .enabled_ports = 0x1f,
1da6df85 1822 .arl_entries = 4,
967dd82f
FF		 1823 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1824 .vta_regs = B53_VTA_REGS,
1825 .duplex_reg = B53_DUPLEX_STAT_GE,
1826 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1827 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1828 },
991a36bb
FF		 1829 {
1830 .chip_id = BCM58XX_DEVICE_ID,
1831 .dev_name = "BCM585xx/586xx/88312",
1832 .vlans = 4096,
1833 .enabled_ports = 0x1ff,
1834 .arl_entries = 4,
bfcda65c 1835 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 1836 .vta_regs = B53_VTA_REGS,
1837 .duplex_reg = B53_DUPLEX_STAT_GE,
1838 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1839 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1840 },
130401d9
FF		 1841 {
1842 .chip_id = BCM7445_DEVICE_ID,
1843 .dev_name = "BCM7445",
1844 .vlans = 4096,
1845 .enabled_ports = 0x1ff,
1846 .arl_entries = 4,
1847 .cpu_port = B53_CPU_PORT,
1848 .vta_regs = B53_VTA_REGS,
1849 .duplex_reg = B53_DUPLEX_STAT_GE,
1850 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1851 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1852 },
0fe99338
FF		 1853 {
1854 .chip_id = BCM7278_DEVICE_ID,
1855 .dev_name = "BCM7278",
1856 .vlans = 4096,
1857 .enabled_ports = 0x1ff,
1858 .arl_entries= 4,
1859 .cpu_port = B53_CPU_PORT,
1860 .vta_regs = B53_VTA_REGS,
1861 .duplex_reg = B53_DUPLEX_STAT_GE,
1862 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1863 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1864 },
967dd82f
FF		 1865};
1866
1867static int b53_switch_init(struct b53_device *dev)
1868{
967dd82f
FF		 1869 unsigned int i;
1870 int ret;
1871
1872 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1873 const struct b53_chip_data *chip = &b53_switch_chips[i];
1874
1875 if (chip->chip_id == dev->chip_id) {
1876 if (!dev->enabled_ports)
1877 dev->enabled_ports = chip->enabled_ports;
1878 dev->name = chip->dev_name;
1879 dev->duplex_reg = chip->duplex_reg;
1880 dev->vta_regs[0] = chip->vta_regs[0];
1881 dev->vta_regs[1] = chip->vta_regs[1];
1882 dev->vta_regs[2] = chip->vta_regs[2];
1883 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1884 dev->cpu_port = chip->cpu_port;
1885 dev->num_vlans = chip->vlans;
1da6df85 1886 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1887 break;
1888 }
1889 }
1890
1891 /* check which BCM5325x version we have */
1892 if (is5325(dev)) {
1893 u8 vc4;
1894
1895 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1896
1897 /* check reserved bits */
1898 switch (vc4 & 3) {
1899 case 1:
1900 /* BCM5325E */
1901 break;
1902 case 3:
1903 /* BCM5325F - do not use port 4 */
1904 dev->enabled_ports &= ~BIT(4);
1905 break;
1906 default:
1907/* On the BCM47XX SoCs this is the supported internal switch.*/
1908#ifndef CONFIG_BCM47XX
1909 /* BCM5325M */
1910 return -EINVAL;
1911#else
1912 break;
1913#endif
1914 }
1915 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1916 u64 strap_value;
1917
1918 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1919 /* use second IMP port if GMII is enabled */
1920 if (strap_value & SV_GMII_CTRL_115)
1921 dev->cpu_port = 5;
1922 }
1923
1924 /* cpu port is always last */
1925 dev->num_ports = dev->cpu_port + 1;
1926 dev->enabled_ports |= BIT(dev->cpu_port);
1927
1928 dev->ports = devm_kzalloc(dev->dev,
1929 sizeof(struct b53_port) * dev->num_ports,
1930 GFP_KERNEL);
1931 if (!dev->ports)
1932 return -ENOMEM;
1933
a2482d2c
FF		 1934 dev->vlans = devm_kzalloc(dev->dev,
1935 sizeof(struct b53_vlan) * dev->num_vlans,
1936 GFP_KERNEL);
1937 if (!dev->vlans)
1938 return -ENOMEM;
1939
967dd82f
FF		 1940 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1941 if (dev->reset_gpio >= 0) {
1942 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1943 GPIOF_OUT_INIT_HIGH, "robo_reset");
1944 if (ret)
1945 return ret;
1946 }
1947
1948 return 0;
1949}
1950
0dff88d3
JL		 1951struct b53_device *b53_switch_alloc(struct device *base,
1952 const struct b53_io_ops *ops,
967dd82f
FF		 1953 void *priv)
1954{
1955 struct dsa_switch *ds;
1956 struct b53_device *dev;
1957
a0c02161 1958 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 1959 if (!ds)
1960 return NULL;
1961
a0c02161
VD		 1962 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1963 if (!dev)
1964 return NULL;
967dd82f
FF		 1965
1966 ds->priv = dev;
967dd82f
FF		 1967 dev->dev = base;
1968
1969 dev->ds = ds;
1970 dev->priv = priv;
1971 dev->ops = ops;
485ebd61 1972 ds->ops = &b53_switch_ops;
967dd82f
FF		 1973 mutex_init(&dev->reg_mutex);
1974 mutex_init(&dev->stats_mutex);
1975
1976 return dev;
1977}
1978EXPORT_SYMBOL(b53_switch_alloc);
1979
1980int b53_switch_detect(struct b53_device *dev)
1981{
1982 u32 id32;
1983 u16 tmp;
1984 u8 id8;
1985 int ret;
1986
1987 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1988 if (ret)
1989 return ret;
1990
1991 switch (id8) {
1992 case 0:
1993 /* BCM5325 and BCM5365 do not have this register so reads
1994 * return 0. But the read operation did succeed, so assume this
1995 * is one of them.
1996 *
1997 * Next check if we can write to the 5325's VTA register; for
1998 * 5365 it is read only.
1999 */
2000 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2001 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2002
2003 if (tmp == 0xf)
2004 dev->chip_id = BCM5325_DEVICE_ID;
2005 else
2006 dev->chip_id = BCM5365_DEVICE_ID;
2007 break;
2008 case BCM5395_DEVICE_ID:
2009 case BCM5397_DEVICE_ID:
2010 case BCM5398_DEVICE_ID:
2011 dev->chip_id = id8;
2012 break;
2013 default:
2014 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2015 if (ret)
2016 return ret;
2017
2018 switch (id32) {
2019 case BCM53115_DEVICE_ID:
2020 case BCM53125_DEVICE_ID:
2021 case BCM53128_DEVICE_ID:
2022 case BCM53010_DEVICE_ID:
2023 case BCM53011_DEVICE_ID:
2024 case BCM53012_DEVICE_ID:
2025 case BCM53018_DEVICE_ID:
2026 case BCM53019_DEVICE_ID:
2027 dev->chip_id = id32;
2028 break;
2029 default:
2030 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2031 id8, id32);
2032 return -ENODEV;
2033 }
2034 }
2035
2036 if (dev->chip_id == BCM5325_DEVICE_ID)
2037 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2038 &dev->core_rev);
2039 else
2040 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2041 &dev->core_rev);
2042}
2043EXPORT_SYMBOL(b53_switch_detect);
2044
2045int b53_switch_register(struct b53_device *dev)
2046{
2047 int ret;
2048
2049 if (dev->pdata) {
2050 dev->chip_id = dev->pdata->chip_id;
2051 dev->enabled_ports = dev->pdata->enabled_ports;
2052 }
2053
2054 if (!dev->chip_id && b53_switch_detect(dev))
2055 return -EINVAL;
2056
2057 ret = b53_switch_init(dev);
2058 if (ret)
2059 return ret;
2060
2061 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2062
23c9ee49 2063 return dsa_register_switch(dev->ds);
967dd82f
FF		 2064}
2065EXPORT_SYMBOL(b53_switch_register);
2066
2067MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2068MODULE_DESCRIPTION("B53 switch library");
2069MODULE_LICENSE("Dual BSD/GPL");
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