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[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f
FF		 31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
bde5d132
FF		 169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
967dd82f
FF		 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
a2482d2c
FF		 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
967dd82f
FF		 249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
a2482d2c
FF		 253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
a2482d2c
FF		 268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
a2482d2c
FF		 282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
967dd82f
FF		 324}
325
a2482d2c 326static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f 327{
a424f0de 328 struct dsa_switch *ds = dev->ds;
967dd82f
FF		 329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de
FF		 339
340 /* Include IMP port in dumb forwarding mode when no tagging protocol is
341 * set
342 */
343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
347 }
967dd82f
FF		 348}
349
a2482d2c 350static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 351{
352 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
353
354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
357
358 if (is5325(dev) || is5365(dev)) {
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
361 } else if (is63xx(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
364 } else {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
367 }
368
369 mgmt &= ~SM_SW_FWD_MODE;
370
371 if (enable) {
372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
374 vc4 &= ~VC4_ING_VID_CHECK_MASK;
375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
376 vc5 |= VC5_DROP_VTABLE_MISS;
377
378 if (is5325(dev))
379 vc0 &= ~VC0_RESERVED_1;
380
381 if (is5325(dev) || is5365(dev))
382 vc1 |= VC1_RX_MCST_TAG_EN;
383
967dd82f
FF		 384 } else {
385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
387 vc4 &= ~VC4_ING_VID_CHECK_MASK;
388 vc5 &= ~VC5_DROP_VTABLE_MISS;
389
390 if (is5325(dev) || is5365(dev))
391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
392 else
393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
394
395 if (is5325(dev) || is5365(dev))
396 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 397 }
398
a2482d2c
FF		 399 if (!is5325(dev) && !is5365(dev))
400 vc5 &= ~VC5_VID_FFF_EN;
401
967dd82f
FF		 402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
404
405 if (is5325(dev) || is5365(dev)) {
406 /* enable the high 8 bit vid check on 5325 */
407 if (is5325(dev) && enable)
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
409 VC3_HIGH_8BIT_EN);
410 else
411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
412
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
415 } else if (is63xx(dev)) {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
419 } else {
420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
423 }
424
425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
426}
427
428static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
429{
430 u32 port_mask = 0;
431 u16 max_size = JMS_MIN_SIZE;
432
433 if (is5325(dev) || is5365(dev))
434 return -EINVAL;
435
436 if (enable) {
437 port_mask = dev->enabled_ports;
438 max_size = JMS_MAX_SIZE;
439 if (allow_10_100)
440 port_mask |= JPM_10_100_JUMBO_EN;
441 }
442
443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
445}
446
ff39c2d6 447static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 448{
449 unsigned int i;
450
451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 453
454 for (i = 0; i < 10; i++) {
455 u8 fast_age_ctrl;
456
457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
458 &fast_age_ctrl);
459
460 if (!(fast_age_ctrl & FAST_AGE_DONE))
461 goto out;
462
463 msleep(1);
464 }
465
466 return -ETIMEDOUT;
467out:
468 /* Only age dynamic entries (default behavior) */
469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
470 return 0;
471}
472
ff39c2d6
FF		 473static int b53_fast_age_port(struct b53_device *dev, int port)
474{
475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
476
477 return b53_flush_arl(dev, FAST_AGE_PORT);
478}
479
a2482d2c
FF		 480static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
481{
482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
483
484 return b53_flush_arl(dev, FAST_AGE_VLAN);
485}
486
aac02867 487void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 488{
04bed143 489 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 490 unsigned int i;
491 u16 pvlan;
492
493 /* Enable the IMP port to be in the same VLAN as the other ports
494 * on a per-port basis such that we only have Port i and IMP in
495 * the same VLAN.
496 */
497 b53_for_each_port(dev, i) {
498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
499 pvlan |= BIT(cpu_port);
500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
501 }
502}
aac02867 503EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 504
f86ad77f 505int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 506{
04bed143 507 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 508 unsigned int cpu_port = dev->cpu_port;
509 u16 pvlan;
967dd82f
FF		 510
511 /* Clear the Rx and Tx disable bits and set to no spanning tree */
512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
513
ff39c2d6
FF		 514 /* Set this port, and only this one to be in the default VLAN,
515 * if member of a bridge, restore its membership prior to
516 * bringing down this port.
517 */
518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
519 pvlan &= ~0x1ff;
520 pvlan |= BIT(port);
521 pvlan |= dev->ports[port].vlan_ctl_mask;
522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
523
524 b53_imp_vlan_setup(ds, cpu_port);
525
f43a2dbe
FF		 526 /* If EEE was enabled, restore it */
527 if (dev->ports[port].eee.eee_enabled)
528 b53_eee_enable_set(ds, port, true);
529
967dd82f
FF		 530 return 0;
531}
f86ad77f 532EXPORT_SYMBOL(b53_enable_port);
967dd82f 533
f86ad77f 534void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 535{
04bed143 536 struct b53_device *dev = ds->priv;
967dd82f
FF		 537 u8 reg;
538
539 /* Disable Tx/Rx for the port */
540 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
541 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
542 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
543}
f86ad77f 544EXPORT_SYMBOL(b53_disable_port);
967dd82f 545
b409a9ef
FF		 546void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
547{
548 struct b53_device *dev = ds->priv;
549 u8 hdr_ctl, val;
550 u16 reg;
551
552 /* Resolve which bit controls the Broadcom tag */
553 switch (port) {
554 case 8:
555 val = BRCM_HDR_P8_EN;
556 break;
557 case 7:
558 val = BRCM_HDR_P7_EN;
559 break;
560 case 5:
561 val = BRCM_HDR_P5_EN;
562 break;
563 default:
564 val = 0;
565 break;
566 }
567
568 /* Enable Broadcom tags for IMP port */
569 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
570 hdr_ctl |= val;
571 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
572
573 /* Registers below are only accessible on newer devices */
574 if (!is58xx(dev))
575 return;
576
577 /* Enable reception Broadcom tag for CPU TX (switch RX) to
578 * allow us to tag outgoing frames
579 */
580 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
581 reg &= ~BIT(port);
582 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
583
584 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
585 * allow delivering frames to the per-port net_devices
586 */
587 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
588 reg &= ~BIT(port);
589 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
590}
591EXPORT_SYMBOL(b53_brcm_hdr_setup);
592
299752a7 593static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 594{
967dd82f
FF		 595 u8 port_ctrl;
596
597 /* BCM5325 CPU port is at 8 */
299752a7
FF		 598 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
599 port = B53_CPU_PORT;
967dd82f
FF		 600
601 port_ctrl = PORT_CTRL_RX_BCST_EN |
602 PORT_CTRL_RX_MCST_EN |
603 PORT_CTRL_RX_UCST_EN;
299752a7 604 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
967dd82f
FF		 605}
606
607static void b53_enable_mib(struct b53_device *dev)
608{
609 u8 gc;
610
611 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
612 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
613 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
614}
615
616static int b53_configure_vlan(struct b53_device *dev)
617{
a2482d2c 618 struct b53_vlan vl = { 0 };
967dd82f
FF		 619 int i;
620
621 /* clear all vlan entries */
622 if (is5325(dev) || is5365(dev)) {
623 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 624 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 625 } else {
626 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
627 }
628
629 b53_enable_vlan(dev, false);
630
631 b53_for_each_port(dev, i)
632 b53_write16(dev, B53_VLAN_PAGE,
633 B53_VLAN_PORT_DEF_TAG(i), 1);
634
635 if (!is5325(dev) && !is5365(dev))
636 b53_set_jumbo(dev, dev->enable_jumbo, false);
637
638 return 0;
639}
640
641static void b53_switch_reset_gpio(struct b53_device *dev)
642{
643 int gpio = dev->reset_gpio;
644
645 if (gpio < 0)
646 return;
647
648 /* Reset sequence: RESET low(50ms)->high(20ms)
649 */
650 gpio_set_value(gpio, 0);
651 mdelay(50);
652
653 gpio_set_value(gpio, 1);
654 mdelay(20);
655
656 dev->current_page = 0xff;
657}
658
659static int b53_switch_reset(struct b53_device *dev)
660{
3fb22b05
FF		 661 unsigned int timeout = 1000;
662 u8 mgmt, reg;
967dd82f
FF		 663
664 b53_switch_reset_gpio(dev);
665
666 if (is539x(dev)) {
667 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
668 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
669 }
670
3fb22b05
FF		 671 /* This is specific to 58xx devices here, do not use is58xx() which
672 * covers the larger Starfigther 2 family, including 7445/7278 which
673 * still use this driver as a library and need to perform the reset
674 * earlier.
675 */
676 if (dev->chip_id == BCM58XX_DEVICE_ID) {
677 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
678 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
680
681 do {
682 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
683 if (!(reg & SW_RST))
684 break;
685
686 usleep_range(1000, 2000);
687 } while (timeout-- > 0);
688
689 if (timeout == 0)
690 return -ETIMEDOUT;
691 }
692
967dd82f
FF		 693 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
694
695 if (!(mgmt & SM_SW_FWD_EN)) {
696 mgmt &= ~SM_SW_FWD_MODE;
697 mgmt |= SM_SW_FWD_EN;
698
699 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
700 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
701
702 if (!(mgmt & SM_SW_FWD_EN)) {
703 dev_err(dev->dev, "Failed to enable switch!\n");
704 return -EINVAL;
705 }
706 }
707
708 b53_enable_mib(dev);
709
ff39c2d6 710 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 711}
712
713static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
714{
04bed143 715 struct b53_device *priv = ds->priv;
967dd82f
FF		 716 u16 value = 0;
717 int ret;
718
719 if (priv->ops->phy_read16)
720 ret = priv->ops->phy_read16(priv, addr, reg, &value);
721 else
722 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
723 reg * 2, &value);
724
725 return ret ? ret : value;
726}
727
728static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
729{
04bed143 730 struct b53_device *priv = ds->priv;
967dd82f
FF		 731
732 if (priv->ops->phy_write16)
733 return priv->ops->phy_write16(priv, addr, reg, val);
734
735 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
736}
737
738static int b53_reset_switch(struct b53_device *priv)
739{
740 /* reset vlans */
741 priv->enable_jumbo = false;
742
a2482d2c 743 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 744 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
745
746 return b53_switch_reset(priv);
747}
748
749static int b53_apply_config(struct b53_device *priv)
750{
751 /* disable switching */
752 b53_set_forwarding(priv, 0);
753
754 b53_configure_vlan(priv);
755
756 /* enable switching */
757 b53_set_forwarding(priv, 1);
758
759 return 0;
760}
761
762static void b53_reset_mib(struct b53_device *priv)
763{
764 u8 gc;
765
766 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
767
768 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
769 msleep(1);
770 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
771 msleep(1);
772}
773
774static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
775{
776 if (is5365(dev))
777 return b53_mibs_65;
778 else if (is63xx(dev))
779 return b53_mibs_63xx;
bde5d132
FF		 780 else if (is58xx(dev))
781 return b53_mibs_58xx;
967dd82f
FF		 782 else
783 return b53_mibs;
784}
785
786static unsigned int b53_get_mib_size(struct b53_device *dev)
787{
788 if (is5365(dev))
789 return B53_MIBS_65_SIZE;
790 else if (is63xx(dev))
791 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 792 else if (is58xx(dev))
793 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 794 else
795 return B53_MIBS_SIZE;
796}
797
3117455d 798void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
967dd82f 799{
04bed143 800 struct b53_device *dev = ds->priv;
967dd82f
FF		 801 const struct b53_mib_desc *mibs = b53_get_mib(dev);
802 unsigned int mib_size = b53_get_mib_size(dev);
803 unsigned int i;
804
805 for (i = 0; i < mib_size; i++)
806 memcpy(data + i * ETH_GSTRING_LEN,
807 mibs[i].name, ETH_GSTRING_LEN);
808}
3117455d 809EXPORT_SYMBOL(b53_get_strings);
967dd82f 810
3117455d 811void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 812{
04bed143 813 struct b53_device *dev = ds->priv;
967dd82f
FF		 814 const struct b53_mib_desc *mibs = b53_get_mib(dev);
815 unsigned int mib_size = b53_get_mib_size(dev);
816 const struct b53_mib_desc *s;
817 unsigned int i;
818 u64 val = 0;
819
820 if (is5365(dev) && port == 5)
821 port = 8;
822
823 mutex_lock(&dev->stats_mutex);
824
825 for (i = 0; i < mib_size; i++) {
826 s = &mibs[i];
827
51dca8a1 828 if (s->size == 8) {
967dd82f
FF		 829 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
830 } else {
831 u32 val32;
832
833 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
834 &val32);
835 val = val32;
836 }
837 data[i] = (u64)val;
838 }
839
840 mutex_unlock(&dev->stats_mutex);
841}
3117455d 842EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 843
3117455d 844int b53_get_sset_count(struct dsa_switch *ds)
967dd82f 845{
04bed143 846 struct b53_device *dev = ds->priv;
967dd82f
FF		 847
848 return b53_get_mib_size(dev);
849}
3117455d 850EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 851
967dd82f
FF		 852static int b53_setup(struct dsa_switch *ds)
853{
04bed143 854 struct b53_device *dev = ds->priv;
967dd82f
FF		 855 unsigned int port;
856 int ret;
857
858 ret = b53_reset_switch(dev);
859 if (ret) {
860 dev_err(ds->dev, "failed to reset switch\n");
861 return ret;
862 }
863
864 b53_reset_mib(dev);
865
866 ret = b53_apply_config(dev);
867 if (ret)
868 dev_err(ds->dev, "failed to apply configuration\n");
869
34c8befd
FF		 870 /* Configure IMP/CPU port, disable unused ports. Enabled
871 * ports will be configured with .port_enable
872 */
967dd82f 873 for (port = 0; port < dev->num_ports; port++) {
34c8befd 874 if (dsa_is_cpu_port(ds, port))
299752a7 875 b53_enable_cpu_port(dev, port);
34c8befd 876 else if (!(BIT(port) & ds->enabled_port_mask))
967dd82f
FF		 877 b53_disable_port(ds, port, NULL);
878 }
879
880 return ret;
881}
882
883static void b53_adjust_link(struct dsa_switch *ds, int port,
884 struct phy_device *phydev)
885{
04bed143 886 struct b53_device *dev = ds->priv;
f43a2dbe 887 struct ethtool_eee *p = &dev->ports[port].eee;
967dd82f
FF		 888 u8 rgmii_ctrl = 0, reg = 0, off;
889
890 if (!phy_is_pseudo_fixed_link(phydev))
891 return;
892
893 /* Override the port settings */
894 if (port == dev->cpu_port) {
895 off = B53_PORT_OVERRIDE_CTRL;
896 reg = PORT_OVERRIDE_EN;
897 } else {
898 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
899 reg = GMII_PO_EN;
900 }
901
902 /* Set the link UP */
903 if (phydev->link)
904 reg |= PORT_OVERRIDE_LINK;
905
906 if (phydev->duplex == DUPLEX_FULL)
907 reg |= PORT_OVERRIDE_FULL_DUPLEX;
908
909 switch (phydev->speed) {
910 case 2000:
911 reg |= PORT_OVERRIDE_SPEED_2000M;
912 /* fallthrough */
913 case SPEED_1000:
914 reg |= PORT_OVERRIDE_SPEED_1000M;
915 break;
916 case SPEED_100:
917 reg |= PORT_OVERRIDE_SPEED_100M;
918 break;
919 case SPEED_10:
920 reg |= PORT_OVERRIDE_SPEED_10M;
921 break;
922 default:
923 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
924 return;
925 }
926
927 /* Enable flow control on BCM5301x's CPU port */
928 if (is5301x(dev) && port == dev->cpu_port)
929 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
930
931 if (phydev->pause) {
932 if (phydev->asym_pause)
933 reg |= PORT_OVERRIDE_TX_FLOW;
934 reg |= PORT_OVERRIDE_RX_FLOW;
935 }
936
937 b53_write8(dev, B53_CTRL_PAGE, off, reg);
938
939 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
940 if (port == 8)
941 off = B53_RGMII_CTRL_IMP;
942 else
943 off = B53_RGMII_CTRL_P(port);
944
945 /* Configure the port RGMII clock delay by DLL disabled and
946 * tx_clk aligned timing (restoring to reset defaults)
947 */
948 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
949 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
950 RGMII_CTRL_TIMING_SEL);
951
952 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
953 * sure that we enable the port TX clock internal delay to
954 * account for this internal delay that is inserted, otherwise
955 * the switch won't be able to receive correctly.
956 *
957 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
958 * any delay neither on transmission nor reception, so the
959 * BCM53125 must also be configured accordingly to account for
960 * the lack of delay and introduce
961 *
962 * The BCM53125 switch has its RX clock and TX clock control
963 * swapped, hence the reason why we modify the TX clock path in
964 * the "RGMII" case
965 */
966 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
967 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
968 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
969 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
970 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
971 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
972
973 dev_info(ds->dev, "Configured port %d for %s\n", port,
974 phy_modes(phydev->interface));
975 }
976
977 /* configure MII port if necessary */
978 if (is5325(dev)) {
979 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
980 &reg);
981
982 /* reverse mii needs to be enabled */
983 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
984 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
985 reg | PORT_OVERRIDE_RV_MII_25);
986 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
987 &reg);
988
989 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
990 dev_err(ds->dev,
991 "Failed to enable reverse MII mode\n");
992 return;
993 }
994 }
995 } else if (is5301x(dev)) {
996 if (port != dev->cpu_port) {
997 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
998 u8 gmii_po;
999
1000 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1001 gmii_po |= GMII_PO_LINK |
1002 GMII_PO_RX_FLOW |
1003 GMII_PO_TX_FLOW |
1004 GMII_PO_EN |
1005 GMII_PO_SPEED_2000M;
1006 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1007 }
1008 }
f43a2dbe
FF		 1009
1010 /* Re-negotiate EEE if it was enabled already */
1011 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1012}
1013
3117455d 1014int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 1015{
1016 return 0;
1017}
3117455d 1018EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1019
3117455d
FF		 1020int b53_vlan_prepare(struct dsa_switch *ds, int port,
1021 const struct switchdev_obj_port_vlan *vlan,
1022 struct switchdev_trans *trans)
a2482d2c 1023{
04bed143 1024 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1025
1026 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1027 return -EOPNOTSUPP;
1028
1029 if (vlan->vid_end > dev->num_vlans)
1030 return -ERANGE;
1031
1032 b53_enable_vlan(dev, true);
1033
1034 return 0;
1035}
3117455d 1036EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 1037
3117455d
FF		 1038void b53_vlan_add(struct dsa_switch *ds, int port,
1039 const struct switchdev_obj_port_vlan *vlan,
1040 struct switchdev_trans *trans)
a2482d2c 1041{
04bed143 1042 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1043 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1044 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1045 unsigned int cpu_port = dev->cpu_port;
1046 struct b53_vlan *vl;
1047 u16 vid;
1048
1049 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1050 vl = &dev->vlans[vid];
1051
1052 b53_get_vlan_entry(dev, vid, vl);
1053
1054 vl->members |= BIT(port) | BIT(cpu_port);
1055 if (untagged)
e47112d9 1056 vl->untag |= BIT(port);
a2482d2c 1057 else
e47112d9
FF		 1058 vl->untag &= ~BIT(port);
1059 vl->untag &= ~BIT(cpu_port);
a2482d2c
FF		 1060
1061 b53_set_vlan_entry(dev, vid, vl);
1062 b53_fast_age_vlan(dev, vid);
1063 }
1064
1065 if (pvid) {
1066 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1067 vlan->vid_end);
a2482d2c
FF		 1068 b53_fast_age_vlan(dev, vid);
1069 }
1070}
3117455d 1071EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1072
3117455d
FF		 1073int b53_vlan_del(struct dsa_switch *ds, int port,
1074 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1075{
04bed143 1076 struct b53_device *dev = ds->priv;
a2482d2c 1077 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1078 struct b53_vlan *vl;
1079 u16 vid;
1080 u16 pvid;
1081
1082 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1083
1084 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1085 vl = &dev->vlans[vid];
1086
1087 b53_get_vlan_entry(dev, vid, vl);
1088
1089 vl->members &= ~BIT(port);
a2482d2c
FF		 1090
1091 if (pvid == vid) {
1092 if (is5325(dev) || is5365(dev))
1093 pvid = 1;
1094 else
1095 pvid = 0;
1096 }
1097
e47112d9 1098 if (untagged)
a2482d2c 1099 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1100
1101 b53_set_vlan_entry(dev, vid, vl);
1102 b53_fast_age_vlan(dev, vid);
1103 }
1104
1105 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1106 b53_fast_age_vlan(dev, pvid);
1107
1108 return 0;
1109}
3117455d 1110EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1111
1da6df85
FF		 1112/* Address Resolution Logic routines */
1113static int b53_arl_op_wait(struct b53_device *dev)
1114{
1115 unsigned int timeout = 10;
1116 u8 reg;
1117
1118 do {
1119 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1120 if (!(reg & ARLTBL_START_DONE))
1121 return 0;
1122
1123 usleep_range(1000, 2000);
1124 } while (timeout--);
1125
1126 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1127
1128 return -ETIMEDOUT;
1129}
1130
1131static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1132{
1133 u8 reg;
1134
1135 if (op > ARLTBL_RW)
1136 return -EINVAL;
1137
1138 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1139 reg |= ARLTBL_START_DONE;
1140 if (op)
1141 reg |= ARLTBL_RW;
1142 else
1143 reg &= ~ARLTBL_RW;
1144 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1145
1146 return b53_arl_op_wait(dev);
1147}
1148
1149static int b53_arl_read(struct b53_device *dev, u64 mac,
1150 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1151 bool is_valid)
1152{
1153 unsigned int i;
1154 int ret;
1155
1156 ret = b53_arl_op_wait(dev);
1157 if (ret)
1158 return ret;
1159
1160 /* Read the bins */
1161 for (i = 0; i < dev->num_arl_entries; i++) {
1162 u64 mac_vid;
1163 u32 fwd_entry;
1164
1165 b53_read64(dev, B53_ARLIO_PAGE,
1166 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1167 b53_read32(dev, B53_ARLIO_PAGE,
1168 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1169 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1170
1171 if (!(fwd_entry & ARLTBL_VALID))
1172 continue;
1173 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1174 continue;
1175 *idx = i;
1176 }
1177
1178 return -ENOENT;
1179}
1180
1181static int b53_arl_op(struct b53_device *dev, int op, int port,
1182 const unsigned char *addr, u16 vid, bool is_valid)
1183{
1184 struct b53_arl_entry ent;
1185 u32 fwd_entry;
1186 u64 mac, mac_vid = 0;
1187 u8 idx = 0;
1188 int ret;
1189
1190 /* Convert the array into a 64-bit MAC */
4b92ea81 1191 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1192
1193 /* Perform a read for the given MAC and VID */
1194 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1195 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1196
1197 /* Issue a read operation for this MAC */
1198 ret = b53_arl_rw_op(dev, 1);
1199 if (ret)
1200 return ret;
1201
1202 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1203 /* If this is a read, just finish now */
1204 if (op)
1205 return ret;
1206
1207 /* We could not find a matching MAC, so reset to a new entry */
1208 if (ret) {
1209 fwd_entry = 0;
1210 idx = 1;
1211 }
1212
1213 memset(&ent, 0, sizeof(ent));
1214 ent.port = port;
1215 ent.is_valid = is_valid;
1216 ent.vid = vid;
1217 ent.is_static = true;
1218 memcpy(ent.mac, addr, ETH_ALEN);
1219 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1220
1221 b53_write64(dev, B53_ARLIO_PAGE,
1222 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1223 b53_write32(dev, B53_ARLIO_PAGE,
1224 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1225
1226 return b53_arl_rw_op(dev, 0);
1227}
1228
1b6dd556
AS		 1229int b53_fdb_add(struct dsa_switch *ds, int port,
1230 const unsigned char *addr, u16 vid)
1da6df85 1231{
04bed143 1232 struct b53_device *priv = ds->priv;
1da6df85
FF		 1233
1234 /* 5325 and 5365 require some more massaging, but could
1235 * be supported eventually
1236 */
1237 if (is5325(priv) || is5365(priv))
1238 return -EOPNOTSUPP;
1239
1b6dd556 1240 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1241}
3117455d 1242EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1243
3117455d 1244int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1245 const unsigned char *addr, u16 vid)
1da6df85 1246{
04bed143 1247 struct b53_device *priv = ds->priv;
1da6df85 1248
6c2c1dcb 1249 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1250}
3117455d 1251EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1252
1253static int b53_arl_search_wait(struct b53_device *dev)
1254{
1255 unsigned int timeout = 1000;
1256 u8 reg;
1257
1258 do {
1259 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1260 if (!(reg & ARL_SRCH_STDN))
1261 return 0;
1262
1263 if (reg & ARL_SRCH_VLID)
1264 return 0;
1265
1266 usleep_range(1000, 2000);
1267 } while (timeout--);
1268
1269 return -ETIMEDOUT;
1270}
1271
1272static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1273 struct b53_arl_entry *ent)
1274{
1275 u64 mac_vid;
1276 u32 fwd_entry;
1277
1278 b53_read64(dev, B53_ARLIO_PAGE,
1279 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1280 b53_read32(dev, B53_ARLIO_PAGE,
1281 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1282 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1283}
1284
e6cbef0c 1285static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1286 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1287{
1288 if (!ent->is_valid)
1289 return 0;
1290
1291 if (port != ent->port)
1292 return 0;
1293
2bedde1a 1294 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1295}
1296
3117455d 1297int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1298 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1299{
04bed143 1300 struct b53_device *priv = ds->priv;
1da6df85
FF		 1301 struct b53_arl_entry results[2];
1302 unsigned int count = 0;
1303 int ret;
1304 u8 reg;
1305
1306 /* Start search operation */
1307 reg = ARL_SRCH_STDN;
1308 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1309
1310 do {
1311 ret = b53_arl_search_wait(priv);
1312 if (ret)
1313 return ret;
1314
1315 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1316 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1317 if (ret)
1318 return ret;
1319
1320 if (priv->num_arl_entries > 2) {
1321 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1322 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1323 if (ret)
1324 return ret;
1325
1326 if (!results[0].is_valid && !results[1].is_valid)
1327 break;
1328 }
1329
1330 } while (count++ < 1024);
1331
1332 return 0;
1333}
3117455d 1334EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1335
ddd3a0c8 1336int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1337{
04bed143 1338 struct b53_device *dev = ds->priv;
0abfd494 1339 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6
FF		 1340 u16 pvlan, reg;
1341 unsigned int i;
1342
48aea33a
FF		 1343 /* Make this port leave the all VLANs join since we will have proper
1344 * VLAN entries from now on
1345 */
1346 if (is58xx(dev)) {
1347 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1348 reg &= ~BIT(port);
1349 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1350 reg &= ~BIT(cpu_port);
1351 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1352 }
1353
ff39c2d6
FF		 1354 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1355
1356 b53_for_each_port(dev, i) {
c8652c83 1357 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1358 continue;
1359
1360 /* Add this local port to the remote port VLAN control
1361 * membership and update the remote port bitmask
1362 */
1363 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1364 reg |= BIT(port);
1365 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1366 dev->ports[i].vlan_ctl_mask = reg;
1367
1368 pvlan |= BIT(i);
1369 }
1370
1371 /* Configure the local port VLAN control membership to include
1372 * remote ports and update the local port bitmask
1373 */
1374 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1375 dev->ports[port].vlan_ctl_mask = pvlan;
1376
1377 return 0;
1378}
3117455d 1379EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1380
f123f2fb 1381void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1382{
04bed143 1383 struct b53_device *dev = ds->priv;
a2482d2c 1384 struct b53_vlan *vl = &dev->vlans[0];
0abfd494 1385 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 1386 unsigned int i;
a2482d2c 1387 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1388
1389 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1390
1391 b53_for_each_port(dev, i) {
1392 /* Don't touch the remaining ports */
c8652c83 1393 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1394 continue;
1395
1396 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1397 reg &= ~BIT(port);
1398 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1399 dev->ports[port].vlan_ctl_mask = reg;
1400
1401 /* Prevent self removal to preserve isolation */
1402 if (port != i)
1403 pvlan &= ~BIT(i);
1404 }
1405
1406 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1407 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1408
1409 if (is5325(dev) || is5365(dev))
1410 pvid = 1;
1411 else
1412 pvid = 0;
1413
48aea33a
FF		 1414 /* Make this port join all VLANs without VLAN entries */
1415 if (is58xx(dev)) {
1416 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1417 reg |= BIT(port);
1418 if (!(reg & BIT(cpu_port)))
1419 reg |= BIT(cpu_port);
1420 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1421 } else {
1422 b53_get_vlan_entry(dev, pvid, vl);
1423 vl->members |= BIT(port) | BIT(dev->cpu_port);
1424 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1425 b53_set_vlan_entry(dev, pvid, vl);
1426 }
ff39c2d6 1427}
3117455d 1428EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1429
3117455d 1430void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1431{
04bed143 1432 struct b53_device *dev = ds->priv;
597698f1 1433 u8 hw_state;
ff39c2d6
FF		 1434 u8 reg;
1435
ff39c2d6
FF		 1436 switch (state) {
1437 case BR_STATE_DISABLED:
1438 hw_state = PORT_CTRL_DIS_STATE;
1439 break;
1440 case BR_STATE_LISTENING:
1441 hw_state = PORT_CTRL_LISTEN_STATE;
1442 break;
1443 case BR_STATE_LEARNING:
1444 hw_state = PORT_CTRL_LEARN_STATE;
1445 break;
1446 case BR_STATE_FORWARDING:
1447 hw_state = PORT_CTRL_FWD_STATE;
1448 break;
1449 case BR_STATE_BLOCKING:
1450 hw_state = PORT_CTRL_BLOCK_STATE;
1451 break;
1452 default:
1453 dev_err(ds->dev, "invalid STP state: %d\n", state);
1454 return;
1455 }
1456
ff39c2d6
FF		 1457 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1458 reg &= ~PORT_CTRL_STP_STATE_MASK;
1459 reg |= hw_state;
1460 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1461}
3117455d 1462EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1463
3117455d 1464void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1465{
1466 struct b53_device *dev = ds->priv;
1467
1468 if (b53_fast_age_port(dev, port))
1469 dev_err(ds->dev, "fast ageing failed\n");
1470}
3117455d 1471EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1472
7b314362
AL		 1473static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1474{
1475 return DSA_TAG_PROTO_NONE;
1476}
1477
ed3af5fd
FF		 1478int b53_mirror_add(struct dsa_switch *ds, int port,
1479 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1480{
1481 struct b53_device *dev = ds->priv;
1482 u16 reg, loc;
1483
1484 if (ingress)
1485 loc = B53_IG_MIR_CTL;
1486 else
1487 loc = B53_EG_MIR_CTL;
1488
1489 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1490 reg &= ~MIRROR_MASK;
1491 reg |= BIT(port);
1492 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1493
1494 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1495 reg &= ~CAP_PORT_MASK;
1496 reg |= mirror->to_local_port;
1497 reg |= MIRROR_EN;
1498 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1499
1500 return 0;
1501}
1502EXPORT_SYMBOL(b53_mirror_add);
1503
1504void b53_mirror_del(struct dsa_switch *ds, int port,
1505 struct dsa_mall_mirror_tc_entry *mirror)
1506{
1507 struct b53_device *dev = ds->priv;
1508 bool loc_disable = false, other_loc_disable = false;
1509 u16 reg, loc;
1510
1511 if (mirror->ingress)
1512 loc = B53_IG_MIR_CTL;
1513 else
1514 loc = B53_EG_MIR_CTL;
1515
1516 /* Update the desired ingress/egress register */
1517 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1518 reg &= ~BIT(port);
1519 if (!(reg & MIRROR_MASK))
1520 loc_disable = true;
1521 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1522
1523 /* Now look at the other one to know if we can disable mirroring
1524 * entirely
1525 */
1526 if (mirror->ingress)
1527 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1528 else
1529 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1530 if (!(reg & MIRROR_MASK))
1531 other_loc_disable = true;
1532
1533 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1534 /* Both no longer have ports, let's disable mirroring */
1535 if (loc_disable && other_loc_disable) {
1536 reg &= ~MIRROR_EN;
1537 reg &= ~mirror->to_local_port;
1538 }
1539 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1540}
1541EXPORT_SYMBOL(b53_mirror_del);
1542
22256b0a
FF		 1543void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1544{
1545 struct b53_device *dev = ds->priv;
1546 u16 reg;
1547
1548 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1549 if (enable)
1550 reg |= BIT(port);
1551 else
1552 reg &= ~BIT(port);
1553 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1554}
1555EXPORT_SYMBOL(b53_eee_enable_set);
1556
1557
1558/* Returns 0 if EEE was not enabled, or 1 otherwise
1559 */
1560int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1561{
1562 int ret;
1563
1564 ret = phy_init_eee(phy, 0);
1565 if (ret)
1566 return 0;
1567
1568 b53_eee_enable_set(ds, port, true);
1569
1570 return 1;
1571}
1572EXPORT_SYMBOL(b53_eee_init);
1573
1574int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1575{
1576 struct b53_device *dev = ds->priv;
1577 struct ethtool_eee *p = &dev->ports[port].eee;
1578 u16 reg;
1579
1580 if (is5325(dev) || is5365(dev))
1581 return -EOPNOTSUPP;
1582
1583 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1584 e->eee_enabled = p->eee_enabled;
1585 e->eee_active = !!(reg & BIT(port));
1586
1587 return 0;
1588}
1589EXPORT_SYMBOL(b53_get_mac_eee);
1590
1591int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1592{
1593 struct b53_device *dev = ds->priv;
1594 struct ethtool_eee *p = &dev->ports[port].eee;
1595
1596 if (is5325(dev) || is5365(dev))
1597 return -EOPNOTSUPP;
1598
1599 p->eee_enabled = e->eee_enabled;
1600 b53_eee_enable_set(ds, port, e->eee_enabled);
1601
1602 return 0;
1603}
1604EXPORT_SYMBOL(b53_set_mac_eee);
1605
a82f67af 1606static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1607 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1608 .setup = b53_setup,
967dd82f
FF		 1609 .get_strings = b53_get_strings,
1610 .get_ethtool_stats = b53_get_ethtool_stats,
1611 .get_sset_count = b53_get_sset_count,
1612 .phy_read = b53_phy_read16,
1613 .phy_write = b53_phy_write16,
1614 .adjust_link = b53_adjust_link,
1615 .port_enable = b53_enable_port,
1616 .port_disable = b53_disable_port,
f43a2dbe
FF		 1617 .get_mac_eee = b53_get_mac_eee,
1618 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 1619 .port_bridge_join = b53_br_join,
1620 .port_bridge_leave = b53_br_leave,
1621 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1622 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1623 .port_vlan_filtering = b53_vlan_filtering,
1624 .port_vlan_prepare = b53_vlan_prepare,
1625 .port_vlan_add = b53_vlan_add,
1626 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 1627 .port_fdb_dump = b53_fdb_dump,
1628 .port_fdb_add = b53_fdb_add,
1629 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1630 .port_mirror_add = b53_mirror_add,
1631 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1632};
1633
1634struct b53_chip_data {
1635 u32 chip_id;
1636 const char *dev_name;
1637 u16 vlans;
1638 u16 enabled_ports;
1639 u8 cpu_port;
1640 u8 vta_regs[3];
1da6df85 1641 u8 arl_entries;
967dd82f
FF		 1642 u8 duplex_reg;
1643 u8 jumbo_pm_reg;
1644 u8 jumbo_size_reg;
1645};
1646
1647#define B53_VTA_REGS \
1648 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1649#define B53_VTA_REGS_9798 \
1650 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1651#define B53_VTA_REGS_63XX \
1652 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1653
1654static const struct b53_chip_data b53_switch_chips[] = {
1655 {
1656 .chip_id = BCM5325_DEVICE_ID,
1657 .dev_name = "BCM5325",
1658 .vlans = 16,
1659 .enabled_ports = 0x1f,
1da6df85 1660 .arl_entries = 2,
967dd82f
FF		 1661 .cpu_port = B53_CPU_PORT_25,
1662 .duplex_reg = B53_DUPLEX_STAT_FE,
1663 },
1664 {
1665 .chip_id = BCM5365_DEVICE_ID,
1666 .dev_name = "BCM5365",
1667 .vlans = 256,
1668 .enabled_ports = 0x1f,
1da6df85 1669 .arl_entries = 2,
967dd82f
FF		 1670 .cpu_port = B53_CPU_PORT_25,
1671 .duplex_reg = B53_DUPLEX_STAT_FE,
1672 },
1673 {
1674 .chip_id = BCM5395_DEVICE_ID,
1675 .dev_name = "BCM5395",
1676 .vlans = 4096,
1677 .enabled_ports = 0x1f,
1da6df85 1678 .arl_entries = 4,
967dd82f
FF		 1679 .cpu_port = B53_CPU_PORT,
1680 .vta_regs = B53_VTA_REGS,
1681 .duplex_reg = B53_DUPLEX_STAT_GE,
1682 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1683 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1684 },
1685 {
1686 .chip_id = BCM5397_DEVICE_ID,
1687 .dev_name = "BCM5397",
1688 .vlans = 4096,
1689 .enabled_ports = 0x1f,
1da6df85 1690 .arl_entries = 4,
967dd82f
FF		 1691 .cpu_port = B53_CPU_PORT,
1692 .vta_regs = B53_VTA_REGS_9798,
1693 .duplex_reg = B53_DUPLEX_STAT_GE,
1694 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1695 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1696 },
1697 {
1698 .chip_id = BCM5398_DEVICE_ID,
1699 .dev_name = "BCM5398",
1700 .vlans = 4096,
1701 .enabled_ports = 0x7f,
1da6df85 1702 .arl_entries = 4,
967dd82f
FF		 1703 .cpu_port = B53_CPU_PORT,
1704 .vta_regs = B53_VTA_REGS_9798,
1705 .duplex_reg = B53_DUPLEX_STAT_GE,
1706 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1707 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1708 },
1709 {
1710 .chip_id = BCM53115_DEVICE_ID,
1711 .dev_name = "BCM53115",
1712 .vlans = 4096,
1713 .enabled_ports = 0x1f,
1da6df85 1714 .arl_entries = 4,
967dd82f
FF		 1715 .vta_regs = B53_VTA_REGS,
1716 .cpu_port = B53_CPU_PORT,
1717 .duplex_reg = B53_DUPLEX_STAT_GE,
1718 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1719 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1720 },
1721 {
1722 .chip_id = BCM53125_DEVICE_ID,
1723 .dev_name = "BCM53125",
1724 .vlans = 4096,
1725 .enabled_ports = 0xff,
be35e8c5 1726 .arl_entries = 4,
967dd82f
FF		 1727 .cpu_port = B53_CPU_PORT,
1728 .vta_regs = B53_VTA_REGS,
1729 .duplex_reg = B53_DUPLEX_STAT_GE,
1730 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1731 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1732 },
1733 {
1734 .chip_id = BCM53128_DEVICE_ID,
1735 .dev_name = "BCM53128",
1736 .vlans = 4096,
1737 .enabled_ports = 0x1ff,
1da6df85 1738 .arl_entries = 4,
967dd82f
FF		 1739 .cpu_port = B53_CPU_PORT,
1740 .vta_regs = B53_VTA_REGS,
1741 .duplex_reg = B53_DUPLEX_STAT_GE,
1742 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1743 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1744 },
1745 {
1746 .chip_id = BCM63XX_DEVICE_ID,
1747 .dev_name = "BCM63xx",
1748 .vlans = 4096,
1749 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1750 .arl_entries = 4,
967dd82f
FF		 1751 .cpu_port = B53_CPU_PORT,
1752 .vta_regs = B53_VTA_REGS_63XX,
1753 .duplex_reg = B53_DUPLEX_STAT_63XX,
1754 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1755 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1756 },
1757 {
1758 .chip_id = BCM53010_DEVICE_ID,
1759 .dev_name = "BCM53010",
1760 .vlans = 4096,
1761 .enabled_ports = 0x1f,
1da6df85 1762 .arl_entries = 4,
967dd82f
FF		 1763 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1764 .vta_regs = B53_VTA_REGS,
1765 .duplex_reg = B53_DUPLEX_STAT_GE,
1766 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1767 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1768 },
1769 {
1770 .chip_id = BCM53011_DEVICE_ID,
1771 .dev_name = "BCM53011",
1772 .vlans = 4096,
1773 .enabled_ports = 0x1bf,
1da6df85 1774 .arl_entries = 4,
967dd82f
FF		 1775 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1776 .vta_regs = B53_VTA_REGS,
1777 .duplex_reg = B53_DUPLEX_STAT_GE,
1778 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1779 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1780 },
1781 {
1782 .chip_id = BCM53012_DEVICE_ID,
1783 .dev_name = "BCM53012",
1784 .vlans = 4096,
1785 .enabled_ports = 0x1bf,
1da6df85 1786 .arl_entries = 4,
967dd82f
FF		 1787 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1788 .vta_regs = B53_VTA_REGS,
1789 .duplex_reg = B53_DUPLEX_STAT_GE,
1790 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1791 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1792 },
1793 {
1794 .chip_id = BCM53018_DEVICE_ID,
1795 .dev_name = "BCM53018",
1796 .vlans = 4096,
1797 .enabled_ports = 0x1f,
1da6df85 1798 .arl_entries = 4,
967dd82f
FF		 1799 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1800 .vta_regs = B53_VTA_REGS,
1801 .duplex_reg = B53_DUPLEX_STAT_GE,
1802 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1803 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1804 },
1805 {
1806 .chip_id = BCM53019_DEVICE_ID,
1807 .dev_name = "BCM53019",
1808 .vlans = 4096,
1809 .enabled_ports = 0x1f,
1da6df85 1810 .arl_entries = 4,
967dd82f
FF		 1811 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1812 .vta_regs = B53_VTA_REGS,
1813 .duplex_reg = B53_DUPLEX_STAT_GE,
1814 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1815 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1816 },
991a36bb
FF		 1817 {
1818 .chip_id = BCM58XX_DEVICE_ID,
1819 .dev_name = "BCM585xx/586xx/88312",
1820 .vlans = 4096,
1821 .enabled_ports = 0x1ff,
1822 .arl_entries = 4,
bfcda65c 1823 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 1824 .vta_regs = B53_VTA_REGS,
1825 .duplex_reg = B53_DUPLEX_STAT_GE,
1826 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1827 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1828 },
130401d9
FF		 1829 {
1830 .chip_id = BCM7445_DEVICE_ID,
1831 .dev_name = "BCM7445",
1832 .vlans = 4096,
1833 .enabled_ports = 0x1ff,
1834 .arl_entries = 4,
1835 .cpu_port = B53_CPU_PORT,
1836 .vta_regs = B53_VTA_REGS,
1837 .duplex_reg = B53_DUPLEX_STAT_GE,
1838 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1839 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1840 },
0fe99338
FF		 1841 {
1842 .chip_id = BCM7278_DEVICE_ID,
1843 .dev_name = "BCM7278",
1844 .vlans = 4096,
1845 .enabled_ports = 0x1ff,
1846 .arl_entries= 4,
1847 .cpu_port = B53_CPU_PORT,
1848 .vta_regs = B53_VTA_REGS,
1849 .duplex_reg = B53_DUPLEX_STAT_GE,
1850 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1851 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1852 },
967dd82f
FF		 1853};
1854
1855static int b53_switch_init(struct b53_device *dev)
1856{
967dd82f
FF		 1857 unsigned int i;
1858 int ret;
1859
1860 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1861 const struct b53_chip_data *chip = &b53_switch_chips[i];
1862
1863 if (chip->chip_id == dev->chip_id) {
1864 if (!dev->enabled_ports)
1865 dev->enabled_ports = chip->enabled_ports;
1866 dev->name = chip->dev_name;
1867 dev->duplex_reg = chip->duplex_reg;
1868 dev->vta_regs[0] = chip->vta_regs[0];
1869 dev->vta_regs[1] = chip->vta_regs[1];
1870 dev->vta_regs[2] = chip->vta_regs[2];
1871 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1872 dev->cpu_port = chip->cpu_port;
1873 dev->num_vlans = chip->vlans;
1da6df85 1874 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1875 break;
1876 }
1877 }
1878
1879 /* check which BCM5325x version we have */
1880 if (is5325(dev)) {
1881 u8 vc4;
1882
1883 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1884
1885 /* check reserved bits */
1886 switch (vc4 & 3) {
1887 case 1:
1888 /* BCM5325E */
1889 break;
1890 case 3:
1891 /* BCM5325F - do not use port 4 */
1892 dev->enabled_ports &= ~BIT(4);
1893 break;
1894 default:
1895/* On the BCM47XX SoCs this is the supported internal switch.*/
1896#ifndef CONFIG_BCM47XX
1897 /* BCM5325M */
1898 return -EINVAL;
1899#else
1900 break;
1901#endif
1902 }
1903 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1904 u64 strap_value;
1905
1906 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1907 /* use second IMP port if GMII is enabled */
1908 if (strap_value & SV_GMII_CTRL_115)
1909 dev->cpu_port = 5;
1910 }
1911
1912 /* cpu port is always last */
1913 dev->num_ports = dev->cpu_port + 1;
1914 dev->enabled_ports |= BIT(dev->cpu_port);
1915
1916 dev->ports = devm_kzalloc(dev->dev,
1917 sizeof(struct b53_port) * dev->num_ports,
1918 GFP_KERNEL);
1919 if (!dev->ports)
1920 return -ENOMEM;
1921
a2482d2c
FF		 1922 dev->vlans = devm_kzalloc(dev->dev,
1923 sizeof(struct b53_vlan) * dev->num_vlans,
1924 GFP_KERNEL);
1925 if (!dev->vlans)
1926 return -ENOMEM;
1927
967dd82f
FF		 1928 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1929 if (dev->reset_gpio >= 0) {
1930 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1931 GPIOF_OUT_INIT_HIGH, "robo_reset");
1932 if (ret)
1933 return ret;
1934 }
1935
1936 return 0;
1937}
1938
0dff88d3
JL		 1939struct b53_device *b53_switch_alloc(struct device *base,
1940 const struct b53_io_ops *ops,
967dd82f
FF		 1941 void *priv)
1942{
1943 struct dsa_switch *ds;
1944 struct b53_device *dev;
1945
a0c02161 1946 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 1947 if (!ds)
1948 return NULL;
1949
a0c02161
VD		 1950 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1951 if (!dev)
1952 return NULL;
967dd82f
FF		 1953
1954 ds->priv = dev;
967dd82f
FF		 1955 dev->dev = base;
1956
1957 dev->ds = ds;
1958 dev->priv = priv;
1959 dev->ops = ops;
485ebd61 1960 ds->ops = &b53_switch_ops;
967dd82f
FF		 1961 mutex_init(&dev->reg_mutex);
1962 mutex_init(&dev->stats_mutex);
1963
1964 return dev;
1965}
1966EXPORT_SYMBOL(b53_switch_alloc);
1967
1968int b53_switch_detect(struct b53_device *dev)
1969{
1970 u32 id32;
1971 u16 tmp;
1972 u8 id8;
1973 int ret;
1974
1975 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1976 if (ret)
1977 return ret;
1978
1979 switch (id8) {
1980 case 0:
1981 /* BCM5325 and BCM5365 do not have this register so reads
1982 * return 0. But the read operation did succeed, so assume this
1983 * is one of them.
1984 *
1985 * Next check if we can write to the 5325's VTA register; for
1986 * 5365 it is read only.
1987 */
1988 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1989 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1990
1991 if (tmp == 0xf)
1992 dev->chip_id = BCM5325_DEVICE_ID;
1993 else
1994 dev->chip_id = BCM5365_DEVICE_ID;
1995 break;
1996 case BCM5395_DEVICE_ID:
1997 case BCM5397_DEVICE_ID:
1998 case BCM5398_DEVICE_ID:
1999 dev->chip_id = id8;
2000 break;
2001 default:
2002 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2003 if (ret)
2004 return ret;
2005
2006 switch (id32) {
2007 case BCM53115_DEVICE_ID:
2008 case BCM53125_DEVICE_ID:
2009 case BCM53128_DEVICE_ID:
2010 case BCM53010_DEVICE_ID:
2011 case BCM53011_DEVICE_ID:
2012 case BCM53012_DEVICE_ID:
2013 case BCM53018_DEVICE_ID:
2014 case BCM53019_DEVICE_ID:
2015 dev->chip_id = id32;
2016 break;
2017 default:
2018 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2019 id8, id32);
2020 return -ENODEV;
2021 }
2022 }
2023
2024 if (dev->chip_id == BCM5325_DEVICE_ID)
2025 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2026 &dev->core_rev);
2027 else
2028 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2029 &dev->core_rev);
2030}
2031EXPORT_SYMBOL(b53_switch_detect);
2032
2033int b53_switch_register(struct b53_device *dev)
2034{
2035 int ret;
2036
2037 if (dev->pdata) {
2038 dev->chip_id = dev->pdata->chip_id;
2039 dev->enabled_ports = dev->pdata->enabled_ports;
2040 }
2041
2042 if (!dev->chip_id && b53_switch_detect(dev))
2043 return -EINVAL;
2044
2045 ret = b53_switch_init(dev);
2046 if (ret)
2047 return ret;
2048
2049 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2050
23c9ee49 2051 return dsa_register_switch(dev->ds);
967dd82f
FF		 2052}
2053EXPORT_SYMBOL(b53_switch_register);
2054
2055MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2056MODULE_DESCRIPTION("B53 switch library");
2057MODULE_LICENSE("Dual BSD/GPL");
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