]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/dsa/b53/b53_common.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: dsa: Pass a port to get_tag_protocol()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f
FF		 31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
bde5d132
FF		 169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
967dd82f
FF		 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
a2482d2c
FF		 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
967dd82f
FF		 249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
a2482d2c
FF		 253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
a2482d2c
FF		 268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
a2482d2c
FF		 282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
967dd82f
FF		 324}
325
a2482d2c 326static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f
FF		 327{
328 u8 mgmt;
329
330 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
331
332 if (enable)
333 mgmt |= SM_SW_FWD_EN;
334 else
335 mgmt &= ~SM_SW_FWD_EN;
336
337 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de 338
7edc58d6 339 /* Include IMP port in dumb forwarding mode
a424f0de 340 */
7edc58d6
FF		 341 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
342 mgmt |= B53_MII_DUMB_FWDG_EN;
343 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
967dd82f
FF		 344}
345
a2482d2c 346static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 347{
348 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
349
350 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
353
354 if (is5325(dev) || is5365(dev)) {
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
357 } else if (is63xx(dev)) {
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
360 } else {
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
363 }
364
365 mgmt &= ~SM_SW_FWD_MODE;
366
367 if (enable) {
368 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
369 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
370 vc4 &= ~VC4_ING_VID_CHECK_MASK;
371 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
372 vc5 |= VC5_DROP_VTABLE_MISS;
373
374 if (is5325(dev))
375 vc0 &= ~VC0_RESERVED_1;
376
377 if (is5325(dev) || is5365(dev))
378 vc1 |= VC1_RX_MCST_TAG_EN;
379
967dd82f
FF		 380 } else {
381 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
382 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
383 vc4 &= ~VC4_ING_VID_CHECK_MASK;
384 vc5 &= ~VC5_DROP_VTABLE_MISS;
385
386 if (is5325(dev) || is5365(dev))
387 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
388 else
389 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
390
391 if (is5325(dev) || is5365(dev))
392 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 393 }
394
a2482d2c
FF		 395 if (!is5325(dev) && !is5365(dev))
396 vc5 &= ~VC5_VID_FFF_EN;
397
967dd82f
FF		 398 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
400
401 if (is5325(dev) || is5365(dev)) {
402 /* enable the high 8 bit vid check on 5325 */
403 if (is5325(dev) && enable)
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
405 VC3_HIGH_8BIT_EN);
406 else
407 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
408
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
411 } else if (is63xx(dev)) {
412 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
415 } else {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
419 }
420
421 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
422}
423
424static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
425{
426 u32 port_mask = 0;
427 u16 max_size = JMS_MIN_SIZE;
428
429 if (is5325(dev) || is5365(dev))
430 return -EINVAL;
431
432 if (enable) {
433 port_mask = dev->enabled_ports;
434 max_size = JMS_MAX_SIZE;
435 if (allow_10_100)
436 port_mask |= JPM_10_100_JUMBO_EN;
437 }
438
439 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
440 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
441}
442
ff39c2d6 443static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 444{
445 unsigned int i;
446
447 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 448 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 449
450 for (i = 0; i < 10; i++) {
451 u8 fast_age_ctrl;
452
453 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
454 &fast_age_ctrl);
455
456 if (!(fast_age_ctrl & FAST_AGE_DONE))
457 goto out;
458
459 msleep(1);
460 }
461
462 return -ETIMEDOUT;
463out:
464 /* Only age dynamic entries (default behavior) */
465 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
466 return 0;
467}
468
ff39c2d6
FF		 469static int b53_fast_age_port(struct b53_device *dev, int port)
470{
471 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
472
473 return b53_flush_arl(dev, FAST_AGE_PORT);
474}
475
a2482d2c
FF		 476static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
477{
478 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
479
480 return b53_flush_arl(dev, FAST_AGE_VLAN);
481}
482
aac02867 483void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 484{
04bed143 485 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 486 unsigned int i;
487 u16 pvlan;
488
489 /* Enable the IMP port to be in the same VLAN as the other ports
490 * on a per-port basis such that we only have Port i and IMP in
491 * the same VLAN.
492 */
493 b53_for_each_port(dev, i) {
494 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
495 pvlan |= BIT(cpu_port);
496 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
497 }
498}
aac02867 499EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 500
f86ad77f 501int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 502{
04bed143 503 struct b53_device *dev = ds->priv;
c499696e 504 unsigned int cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 505 u16 pvlan;
967dd82f
FF		 506
507 /* Clear the Rx and Tx disable bits and set to no spanning tree */
508 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
509
ff39c2d6
FF		 510 /* Set this port, and only this one to be in the default VLAN,
511 * if member of a bridge, restore its membership prior to
512 * bringing down this port.
513 */
514 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
515 pvlan &= ~0x1ff;
516 pvlan |= BIT(port);
517 pvlan |= dev->ports[port].vlan_ctl_mask;
518 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
519
520 b53_imp_vlan_setup(ds, cpu_port);
521
f43a2dbe
FF		 522 /* If EEE was enabled, restore it */
523 if (dev->ports[port].eee.eee_enabled)
524 b53_eee_enable_set(ds, port, true);
525
967dd82f
FF		 526 return 0;
527}
f86ad77f 528EXPORT_SYMBOL(b53_enable_port);
967dd82f 529
f86ad77f 530void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 531{
04bed143 532 struct b53_device *dev = ds->priv;
967dd82f
FF		 533 u8 reg;
534
535 /* Disable Tx/Rx for the port */
536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
539}
f86ad77f 540EXPORT_SYMBOL(b53_disable_port);
967dd82f 541
b409a9ef
FF		 542void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
543{
5ed4e3eb
FF		 544 bool tag_en = !!(ds->ops->get_tag_protocol(ds, port) ==
545 DSA_TAG_PROTO_BRCM);
b409a9ef
FF		 546 struct b53_device *dev = ds->priv;
547 u8 hdr_ctl, val;
548 u16 reg;
549
550 /* Resolve which bit controls the Broadcom tag */
551 switch (port) {
552 case 8:
553 val = BRCM_HDR_P8_EN;
554 break;
555 case 7:
556 val = BRCM_HDR_P7_EN;
557 break;
558 case 5:
559 val = BRCM_HDR_P5_EN;
560 break;
561 default:
562 val = 0;
563 break;
564 }
565
566 /* Enable Broadcom tags for IMP port */
567 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
cdb583cf
FF		 568 if (tag_en)
569 hdr_ctl |= val;
570 else
571 hdr_ctl &= ~val;
b409a9ef
FF		 572 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
573
574 /* Registers below are only accessible on newer devices */
575 if (!is58xx(dev))
576 return;
577
578 /* Enable reception Broadcom tag for CPU TX (switch RX) to
579 * allow us to tag outgoing frames
580 */
581 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
cdb583cf
FF		 582 if (tag_en)
583 reg &= ~BIT(port);
584 else
585 reg |= BIT(port);
b409a9ef
FF		 586 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
587
588 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
589 * allow delivering frames to the per-port net_devices
590 */
591 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
cdb583cf
FF		 592 if (tag_en)
593 reg &= ~BIT(port);
594 else
595 reg |= BIT(port);
b409a9ef
FF		 596 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
597}
598EXPORT_SYMBOL(b53_brcm_hdr_setup);
599
299752a7 600static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 601{
967dd82f
FF		 602 u8 port_ctrl;
603
604 /* BCM5325 CPU port is at 8 */
299752a7
FF		 605 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
606 port = B53_CPU_PORT;
967dd82f
FF		 607
608 port_ctrl = PORT_CTRL_RX_BCST_EN |
609 PORT_CTRL_RX_MCST_EN |
610 PORT_CTRL_RX_UCST_EN;
299752a7 611 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
7edc58d6
FF		 612
613 b53_brcm_hdr_setup(dev->ds, port);
967dd82f
FF		 614}
615
616static void b53_enable_mib(struct b53_device *dev)
617{
618 u8 gc;
619
620 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
621 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
622 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
623}
624
5c1a6eaf 625int b53_configure_vlan(struct dsa_switch *ds)
967dd82f 626{
5c1a6eaf 627 struct b53_device *dev = ds->priv;
a2482d2c 628 struct b53_vlan vl = { 0 };
967dd82f
FF		 629 int i;
630
631 /* clear all vlan entries */
632 if (is5325(dev) || is5365(dev)) {
633 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 634 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 635 } else {
636 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
637 }
638
639 b53_enable_vlan(dev, false);
640
641 b53_for_each_port(dev, i)
642 b53_write16(dev, B53_VLAN_PAGE,
643 B53_VLAN_PORT_DEF_TAG(i), 1);
644
645 if (!is5325(dev) && !is5365(dev))
646 b53_set_jumbo(dev, dev->enable_jumbo, false);
647
648 return 0;
649}
5c1a6eaf 650EXPORT_SYMBOL(b53_configure_vlan);
967dd82f
FF		 651
652static void b53_switch_reset_gpio(struct b53_device *dev)
653{
654 int gpio = dev->reset_gpio;
655
656 if (gpio < 0)
657 return;
658
659 /* Reset sequence: RESET low(50ms)->high(20ms)
660 */
661 gpio_set_value(gpio, 0);
662 mdelay(50);
663
664 gpio_set_value(gpio, 1);
665 mdelay(20);
666
667 dev->current_page = 0xff;
668}
669
670static int b53_switch_reset(struct b53_device *dev)
671{
3fb22b05
FF		 672 unsigned int timeout = 1000;
673 u8 mgmt, reg;
967dd82f
FF		 674
675 b53_switch_reset_gpio(dev);
676
677 if (is539x(dev)) {
678 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
680 }
681
3fb22b05
FF		 682 /* This is specific to 58xx devices here, do not use is58xx() which
683 * covers the larger Starfigther 2 family, including 7445/7278 which
684 * still use this driver as a library and need to perform the reset
685 * earlier.
686 */
687 if (dev->chip_id == BCM58XX_DEVICE_ID) {
688 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
689 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
690 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
691
692 do {
693 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
694 if (!(reg & SW_RST))
695 break;
696
697 usleep_range(1000, 2000);
698 } while (timeout-- > 0);
699
700 if (timeout == 0)
701 return -ETIMEDOUT;
702 }
703
967dd82f
FF		 704 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
705
706 if (!(mgmt & SM_SW_FWD_EN)) {
707 mgmt &= ~SM_SW_FWD_MODE;
708 mgmt |= SM_SW_FWD_EN;
709
710 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
711 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
712
713 if (!(mgmt & SM_SW_FWD_EN)) {
714 dev_err(dev->dev, "Failed to enable switch!\n");
715 return -EINVAL;
716 }
717 }
718
719 b53_enable_mib(dev);
720
ff39c2d6 721 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 722}
723
724static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
725{
04bed143 726 struct b53_device *priv = ds->priv;
967dd82f
FF		 727 u16 value = 0;
728 int ret;
729
730 if (priv->ops->phy_read16)
731 ret = priv->ops->phy_read16(priv, addr, reg, &value);
732 else
733 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
734 reg * 2, &value);
735
736 return ret ? ret : value;
737}
738
739static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
740{
04bed143 741 struct b53_device *priv = ds->priv;
967dd82f
FF		 742
743 if (priv->ops->phy_write16)
744 return priv->ops->phy_write16(priv, addr, reg, val);
745
746 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
747}
748
749static int b53_reset_switch(struct b53_device *priv)
750{
751 /* reset vlans */
752 priv->enable_jumbo = false;
753
a2482d2c 754 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 755 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
756
757 return b53_switch_reset(priv);
758}
759
760static int b53_apply_config(struct b53_device *priv)
761{
762 /* disable switching */
763 b53_set_forwarding(priv, 0);
764
5c1a6eaf 765 b53_configure_vlan(priv->ds);
967dd82f
FF		 766
767 /* enable switching */
768 b53_set_forwarding(priv, 1);
769
770 return 0;
771}
772
773static void b53_reset_mib(struct b53_device *priv)
774{
775 u8 gc;
776
777 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
778
779 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
780 msleep(1);
781 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
782 msleep(1);
783}
784
785static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
786{
787 if (is5365(dev))
788 return b53_mibs_65;
789 else if (is63xx(dev))
790 return b53_mibs_63xx;
bde5d132
FF		 791 else if (is58xx(dev))
792 return b53_mibs_58xx;
967dd82f
FF		 793 else
794 return b53_mibs;
795}
796
797static unsigned int b53_get_mib_size(struct b53_device *dev)
798{
799 if (is5365(dev))
800 return B53_MIBS_65_SIZE;
801 else if (is63xx(dev))
802 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 803 else if (is58xx(dev))
804 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 805 else
806 return B53_MIBS_SIZE;
807}
808
3117455d 809void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
967dd82f 810{
04bed143 811 struct b53_device *dev = ds->priv;
967dd82f
FF		 812 const struct b53_mib_desc *mibs = b53_get_mib(dev);
813 unsigned int mib_size = b53_get_mib_size(dev);
814 unsigned int i;
815
816 for (i = 0; i < mib_size; i++)
817 memcpy(data + i * ETH_GSTRING_LEN,
818 mibs[i].name, ETH_GSTRING_LEN);
819}
3117455d 820EXPORT_SYMBOL(b53_get_strings);
967dd82f 821
3117455d 822void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 823{
04bed143 824 struct b53_device *dev = ds->priv;
967dd82f
FF		 825 const struct b53_mib_desc *mibs = b53_get_mib(dev);
826 unsigned int mib_size = b53_get_mib_size(dev);
827 const struct b53_mib_desc *s;
828 unsigned int i;
829 u64 val = 0;
830
831 if (is5365(dev) && port == 5)
832 port = 8;
833
834 mutex_lock(&dev->stats_mutex);
835
836 for (i = 0; i < mib_size; i++) {
837 s = &mibs[i];
838
51dca8a1 839 if (s->size == 8) {
967dd82f
FF		 840 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
841 } else {
842 u32 val32;
843
844 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
845 &val32);
846 val = val32;
847 }
848 data[i] = (u64)val;
849 }
850
851 mutex_unlock(&dev->stats_mutex);
852}
3117455d 853EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 854
3117455d 855int b53_get_sset_count(struct dsa_switch *ds)
967dd82f 856{
04bed143 857 struct b53_device *dev = ds->priv;
967dd82f
FF		 858
859 return b53_get_mib_size(dev);
860}
3117455d 861EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 862
967dd82f
FF		 863static int b53_setup(struct dsa_switch *ds)
864{
04bed143 865 struct b53_device *dev = ds->priv;
967dd82f
FF		 866 unsigned int port;
867 int ret;
868
869 ret = b53_reset_switch(dev);
870 if (ret) {
871 dev_err(ds->dev, "failed to reset switch\n");
872 return ret;
873 }
874
875 b53_reset_mib(dev);
876
877 ret = b53_apply_config(dev);
878 if (ret)
879 dev_err(ds->dev, "failed to apply configuration\n");
880
34c8befd
FF		 881 /* Configure IMP/CPU port, disable unused ports. Enabled
882 * ports will be configured with .port_enable
883 */
967dd82f 884 for (port = 0; port < dev->num_ports; port++) {
34c8befd 885 if (dsa_is_cpu_port(ds, port))
299752a7 886 b53_enable_cpu_port(dev, port);
bff7b688 887 else if (dsa_is_unused_port(ds, port))
967dd82f
FF		 888 b53_disable_port(ds, port, NULL);
889 }
890
891 return ret;
892}
893
894static void b53_adjust_link(struct dsa_switch *ds, int port,
895 struct phy_device *phydev)
896{
04bed143 897 struct b53_device *dev = ds->priv;
f43a2dbe 898 struct ethtool_eee *p = &dev->ports[port].eee;
967dd82f
FF		 899 u8 rgmii_ctrl = 0, reg = 0, off;
900
901 if (!phy_is_pseudo_fixed_link(phydev))
902 return;
903
904 /* Override the port settings */
905 if (port == dev->cpu_port) {
906 off = B53_PORT_OVERRIDE_CTRL;
907 reg = PORT_OVERRIDE_EN;
908 } else {
909 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
910 reg = GMII_PO_EN;
911 }
912
913 /* Set the link UP */
914 if (phydev->link)
915 reg |= PORT_OVERRIDE_LINK;
916
917 if (phydev->duplex == DUPLEX_FULL)
918 reg |= PORT_OVERRIDE_FULL_DUPLEX;
919
920 switch (phydev->speed) {
921 case 2000:
922 reg |= PORT_OVERRIDE_SPEED_2000M;
923 /* fallthrough */
924 case SPEED_1000:
925 reg |= PORT_OVERRIDE_SPEED_1000M;
926 break;
927 case SPEED_100:
928 reg |= PORT_OVERRIDE_SPEED_100M;
929 break;
930 case SPEED_10:
931 reg |= PORT_OVERRIDE_SPEED_10M;
932 break;
933 default:
934 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
935 return;
936 }
937
938 /* Enable flow control on BCM5301x's CPU port */
939 if (is5301x(dev) && port == dev->cpu_port)
940 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
941
942 if (phydev->pause) {
943 if (phydev->asym_pause)
944 reg |= PORT_OVERRIDE_TX_FLOW;
945 reg |= PORT_OVERRIDE_RX_FLOW;
946 }
947
948 b53_write8(dev, B53_CTRL_PAGE, off, reg);
949
950 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
951 if (port == 8)
952 off = B53_RGMII_CTRL_IMP;
953 else
954 off = B53_RGMII_CTRL_P(port);
955
956 /* Configure the port RGMII clock delay by DLL disabled and
957 * tx_clk aligned timing (restoring to reset defaults)
958 */
959 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
960 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
961 RGMII_CTRL_TIMING_SEL);
962
963 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
964 * sure that we enable the port TX clock internal delay to
965 * account for this internal delay that is inserted, otherwise
966 * the switch won't be able to receive correctly.
967 *
968 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
969 * any delay neither on transmission nor reception, so the
970 * BCM53125 must also be configured accordingly to account for
971 * the lack of delay and introduce
972 *
973 * The BCM53125 switch has its RX clock and TX clock control
974 * swapped, hence the reason why we modify the TX clock path in
975 * the "RGMII" case
976 */
977 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
978 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
979 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
980 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
981 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
982 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
983
984 dev_info(ds->dev, "Configured port %d for %s\n", port,
985 phy_modes(phydev->interface));
986 }
987
988 /* configure MII port if necessary */
989 if (is5325(dev)) {
990 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
991 &reg);
992
993 /* reverse mii needs to be enabled */
994 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
995 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
996 reg | PORT_OVERRIDE_RV_MII_25);
997 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
998 &reg);
999
1000 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1001 dev_err(ds->dev,
1002 "Failed to enable reverse MII mode\n");
1003 return;
1004 }
1005 }
1006 } else if (is5301x(dev)) {
1007 if (port != dev->cpu_port) {
1008 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1009 u8 gmii_po;
1010
1011 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1012 gmii_po |= GMII_PO_LINK |
1013 GMII_PO_RX_FLOW |
1014 GMII_PO_TX_FLOW |
1015 GMII_PO_EN |
1016 GMII_PO_SPEED_2000M;
1017 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1018 }
1019 }
f43a2dbe
FF		 1020
1021 /* Re-negotiate EEE if it was enabled already */
1022 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1023}
1024
3117455d 1025int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 1026{
1027 return 0;
1028}
3117455d 1029EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1030
3117455d
FF		 1031int b53_vlan_prepare(struct dsa_switch *ds, int port,
1032 const struct switchdev_obj_port_vlan *vlan,
1033 struct switchdev_trans *trans)
a2482d2c 1034{
04bed143 1035 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1036
1037 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1038 return -EOPNOTSUPP;
1039
1040 if (vlan->vid_end > dev->num_vlans)
1041 return -ERANGE;
1042
1043 b53_enable_vlan(dev, true);
1044
1045 return 0;
1046}
3117455d 1047EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 1048
3117455d
FF		 1049void b53_vlan_add(struct dsa_switch *ds, int port,
1050 const struct switchdev_obj_port_vlan *vlan,
1051 struct switchdev_trans *trans)
a2482d2c 1052{
04bed143 1053 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1054 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1055 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
a2482d2c
FF		 1056 struct b53_vlan *vl;
1057 u16 vid;
1058
1059 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1060 vl = &dev->vlans[vid];
1061
1062 b53_get_vlan_entry(dev, vid, vl);
1063
c499696e 1064 vl->members |= BIT(port);
a2482d2c 1065 if (untagged)
e47112d9 1066 vl->untag |= BIT(port);
a2482d2c 1067 else
e47112d9 1068 vl->untag &= ~BIT(port);
a2482d2c
FF		 1069
1070 b53_set_vlan_entry(dev, vid, vl);
1071 b53_fast_age_vlan(dev, vid);
1072 }
1073
1074 if (pvid) {
1075 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1076 vlan->vid_end);
a2482d2c
FF		 1077 b53_fast_age_vlan(dev, vid);
1078 }
1079}
3117455d 1080EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1081
3117455d
FF		 1082int b53_vlan_del(struct dsa_switch *ds, int port,
1083 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1084{
04bed143 1085 struct b53_device *dev = ds->priv;
a2482d2c 1086 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1087 struct b53_vlan *vl;
1088 u16 vid;
1089 u16 pvid;
1090
1091 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1092
1093 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1094 vl = &dev->vlans[vid];
1095
1096 b53_get_vlan_entry(dev, vid, vl);
1097
1098 vl->members &= ~BIT(port);
a2482d2c
FF		 1099
1100 if (pvid == vid) {
1101 if (is5325(dev) || is5365(dev))
1102 pvid = 1;
1103 else
1104 pvid = 0;
1105 }
1106
e47112d9 1107 if (untagged)
a2482d2c 1108 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1109
1110 b53_set_vlan_entry(dev, vid, vl);
1111 b53_fast_age_vlan(dev, vid);
1112 }
1113
1114 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1115 b53_fast_age_vlan(dev, pvid);
1116
1117 return 0;
1118}
3117455d 1119EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1120
1da6df85
FF		 1121/* Address Resolution Logic routines */
1122static int b53_arl_op_wait(struct b53_device *dev)
1123{
1124 unsigned int timeout = 10;
1125 u8 reg;
1126
1127 do {
1128 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1129 if (!(reg & ARLTBL_START_DONE))
1130 return 0;
1131
1132 usleep_range(1000, 2000);
1133 } while (timeout--);
1134
1135 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1136
1137 return -ETIMEDOUT;
1138}
1139
1140static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1141{
1142 u8 reg;
1143
1144 if (op > ARLTBL_RW)
1145 return -EINVAL;
1146
1147 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1148 reg |= ARLTBL_START_DONE;
1149 if (op)
1150 reg |= ARLTBL_RW;
1151 else
1152 reg &= ~ARLTBL_RW;
1153 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1154
1155 return b53_arl_op_wait(dev);
1156}
1157
1158static int b53_arl_read(struct b53_device *dev, u64 mac,
1159 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1160 bool is_valid)
1161{
1162 unsigned int i;
1163 int ret;
1164
1165 ret = b53_arl_op_wait(dev);
1166 if (ret)
1167 return ret;
1168
1169 /* Read the bins */
1170 for (i = 0; i < dev->num_arl_entries; i++) {
1171 u64 mac_vid;
1172 u32 fwd_entry;
1173
1174 b53_read64(dev, B53_ARLIO_PAGE,
1175 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1176 b53_read32(dev, B53_ARLIO_PAGE,
1177 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1178 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1179
1180 if (!(fwd_entry & ARLTBL_VALID))
1181 continue;
1182 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1183 continue;
1184 *idx = i;
1185 }
1186
1187 return -ENOENT;
1188}
1189
1190static int b53_arl_op(struct b53_device *dev, int op, int port,
1191 const unsigned char *addr, u16 vid, bool is_valid)
1192{
1193 struct b53_arl_entry ent;
1194 u32 fwd_entry;
1195 u64 mac, mac_vid = 0;
1196 u8 idx = 0;
1197 int ret;
1198
1199 /* Convert the array into a 64-bit MAC */
4b92ea81 1200 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1201
1202 /* Perform a read for the given MAC and VID */
1203 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1204 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1205
1206 /* Issue a read operation for this MAC */
1207 ret = b53_arl_rw_op(dev, 1);
1208 if (ret)
1209 return ret;
1210
1211 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1212 /* If this is a read, just finish now */
1213 if (op)
1214 return ret;
1215
1216 /* We could not find a matching MAC, so reset to a new entry */
1217 if (ret) {
1218 fwd_entry = 0;
1219 idx = 1;
1220 }
1221
1222 memset(&ent, 0, sizeof(ent));
1223 ent.port = port;
1224 ent.is_valid = is_valid;
1225 ent.vid = vid;
1226 ent.is_static = true;
1227 memcpy(ent.mac, addr, ETH_ALEN);
1228 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1229
1230 b53_write64(dev, B53_ARLIO_PAGE,
1231 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1232 b53_write32(dev, B53_ARLIO_PAGE,
1233 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1234
1235 return b53_arl_rw_op(dev, 0);
1236}
1237
1b6dd556
AS		 1238int b53_fdb_add(struct dsa_switch *ds, int port,
1239 const unsigned char *addr, u16 vid)
1da6df85 1240{
04bed143 1241 struct b53_device *priv = ds->priv;
1da6df85
FF		 1242
1243 /* 5325 and 5365 require some more massaging, but could
1244 * be supported eventually
1245 */
1246 if (is5325(priv) || is5365(priv))
1247 return -EOPNOTSUPP;
1248
1b6dd556 1249 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1250}
3117455d 1251EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1252
3117455d 1253int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1254 const unsigned char *addr, u16 vid)
1da6df85 1255{
04bed143 1256 struct b53_device *priv = ds->priv;
1da6df85 1257
6c2c1dcb 1258 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1259}
3117455d 1260EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1261
1262static int b53_arl_search_wait(struct b53_device *dev)
1263{
1264 unsigned int timeout = 1000;
1265 u8 reg;
1266
1267 do {
1268 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1269 if (!(reg & ARL_SRCH_STDN))
1270 return 0;
1271
1272 if (reg & ARL_SRCH_VLID)
1273 return 0;
1274
1275 usleep_range(1000, 2000);
1276 } while (timeout--);
1277
1278 return -ETIMEDOUT;
1279}
1280
1281static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1282 struct b53_arl_entry *ent)
1283{
1284 u64 mac_vid;
1285 u32 fwd_entry;
1286
1287 b53_read64(dev, B53_ARLIO_PAGE,
1288 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1289 b53_read32(dev, B53_ARLIO_PAGE,
1290 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1291 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1292}
1293
e6cbef0c 1294static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1295 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1296{
1297 if (!ent->is_valid)
1298 return 0;
1299
1300 if (port != ent->port)
1301 return 0;
1302
2bedde1a 1303 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1304}
1305
3117455d 1306int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1307 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1308{
04bed143 1309 struct b53_device *priv = ds->priv;
1da6df85
FF		 1310 struct b53_arl_entry results[2];
1311 unsigned int count = 0;
1312 int ret;
1313 u8 reg;
1314
1315 /* Start search operation */
1316 reg = ARL_SRCH_STDN;
1317 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1318
1319 do {
1320 ret = b53_arl_search_wait(priv);
1321 if (ret)
1322 return ret;
1323
1324 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1325 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1326 if (ret)
1327 return ret;
1328
1329 if (priv->num_arl_entries > 2) {
1330 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1331 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1332 if (ret)
1333 return ret;
1334
1335 if (!results[0].is_valid && !results[1].is_valid)
1336 break;
1337 }
1338
1339 } while (count++ < 1024);
1340
1341 return 0;
1342}
3117455d 1343EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1344
ddd3a0c8 1345int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1346{
04bed143 1347 struct b53_device *dev = ds->priv;
0abfd494 1348 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6
FF		 1349 u16 pvlan, reg;
1350 unsigned int i;
1351
48aea33a
FF		 1352 /* Make this port leave the all VLANs join since we will have proper
1353 * VLAN entries from now on
1354 */
1355 if (is58xx(dev)) {
1356 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1357 reg &= ~BIT(port);
1358 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1359 reg &= ~BIT(cpu_port);
1360 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1361 }
1362
ff39c2d6
FF		 1363 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1364
1365 b53_for_each_port(dev, i) {
c8652c83 1366 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1367 continue;
1368
1369 /* Add this local port to the remote port VLAN control
1370 * membership and update the remote port bitmask
1371 */
1372 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1373 reg |= BIT(port);
1374 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1375 dev->ports[i].vlan_ctl_mask = reg;
1376
1377 pvlan |= BIT(i);
1378 }
1379
1380 /* Configure the local port VLAN control membership to include
1381 * remote ports and update the local port bitmask
1382 */
1383 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1384 dev->ports[port].vlan_ctl_mask = pvlan;
1385
1386 return 0;
1387}
3117455d 1388EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1389
f123f2fb 1390void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1391{
04bed143 1392 struct b53_device *dev = ds->priv;
a2482d2c 1393 struct b53_vlan *vl = &dev->vlans[0];
0abfd494 1394 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 1395 unsigned int i;
a2482d2c 1396 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1397
1398 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1399
1400 b53_for_each_port(dev, i) {
1401 /* Don't touch the remaining ports */
c8652c83 1402 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1403 continue;
1404
1405 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1406 reg &= ~BIT(port);
1407 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1408 dev->ports[port].vlan_ctl_mask = reg;
1409
1410 /* Prevent self removal to preserve isolation */
1411 if (port != i)
1412 pvlan &= ~BIT(i);
1413 }
1414
1415 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1416 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1417
1418 if (is5325(dev) || is5365(dev))
1419 pvid = 1;
1420 else
1421 pvid = 0;
1422
48aea33a
FF		 1423 /* Make this port join all VLANs without VLAN entries */
1424 if (is58xx(dev)) {
1425 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1426 reg |= BIT(port);
1427 if (!(reg & BIT(cpu_port)))
1428 reg |= BIT(cpu_port);
1429 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1430 } else {
1431 b53_get_vlan_entry(dev, pvid, vl);
c499696e
FF		 1432 vl->members |= BIT(port) | BIT(cpu_port);
1433 vl->untag |= BIT(port) | BIT(cpu_port);
48aea33a
FF		 1434 b53_set_vlan_entry(dev, pvid, vl);
1435 }
ff39c2d6 1436}
3117455d 1437EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1438
3117455d 1439void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1440{
04bed143 1441 struct b53_device *dev = ds->priv;
597698f1 1442 u8 hw_state;
ff39c2d6
FF		 1443 u8 reg;
1444
ff39c2d6
FF		 1445 switch (state) {
1446 case BR_STATE_DISABLED:
1447 hw_state = PORT_CTRL_DIS_STATE;
1448 break;
1449 case BR_STATE_LISTENING:
1450 hw_state = PORT_CTRL_LISTEN_STATE;
1451 break;
1452 case BR_STATE_LEARNING:
1453 hw_state = PORT_CTRL_LEARN_STATE;
1454 break;
1455 case BR_STATE_FORWARDING:
1456 hw_state = PORT_CTRL_FWD_STATE;
1457 break;
1458 case BR_STATE_BLOCKING:
1459 hw_state = PORT_CTRL_BLOCK_STATE;
1460 break;
1461 default:
1462 dev_err(ds->dev, "invalid STP state: %d\n", state);
1463 return;
1464 }
1465
ff39c2d6
FF		 1466 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1467 reg &= ~PORT_CTRL_STP_STATE_MASK;
1468 reg |= hw_state;
1469 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1470}
3117455d 1471EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1472
3117455d 1473void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1474{
1475 struct b53_device *dev = ds->priv;
1476
1477 if (b53_fast_age_port(dev, port))
1478 dev_err(ds->dev, "fast ageing failed\n");
1479}
3117455d 1480EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1481
5ed4e3eb 1482static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
7edc58d6 1483{
7edc58d6
FF		 1484 /* Broadcom switches will accept enabling Broadcom tags on the
1485 * following ports: 5, 7 and 8, any other port is not supported
1486 */
5ed4e3eb
FF		 1487 switch (port) {
1488 case B53_CPU_PORT_25:
1489 case 7:
1490 case B53_CPU_PORT:
1491 return true;
7edc58d6
FF		 1492 }
1493
5ed4e3eb
FF		 1494 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", port);
1495 return false;
7edc58d6
FF		 1496}
1497
5ed4e3eb
FF		 1498static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds,
1499 int port)
7b314362 1500{
7edc58d6
FF		 1501 struct b53_device *dev = ds->priv;
1502
1503 /* Older models support a different tag format that we do not
1504 * support in net/dsa/tag_brcm.c yet.
1505 */
5ed4e3eb 1506 if (is5325(dev) || is5365(dev) || !b53_can_enable_brcm_tags(ds, port))
7edc58d6
FF		 1507 return DSA_TAG_PROTO_NONE;
1508 else
1509 return DSA_TAG_PROTO_BRCM;
7b314362
AL		 1510}
1511
ed3af5fd
FF		 1512int b53_mirror_add(struct dsa_switch *ds, int port,
1513 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1514{
1515 struct b53_device *dev = ds->priv;
1516 u16 reg, loc;
1517
1518 if (ingress)
1519 loc = B53_IG_MIR_CTL;
1520 else
1521 loc = B53_EG_MIR_CTL;
1522
1523 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1524 reg &= ~MIRROR_MASK;
1525 reg |= BIT(port);
1526 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1527
1528 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1529 reg &= ~CAP_PORT_MASK;
1530 reg |= mirror->to_local_port;
1531 reg |= MIRROR_EN;
1532 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1533
1534 return 0;
1535}
1536EXPORT_SYMBOL(b53_mirror_add);
1537
1538void b53_mirror_del(struct dsa_switch *ds, int port,
1539 struct dsa_mall_mirror_tc_entry *mirror)
1540{
1541 struct b53_device *dev = ds->priv;
1542 bool loc_disable = false, other_loc_disable = false;
1543 u16 reg, loc;
1544
1545 if (mirror->ingress)
1546 loc = B53_IG_MIR_CTL;
1547 else
1548 loc = B53_EG_MIR_CTL;
1549
1550 /* Update the desired ingress/egress register */
1551 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1552 reg &= ~BIT(port);
1553 if (!(reg & MIRROR_MASK))
1554 loc_disable = true;
1555 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1556
1557 /* Now look at the other one to know if we can disable mirroring
1558 * entirely
1559 */
1560 if (mirror->ingress)
1561 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1562 else
1563 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1564 if (!(reg & MIRROR_MASK))
1565 other_loc_disable = true;
1566
1567 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1568 /* Both no longer have ports, let's disable mirroring */
1569 if (loc_disable && other_loc_disable) {
1570 reg &= ~MIRROR_EN;
1571 reg &= ~mirror->to_local_port;
1572 }
1573 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1574}
1575EXPORT_SYMBOL(b53_mirror_del);
1576
22256b0a
FF		 1577void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1578{
1579 struct b53_device *dev = ds->priv;
1580 u16 reg;
1581
1582 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1583 if (enable)
1584 reg |= BIT(port);
1585 else
1586 reg &= ~BIT(port);
1587 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1588}
1589EXPORT_SYMBOL(b53_eee_enable_set);
1590
1591
1592/* Returns 0 if EEE was not enabled, or 1 otherwise
1593 */
1594int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1595{
1596 int ret;
1597
1598 ret = phy_init_eee(phy, 0);
1599 if (ret)
1600 return 0;
1601
1602 b53_eee_enable_set(ds, port, true);
1603
1604 return 1;
1605}
1606EXPORT_SYMBOL(b53_eee_init);
1607
1608int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1609{
1610 struct b53_device *dev = ds->priv;
1611 struct ethtool_eee *p = &dev->ports[port].eee;
1612 u16 reg;
1613
1614 if (is5325(dev) || is5365(dev))
1615 return -EOPNOTSUPP;
1616
1617 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1618 e->eee_enabled = p->eee_enabled;
1619 e->eee_active = !!(reg & BIT(port));
1620
1621 return 0;
1622}
1623EXPORT_SYMBOL(b53_get_mac_eee);
1624
1625int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1626{
1627 struct b53_device *dev = ds->priv;
1628 struct ethtool_eee *p = &dev->ports[port].eee;
1629
1630 if (is5325(dev) || is5365(dev))
1631 return -EOPNOTSUPP;
1632
1633 p->eee_enabled = e->eee_enabled;
1634 b53_eee_enable_set(ds, port, e->eee_enabled);
1635
1636 return 0;
1637}
1638EXPORT_SYMBOL(b53_set_mac_eee);
1639
a82f67af 1640static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1641 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1642 .setup = b53_setup,
967dd82f
FF		 1643 .get_strings = b53_get_strings,
1644 .get_ethtool_stats = b53_get_ethtool_stats,
1645 .get_sset_count = b53_get_sset_count,
1646 .phy_read = b53_phy_read16,
1647 .phy_write = b53_phy_write16,
1648 .adjust_link = b53_adjust_link,
1649 .port_enable = b53_enable_port,
1650 .port_disable = b53_disable_port,
f43a2dbe
FF		 1651 .get_mac_eee = b53_get_mac_eee,
1652 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 1653 .port_bridge_join = b53_br_join,
1654 .port_bridge_leave = b53_br_leave,
1655 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1656 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1657 .port_vlan_filtering = b53_vlan_filtering,
1658 .port_vlan_prepare = b53_vlan_prepare,
1659 .port_vlan_add = b53_vlan_add,
1660 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 1661 .port_fdb_dump = b53_fdb_dump,
1662 .port_fdb_add = b53_fdb_add,
1663 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1664 .port_mirror_add = b53_mirror_add,
1665 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1666};
1667
1668struct b53_chip_data {
1669 u32 chip_id;
1670 const char *dev_name;
1671 u16 vlans;
1672 u16 enabled_ports;
1673 u8 cpu_port;
1674 u8 vta_regs[3];
1da6df85 1675 u8 arl_entries;
967dd82f
FF		 1676 u8 duplex_reg;
1677 u8 jumbo_pm_reg;
1678 u8 jumbo_size_reg;
1679};
1680
1681#define B53_VTA_REGS \
1682 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1683#define B53_VTA_REGS_9798 \
1684 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1685#define B53_VTA_REGS_63XX \
1686 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1687
1688static const struct b53_chip_data b53_switch_chips[] = {
1689 {
1690 .chip_id = BCM5325_DEVICE_ID,
1691 .dev_name = "BCM5325",
1692 .vlans = 16,
1693 .enabled_ports = 0x1f,
1da6df85 1694 .arl_entries = 2,
967dd82f
FF		 1695 .cpu_port = B53_CPU_PORT_25,
1696 .duplex_reg = B53_DUPLEX_STAT_FE,
1697 },
1698 {
1699 .chip_id = BCM5365_DEVICE_ID,
1700 .dev_name = "BCM5365",
1701 .vlans = 256,
1702 .enabled_ports = 0x1f,
1da6df85 1703 .arl_entries = 2,
967dd82f
FF		 1704 .cpu_port = B53_CPU_PORT_25,
1705 .duplex_reg = B53_DUPLEX_STAT_FE,
1706 },
1707 {
1708 .chip_id = BCM5395_DEVICE_ID,
1709 .dev_name = "BCM5395",
1710 .vlans = 4096,
1711 .enabled_ports = 0x1f,
1da6df85 1712 .arl_entries = 4,
967dd82f
FF		 1713 .cpu_port = B53_CPU_PORT,
1714 .vta_regs = B53_VTA_REGS,
1715 .duplex_reg = B53_DUPLEX_STAT_GE,
1716 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1717 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1718 },
1719 {
1720 .chip_id = BCM5397_DEVICE_ID,
1721 .dev_name = "BCM5397",
1722 .vlans = 4096,
1723 .enabled_ports = 0x1f,
1da6df85 1724 .arl_entries = 4,
967dd82f
FF		 1725 .cpu_port = B53_CPU_PORT,
1726 .vta_regs = B53_VTA_REGS_9798,
1727 .duplex_reg = B53_DUPLEX_STAT_GE,
1728 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1729 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1730 },
1731 {
1732 .chip_id = BCM5398_DEVICE_ID,
1733 .dev_name = "BCM5398",
1734 .vlans = 4096,
1735 .enabled_ports = 0x7f,
1da6df85 1736 .arl_entries = 4,
967dd82f
FF		 1737 .cpu_port = B53_CPU_PORT,
1738 .vta_regs = B53_VTA_REGS_9798,
1739 .duplex_reg = B53_DUPLEX_STAT_GE,
1740 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1741 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1742 },
1743 {
1744 .chip_id = BCM53115_DEVICE_ID,
1745 .dev_name = "BCM53115",
1746 .vlans = 4096,
1747 .enabled_ports = 0x1f,
1da6df85 1748 .arl_entries = 4,
967dd82f
FF		 1749 .vta_regs = B53_VTA_REGS,
1750 .cpu_port = B53_CPU_PORT,
1751 .duplex_reg = B53_DUPLEX_STAT_GE,
1752 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1753 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1754 },
1755 {
1756 .chip_id = BCM53125_DEVICE_ID,
1757 .dev_name = "BCM53125",
1758 .vlans = 4096,
1759 .enabled_ports = 0xff,
be35e8c5 1760 .arl_entries = 4,
967dd82f
FF		 1761 .cpu_port = B53_CPU_PORT,
1762 .vta_regs = B53_VTA_REGS,
1763 .duplex_reg = B53_DUPLEX_STAT_GE,
1764 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1765 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1766 },
1767 {
1768 .chip_id = BCM53128_DEVICE_ID,
1769 .dev_name = "BCM53128",
1770 .vlans = 4096,
1771 .enabled_ports = 0x1ff,
1da6df85 1772 .arl_entries = 4,
967dd82f
FF		 1773 .cpu_port = B53_CPU_PORT,
1774 .vta_regs = B53_VTA_REGS,
1775 .duplex_reg = B53_DUPLEX_STAT_GE,
1776 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1777 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1778 },
1779 {
1780 .chip_id = BCM63XX_DEVICE_ID,
1781 .dev_name = "BCM63xx",
1782 .vlans = 4096,
1783 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1784 .arl_entries = 4,
967dd82f
FF		 1785 .cpu_port = B53_CPU_PORT,
1786 .vta_regs = B53_VTA_REGS_63XX,
1787 .duplex_reg = B53_DUPLEX_STAT_63XX,
1788 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1789 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1790 },
1791 {
1792 .chip_id = BCM53010_DEVICE_ID,
1793 .dev_name = "BCM53010",
1794 .vlans = 4096,
1795 .enabled_ports = 0x1f,
1da6df85 1796 .arl_entries = 4,
967dd82f
FF		 1797 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1798 .vta_regs = B53_VTA_REGS,
1799 .duplex_reg = B53_DUPLEX_STAT_GE,
1800 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1801 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1802 },
1803 {
1804 .chip_id = BCM53011_DEVICE_ID,
1805 .dev_name = "BCM53011",
1806 .vlans = 4096,
1807 .enabled_ports = 0x1bf,
1da6df85 1808 .arl_entries = 4,
967dd82f
FF		 1809 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1810 .vta_regs = B53_VTA_REGS,
1811 .duplex_reg = B53_DUPLEX_STAT_GE,
1812 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1813 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1814 },
1815 {
1816 .chip_id = BCM53012_DEVICE_ID,
1817 .dev_name = "BCM53012",
1818 .vlans = 4096,
1819 .enabled_ports = 0x1bf,
1da6df85 1820 .arl_entries = 4,
967dd82f
FF		 1821 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1822 .vta_regs = B53_VTA_REGS,
1823 .duplex_reg = B53_DUPLEX_STAT_GE,
1824 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1825 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1826 },
1827 {
1828 .chip_id = BCM53018_DEVICE_ID,
1829 .dev_name = "BCM53018",
1830 .vlans = 4096,
1831 .enabled_ports = 0x1f,
1da6df85 1832 .arl_entries = 4,
967dd82f
FF		 1833 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1834 .vta_regs = B53_VTA_REGS,
1835 .duplex_reg = B53_DUPLEX_STAT_GE,
1836 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1837 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1838 },
1839 {
1840 .chip_id = BCM53019_DEVICE_ID,
1841 .dev_name = "BCM53019",
1842 .vlans = 4096,
1843 .enabled_ports = 0x1f,
1da6df85 1844 .arl_entries = 4,
967dd82f
FF		 1845 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1846 .vta_regs = B53_VTA_REGS,
1847 .duplex_reg = B53_DUPLEX_STAT_GE,
1848 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1849 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1850 },
991a36bb
FF		 1851 {
1852 .chip_id = BCM58XX_DEVICE_ID,
1853 .dev_name = "BCM585xx/586xx/88312",
1854 .vlans = 4096,
1855 .enabled_ports = 0x1ff,
1856 .arl_entries = 4,
bfcda65c 1857 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 1858 .vta_regs = B53_VTA_REGS,
1859 .duplex_reg = B53_DUPLEX_STAT_GE,
1860 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1861 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1862 },
130401d9
FF		 1863 {
1864 .chip_id = BCM7445_DEVICE_ID,
1865 .dev_name = "BCM7445",
1866 .vlans = 4096,
1867 .enabled_ports = 0x1ff,
1868 .arl_entries = 4,
1869 .cpu_port = B53_CPU_PORT,
1870 .vta_regs = B53_VTA_REGS,
1871 .duplex_reg = B53_DUPLEX_STAT_GE,
1872 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1873 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1874 },
0fe99338
FF		 1875 {
1876 .chip_id = BCM7278_DEVICE_ID,
1877 .dev_name = "BCM7278",
1878 .vlans = 4096,
1879 .enabled_ports = 0x1ff,
1880 .arl_entries= 4,
1881 .cpu_port = B53_CPU_PORT,
1882 .vta_regs = B53_VTA_REGS,
1883 .duplex_reg = B53_DUPLEX_STAT_GE,
1884 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1885 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1886 },
967dd82f
FF		 1887};
1888
1889static int b53_switch_init(struct b53_device *dev)
1890{
967dd82f
FF		 1891 unsigned int i;
1892 int ret;
1893
1894 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1895 const struct b53_chip_data *chip = &b53_switch_chips[i];
1896
1897 if (chip->chip_id == dev->chip_id) {
1898 if (!dev->enabled_ports)
1899 dev->enabled_ports = chip->enabled_ports;
1900 dev->name = chip->dev_name;
1901 dev->duplex_reg = chip->duplex_reg;
1902 dev->vta_regs[0] = chip->vta_regs[0];
1903 dev->vta_regs[1] = chip->vta_regs[1];
1904 dev->vta_regs[2] = chip->vta_regs[2];
1905 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1906 dev->cpu_port = chip->cpu_port;
1907 dev->num_vlans = chip->vlans;
1da6df85 1908 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1909 break;
1910 }
1911 }
1912
1913 /* check which BCM5325x version we have */
1914 if (is5325(dev)) {
1915 u8 vc4;
1916
1917 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1918
1919 /* check reserved bits */
1920 switch (vc4 & 3) {
1921 case 1:
1922 /* BCM5325E */
1923 break;
1924 case 3:
1925 /* BCM5325F - do not use port 4 */
1926 dev->enabled_ports &= ~BIT(4);
1927 break;
1928 default:
1929/* On the BCM47XX SoCs this is the supported internal switch.*/
1930#ifndef CONFIG_BCM47XX
1931 /* BCM5325M */
1932 return -EINVAL;
1933#else
1934 break;
1935#endif
1936 }
1937 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1938 u64 strap_value;
1939
1940 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1941 /* use second IMP port if GMII is enabled */
1942 if (strap_value & SV_GMII_CTRL_115)
1943 dev->cpu_port = 5;
1944 }
1945
1946 /* cpu port is always last */
1947 dev->num_ports = dev->cpu_port + 1;
1948 dev->enabled_ports |= BIT(dev->cpu_port);
1949
1950 dev->ports = devm_kzalloc(dev->dev,
1951 sizeof(struct b53_port) * dev->num_ports,
1952 GFP_KERNEL);
1953 if (!dev->ports)
1954 return -ENOMEM;
1955
a2482d2c
FF		 1956 dev->vlans = devm_kzalloc(dev->dev,
1957 sizeof(struct b53_vlan) * dev->num_vlans,
1958 GFP_KERNEL);
1959 if (!dev->vlans)
1960 return -ENOMEM;
1961
967dd82f
FF		 1962 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1963 if (dev->reset_gpio >= 0) {
1964 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1965 GPIOF_OUT_INIT_HIGH, "robo_reset");
1966 if (ret)
1967 return ret;
1968 }
1969
1970 return 0;
1971}
1972
0dff88d3
JL		 1973struct b53_device *b53_switch_alloc(struct device *base,
1974 const struct b53_io_ops *ops,
967dd82f
FF		 1975 void *priv)
1976{
1977 struct dsa_switch *ds;
1978 struct b53_device *dev;
1979
a0c02161 1980 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 1981 if (!ds)
1982 return NULL;
1983
a0c02161
VD		 1984 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1985 if (!dev)
1986 return NULL;
967dd82f
FF		 1987
1988 ds->priv = dev;
967dd82f
FF		 1989 dev->dev = base;
1990
1991 dev->ds = ds;
1992 dev->priv = priv;
1993 dev->ops = ops;
485ebd61 1994 ds->ops = &b53_switch_ops;
967dd82f
FF		 1995 mutex_init(&dev->reg_mutex);
1996 mutex_init(&dev->stats_mutex);
1997
1998 return dev;
1999}
2000EXPORT_SYMBOL(b53_switch_alloc);
2001
2002int b53_switch_detect(struct b53_device *dev)
2003{
2004 u32 id32;
2005 u16 tmp;
2006 u8 id8;
2007 int ret;
2008
2009 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2010 if (ret)
2011 return ret;
2012
2013 switch (id8) {
2014 case 0:
2015 /* BCM5325 and BCM5365 do not have this register so reads
2016 * return 0. But the read operation did succeed, so assume this
2017 * is one of them.
2018 *
2019 * Next check if we can write to the 5325's VTA register; for
2020 * 5365 it is read only.
2021 */
2022 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2023 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2024
2025 if (tmp == 0xf)
2026 dev->chip_id = BCM5325_DEVICE_ID;
2027 else
2028 dev->chip_id = BCM5365_DEVICE_ID;
2029 break;
2030 case BCM5395_DEVICE_ID:
2031 case BCM5397_DEVICE_ID:
2032 case BCM5398_DEVICE_ID:
2033 dev->chip_id = id8;
2034 break;
2035 default:
2036 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2037 if (ret)
2038 return ret;
2039
2040 switch (id32) {
2041 case BCM53115_DEVICE_ID:
2042 case BCM53125_DEVICE_ID:
2043 case BCM53128_DEVICE_ID:
2044 case BCM53010_DEVICE_ID:
2045 case BCM53011_DEVICE_ID:
2046 case BCM53012_DEVICE_ID:
2047 case BCM53018_DEVICE_ID:
2048 case BCM53019_DEVICE_ID:
2049 dev->chip_id = id32;
2050 break;
2051 default:
2052 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2053 id8, id32);
2054 return -ENODEV;
2055 }
2056 }
2057
2058 if (dev->chip_id == BCM5325_DEVICE_ID)
2059 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2060 &dev->core_rev);
2061 else
2062 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2063 &dev->core_rev);
2064}
2065EXPORT_SYMBOL(b53_switch_detect);
2066
2067int b53_switch_register(struct b53_device *dev)
2068{
2069 int ret;
2070
2071 if (dev->pdata) {
2072 dev->chip_id = dev->pdata->chip_id;
2073 dev->enabled_ports = dev->pdata->enabled_ports;
2074 }
2075
2076 if (!dev->chip_id && b53_switch_detect(dev))
2077 return -EINVAL;
2078
2079 ret = b53_switch_init(dev);
2080 if (ret)
2081 return ret;
2082
2083 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2084
23c9ee49 2085 return dsa_register_switch(dev->ds);
967dd82f
FF		 2086}
2087EXPORT_SYMBOL(b53_switch_register);
2088
2089MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2090MODULE_DESCRIPTION("B53 switch library");
2091MODULE_LICENSE("Dual BSD/GPL");
ubuntu-bionic-kernel mirror