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net: dsa: add port fast ageing
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f 31#include <net/dsa.h>
1da6df85 32#include <net/switchdev.h>
967dd82f
FF		 33
34#include "b53_regs.h"
35#include "b53_priv.h"
36
37struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41};
42
43/* BCM5365 MIB counters */
44static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77};
78
79#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80
81/* BCM63xx MIB counters */
82static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125};
126
127#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
128
129/* MIB counters */
130static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
166};
167
168#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169
bde5d132
FF		 170static const struct b53_mib_desc b53_mibs_58xx[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
225};
226
227#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228
967dd82f
FF		 229static int b53_do_vlan_op(struct b53_device *dev, u8 op)
230{
231 unsigned int i;
232
233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234
235 for (i = 0; i < 10; i++) {
236 u8 vta;
237
238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
239 if (!(vta & VTA_START_CMD))
240 return 0;
241
242 usleep_range(100, 200);
243 }
244
245 return -EIO;
246}
247
a2482d2c
FF		 248static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
249 struct b53_vlan *vlan)
967dd82f
FF		 250{
251 if (is5325(dev)) {
252 u32 entry = 0;
253
a2482d2c
FF		 254 if (vlan->members) {
255 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
256 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 257 if (dev->core_rev >= 3)
258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 else
260 entry |= VA_VALID_25;
261 }
262
263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
265 VTA_RW_STATE_WR | VTA_RW_OP_EN);
266 } else if (is5365(dev)) {
267 u16 entry = 0;
268
a2482d2c
FF		 269 if (vlan->members)
270 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 272
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
275 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 } else {
277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 279 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 280
281 b53_do_vlan_op(dev, VTA_CMD_WRITE);
282 }
a2482d2c
FF		 283
284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid, vlan->members, vlan->untag);
286}
287
288static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
289 struct b53_vlan *vlan)
290{
291 if (is5325(dev)) {
292 u32 entry = 0;
293
294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
295 VTA_RW_STATE_RD | VTA_RW_OP_EN);
296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297
298 if (dev->core_rev >= 3)
299 vlan->valid = !!(entry & VA_VALID_25_R4);
300 else
301 vlan->valid = !!(entry & VA_VALID_25);
302 vlan->members = entry & VA_MEMBER_MASK;
303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304
305 } else if (is5365(dev)) {
306 u16 entry = 0;
307
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
309 VTA_RW_STATE_WR | VTA_RW_OP_EN);
310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311
312 vlan->valid = !!(entry & VA_VALID_65);
313 vlan->members = entry & VA_MEMBER_MASK;
314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
315 } else {
316 u32 entry = 0;
317
318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
319 b53_do_vlan_op(dev, VTA_CMD_READ);
320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
321 vlan->members = entry & VTE_MEMBERS;
322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
323 vlan->valid = true;
324 }
967dd82f
FF		 325}
326
a2482d2c 327static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f
FF		 328{
329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
339}
340
a2482d2c 341static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 342{
343 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
344
345 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
346 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
347 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
348
349 if (is5325(dev) || is5365(dev)) {
350 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
352 } else if (is63xx(dev)) {
353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
354 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
355 } else {
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
358 }
359
360 mgmt &= ~SM_SW_FWD_MODE;
361
362 if (enable) {
363 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
364 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
365 vc4 &= ~VC4_ING_VID_CHECK_MASK;
366 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
367 vc5 |= VC5_DROP_VTABLE_MISS;
368
369 if (is5325(dev))
370 vc0 &= ~VC0_RESERVED_1;
371
372 if (is5325(dev) || is5365(dev))
373 vc1 |= VC1_RX_MCST_TAG_EN;
374
967dd82f
FF		 375 } else {
376 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
377 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
378 vc4 &= ~VC4_ING_VID_CHECK_MASK;
379 vc5 &= ~VC5_DROP_VTABLE_MISS;
380
381 if (is5325(dev) || is5365(dev))
382 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
383 else
384 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
385
386 if (is5325(dev) || is5365(dev))
387 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 388 }
389
a2482d2c
FF		 390 if (!is5325(dev) && !is5365(dev))
391 vc5 &= ~VC5_VID_FFF_EN;
392
967dd82f
FF		 393 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
394 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
395
396 if (is5325(dev) || is5365(dev)) {
397 /* enable the high 8 bit vid check on 5325 */
398 if (is5325(dev) && enable)
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
400 VC3_HIGH_8BIT_EN);
401 else
402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
403
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
406 } else if (is63xx(dev)) {
407 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
410 } else {
411 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
414 }
415
416 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
417}
418
419static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
420{
421 u32 port_mask = 0;
422 u16 max_size = JMS_MIN_SIZE;
423
424 if (is5325(dev) || is5365(dev))
425 return -EINVAL;
426
427 if (enable) {
428 port_mask = dev->enabled_ports;
429 max_size = JMS_MAX_SIZE;
430 if (allow_10_100)
431 port_mask |= JPM_10_100_JUMBO_EN;
432 }
433
434 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
435 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
436}
437
ff39c2d6 438static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 439{
440 unsigned int i;
441
442 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 443 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 444
445 for (i = 0; i < 10; i++) {
446 u8 fast_age_ctrl;
447
448 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
449 &fast_age_ctrl);
450
451 if (!(fast_age_ctrl & FAST_AGE_DONE))
452 goto out;
453
454 msleep(1);
455 }
456
457 return -ETIMEDOUT;
458out:
459 /* Only age dynamic entries (default behavior) */
460 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
461 return 0;
462}
463
ff39c2d6
FF		 464static int b53_fast_age_port(struct b53_device *dev, int port)
465{
466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
467
468 return b53_flush_arl(dev, FAST_AGE_PORT);
469}
470
a2482d2c
FF		 471static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
472{
473 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
474
475 return b53_flush_arl(dev, FAST_AGE_VLAN);
476}
477
ff39c2d6
FF		 478static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
479{
04bed143 480 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 481 unsigned int i;
482 u16 pvlan;
483
484 /* Enable the IMP port to be in the same VLAN as the other ports
485 * on a per-port basis such that we only have Port i and IMP in
486 * the same VLAN.
487 */
488 b53_for_each_port(dev, i) {
489 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
490 pvlan |= BIT(cpu_port);
491 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
492 }
493}
494
967dd82f
FF		 495static int b53_enable_port(struct dsa_switch *ds, int port,
496 struct phy_device *phy)
497{
04bed143 498 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 499 unsigned int cpu_port = dev->cpu_port;
500 u16 pvlan;
967dd82f
FF		 501
502 /* Clear the Rx and Tx disable bits and set to no spanning tree */
503 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
504
ff39c2d6
FF		 505 /* Set this port, and only this one to be in the default VLAN,
506 * if member of a bridge, restore its membership prior to
507 * bringing down this port.
508 */
509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
510 pvlan &= ~0x1ff;
511 pvlan |= BIT(port);
512 pvlan |= dev->ports[port].vlan_ctl_mask;
513 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
514
515 b53_imp_vlan_setup(ds, cpu_port);
516
967dd82f
FF		 517 return 0;
518}
519
520static void b53_disable_port(struct dsa_switch *ds, int port,
521 struct phy_device *phy)
522{
04bed143 523 struct b53_device *dev = ds->priv;
967dd82f
FF		 524 u8 reg;
525
526 /* Disable Tx/Rx for the port */
527 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
528 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
529 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
530}
531
532static void b53_enable_cpu_port(struct b53_device *dev)
533{
534 unsigned int cpu_port = dev->cpu_port;
535 u8 port_ctrl;
536
537 /* BCM5325 CPU port is at 8 */
538 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
539 cpu_port = B53_CPU_PORT;
540
541 port_ctrl = PORT_CTRL_RX_BCST_EN |
542 PORT_CTRL_RX_MCST_EN |
543 PORT_CTRL_RX_UCST_EN;
544 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
545}
546
547static void b53_enable_mib(struct b53_device *dev)
548{
549 u8 gc;
550
551 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
552 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
553 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
554}
555
556static int b53_configure_vlan(struct b53_device *dev)
557{
a2482d2c 558 struct b53_vlan vl = { 0 };
967dd82f
FF		 559 int i;
560
561 /* clear all vlan entries */
562 if (is5325(dev) || is5365(dev)) {
563 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 564 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 565 } else {
566 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
567 }
568
569 b53_enable_vlan(dev, false);
570
571 b53_for_each_port(dev, i)
572 b53_write16(dev, B53_VLAN_PAGE,
573 B53_VLAN_PORT_DEF_TAG(i), 1);
574
575 if (!is5325(dev) && !is5365(dev))
576 b53_set_jumbo(dev, dev->enable_jumbo, false);
577
578 return 0;
579}
580
581static void b53_switch_reset_gpio(struct b53_device *dev)
582{
583 int gpio = dev->reset_gpio;
584
585 if (gpio < 0)
586 return;
587
588 /* Reset sequence: RESET low(50ms)->high(20ms)
589 */
590 gpio_set_value(gpio, 0);
591 mdelay(50);
592
593 gpio_set_value(gpio, 1);
594 mdelay(20);
595
596 dev->current_page = 0xff;
597}
598
599static int b53_switch_reset(struct b53_device *dev)
600{
601 u8 mgmt;
602
603 b53_switch_reset_gpio(dev);
604
605 if (is539x(dev)) {
606 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
607 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
608 }
609
610 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
611
612 if (!(mgmt & SM_SW_FWD_EN)) {
613 mgmt &= ~SM_SW_FWD_MODE;
614 mgmt |= SM_SW_FWD_EN;
615
616 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
617 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
618
619 if (!(mgmt & SM_SW_FWD_EN)) {
620 dev_err(dev->dev, "Failed to enable switch!\n");
621 return -EINVAL;
622 }
623 }
624
625 b53_enable_mib(dev);
626
ff39c2d6 627 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 628}
629
630static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
631{
04bed143 632 struct b53_device *priv = ds->priv;
967dd82f
FF		 633 u16 value = 0;
634 int ret;
635
636 if (priv->ops->phy_read16)
637 ret = priv->ops->phy_read16(priv, addr, reg, &value);
638 else
639 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
640 reg * 2, &value);
641
642 return ret ? ret : value;
643}
644
645static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
646{
04bed143 647 struct b53_device *priv = ds->priv;
967dd82f
FF		 648
649 if (priv->ops->phy_write16)
650 return priv->ops->phy_write16(priv, addr, reg, val);
651
652 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
653}
654
655static int b53_reset_switch(struct b53_device *priv)
656{
657 /* reset vlans */
658 priv->enable_jumbo = false;
659
a2482d2c 660 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 661 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
662
663 return b53_switch_reset(priv);
664}
665
666static int b53_apply_config(struct b53_device *priv)
667{
668 /* disable switching */
669 b53_set_forwarding(priv, 0);
670
671 b53_configure_vlan(priv);
672
673 /* enable switching */
674 b53_set_forwarding(priv, 1);
675
676 return 0;
677}
678
679static void b53_reset_mib(struct b53_device *priv)
680{
681 u8 gc;
682
683 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
684
685 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
686 msleep(1);
687 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
688 msleep(1);
689}
690
691static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
692{
693 if (is5365(dev))
694 return b53_mibs_65;
695 else if (is63xx(dev))
696 return b53_mibs_63xx;
bde5d132
FF		 697 else if (is58xx(dev))
698 return b53_mibs_58xx;
967dd82f
FF		 699 else
700 return b53_mibs;
701}
702
703static unsigned int b53_get_mib_size(struct b53_device *dev)
704{
705 if (is5365(dev))
706 return B53_MIBS_65_SIZE;
707 else if (is63xx(dev))
708 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 709 else if (is58xx(dev))
710 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 711 else
712 return B53_MIBS_SIZE;
713}
714
715static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
716{
04bed143 717 struct b53_device *dev = ds->priv;
967dd82f
FF		 718 const struct b53_mib_desc *mibs = b53_get_mib(dev);
719 unsigned int mib_size = b53_get_mib_size(dev);
720 unsigned int i;
721
722 for (i = 0; i < mib_size; i++)
723 memcpy(data + i * ETH_GSTRING_LEN,
724 mibs[i].name, ETH_GSTRING_LEN);
725}
726
727static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
728 uint64_t *data)
729{
04bed143 730 struct b53_device *dev = ds->priv;
967dd82f
FF		 731 const struct b53_mib_desc *mibs = b53_get_mib(dev);
732 unsigned int mib_size = b53_get_mib_size(dev);
733 const struct b53_mib_desc *s;
734 unsigned int i;
735 u64 val = 0;
736
737 if (is5365(dev) && port == 5)
738 port = 8;
739
740 mutex_lock(&dev->stats_mutex);
741
742 for (i = 0; i < mib_size; i++) {
743 s = &mibs[i];
744
51dca8a1 745 if (s->size == 8) {
967dd82f
FF		 746 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
747 } else {
748 u32 val32;
749
750 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
751 &val32);
752 val = val32;
753 }
754 data[i] = (u64)val;
755 }
756
757 mutex_unlock(&dev->stats_mutex);
758}
759
760static int b53_get_sset_count(struct dsa_switch *ds)
761{
04bed143 762 struct b53_device *dev = ds->priv;
967dd82f
FF		 763
764 return b53_get_mib_size(dev);
765}
766
967dd82f
FF		 767static int b53_setup(struct dsa_switch *ds)
768{
04bed143 769 struct b53_device *dev = ds->priv;
967dd82f
FF		 770 unsigned int port;
771 int ret;
772
773 ret = b53_reset_switch(dev);
774 if (ret) {
775 dev_err(ds->dev, "failed to reset switch\n");
776 return ret;
777 }
778
779 b53_reset_mib(dev);
780
781 ret = b53_apply_config(dev);
782 if (ret)
783 dev_err(ds->dev, "failed to apply configuration\n");
784
785 for (port = 0; port < dev->num_ports; port++) {
786 if (BIT(port) & ds->enabled_port_mask)
787 b53_enable_port(ds, port, NULL);
788 else if (dsa_is_cpu_port(ds, port))
789 b53_enable_cpu_port(dev);
790 else
791 b53_disable_port(ds, port, NULL);
792 }
793
794 return ret;
795}
796
797static void b53_adjust_link(struct dsa_switch *ds, int port,
798 struct phy_device *phydev)
799{
04bed143 800 struct b53_device *dev = ds->priv;
967dd82f
FF		 801 u8 rgmii_ctrl = 0, reg = 0, off;
802
803 if (!phy_is_pseudo_fixed_link(phydev))
804 return;
805
806 /* Override the port settings */
807 if (port == dev->cpu_port) {
808 off = B53_PORT_OVERRIDE_CTRL;
809 reg = PORT_OVERRIDE_EN;
810 } else {
811 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
812 reg = GMII_PO_EN;
813 }
814
815 /* Set the link UP */
816 if (phydev->link)
817 reg |= PORT_OVERRIDE_LINK;
818
819 if (phydev->duplex == DUPLEX_FULL)
820 reg |= PORT_OVERRIDE_FULL_DUPLEX;
821
822 switch (phydev->speed) {
823 case 2000:
824 reg |= PORT_OVERRIDE_SPEED_2000M;
825 /* fallthrough */
826 case SPEED_1000:
827 reg |= PORT_OVERRIDE_SPEED_1000M;
828 break;
829 case SPEED_100:
830 reg |= PORT_OVERRIDE_SPEED_100M;
831 break;
832 case SPEED_10:
833 reg |= PORT_OVERRIDE_SPEED_10M;
834 break;
835 default:
836 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
837 return;
838 }
839
840 /* Enable flow control on BCM5301x's CPU port */
841 if (is5301x(dev) && port == dev->cpu_port)
842 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
843
844 if (phydev->pause) {
845 if (phydev->asym_pause)
846 reg |= PORT_OVERRIDE_TX_FLOW;
847 reg |= PORT_OVERRIDE_RX_FLOW;
848 }
849
850 b53_write8(dev, B53_CTRL_PAGE, off, reg);
851
852 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
853 if (port == 8)
854 off = B53_RGMII_CTRL_IMP;
855 else
856 off = B53_RGMII_CTRL_P(port);
857
858 /* Configure the port RGMII clock delay by DLL disabled and
859 * tx_clk aligned timing (restoring to reset defaults)
860 */
861 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
862 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
863 RGMII_CTRL_TIMING_SEL);
864
865 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
866 * sure that we enable the port TX clock internal delay to
867 * account for this internal delay that is inserted, otherwise
868 * the switch won't be able to receive correctly.
869 *
870 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
871 * any delay neither on transmission nor reception, so the
872 * BCM53125 must also be configured accordingly to account for
873 * the lack of delay and introduce
874 *
875 * The BCM53125 switch has its RX clock and TX clock control
876 * swapped, hence the reason why we modify the TX clock path in
877 * the "RGMII" case
878 */
879 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
880 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
881 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
882 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
883 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
884 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
885
886 dev_info(ds->dev, "Configured port %d for %s\n", port,
887 phy_modes(phydev->interface));
888 }
889
890 /* configure MII port if necessary */
891 if (is5325(dev)) {
892 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
893 &reg);
894
895 /* reverse mii needs to be enabled */
896 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
897 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
898 reg | PORT_OVERRIDE_RV_MII_25);
899 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
900 &reg);
901
902 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
903 dev_err(ds->dev,
904 "Failed to enable reverse MII mode\n");
905 return;
906 }
907 }
908 } else if (is5301x(dev)) {
909 if (port != dev->cpu_port) {
910 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
911 u8 gmii_po;
912
913 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
914 gmii_po |= GMII_PO_LINK |
915 GMII_PO_RX_FLOW |
916 GMII_PO_TX_FLOW |
917 GMII_PO_EN |
918 GMII_PO_SPEED_2000M;
919 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
920 }
921 }
922}
923
a2482d2c
FF		 924static int b53_vlan_filtering(struct dsa_switch *ds, int port,
925 bool vlan_filtering)
926{
927 return 0;
928}
929
930static int b53_vlan_prepare(struct dsa_switch *ds, int port,
931 const struct switchdev_obj_port_vlan *vlan,
932 struct switchdev_trans *trans)
933{
04bed143 934 struct b53_device *dev = ds->priv;
a2482d2c
FF		 935
936 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
937 return -EOPNOTSUPP;
938
939 if (vlan->vid_end > dev->num_vlans)
940 return -ERANGE;
941
942 b53_enable_vlan(dev, true);
943
944 return 0;
945}
946
947static void b53_vlan_add(struct dsa_switch *ds, int port,
948 const struct switchdev_obj_port_vlan *vlan,
949 struct switchdev_trans *trans)
950{
04bed143 951 struct b53_device *dev = ds->priv;
a2482d2c
FF		 952 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
953 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
954 unsigned int cpu_port = dev->cpu_port;
955 struct b53_vlan *vl;
956 u16 vid;
957
958 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
959 vl = &dev->vlans[vid];
960
961 b53_get_vlan_entry(dev, vid, vl);
962
963 vl->members |= BIT(port) | BIT(cpu_port);
964 if (untagged)
965 vl->untag |= BIT(port) | BIT(cpu_port);
966 else
967 vl->untag &= ~(BIT(port) | BIT(cpu_port));
968
969 b53_set_vlan_entry(dev, vid, vl);
970 b53_fast_age_vlan(dev, vid);
971 }
972
973 if (pvid) {
974 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
975 vlan->vid_end);
976 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port),
977 vlan->vid_end);
978 b53_fast_age_vlan(dev, vid);
979 }
980}
981
982static int b53_vlan_del(struct dsa_switch *ds, int port,
983 const struct switchdev_obj_port_vlan *vlan)
984{
04bed143 985 struct b53_device *dev = ds->priv;
a2482d2c
FF		 986 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
987 unsigned int cpu_port = dev->cpu_port;
988 struct b53_vlan *vl;
989 u16 vid;
990 u16 pvid;
991
992 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
993
994 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
995 vl = &dev->vlans[vid];
996
997 b53_get_vlan_entry(dev, vid, vl);
998
999 vl->members &= ~BIT(port);
1000 if ((vl->members & BIT(cpu_port)) == BIT(cpu_port))
1001 vl->members = 0;
1002
1003 if (pvid == vid) {
1004 if (is5325(dev) || is5365(dev))
1005 pvid = 1;
1006 else
1007 pvid = 0;
1008 }
1009
1010 if (untagged) {
1011 vl->untag &= ~(BIT(port));
1012 if ((vl->untag & BIT(cpu_port)) == BIT(cpu_port))
1013 vl->untag = 0;
1014 }
1015
1016 b53_set_vlan_entry(dev, vid, vl);
1017 b53_fast_age_vlan(dev, vid);
1018 }
1019
1020 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1021 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), pvid);
1022 b53_fast_age_vlan(dev, pvid);
1023
1024 return 0;
1025}
1026
1027static int b53_vlan_dump(struct dsa_switch *ds, int port,
1028 struct switchdev_obj_port_vlan *vlan,
1029 int (*cb)(struct switchdev_obj *obj))
1030{
04bed143 1031 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1032 u16 vid, vid_start = 0, pvid;
1033 struct b53_vlan *vl;
1034 int err = 0;
1035
1036 if (is5325(dev) || is5365(dev))
1037 vid_start = 1;
1038
1039 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1040
1041 /* Use our software cache for dumps, since we do not have any HW
1042 * operation returning only the used/valid VLANs
1043 */
1044 for (vid = vid_start; vid < dev->num_vlans; vid++) {
1045 vl = &dev->vlans[vid];
1046
1047 if (!vl->valid)
1048 continue;
1049
1050 if (!(vl->members & BIT(port)))
1051 continue;
1052
1053 vlan->vid_begin = vlan->vid_end = vid;
1054 vlan->flags = 0;
1055
1056 if (vl->untag & BIT(port))
1057 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1058 if (pvid == vid)
1059 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1060
1061 err = cb(&vlan->obj);
1062 if (err)
1063 break;
1064 }
1065
1066 return err;
1067}
1068
1da6df85
FF		 1069/* Address Resolution Logic routines */
1070static int b53_arl_op_wait(struct b53_device *dev)
1071{
1072 unsigned int timeout = 10;
1073 u8 reg;
1074
1075 do {
1076 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1077 if (!(reg & ARLTBL_START_DONE))
1078 return 0;
1079
1080 usleep_range(1000, 2000);
1081 } while (timeout--);
1082
1083 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1084
1085 return -ETIMEDOUT;
1086}
1087
1088static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1089{
1090 u8 reg;
1091
1092 if (op > ARLTBL_RW)
1093 return -EINVAL;
1094
1095 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1096 reg |= ARLTBL_START_DONE;
1097 if (op)
1098 reg |= ARLTBL_RW;
1099 else
1100 reg &= ~ARLTBL_RW;
1101 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1102
1103 return b53_arl_op_wait(dev);
1104}
1105
1106static int b53_arl_read(struct b53_device *dev, u64 mac,
1107 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1108 bool is_valid)
1109{
1110 unsigned int i;
1111 int ret;
1112
1113 ret = b53_arl_op_wait(dev);
1114 if (ret)
1115 return ret;
1116
1117 /* Read the bins */
1118 for (i = 0; i < dev->num_arl_entries; i++) {
1119 u64 mac_vid;
1120 u32 fwd_entry;
1121
1122 b53_read64(dev, B53_ARLIO_PAGE,
1123 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1124 b53_read32(dev, B53_ARLIO_PAGE,
1125 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1126 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1127
1128 if (!(fwd_entry & ARLTBL_VALID))
1129 continue;
1130 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1131 continue;
1132 *idx = i;
1133 }
1134
1135 return -ENOENT;
1136}
1137
1138static int b53_arl_op(struct b53_device *dev, int op, int port,
1139 const unsigned char *addr, u16 vid, bool is_valid)
1140{
1141 struct b53_arl_entry ent;
1142 u32 fwd_entry;
1143 u64 mac, mac_vid = 0;
1144 u8 idx = 0;
1145 int ret;
1146
1147 /* Convert the array into a 64-bit MAC */
1148 mac = b53_mac_to_u64(addr);
1149
1150 /* Perform a read for the given MAC and VID */
1151 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1152 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1153
1154 /* Issue a read operation for this MAC */
1155 ret = b53_arl_rw_op(dev, 1);
1156 if (ret)
1157 return ret;
1158
1159 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1160 /* If this is a read, just finish now */
1161 if (op)
1162 return ret;
1163
1164 /* We could not find a matching MAC, so reset to a new entry */
1165 if (ret) {
1166 fwd_entry = 0;
1167 idx = 1;
1168 }
1169
1170 memset(&ent, 0, sizeof(ent));
1171 ent.port = port;
1172 ent.is_valid = is_valid;
1173 ent.vid = vid;
1174 ent.is_static = true;
1175 memcpy(ent.mac, addr, ETH_ALEN);
1176 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1177
1178 b53_write64(dev, B53_ARLIO_PAGE,
1179 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1180 b53_write32(dev, B53_ARLIO_PAGE,
1181 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1182
1183 return b53_arl_rw_op(dev, 0);
1184}
1185
1186static int b53_fdb_prepare(struct dsa_switch *ds, int port,
1187 const struct switchdev_obj_port_fdb *fdb,
1188 struct switchdev_trans *trans)
1189{
04bed143 1190 struct b53_device *priv = ds->priv;
1da6df85
FF		 1191
1192 /* 5325 and 5365 require some more massaging, but could
1193 * be supported eventually
1194 */
1195 if (is5325(priv) || is5365(priv))
1196 return -EOPNOTSUPP;
1197
1198 return 0;
1199}
1200
1201static void b53_fdb_add(struct dsa_switch *ds, int port,
1202 const struct switchdev_obj_port_fdb *fdb,
1203 struct switchdev_trans *trans)
1204{
04bed143 1205 struct b53_device *priv = ds->priv;
1da6df85
FF		 1206
1207 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1208 pr_err("%s: failed to add MAC address\n", __func__);
1209}
1210
1211static int b53_fdb_del(struct dsa_switch *ds, int port,
1212 const struct switchdev_obj_port_fdb *fdb)
1213{
04bed143 1214 struct b53_device *priv = ds->priv;
1da6df85
FF		 1215
1216 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1217}
1218
1219static int b53_arl_search_wait(struct b53_device *dev)
1220{
1221 unsigned int timeout = 1000;
1222 u8 reg;
1223
1224 do {
1225 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1226 if (!(reg & ARL_SRCH_STDN))
1227 return 0;
1228
1229 if (reg & ARL_SRCH_VLID)
1230 return 0;
1231
1232 usleep_range(1000, 2000);
1233 } while (timeout--);
1234
1235 return -ETIMEDOUT;
1236}
1237
1238static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1239 struct b53_arl_entry *ent)
1240{
1241 u64 mac_vid;
1242 u32 fwd_entry;
1243
1244 b53_read64(dev, B53_ARLIO_PAGE,
1245 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1246 b53_read32(dev, B53_ARLIO_PAGE,
1247 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1248 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1249}
1250
1251static int b53_fdb_copy(struct net_device *dev, int port,
1252 const struct b53_arl_entry *ent,
1253 struct switchdev_obj_port_fdb *fdb,
1254 int (*cb)(struct switchdev_obj *obj))
1255{
1256 if (!ent->is_valid)
1257 return 0;
1258
1259 if (port != ent->port)
1260 return 0;
1261
1262 ether_addr_copy(fdb->addr, ent->mac);
1263 fdb->vid = ent->vid;
1264 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1265
1266 return cb(&fdb->obj);
1267}
1268
1269static int b53_fdb_dump(struct dsa_switch *ds, int port,
1270 struct switchdev_obj_port_fdb *fdb,
1271 int (*cb)(struct switchdev_obj *obj))
1272{
04bed143 1273 struct b53_device *priv = ds->priv;
1da6df85
FF		 1274 struct net_device *dev = ds->ports[port].netdev;
1275 struct b53_arl_entry results[2];
1276 unsigned int count = 0;
1277 int ret;
1278 u8 reg;
1279
1280 /* Start search operation */
1281 reg = ARL_SRCH_STDN;
1282 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1283
1284 do {
1285 ret = b53_arl_search_wait(priv);
1286 if (ret)
1287 return ret;
1288
1289 b53_arl_search_rd(priv, 0, &results[0]);
1290 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1291 if (ret)
1292 return ret;
1293
1294 if (priv->num_arl_entries > 2) {
1295 b53_arl_search_rd(priv, 1, &results[1]);
1296 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1297 if (ret)
1298 return ret;
1299
1300 if (!results[0].is_valid && !results[1].is_valid)
1301 break;
1302 }
1303
1304 } while (count++ < 1024);
1305
1306 return 0;
1307}
1308
ff39c2d6
FF		 1309static int b53_br_join(struct dsa_switch *ds, int port,
1310 struct net_device *bridge)
1311{
04bed143 1312 struct b53_device *dev = ds->priv;
48aea33a 1313 s8 cpu_port = ds->dst->cpu_port;
ff39c2d6
FF		 1314 u16 pvlan, reg;
1315 unsigned int i;
1316
48aea33a
FF		 1317 /* Make this port leave the all VLANs join since we will have proper
1318 * VLAN entries from now on
1319 */
1320 if (is58xx(dev)) {
1321 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1322 reg &= ~BIT(port);
1323 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1324 reg &= ~BIT(cpu_port);
1325 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1326 }
1327
ff39c2d6
FF		 1328 dev->ports[port].bridge_dev = bridge;
1329 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1330
1331 b53_for_each_port(dev, i) {
1332 if (dev->ports[i].bridge_dev != bridge)
1333 continue;
1334
1335 /* Add this local port to the remote port VLAN control
1336 * membership and update the remote port bitmask
1337 */
1338 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1339 reg |= BIT(port);
1340 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1341 dev->ports[i].vlan_ctl_mask = reg;
1342
1343 pvlan |= BIT(i);
1344 }
1345
1346 /* Configure the local port VLAN control membership to include
1347 * remote ports and update the local port bitmask
1348 */
1349 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1350 dev->ports[port].vlan_ctl_mask = pvlan;
1351
1352 return 0;
1353}
1354
1355static void b53_br_leave(struct dsa_switch *ds, int port)
1356{
04bed143 1357 struct b53_device *dev = ds->priv;
ff39c2d6 1358 struct net_device *bridge = dev->ports[port].bridge_dev;
a2482d2c 1359 struct b53_vlan *vl = &dev->vlans[0];
48aea33a 1360 s8 cpu_port = ds->dst->cpu_port;
ff39c2d6 1361 unsigned int i;
a2482d2c 1362 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1363
1364 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1365
1366 b53_for_each_port(dev, i) {
1367 /* Don't touch the remaining ports */
1368 if (dev->ports[i].bridge_dev != bridge)
1369 continue;
1370
1371 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1372 reg &= ~BIT(port);
1373 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1374 dev->ports[port].vlan_ctl_mask = reg;
1375
1376 /* Prevent self removal to preserve isolation */
1377 if (port != i)
1378 pvlan &= ~BIT(i);
1379 }
1380
1381 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1382 dev->ports[port].vlan_ctl_mask = pvlan;
1383 dev->ports[port].bridge_dev = NULL;
a2482d2c
FF		 1384
1385 if (is5325(dev) || is5365(dev))
1386 pvid = 1;
1387 else
1388 pvid = 0;
1389
48aea33a
FF		 1390 /* Make this port join all VLANs without VLAN entries */
1391 if (is58xx(dev)) {
1392 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1393 reg |= BIT(port);
1394 if (!(reg & BIT(cpu_port)))
1395 reg |= BIT(cpu_port);
1396 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1397 } else {
1398 b53_get_vlan_entry(dev, pvid, vl);
1399 vl->members |= BIT(port) | BIT(dev->cpu_port);
1400 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1401 b53_set_vlan_entry(dev, pvid, vl);
1402 }
ff39c2d6
FF		 1403}
1404
1405static void b53_br_set_stp_state(struct dsa_switch *ds, int port,
1406 u8 state)
1407{
04bed143 1408 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 1409 u8 hw_state, cur_hw_state;
1410 u8 reg;
1411
1412 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1413 cur_hw_state = reg & PORT_CTRL_STP_STATE_MASK;
1414
1415 switch (state) {
1416 case BR_STATE_DISABLED:
1417 hw_state = PORT_CTRL_DIS_STATE;
1418 break;
1419 case BR_STATE_LISTENING:
1420 hw_state = PORT_CTRL_LISTEN_STATE;
1421 break;
1422 case BR_STATE_LEARNING:
1423 hw_state = PORT_CTRL_LEARN_STATE;
1424 break;
1425 case BR_STATE_FORWARDING:
1426 hw_state = PORT_CTRL_FWD_STATE;
1427 break;
1428 case BR_STATE_BLOCKING:
1429 hw_state = PORT_CTRL_BLOCK_STATE;
1430 break;
1431 default:
1432 dev_err(ds->dev, "invalid STP state: %d\n", state);
1433 return;
1434 }
1435
1436 /* Fast-age ARL entries if we are moving a port from Learning or
1437 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
1438 * state (hw_state)
1439 */
1440 if (cur_hw_state != hw_state) {
1441 if (cur_hw_state >= PORT_CTRL_LEARN_STATE &&
1442 hw_state <= PORT_CTRL_LISTEN_STATE) {
1443 if (b53_fast_age_port(dev, port)) {
1444 dev_err(ds->dev, "fast ageing failed\n");
1445 return;
1446 }
1447 }
1448 }
1449
1450 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1451 reg &= ~PORT_CTRL_STP_STATE_MASK;
1452 reg |= hw_state;
1453 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1454}
1455
7b314362
AL		 1456static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1457{
1458 return DSA_TAG_PROTO_NONE;
1459}
1460
9d490b4e 1461static struct dsa_switch_ops b53_switch_ops = {
7b314362 1462 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1463 .setup = b53_setup,
967dd82f
FF		 1464 .get_strings = b53_get_strings,
1465 .get_ethtool_stats = b53_get_ethtool_stats,
1466 .get_sset_count = b53_get_sset_count,
1467 .phy_read = b53_phy_read16,
1468 .phy_write = b53_phy_write16,
1469 .adjust_link = b53_adjust_link,
1470 .port_enable = b53_enable_port,
1471 .port_disable = b53_disable_port,
ff39c2d6
FF		 1472 .port_bridge_join = b53_br_join,
1473 .port_bridge_leave = b53_br_leave,
1474 .port_stp_state_set = b53_br_set_stp_state,
a2482d2c
FF		 1475 .port_vlan_filtering = b53_vlan_filtering,
1476 .port_vlan_prepare = b53_vlan_prepare,
1477 .port_vlan_add = b53_vlan_add,
1478 .port_vlan_del = b53_vlan_del,
1479 .port_vlan_dump = b53_vlan_dump,
1da6df85
FF		 1480 .port_fdb_prepare = b53_fdb_prepare,
1481 .port_fdb_dump = b53_fdb_dump,
1482 .port_fdb_add = b53_fdb_add,
1483 .port_fdb_del = b53_fdb_del,
967dd82f
FF		 1484};
1485
1486struct b53_chip_data {
1487 u32 chip_id;
1488 const char *dev_name;
1489 u16 vlans;
1490 u16 enabled_ports;
1491 u8 cpu_port;
1492 u8 vta_regs[3];
1da6df85 1493 u8 arl_entries;
967dd82f
FF		 1494 u8 duplex_reg;
1495 u8 jumbo_pm_reg;
1496 u8 jumbo_size_reg;
1497};
1498
1499#define B53_VTA_REGS \
1500 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1501#define B53_VTA_REGS_9798 \
1502 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1503#define B53_VTA_REGS_63XX \
1504 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1505
1506static const struct b53_chip_data b53_switch_chips[] = {
1507 {
1508 .chip_id = BCM5325_DEVICE_ID,
1509 .dev_name = "BCM5325",
1510 .vlans = 16,
1511 .enabled_ports = 0x1f,
1da6df85 1512 .arl_entries = 2,
967dd82f
FF		 1513 .cpu_port = B53_CPU_PORT_25,
1514 .duplex_reg = B53_DUPLEX_STAT_FE,
1515 },
1516 {
1517 .chip_id = BCM5365_DEVICE_ID,
1518 .dev_name = "BCM5365",
1519 .vlans = 256,
1520 .enabled_ports = 0x1f,
1da6df85 1521 .arl_entries = 2,
967dd82f
FF		 1522 .cpu_port = B53_CPU_PORT_25,
1523 .duplex_reg = B53_DUPLEX_STAT_FE,
1524 },
1525 {
1526 .chip_id = BCM5395_DEVICE_ID,
1527 .dev_name = "BCM5395",
1528 .vlans = 4096,
1529 .enabled_ports = 0x1f,
1da6df85 1530 .arl_entries = 4,
967dd82f
FF		 1531 .cpu_port = B53_CPU_PORT,
1532 .vta_regs = B53_VTA_REGS,
1533 .duplex_reg = B53_DUPLEX_STAT_GE,
1534 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1535 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1536 },
1537 {
1538 .chip_id = BCM5397_DEVICE_ID,
1539 .dev_name = "BCM5397",
1540 .vlans = 4096,
1541 .enabled_ports = 0x1f,
1da6df85 1542 .arl_entries = 4,
967dd82f
FF		 1543 .cpu_port = B53_CPU_PORT,
1544 .vta_regs = B53_VTA_REGS_9798,
1545 .duplex_reg = B53_DUPLEX_STAT_GE,
1546 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1547 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1548 },
1549 {
1550 .chip_id = BCM5398_DEVICE_ID,
1551 .dev_name = "BCM5398",
1552 .vlans = 4096,
1553 .enabled_ports = 0x7f,
1da6df85 1554 .arl_entries = 4,
967dd82f
FF		 1555 .cpu_port = B53_CPU_PORT,
1556 .vta_regs = B53_VTA_REGS_9798,
1557 .duplex_reg = B53_DUPLEX_STAT_GE,
1558 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1559 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1560 },
1561 {
1562 .chip_id = BCM53115_DEVICE_ID,
1563 .dev_name = "BCM53115",
1564 .vlans = 4096,
1565 .enabled_ports = 0x1f,
1da6df85 1566 .arl_entries = 4,
967dd82f
FF		 1567 .vta_regs = B53_VTA_REGS,
1568 .cpu_port = B53_CPU_PORT,
1569 .duplex_reg = B53_DUPLEX_STAT_GE,
1570 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1571 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1572 },
1573 {
1574 .chip_id = BCM53125_DEVICE_ID,
1575 .dev_name = "BCM53125",
1576 .vlans = 4096,
1577 .enabled_ports = 0xff,
1578 .cpu_port = B53_CPU_PORT,
1579 .vta_regs = B53_VTA_REGS,
1580 .duplex_reg = B53_DUPLEX_STAT_GE,
1581 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1582 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1583 },
1584 {
1585 .chip_id = BCM53128_DEVICE_ID,
1586 .dev_name = "BCM53128",
1587 .vlans = 4096,
1588 .enabled_ports = 0x1ff,
1da6df85 1589 .arl_entries = 4,
967dd82f
FF		 1590 .cpu_port = B53_CPU_PORT,
1591 .vta_regs = B53_VTA_REGS,
1592 .duplex_reg = B53_DUPLEX_STAT_GE,
1593 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1594 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1595 },
1596 {
1597 .chip_id = BCM63XX_DEVICE_ID,
1598 .dev_name = "BCM63xx",
1599 .vlans = 4096,
1600 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1601 .arl_entries = 4,
967dd82f
FF		 1602 .cpu_port = B53_CPU_PORT,
1603 .vta_regs = B53_VTA_REGS_63XX,
1604 .duplex_reg = B53_DUPLEX_STAT_63XX,
1605 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1606 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1607 },
1608 {
1609 .chip_id = BCM53010_DEVICE_ID,
1610 .dev_name = "BCM53010",
1611 .vlans = 4096,
1612 .enabled_ports = 0x1f,
1da6df85 1613 .arl_entries = 4,
967dd82f
FF		 1614 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1615 .vta_regs = B53_VTA_REGS,
1616 .duplex_reg = B53_DUPLEX_STAT_GE,
1617 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1618 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1619 },
1620 {
1621 .chip_id = BCM53011_DEVICE_ID,
1622 .dev_name = "BCM53011",
1623 .vlans = 4096,
1624 .enabled_ports = 0x1bf,
1da6df85 1625 .arl_entries = 4,
967dd82f
FF		 1626 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1627 .vta_regs = B53_VTA_REGS,
1628 .duplex_reg = B53_DUPLEX_STAT_GE,
1629 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1630 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1631 },
1632 {
1633 .chip_id = BCM53012_DEVICE_ID,
1634 .dev_name = "BCM53012",
1635 .vlans = 4096,
1636 .enabled_ports = 0x1bf,
1da6df85 1637 .arl_entries = 4,
967dd82f
FF		 1638 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1639 .vta_regs = B53_VTA_REGS,
1640 .duplex_reg = B53_DUPLEX_STAT_GE,
1641 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1642 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1643 },
1644 {
1645 .chip_id = BCM53018_DEVICE_ID,
1646 .dev_name = "BCM53018",
1647 .vlans = 4096,
1648 .enabled_ports = 0x1f,
1da6df85 1649 .arl_entries = 4,
967dd82f
FF		 1650 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1651 .vta_regs = B53_VTA_REGS,
1652 .duplex_reg = B53_DUPLEX_STAT_GE,
1653 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1654 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1655 },
1656 {
1657 .chip_id = BCM53019_DEVICE_ID,
1658 .dev_name = "BCM53019",
1659 .vlans = 4096,
1660 .enabled_ports = 0x1f,
1da6df85 1661 .arl_entries = 4,
967dd82f
FF		 1662 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1663 .vta_regs = B53_VTA_REGS,
1664 .duplex_reg = B53_DUPLEX_STAT_GE,
1665 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1666 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1667 },
991a36bb
FF		 1668 {
1669 .chip_id = BCM58XX_DEVICE_ID,
1670 .dev_name = "BCM585xx/586xx/88312",
1671 .vlans = 4096,
1672 .enabled_ports = 0x1ff,
1673 .arl_entries = 4,
1674 .cpu_port = B53_CPU_PORT_25,
1675 .vta_regs = B53_VTA_REGS,
1676 .duplex_reg = B53_DUPLEX_STAT_GE,
1677 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1678 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1679 },
130401d9
FF		 1680 {
1681 .chip_id = BCM7445_DEVICE_ID,
1682 .dev_name = "BCM7445",
1683 .vlans = 4096,
1684 .enabled_ports = 0x1ff,
1685 .arl_entries = 4,
1686 .cpu_port = B53_CPU_PORT,
1687 .vta_regs = B53_VTA_REGS,
1688 .duplex_reg = B53_DUPLEX_STAT_GE,
1689 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1690 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1691 },
967dd82f
FF		 1692};
1693
1694static int b53_switch_init(struct b53_device *dev)
1695{
967dd82f
FF		 1696 unsigned int i;
1697 int ret;
1698
1699 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1700 const struct b53_chip_data *chip = &b53_switch_chips[i];
1701
1702 if (chip->chip_id == dev->chip_id) {
1703 if (!dev->enabled_ports)
1704 dev->enabled_ports = chip->enabled_ports;
1705 dev->name = chip->dev_name;
1706 dev->duplex_reg = chip->duplex_reg;
1707 dev->vta_regs[0] = chip->vta_regs[0];
1708 dev->vta_regs[1] = chip->vta_regs[1];
1709 dev->vta_regs[2] = chip->vta_regs[2];
1710 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1711 dev->cpu_port = chip->cpu_port;
1712 dev->num_vlans = chip->vlans;
1da6df85 1713 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1714 break;
1715 }
1716 }
1717
1718 /* check which BCM5325x version we have */
1719 if (is5325(dev)) {
1720 u8 vc4;
1721
1722 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1723
1724 /* check reserved bits */
1725 switch (vc4 & 3) {
1726 case 1:
1727 /* BCM5325E */
1728 break;
1729 case 3:
1730 /* BCM5325F - do not use port 4 */
1731 dev->enabled_ports &= ~BIT(4);
1732 break;
1733 default:
1734/* On the BCM47XX SoCs this is the supported internal switch.*/
1735#ifndef CONFIG_BCM47XX
1736 /* BCM5325M */
1737 return -EINVAL;
1738#else
1739 break;
1740#endif
1741 }
1742 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1743 u64 strap_value;
1744
1745 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1746 /* use second IMP port if GMII is enabled */
1747 if (strap_value & SV_GMII_CTRL_115)
1748 dev->cpu_port = 5;
1749 }
1750
1751 /* cpu port is always last */
1752 dev->num_ports = dev->cpu_port + 1;
1753 dev->enabled_ports |= BIT(dev->cpu_port);
1754
1755 dev->ports = devm_kzalloc(dev->dev,
1756 sizeof(struct b53_port) * dev->num_ports,
1757 GFP_KERNEL);
1758 if (!dev->ports)
1759 return -ENOMEM;
1760
a2482d2c
FF		 1761 dev->vlans = devm_kzalloc(dev->dev,
1762 sizeof(struct b53_vlan) * dev->num_vlans,
1763 GFP_KERNEL);
1764 if (!dev->vlans)
1765 return -ENOMEM;
1766
967dd82f
FF		 1767 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1768 if (dev->reset_gpio >= 0) {
1769 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1770 GPIOF_OUT_INIT_HIGH, "robo_reset");
1771 if (ret)
1772 return ret;
1773 }
1774
1775 return 0;
1776}
1777
0dff88d3
JL		 1778struct b53_device *b53_switch_alloc(struct device *base,
1779 const struct b53_io_ops *ops,
967dd82f
FF		 1780 void *priv)
1781{
1782 struct dsa_switch *ds;
1783 struct b53_device *dev;
1784
1785 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1786 if (!ds)
1787 return NULL;
1788
1789 dev = (struct b53_device *)(ds + 1);
1790
1791 ds->priv = dev;
1792 ds->dev = base;
1793 dev->dev = base;
1794
1795 dev->ds = ds;
1796 dev->priv = priv;
1797 dev->ops = ops;
485ebd61 1798 ds->ops = &b53_switch_ops;
967dd82f
FF		 1799 mutex_init(&dev->reg_mutex);
1800 mutex_init(&dev->stats_mutex);
1801
1802 return dev;
1803}
1804EXPORT_SYMBOL(b53_switch_alloc);
1805
1806int b53_switch_detect(struct b53_device *dev)
1807{
1808 u32 id32;
1809 u16 tmp;
1810 u8 id8;
1811 int ret;
1812
1813 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1814 if (ret)
1815 return ret;
1816
1817 switch (id8) {
1818 case 0:
1819 /* BCM5325 and BCM5365 do not have this register so reads
1820 * return 0. But the read operation did succeed, so assume this
1821 * is one of them.
1822 *
1823 * Next check if we can write to the 5325's VTA register; for
1824 * 5365 it is read only.
1825 */
1826 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1827 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1828
1829 if (tmp == 0xf)
1830 dev->chip_id = BCM5325_DEVICE_ID;
1831 else
1832 dev->chip_id = BCM5365_DEVICE_ID;
1833 break;
1834 case BCM5395_DEVICE_ID:
1835 case BCM5397_DEVICE_ID:
1836 case BCM5398_DEVICE_ID:
1837 dev->chip_id = id8;
1838 break;
1839 default:
1840 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1841 if (ret)
1842 return ret;
1843
1844 switch (id32) {
1845 case BCM53115_DEVICE_ID:
1846 case BCM53125_DEVICE_ID:
1847 case BCM53128_DEVICE_ID:
1848 case BCM53010_DEVICE_ID:
1849 case BCM53011_DEVICE_ID:
1850 case BCM53012_DEVICE_ID:
1851 case BCM53018_DEVICE_ID:
1852 case BCM53019_DEVICE_ID:
1853 dev->chip_id = id32;
1854 break;
1855 default:
1856 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1857 id8, id32);
1858 return -ENODEV;
1859 }
1860 }
1861
1862 if (dev->chip_id == BCM5325_DEVICE_ID)
1863 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1864 &dev->core_rev);
1865 else
1866 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1867 &dev->core_rev);
1868}
1869EXPORT_SYMBOL(b53_switch_detect);
1870
1871int b53_switch_register(struct b53_device *dev)
1872{
1873 int ret;
1874
1875 if (dev->pdata) {
1876 dev->chip_id = dev->pdata->chip_id;
1877 dev->enabled_ports = dev->pdata->enabled_ports;
1878 }
1879
1880 if (!dev->chip_id && b53_switch_detect(dev))
1881 return -EINVAL;
1882
1883 ret = b53_switch_init(dev);
1884 if (ret)
1885 return ret;
1886
1887 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1888
1889 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1890}
1891EXPORT_SYMBOL(b53_switch_register);
1892
1893MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1894MODULE_DESCRIPTION("B53 switch library");
1895MODULE_LICENSE("Dual BSD/GPL");
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