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1 | /* |
2 | * B53 switch driver main logic | |
3 | * | |
4 | * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> | |
5 | * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> | |
6 | * | |
7 | * Permission to use, copy, modify, and/or distribute this software for any | |
8 | * purpose with or without fee is hereby granted, provided that the above | |
9 | * copyright notice and this permission notice appear in all copies. | |
10 | * | |
11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
18 | */ | |
19 | ||
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
21 | ||
22 | #include <linux/delay.h> | |
23 | #include <linux/export.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/platform_data/b53.h> | |
28 | #include <linux/phy.h> | |
29 | #include <net/dsa.h> | |
30 | ||
31 | #include "b53_regs.h" | |
32 | #include "b53_priv.h" | |
33 | ||
34 | struct b53_mib_desc { | |
35 | u8 size; | |
36 | u8 offset; | |
37 | const char *name; | |
38 | }; | |
39 | ||
40 | /* BCM5365 MIB counters */ | |
41 | static const struct b53_mib_desc b53_mibs_65[] = { | |
42 | { 8, 0x00, "TxOctets" }, | |
43 | { 4, 0x08, "TxDropPkts" }, | |
44 | { 4, 0x10, "TxBroadcastPkts" }, | |
45 | { 4, 0x14, "TxMulticastPkts" }, | |
46 | { 4, 0x18, "TxUnicastPkts" }, | |
47 | { 4, 0x1c, "TxCollisions" }, | |
48 | { 4, 0x20, "TxSingleCollision" }, | |
49 | { 4, 0x24, "TxMultipleCollision" }, | |
50 | { 4, 0x28, "TxDeferredTransmit" }, | |
51 | { 4, 0x2c, "TxLateCollision" }, | |
52 | { 4, 0x30, "TxExcessiveCollision" }, | |
53 | { 4, 0x38, "TxPausePkts" }, | |
54 | { 8, 0x44, "RxOctets" }, | |
55 | { 4, 0x4c, "RxUndersizePkts" }, | |
56 | { 4, 0x50, "RxPausePkts" }, | |
57 | { 4, 0x54, "Pkts64Octets" }, | |
58 | { 4, 0x58, "Pkts65to127Octets" }, | |
59 | { 4, 0x5c, "Pkts128to255Octets" }, | |
60 | { 4, 0x60, "Pkts256to511Octets" }, | |
61 | { 4, 0x64, "Pkts512to1023Octets" }, | |
62 | { 4, 0x68, "Pkts1024to1522Octets" }, | |
63 | { 4, 0x6c, "RxOversizePkts" }, | |
64 | { 4, 0x70, "RxJabbers" }, | |
65 | { 4, 0x74, "RxAlignmentErrors" }, | |
66 | { 4, 0x78, "RxFCSErrors" }, | |
67 | { 8, 0x7c, "RxGoodOctets" }, | |
68 | { 4, 0x84, "RxDropPkts" }, | |
69 | { 4, 0x88, "RxUnicastPkts" }, | |
70 | { 4, 0x8c, "RxMulticastPkts" }, | |
71 | { 4, 0x90, "RxBroadcastPkts" }, | |
72 | { 4, 0x94, "RxSAChanges" }, | |
73 | { 4, 0x98, "RxFragments" }, | |
74 | }; | |
75 | ||
76 | #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) | |
77 | ||
78 | /* BCM63xx MIB counters */ | |
79 | static const struct b53_mib_desc b53_mibs_63xx[] = { | |
80 | { 8, 0x00, "TxOctets" }, | |
81 | { 4, 0x08, "TxDropPkts" }, | |
82 | { 4, 0x0c, "TxQoSPkts" }, | |
83 | { 4, 0x10, "TxBroadcastPkts" }, | |
84 | { 4, 0x14, "TxMulticastPkts" }, | |
85 | { 4, 0x18, "TxUnicastPkts" }, | |
86 | { 4, 0x1c, "TxCollisions" }, | |
87 | { 4, 0x20, "TxSingleCollision" }, | |
88 | { 4, 0x24, "TxMultipleCollision" }, | |
89 | { 4, 0x28, "TxDeferredTransmit" }, | |
90 | { 4, 0x2c, "TxLateCollision" }, | |
91 | { 4, 0x30, "TxExcessiveCollision" }, | |
92 | { 4, 0x38, "TxPausePkts" }, | |
93 | { 8, 0x3c, "TxQoSOctets" }, | |
94 | { 8, 0x44, "RxOctets" }, | |
95 | { 4, 0x4c, "RxUndersizePkts" }, | |
96 | { 4, 0x50, "RxPausePkts" }, | |
97 | { 4, 0x54, "Pkts64Octets" }, | |
98 | { 4, 0x58, "Pkts65to127Octets" }, | |
99 | { 4, 0x5c, "Pkts128to255Octets" }, | |
100 | { 4, 0x60, "Pkts256to511Octets" }, | |
101 | { 4, 0x64, "Pkts512to1023Octets" }, | |
102 | { 4, 0x68, "Pkts1024to1522Octets" }, | |
103 | { 4, 0x6c, "RxOversizePkts" }, | |
104 | { 4, 0x70, "RxJabbers" }, | |
105 | { 4, 0x74, "RxAlignmentErrors" }, | |
106 | { 4, 0x78, "RxFCSErrors" }, | |
107 | { 8, 0x7c, "RxGoodOctets" }, | |
108 | { 4, 0x84, "RxDropPkts" }, | |
109 | { 4, 0x88, "RxUnicastPkts" }, | |
110 | { 4, 0x8c, "RxMulticastPkts" }, | |
111 | { 4, 0x90, "RxBroadcastPkts" }, | |
112 | { 4, 0x94, "RxSAChanges" }, | |
113 | { 4, 0x98, "RxFragments" }, | |
114 | { 4, 0xa0, "RxSymbolErrors" }, | |
115 | { 4, 0xa4, "RxQoSPkts" }, | |
116 | { 8, 0xa8, "RxQoSOctets" }, | |
117 | { 4, 0xb0, "Pkts1523to2047Octets" }, | |
118 | { 4, 0xb4, "Pkts2048to4095Octets" }, | |
119 | { 4, 0xb8, "Pkts4096to8191Octets" }, | |
120 | { 4, 0xbc, "Pkts8192to9728Octets" }, | |
121 | { 4, 0xc0, "RxDiscarded" }, | |
122 | }; | |
123 | ||
124 | #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) | |
125 | ||
126 | /* MIB counters */ | |
127 | static const struct b53_mib_desc b53_mibs[] = { | |
128 | { 8, 0x00, "TxOctets" }, | |
129 | { 4, 0x08, "TxDropPkts" }, | |
130 | { 4, 0x10, "TxBroadcastPkts" }, | |
131 | { 4, 0x14, "TxMulticastPkts" }, | |
132 | { 4, 0x18, "TxUnicastPkts" }, | |
133 | { 4, 0x1c, "TxCollisions" }, | |
134 | { 4, 0x20, "TxSingleCollision" }, | |
135 | { 4, 0x24, "TxMultipleCollision" }, | |
136 | { 4, 0x28, "TxDeferredTransmit" }, | |
137 | { 4, 0x2c, "TxLateCollision" }, | |
138 | { 4, 0x30, "TxExcessiveCollision" }, | |
139 | { 4, 0x38, "TxPausePkts" }, | |
140 | { 8, 0x50, "RxOctets" }, | |
141 | { 4, 0x58, "RxUndersizePkts" }, | |
142 | { 4, 0x5c, "RxPausePkts" }, | |
143 | { 4, 0x60, "Pkts64Octets" }, | |
144 | { 4, 0x64, "Pkts65to127Octets" }, | |
145 | { 4, 0x68, "Pkts128to255Octets" }, | |
146 | { 4, 0x6c, "Pkts256to511Octets" }, | |
147 | { 4, 0x70, "Pkts512to1023Octets" }, | |
148 | { 4, 0x74, "Pkts1024to1522Octets" }, | |
149 | { 4, 0x78, "RxOversizePkts" }, | |
150 | { 4, 0x7c, "RxJabbers" }, | |
151 | { 4, 0x80, "RxAlignmentErrors" }, | |
152 | { 4, 0x84, "RxFCSErrors" }, | |
153 | { 8, 0x88, "RxGoodOctets" }, | |
154 | { 4, 0x90, "RxDropPkts" }, | |
155 | { 4, 0x94, "RxUnicastPkts" }, | |
156 | { 4, 0x98, "RxMulticastPkts" }, | |
157 | { 4, 0x9c, "RxBroadcastPkts" }, | |
158 | { 4, 0xa0, "RxSAChanges" }, | |
159 | { 4, 0xa4, "RxFragments" }, | |
160 | { 4, 0xa8, "RxJumboPkts" }, | |
161 | { 4, 0xac, "RxSymbolErrors" }, | |
162 | { 4, 0xc0, "RxDiscarded" }, | |
163 | }; | |
164 | ||
165 | #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) | |
166 | ||
167 | static int b53_do_vlan_op(struct b53_device *dev, u8 op) | |
168 | { | |
169 | unsigned int i; | |
170 | ||
171 | b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); | |
172 | ||
173 | for (i = 0; i < 10; i++) { | |
174 | u8 vta; | |
175 | ||
176 | b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); | |
177 | if (!(vta & VTA_START_CMD)) | |
178 | return 0; | |
179 | ||
180 | usleep_range(100, 200); | |
181 | } | |
182 | ||
183 | return -EIO; | |
184 | } | |
185 | ||
186 | static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members, | |
187 | u16 untag) | |
188 | { | |
189 | if (is5325(dev)) { | |
190 | u32 entry = 0; | |
191 | ||
192 | if (members) { | |
193 | entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) | | |
194 | members; | |
195 | if (dev->core_rev >= 3) | |
196 | entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; | |
197 | else | |
198 | entry |= VA_VALID_25; | |
199 | } | |
200 | ||
201 | b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); | |
202 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | | |
203 | VTA_RW_STATE_WR | VTA_RW_OP_EN); | |
204 | } else if (is5365(dev)) { | |
205 | u16 entry = 0; | |
206 | ||
207 | if (members) | |
208 | entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) | | |
209 | members | VA_VALID_65; | |
210 | ||
211 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); | |
212 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | | |
213 | VTA_RW_STATE_WR | VTA_RW_OP_EN); | |
214 | } else { | |
215 | b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); | |
216 | b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], | |
217 | (untag << VTE_UNTAG_S) | members); | |
218 | ||
219 | b53_do_vlan_op(dev, VTA_CMD_WRITE); | |
220 | } | |
221 | } | |
222 | ||
223 | void b53_set_forwarding(struct b53_device *dev, int enable) | |
224 | { | |
225 | u8 mgmt; | |
226 | ||
227 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
228 | ||
229 | if (enable) | |
230 | mgmt |= SM_SW_FWD_EN; | |
231 | else | |
232 | mgmt &= ~SM_SW_FWD_EN; | |
233 | ||
234 | b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); | |
235 | } | |
236 | ||
237 | static void b53_enable_vlan(struct b53_device *dev, int enable) | |
238 | { | |
239 | u8 mgmt, vc0, vc1, vc4 = 0, vc5; | |
240 | ||
241 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
242 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); | |
243 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); | |
244 | ||
245 | if (is5325(dev) || is5365(dev)) { | |
246 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); | |
247 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); | |
248 | } else if (is63xx(dev)) { | |
249 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); | |
250 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); | |
251 | } else { | |
252 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); | |
253 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); | |
254 | } | |
255 | ||
256 | mgmt &= ~SM_SW_FWD_MODE; | |
257 | ||
258 | if (enable) { | |
259 | vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; | |
260 | vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; | |
261 | vc4 &= ~VC4_ING_VID_CHECK_MASK; | |
262 | vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; | |
263 | vc5 |= VC5_DROP_VTABLE_MISS; | |
264 | ||
265 | if (is5325(dev)) | |
266 | vc0 &= ~VC0_RESERVED_1; | |
267 | ||
268 | if (is5325(dev) || is5365(dev)) | |
269 | vc1 |= VC1_RX_MCST_TAG_EN; | |
270 | ||
271 | if (!is5325(dev) && !is5365(dev)) { | |
272 | if (dev->allow_vid_4095) | |
273 | vc5 |= VC5_VID_FFF_EN; | |
274 | else | |
275 | vc5 &= ~VC5_VID_FFF_EN; | |
276 | } | |
277 | } else { | |
278 | vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); | |
279 | vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); | |
280 | vc4 &= ~VC4_ING_VID_CHECK_MASK; | |
281 | vc5 &= ~VC5_DROP_VTABLE_MISS; | |
282 | ||
283 | if (is5325(dev) || is5365(dev)) | |
284 | vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; | |
285 | else | |
286 | vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; | |
287 | ||
288 | if (is5325(dev) || is5365(dev)) | |
289 | vc1 &= ~VC1_RX_MCST_TAG_EN; | |
290 | ||
291 | if (!is5325(dev) && !is5365(dev)) | |
292 | vc5 &= ~VC5_VID_FFF_EN; | |
293 | } | |
294 | ||
295 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); | |
296 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); | |
297 | ||
298 | if (is5325(dev) || is5365(dev)) { | |
299 | /* enable the high 8 bit vid check on 5325 */ | |
300 | if (is5325(dev) && enable) | |
301 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, | |
302 | VC3_HIGH_8BIT_EN); | |
303 | else | |
304 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); | |
305 | ||
306 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); | |
307 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); | |
308 | } else if (is63xx(dev)) { | |
309 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); | |
310 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); | |
311 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); | |
312 | } else { | |
313 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); | |
314 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); | |
315 | b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); | |
316 | } | |
317 | ||
318 | b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); | |
319 | } | |
320 | ||
321 | static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) | |
322 | { | |
323 | u32 port_mask = 0; | |
324 | u16 max_size = JMS_MIN_SIZE; | |
325 | ||
326 | if (is5325(dev) || is5365(dev)) | |
327 | return -EINVAL; | |
328 | ||
329 | if (enable) { | |
330 | port_mask = dev->enabled_ports; | |
331 | max_size = JMS_MAX_SIZE; | |
332 | if (allow_10_100) | |
333 | port_mask |= JPM_10_100_JUMBO_EN; | |
334 | } | |
335 | ||
336 | b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); | |
337 | return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); | |
338 | } | |
339 | ||
340 | static int b53_flush_arl(struct b53_device *dev) | |
341 | { | |
342 | unsigned int i; | |
343 | ||
344 | b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, | |
345 | FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC); | |
346 | ||
347 | for (i = 0; i < 10; i++) { | |
348 | u8 fast_age_ctrl; | |
349 | ||
350 | b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, | |
351 | &fast_age_ctrl); | |
352 | ||
353 | if (!(fast_age_ctrl & FAST_AGE_DONE)) | |
354 | goto out; | |
355 | ||
356 | msleep(1); | |
357 | } | |
358 | ||
359 | return -ETIMEDOUT; | |
360 | out: | |
361 | /* Only age dynamic entries (default behavior) */ | |
362 | b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); | |
363 | return 0; | |
364 | } | |
365 | ||
366 | static int b53_enable_port(struct dsa_switch *ds, int port, | |
367 | struct phy_device *phy) | |
368 | { | |
369 | struct b53_device *dev = ds_to_priv(ds); | |
370 | ||
371 | /* Clear the Rx and Tx disable bits and set to no spanning tree */ | |
372 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static void b53_disable_port(struct dsa_switch *ds, int port, | |
378 | struct phy_device *phy) | |
379 | { | |
380 | struct b53_device *dev = ds_to_priv(ds); | |
381 | u8 reg; | |
382 | ||
383 | /* Disable Tx/Rx for the port */ | |
384 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); | |
385 | reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; | |
386 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); | |
387 | } | |
388 | ||
389 | static void b53_enable_cpu_port(struct b53_device *dev) | |
390 | { | |
391 | unsigned int cpu_port = dev->cpu_port; | |
392 | u8 port_ctrl; | |
393 | ||
394 | /* BCM5325 CPU port is at 8 */ | |
395 | if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25) | |
396 | cpu_port = B53_CPU_PORT; | |
397 | ||
398 | port_ctrl = PORT_CTRL_RX_BCST_EN | | |
399 | PORT_CTRL_RX_MCST_EN | | |
400 | PORT_CTRL_RX_UCST_EN; | |
401 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl); | |
402 | } | |
403 | ||
404 | static void b53_enable_mib(struct b53_device *dev) | |
405 | { | |
406 | u8 gc; | |
407 | ||
408 | b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); | |
409 | gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); | |
410 | b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); | |
411 | } | |
412 | ||
413 | static int b53_configure_vlan(struct b53_device *dev) | |
414 | { | |
415 | int i; | |
416 | ||
417 | /* clear all vlan entries */ | |
418 | if (is5325(dev) || is5365(dev)) { | |
419 | for (i = 1; i < dev->num_vlans; i++) | |
420 | b53_set_vlan_entry(dev, i, 0, 0); | |
421 | } else { | |
422 | b53_do_vlan_op(dev, VTA_CMD_CLEAR); | |
423 | } | |
424 | ||
425 | b53_enable_vlan(dev, false); | |
426 | ||
427 | b53_for_each_port(dev, i) | |
428 | b53_write16(dev, B53_VLAN_PAGE, | |
429 | B53_VLAN_PORT_DEF_TAG(i), 1); | |
430 | ||
431 | if (!is5325(dev) && !is5365(dev)) | |
432 | b53_set_jumbo(dev, dev->enable_jumbo, false); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static void b53_switch_reset_gpio(struct b53_device *dev) | |
438 | { | |
439 | int gpio = dev->reset_gpio; | |
440 | ||
441 | if (gpio < 0) | |
442 | return; | |
443 | ||
444 | /* Reset sequence: RESET low(50ms)->high(20ms) | |
445 | */ | |
446 | gpio_set_value(gpio, 0); | |
447 | mdelay(50); | |
448 | ||
449 | gpio_set_value(gpio, 1); | |
450 | mdelay(20); | |
451 | ||
452 | dev->current_page = 0xff; | |
453 | } | |
454 | ||
455 | static int b53_switch_reset(struct b53_device *dev) | |
456 | { | |
457 | u8 mgmt; | |
458 | ||
459 | b53_switch_reset_gpio(dev); | |
460 | ||
461 | if (is539x(dev)) { | |
462 | b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); | |
463 | b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); | |
464 | } | |
465 | ||
466 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
467 | ||
468 | if (!(mgmt & SM_SW_FWD_EN)) { | |
469 | mgmt &= ~SM_SW_FWD_MODE; | |
470 | mgmt |= SM_SW_FWD_EN; | |
471 | ||
472 | b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); | |
473 | b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); | |
474 | ||
475 | if (!(mgmt & SM_SW_FWD_EN)) { | |
476 | dev_err(dev->dev, "Failed to enable switch!\n"); | |
477 | return -EINVAL; | |
478 | } | |
479 | } | |
480 | ||
481 | b53_enable_mib(dev); | |
482 | ||
483 | return b53_flush_arl(dev); | |
484 | } | |
485 | ||
486 | static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) | |
487 | { | |
488 | struct b53_device *priv = ds_to_priv(ds); | |
489 | u16 value = 0; | |
490 | int ret; | |
491 | ||
492 | if (priv->ops->phy_read16) | |
493 | ret = priv->ops->phy_read16(priv, addr, reg, &value); | |
494 | else | |
495 | ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), | |
496 | reg * 2, &value); | |
497 | ||
498 | return ret ? ret : value; | |
499 | } | |
500 | ||
501 | static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) | |
502 | { | |
503 | struct b53_device *priv = ds_to_priv(ds); | |
504 | ||
505 | if (priv->ops->phy_write16) | |
506 | return priv->ops->phy_write16(priv, addr, reg, val); | |
507 | ||
508 | return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); | |
509 | } | |
510 | ||
511 | static int b53_reset_switch(struct b53_device *priv) | |
512 | { | |
513 | /* reset vlans */ | |
514 | priv->enable_jumbo = false; | |
515 | ||
516 | memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); | |
517 | ||
518 | return b53_switch_reset(priv); | |
519 | } | |
520 | ||
521 | static int b53_apply_config(struct b53_device *priv) | |
522 | { | |
523 | /* disable switching */ | |
524 | b53_set_forwarding(priv, 0); | |
525 | ||
526 | b53_configure_vlan(priv); | |
527 | ||
528 | /* enable switching */ | |
529 | b53_set_forwarding(priv, 1); | |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
534 | static void b53_reset_mib(struct b53_device *priv) | |
535 | { | |
536 | u8 gc; | |
537 | ||
538 | b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); | |
539 | ||
540 | b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); | |
541 | msleep(1); | |
542 | b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); | |
543 | msleep(1); | |
544 | } | |
545 | ||
546 | static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) | |
547 | { | |
548 | if (is5365(dev)) | |
549 | return b53_mibs_65; | |
550 | else if (is63xx(dev)) | |
551 | return b53_mibs_63xx; | |
552 | else | |
553 | return b53_mibs; | |
554 | } | |
555 | ||
556 | static unsigned int b53_get_mib_size(struct b53_device *dev) | |
557 | { | |
558 | if (is5365(dev)) | |
559 | return B53_MIBS_65_SIZE; | |
560 | else if (is63xx(dev)) | |
561 | return B53_MIBS_63XX_SIZE; | |
562 | else | |
563 | return B53_MIBS_SIZE; | |
564 | } | |
565 | ||
566 | static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
567 | { | |
568 | struct b53_device *dev = ds_to_priv(ds); | |
569 | const struct b53_mib_desc *mibs = b53_get_mib(dev); | |
570 | unsigned int mib_size = b53_get_mib_size(dev); | |
571 | unsigned int i; | |
572 | ||
573 | for (i = 0; i < mib_size; i++) | |
574 | memcpy(data + i * ETH_GSTRING_LEN, | |
575 | mibs[i].name, ETH_GSTRING_LEN); | |
576 | } | |
577 | ||
578 | static void b53_get_ethtool_stats(struct dsa_switch *ds, int port, | |
579 | uint64_t *data) | |
580 | { | |
581 | struct b53_device *dev = ds_to_priv(ds); | |
582 | const struct b53_mib_desc *mibs = b53_get_mib(dev); | |
583 | unsigned int mib_size = b53_get_mib_size(dev); | |
584 | const struct b53_mib_desc *s; | |
585 | unsigned int i; | |
586 | u64 val = 0; | |
587 | ||
588 | if (is5365(dev) && port == 5) | |
589 | port = 8; | |
590 | ||
591 | mutex_lock(&dev->stats_mutex); | |
592 | ||
593 | for (i = 0; i < mib_size; i++) { | |
594 | s = &mibs[i]; | |
595 | ||
596 | if (mibs->size == 8) { | |
597 | b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); | |
598 | } else { | |
599 | u32 val32; | |
600 | ||
601 | b53_read32(dev, B53_MIB_PAGE(port), s->offset, | |
602 | &val32); | |
603 | val = val32; | |
604 | } | |
605 | data[i] = (u64)val; | |
606 | } | |
607 | ||
608 | mutex_unlock(&dev->stats_mutex); | |
609 | } | |
610 | ||
611 | static int b53_get_sset_count(struct dsa_switch *ds) | |
612 | { | |
613 | struct b53_device *dev = ds_to_priv(ds); | |
614 | ||
615 | return b53_get_mib_size(dev); | |
616 | } | |
617 | ||
618 | static int b53_set_addr(struct dsa_switch *ds, u8 *addr) | |
619 | { | |
620 | return 0; | |
621 | } | |
622 | ||
623 | static int b53_setup(struct dsa_switch *ds) | |
624 | { | |
625 | struct b53_device *dev = ds_to_priv(ds); | |
626 | unsigned int port; | |
627 | int ret; | |
628 | ||
629 | ret = b53_reset_switch(dev); | |
630 | if (ret) { | |
631 | dev_err(ds->dev, "failed to reset switch\n"); | |
632 | return ret; | |
633 | } | |
634 | ||
635 | b53_reset_mib(dev); | |
636 | ||
637 | ret = b53_apply_config(dev); | |
638 | if (ret) | |
639 | dev_err(ds->dev, "failed to apply configuration\n"); | |
640 | ||
641 | for (port = 0; port < dev->num_ports; port++) { | |
642 | if (BIT(port) & ds->enabled_port_mask) | |
643 | b53_enable_port(ds, port, NULL); | |
644 | else if (dsa_is_cpu_port(ds, port)) | |
645 | b53_enable_cpu_port(dev); | |
646 | else | |
647 | b53_disable_port(ds, port, NULL); | |
648 | } | |
649 | ||
650 | return ret; | |
651 | } | |
652 | ||
653 | static void b53_adjust_link(struct dsa_switch *ds, int port, | |
654 | struct phy_device *phydev) | |
655 | { | |
656 | struct b53_device *dev = ds_to_priv(ds); | |
657 | u8 rgmii_ctrl = 0, reg = 0, off; | |
658 | ||
659 | if (!phy_is_pseudo_fixed_link(phydev)) | |
660 | return; | |
661 | ||
662 | /* Override the port settings */ | |
663 | if (port == dev->cpu_port) { | |
664 | off = B53_PORT_OVERRIDE_CTRL; | |
665 | reg = PORT_OVERRIDE_EN; | |
666 | } else { | |
667 | off = B53_GMII_PORT_OVERRIDE_CTRL(port); | |
668 | reg = GMII_PO_EN; | |
669 | } | |
670 | ||
671 | /* Set the link UP */ | |
672 | if (phydev->link) | |
673 | reg |= PORT_OVERRIDE_LINK; | |
674 | ||
675 | if (phydev->duplex == DUPLEX_FULL) | |
676 | reg |= PORT_OVERRIDE_FULL_DUPLEX; | |
677 | ||
678 | switch (phydev->speed) { | |
679 | case 2000: | |
680 | reg |= PORT_OVERRIDE_SPEED_2000M; | |
681 | /* fallthrough */ | |
682 | case SPEED_1000: | |
683 | reg |= PORT_OVERRIDE_SPEED_1000M; | |
684 | break; | |
685 | case SPEED_100: | |
686 | reg |= PORT_OVERRIDE_SPEED_100M; | |
687 | break; | |
688 | case SPEED_10: | |
689 | reg |= PORT_OVERRIDE_SPEED_10M; | |
690 | break; | |
691 | default: | |
692 | dev_err(ds->dev, "unknown speed: %d\n", phydev->speed); | |
693 | return; | |
694 | } | |
695 | ||
696 | /* Enable flow control on BCM5301x's CPU port */ | |
697 | if (is5301x(dev) && port == dev->cpu_port) | |
698 | reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW; | |
699 | ||
700 | if (phydev->pause) { | |
701 | if (phydev->asym_pause) | |
702 | reg |= PORT_OVERRIDE_TX_FLOW; | |
703 | reg |= PORT_OVERRIDE_RX_FLOW; | |
704 | } | |
705 | ||
706 | b53_write8(dev, B53_CTRL_PAGE, off, reg); | |
707 | ||
708 | if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { | |
709 | if (port == 8) | |
710 | off = B53_RGMII_CTRL_IMP; | |
711 | else | |
712 | off = B53_RGMII_CTRL_P(port); | |
713 | ||
714 | /* Configure the port RGMII clock delay by DLL disabled and | |
715 | * tx_clk aligned timing (restoring to reset defaults) | |
716 | */ | |
717 | b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); | |
718 | rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | | |
719 | RGMII_CTRL_TIMING_SEL); | |
720 | ||
721 | /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make | |
722 | * sure that we enable the port TX clock internal delay to | |
723 | * account for this internal delay that is inserted, otherwise | |
724 | * the switch won't be able to receive correctly. | |
725 | * | |
726 | * PHY_INTERFACE_MODE_RGMII means that we are not introducing | |
727 | * any delay neither on transmission nor reception, so the | |
728 | * BCM53125 must also be configured accordingly to account for | |
729 | * the lack of delay and introduce | |
730 | * | |
731 | * The BCM53125 switch has its RX clock and TX clock control | |
732 | * swapped, hence the reason why we modify the TX clock path in | |
733 | * the "RGMII" case | |
734 | */ | |
735 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
736 | rgmii_ctrl |= RGMII_CTRL_DLL_TXC; | |
737 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII) | |
738 | rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; | |
739 | rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; | |
740 | b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); | |
741 | ||
742 | dev_info(ds->dev, "Configured port %d for %s\n", port, | |
743 | phy_modes(phydev->interface)); | |
744 | } | |
745 | ||
746 | /* configure MII port if necessary */ | |
747 | if (is5325(dev)) { | |
748 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, | |
749 | ®); | |
750 | ||
751 | /* reverse mii needs to be enabled */ | |
752 | if (!(reg & PORT_OVERRIDE_RV_MII_25)) { | |
753 | b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, | |
754 | reg | PORT_OVERRIDE_RV_MII_25); | |
755 | b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, | |
756 | ®); | |
757 | ||
758 | if (!(reg & PORT_OVERRIDE_RV_MII_25)) { | |
759 | dev_err(ds->dev, | |
760 | "Failed to enable reverse MII mode\n"); | |
761 | return; | |
762 | } | |
763 | } | |
764 | } else if (is5301x(dev)) { | |
765 | if (port != dev->cpu_port) { | |
766 | u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port); | |
767 | u8 gmii_po; | |
768 | ||
769 | b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); | |
770 | gmii_po |= GMII_PO_LINK | | |
771 | GMII_PO_RX_FLOW | | |
772 | GMII_PO_TX_FLOW | | |
773 | GMII_PO_EN | | |
774 | GMII_PO_SPEED_2000M; | |
775 | b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); | |
776 | } | |
777 | } | |
778 | } | |
779 | ||
780 | static struct dsa_switch_driver b53_switch_ops = { | |
781 | .tag_protocol = DSA_TAG_PROTO_NONE, | |
782 | .setup = b53_setup, | |
783 | .set_addr = b53_set_addr, | |
784 | .get_strings = b53_get_strings, | |
785 | .get_ethtool_stats = b53_get_ethtool_stats, | |
786 | .get_sset_count = b53_get_sset_count, | |
787 | .phy_read = b53_phy_read16, | |
788 | .phy_write = b53_phy_write16, | |
789 | .adjust_link = b53_adjust_link, | |
790 | .port_enable = b53_enable_port, | |
791 | .port_disable = b53_disable_port, | |
792 | }; | |
793 | ||
794 | struct b53_chip_data { | |
795 | u32 chip_id; | |
796 | const char *dev_name; | |
797 | u16 vlans; | |
798 | u16 enabled_ports; | |
799 | u8 cpu_port; | |
800 | u8 vta_regs[3]; | |
801 | u8 duplex_reg; | |
802 | u8 jumbo_pm_reg; | |
803 | u8 jumbo_size_reg; | |
804 | }; | |
805 | ||
806 | #define B53_VTA_REGS \ | |
807 | { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } | |
808 | #define B53_VTA_REGS_9798 \ | |
809 | { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } | |
810 | #define B53_VTA_REGS_63XX \ | |
811 | { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } | |
812 | ||
813 | static const struct b53_chip_data b53_switch_chips[] = { | |
814 | { | |
815 | .chip_id = BCM5325_DEVICE_ID, | |
816 | .dev_name = "BCM5325", | |
817 | .vlans = 16, | |
818 | .enabled_ports = 0x1f, | |
819 | .cpu_port = B53_CPU_PORT_25, | |
820 | .duplex_reg = B53_DUPLEX_STAT_FE, | |
821 | }, | |
822 | { | |
823 | .chip_id = BCM5365_DEVICE_ID, | |
824 | .dev_name = "BCM5365", | |
825 | .vlans = 256, | |
826 | .enabled_ports = 0x1f, | |
827 | .cpu_port = B53_CPU_PORT_25, | |
828 | .duplex_reg = B53_DUPLEX_STAT_FE, | |
829 | }, | |
830 | { | |
831 | .chip_id = BCM5395_DEVICE_ID, | |
832 | .dev_name = "BCM5395", | |
833 | .vlans = 4096, | |
834 | .enabled_ports = 0x1f, | |
835 | .cpu_port = B53_CPU_PORT, | |
836 | .vta_regs = B53_VTA_REGS, | |
837 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
838 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
839 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
840 | }, | |
841 | { | |
842 | .chip_id = BCM5397_DEVICE_ID, | |
843 | .dev_name = "BCM5397", | |
844 | .vlans = 4096, | |
845 | .enabled_ports = 0x1f, | |
846 | .cpu_port = B53_CPU_PORT, | |
847 | .vta_regs = B53_VTA_REGS_9798, | |
848 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
849 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
850 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
851 | }, | |
852 | { | |
853 | .chip_id = BCM5398_DEVICE_ID, | |
854 | .dev_name = "BCM5398", | |
855 | .vlans = 4096, | |
856 | .enabled_ports = 0x7f, | |
857 | .cpu_port = B53_CPU_PORT, | |
858 | .vta_regs = B53_VTA_REGS_9798, | |
859 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
860 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
861 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
862 | }, | |
863 | { | |
864 | .chip_id = BCM53115_DEVICE_ID, | |
865 | .dev_name = "BCM53115", | |
866 | .vlans = 4096, | |
867 | .enabled_ports = 0x1f, | |
868 | .vta_regs = B53_VTA_REGS, | |
869 | .cpu_port = B53_CPU_PORT, | |
870 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
871 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
872 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
873 | }, | |
874 | { | |
875 | .chip_id = BCM53125_DEVICE_ID, | |
876 | .dev_name = "BCM53125", | |
877 | .vlans = 4096, | |
878 | .enabled_ports = 0xff, | |
879 | .cpu_port = B53_CPU_PORT, | |
880 | .vta_regs = B53_VTA_REGS, | |
881 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
882 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
883 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
884 | }, | |
885 | { | |
886 | .chip_id = BCM53128_DEVICE_ID, | |
887 | .dev_name = "BCM53128", | |
888 | .vlans = 4096, | |
889 | .enabled_ports = 0x1ff, | |
890 | .cpu_port = B53_CPU_PORT, | |
891 | .vta_regs = B53_VTA_REGS, | |
892 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
893 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
894 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
895 | }, | |
896 | { | |
897 | .chip_id = BCM63XX_DEVICE_ID, | |
898 | .dev_name = "BCM63xx", | |
899 | .vlans = 4096, | |
900 | .enabled_ports = 0, /* pdata must provide them */ | |
901 | .cpu_port = B53_CPU_PORT, | |
902 | .vta_regs = B53_VTA_REGS_63XX, | |
903 | .duplex_reg = B53_DUPLEX_STAT_63XX, | |
904 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, | |
905 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, | |
906 | }, | |
907 | { | |
908 | .chip_id = BCM53010_DEVICE_ID, | |
909 | .dev_name = "BCM53010", | |
910 | .vlans = 4096, | |
911 | .enabled_ports = 0x1f, | |
912 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ | |
913 | .vta_regs = B53_VTA_REGS, | |
914 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
915 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
916 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
917 | }, | |
918 | { | |
919 | .chip_id = BCM53011_DEVICE_ID, | |
920 | .dev_name = "BCM53011", | |
921 | .vlans = 4096, | |
922 | .enabled_ports = 0x1bf, | |
923 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ | |
924 | .vta_regs = B53_VTA_REGS, | |
925 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
926 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
927 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
928 | }, | |
929 | { | |
930 | .chip_id = BCM53012_DEVICE_ID, | |
931 | .dev_name = "BCM53012", | |
932 | .vlans = 4096, | |
933 | .enabled_ports = 0x1bf, | |
934 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ | |
935 | .vta_regs = B53_VTA_REGS, | |
936 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
937 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
938 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
939 | }, | |
940 | { | |
941 | .chip_id = BCM53018_DEVICE_ID, | |
942 | .dev_name = "BCM53018", | |
943 | .vlans = 4096, | |
944 | .enabled_ports = 0x1f, | |
945 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ | |
946 | .vta_regs = B53_VTA_REGS, | |
947 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
948 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
949 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
950 | }, | |
951 | { | |
952 | .chip_id = BCM53019_DEVICE_ID, | |
953 | .dev_name = "BCM53019", | |
954 | .vlans = 4096, | |
955 | .enabled_ports = 0x1f, | |
956 | .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ | |
957 | .vta_regs = B53_VTA_REGS, | |
958 | .duplex_reg = B53_DUPLEX_STAT_GE, | |
959 | .jumbo_pm_reg = B53_JUMBO_PORT_MASK, | |
960 | .jumbo_size_reg = B53_JUMBO_MAX_SIZE, | |
961 | }, | |
962 | }; | |
963 | ||
964 | static int b53_switch_init(struct b53_device *dev) | |
965 | { | |
966 | struct dsa_switch *ds = dev->ds; | |
967 | unsigned int i; | |
968 | int ret; | |
969 | ||
970 | for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { | |
971 | const struct b53_chip_data *chip = &b53_switch_chips[i]; | |
972 | ||
973 | if (chip->chip_id == dev->chip_id) { | |
974 | if (!dev->enabled_ports) | |
975 | dev->enabled_ports = chip->enabled_ports; | |
976 | dev->name = chip->dev_name; | |
977 | dev->duplex_reg = chip->duplex_reg; | |
978 | dev->vta_regs[0] = chip->vta_regs[0]; | |
979 | dev->vta_regs[1] = chip->vta_regs[1]; | |
980 | dev->vta_regs[2] = chip->vta_regs[2]; | |
981 | dev->jumbo_pm_reg = chip->jumbo_pm_reg; | |
982 | ds->drv = &b53_switch_ops; | |
983 | dev->cpu_port = chip->cpu_port; | |
984 | dev->num_vlans = chip->vlans; | |
985 | break; | |
986 | } | |
987 | } | |
988 | ||
989 | /* check which BCM5325x version we have */ | |
990 | if (is5325(dev)) { | |
991 | u8 vc4; | |
992 | ||
993 | b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); | |
994 | ||
995 | /* check reserved bits */ | |
996 | switch (vc4 & 3) { | |
997 | case 1: | |
998 | /* BCM5325E */ | |
999 | break; | |
1000 | case 3: | |
1001 | /* BCM5325F - do not use port 4 */ | |
1002 | dev->enabled_ports &= ~BIT(4); | |
1003 | break; | |
1004 | default: | |
1005 | /* On the BCM47XX SoCs this is the supported internal switch.*/ | |
1006 | #ifndef CONFIG_BCM47XX | |
1007 | /* BCM5325M */ | |
1008 | return -EINVAL; | |
1009 | #else | |
1010 | break; | |
1011 | #endif | |
1012 | } | |
1013 | } else if (dev->chip_id == BCM53115_DEVICE_ID) { | |
1014 | u64 strap_value; | |
1015 | ||
1016 | b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); | |
1017 | /* use second IMP port if GMII is enabled */ | |
1018 | if (strap_value & SV_GMII_CTRL_115) | |
1019 | dev->cpu_port = 5; | |
1020 | } | |
1021 | ||
1022 | /* cpu port is always last */ | |
1023 | dev->num_ports = dev->cpu_port + 1; | |
1024 | dev->enabled_ports |= BIT(dev->cpu_port); | |
1025 | ||
1026 | dev->ports = devm_kzalloc(dev->dev, | |
1027 | sizeof(struct b53_port) * dev->num_ports, | |
1028 | GFP_KERNEL); | |
1029 | if (!dev->ports) | |
1030 | return -ENOMEM; | |
1031 | ||
1032 | dev->reset_gpio = b53_switch_get_reset_gpio(dev); | |
1033 | if (dev->reset_gpio >= 0) { | |
1034 | ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, | |
1035 | GPIOF_OUT_INIT_HIGH, "robo_reset"); | |
1036 | if (ret) | |
1037 | return ret; | |
1038 | } | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
1043 | struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops, | |
1044 | void *priv) | |
1045 | { | |
1046 | struct dsa_switch *ds; | |
1047 | struct b53_device *dev; | |
1048 | ||
1049 | ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL); | |
1050 | if (!ds) | |
1051 | return NULL; | |
1052 | ||
1053 | dev = (struct b53_device *)(ds + 1); | |
1054 | ||
1055 | ds->priv = dev; | |
1056 | ds->dev = base; | |
1057 | dev->dev = base; | |
1058 | ||
1059 | dev->ds = ds; | |
1060 | dev->priv = priv; | |
1061 | dev->ops = ops; | |
1062 | mutex_init(&dev->reg_mutex); | |
1063 | mutex_init(&dev->stats_mutex); | |
1064 | ||
1065 | return dev; | |
1066 | } | |
1067 | EXPORT_SYMBOL(b53_switch_alloc); | |
1068 | ||
1069 | int b53_switch_detect(struct b53_device *dev) | |
1070 | { | |
1071 | u32 id32; | |
1072 | u16 tmp; | |
1073 | u8 id8; | |
1074 | int ret; | |
1075 | ||
1076 | ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); | |
1077 | if (ret) | |
1078 | return ret; | |
1079 | ||
1080 | switch (id8) { | |
1081 | case 0: | |
1082 | /* BCM5325 and BCM5365 do not have this register so reads | |
1083 | * return 0. But the read operation did succeed, so assume this | |
1084 | * is one of them. | |
1085 | * | |
1086 | * Next check if we can write to the 5325's VTA register; for | |
1087 | * 5365 it is read only. | |
1088 | */ | |
1089 | b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); | |
1090 | b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); | |
1091 | ||
1092 | if (tmp == 0xf) | |
1093 | dev->chip_id = BCM5325_DEVICE_ID; | |
1094 | else | |
1095 | dev->chip_id = BCM5365_DEVICE_ID; | |
1096 | break; | |
1097 | case BCM5395_DEVICE_ID: | |
1098 | case BCM5397_DEVICE_ID: | |
1099 | case BCM5398_DEVICE_ID: | |
1100 | dev->chip_id = id8; | |
1101 | break; | |
1102 | default: | |
1103 | ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); | |
1104 | if (ret) | |
1105 | return ret; | |
1106 | ||
1107 | switch (id32) { | |
1108 | case BCM53115_DEVICE_ID: | |
1109 | case BCM53125_DEVICE_ID: | |
1110 | case BCM53128_DEVICE_ID: | |
1111 | case BCM53010_DEVICE_ID: | |
1112 | case BCM53011_DEVICE_ID: | |
1113 | case BCM53012_DEVICE_ID: | |
1114 | case BCM53018_DEVICE_ID: | |
1115 | case BCM53019_DEVICE_ID: | |
1116 | dev->chip_id = id32; | |
1117 | break; | |
1118 | default: | |
1119 | pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", | |
1120 | id8, id32); | |
1121 | return -ENODEV; | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | if (dev->chip_id == BCM5325_DEVICE_ID) | |
1126 | return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, | |
1127 | &dev->core_rev); | |
1128 | else | |
1129 | return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, | |
1130 | &dev->core_rev); | |
1131 | } | |
1132 | EXPORT_SYMBOL(b53_switch_detect); | |
1133 | ||
1134 | int b53_switch_register(struct b53_device *dev) | |
1135 | { | |
1136 | int ret; | |
1137 | ||
1138 | if (dev->pdata) { | |
1139 | dev->chip_id = dev->pdata->chip_id; | |
1140 | dev->enabled_ports = dev->pdata->enabled_ports; | |
1141 | } | |
1142 | ||
1143 | if (!dev->chip_id && b53_switch_detect(dev)) | |
1144 | return -EINVAL; | |
1145 | ||
1146 | ret = b53_switch_init(dev); | |
1147 | if (ret) | |
1148 | return ret; | |
1149 | ||
1150 | pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); | |
1151 | ||
1152 | return dsa_register_switch(dev->ds, dev->ds->dev->of_node); | |
1153 | } | |
1154 | EXPORT_SYMBOL(b53_switch_register); | |
1155 | ||
1156 | MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); | |
1157 | MODULE_DESCRIPTION("B53 switch library"); | |
1158 | MODULE_LICENSE("Dual BSD/GPL"); |