]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/dsa/b53/b53_common.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: dsa: b53: Include IMP/CPU port in dumb forwarding mode
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f 31#include <net/dsa.h>
1da6df85 32#include <net/switchdev.h>
967dd82f
FF		 33
34#include "b53_regs.h"
35#include "b53_priv.h"
36
37struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41};
42
43/* BCM5365 MIB counters */
44static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77};
78
79#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80
81/* BCM63xx MIB counters */
82static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125};
126
127#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
128
129/* MIB counters */
130static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
166};
167
168#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169
bde5d132
FF		 170static const struct b53_mib_desc b53_mibs_58xx[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
225};
226
227#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228
967dd82f
FF		 229static int b53_do_vlan_op(struct b53_device *dev, u8 op)
230{
231 unsigned int i;
232
233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234
235 for (i = 0; i < 10; i++) {
236 u8 vta;
237
238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
239 if (!(vta & VTA_START_CMD))
240 return 0;
241
242 usleep_range(100, 200);
243 }
244
245 return -EIO;
246}
247
a2482d2c
FF		 248static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
249 struct b53_vlan *vlan)
967dd82f
FF		 250{
251 if (is5325(dev)) {
252 u32 entry = 0;
253
a2482d2c
FF		 254 if (vlan->members) {
255 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
256 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 257 if (dev->core_rev >= 3)
258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 else
260 entry |= VA_VALID_25;
261 }
262
263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
265 VTA_RW_STATE_WR | VTA_RW_OP_EN);
266 } else if (is5365(dev)) {
267 u16 entry = 0;
268
a2482d2c
FF		 269 if (vlan->members)
270 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 272
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
275 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 } else {
277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 279 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 280
281 b53_do_vlan_op(dev, VTA_CMD_WRITE);
282 }
a2482d2c
FF		 283
284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid, vlan->members, vlan->untag);
286}
287
288static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
289 struct b53_vlan *vlan)
290{
291 if (is5325(dev)) {
292 u32 entry = 0;
293
294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
295 VTA_RW_STATE_RD | VTA_RW_OP_EN);
296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297
298 if (dev->core_rev >= 3)
299 vlan->valid = !!(entry & VA_VALID_25_R4);
300 else
301 vlan->valid = !!(entry & VA_VALID_25);
302 vlan->members = entry & VA_MEMBER_MASK;
303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304
305 } else if (is5365(dev)) {
306 u16 entry = 0;
307
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
309 VTA_RW_STATE_WR | VTA_RW_OP_EN);
310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311
312 vlan->valid = !!(entry & VA_VALID_65);
313 vlan->members = entry & VA_MEMBER_MASK;
314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
315 } else {
316 u32 entry = 0;
317
318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
319 b53_do_vlan_op(dev, VTA_CMD_READ);
320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
321 vlan->members = entry & VTE_MEMBERS;
322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
323 vlan->valid = true;
324 }
967dd82f
FF		 325}
326
a2482d2c 327static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f 328{
a424f0de 329 struct dsa_switch *ds = dev->ds;
967dd82f
FF		 330 u8 mgmt;
331
332 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
333
334 if (enable)
335 mgmt |= SM_SW_FWD_EN;
336 else
337 mgmt &= ~SM_SW_FWD_EN;
338
339 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de
FF		 340
341 /* Include IMP port in dumb forwarding mode when no tagging protocol is
342 * set
343 */
344 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
345 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
346 mgmt |= B53_MII_DUMB_FWDG_EN;
347 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
348 }
967dd82f
FF		 349}
350
a2482d2c 351static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 352{
353 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
354
355 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
358
359 if (is5325(dev) || is5365(dev)) {
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
362 } else if (is63xx(dev)) {
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
365 } else {
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
368 }
369
370 mgmt &= ~SM_SW_FWD_MODE;
371
372 if (enable) {
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
376 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
377 vc5 |= VC5_DROP_VTABLE_MISS;
378
379 if (is5325(dev))
380 vc0 &= ~VC0_RESERVED_1;
381
382 if (is5325(dev) || is5365(dev))
383 vc1 |= VC1_RX_MCST_TAG_EN;
384
967dd82f
FF		 385 } else {
386 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
387 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
388 vc4 &= ~VC4_ING_VID_CHECK_MASK;
389 vc5 &= ~VC5_DROP_VTABLE_MISS;
390
391 if (is5325(dev) || is5365(dev))
392 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
393 else
394 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
395
396 if (is5325(dev) || is5365(dev))
397 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 398 }
399
a2482d2c
FF		 400 if (!is5325(dev) && !is5365(dev))
401 vc5 &= ~VC5_VID_FFF_EN;
402
967dd82f
FF		 403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
405
406 if (is5325(dev) || is5365(dev)) {
407 /* enable the high 8 bit vid check on 5325 */
408 if (is5325(dev) && enable)
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
410 VC3_HIGH_8BIT_EN);
411 else
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
413
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
416 } else if (is63xx(dev)) {
417 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
420 } else {
421 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
424 }
425
426 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
427}
428
429static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
430{
431 u32 port_mask = 0;
432 u16 max_size = JMS_MIN_SIZE;
433
434 if (is5325(dev) || is5365(dev))
435 return -EINVAL;
436
437 if (enable) {
438 port_mask = dev->enabled_ports;
439 max_size = JMS_MAX_SIZE;
440 if (allow_10_100)
441 port_mask |= JPM_10_100_JUMBO_EN;
442 }
443
444 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
445 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
446}
447
ff39c2d6 448static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 449{
450 unsigned int i;
451
452 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 453 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 454
455 for (i = 0; i < 10; i++) {
456 u8 fast_age_ctrl;
457
458 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
459 &fast_age_ctrl);
460
461 if (!(fast_age_ctrl & FAST_AGE_DONE))
462 goto out;
463
464 msleep(1);
465 }
466
467 return -ETIMEDOUT;
468out:
469 /* Only age dynamic entries (default behavior) */
470 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
471 return 0;
472}
473
ff39c2d6
FF		 474static int b53_fast_age_port(struct b53_device *dev, int port)
475{
476 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
477
478 return b53_flush_arl(dev, FAST_AGE_PORT);
479}
480
a2482d2c
FF		 481static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
482{
483 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
484
485 return b53_flush_arl(dev, FAST_AGE_VLAN);
486}
487
ff39c2d6
FF		 488static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
489{
04bed143 490 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 491 unsigned int i;
492 u16 pvlan;
493
494 /* Enable the IMP port to be in the same VLAN as the other ports
495 * on a per-port basis such that we only have Port i and IMP in
496 * the same VLAN.
497 */
498 b53_for_each_port(dev, i) {
499 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
500 pvlan |= BIT(cpu_port);
501 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
502 }
503}
504
967dd82f
FF		 505static int b53_enable_port(struct dsa_switch *ds, int port,
506 struct phy_device *phy)
507{
04bed143 508 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 509 unsigned int cpu_port = dev->cpu_port;
510 u16 pvlan;
967dd82f
FF		 511
512 /* Clear the Rx and Tx disable bits and set to no spanning tree */
513 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
514
ff39c2d6
FF		 515 /* Set this port, and only this one to be in the default VLAN,
516 * if member of a bridge, restore its membership prior to
517 * bringing down this port.
518 */
519 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
520 pvlan &= ~0x1ff;
521 pvlan |= BIT(port);
522 pvlan |= dev->ports[port].vlan_ctl_mask;
523 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
524
525 b53_imp_vlan_setup(ds, cpu_port);
526
967dd82f
FF		 527 return 0;
528}
529
530static void b53_disable_port(struct dsa_switch *ds, int port,
531 struct phy_device *phy)
532{
04bed143 533 struct b53_device *dev = ds->priv;
967dd82f
FF		 534 u8 reg;
535
536 /* Disable Tx/Rx for the port */
537 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
538 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
539 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
540}
541
542static void b53_enable_cpu_port(struct b53_device *dev)
543{
544 unsigned int cpu_port = dev->cpu_port;
545 u8 port_ctrl;
546
547 /* BCM5325 CPU port is at 8 */
548 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
549 cpu_port = B53_CPU_PORT;
550
551 port_ctrl = PORT_CTRL_RX_BCST_EN |
552 PORT_CTRL_RX_MCST_EN |
553 PORT_CTRL_RX_UCST_EN;
554 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
555}
556
557static void b53_enable_mib(struct b53_device *dev)
558{
559 u8 gc;
560
561 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
562 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
563 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
564}
565
566static int b53_configure_vlan(struct b53_device *dev)
567{
a2482d2c 568 struct b53_vlan vl = { 0 };
967dd82f
FF		 569 int i;
570
571 /* clear all vlan entries */
572 if (is5325(dev) || is5365(dev)) {
573 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 574 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 575 } else {
576 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
577 }
578
579 b53_enable_vlan(dev, false);
580
581 b53_for_each_port(dev, i)
582 b53_write16(dev, B53_VLAN_PAGE,
583 B53_VLAN_PORT_DEF_TAG(i), 1);
584
585 if (!is5325(dev) && !is5365(dev))
586 b53_set_jumbo(dev, dev->enable_jumbo, false);
587
588 return 0;
589}
590
591static void b53_switch_reset_gpio(struct b53_device *dev)
592{
593 int gpio = dev->reset_gpio;
594
595 if (gpio < 0)
596 return;
597
598 /* Reset sequence: RESET low(50ms)->high(20ms)
599 */
600 gpio_set_value(gpio, 0);
601 mdelay(50);
602
603 gpio_set_value(gpio, 1);
604 mdelay(20);
605
606 dev->current_page = 0xff;
607}
608
609static int b53_switch_reset(struct b53_device *dev)
610{
611 u8 mgmt;
612
613 b53_switch_reset_gpio(dev);
614
615 if (is539x(dev)) {
616 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
617 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
618 }
619
620 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
621
622 if (!(mgmt & SM_SW_FWD_EN)) {
623 mgmt &= ~SM_SW_FWD_MODE;
624 mgmt |= SM_SW_FWD_EN;
625
626 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
627 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
628
629 if (!(mgmt & SM_SW_FWD_EN)) {
630 dev_err(dev->dev, "Failed to enable switch!\n");
631 return -EINVAL;
632 }
633 }
634
635 b53_enable_mib(dev);
636
ff39c2d6 637 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 638}
639
640static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
641{
04bed143 642 struct b53_device *priv = ds->priv;
967dd82f
FF		 643 u16 value = 0;
644 int ret;
645
646 if (priv->ops->phy_read16)
647 ret = priv->ops->phy_read16(priv, addr, reg, &value);
648 else
649 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
650 reg * 2, &value);
651
652 return ret ? ret : value;
653}
654
655static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
656{
04bed143 657 struct b53_device *priv = ds->priv;
967dd82f
FF		 658
659 if (priv->ops->phy_write16)
660 return priv->ops->phy_write16(priv, addr, reg, val);
661
662 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
663}
664
665static int b53_reset_switch(struct b53_device *priv)
666{
667 /* reset vlans */
668 priv->enable_jumbo = false;
669
a2482d2c 670 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 671 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
672
673 return b53_switch_reset(priv);
674}
675
676static int b53_apply_config(struct b53_device *priv)
677{
678 /* disable switching */
679 b53_set_forwarding(priv, 0);
680
681 b53_configure_vlan(priv);
682
683 /* enable switching */
684 b53_set_forwarding(priv, 1);
685
686 return 0;
687}
688
689static void b53_reset_mib(struct b53_device *priv)
690{
691 u8 gc;
692
693 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
694
695 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
696 msleep(1);
697 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
698 msleep(1);
699}
700
701static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
702{
703 if (is5365(dev))
704 return b53_mibs_65;
705 else if (is63xx(dev))
706 return b53_mibs_63xx;
bde5d132
FF		 707 else if (is58xx(dev))
708 return b53_mibs_58xx;
967dd82f
FF		 709 else
710 return b53_mibs;
711}
712
713static unsigned int b53_get_mib_size(struct b53_device *dev)
714{
715 if (is5365(dev))
716 return B53_MIBS_65_SIZE;
717 else if (is63xx(dev))
718 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 719 else if (is58xx(dev))
720 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 721 else
722 return B53_MIBS_SIZE;
723}
724
3117455d 725void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
967dd82f 726{
04bed143 727 struct b53_device *dev = ds->priv;
967dd82f
FF		 728 const struct b53_mib_desc *mibs = b53_get_mib(dev);
729 unsigned int mib_size = b53_get_mib_size(dev);
730 unsigned int i;
731
732 for (i = 0; i < mib_size; i++)
733 memcpy(data + i * ETH_GSTRING_LEN,
734 mibs[i].name, ETH_GSTRING_LEN);
735}
3117455d 736EXPORT_SYMBOL(b53_get_strings);
967dd82f 737
3117455d 738void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 739{
04bed143 740 struct b53_device *dev = ds->priv;
967dd82f
FF		 741 const struct b53_mib_desc *mibs = b53_get_mib(dev);
742 unsigned int mib_size = b53_get_mib_size(dev);
743 const struct b53_mib_desc *s;
744 unsigned int i;
745 u64 val = 0;
746
747 if (is5365(dev) && port == 5)
748 port = 8;
749
750 mutex_lock(&dev->stats_mutex);
751
752 for (i = 0; i < mib_size; i++) {
753 s = &mibs[i];
754
51dca8a1 755 if (s->size == 8) {
967dd82f
FF		 756 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
757 } else {
758 u32 val32;
759
760 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
761 &val32);
762 val = val32;
763 }
764 data[i] = (u64)val;
765 }
766
767 mutex_unlock(&dev->stats_mutex);
768}
3117455d 769EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 770
3117455d 771int b53_get_sset_count(struct dsa_switch *ds)
967dd82f 772{
04bed143 773 struct b53_device *dev = ds->priv;
967dd82f
FF		 774
775 return b53_get_mib_size(dev);
776}
3117455d 777EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 778
967dd82f
FF		 779static int b53_setup(struct dsa_switch *ds)
780{
04bed143 781 struct b53_device *dev = ds->priv;
967dd82f
FF		 782 unsigned int port;
783 int ret;
784
785 ret = b53_reset_switch(dev);
786 if (ret) {
787 dev_err(ds->dev, "failed to reset switch\n");
788 return ret;
789 }
790
791 b53_reset_mib(dev);
792
793 ret = b53_apply_config(dev);
794 if (ret)
795 dev_err(ds->dev, "failed to apply configuration\n");
796
797 for (port = 0; port < dev->num_ports; port++) {
798 if (BIT(port) & ds->enabled_port_mask)
799 b53_enable_port(ds, port, NULL);
800 else if (dsa_is_cpu_port(ds, port))
801 b53_enable_cpu_port(dev);
802 else
803 b53_disable_port(ds, port, NULL);
804 }
805
806 return ret;
807}
808
809static void b53_adjust_link(struct dsa_switch *ds, int port,
810 struct phy_device *phydev)
811{
04bed143 812 struct b53_device *dev = ds->priv;
967dd82f
FF		 813 u8 rgmii_ctrl = 0, reg = 0, off;
814
815 if (!phy_is_pseudo_fixed_link(phydev))
816 return;
817
818 /* Override the port settings */
819 if (port == dev->cpu_port) {
820 off = B53_PORT_OVERRIDE_CTRL;
821 reg = PORT_OVERRIDE_EN;
822 } else {
823 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
824 reg = GMII_PO_EN;
825 }
826
827 /* Set the link UP */
828 if (phydev->link)
829 reg |= PORT_OVERRIDE_LINK;
830
831 if (phydev->duplex == DUPLEX_FULL)
832 reg |= PORT_OVERRIDE_FULL_DUPLEX;
833
834 switch (phydev->speed) {
835 case 2000:
836 reg |= PORT_OVERRIDE_SPEED_2000M;
837 /* fallthrough */
838 case SPEED_1000:
839 reg |= PORT_OVERRIDE_SPEED_1000M;
840 break;
841 case SPEED_100:
842 reg |= PORT_OVERRIDE_SPEED_100M;
843 break;
844 case SPEED_10:
845 reg |= PORT_OVERRIDE_SPEED_10M;
846 break;
847 default:
848 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
849 return;
850 }
851
852 /* Enable flow control on BCM5301x's CPU port */
853 if (is5301x(dev) && port == dev->cpu_port)
854 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
855
856 if (phydev->pause) {
857 if (phydev->asym_pause)
858 reg |= PORT_OVERRIDE_TX_FLOW;
859 reg |= PORT_OVERRIDE_RX_FLOW;
860 }
861
862 b53_write8(dev, B53_CTRL_PAGE, off, reg);
863
864 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
865 if (port == 8)
866 off = B53_RGMII_CTRL_IMP;
867 else
868 off = B53_RGMII_CTRL_P(port);
869
870 /* Configure the port RGMII clock delay by DLL disabled and
871 * tx_clk aligned timing (restoring to reset defaults)
872 */
873 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
874 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
875 RGMII_CTRL_TIMING_SEL);
876
877 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
878 * sure that we enable the port TX clock internal delay to
879 * account for this internal delay that is inserted, otherwise
880 * the switch won't be able to receive correctly.
881 *
882 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
883 * any delay neither on transmission nor reception, so the
884 * BCM53125 must also be configured accordingly to account for
885 * the lack of delay and introduce
886 *
887 * The BCM53125 switch has its RX clock and TX clock control
888 * swapped, hence the reason why we modify the TX clock path in
889 * the "RGMII" case
890 */
891 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
892 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
893 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
894 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
895 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
896 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
897
898 dev_info(ds->dev, "Configured port %d for %s\n", port,
899 phy_modes(phydev->interface));
900 }
901
902 /* configure MII port if necessary */
903 if (is5325(dev)) {
904 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
905 &reg);
906
907 /* reverse mii needs to be enabled */
908 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
909 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
910 reg | PORT_OVERRIDE_RV_MII_25);
911 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
912 &reg);
913
914 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
915 dev_err(ds->dev,
916 "Failed to enable reverse MII mode\n");
917 return;
918 }
919 }
920 } else if (is5301x(dev)) {
921 if (port != dev->cpu_port) {
922 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
923 u8 gmii_po;
924
925 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
926 gmii_po |= GMII_PO_LINK |
927 GMII_PO_RX_FLOW |
928 GMII_PO_TX_FLOW |
929 GMII_PO_EN |
930 GMII_PO_SPEED_2000M;
931 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
932 }
933 }
934}
935
3117455d 936int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 937{
938 return 0;
939}
3117455d 940EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 941
3117455d
FF		 942int b53_vlan_prepare(struct dsa_switch *ds, int port,
943 const struct switchdev_obj_port_vlan *vlan,
944 struct switchdev_trans *trans)
a2482d2c 945{
04bed143 946 struct b53_device *dev = ds->priv;
a2482d2c
FF		 947
948 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
949 return -EOPNOTSUPP;
950
951 if (vlan->vid_end > dev->num_vlans)
952 return -ERANGE;
953
954 b53_enable_vlan(dev, true);
955
956 return 0;
957}
3117455d 958EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 959
3117455d
FF		 960void b53_vlan_add(struct dsa_switch *ds, int port,
961 const struct switchdev_obj_port_vlan *vlan,
962 struct switchdev_trans *trans)
a2482d2c 963{
04bed143 964 struct b53_device *dev = ds->priv;
a2482d2c
FF		 965 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
966 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
967 unsigned int cpu_port = dev->cpu_port;
968 struct b53_vlan *vl;
969 u16 vid;
970
971 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
972 vl = &dev->vlans[vid];
973
974 b53_get_vlan_entry(dev, vid, vl);
975
976 vl->members |= BIT(port) | BIT(cpu_port);
977 if (untagged)
e47112d9 978 vl->untag |= BIT(port);
a2482d2c 979 else
e47112d9
FF		 980 vl->untag &= ~BIT(port);
981 vl->untag &= ~BIT(cpu_port);
a2482d2c
FF		 982
983 b53_set_vlan_entry(dev, vid, vl);
984 b53_fast_age_vlan(dev, vid);
985 }
986
987 if (pvid) {
988 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
989 vlan->vid_end);
a2482d2c
FF		 990 b53_fast_age_vlan(dev, vid);
991 }
992}
3117455d 993EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 994
3117455d
FF		 995int b53_vlan_del(struct dsa_switch *ds, int port,
996 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 997{
04bed143 998 struct b53_device *dev = ds->priv;
a2482d2c 999 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1000 struct b53_vlan *vl;
1001 u16 vid;
1002 u16 pvid;
1003
1004 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1005
1006 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1007 vl = &dev->vlans[vid];
1008
1009 b53_get_vlan_entry(dev, vid, vl);
1010
1011 vl->members &= ~BIT(port);
a2482d2c
FF		 1012
1013 if (pvid == vid) {
1014 if (is5325(dev) || is5365(dev))
1015 pvid = 1;
1016 else
1017 pvid = 0;
1018 }
1019
e47112d9 1020 if (untagged)
a2482d2c 1021 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1022
1023 b53_set_vlan_entry(dev, vid, vl);
1024 b53_fast_age_vlan(dev, vid);
1025 }
1026
1027 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1028 b53_fast_age_vlan(dev, pvid);
1029
1030 return 0;
1031}
3117455d 1032EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1033
3117455d
FF		 1034int b53_vlan_dump(struct dsa_switch *ds, int port,
1035 struct switchdev_obj_port_vlan *vlan,
1036 int (*cb)(struct switchdev_obj *obj))
a2482d2c 1037{
04bed143 1038 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1039 u16 vid, vid_start = 0, pvid;
1040 struct b53_vlan *vl;
1041 int err = 0;
1042
1043 if (is5325(dev) || is5365(dev))
1044 vid_start = 1;
1045
1046 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1047
1048 /* Use our software cache for dumps, since we do not have any HW
1049 * operation returning only the used/valid VLANs
1050 */
1051 for (vid = vid_start; vid < dev->num_vlans; vid++) {
1052 vl = &dev->vlans[vid];
1053
1054 if (!vl->valid)
1055 continue;
1056
1057 if (!(vl->members & BIT(port)))
1058 continue;
1059
1060 vlan->vid_begin = vlan->vid_end = vid;
1061 vlan->flags = 0;
1062
1063 if (vl->untag & BIT(port))
1064 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1065 if (pvid == vid)
1066 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1067
1068 err = cb(&vlan->obj);
1069 if (err)
1070 break;
1071 }
1072
1073 return err;
1074}
3117455d 1075EXPORT_SYMBOL(b53_vlan_dump);
a2482d2c 1076
1da6df85
FF		 1077/* Address Resolution Logic routines */
1078static int b53_arl_op_wait(struct b53_device *dev)
1079{
1080 unsigned int timeout = 10;
1081 u8 reg;
1082
1083 do {
1084 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1085 if (!(reg & ARLTBL_START_DONE))
1086 return 0;
1087
1088 usleep_range(1000, 2000);
1089 } while (timeout--);
1090
1091 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1092
1093 return -ETIMEDOUT;
1094}
1095
1096static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1097{
1098 u8 reg;
1099
1100 if (op > ARLTBL_RW)
1101 return -EINVAL;
1102
1103 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1104 reg |= ARLTBL_START_DONE;
1105 if (op)
1106 reg |= ARLTBL_RW;
1107 else
1108 reg &= ~ARLTBL_RW;
1109 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1110
1111 return b53_arl_op_wait(dev);
1112}
1113
1114static int b53_arl_read(struct b53_device *dev, u64 mac,
1115 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1116 bool is_valid)
1117{
1118 unsigned int i;
1119 int ret;
1120
1121 ret = b53_arl_op_wait(dev);
1122 if (ret)
1123 return ret;
1124
1125 /* Read the bins */
1126 for (i = 0; i < dev->num_arl_entries; i++) {
1127 u64 mac_vid;
1128 u32 fwd_entry;
1129
1130 b53_read64(dev, B53_ARLIO_PAGE,
1131 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1132 b53_read32(dev, B53_ARLIO_PAGE,
1133 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1134 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1135
1136 if (!(fwd_entry & ARLTBL_VALID))
1137 continue;
1138 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1139 continue;
1140 *idx = i;
1141 }
1142
1143 return -ENOENT;
1144}
1145
1146static int b53_arl_op(struct b53_device *dev, int op, int port,
1147 const unsigned char *addr, u16 vid, bool is_valid)
1148{
1149 struct b53_arl_entry ent;
1150 u32 fwd_entry;
1151 u64 mac, mac_vid = 0;
1152 u8 idx = 0;
1153 int ret;
1154
1155 /* Convert the array into a 64-bit MAC */
4b92ea81 1156 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1157
1158 /* Perform a read for the given MAC and VID */
1159 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1160 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1161
1162 /* Issue a read operation for this MAC */
1163 ret = b53_arl_rw_op(dev, 1);
1164 if (ret)
1165 return ret;
1166
1167 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1168 /* If this is a read, just finish now */
1169 if (op)
1170 return ret;
1171
1172 /* We could not find a matching MAC, so reset to a new entry */
1173 if (ret) {
1174 fwd_entry = 0;
1175 idx = 1;
1176 }
1177
1178 memset(&ent, 0, sizeof(ent));
1179 ent.port = port;
1180 ent.is_valid = is_valid;
1181 ent.vid = vid;
1182 ent.is_static = true;
1183 memcpy(ent.mac, addr, ETH_ALEN);
1184 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1185
1186 b53_write64(dev, B53_ARLIO_PAGE,
1187 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1188 b53_write32(dev, B53_ARLIO_PAGE,
1189 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1190
1191 return b53_arl_rw_op(dev, 0);
1192}
1193
3117455d
FF		 1194int b53_fdb_prepare(struct dsa_switch *ds, int port,
1195 const struct switchdev_obj_port_fdb *fdb,
1196 struct switchdev_trans *trans)
1da6df85 1197{
04bed143 1198 struct b53_device *priv = ds->priv;
1da6df85
FF		 1199
1200 /* 5325 and 5365 require some more massaging, but could
1201 * be supported eventually
1202 */
1203 if (is5325(priv) || is5365(priv))
1204 return -EOPNOTSUPP;
1205
1206 return 0;
1207}
3117455d 1208EXPORT_SYMBOL(b53_fdb_prepare);
1da6df85 1209
3117455d
FF		 1210void b53_fdb_add(struct dsa_switch *ds, int port,
1211 const struct switchdev_obj_port_fdb *fdb,
1212 struct switchdev_trans *trans)
1da6df85 1213{
04bed143 1214 struct b53_device *priv = ds->priv;
1da6df85
FF		 1215
1216 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1217 pr_err("%s: failed to add MAC address\n", __func__);
1218}
3117455d 1219EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1220
3117455d
FF		 1221int b53_fdb_del(struct dsa_switch *ds, int port,
1222 const struct switchdev_obj_port_fdb *fdb)
1da6df85 1223{
04bed143 1224 struct b53_device *priv = ds->priv;
1da6df85
FF		 1225
1226 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1227}
3117455d 1228EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1229
1230static int b53_arl_search_wait(struct b53_device *dev)
1231{
1232 unsigned int timeout = 1000;
1233 u8 reg;
1234
1235 do {
1236 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1237 if (!(reg & ARL_SRCH_STDN))
1238 return 0;
1239
1240 if (reg & ARL_SRCH_VLID)
1241 return 0;
1242
1243 usleep_range(1000, 2000);
1244 } while (timeout--);
1245
1246 return -ETIMEDOUT;
1247}
1248
1249static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1250 struct b53_arl_entry *ent)
1251{
1252 u64 mac_vid;
1253 u32 fwd_entry;
1254
1255 b53_read64(dev, B53_ARLIO_PAGE,
1256 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1257 b53_read32(dev, B53_ARLIO_PAGE,
1258 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1259 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1260}
1261
1262static int b53_fdb_copy(struct net_device *dev, int port,
1263 const struct b53_arl_entry *ent,
1264 struct switchdev_obj_port_fdb *fdb,
1265 int (*cb)(struct switchdev_obj *obj))
1266{
1267 if (!ent->is_valid)
1268 return 0;
1269
1270 if (port != ent->port)
1271 return 0;
1272
1273 ether_addr_copy(fdb->addr, ent->mac);
1274 fdb->vid = ent->vid;
1275 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1276
1277 return cb(&fdb->obj);
1278}
1279
3117455d
FF		 1280int b53_fdb_dump(struct dsa_switch *ds, int port,
1281 struct switchdev_obj_port_fdb *fdb,
1282 int (*cb)(struct switchdev_obj *obj))
1da6df85 1283{
04bed143 1284 struct b53_device *priv = ds->priv;
1da6df85
FF		 1285 struct net_device *dev = ds->ports[port].netdev;
1286 struct b53_arl_entry results[2];
1287 unsigned int count = 0;
1288 int ret;
1289 u8 reg;
1290
1291 /* Start search operation */
1292 reg = ARL_SRCH_STDN;
1293 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1294
1295 do {
1296 ret = b53_arl_search_wait(priv);
1297 if (ret)
1298 return ret;
1299
1300 b53_arl_search_rd(priv, 0, &results[0]);
1301 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1302 if (ret)
1303 return ret;
1304
1305 if (priv->num_arl_entries > 2) {
1306 b53_arl_search_rd(priv, 1, &results[1]);
1307 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1308 if (ret)
1309 return ret;
1310
1311 if (!results[0].is_valid && !results[1].is_valid)
1312 break;
1313 }
1314
1315 } while (count++ < 1024);
1316
1317 return 0;
1318}
3117455d 1319EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1320
ddd3a0c8 1321int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1322{
04bed143 1323 struct b53_device *dev = ds->priv;
48aea33a 1324 s8 cpu_port = ds->dst->cpu_port;
ff39c2d6
FF		 1325 u16 pvlan, reg;
1326 unsigned int i;
1327
48aea33a
FF		 1328 /* Make this port leave the all VLANs join since we will have proper
1329 * VLAN entries from now on
1330 */
1331 if (is58xx(dev)) {
1332 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1333 reg &= ~BIT(port);
1334 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1335 reg &= ~BIT(cpu_port);
1336 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1337 }
1338
ff39c2d6
FF		 1339 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1340
1341 b53_for_each_port(dev, i) {
ddd3a0c8 1342 if (ds->ports[i].bridge_dev != br)
ff39c2d6
FF		 1343 continue;
1344
1345 /* Add this local port to the remote port VLAN control
1346 * membership and update the remote port bitmask
1347 */
1348 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1349 reg |= BIT(port);
1350 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1351 dev->ports[i].vlan_ctl_mask = reg;
1352
1353 pvlan |= BIT(i);
1354 }
1355
1356 /* Configure the local port VLAN control membership to include
1357 * remote ports and update the local port bitmask
1358 */
1359 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1360 dev->ports[port].vlan_ctl_mask = pvlan;
1361
1362 return 0;
1363}
3117455d 1364EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1365
f123f2fb 1366void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1367{
04bed143 1368 struct b53_device *dev = ds->priv;
a2482d2c 1369 struct b53_vlan *vl = &dev->vlans[0];
48aea33a 1370 s8 cpu_port = ds->dst->cpu_port;
ff39c2d6 1371 unsigned int i;
a2482d2c 1372 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1373
1374 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1375
1376 b53_for_each_port(dev, i) {
1377 /* Don't touch the remaining ports */
ddd3a0c8 1378 if (ds->ports[i].bridge_dev != br)
ff39c2d6
FF		 1379 continue;
1380
1381 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1382 reg &= ~BIT(port);
1383 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1384 dev->ports[port].vlan_ctl_mask = reg;
1385
1386 /* Prevent self removal to preserve isolation */
1387 if (port != i)
1388 pvlan &= ~BIT(i);
1389 }
1390
1391 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1392 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1393
1394 if (is5325(dev) || is5365(dev))
1395 pvid = 1;
1396 else
1397 pvid = 0;
1398
48aea33a
FF		 1399 /* Make this port join all VLANs without VLAN entries */
1400 if (is58xx(dev)) {
1401 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1402 reg |= BIT(port);
1403 if (!(reg & BIT(cpu_port)))
1404 reg |= BIT(cpu_port);
1405 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1406 } else {
1407 b53_get_vlan_entry(dev, pvid, vl);
1408 vl->members |= BIT(port) | BIT(dev->cpu_port);
1409 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1410 b53_set_vlan_entry(dev, pvid, vl);
1411 }
ff39c2d6 1412}
3117455d 1413EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1414
3117455d 1415void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1416{
04bed143 1417 struct b53_device *dev = ds->priv;
597698f1 1418 u8 hw_state;
ff39c2d6
FF		 1419 u8 reg;
1420
ff39c2d6
FF		 1421 switch (state) {
1422 case BR_STATE_DISABLED:
1423 hw_state = PORT_CTRL_DIS_STATE;
1424 break;
1425 case BR_STATE_LISTENING:
1426 hw_state = PORT_CTRL_LISTEN_STATE;
1427 break;
1428 case BR_STATE_LEARNING:
1429 hw_state = PORT_CTRL_LEARN_STATE;
1430 break;
1431 case BR_STATE_FORWARDING:
1432 hw_state = PORT_CTRL_FWD_STATE;
1433 break;
1434 case BR_STATE_BLOCKING:
1435 hw_state = PORT_CTRL_BLOCK_STATE;
1436 break;
1437 default:
1438 dev_err(ds->dev, "invalid STP state: %d\n", state);
1439 return;
1440 }
1441
ff39c2d6
FF		 1442 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1443 reg &= ~PORT_CTRL_STP_STATE_MASK;
1444 reg |= hw_state;
1445 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1446}
3117455d 1447EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1448
3117455d 1449void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1450{
1451 struct b53_device *dev = ds->priv;
1452
1453 if (b53_fast_age_port(dev, port))
1454 dev_err(ds->dev, "fast ageing failed\n");
1455}
3117455d 1456EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1457
7b314362
AL		 1458static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1459{
1460 return DSA_TAG_PROTO_NONE;
1461}
1462
ed3af5fd
FF		 1463int b53_mirror_add(struct dsa_switch *ds, int port,
1464 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1465{
1466 struct b53_device *dev = ds->priv;
1467 u16 reg, loc;
1468
1469 if (ingress)
1470 loc = B53_IG_MIR_CTL;
1471 else
1472 loc = B53_EG_MIR_CTL;
1473
1474 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1475 reg &= ~MIRROR_MASK;
1476 reg |= BIT(port);
1477 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1478
1479 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1480 reg &= ~CAP_PORT_MASK;
1481 reg |= mirror->to_local_port;
1482 reg |= MIRROR_EN;
1483 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1484
1485 return 0;
1486}
1487EXPORT_SYMBOL(b53_mirror_add);
1488
1489void b53_mirror_del(struct dsa_switch *ds, int port,
1490 struct dsa_mall_mirror_tc_entry *mirror)
1491{
1492 struct b53_device *dev = ds->priv;
1493 bool loc_disable = false, other_loc_disable = false;
1494 u16 reg, loc;
1495
1496 if (mirror->ingress)
1497 loc = B53_IG_MIR_CTL;
1498 else
1499 loc = B53_EG_MIR_CTL;
1500
1501 /* Update the desired ingress/egress register */
1502 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1503 reg &= ~BIT(port);
1504 if (!(reg & MIRROR_MASK))
1505 loc_disable = true;
1506 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1507
1508 /* Now look at the other one to know if we can disable mirroring
1509 * entirely
1510 */
1511 if (mirror->ingress)
1512 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1513 else
1514 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1515 if (!(reg & MIRROR_MASK))
1516 other_loc_disable = true;
1517
1518 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1519 /* Both no longer have ports, let's disable mirroring */
1520 if (loc_disable && other_loc_disable) {
1521 reg &= ~MIRROR_EN;
1522 reg &= ~mirror->to_local_port;
1523 }
1524 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1525}
1526EXPORT_SYMBOL(b53_mirror_del);
1527
a82f67af 1528static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1529 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1530 .setup = b53_setup,
967dd82f
FF		 1531 .get_strings = b53_get_strings,
1532 .get_ethtool_stats = b53_get_ethtool_stats,
1533 .get_sset_count = b53_get_sset_count,
1534 .phy_read = b53_phy_read16,
1535 .phy_write = b53_phy_write16,
1536 .adjust_link = b53_adjust_link,
1537 .port_enable = b53_enable_port,
1538 .port_disable = b53_disable_port,
ff39c2d6
FF		 1539 .port_bridge_join = b53_br_join,
1540 .port_bridge_leave = b53_br_leave,
1541 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1542 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1543 .port_vlan_filtering = b53_vlan_filtering,
1544 .port_vlan_prepare = b53_vlan_prepare,
1545 .port_vlan_add = b53_vlan_add,
1546 .port_vlan_del = b53_vlan_del,
1547 .port_vlan_dump = b53_vlan_dump,
1da6df85
FF		 1548 .port_fdb_prepare = b53_fdb_prepare,
1549 .port_fdb_dump = b53_fdb_dump,
1550 .port_fdb_add = b53_fdb_add,
1551 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1552 .port_mirror_add = b53_mirror_add,
1553 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1554};
1555
1556struct b53_chip_data {
1557 u32 chip_id;
1558 const char *dev_name;
1559 u16 vlans;
1560 u16 enabled_ports;
1561 u8 cpu_port;
1562 u8 vta_regs[3];
1da6df85 1563 u8 arl_entries;
967dd82f
FF		 1564 u8 duplex_reg;
1565 u8 jumbo_pm_reg;
1566 u8 jumbo_size_reg;
1567};
1568
1569#define B53_VTA_REGS \
1570 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1571#define B53_VTA_REGS_9798 \
1572 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1573#define B53_VTA_REGS_63XX \
1574 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1575
1576static const struct b53_chip_data b53_switch_chips[] = {
1577 {
1578 .chip_id = BCM5325_DEVICE_ID,
1579 .dev_name = "BCM5325",
1580 .vlans = 16,
1581 .enabled_ports = 0x1f,
1da6df85 1582 .arl_entries = 2,
967dd82f
FF		 1583 .cpu_port = B53_CPU_PORT_25,
1584 .duplex_reg = B53_DUPLEX_STAT_FE,
1585 },
1586 {
1587 .chip_id = BCM5365_DEVICE_ID,
1588 .dev_name = "BCM5365",
1589 .vlans = 256,
1590 .enabled_ports = 0x1f,
1da6df85 1591 .arl_entries = 2,
967dd82f
FF		 1592 .cpu_port = B53_CPU_PORT_25,
1593 .duplex_reg = B53_DUPLEX_STAT_FE,
1594 },
1595 {
1596 .chip_id = BCM5395_DEVICE_ID,
1597 .dev_name = "BCM5395",
1598 .vlans = 4096,
1599 .enabled_ports = 0x1f,
1da6df85 1600 .arl_entries = 4,
967dd82f
FF		 1601 .cpu_port = B53_CPU_PORT,
1602 .vta_regs = B53_VTA_REGS,
1603 .duplex_reg = B53_DUPLEX_STAT_GE,
1604 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1605 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1606 },
1607 {
1608 .chip_id = BCM5397_DEVICE_ID,
1609 .dev_name = "BCM5397",
1610 .vlans = 4096,
1611 .enabled_ports = 0x1f,
1da6df85 1612 .arl_entries = 4,
967dd82f
FF		 1613 .cpu_port = B53_CPU_PORT,
1614 .vta_regs = B53_VTA_REGS_9798,
1615 .duplex_reg = B53_DUPLEX_STAT_GE,
1616 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1617 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1618 },
1619 {
1620 .chip_id = BCM5398_DEVICE_ID,
1621 .dev_name = "BCM5398",
1622 .vlans = 4096,
1623 .enabled_ports = 0x7f,
1da6df85 1624 .arl_entries = 4,
967dd82f
FF		 1625 .cpu_port = B53_CPU_PORT,
1626 .vta_regs = B53_VTA_REGS_9798,
1627 .duplex_reg = B53_DUPLEX_STAT_GE,
1628 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1629 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1630 },
1631 {
1632 .chip_id = BCM53115_DEVICE_ID,
1633 .dev_name = "BCM53115",
1634 .vlans = 4096,
1635 .enabled_ports = 0x1f,
1da6df85 1636 .arl_entries = 4,
967dd82f
FF		 1637 .vta_regs = B53_VTA_REGS,
1638 .cpu_port = B53_CPU_PORT,
1639 .duplex_reg = B53_DUPLEX_STAT_GE,
1640 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1641 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1642 },
1643 {
1644 .chip_id = BCM53125_DEVICE_ID,
1645 .dev_name = "BCM53125",
1646 .vlans = 4096,
1647 .enabled_ports = 0xff,
1648 .cpu_port = B53_CPU_PORT,
1649 .vta_regs = B53_VTA_REGS,
1650 .duplex_reg = B53_DUPLEX_STAT_GE,
1651 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1652 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1653 },
1654 {
1655 .chip_id = BCM53128_DEVICE_ID,
1656 .dev_name = "BCM53128",
1657 .vlans = 4096,
1658 .enabled_ports = 0x1ff,
1da6df85 1659 .arl_entries = 4,
967dd82f
FF		 1660 .cpu_port = B53_CPU_PORT,
1661 .vta_regs = B53_VTA_REGS,
1662 .duplex_reg = B53_DUPLEX_STAT_GE,
1663 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1664 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1665 },
1666 {
1667 .chip_id = BCM63XX_DEVICE_ID,
1668 .dev_name = "BCM63xx",
1669 .vlans = 4096,
1670 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1671 .arl_entries = 4,
967dd82f
FF		 1672 .cpu_port = B53_CPU_PORT,
1673 .vta_regs = B53_VTA_REGS_63XX,
1674 .duplex_reg = B53_DUPLEX_STAT_63XX,
1675 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1676 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1677 },
1678 {
1679 .chip_id = BCM53010_DEVICE_ID,
1680 .dev_name = "BCM53010",
1681 .vlans = 4096,
1682 .enabled_ports = 0x1f,
1da6df85 1683 .arl_entries = 4,
967dd82f
FF		 1684 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1685 .vta_regs = B53_VTA_REGS,
1686 .duplex_reg = B53_DUPLEX_STAT_GE,
1687 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1688 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1689 },
1690 {
1691 .chip_id = BCM53011_DEVICE_ID,
1692 .dev_name = "BCM53011",
1693 .vlans = 4096,
1694 .enabled_ports = 0x1bf,
1da6df85 1695 .arl_entries = 4,
967dd82f
FF		 1696 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1697 .vta_regs = B53_VTA_REGS,
1698 .duplex_reg = B53_DUPLEX_STAT_GE,
1699 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1700 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1701 },
1702 {
1703 .chip_id = BCM53012_DEVICE_ID,
1704 .dev_name = "BCM53012",
1705 .vlans = 4096,
1706 .enabled_ports = 0x1bf,
1da6df85 1707 .arl_entries = 4,
967dd82f
FF		 1708 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1709 .vta_regs = B53_VTA_REGS,
1710 .duplex_reg = B53_DUPLEX_STAT_GE,
1711 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1712 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1713 },
1714 {
1715 .chip_id = BCM53018_DEVICE_ID,
1716 .dev_name = "BCM53018",
1717 .vlans = 4096,
1718 .enabled_ports = 0x1f,
1da6df85 1719 .arl_entries = 4,
967dd82f
FF		 1720 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1721 .vta_regs = B53_VTA_REGS,
1722 .duplex_reg = B53_DUPLEX_STAT_GE,
1723 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1724 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1725 },
1726 {
1727 .chip_id = BCM53019_DEVICE_ID,
1728 .dev_name = "BCM53019",
1729 .vlans = 4096,
1730 .enabled_ports = 0x1f,
1da6df85 1731 .arl_entries = 4,
967dd82f
FF		 1732 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1733 .vta_regs = B53_VTA_REGS,
1734 .duplex_reg = B53_DUPLEX_STAT_GE,
1735 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1736 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1737 },
991a36bb
FF		 1738 {
1739 .chip_id = BCM58XX_DEVICE_ID,
1740 .dev_name = "BCM585xx/586xx/88312",
1741 .vlans = 4096,
1742 .enabled_ports = 0x1ff,
1743 .arl_entries = 4,
1744 .cpu_port = B53_CPU_PORT_25,
1745 .vta_regs = B53_VTA_REGS,
1746 .duplex_reg = B53_DUPLEX_STAT_GE,
1747 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1748 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1749 },
130401d9
FF		 1750 {
1751 .chip_id = BCM7445_DEVICE_ID,
1752 .dev_name = "BCM7445",
1753 .vlans = 4096,
1754 .enabled_ports = 0x1ff,
1755 .arl_entries = 4,
1756 .cpu_port = B53_CPU_PORT,
1757 .vta_regs = B53_VTA_REGS,
1758 .duplex_reg = B53_DUPLEX_STAT_GE,
1759 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1760 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1761 },
0fe99338
FF		 1762 {
1763 .chip_id = BCM7278_DEVICE_ID,
1764 .dev_name = "BCM7278",
1765 .vlans = 4096,
1766 .enabled_ports = 0x1ff,
1767 .arl_entries= 4,
1768 .cpu_port = B53_CPU_PORT,
1769 .vta_regs = B53_VTA_REGS,
1770 .duplex_reg = B53_DUPLEX_STAT_GE,
1771 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1772 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1773 },
967dd82f
FF		 1774};
1775
1776static int b53_switch_init(struct b53_device *dev)
1777{
967dd82f
FF		 1778 unsigned int i;
1779 int ret;
1780
1781 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1782 const struct b53_chip_data *chip = &b53_switch_chips[i];
1783
1784 if (chip->chip_id == dev->chip_id) {
1785 if (!dev->enabled_ports)
1786 dev->enabled_ports = chip->enabled_ports;
1787 dev->name = chip->dev_name;
1788 dev->duplex_reg = chip->duplex_reg;
1789 dev->vta_regs[0] = chip->vta_regs[0];
1790 dev->vta_regs[1] = chip->vta_regs[1];
1791 dev->vta_regs[2] = chip->vta_regs[2];
1792 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1793 dev->cpu_port = chip->cpu_port;
1794 dev->num_vlans = chip->vlans;
1da6df85 1795 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1796 break;
1797 }
1798 }
1799
1800 /* check which BCM5325x version we have */
1801 if (is5325(dev)) {
1802 u8 vc4;
1803
1804 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1805
1806 /* check reserved bits */
1807 switch (vc4 & 3) {
1808 case 1:
1809 /* BCM5325E */
1810 break;
1811 case 3:
1812 /* BCM5325F - do not use port 4 */
1813 dev->enabled_ports &= ~BIT(4);
1814 break;
1815 default:
1816/* On the BCM47XX SoCs this is the supported internal switch.*/
1817#ifndef CONFIG_BCM47XX
1818 /* BCM5325M */
1819 return -EINVAL;
1820#else
1821 break;
1822#endif
1823 }
1824 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1825 u64 strap_value;
1826
1827 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1828 /* use second IMP port if GMII is enabled */
1829 if (strap_value & SV_GMII_CTRL_115)
1830 dev->cpu_port = 5;
1831 }
1832
1833 /* cpu port is always last */
1834 dev->num_ports = dev->cpu_port + 1;
1835 dev->enabled_ports |= BIT(dev->cpu_port);
1836
1837 dev->ports = devm_kzalloc(dev->dev,
1838 sizeof(struct b53_port) * dev->num_ports,
1839 GFP_KERNEL);
1840 if (!dev->ports)
1841 return -ENOMEM;
1842
a2482d2c
FF		 1843 dev->vlans = devm_kzalloc(dev->dev,
1844 sizeof(struct b53_vlan) * dev->num_vlans,
1845 GFP_KERNEL);
1846 if (!dev->vlans)
1847 return -ENOMEM;
1848
967dd82f
FF		 1849 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1850 if (dev->reset_gpio >= 0) {
1851 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1852 GPIOF_OUT_INIT_HIGH, "robo_reset");
1853 if (ret)
1854 return ret;
1855 }
1856
1857 return 0;
1858}
1859
0dff88d3
JL		 1860struct b53_device *b53_switch_alloc(struct device *base,
1861 const struct b53_io_ops *ops,
967dd82f
FF		 1862 void *priv)
1863{
1864 struct dsa_switch *ds;
1865 struct b53_device *dev;
1866
a0c02161 1867 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 1868 if (!ds)
1869 return NULL;
1870
a0c02161
VD		 1871 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1872 if (!dev)
1873 return NULL;
967dd82f
FF		 1874
1875 ds->priv = dev;
967dd82f
FF		 1876 dev->dev = base;
1877
1878 dev->ds = ds;
1879 dev->priv = priv;
1880 dev->ops = ops;
485ebd61 1881 ds->ops = &b53_switch_ops;
967dd82f
FF		 1882 mutex_init(&dev->reg_mutex);
1883 mutex_init(&dev->stats_mutex);
1884
1885 return dev;
1886}
1887EXPORT_SYMBOL(b53_switch_alloc);
1888
1889int b53_switch_detect(struct b53_device *dev)
1890{
1891 u32 id32;
1892 u16 tmp;
1893 u8 id8;
1894 int ret;
1895
1896 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1897 if (ret)
1898 return ret;
1899
1900 switch (id8) {
1901 case 0:
1902 /* BCM5325 and BCM5365 do not have this register so reads
1903 * return 0. But the read operation did succeed, so assume this
1904 * is one of them.
1905 *
1906 * Next check if we can write to the 5325's VTA register; for
1907 * 5365 it is read only.
1908 */
1909 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1910 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1911
1912 if (tmp == 0xf)
1913 dev->chip_id = BCM5325_DEVICE_ID;
1914 else
1915 dev->chip_id = BCM5365_DEVICE_ID;
1916 break;
1917 case BCM5395_DEVICE_ID:
1918 case BCM5397_DEVICE_ID:
1919 case BCM5398_DEVICE_ID:
1920 dev->chip_id = id8;
1921 break;
1922 default:
1923 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1924 if (ret)
1925 return ret;
1926
1927 switch (id32) {
1928 case BCM53115_DEVICE_ID:
1929 case BCM53125_DEVICE_ID:
1930 case BCM53128_DEVICE_ID:
1931 case BCM53010_DEVICE_ID:
1932 case BCM53011_DEVICE_ID:
1933 case BCM53012_DEVICE_ID:
1934 case BCM53018_DEVICE_ID:
1935 case BCM53019_DEVICE_ID:
1936 dev->chip_id = id32;
1937 break;
1938 default:
1939 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1940 id8, id32);
1941 return -ENODEV;
1942 }
1943 }
1944
1945 if (dev->chip_id == BCM5325_DEVICE_ID)
1946 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1947 &dev->core_rev);
1948 else
1949 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1950 &dev->core_rev);
1951}
1952EXPORT_SYMBOL(b53_switch_detect);
1953
1954int b53_switch_register(struct b53_device *dev)
1955{
1956 int ret;
1957
1958 if (dev->pdata) {
1959 dev->chip_id = dev->pdata->chip_id;
1960 dev->enabled_ports = dev->pdata->enabled_ports;
1961 }
1962
1963 if (!dev->chip_id && b53_switch_detect(dev))
1964 return -EINVAL;
1965
1966 ret = b53_switch_init(dev);
1967 if (ret)
1968 return ret;
1969
1970 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1971
55ed0ce0 1972 return dsa_register_switch(dev->ds, dev->ds->dev);
967dd82f
FF		 1973}
1974EXPORT_SYMBOL(b53_switch_register);
1975
1976MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1977MODULE_DESCRIPTION("B53 switch library");
1978MODULE_LICENSE("Dual BSD/GPL");
ubuntu-bionic-kernel mirror