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net: dsa: b53: Stop using dev->cpu_port incorrectly
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f
FF		 31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
bde5d132
FF		 169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
967dd82f
FF		 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
a2482d2c
FF		 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
967dd82f
FF		 249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
a2482d2c
FF		 253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
a2482d2c
FF		 268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
a2482d2c
FF		 282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
967dd82f
FF		 324}
325
a2482d2c 326static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f 327{
a424f0de 328 struct dsa_switch *ds = dev->ds;
967dd82f
FF		 329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de
FF		 339
340 /* Include IMP port in dumb forwarding mode when no tagging protocol is
341 * set
342 */
343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
347 }
967dd82f
FF		 348}
349
a2482d2c 350static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 351{
352 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
353
354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
357
358 if (is5325(dev) || is5365(dev)) {
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
361 } else if (is63xx(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
364 } else {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
367 }
368
369 mgmt &= ~SM_SW_FWD_MODE;
370
371 if (enable) {
372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
374 vc4 &= ~VC4_ING_VID_CHECK_MASK;
375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
376 vc5 |= VC5_DROP_VTABLE_MISS;
377
378 if (is5325(dev))
379 vc0 &= ~VC0_RESERVED_1;
380
381 if (is5325(dev) || is5365(dev))
382 vc1 |= VC1_RX_MCST_TAG_EN;
383
967dd82f
FF		 384 } else {
385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
387 vc4 &= ~VC4_ING_VID_CHECK_MASK;
388 vc5 &= ~VC5_DROP_VTABLE_MISS;
389
390 if (is5325(dev) || is5365(dev))
391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
392 else
393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
394
395 if (is5325(dev) || is5365(dev))
396 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 397 }
398
a2482d2c
FF		 399 if (!is5325(dev) && !is5365(dev))
400 vc5 &= ~VC5_VID_FFF_EN;
401
967dd82f
FF		 402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
404
405 if (is5325(dev) || is5365(dev)) {
406 /* enable the high 8 bit vid check on 5325 */
407 if (is5325(dev) && enable)
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
409 VC3_HIGH_8BIT_EN);
410 else
411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
412
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
415 } else if (is63xx(dev)) {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
419 } else {
420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
423 }
424
425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
426}
427
428static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
429{
430 u32 port_mask = 0;
431 u16 max_size = JMS_MIN_SIZE;
432
433 if (is5325(dev) || is5365(dev))
434 return -EINVAL;
435
436 if (enable) {
437 port_mask = dev->enabled_ports;
438 max_size = JMS_MAX_SIZE;
439 if (allow_10_100)
440 port_mask |= JPM_10_100_JUMBO_EN;
441 }
442
443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
445}
446
ff39c2d6 447static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 448{
449 unsigned int i;
450
451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 453
454 for (i = 0; i < 10; i++) {
455 u8 fast_age_ctrl;
456
457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
458 &fast_age_ctrl);
459
460 if (!(fast_age_ctrl & FAST_AGE_DONE))
461 goto out;
462
463 msleep(1);
464 }
465
466 return -ETIMEDOUT;
467out:
468 /* Only age dynamic entries (default behavior) */
469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
470 return 0;
471}
472
ff39c2d6
FF		 473static int b53_fast_age_port(struct b53_device *dev, int port)
474{
475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
476
477 return b53_flush_arl(dev, FAST_AGE_PORT);
478}
479
a2482d2c
FF		 480static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
481{
482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
483
484 return b53_flush_arl(dev, FAST_AGE_VLAN);
485}
486
aac02867 487void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 488{
04bed143 489 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 490 unsigned int i;
491 u16 pvlan;
492
493 /* Enable the IMP port to be in the same VLAN as the other ports
494 * on a per-port basis such that we only have Port i and IMP in
495 * the same VLAN.
496 */
497 b53_for_each_port(dev, i) {
498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
499 pvlan |= BIT(cpu_port);
500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
501 }
502}
aac02867 503EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 504
f86ad77f 505int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 506{
04bed143 507 struct b53_device *dev = ds->priv;
c499696e 508 unsigned int cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 509 u16 pvlan;
967dd82f
FF		 510
511 /* Clear the Rx and Tx disable bits and set to no spanning tree */
512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
513
ff39c2d6
FF		 514 /* Set this port, and only this one to be in the default VLAN,
515 * if member of a bridge, restore its membership prior to
516 * bringing down this port.
517 */
518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
519 pvlan &= ~0x1ff;
520 pvlan |= BIT(port);
521 pvlan |= dev->ports[port].vlan_ctl_mask;
522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
523
524 b53_imp_vlan_setup(ds, cpu_port);
525
f43a2dbe
FF		 526 /* If EEE was enabled, restore it */
527 if (dev->ports[port].eee.eee_enabled)
528 b53_eee_enable_set(ds, port, true);
529
967dd82f
FF		 530 return 0;
531}
f86ad77f 532EXPORT_SYMBOL(b53_enable_port);
967dd82f 533
f86ad77f 534void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 535{
04bed143 536 struct b53_device *dev = ds->priv;
967dd82f
FF		 537 u8 reg;
538
539 /* Disable Tx/Rx for the port */
540 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
541 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
542 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
543}
f86ad77f 544EXPORT_SYMBOL(b53_disable_port);
967dd82f 545
b409a9ef
FF		 546void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
547{
cdb583cf 548 bool tag_en = !!(ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_BRCM);
b409a9ef
FF		 549 struct b53_device *dev = ds->priv;
550 u8 hdr_ctl, val;
551 u16 reg;
552
553 /* Resolve which bit controls the Broadcom tag */
554 switch (port) {
555 case 8:
556 val = BRCM_HDR_P8_EN;
557 break;
558 case 7:
559 val = BRCM_HDR_P7_EN;
560 break;
561 case 5:
562 val = BRCM_HDR_P5_EN;
563 break;
564 default:
565 val = 0;
566 break;
567 }
568
569 /* Enable Broadcom tags for IMP port */
570 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
cdb583cf
FF		 571 if (tag_en)
572 hdr_ctl |= val;
573 else
574 hdr_ctl &= ~val;
b409a9ef
FF		 575 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
576
577 /* Registers below are only accessible on newer devices */
578 if (!is58xx(dev))
579 return;
580
581 /* Enable reception Broadcom tag for CPU TX (switch RX) to
582 * allow us to tag outgoing frames
583 */
584 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
cdb583cf
FF		 585 if (tag_en)
586 reg &= ~BIT(port);
587 else
588 reg |= BIT(port);
b409a9ef
FF		 589 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
590
591 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
592 * allow delivering frames to the per-port net_devices
593 */
594 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
cdb583cf
FF		 595 if (tag_en)
596 reg &= ~BIT(port);
597 else
598 reg |= BIT(port);
b409a9ef
FF		 599 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
600}
601EXPORT_SYMBOL(b53_brcm_hdr_setup);
602
299752a7 603static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 604{
967dd82f
FF		 605 u8 port_ctrl;
606
607 /* BCM5325 CPU port is at 8 */
299752a7
FF		 608 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
609 port = B53_CPU_PORT;
967dd82f
FF		 610
611 port_ctrl = PORT_CTRL_RX_BCST_EN |
612 PORT_CTRL_RX_MCST_EN |
613 PORT_CTRL_RX_UCST_EN;
299752a7 614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
967dd82f
FF		 615}
616
617static void b53_enable_mib(struct b53_device *dev)
618{
619 u8 gc;
620
621 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
622 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
623 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
624}
625
5c1a6eaf 626int b53_configure_vlan(struct dsa_switch *ds)
967dd82f 627{
5c1a6eaf 628 struct b53_device *dev = ds->priv;
a2482d2c 629 struct b53_vlan vl = { 0 };
967dd82f
FF		 630 int i;
631
632 /* clear all vlan entries */
633 if (is5325(dev) || is5365(dev)) {
634 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 635 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 636 } else {
637 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
638 }
639
640 b53_enable_vlan(dev, false);
641
642 b53_for_each_port(dev, i)
643 b53_write16(dev, B53_VLAN_PAGE,
644 B53_VLAN_PORT_DEF_TAG(i), 1);
645
646 if (!is5325(dev) && !is5365(dev))
647 b53_set_jumbo(dev, dev->enable_jumbo, false);
648
649 return 0;
650}
5c1a6eaf 651EXPORT_SYMBOL(b53_configure_vlan);
967dd82f
FF		 652
653static void b53_switch_reset_gpio(struct b53_device *dev)
654{
655 int gpio = dev->reset_gpio;
656
657 if (gpio < 0)
658 return;
659
660 /* Reset sequence: RESET low(50ms)->high(20ms)
661 */
662 gpio_set_value(gpio, 0);
663 mdelay(50);
664
665 gpio_set_value(gpio, 1);
666 mdelay(20);
667
668 dev->current_page = 0xff;
669}
670
671static int b53_switch_reset(struct b53_device *dev)
672{
3fb22b05
FF		 673 unsigned int timeout = 1000;
674 u8 mgmt, reg;
967dd82f
FF		 675
676 b53_switch_reset_gpio(dev);
677
678 if (is539x(dev)) {
679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
680 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
681 }
682
3fb22b05
FF		 683 /* This is specific to 58xx devices here, do not use is58xx() which
684 * covers the larger Starfigther 2 family, including 7445/7278 which
685 * still use this driver as a library and need to perform the reset
686 * earlier.
687 */
688 if (dev->chip_id == BCM58XX_DEVICE_ID) {
689 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
690 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
691 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
692
693 do {
694 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
695 if (!(reg & SW_RST))
696 break;
697
698 usleep_range(1000, 2000);
699 } while (timeout-- > 0);
700
701 if (timeout == 0)
702 return -ETIMEDOUT;
703 }
704
967dd82f
FF		 705 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
706
707 if (!(mgmt & SM_SW_FWD_EN)) {
708 mgmt &= ~SM_SW_FWD_MODE;
709 mgmt |= SM_SW_FWD_EN;
710
711 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
712 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
713
714 if (!(mgmt & SM_SW_FWD_EN)) {
715 dev_err(dev->dev, "Failed to enable switch!\n");
716 return -EINVAL;
717 }
718 }
719
720 b53_enable_mib(dev);
721
ff39c2d6 722 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 723}
724
725static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
726{
04bed143 727 struct b53_device *priv = ds->priv;
967dd82f
FF		 728 u16 value = 0;
729 int ret;
730
731 if (priv->ops->phy_read16)
732 ret = priv->ops->phy_read16(priv, addr, reg, &value);
733 else
734 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
735 reg * 2, &value);
736
737 return ret ? ret : value;
738}
739
740static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
741{
04bed143 742 struct b53_device *priv = ds->priv;
967dd82f
FF		 743
744 if (priv->ops->phy_write16)
745 return priv->ops->phy_write16(priv, addr, reg, val);
746
747 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
748}
749
750static int b53_reset_switch(struct b53_device *priv)
751{
752 /* reset vlans */
753 priv->enable_jumbo = false;
754
a2482d2c 755 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 756 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
757
758 return b53_switch_reset(priv);
759}
760
761static int b53_apply_config(struct b53_device *priv)
762{
763 /* disable switching */
764 b53_set_forwarding(priv, 0);
765
5c1a6eaf 766 b53_configure_vlan(priv->ds);
967dd82f
FF		 767
768 /* enable switching */
769 b53_set_forwarding(priv, 1);
770
771 return 0;
772}
773
774static void b53_reset_mib(struct b53_device *priv)
775{
776 u8 gc;
777
778 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
779
780 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
781 msleep(1);
782 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
783 msleep(1);
784}
785
786static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
787{
788 if (is5365(dev))
789 return b53_mibs_65;
790 else if (is63xx(dev))
791 return b53_mibs_63xx;
bde5d132
FF		 792 else if (is58xx(dev))
793 return b53_mibs_58xx;
967dd82f
FF		 794 else
795 return b53_mibs;
796}
797
798static unsigned int b53_get_mib_size(struct b53_device *dev)
799{
800 if (is5365(dev))
801 return B53_MIBS_65_SIZE;
802 else if (is63xx(dev))
803 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 804 else if (is58xx(dev))
805 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 806 else
807 return B53_MIBS_SIZE;
808}
809
3117455d 810void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
967dd82f 811{
04bed143 812 struct b53_device *dev = ds->priv;
967dd82f
FF		 813 const struct b53_mib_desc *mibs = b53_get_mib(dev);
814 unsigned int mib_size = b53_get_mib_size(dev);
815 unsigned int i;
816
817 for (i = 0; i < mib_size; i++)
818 memcpy(data + i * ETH_GSTRING_LEN,
819 mibs[i].name, ETH_GSTRING_LEN);
820}
3117455d 821EXPORT_SYMBOL(b53_get_strings);
967dd82f 822
3117455d 823void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 824{
04bed143 825 struct b53_device *dev = ds->priv;
967dd82f
FF		 826 const struct b53_mib_desc *mibs = b53_get_mib(dev);
827 unsigned int mib_size = b53_get_mib_size(dev);
828 const struct b53_mib_desc *s;
829 unsigned int i;
830 u64 val = 0;
831
832 if (is5365(dev) && port == 5)
833 port = 8;
834
835 mutex_lock(&dev->stats_mutex);
836
837 for (i = 0; i < mib_size; i++) {
838 s = &mibs[i];
839
51dca8a1 840 if (s->size == 8) {
967dd82f
FF		 841 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
842 } else {
843 u32 val32;
844
845 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
846 &val32);
847 val = val32;
848 }
849 data[i] = (u64)val;
850 }
851
852 mutex_unlock(&dev->stats_mutex);
853}
3117455d 854EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 855
3117455d 856int b53_get_sset_count(struct dsa_switch *ds)
967dd82f 857{
04bed143 858 struct b53_device *dev = ds->priv;
967dd82f
FF		 859
860 return b53_get_mib_size(dev);
861}
3117455d 862EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 863
967dd82f
FF		 864static int b53_setup(struct dsa_switch *ds)
865{
04bed143 866 struct b53_device *dev = ds->priv;
967dd82f
FF		 867 unsigned int port;
868 int ret;
869
870 ret = b53_reset_switch(dev);
871 if (ret) {
872 dev_err(ds->dev, "failed to reset switch\n");
873 return ret;
874 }
875
876 b53_reset_mib(dev);
877
878 ret = b53_apply_config(dev);
879 if (ret)
880 dev_err(ds->dev, "failed to apply configuration\n");
881
34c8befd
FF		 882 /* Configure IMP/CPU port, disable unused ports. Enabled
883 * ports will be configured with .port_enable
884 */
967dd82f 885 for (port = 0; port < dev->num_ports; port++) {
34c8befd 886 if (dsa_is_cpu_port(ds, port))
299752a7 887 b53_enable_cpu_port(dev, port);
bff7b688 888 else if (dsa_is_unused_port(ds, port))
967dd82f
FF		 889 b53_disable_port(ds, port, NULL);
890 }
891
892 return ret;
893}
894
895static void b53_adjust_link(struct dsa_switch *ds, int port,
896 struct phy_device *phydev)
897{
04bed143 898 struct b53_device *dev = ds->priv;
f43a2dbe 899 struct ethtool_eee *p = &dev->ports[port].eee;
967dd82f
FF		 900 u8 rgmii_ctrl = 0, reg = 0, off;
901
902 if (!phy_is_pseudo_fixed_link(phydev))
903 return;
904
905 /* Override the port settings */
906 if (port == dev->cpu_port) {
907 off = B53_PORT_OVERRIDE_CTRL;
908 reg = PORT_OVERRIDE_EN;
909 } else {
910 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
911 reg = GMII_PO_EN;
912 }
913
914 /* Set the link UP */
915 if (phydev->link)
916 reg |= PORT_OVERRIDE_LINK;
917
918 if (phydev->duplex == DUPLEX_FULL)
919 reg |= PORT_OVERRIDE_FULL_DUPLEX;
920
921 switch (phydev->speed) {
922 case 2000:
923 reg |= PORT_OVERRIDE_SPEED_2000M;
924 /* fallthrough */
925 case SPEED_1000:
926 reg |= PORT_OVERRIDE_SPEED_1000M;
927 break;
928 case SPEED_100:
929 reg |= PORT_OVERRIDE_SPEED_100M;
930 break;
931 case SPEED_10:
932 reg |= PORT_OVERRIDE_SPEED_10M;
933 break;
934 default:
935 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
936 return;
937 }
938
939 /* Enable flow control on BCM5301x's CPU port */
940 if (is5301x(dev) && port == dev->cpu_port)
941 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
942
943 if (phydev->pause) {
944 if (phydev->asym_pause)
945 reg |= PORT_OVERRIDE_TX_FLOW;
946 reg |= PORT_OVERRIDE_RX_FLOW;
947 }
948
949 b53_write8(dev, B53_CTRL_PAGE, off, reg);
950
951 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
952 if (port == 8)
953 off = B53_RGMII_CTRL_IMP;
954 else
955 off = B53_RGMII_CTRL_P(port);
956
957 /* Configure the port RGMII clock delay by DLL disabled and
958 * tx_clk aligned timing (restoring to reset defaults)
959 */
960 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
961 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
962 RGMII_CTRL_TIMING_SEL);
963
964 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
965 * sure that we enable the port TX clock internal delay to
966 * account for this internal delay that is inserted, otherwise
967 * the switch won't be able to receive correctly.
968 *
969 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
970 * any delay neither on transmission nor reception, so the
971 * BCM53125 must also be configured accordingly to account for
972 * the lack of delay and introduce
973 *
974 * The BCM53125 switch has its RX clock and TX clock control
975 * swapped, hence the reason why we modify the TX clock path in
976 * the "RGMII" case
977 */
978 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
979 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
980 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
981 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
982 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
983 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
984
985 dev_info(ds->dev, "Configured port %d for %s\n", port,
986 phy_modes(phydev->interface));
987 }
988
989 /* configure MII port if necessary */
990 if (is5325(dev)) {
991 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
992 &reg);
993
994 /* reverse mii needs to be enabled */
995 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
996 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
997 reg | PORT_OVERRIDE_RV_MII_25);
998 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
999 &reg);
1000
1001 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1002 dev_err(ds->dev,
1003 "Failed to enable reverse MII mode\n");
1004 return;
1005 }
1006 }
1007 } else if (is5301x(dev)) {
1008 if (port != dev->cpu_port) {
1009 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1010 u8 gmii_po;
1011
1012 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1013 gmii_po |= GMII_PO_LINK |
1014 GMII_PO_RX_FLOW |
1015 GMII_PO_TX_FLOW |
1016 GMII_PO_EN |
1017 GMII_PO_SPEED_2000M;
1018 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1019 }
1020 }
f43a2dbe
FF		 1021
1022 /* Re-negotiate EEE if it was enabled already */
1023 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1024}
1025
3117455d 1026int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 1027{
1028 return 0;
1029}
3117455d 1030EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1031
3117455d
FF		 1032int b53_vlan_prepare(struct dsa_switch *ds, int port,
1033 const struct switchdev_obj_port_vlan *vlan,
1034 struct switchdev_trans *trans)
a2482d2c 1035{
04bed143 1036 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1037
1038 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1039 return -EOPNOTSUPP;
1040
1041 if (vlan->vid_end > dev->num_vlans)
1042 return -ERANGE;
1043
1044 b53_enable_vlan(dev, true);
1045
1046 return 0;
1047}
3117455d 1048EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 1049
3117455d
FF		 1050void b53_vlan_add(struct dsa_switch *ds, int port,
1051 const struct switchdev_obj_port_vlan *vlan,
1052 struct switchdev_trans *trans)
a2482d2c 1053{
04bed143 1054 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1055 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1056 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
a2482d2c
FF		 1057 struct b53_vlan *vl;
1058 u16 vid;
1059
1060 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1061 vl = &dev->vlans[vid];
1062
1063 b53_get_vlan_entry(dev, vid, vl);
1064
c499696e 1065 vl->members |= BIT(port);
a2482d2c 1066 if (untagged)
e47112d9 1067 vl->untag |= BIT(port);
a2482d2c 1068 else
e47112d9 1069 vl->untag &= ~BIT(port);
a2482d2c
FF		 1070
1071 b53_set_vlan_entry(dev, vid, vl);
1072 b53_fast_age_vlan(dev, vid);
1073 }
1074
1075 if (pvid) {
1076 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1077 vlan->vid_end);
a2482d2c
FF		 1078 b53_fast_age_vlan(dev, vid);
1079 }
1080}
3117455d 1081EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1082
3117455d
FF		 1083int b53_vlan_del(struct dsa_switch *ds, int port,
1084 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1085{
04bed143 1086 struct b53_device *dev = ds->priv;
a2482d2c 1087 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1088 struct b53_vlan *vl;
1089 u16 vid;
1090 u16 pvid;
1091
1092 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1093
1094 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1095 vl = &dev->vlans[vid];
1096
1097 b53_get_vlan_entry(dev, vid, vl);
1098
1099 vl->members &= ~BIT(port);
a2482d2c
FF		 1100
1101 if (pvid == vid) {
1102 if (is5325(dev) || is5365(dev))
1103 pvid = 1;
1104 else
1105 pvid = 0;
1106 }
1107
e47112d9 1108 if (untagged)
a2482d2c 1109 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1110
1111 b53_set_vlan_entry(dev, vid, vl);
1112 b53_fast_age_vlan(dev, vid);
1113 }
1114
1115 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1116 b53_fast_age_vlan(dev, pvid);
1117
1118 return 0;
1119}
3117455d 1120EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1121
1da6df85
FF		 1122/* Address Resolution Logic routines */
1123static int b53_arl_op_wait(struct b53_device *dev)
1124{
1125 unsigned int timeout = 10;
1126 u8 reg;
1127
1128 do {
1129 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1130 if (!(reg & ARLTBL_START_DONE))
1131 return 0;
1132
1133 usleep_range(1000, 2000);
1134 } while (timeout--);
1135
1136 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1137
1138 return -ETIMEDOUT;
1139}
1140
1141static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1142{
1143 u8 reg;
1144
1145 if (op > ARLTBL_RW)
1146 return -EINVAL;
1147
1148 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1149 reg |= ARLTBL_START_DONE;
1150 if (op)
1151 reg |= ARLTBL_RW;
1152 else
1153 reg &= ~ARLTBL_RW;
1154 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1155
1156 return b53_arl_op_wait(dev);
1157}
1158
1159static int b53_arl_read(struct b53_device *dev, u64 mac,
1160 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1161 bool is_valid)
1162{
1163 unsigned int i;
1164 int ret;
1165
1166 ret = b53_arl_op_wait(dev);
1167 if (ret)
1168 return ret;
1169
1170 /* Read the bins */
1171 for (i = 0; i < dev->num_arl_entries; i++) {
1172 u64 mac_vid;
1173 u32 fwd_entry;
1174
1175 b53_read64(dev, B53_ARLIO_PAGE,
1176 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1177 b53_read32(dev, B53_ARLIO_PAGE,
1178 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1179 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1180
1181 if (!(fwd_entry & ARLTBL_VALID))
1182 continue;
1183 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1184 continue;
1185 *idx = i;
1186 }
1187
1188 return -ENOENT;
1189}
1190
1191static int b53_arl_op(struct b53_device *dev, int op, int port,
1192 const unsigned char *addr, u16 vid, bool is_valid)
1193{
1194 struct b53_arl_entry ent;
1195 u32 fwd_entry;
1196 u64 mac, mac_vid = 0;
1197 u8 idx = 0;
1198 int ret;
1199
1200 /* Convert the array into a 64-bit MAC */
4b92ea81 1201 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1202
1203 /* Perform a read for the given MAC and VID */
1204 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1205 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1206
1207 /* Issue a read operation for this MAC */
1208 ret = b53_arl_rw_op(dev, 1);
1209 if (ret)
1210 return ret;
1211
1212 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1213 /* If this is a read, just finish now */
1214 if (op)
1215 return ret;
1216
1217 /* We could not find a matching MAC, so reset to a new entry */
1218 if (ret) {
1219 fwd_entry = 0;
1220 idx = 1;
1221 }
1222
1223 memset(&ent, 0, sizeof(ent));
1224 ent.port = port;
1225 ent.is_valid = is_valid;
1226 ent.vid = vid;
1227 ent.is_static = true;
1228 memcpy(ent.mac, addr, ETH_ALEN);
1229 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1230
1231 b53_write64(dev, B53_ARLIO_PAGE,
1232 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1233 b53_write32(dev, B53_ARLIO_PAGE,
1234 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1235
1236 return b53_arl_rw_op(dev, 0);
1237}
1238
1b6dd556
AS		 1239int b53_fdb_add(struct dsa_switch *ds, int port,
1240 const unsigned char *addr, u16 vid)
1da6df85 1241{
04bed143 1242 struct b53_device *priv = ds->priv;
1da6df85
FF		 1243
1244 /* 5325 and 5365 require some more massaging, but could
1245 * be supported eventually
1246 */
1247 if (is5325(priv) || is5365(priv))
1248 return -EOPNOTSUPP;
1249
1b6dd556 1250 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1251}
3117455d 1252EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1253
3117455d 1254int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1255 const unsigned char *addr, u16 vid)
1da6df85 1256{
04bed143 1257 struct b53_device *priv = ds->priv;
1da6df85 1258
6c2c1dcb 1259 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1260}
3117455d 1261EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1262
1263static int b53_arl_search_wait(struct b53_device *dev)
1264{
1265 unsigned int timeout = 1000;
1266 u8 reg;
1267
1268 do {
1269 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1270 if (!(reg & ARL_SRCH_STDN))
1271 return 0;
1272
1273 if (reg & ARL_SRCH_VLID)
1274 return 0;
1275
1276 usleep_range(1000, 2000);
1277 } while (timeout--);
1278
1279 return -ETIMEDOUT;
1280}
1281
1282static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1283 struct b53_arl_entry *ent)
1284{
1285 u64 mac_vid;
1286 u32 fwd_entry;
1287
1288 b53_read64(dev, B53_ARLIO_PAGE,
1289 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1290 b53_read32(dev, B53_ARLIO_PAGE,
1291 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1292 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1293}
1294
e6cbef0c 1295static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1296 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1297{
1298 if (!ent->is_valid)
1299 return 0;
1300
1301 if (port != ent->port)
1302 return 0;
1303
2bedde1a 1304 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1305}
1306
3117455d 1307int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1308 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1309{
04bed143 1310 struct b53_device *priv = ds->priv;
1da6df85
FF		 1311 struct b53_arl_entry results[2];
1312 unsigned int count = 0;
1313 int ret;
1314 u8 reg;
1315
1316 /* Start search operation */
1317 reg = ARL_SRCH_STDN;
1318 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1319
1320 do {
1321 ret = b53_arl_search_wait(priv);
1322 if (ret)
1323 return ret;
1324
1325 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1326 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1327 if (ret)
1328 return ret;
1329
1330 if (priv->num_arl_entries > 2) {
1331 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1332 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1333 if (ret)
1334 return ret;
1335
1336 if (!results[0].is_valid && !results[1].is_valid)
1337 break;
1338 }
1339
1340 } while (count++ < 1024);
1341
1342 return 0;
1343}
3117455d 1344EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1345
ddd3a0c8 1346int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1347{
04bed143 1348 struct b53_device *dev = ds->priv;
0abfd494 1349 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6
FF		 1350 u16 pvlan, reg;
1351 unsigned int i;
1352
48aea33a
FF		 1353 /* Make this port leave the all VLANs join since we will have proper
1354 * VLAN entries from now on
1355 */
1356 if (is58xx(dev)) {
1357 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1358 reg &= ~BIT(port);
1359 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1360 reg &= ~BIT(cpu_port);
1361 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1362 }
1363
ff39c2d6
FF		 1364 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1365
1366 b53_for_each_port(dev, i) {
c8652c83 1367 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1368 continue;
1369
1370 /* Add this local port to the remote port VLAN control
1371 * membership and update the remote port bitmask
1372 */
1373 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1374 reg |= BIT(port);
1375 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1376 dev->ports[i].vlan_ctl_mask = reg;
1377
1378 pvlan |= BIT(i);
1379 }
1380
1381 /* Configure the local port VLAN control membership to include
1382 * remote ports and update the local port bitmask
1383 */
1384 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1385 dev->ports[port].vlan_ctl_mask = pvlan;
1386
1387 return 0;
1388}
3117455d 1389EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1390
f123f2fb 1391void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1392{
04bed143 1393 struct b53_device *dev = ds->priv;
a2482d2c 1394 struct b53_vlan *vl = &dev->vlans[0];
0abfd494 1395 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 1396 unsigned int i;
a2482d2c 1397 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1398
1399 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1400
1401 b53_for_each_port(dev, i) {
1402 /* Don't touch the remaining ports */
c8652c83 1403 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1404 continue;
1405
1406 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1407 reg &= ~BIT(port);
1408 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1409 dev->ports[port].vlan_ctl_mask = reg;
1410
1411 /* Prevent self removal to preserve isolation */
1412 if (port != i)
1413 pvlan &= ~BIT(i);
1414 }
1415
1416 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1417 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1418
1419 if (is5325(dev) || is5365(dev))
1420 pvid = 1;
1421 else
1422 pvid = 0;
1423
48aea33a
FF		 1424 /* Make this port join all VLANs without VLAN entries */
1425 if (is58xx(dev)) {
1426 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1427 reg |= BIT(port);
1428 if (!(reg & BIT(cpu_port)))
1429 reg |= BIT(cpu_port);
1430 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1431 } else {
1432 b53_get_vlan_entry(dev, pvid, vl);
c499696e
FF		 1433 vl->members |= BIT(port) | BIT(cpu_port);
1434 vl->untag |= BIT(port) | BIT(cpu_port);
48aea33a
FF		 1435 b53_set_vlan_entry(dev, pvid, vl);
1436 }
ff39c2d6 1437}
3117455d 1438EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1439
3117455d 1440void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1441{
04bed143 1442 struct b53_device *dev = ds->priv;
597698f1 1443 u8 hw_state;
ff39c2d6
FF		 1444 u8 reg;
1445
ff39c2d6
FF		 1446 switch (state) {
1447 case BR_STATE_DISABLED:
1448 hw_state = PORT_CTRL_DIS_STATE;
1449 break;
1450 case BR_STATE_LISTENING:
1451 hw_state = PORT_CTRL_LISTEN_STATE;
1452 break;
1453 case BR_STATE_LEARNING:
1454 hw_state = PORT_CTRL_LEARN_STATE;
1455 break;
1456 case BR_STATE_FORWARDING:
1457 hw_state = PORT_CTRL_FWD_STATE;
1458 break;
1459 case BR_STATE_BLOCKING:
1460 hw_state = PORT_CTRL_BLOCK_STATE;
1461 break;
1462 default:
1463 dev_err(ds->dev, "invalid STP state: %d\n", state);
1464 return;
1465 }
1466
ff39c2d6
FF		 1467 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1468 reg &= ~PORT_CTRL_STP_STATE_MASK;
1469 reg |= hw_state;
1470 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1471}
3117455d 1472EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1473
3117455d 1474void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1475{
1476 struct b53_device *dev = ds->priv;
1477
1478 if (b53_fast_age_port(dev, port))
1479 dev_err(ds->dev, "fast ageing failed\n");
1480}
3117455d 1481EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1482
7b314362
AL		 1483static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1484{
1485 return DSA_TAG_PROTO_NONE;
1486}
1487
ed3af5fd
FF		 1488int b53_mirror_add(struct dsa_switch *ds, int port,
1489 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1490{
1491 struct b53_device *dev = ds->priv;
1492 u16 reg, loc;
1493
1494 if (ingress)
1495 loc = B53_IG_MIR_CTL;
1496 else
1497 loc = B53_EG_MIR_CTL;
1498
1499 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1500 reg &= ~MIRROR_MASK;
1501 reg |= BIT(port);
1502 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1503
1504 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1505 reg &= ~CAP_PORT_MASK;
1506 reg |= mirror->to_local_port;
1507 reg |= MIRROR_EN;
1508 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1509
1510 return 0;
1511}
1512EXPORT_SYMBOL(b53_mirror_add);
1513
1514void b53_mirror_del(struct dsa_switch *ds, int port,
1515 struct dsa_mall_mirror_tc_entry *mirror)
1516{
1517 struct b53_device *dev = ds->priv;
1518 bool loc_disable = false, other_loc_disable = false;
1519 u16 reg, loc;
1520
1521 if (mirror->ingress)
1522 loc = B53_IG_MIR_CTL;
1523 else
1524 loc = B53_EG_MIR_CTL;
1525
1526 /* Update the desired ingress/egress register */
1527 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1528 reg &= ~BIT(port);
1529 if (!(reg & MIRROR_MASK))
1530 loc_disable = true;
1531 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1532
1533 /* Now look at the other one to know if we can disable mirroring
1534 * entirely
1535 */
1536 if (mirror->ingress)
1537 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1538 else
1539 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1540 if (!(reg & MIRROR_MASK))
1541 other_loc_disable = true;
1542
1543 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1544 /* Both no longer have ports, let's disable mirroring */
1545 if (loc_disable && other_loc_disable) {
1546 reg &= ~MIRROR_EN;
1547 reg &= ~mirror->to_local_port;
1548 }
1549 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1550}
1551EXPORT_SYMBOL(b53_mirror_del);
1552
22256b0a
FF		 1553void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1554{
1555 struct b53_device *dev = ds->priv;
1556 u16 reg;
1557
1558 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1559 if (enable)
1560 reg |= BIT(port);
1561 else
1562 reg &= ~BIT(port);
1563 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1564}
1565EXPORT_SYMBOL(b53_eee_enable_set);
1566
1567
1568/* Returns 0 if EEE was not enabled, or 1 otherwise
1569 */
1570int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1571{
1572 int ret;
1573
1574 ret = phy_init_eee(phy, 0);
1575 if (ret)
1576 return 0;
1577
1578 b53_eee_enable_set(ds, port, true);
1579
1580 return 1;
1581}
1582EXPORT_SYMBOL(b53_eee_init);
1583
1584int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1585{
1586 struct b53_device *dev = ds->priv;
1587 struct ethtool_eee *p = &dev->ports[port].eee;
1588 u16 reg;
1589
1590 if (is5325(dev) || is5365(dev))
1591 return -EOPNOTSUPP;
1592
1593 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1594 e->eee_enabled = p->eee_enabled;
1595 e->eee_active = !!(reg & BIT(port));
1596
1597 return 0;
1598}
1599EXPORT_SYMBOL(b53_get_mac_eee);
1600
1601int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1602{
1603 struct b53_device *dev = ds->priv;
1604 struct ethtool_eee *p = &dev->ports[port].eee;
1605
1606 if (is5325(dev) || is5365(dev))
1607 return -EOPNOTSUPP;
1608
1609 p->eee_enabled = e->eee_enabled;
1610 b53_eee_enable_set(ds, port, e->eee_enabled);
1611
1612 return 0;
1613}
1614EXPORT_SYMBOL(b53_set_mac_eee);
1615
a82f67af 1616static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1617 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1618 .setup = b53_setup,
967dd82f
FF		 1619 .get_strings = b53_get_strings,
1620 .get_ethtool_stats = b53_get_ethtool_stats,
1621 .get_sset_count = b53_get_sset_count,
1622 .phy_read = b53_phy_read16,
1623 .phy_write = b53_phy_write16,
1624 .adjust_link = b53_adjust_link,
1625 .port_enable = b53_enable_port,
1626 .port_disable = b53_disable_port,
f43a2dbe
FF		 1627 .get_mac_eee = b53_get_mac_eee,
1628 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 1629 .port_bridge_join = b53_br_join,
1630 .port_bridge_leave = b53_br_leave,
1631 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1632 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1633 .port_vlan_filtering = b53_vlan_filtering,
1634 .port_vlan_prepare = b53_vlan_prepare,
1635 .port_vlan_add = b53_vlan_add,
1636 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 1637 .port_fdb_dump = b53_fdb_dump,
1638 .port_fdb_add = b53_fdb_add,
1639 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1640 .port_mirror_add = b53_mirror_add,
1641 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1642};
1643
1644struct b53_chip_data {
1645 u32 chip_id;
1646 const char *dev_name;
1647 u16 vlans;
1648 u16 enabled_ports;
1649 u8 cpu_port;
1650 u8 vta_regs[3];
1da6df85 1651 u8 arl_entries;
967dd82f
FF		 1652 u8 duplex_reg;
1653 u8 jumbo_pm_reg;
1654 u8 jumbo_size_reg;
1655};
1656
1657#define B53_VTA_REGS \
1658 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1659#define B53_VTA_REGS_9798 \
1660 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1661#define B53_VTA_REGS_63XX \
1662 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1663
1664static const struct b53_chip_data b53_switch_chips[] = {
1665 {
1666 .chip_id = BCM5325_DEVICE_ID,
1667 .dev_name = "BCM5325",
1668 .vlans = 16,
1669 .enabled_ports = 0x1f,
1da6df85 1670 .arl_entries = 2,
967dd82f
FF		 1671 .cpu_port = B53_CPU_PORT_25,
1672 .duplex_reg = B53_DUPLEX_STAT_FE,
1673 },
1674 {
1675 .chip_id = BCM5365_DEVICE_ID,
1676 .dev_name = "BCM5365",
1677 .vlans = 256,
1678 .enabled_ports = 0x1f,
1da6df85 1679 .arl_entries = 2,
967dd82f
FF		 1680 .cpu_port = B53_CPU_PORT_25,
1681 .duplex_reg = B53_DUPLEX_STAT_FE,
1682 },
1683 {
1684 .chip_id = BCM5395_DEVICE_ID,
1685 .dev_name = "BCM5395",
1686 .vlans = 4096,
1687 .enabled_ports = 0x1f,
1da6df85 1688 .arl_entries = 4,
967dd82f
FF		 1689 .cpu_port = B53_CPU_PORT,
1690 .vta_regs = B53_VTA_REGS,
1691 .duplex_reg = B53_DUPLEX_STAT_GE,
1692 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1693 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1694 },
1695 {
1696 .chip_id = BCM5397_DEVICE_ID,
1697 .dev_name = "BCM5397",
1698 .vlans = 4096,
1699 .enabled_ports = 0x1f,
1da6df85 1700 .arl_entries = 4,
967dd82f
FF		 1701 .cpu_port = B53_CPU_PORT,
1702 .vta_regs = B53_VTA_REGS_9798,
1703 .duplex_reg = B53_DUPLEX_STAT_GE,
1704 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1705 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1706 },
1707 {
1708 .chip_id = BCM5398_DEVICE_ID,
1709 .dev_name = "BCM5398",
1710 .vlans = 4096,
1711 .enabled_ports = 0x7f,
1da6df85 1712 .arl_entries = 4,
967dd82f
FF		 1713 .cpu_port = B53_CPU_PORT,
1714 .vta_regs = B53_VTA_REGS_9798,
1715 .duplex_reg = B53_DUPLEX_STAT_GE,
1716 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1717 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1718 },
1719 {
1720 .chip_id = BCM53115_DEVICE_ID,
1721 .dev_name = "BCM53115",
1722 .vlans = 4096,
1723 .enabled_ports = 0x1f,
1da6df85 1724 .arl_entries = 4,
967dd82f
FF		 1725 .vta_regs = B53_VTA_REGS,
1726 .cpu_port = B53_CPU_PORT,
1727 .duplex_reg = B53_DUPLEX_STAT_GE,
1728 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1729 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1730 },
1731 {
1732 .chip_id = BCM53125_DEVICE_ID,
1733 .dev_name = "BCM53125",
1734 .vlans = 4096,
1735 .enabled_ports = 0xff,
be35e8c5 1736 .arl_entries = 4,
967dd82f
FF		 1737 .cpu_port = B53_CPU_PORT,
1738 .vta_regs = B53_VTA_REGS,
1739 .duplex_reg = B53_DUPLEX_STAT_GE,
1740 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1741 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1742 },
1743 {
1744 .chip_id = BCM53128_DEVICE_ID,
1745 .dev_name = "BCM53128",
1746 .vlans = 4096,
1747 .enabled_ports = 0x1ff,
1da6df85 1748 .arl_entries = 4,
967dd82f
FF		 1749 .cpu_port = B53_CPU_PORT,
1750 .vta_regs = B53_VTA_REGS,
1751 .duplex_reg = B53_DUPLEX_STAT_GE,
1752 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1753 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1754 },
1755 {
1756 .chip_id = BCM63XX_DEVICE_ID,
1757 .dev_name = "BCM63xx",
1758 .vlans = 4096,
1759 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1760 .arl_entries = 4,
967dd82f
FF		 1761 .cpu_port = B53_CPU_PORT,
1762 .vta_regs = B53_VTA_REGS_63XX,
1763 .duplex_reg = B53_DUPLEX_STAT_63XX,
1764 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1765 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1766 },
1767 {
1768 .chip_id = BCM53010_DEVICE_ID,
1769 .dev_name = "BCM53010",
1770 .vlans = 4096,
1771 .enabled_ports = 0x1f,
1da6df85 1772 .arl_entries = 4,
967dd82f
FF		 1773 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1774 .vta_regs = B53_VTA_REGS,
1775 .duplex_reg = B53_DUPLEX_STAT_GE,
1776 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1777 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1778 },
1779 {
1780 .chip_id = BCM53011_DEVICE_ID,
1781 .dev_name = "BCM53011",
1782 .vlans = 4096,
1783 .enabled_ports = 0x1bf,
1da6df85 1784 .arl_entries = 4,
967dd82f
FF		 1785 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1786 .vta_regs = B53_VTA_REGS,
1787 .duplex_reg = B53_DUPLEX_STAT_GE,
1788 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1789 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1790 },
1791 {
1792 .chip_id = BCM53012_DEVICE_ID,
1793 .dev_name = "BCM53012",
1794 .vlans = 4096,
1795 .enabled_ports = 0x1bf,
1da6df85 1796 .arl_entries = 4,
967dd82f
FF		 1797 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1798 .vta_regs = B53_VTA_REGS,
1799 .duplex_reg = B53_DUPLEX_STAT_GE,
1800 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1801 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1802 },
1803 {
1804 .chip_id = BCM53018_DEVICE_ID,
1805 .dev_name = "BCM53018",
1806 .vlans = 4096,
1807 .enabled_ports = 0x1f,
1da6df85 1808 .arl_entries = 4,
967dd82f
FF		 1809 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1810 .vta_regs = B53_VTA_REGS,
1811 .duplex_reg = B53_DUPLEX_STAT_GE,
1812 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1813 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1814 },
1815 {
1816 .chip_id = BCM53019_DEVICE_ID,
1817 .dev_name = "BCM53019",
1818 .vlans = 4096,
1819 .enabled_ports = 0x1f,
1da6df85 1820 .arl_entries = 4,
967dd82f
FF		 1821 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1822 .vta_regs = B53_VTA_REGS,
1823 .duplex_reg = B53_DUPLEX_STAT_GE,
1824 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1825 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1826 },
991a36bb
FF		 1827 {
1828 .chip_id = BCM58XX_DEVICE_ID,
1829 .dev_name = "BCM585xx/586xx/88312",
1830 .vlans = 4096,
1831 .enabled_ports = 0x1ff,
1832 .arl_entries = 4,
bfcda65c 1833 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 1834 .vta_regs = B53_VTA_REGS,
1835 .duplex_reg = B53_DUPLEX_STAT_GE,
1836 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1837 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1838 },
130401d9
FF		 1839 {
1840 .chip_id = BCM7445_DEVICE_ID,
1841 .dev_name = "BCM7445",
1842 .vlans = 4096,
1843 .enabled_ports = 0x1ff,
1844 .arl_entries = 4,
1845 .cpu_port = B53_CPU_PORT,
1846 .vta_regs = B53_VTA_REGS,
1847 .duplex_reg = B53_DUPLEX_STAT_GE,
1848 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1849 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1850 },
0fe99338
FF		 1851 {
1852 .chip_id = BCM7278_DEVICE_ID,
1853 .dev_name = "BCM7278",
1854 .vlans = 4096,
1855 .enabled_ports = 0x1ff,
1856 .arl_entries= 4,
1857 .cpu_port = B53_CPU_PORT,
1858 .vta_regs = B53_VTA_REGS,
1859 .duplex_reg = B53_DUPLEX_STAT_GE,
1860 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1861 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1862 },
967dd82f
FF		 1863};
1864
1865static int b53_switch_init(struct b53_device *dev)
1866{
967dd82f
FF		 1867 unsigned int i;
1868 int ret;
1869
1870 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1871 const struct b53_chip_data *chip = &b53_switch_chips[i];
1872
1873 if (chip->chip_id == dev->chip_id) {
1874 if (!dev->enabled_ports)
1875 dev->enabled_ports = chip->enabled_ports;
1876 dev->name = chip->dev_name;
1877 dev->duplex_reg = chip->duplex_reg;
1878 dev->vta_regs[0] = chip->vta_regs[0];
1879 dev->vta_regs[1] = chip->vta_regs[1];
1880 dev->vta_regs[2] = chip->vta_regs[2];
1881 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1882 dev->cpu_port = chip->cpu_port;
1883 dev->num_vlans = chip->vlans;
1da6df85 1884 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1885 break;
1886 }
1887 }
1888
1889 /* check which BCM5325x version we have */
1890 if (is5325(dev)) {
1891 u8 vc4;
1892
1893 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1894
1895 /* check reserved bits */
1896 switch (vc4 & 3) {
1897 case 1:
1898 /* BCM5325E */
1899 break;
1900 case 3:
1901 /* BCM5325F - do not use port 4 */
1902 dev->enabled_ports &= ~BIT(4);
1903 break;
1904 default:
1905/* On the BCM47XX SoCs this is the supported internal switch.*/
1906#ifndef CONFIG_BCM47XX
1907 /* BCM5325M */
1908 return -EINVAL;
1909#else
1910 break;
1911#endif
1912 }
1913 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1914 u64 strap_value;
1915
1916 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1917 /* use second IMP port if GMII is enabled */
1918 if (strap_value & SV_GMII_CTRL_115)
1919 dev->cpu_port = 5;
1920 }
1921
1922 /* cpu port is always last */
1923 dev->num_ports = dev->cpu_port + 1;
1924 dev->enabled_ports |= BIT(dev->cpu_port);
1925
1926 dev->ports = devm_kzalloc(dev->dev,
1927 sizeof(struct b53_port) * dev->num_ports,
1928 GFP_KERNEL);
1929 if (!dev->ports)
1930 return -ENOMEM;
1931
a2482d2c
FF		 1932 dev->vlans = devm_kzalloc(dev->dev,
1933 sizeof(struct b53_vlan) * dev->num_vlans,
1934 GFP_KERNEL);
1935 if (!dev->vlans)
1936 return -ENOMEM;
1937
967dd82f
FF		 1938 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1939 if (dev->reset_gpio >= 0) {
1940 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1941 GPIOF_OUT_INIT_HIGH, "robo_reset");
1942 if (ret)
1943 return ret;
1944 }
1945
1946 return 0;
1947}
1948
0dff88d3
JL		 1949struct b53_device *b53_switch_alloc(struct device *base,
1950 const struct b53_io_ops *ops,
967dd82f
FF		 1951 void *priv)
1952{
1953 struct dsa_switch *ds;
1954 struct b53_device *dev;
1955
a0c02161 1956 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 1957 if (!ds)
1958 return NULL;
1959
a0c02161
VD		 1960 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1961 if (!dev)
1962 return NULL;
967dd82f
FF		 1963
1964 ds->priv = dev;
967dd82f
FF		 1965 dev->dev = base;
1966
1967 dev->ds = ds;
1968 dev->priv = priv;
1969 dev->ops = ops;
485ebd61 1970 ds->ops = &b53_switch_ops;
967dd82f
FF		 1971 mutex_init(&dev->reg_mutex);
1972 mutex_init(&dev->stats_mutex);
1973
1974 return dev;
1975}
1976EXPORT_SYMBOL(b53_switch_alloc);
1977
1978int b53_switch_detect(struct b53_device *dev)
1979{
1980 u32 id32;
1981 u16 tmp;
1982 u8 id8;
1983 int ret;
1984
1985 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1986 if (ret)
1987 return ret;
1988
1989 switch (id8) {
1990 case 0:
1991 /* BCM5325 and BCM5365 do not have this register so reads
1992 * return 0. But the read operation did succeed, so assume this
1993 * is one of them.
1994 *
1995 * Next check if we can write to the 5325's VTA register; for
1996 * 5365 it is read only.
1997 */
1998 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1999 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2000
2001 if (tmp == 0xf)
2002 dev->chip_id = BCM5325_DEVICE_ID;
2003 else
2004 dev->chip_id = BCM5365_DEVICE_ID;
2005 break;
2006 case BCM5395_DEVICE_ID:
2007 case BCM5397_DEVICE_ID:
2008 case BCM5398_DEVICE_ID:
2009 dev->chip_id = id8;
2010 break;
2011 default:
2012 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2013 if (ret)
2014 return ret;
2015
2016 switch (id32) {
2017 case BCM53115_DEVICE_ID:
2018 case BCM53125_DEVICE_ID:
2019 case BCM53128_DEVICE_ID:
2020 case BCM53010_DEVICE_ID:
2021 case BCM53011_DEVICE_ID:
2022 case BCM53012_DEVICE_ID:
2023 case BCM53018_DEVICE_ID:
2024 case BCM53019_DEVICE_ID:
2025 dev->chip_id = id32;
2026 break;
2027 default:
2028 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2029 id8, id32);
2030 return -ENODEV;
2031 }
2032 }
2033
2034 if (dev->chip_id == BCM5325_DEVICE_ID)
2035 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2036 &dev->core_rev);
2037 else
2038 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2039 &dev->core_rev);
2040}
2041EXPORT_SYMBOL(b53_switch_detect);
2042
2043int b53_switch_register(struct b53_device *dev)
2044{
2045 int ret;
2046
2047 if (dev->pdata) {
2048 dev->chip_id = dev->pdata->chip_id;
2049 dev->enabled_ports = dev->pdata->enabled_ports;
2050 }
2051
2052 if (!dev->chip_id && b53_switch_detect(dev))
2053 return -EINVAL;
2054
2055 ret = b53_switch_init(dev);
2056 if (ret)
2057 return ret;
2058
2059 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2060
23c9ee49 2061 return dsa_register_switch(dev->ds);
967dd82f
FF		 2062}
2063EXPORT_SYMBOL(b53_switch_register);
2064
2065MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2066MODULE_DESCRIPTION("B53 switch library");
2067MODULE_LICENSE("Dual BSD/GPL");
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