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net: dsa: b53: Add bridge support
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f 31#include <net/dsa.h>
1da6df85 32#include <net/switchdev.h>
967dd82f
FF		 33
34#include "b53_regs.h"
35#include "b53_priv.h"
36
37struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41};
42
43/* BCM5365 MIB counters */
44static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77};
78
79#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80
81/* BCM63xx MIB counters */
82static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125};
126
127#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
128
129/* MIB counters */
130static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
166};
167
168#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169
170static int b53_do_vlan_op(struct b53_device *dev, u8 op)
171{
172 unsigned int i;
173
174 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
175
176 for (i = 0; i < 10; i++) {
177 u8 vta;
178
179 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
180 if (!(vta & VTA_START_CMD))
181 return 0;
182
183 usleep_range(100, 200);
184 }
185
186 return -EIO;
187}
188
189static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
190 u16 untag)
191{
192 if (is5325(dev)) {
193 u32 entry = 0;
194
195 if (members) {
196 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
197 members;
198 if (dev->core_rev >= 3)
199 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
200 else
201 entry |= VA_VALID_25;
202 }
203
204 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
205 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
206 VTA_RW_STATE_WR | VTA_RW_OP_EN);
207 } else if (is5365(dev)) {
208 u16 entry = 0;
209
210 if (members)
211 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
212 members | VA_VALID_65;
213
214 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
215 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
216 VTA_RW_STATE_WR | VTA_RW_OP_EN);
217 } else {
218 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
219 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
220 (untag << VTE_UNTAG_S) | members);
221
222 b53_do_vlan_op(dev, VTA_CMD_WRITE);
223 }
224}
225
226void b53_set_forwarding(struct b53_device *dev, int enable)
227{
228 u8 mgmt;
229
230 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
231
232 if (enable)
233 mgmt |= SM_SW_FWD_EN;
234 else
235 mgmt &= ~SM_SW_FWD_EN;
236
237 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
238}
239
240static void b53_enable_vlan(struct b53_device *dev, int enable)
241{
242 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
243
244 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
246 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
247
248 if (is5325(dev) || is5365(dev)) {
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
250 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
251 } else if (is63xx(dev)) {
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
253 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
254 } else {
255 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
256 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
257 }
258
259 mgmt &= ~SM_SW_FWD_MODE;
260
261 if (enable) {
262 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
263 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
264 vc4 &= ~VC4_ING_VID_CHECK_MASK;
265 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
266 vc5 |= VC5_DROP_VTABLE_MISS;
267
268 if (is5325(dev))
269 vc0 &= ~VC0_RESERVED_1;
270
271 if (is5325(dev) || is5365(dev))
272 vc1 |= VC1_RX_MCST_TAG_EN;
273
274 if (!is5325(dev) && !is5365(dev)) {
275 if (dev->allow_vid_4095)
276 vc5 |= VC5_VID_FFF_EN;
277 else
278 vc5 &= ~VC5_VID_FFF_EN;
279 }
280 } else {
281 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
282 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
283 vc4 &= ~VC4_ING_VID_CHECK_MASK;
284 vc5 &= ~VC5_DROP_VTABLE_MISS;
285
286 if (is5325(dev) || is5365(dev))
287 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
288 else
289 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
290
291 if (is5325(dev) || is5365(dev))
292 vc1 &= ~VC1_RX_MCST_TAG_EN;
293
294 if (!is5325(dev) && !is5365(dev))
295 vc5 &= ~VC5_VID_FFF_EN;
296 }
297
298 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
299 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
300
301 if (is5325(dev) || is5365(dev)) {
302 /* enable the high 8 bit vid check on 5325 */
303 if (is5325(dev) && enable)
304 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
305 VC3_HIGH_8BIT_EN);
306 else
307 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
308
309 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
310 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
311 } else if (is63xx(dev)) {
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
315 } else {
316 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
317 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
318 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
319 }
320
321 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
322}
323
324static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
325{
326 u32 port_mask = 0;
327 u16 max_size = JMS_MIN_SIZE;
328
329 if (is5325(dev) || is5365(dev))
330 return -EINVAL;
331
332 if (enable) {
333 port_mask = dev->enabled_ports;
334 max_size = JMS_MAX_SIZE;
335 if (allow_10_100)
336 port_mask |= JPM_10_100_JUMBO_EN;
337 }
338
339 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
340 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
341}
342
ff39c2d6 343static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 344{
345 unsigned int i;
346
347 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 348 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 349
350 for (i = 0; i < 10; i++) {
351 u8 fast_age_ctrl;
352
353 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
354 &fast_age_ctrl);
355
356 if (!(fast_age_ctrl & FAST_AGE_DONE))
357 goto out;
358
359 msleep(1);
360 }
361
362 return -ETIMEDOUT;
363out:
364 /* Only age dynamic entries (default behavior) */
365 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
366 return 0;
367}
368
ff39c2d6
FF		 369static int b53_fast_age_port(struct b53_device *dev, int port)
370{
371 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
372
373 return b53_flush_arl(dev, FAST_AGE_PORT);
374}
375
376static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
377{
378 struct b53_device *dev = ds_to_priv(ds);
379 unsigned int i;
380 u16 pvlan;
381
382 /* Enable the IMP port to be in the same VLAN as the other ports
383 * on a per-port basis such that we only have Port i and IMP in
384 * the same VLAN.
385 */
386 b53_for_each_port(dev, i) {
387 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
388 pvlan |= BIT(cpu_port);
389 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
390 }
391}
392
967dd82f
FF		 393static int b53_enable_port(struct dsa_switch *ds, int port,
394 struct phy_device *phy)
395{
396 struct b53_device *dev = ds_to_priv(ds);
ff39c2d6
FF		 397 unsigned int cpu_port = dev->cpu_port;
398 u16 pvlan;
967dd82f
FF		 399
400 /* Clear the Rx and Tx disable bits and set to no spanning tree */
401 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
402
ff39c2d6
FF		 403 /* Set this port, and only this one to be in the default VLAN,
404 * if member of a bridge, restore its membership prior to
405 * bringing down this port.
406 */
407 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
408 pvlan &= ~0x1ff;
409 pvlan |= BIT(port);
410 pvlan |= dev->ports[port].vlan_ctl_mask;
411 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
412
413 b53_imp_vlan_setup(ds, cpu_port);
414
967dd82f
FF		 415 return 0;
416}
417
418static void b53_disable_port(struct dsa_switch *ds, int port,
419 struct phy_device *phy)
420{
421 struct b53_device *dev = ds_to_priv(ds);
422 u8 reg;
423
424 /* Disable Tx/Rx for the port */
425 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
426 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
427 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
428}
429
430static void b53_enable_cpu_port(struct b53_device *dev)
431{
432 unsigned int cpu_port = dev->cpu_port;
433 u8 port_ctrl;
434
435 /* BCM5325 CPU port is at 8 */
436 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
437 cpu_port = B53_CPU_PORT;
438
439 port_ctrl = PORT_CTRL_RX_BCST_EN |
440 PORT_CTRL_RX_MCST_EN |
441 PORT_CTRL_RX_UCST_EN;
442 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
443}
444
445static void b53_enable_mib(struct b53_device *dev)
446{
447 u8 gc;
448
449 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
450 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
451 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
452}
453
454static int b53_configure_vlan(struct b53_device *dev)
455{
456 int i;
457
458 /* clear all vlan entries */
459 if (is5325(dev) || is5365(dev)) {
460 for (i = 1; i < dev->num_vlans; i++)
461 b53_set_vlan_entry(dev, i, 0, 0);
462 } else {
463 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
464 }
465
466 b53_enable_vlan(dev, false);
467
468 b53_for_each_port(dev, i)
469 b53_write16(dev, B53_VLAN_PAGE,
470 B53_VLAN_PORT_DEF_TAG(i), 1);
471
472 if (!is5325(dev) && !is5365(dev))
473 b53_set_jumbo(dev, dev->enable_jumbo, false);
474
475 return 0;
476}
477
478static void b53_switch_reset_gpio(struct b53_device *dev)
479{
480 int gpio = dev->reset_gpio;
481
482 if (gpio < 0)
483 return;
484
485 /* Reset sequence: RESET low(50ms)->high(20ms)
486 */
487 gpio_set_value(gpio, 0);
488 mdelay(50);
489
490 gpio_set_value(gpio, 1);
491 mdelay(20);
492
493 dev->current_page = 0xff;
494}
495
496static int b53_switch_reset(struct b53_device *dev)
497{
498 u8 mgmt;
499
500 b53_switch_reset_gpio(dev);
501
502 if (is539x(dev)) {
503 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
504 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
505 }
506
507 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
508
509 if (!(mgmt & SM_SW_FWD_EN)) {
510 mgmt &= ~SM_SW_FWD_MODE;
511 mgmt |= SM_SW_FWD_EN;
512
513 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
514 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
515
516 if (!(mgmt & SM_SW_FWD_EN)) {
517 dev_err(dev->dev, "Failed to enable switch!\n");
518 return -EINVAL;
519 }
520 }
521
522 b53_enable_mib(dev);
523
ff39c2d6 524 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 525}
526
527static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
528{
529 struct b53_device *priv = ds_to_priv(ds);
530 u16 value = 0;
531 int ret;
532
533 if (priv->ops->phy_read16)
534 ret = priv->ops->phy_read16(priv, addr, reg, &value);
535 else
536 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
537 reg * 2, &value);
538
539 return ret ? ret : value;
540}
541
542static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
543{
544 struct b53_device *priv = ds_to_priv(ds);
545
546 if (priv->ops->phy_write16)
547 return priv->ops->phy_write16(priv, addr, reg, val);
548
549 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
550}
551
552static int b53_reset_switch(struct b53_device *priv)
553{
554 /* reset vlans */
555 priv->enable_jumbo = false;
556
557 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
558
559 return b53_switch_reset(priv);
560}
561
562static int b53_apply_config(struct b53_device *priv)
563{
564 /* disable switching */
565 b53_set_forwarding(priv, 0);
566
567 b53_configure_vlan(priv);
568
569 /* enable switching */
570 b53_set_forwarding(priv, 1);
571
572 return 0;
573}
574
575static void b53_reset_mib(struct b53_device *priv)
576{
577 u8 gc;
578
579 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
580
581 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
582 msleep(1);
583 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
584 msleep(1);
585}
586
587static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
588{
589 if (is5365(dev))
590 return b53_mibs_65;
591 else if (is63xx(dev))
592 return b53_mibs_63xx;
593 else
594 return b53_mibs;
595}
596
597static unsigned int b53_get_mib_size(struct b53_device *dev)
598{
599 if (is5365(dev))
600 return B53_MIBS_65_SIZE;
601 else if (is63xx(dev))
602 return B53_MIBS_63XX_SIZE;
603 else
604 return B53_MIBS_SIZE;
605}
606
607static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
608{
609 struct b53_device *dev = ds_to_priv(ds);
610 const struct b53_mib_desc *mibs = b53_get_mib(dev);
611 unsigned int mib_size = b53_get_mib_size(dev);
612 unsigned int i;
613
614 for (i = 0; i < mib_size; i++)
615 memcpy(data + i * ETH_GSTRING_LEN,
616 mibs[i].name, ETH_GSTRING_LEN);
617}
618
619static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
620 uint64_t *data)
621{
622 struct b53_device *dev = ds_to_priv(ds);
623 const struct b53_mib_desc *mibs = b53_get_mib(dev);
624 unsigned int mib_size = b53_get_mib_size(dev);
625 const struct b53_mib_desc *s;
626 unsigned int i;
627 u64 val = 0;
628
629 if (is5365(dev) && port == 5)
630 port = 8;
631
632 mutex_lock(&dev->stats_mutex);
633
634 for (i = 0; i < mib_size; i++) {
635 s = &mibs[i];
636
637 if (mibs->size == 8) {
638 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
639 } else {
640 u32 val32;
641
642 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
643 &val32);
644 val = val32;
645 }
646 data[i] = (u64)val;
647 }
648
649 mutex_unlock(&dev->stats_mutex);
650}
651
652static int b53_get_sset_count(struct dsa_switch *ds)
653{
654 struct b53_device *dev = ds_to_priv(ds);
655
656 return b53_get_mib_size(dev);
657}
658
659static int b53_set_addr(struct dsa_switch *ds, u8 *addr)
660{
661 return 0;
662}
663
664static int b53_setup(struct dsa_switch *ds)
665{
666 struct b53_device *dev = ds_to_priv(ds);
667 unsigned int port;
668 int ret;
669
670 ret = b53_reset_switch(dev);
671 if (ret) {
672 dev_err(ds->dev, "failed to reset switch\n");
673 return ret;
674 }
675
676 b53_reset_mib(dev);
677
678 ret = b53_apply_config(dev);
679 if (ret)
680 dev_err(ds->dev, "failed to apply configuration\n");
681
682 for (port = 0; port < dev->num_ports; port++) {
683 if (BIT(port) & ds->enabled_port_mask)
684 b53_enable_port(ds, port, NULL);
685 else if (dsa_is_cpu_port(ds, port))
686 b53_enable_cpu_port(dev);
687 else
688 b53_disable_port(ds, port, NULL);
689 }
690
691 return ret;
692}
693
694static void b53_adjust_link(struct dsa_switch *ds, int port,
695 struct phy_device *phydev)
696{
697 struct b53_device *dev = ds_to_priv(ds);
698 u8 rgmii_ctrl = 0, reg = 0, off;
699
700 if (!phy_is_pseudo_fixed_link(phydev))
701 return;
702
703 /* Override the port settings */
704 if (port == dev->cpu_port) {
705 off = B53_PORT_OVERRIDE_CTRL;
706 reg = PORT_OVERRIDE_EN;
707 } else {
708 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
709 reg = GMII_PO_EN;
710 }
711
712 /* Set the link UP */
713 if (phydev->link)
714 reg |= PORT_OVERRIDE_LINK;
715
716 if (phydev->duplex == DUPLEX_FULL)
717 reg |= PORT_OVERRIDE_FULL_DUPLEX;
718
719 switch (phydev->speed) {
720 case 2000:
721 reg |= PORT_OVERRIDE_SPEED_2000M;
722 /* fallthrough */
723 case SPEED_1000:
724 reg |= PORT_OVERRIDE_SPEED_1000M;
725 break;
726 case SPEED_100:
727 reg |= PORT_OVERRIDE_SPEED_100M;
728 break;
729 case SPEED_10:
730 reg |= PORT_OVERRIDE_SPEED_10M;
731 break;
732 default:
733 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
734 return;
735 }
736
737 /* Enable flow control on BCM5301x's CPU port */
738 if (is5301x(dev) && port == dev->cpu_port)
739 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
740
741 if (phydev->pause) {
742 if (phydev->asym_pause)
743 reg |= PORT_OVERRIDE_TX_FLOW;
744 reg |= PORT_OVERRIDE_RX_FLOW;
745 }
746
747 b53_write8(dev, B53_CTRL_PAGE, off, reg);
748
749 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
750 if (port == 8)
751 off = B53_RGMII_CTRL_IMP;
752 else
753 off = B53_RGMII_CTRL_P(port);
754
755 /* Configure the port RGMII clock delay by DLL disabled and
756 * tx_clk aligned timing (restoring to reset defaults)
757 */
758 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
759 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
760 RGMII_CTRL_TIMING_SEL);
761
762 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
763 * sure that we enable the port TX clock internal delay to
764 * account for this internal delay that is inserted, otherwise
765 * the switch won't be able to receive correctly.
766 *
767 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
768 * any delay neither on transmission nor reception, so the
769 * BCM53125 must also be configured accordingly to account for
770 * the lack of delay and introduce
771 *
772 * The BCM53125 switch has its RX clock and TX clock control
773 * swapped, hence the reason why we modify the TX clock path in
774 * the "RGMII" case
775 */
776 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
777 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
778 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
779 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
780 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
781 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
782
783 dev_info(ds->dev, "Configured port %d for %s\n", port,
784 phy_modes(phydev->interface));
785 }
786
787 /* configure MII port if necessary */
788 if (is5325(dev)) {
789 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
790 &reg);
791
792 /* reverse mii needs to be enabled */
793 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
794 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
795 reg | PORT_OVERRIDE_RV_MII_25);
796 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
797 &reg);
798
799 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
800 dev_err(ds->dev,
801 "Failed to enable reverse MII mode\n");
802 return;
803 }
804 }
805 } else if (is5301x(dev)) {
806 if (port != dev->cpu_port) {
807 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
808 u8 gmii_po;
809
810 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
811 gmii_po |= GMII_PO_LINK |
812 GMII_PO_RX_FLOW |
813 GMII_PO_TX_FLOW |
814 GMII_PO_EN |
815 GMII_PO_SPEED_2000M;
816 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
817 }
818 }
819}
820
1da6df85
FF		 821/* Address Resolution Logic routines */
822static int b53_arl_op_wait(struct b53_device *dev)
823{
824 unsigned int timeout = 10;
825 u8 reg;
826
827 do {
828 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
829 if (!(reg & ARLTBL_START_DONE))
830 return 0;
831
832 usleep_range(1000, 2000);
833 } while (timeout--);
834
835 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
836
837 return -ETIMEDOUT;
838}
839
840static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
841{
842 u8 reg;
843
844 if (op > ARLTBL_RW)
845 return -EINVAL;
846
847 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
848 reg |= ARLTBL_START_DONE;
849 if (op)
850 reg |= ARLTBL_RW;
851 else
852 reg &= ~ARLTBL_RW;
853 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
854
855 return b53_arl_op_wait(dev);
856}
857
858static int b53_arl_read(struct b53_device *dev, u64 mac,
859 u16 vid, struct b53_arl_entry *ent, u8 *idx,
860 bool is_valid)
861{
862 unsigned int i;
863 int ret;
864
865 ret = b53_arl_op_wait(dev);
866 if (ret)
867 return ret;
868
869 /* Read the bins */
870 for (i = 0; i < dev->num_arl_entries; i++) {
871 u64 mac_vid;
872 u32 fwd_entry;
873
874 b53_read64(dev, B53_ARLIO_PAGE,
875 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
876 b53_read32(dev, B53_ARLIO_PAGE,
877 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
878 b53_arl_to_entry(ent, mac_vid, fwd_entry);
879
880 if (!(fwd_entry & ARLTBL_VALID))
881 continue;
882 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
883 continue;
884 *idx = i;
885 }
886
887 return -ENOENT;
888}
889
890static int b53_arl_op(struct b53_device *dev, int op, int port,
891 const unsigned char *addr, u16 vid, bool is_valid)
892{
893 struct b53_arl_entry ent;
894 u32 fwd_entry;
895 u64 mac, mac_vid = 0;
896 u8 idx = 0;
897 int ret;
898
899 /* Convert the array into a 64-bit MAC */
900 mac = b53_mac_to_u64(addr);
901
902 /* Perform a read for the given MAC and VID */
903 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
904 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
905
906 /* Issue a read operation for this MAC */
907 ret = b53_arl_rw_op(dev, 1);
908 if (ret)
909 return ret;
910
911 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
912 /* If this is a read, just finish now */
913 if (op)
914 return ret;
915
916 /* We could not find a matching MAC, so reset to a new entry */
917 if (ret) {
918 fwd_entry = 0;
919 idx = 1;
920 }
921
922 memset(&ent, 0, sizeof(ent));
923 ent.port = port;
924 ent.is_valid = is_valid;
925 ent.vid = vid;
926 ent.is_static = true;
927 memcpy(ent.mac, addr, ETH_ALEN);
928 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
929
930 b53_write64(dev, B53_ARLIO_PAGE,
931 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
932 b53_write32(dev, B53_ARLIO_PAGE,
933 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
934
935 return b53_arl_rw_op(dev, 0);
936}
937
938static int b53_fdb_prepare(struct dsa_switch *ds, int port,
939 const struct switchdev_obj_port_fdb *fdb,
940 struct switchdev_trans *trans)
941{
942 struct b53_device *priv = ds_to_priv(ds);
943
944 /* 5325 and 5365 require some more massaging, but could
945 * be supported eventually
946 */
947 if (is5325(priv) || is5365(priv))
948 return -EOPNOTSUPP;
949
950 return 0;
951}
952
953static void b53_fdb_add(struct dsa_switch *ds, int port,
954 const struct switchdev_obj_port_fdb *fdb,
955 struct switchdev_trans *trans)
956{
957 struct b53_device *priv = ds_to_priv(ds);
958
959 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
960 pr_err("%s: failed to add MAC address\n", __func__);
961}
962
963static int b53_fdb_del(struct dsa_switch *ds, int port,
964 const struct switchdev_obj_port_fdb *fdb)
965{
966 struct b53_device *priv = ds_to_priv(ds);
967
968 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
969}
970
971static int b53_arl_search_wait(struct b53_device *dev)
972{
973 unsigned int timeout = 1000;
974 u8 reg;
975
976 do {
977 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
978 if (!(reg & ARL_SRCH_STDN))
979 return 0;
980
981 if (reg & ARL_SRCH_VLID)
982 return 0;
983
984 usleep_range(1000, 2000);
985 } while (timeout--);
986
987 return -ETIMEDOUT;
988}
989
990static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
991 struct b53_arl_entry *ent)
992{
993 u64 mac_vid;
994 u32 fwd_entry;
995
996 b53_read64(dev, B53_ARLIO_PAGE,
997 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
998 b53_read32(dev, B53_ARLIO_PAGE,
999 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1000 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1001}
1002
1003static int b53_fdb_copy(struct net_device *dev, int port,
1004 const struct b53_arl_entry *ent,
1005 struct switchdev_obj_port_fdb *fdb,
1006 int (*cb)(struct switchdev_obj *obj))
1007{
1008 if (!ent->is_valid)
1009 return 0;
1010
1011 if (port != ent->port)
1012 return 0;
1013
1014 ether_addr_copy(fdb->addr, ent->mac);
1015 fdb->vid = ent->vid;
1016 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1017
1018 return cb(&fdb->obj);
1019}
1020
1021static int b53_fdb_dump(struct dsa_switch *ds, int port,
1022 struct switchdev_obj_port_fdb *fdb,
1023 int (*cb)(struct switchdev_obj *obj))
1024{
1025 struct b53_device *priv = ds_to_priv(ds);
1026 struct net_device *dev = ds->ports[port].netdev;
1027 struct b53_arl_entry results[2];
1028 unsigned int count = 0;
1029 int ret;
1030 u8 reg;
1031
1032 /* Start search operation */
1033 reg = ARL_SRCH_STDN;
1034 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1035
1036 do {
1037 ret = b53_arl_search_wait(priv);
1038 if (ret)
1039 return ret;
1040
1041 b53_arl_search_rd(priv, 0, &results[0]);
1042 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1043 if (ret)
1044 return ret;
1045
1046 if (priv->num_arl_entries > 2) {
1047 b53_arl_search_rd(priv, 1, &results[1]);
1048 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1049 if (ret)
1050 return ret;
1051
1052 if (!results[0].is_valid && !results[1].is_valid)
1053 break;
1054 }
1055
1056 } while (count++ < 1024);
1057
1058 return 0;
1059}
1060
ff39c2d6
FF		 1061static int b53_br_join(struct dsa_switch *ds, int port,
1062 struct net_device *bridge)
1063{
1064 struct b53_device *dev = ds_to_priv(ds);
1065 u16 pvlan, reg;
1066 unsigned int i;
1067
1068 dev->ports[port].bridge_dev = bridge;
1069 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1070
1071 b53_for_each_port(dev, i) {
1072 if (dev->ports[i].bridge_dev != bridge)
1073 continue;
1074
1075 /* Add this local port to the remote port VLAN control
1076 * membership and update the remote port bitmask
1077 */
1078 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1079 reg |= BIT(port);
1080 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1081 dev->ports[i].vlan_ctl_mask = reg;
1082
1083 pvlan |= BIT(i);
1084 }
1085
1086 /* Configure the local port VLAN control membership to include
1087 * remote ports and update the local port bitmask
1088 */
1089 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1090 dev->ports[port].vlan_ctl_mask = pvlan;
1091
1092 return 0;
1093}
1094
1095static void b53_br_leave(struct dsa_switch *ds, int port)
1096{
1097 struct b53_device *dev = ds_to_priv(ds);
1098 struct net_device *bridge = dev->ports[port].bridge_dev;
1099 unsigned int i;
1100 u16 pvlan, reg;
1101
1102 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1103
1104 b53_for_each_port(dev, i) {
1105 /* Don't touch the remaining ports */
1106 if (dev->ports[i].bridge_dev != bridge)
1107 continue;
1108
1109 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1110 reg &= ~BIT(port);
1111 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1112 dev->ports[port].vlan_ctl_mask = reg;
1113
1114 /* Prevent self removal to preserve isolation */
1115 if (port != i)
1116 pvlan &= ~BIT(i);
1117 }
1118
1119 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1120 dev->ports[port].vlan_ctl_mask = pvlan;
1121 dev->ports[port].bridge_dev = NULL;
1122}
1123
1124static void b53_br_set_stp_state(struct dsa_switch *ds, int port,
1125 u8 state)
1126{
1127 struct b53_device *dev = ds_to_priv(ds);
1128 u8 hw_state, cur_hw_state;
1129 u8 reg;
1130
1131 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1132 cur_hw_state = reg & PORT_CTRL_STP_STATE_MASK;
1133
1134 switch (state) {
1135 case BR_STATE_DISABLED:
1136 hw_state = PORT_CTRL_DIS_STATE;
1137 break;
1138 case BR_STATE_LISTENING:
1139 hw_state = PORT_CTRL_LISTEN_STATE;
1140 break;
1141 case BR_STATE_LEARNING:
1142 hw_state = PORT_CTRL_LEARN_STATE;
1143 break;
1144 case BR_STATE_FORWARDING:
1145 hw_state = PORT_CTRL_FWD_STATE;
1146 break;
1147 case BR_STATE_BLOCKING:
1148 hw_state = PORT_CTRL_BLOCK_STATE;
1149 break;
1150 default:
1151 dev_err(ds->dev, "invalid STP state: %d\n", state);
1152 return;
1153 }
1154
1155 /* Fast-age ARL entries if we are moving a port from Learning or
1156 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
1157 * state (hw_state)
1158 */
1159 if (cur_hw_state != hw_state) {
1160 if (cur_hw_state >= PORT_CTRL_LEARN_STATE &&
1161 hw_state <= PORT_CTRL_LISTEN_STATE) {
1162 if (b53_fast_age_port(dev, port)) {
1163 dev_err(ds->dev, "fast ageing failed\n");
1164 return;
1165 }
1166 }
1167 }
1168
1169 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1170 reg &= ~PORT_CTRL_STP_STATE_MASK;
1171 reg |= hw_state;
1172 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1173}
1174
967dd82f
FF		 1175static struct dsa_switch_driver b53_switch_ops = {
1176 .tag_protocol = DSA_TAG_PROTO_NONE,
1177 .setup = b53_setup,
1178 .set_addr = b53_set_addr,
1179 .get_strings = b53_get_strings,
1180 .get_ethtool_stats = b53_get_ethtool_stats,
1181 .get_sset_count = b53_get_sset_count,
1182 .phy_read = b53_phy_read16,
1183 .phy_write = b53_phy_write16,
1184 .adjust_link = b53_adjust_link,
1185 .port_enable = b53_enable_port,
1186 .port_disable = b53_disable_port,
ff39c2d6
FF		 1187 .port_bridge_join = b53_br_join,
1188 .port_bridge_leave = b53_br_leave,
1189 .port_stp_state_set = b53_br_set_stp_state,
1da6df85
FF		 1190 .port_fdb_prepare = b53_fdb_prepare,
1191 .port_fdb_dump = b53_fdb_dump,
1192 .port_fdb_add = b53_fdb_add,
1193 .port_fdb_del = b53_fdb_del,
967dd82f
FF		 1194};
1195
1196struct b53_chip_data {
1197 u32 chip_id;
1198 const char *dev_name;
1199 u16 vlans;
1200 u16 enabled_ports;
1201 u8 cpu_port;
1202 u8 vta_regs[3];
1da6df85 1203 u8 arl_entries;
967dd82f
FF		 1204 u8 duplex_reg;
1205 u8 jumbo_pm_reg;
1206 u8 jumbo_size_reg;
1207};
1208
1209#define B53_VTA_REGS \
1210 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1211#define B53_VTA_REGS_9798 \
1212 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1213#define B53_VTA_REGS_63XX \
1214 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1215
1216static const struct b53_chip_data b53_switch_chips[] = {
1217 {
1218 .chip_id = BCM5325_DEVICE_ID,
1219 .dev_name = "BCM5325",
1220 .vlans = 16,
1221 .enabled_ports = 0x1f,
1da6df85 1222 .arl_entries = 2,
967dd82f
FF		 1223 .cpu_port = B53_CPU_PORT_25,
1224 .duplex_reg = B53_DUPLEX_STAT_FE,
1225 },
1226 {
1227 .chip_id = BCM5365_DEVICE_ID,
1228 .dev_name = "BCM5365",
1229 .vlans = 256,
1230 .enabled_ports = 0x1f,
1da6df85 1231 .arl_entries = 2,
967dd82f
FF		 1232 .cpu_port = B53_CPU_PORT_25,
1233 .duplex_reg = B53_DUPLEX_STAT_FE,
1234 },
1235 {
1236 .chip_id = BCM5395_DEVICE_ID,
1237 .dev_name = "BCM5395",
1238 .vlans = 4096,
1239 .enabled_ports = 0x1f,
1da6df85 1240 .arl_entries = 4,
967dd82f
FF		 1241 .cpu_port = B53_CPU_PORT,
1242 .vta_regs = B53_VTA_REGS,
1243 .duplex_reg = B53_DUPLEX_STAT_GE,
1244 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1245 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1246 },
1247 {
1248 .chip_id = BCM5397_DEVICE_ID,
1249 .dev_name = "BCM5397",
1250 .vlans = 4096,
1251 .enabled_ports = 0x1f,
1da6df85 1252 .arl_entries = 4,
967dd82f
FF		 1253 .cpu_port = B53_CPU_PORT,
1254 .vta_regs = B53_VTA_REGS_9798,
1255 .duplex_reg = B53_DUPLEX_STAT_GE,
1256 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1257 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1258 },
1259 {
1260 .chip_id = BCM5398_DEVICE_ID,
1261 .dev_name = "BCM5398",
1262 .vlans = 4096,
1263 .enabled_ports = 0x7f,
1da6df85 1264 .arl_entries = 4,
967dd82f
FF		 1265 .cpu_port = B53_CPU_PORT,
1266 .vta_regs = B53_VTA_REGS_9798,
1267 .duplex_reg = B53_DUPLEX_STAT_GE,
1268 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1269 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1270 },
1271 {
1272 .chip_id = BCM53115_DEVICE_ID,
1273 .dev_name = "BCM53115",
1274 .vlans = 4096,
1275 .enabled_ports = 0x1f,
1da6df85 1276 .arl_entries = 4,
967dd82f
FF		 1277 .vta_regs = B53_VTA_REGS,
1278 .cpu_port = B53_CPU_PORT,
1279 .duplex_reg = B53_DUPLEX_STAT_GE,
1280 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1281 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1282 },
1283 {
1284 .chip_id = BCM53125_DEVICE_ID,
1285 .dev_name = "BCM53125",
1286 .vlans = 4096,
1287 .enabled_ports = 0xff,
1288 .cpu_port = B53_CPU_PORT,
1289 .vta_regs = B53_VTA_REGS,
1290 .duplex_reg = B53_DUPLEX_STAT_GE,
1291 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1292 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1293 },
1294 {
1295 .chip_id = BCM53128_DEVICE_ID,
1296 .dev_name = "BCM53128",
1297 .vlans = 4096,
1298 .enabled_ports = 0x1ff,
1da6df85 1299 .arl_entries = 4,
967dd82f
FF		 1300 .cpu_port = B53_CPU_PORT,
1301 .vta_regs = B53_VTA_REGS,
1302 .duplex_reg = B53_DUPLEX_STAT_GE,
1303 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1304 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1305 },
1306 {
1307 .chip_id = BCM63XX_DEVICE_ID,
1308 .dev_name = "BCM63xx",
1309 .vlans = 4096,
1310 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1311 .arl_entries = 4,
967dd82f
FF		 1312 .cpu_port = B53_CPU_PORT,
1313 .vta_regs = B53_VTA_REGS_63XX,
1314 .duplex_reg = B53_DUPLEX_STAT_63XX,
1315 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1316 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1317 },
1318 {
1319 .chip_id = BCM53010_DEVICE_ID,
1320 .dev_name = "BCM53010",
1321 .vlans = 4096,
1322 .enabled_ports = 0x1f,
1da6df85 1323 .arl_entries = 4,
967dd82f
FF		 1324 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1325 .vta_regs = B53_VTA_REGS,
1326 .duplex_reg = B53_DUPLEX_STAT_GE,
1327 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1328 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1329 },
1330 {
1331 .chip_id = BCM53011_DEVICE_ID,
1332 .dev_name = "BCM53011",
1333 .vlans = 4096,
1334 .enabled_ports = 0x1bf,
1da6df85 1335 .arl_entries = 4,
967dd82f
FF		 1336 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1337 .vta_regs = B53_VTA_REGS,
1338 .duplex_reg = B53_DUPLEX_STAT_GE,
1339 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1340 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1341 },
1342 {
1343 .chip_id = BCM53012_DEVICE_ID,
1344 .dev_name = "BCM53012",
1345 .vlans = 4096,
1346 .enabled_ports = 0x1bf,
1da6df85 1347 .arl_entries = 4,
967dd82f
FF		 1348 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1349 .vta_regs = B53_VTA_REGS,
1350 .duplex_reg = B53_DUPLEX_STAT_GE,
1351 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1352 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1353 },
1354 {
1355 .chip_id = BCM53018_DEVICE_ID,
1356 .dev_name = "BCM53018",
1357 .vlans = 4096,
1358 .enabled_ports = 0x1f,
1da6df85 1359 .arl_entries = 4,
967dd82f
FF		 1360 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1361 .vta_regs = B53_VTA_REGS,
1362 .duplex_reg = B53_DUPLEX_STAT_GE,
1363 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1364 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1365 },
1366 {
1367 .chip_id = BCM53019_DEVICE_ID,
1368 .dev_name = "BCM53019",
1369 .vlans = 4096,
1370 .enabled_ports = 0x1f,
1da6df85 1371 .arl_entries = 4,
967dd82f
FF		 1372 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1373 .vta_regs = B53_VTA_REGS,
1374 .duplex_reg = B53_DUPLEX_STAT_GE,
1375 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1376 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1377 },
1378};
1379
1380static int b53_switch_init(struct b53_device *dev)
1381{
1382 struct dsa_switch *ds = dev->ds;
1383 unsigned int i;
1384 int ret;
1385
1386 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1387 const struct b53_chip_data *chip = &b53_switch_chips[i];
1388
1389 if (chip->chip_id == dev->chip_id) {
1390 if (!dev->enabled_ports)
1391 dev->enabled_ports = chip->enabled_ports;
1392 dev->name = chip->dev_name;
1393 dev->duplex_reg = chip->duplex_reg;
1394 dev->vta_regs[0] = chip->vta_regs[0];
1395 dev->vta_regs[1] = chip->vta_regs[1];
1396 dev->vta_regs[2] = chip->vta_regs[2];
1397 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1398 ds->drv = &b53_switch_ops;
1399 dev->cpu_port = chip->cpu_port;
1400 dev->num_vlans = chip->vlans;
1da6df85 1401 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1402 break;
1403 }
1404 }
1405
1406 /* check which BCM5325x version we have */
1407 if (is5325(dev)) {
1408 u8 vc4;
1409
1410 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1411
1412 /* check reserved bits */
1413 switch (vc4 & 3) {
1414 case 1:
1415 /* BCM5325E */
1416 break;
1417 case 3:
1418 /* BCM5325F - do not use port 4 */
1419 dev->enabled_ports &= ~BIT(4);
1420 break;
1421 default:
1422/* On the BCM47XX SoCs this is the supported internal switch.*/
1423#ifndef CONFIG_BCM47XX
1424 /* BCM5325M */
1425 return -EINVAL;
1426#else
1427 break;
1428#endif
1429 }
1430 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1431 u64 strap_value;
1432
1433 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1434 /* use second IMP port if GMII is enabled */
1435 if (strap_value & SV_GMII_CTRL_115)
1436 dev->cpu_port = 5;
1437 }
1438
1439 /* cpu port is always last */
1440 dev->num_ports = dev->cpu_port + 1;
1441 dev->enabled_ports |= BIT(dev->cpu_port);
1442
1443 dev->ports = devm_kzalloc(dev->dev,
1444 sizeof(struct b53_port) * dev->num_ports,
1445 GFP_KERNEL);
1446 if (!dev->ports)
1447 return -ENOMEM;
1448
1449 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1450 if (dev->reset_gpio >= 0) {
1451 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1452 GPIOF_OUT_INIT_HIGH, "robo_reset");
1453 if (ret)
1454 return ret;
1455 }
1456
1457 return 0;
1458}
1459
1460struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1461 void *priv)
1462{
1463 struct dsa_switch *ds;
1464 struct b53_device *dev;
1465
1466 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1467 if (!ds)
1468 return NULL;
1469
1470 dev = (struct b53_device *)(ds + 1);
1471
1472 ds->priv = dev;
1473 ds->dev = base;
1474 dev->dev = base;
1475
1476 dev->ds = ds;
1477 dev->priv = priv;
1478 dev->ops = ops;
1479 mutex_init(&dev->reg_mutex);
1480 mutex_init(&dev->stats_mutex);
1481
1482 return dev;
1483}
1484EXPORT_SYMBOL(b53_switch_alloc);
1485
1486int b53_switch_detect(struct b53_device *dev)
1487{
1488 u32 id32;
1489 u16 tmp;
1490 u8 id8;
1491 int ret;
1492
1493 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1494 if (ret)
1495 return ret;
1496
1497 switch (id8) {
1498 case 0:
1499 /* BCM5325 and BCM5365 do not have this register so reads
1500 * return 0. But the read operation did succeed, so assume this
1501 * is one of them.
1502 *
1503 * Next check if we can write to the 5325's VTA register; for
1504 * 5365 it is read only.
1505 */
1506 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1507 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1508
1509 if (tmp == 0xf)
1510 dev->chip_id = BCM5325_DEVICE_ID;
1511 else
1512 dev->chip_id = BCM5365_DEVICE_ID;
1513 break;
1514 case BCM5395_DEVICE_ID:
1515 case BCM5397_DEVICE_ID:
1516 case BCM5398_DEVICE_ID:
1517 dev->chip_id = id8;
1518 break;
1519 default:
1520 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1521 if (ret)
1522 return ret;
1523
1524 switch (id32) {
1525 case BCM53115_DEVICE_ID:
1526 case BCM53125_DEVICE_ID:
1527 case BCM53128_DEVICE_ID:
1528 case BCM53010_DEVICE_ID:
1529 case BCM53011_DEVICE_ID:
1530 case BCM53012_DEVICE_ID:
1531 case BCM53018_DEVICE_ID:
1532 case BCM53019_DEVICE_ID:
1533 dev->chip_id = id32;
1534 break;
1535 default:
1536 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1537 id8, id32);
1538 return -ENODEV;
1539 }
1540 }
1541
1542 if (dev->chip_id == BCM5325_DEVICE_ID)
1543 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1544 &dev->core_rev);
1545 else
1546 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1547 &dev->core_rev);
1548}
1549EXPORT_SYMBOL(b53_switch_detect);
1550
1551int b53_switch_register(struct b53_device *dev)
1552{
1553 int ret;
1554
1555 if (dev->pdata) {
1556 dev->chip_id = dev->pdata->chip_id;
1557 dev->enabled_ports = dev->pdata->enabled_ports;
1558 }
1559
1560 if (!dev->chip_id && b53_switch_detect(dev))
1561 return -EINVAL;
1562
1563 ret = b53_switch_init(dev);
1564 if (ret)
1565 return ret;
1566
1567 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1568
1569 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1570}
1571EXPORT_SYMBOL(b53_switch_register);
1572
1573MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1574MODULE_DESCRIPTION("B53 switch library");
1575MODULE_LICENSE("Dual BSD/GPL");
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