]>
Commit | Line | Data |
---|---|---|
246d7f77 FF |
1 | /* |
2 | * Broadcom Starfighter 2 DSA switch driver | |
3 | * | |
4 | * Copyright (C) 2014, Broadcom Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/list.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/phy.h> | |
19 | #include <linux/phy_fixed.h> | |
20 | #include <linux/mii.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_address.h> | |
8b7c94e3 | 24 | #include <linux/of_net.h> |
461cd1b0 | 25 | #include <linux/of_mdio.h> |
246d7f77 | 26 | #include <net/dsa.h> |
96e65d7f | 27 | #include <linux/ethtool.h> |
12f460f2 | 28 | #include <linux/if_bridge.h> |
aafc66f1 | 29 | #include <linux/brcmphy.h> |
680060d3 | 30 | #include <linux/etherdevice.h> |
f458995b | 31 | #include <linux/platform_data/b53.h> |
246d7f77 FF |
32 | |
33 | #include "bcm_sf2.h" | |
34 | #include "bcm_sf2_regs.h" | |
f458995b FF |
35 | #include "b53/b53_priv.h" |
36 | #include "b53/b53_regs.h" | |
246d7f77 | 37 | |
7b314362 AL |
38 | static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds) |
39 | { | |
40 | return DSA_TAG_PROTO_BRCM; | |
41 | } | |
42 | ||
b6d045db | 43 | static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) |
246d7f77 | 44 | { |
f458995b | 45 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
246d7f77 | 46 | unsigned int i; |
b6d045db FF |
47 | u32 reg; |
48 | ||
49 | /* Enable the IMP Port to be in the same VLAN as the other ports | |
50 | * on a per-port basis such that we only have Port i and IMP in | |
51 | * the same VLAN. | |
52 | */ | |
53 | for (i = 0; i < priv->hw_params.num_ports; i++) { | |
74c3e2a5 | 54 | if (!((1 << i) & ds->enabled_port_mask)) |
b6d045db FF |
55 | continue; |
56 | ||
57 | reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); | |
58 | reg |= (1 << cpu_port); | |
59 | core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); | |
60 | } | |
61 | } | |
62 | ||
ebb2ac4f | 63 | static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port) |
b6d045db | 64 | { |
ebb2ac4f | 65 | u32 reg, val; |
246d7f77 FF |
66 | |
67 | /* Resolve which bit controls the Broadcom tag */ | |
68 | switch (port) { | |
69 | case 8: | |
70 | val = BRCM_HDR_EN_P8; | |
71 | break; | |
72 | case 7: | |
73 | val = BRCM_HDR_EN_P7; | |
74 | break; | |
75 | case 5: | |
76 | val = BRCM_HDR_EN_P5; | |
77 | break; | |
78 | default: | |
79 | val = 0; | |
80 | break; | |
81 | } | |
82 | ||
83 | /* Enable Broadcom tags for IMP port */ | |
84 | reg = core_readl(priv, CORE_BRCM_HDR_CTRL); | |
85 | reg |= val; | |
86 | core_writel(priv, reg, CORE_BRCM_HDR_CTRL); | |
87 | ||
88 | /* Enable reception Broadcom tag for CPU TX (switch RX) to | |
89 | * allow us to tag outgoing frames | |
90 | */ | |
91 | reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS); | |
92 | reg &= ~(1 << port); | |
93 | core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS); | |
94 | ||
95 | /* Enable transmission of Broadcom tags from the switch (CPU RX) to | |
96 | * allow delivering frames to the per-port net_devices | |
97 | */ | |
98 | reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS); | |
99 | reg &= ~(1 << port); | |
100 | core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS); | |
ebb2ac4f FF |
101 | } |
102 | ||
103 | static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) | |
104 | { | |
105 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); | |
106 | u32 reg, offset; | |
107 | ||
108 | if (priv->type == BCM7445_DEVICE_ID) | |
109 | offset = CORE_STS_OVERRIDE_IMP; | |
110 | else | |
111 | offset = CORE_STS_OVERRIDE_IMP2; | |
112 | ||
113 | /* Enable the port memories */ | |
114 | reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); | |
115 | reg &= ~P_TXQ_PSM_VDD(port); | |
116 | core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); | |
117 | ||
118 | /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ | |
119 | reg = core_readl(priv, CORE_IMP_CTL); | |
120 | reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); | |
121 | reg &= ~(RX_DIS | TX_DIS); | |
122 | core_writel(priv, reg, CORE_IMP_CTL); | |
123 | ||
124 | /* Enable forwarding */ | |
125 | core_writel(priv, SW_FWDG_EN, CORE_SWMODE); | |
126 | ||
127 | /* Enable IMP port in dumb mode */ | |
128 | reg = core_readl(priv, CORE_SWITCH_CTRL); | |
129 | reg |= MII_DUMB_FWDG_EN; | |
130 | core_writel(priv, reg, CORE_SWITCH_CTRL); | |
131 | ||
132 | bcm_sf2_brcm_hdr_setup(priv, port); | |
246d7f77 FF |
133 | |
134 | /* Force link status for IMP port */ | |
0fe99338 | 135 | reg = core_readl(priv, offset); |
246d7f77 | 136 | reg |= (MII_SW_OR | LINK_STS); |
0fe99338 | 137 | core_writel(priv, reg, offset); |
246d7f77 FF |
138 | } |
139 | ||
450b05c1 FF |
140 | static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable) |
141 | { | |
f458995b | 142 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
450b05c1 FF |
143 | u32 reg; |
144 | ||
145 | reg = core_readl(priv, CORE_EEE_EN_CTRL); | |
146 | if (enable) | |
147 | reg |= 1 << port; | |
148 | else | |
149 | reg &= ~(1 << port); | |
150 | core_writel(priv, reg, CORE_EEE_EN_CTRL); | |
151 | } | |
152 | ||
b083668c FF |
153 | static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) |
154 | { | |
f458995b | 155 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
b083668c FF |
156 | u32 reg; |
157 | ||
b083668c | 158 | reg = reg_readl(priv, REG_SPHY_CNTRL); |
9af197a8 FF |
159 | if (enable) { |
160 | reg |= PHY_RESET; | |
161 | reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS); | |
162 | reg_writel(priv, reg, REG_SPHY_CNTRL); | |
163 | udelay(21); | |
164 | reg = reg_readl(priv, REG_SPHY_CNTRL); | |
165 | reg &= ~PHY_RESET; | |
166 | } else { | |
167 | reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; | |
168 | reg_writel(priv, reg, REG_SPHY_CNTRL); | |
169 | mdelay(1); | |
170 | reg |= CK25_DIS; | |
171 | } | |
b083668c | 172 | reg_writel(priv, reg, REG_SPHY_CNTRL); |
9af197a8 FF |
173 | |
174 | /* Use PHY-driven LED signaling */ | |
175 | if (!enable) { | |
176 | reg = reg_readl(priv, REG_LED_CNTRL(0)); | |
177 | reg |= SPDLNK_SRC_SEL; | |
178 | reg_writel(priv, reg, REG_LED_CNTRL(0)); | |
179 | } | |
b083668c FF |
180 | } |
181 | ||
8b7c94e3 FF |
182 | static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, |
183 | int port) | |
184 | { | |
185 | unsigned int off; | |
186 | ||
187 | switch (port) { | |
188 | case 7: | |
189 | off = P7_IRQ_OFF; | |
190 | break; | |
191 | case 0: | |
192 | /* Port 0 interrupts are located on the first bank */ | |
193 | intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); | |
194 | return; | |
195 | default: | |
196 | off = P_IRQ_OFF(port); | |
197 | break; | |
198 | } | |
199 | ||
200 | intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); | |
201 | } | |
202 | ||
203 | static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, | |
204 | int port) | |
205 | { | |
206 | unsigned int off; | |
207 | ||
208 | switch (port) { | |
209 | case 7: | |
210 | off = P7_IRQ_OFF; | |
211 | break; | |
212 | case 0: | |
213 | /* Port 0 interrupts are located on the first bank */ | |
214 | intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); | |
215 | intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); | |
216 | return; | |
217 | default: | |
218 | off = P_IRQ_OFF(port); | |
219 | break; | |
220 | } | |
221 | ||
222 | intrl2_1_mask_set(priv, P_IRQ_MASK(off)); | |
223 | intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); | |
224 | } | |
225 | ||
b6d045db FF |
226 | static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, |
227 | struct phy_device *phy) | |
246d7f77 | 228 | { |
f458995b | 229 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
8b0d3ea5 | 230 | s8 cpu_port = ds->dst->cpu_dp->index; |
e1b9147c | 231 | unsigned int i; |
246d7f77 FF |
232 | u32 reg; |
233 | ||
234 | /* Clear the memory power down */ | |
235 | reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); | |
236 | reg &= ~P_TXQ_PSM_VDD(port); | |
237 | core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); | |
238 | ||
64ff2aef FF |
239 | /* Enable Broadcom tags for that port if requested */ |
240 | if (priv->brcm_tag_mask & BIT(port)) | |
241 | bcm_sf2_brcm_hdr_setup(priv, port); | |
242 | ||
e1b9147c FF |
243 | /* Configure Traffic Class to QoS mapping, allow each priority to map |
244 | * to a different queue number | |
245 | */ | |
246 | reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); | |
247 | for (i = 0; i < 8; i++) | |
248 | reg |= i << (PRT_TO_QID_SHIFT * i); | |
249 | core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); | |
250 | ||
246d7f77 FF |
251 | /* Clear the Rx and Tx disable bits and set to no spanning tree */ |
252 | core_writel(priv, 0, CORE_G_PCTL_PORT(port)); | |
253 | ||
9af197a8 | 254 | /* Re-enable the GPHY and re-apply workarounds */ |
8b7c94e3 | 255 | if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { |
9af197a8 FF |
256 | bcm_sf2_gphy_enable_set(ds, true); |
257 | if (phy) { | |
258 | /* if phy_stop() has been called before, phy | |
259 | * will be in halted state, and phy_start() | |
260 | * will call resume. | |
261 | * | |
262 | * the resume path does not configure back | |
263 | * autoneg settings, and since we hard reset | |
264 | * the phy manually here, we need to reset the | |
265 | * state machine also. | |
266 | */ | |
267 | phy->state = PHY_READY; | |
268 | phy_init_hw(phy); | |
269 | } | |
270 | } | |
271 | ||
8b7c94e3 FF |
272 | /* Enable MoCA port interrupts to get notified */ |
273 | if (port == priv->moca_port) | |
274 | bcm_sf2_port_intr_enable(priv, port); | |
246d7f77 | 275 | |
12f460f2 FF |
276 | /* Set this port, and only this one to be in the default VLAN, |
277 | * if member of a bridge, restore its membership prior to | |
278 | * bringing down this port. | |
279 | */ | |
246d7f77 FF |
280 | reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port)); |
281 | reg &= ~PORT_VLAN_CTRL_MASK; | |
282 | reg |= (1 << port); | |
02154927 | 283 | reg |= priv->dev->ports[port].vlan_ctl_mask; |
246d7f77 | 284 | core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port)); |
b6d045db FF |
285 | |
286 | bcm_sf2_imp_vlan_setup(ds, cpu_port); | |
287 | ||
450b05c1 FF |
288 | /* If EEE was enabled, restore it */ |
289 | if (priv->port_sts[port].eee.eee_enabled) | |
290 | bcm_sf2_eee_enable_set(ds, port, true); | |
291 | ||
b6d045db | 292 | return 0; |
246d7f77 FF |
293 | } |
294 | ||
b6d045db FF |
295 | static void bcm_sf2_port_disable(struct dsa_switch *ds, int port, |
296 | struct phy_device *phy) | |
246d7f77 | 297 | { |
f458995b | 298 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
246d7f77 FF |
299 | u32 off, reg; |
300 | ||
96e65d7f FF |
301 | if (priv->wol_ports_mask & (1 << port)) |
302 | return; | |
303 | ||
8b7c94e3 FF |
304 | if (port == priv->moca_port) |
305 | bcm_sf2_port_intr_disable(priv, port); | |
b6d045db | 306 | |
8b7c94e3 | 307 | if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) |
9af197a8 FF |
308 | bcm_sf2_gphy_enable_set(ds, false); |
309 | ||
246d7f77 FF |
310 | if (dsa_is_cpu_port(ds, port)) |
311 | off = CORE_IMP_CTL; | |
312 | else | |
313 | off = CORE_G_PCTL_PORT(port); | |
314 | ||
315 | reg = core_readl(priv, off); | |
316 | reg |= RX_DIS | TX_DIS; | |
317 | core_writel(priv, reg, off); | |
318 | ||
319 | /* Power down the port memory */ | |
320 | reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); | |
321 | reg |= P_TXQ_PSM_VDD(port); | |
322 | core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); | |
323 | } | |
324 | ||
450b05c1 FF |
325 | /* Returns 0 if EEE was not enabled, or 1 otherwise |
326 | */ | |
327 | static int bcm_sf2_eee_init(struct dsa_switch *ds, int port, | |
328 | struct phy_device *phy) | |
329 | { | |
f458995b | 330 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
450b05c1 FF |
331 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
332 | int ret; | |
333 | ||
334 | p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full); | |
335 | ||
336 | ret = phy_init_eee(phy, 0); | |
337 | if (ret) | |
338 | return 0; | |
339 | ||
340 | bcm_sf2_eee_enable_set(ds, port, true); | |
341 | ||
342 | return 1; | |
343 | } | |
344 | ||
345 | static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port, | |
346 | struct ethtool_eee *e) | |
347 | { | |
f458995b | 348 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
450b05c1 FF |
349 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
350 | u32 reg; | |
351 | ||
352 | reg = core_readl(priv, CORE_EEE_LPI_INDICATE); | |
353 | e->eee_enabled = p->eee_enabled; | |
354 | e->eee_active = !!(reg & (1 << port)); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port, | |
360 | struct phy_device *phydev, | |
361 | struct ethtool_eee *e) | |
362 | { | |
f458995b | 363 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
450b05c1 FF |
364 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
365 | ||
366 | p->eee_enabled = e->eee_enabled; | |
367 | ||
368 | if (!p->eee_enabled) { | |
369 | bcm_sf2_eee_enable_set(ds, port, false); | |
370 | } else { | |
371 | p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev); | |
372 | if (!p->eee_enabled) | |
373 | return -EOPNOTSUPP; | |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
461cd1b0 FF |
379 | static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, |
380 | int regnum, u16 val) | |
381 | { | |
382 | int ret = 0; | |
383 | u32 reg; | |
384 | ||
385 | reg = reg_readl(priv, REG_SWITCH_CNTRL); | |
386 | reg |= MDIO_MASTER_SEL; | |
387 | reg_writel(priv, reg, REG_SWITCH_CNTRL); | |
388 | ||
389 | /* Page << 8 | offset */ | |
390 | reg = 0x70; | |
391 | reg <<= 2; | |
392 | core_writel(priv, addr, reg); | |
393 | ||
394 | /* Page << 8 | offset */ | |
395 | reg = 0x80 << 8 | regnum << 1; | |
396 | reg <<= 2; | |
397 | ||
398 | if (op) | |
399 | ret = core_readl(priv, reg); | |
400 | else | |
401 | core_writel(priv, val, reg); | |
402 | ||
403 | reg = reg_readl(priv, REG_SWITCH_CNTRL); | |
404 | reg &= ~MDIO_MASTER_SEL; | |
405 | reg_writel(priv, reg, REG_SWITCH_CNTRL); | |
406 | ||
407 | return ret & 0xffff; | |
408 | } | |
409 | ||
410 | static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) | |
411 | { | |
412 | struct bcm_sf2_priv *priv = bus->priv; | |
413 | ||
414 | /* Intercept reads from Broadcom pseudo-PHY address, else, send | |
415 | * them to our master MDIO bus controller | |
416 | */ | |
417 | if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) | |
418 | return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); | |
419 | else | |
2cfe8f82 | 420 | return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); |
461cd1b0 FF |
421 | } |
422 | ||
423 | static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, | |
424 | u16 val) | |
425 | { | |
426 | struct bcm_sf2_priv *priv = bus->priv; | |
427 | ||
428 | /* Intercept writes to the Broadcom pseudo-PHY address, else, | |
429 | * send them to our master MDIO bus controller | |
430 | */ | |
431 | if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) | |
432 | bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); | |
433 | else | |
2cfe8f82 | 434 | mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val); |
461cd1b0 FF |
435 | |
436 | return 0; | |
437 | } | |
438 | ||
246d7f77 FF |
439 | static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) |
440 | { | |
441 | struct bcm_sf2_priv *priv = dev_id; | |
442 | ||
443 | priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & | |
444 | ~priv->irq0_mask; | |
445 | intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); | |
446 | ||
447 | return IRQ_HANDLED; | |
448 | } | |
449 | ||
450 | static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) | |
451 | { | |
452 | struct bcm_sf2_priv *priv = dev_id; | |
453 | ||
454 | priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & | |
455 | ~priv->irq1_mask; | |
456 | intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); | |
457 | ||
458 | if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) | |
459 | priv->port_sts[7].link = 1; | |
460 | if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) | |
461 | priv->port_sts[7].link = 0; | |
462 | ||
463 | return IRQ_HANDLED; | |
464 | } | |
465 | ||
33f84614 FF |
466 | static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) |
467 | { | |
468 | unsigned int timeout = 1000; | |
469 | u32 reg; | |
470 | ||
471 | reg = core_readl(priv, CORE_WATCHDOG_CTRL); | |
472 | reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; | |
473 | core_writel(priv, reg, CORE_WATCHDOG_CTRL); | |
474 | ||
475 | do { | |
476 | reg = core_readl(priv, CORE_WATCHDOG_CTRL); | |
477 | if (!(reg & SOFTWARE_RESET)) | |
478 | break; | |
479 | ||
480 | usleep_range(1000, 2000); | |
481 | } while (timeout-- > 0); | |
482 | ||
483 | if (timeout == 0) | |
484 | return -ETIMEDOUT; | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
691c9a8f FF |
489 | static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) |
490 | { | |
f01d5988 | 491 | intrl2_0_mask_set(priv, 0xffffffff); |
691c9a8f | 492 | intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); |
f01d5988 | 493 | intrl2_1_mask_set(priv, 0xffffffff); |
691c9a8f | 494 | intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); |
691c9a8f FF |
495 | } |
496 | ||
8b7c94e3 FF |
497 | static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, |
498 | struct device_node *dn) | |
499 | { | |
500 | struct device_node *port; | |
8b7c94e3 FF |
501 | int mode; |
502 | unsigned int port_num; | |
8b7c94e3 FF |
503 | |
504 | priv->moca_port = -1; | |
505 | ||
506 | for_each_available_child_of_node(dn, port) { | |
507 | if (of_property_read_u32(port, "reg", &port_num)) | |
508 | continue; | |
509 | ||
510 | /* Internal PHYs get assigned a specific 'phy-mode' property | |
511 | * value: "internal" to help flag them before MDIO probing | |
512 | * has completed, since they might be turned off at that | |
513 | * time | |
514 | */ | |
515 | mode = of_get_phy_mode(port); | |
bedd00c8 FF |
516 | if (mode < 0) |
517 | continue; | |
518 | ||
519 | if (mode == PHY_INTERFACE_MODE_INTERNAL) | |
520 | priv->int_phy_mask |= 1 << port_num; | |
8b7c94e3 FF |
521 | |
522 | if (mode == PHY_INTERFACE_MODE_MOCA) | |
523 | priv->moca_port = port_num; | |
64ff2aef FF |
524 | |
525 | if (of_property_read_bool(port, "brcm,use-bcm-hdr")) | |
526 | priv->brcm_tag_mask |= 1 << port_num; | |
8b7c94e3 FF |
527 | } |
528 | } | |
529 | ||
461cd1b0 FF |
530 | static int bcm_sf2_mdio_register(struct dsa_switch *ds) |
531 | { | |
f458995b | 532 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
461cd1b0 FF |
533 | struct device_node *dn; |
534 | static int index; | |
535 | int err; | |
536 | ||
537 | /* Find our integrated MDIO bus node */ | |
538 | dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); | |
539 | priv->master_mii_bus = of_mdio_find_bus(dn); | |
540 | if (!priv->master_mii_bus) | |
541 | return -EPROBE_DEFER; | |
542 | ||
543 | get_device(&priv->master_mii_bus->dev); | |
544 | priv->master_mii_dn = dn; | |
545 | ||
546 | priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); | |
547 | if (!priv->slave_mii_bus) | |
548 | return -ENOMEM; | |
549 | ||
550 | priv->slave_mii_bus->priv = priv; | |
551 | priv->slave_mii_bus->name = "sf2 slave mii"; | |
552 | priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; | |
553 | priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; | |
554 | snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", | |
555 | index++); | |
556 | priv->slave_mii_bus->dev.of_node = dn; | |
557 | ||
558 | /* Include the pseudo-PHY address to divert reads towards our | |
559 | * workaround. This is only required for 7445D0, since 7445E0 | |
560 | * disconnects the internal switch pseudo-PHY such that we can use the | |
561 | * regular SWITCH_MDIO master controller instead. | |
562 | * | |
563 | * Here we flag the pseudo PHY as needing special treatment and would | |
564 | * otherwise make all other PHY read/writes go to the master MDIO bus | |
565 | * controller that comes with this switch backed by the "mdio-unimac" | |
566 | * driver. | |
567 | */ | |
568 | if (of_machine_is_compatible("brcm,bcm7445d0")) | |
569 | priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); | |
570 | else | |
571 | priv->indir_phy_mask = 0; | |
572 | ||
573 | ds->phys_mii_mask = priv->indir_phy_mask; | |
574 | ds->slave_mii_bus = priv->slave_mii_bus; | |
575 | priv->slave_mii_bus->parent = ds->dev->parent; | |
576 | priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; | |
577 | ||
578 | if (dn) | |
579 | err = of_mdiobus_register(priv->slave_mii_bus, dn); | |
580 | else | |
581 | err = mdiobus_register(priv->slave_mii_bus); | |
582 | ||
583 | if (err) | |
584 | of_node_put(dn); | |
585 | ||
586 | return err; | |
587 | } | |
588 | ||
589 | static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) | |
590 | { | |
591 | mdiobus_unregister(priv->slave_mii_bus); | |
592 | if (priv->master_mii_dn) | |
593 | of_node_put(priv->master_mii_dn); | |
594 | } | |
595 | ||
aa9aef77 FF |
596 | static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) |
597 | { | |
f458995b | 598 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
aa9aef77 FF |
599 | |
600 | /* The BCM7xxx PHY driver expects to find the integrated PHY revision | |
601 | * in bits 15:8 and the patch level in bits 7:0 which is exactly what | |
602 | * the REG_PHY_REVISION register layout is. | |
603 | */ | |
604 | ||
605 | return priv->hw_params.gphy_rev; | |
606 | } | |
607 | ||
246d7f77 FF |
608 | static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port, |
609 | struct phy_device *phydev) | |
610 | { | |
f458995b | 611 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
76da8706 | 612 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
246d7f77 FF |
613 | u32 id_mode_dis = 0, port_mode; |
614 | const char *str = NULL; | |
0fe99338 FF |
615 | u32 reg, offset; |
616 | ||
617 | if (priv->type == BCM7445_DEVICE_ID) | |
618 | offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); | |
619 | else | |
620 | offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); | |
246d7f77 FF |
621 | |
622 | switch (phydev->interface) { | |
623 | case PHY_INTERFACE_MODE_RGMII: | |
624 | str = "RGMII (no delay)"; | |
625 | id_mode_dis = 1; | |
626 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
627 | if (!str) | |
628 | str = "RGMII (TX delay)"; | |
629 | port_mode = EXT_GPHY; | |
630 | break; | |
631 | case PHY_INTERFACE_MODE_MII: | |
632 | str = "MII"; | |
633 | port_mode = EXT_EPHY; | |
634 | break; | |
635 | case PHY_INTERFACE_MODE_REVMII: | |
636 | str = "Reverse MII"; | |
637 | port_mode = EXT_REVMII; | |
638 | break; | |
639 | default: | |
7de1557c FF |
640 | /* All other PHYs: internal and MoCA */ |
641 | goto force_link; | |
642 | } | |
643 | ||
644 | /* If the link is down, just disable the interface to conserve power */ | |
645 | if (!phydev->link) { | |
646 | reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); | |
647 | reg &= ~RGMII_MODE_EN; | |
648 | reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); | |
246d7f77 FF |
649 | goto force_link; |
650 | } | |
651 | ||
652 | /* Clear id_mode_dis bit, and the existing port mode, but | |
653 | * make sure we enable the RGMII block for data to pass | |
654 | */ | |
655 | reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); | |
656 | reg &= ~ID_MODE_DIS; | |
657 | reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); | |
658 | reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); | |
659 | ||
660 | reg |= port_mode | RGMII_MODE_EN; | |
661 | if (id_mode_dis) | |
662 | reg |= ID_MODE_DIS; | |
663 | ||
664 | if (phydev->pause) { | |
665 | if (phydev->asym_pause) | |
666 | reg |= TX_PAUSE_EN; | |
667 | reg |= RX_PAUSE_EN; | |
668 | } | |
669 | ||
670 | reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); | |
671 | ||
672 | pr_info("Port %d configured for %s\n", port, str); | |
673 | ||
674 | force_link: | |
675 | /* Force link settings detected from the PHY */ | |
676 | reg = SW_OVERRIDE; | |
677 | switch (phydev->speed) { | |
678 | case SPEED_1000: | |
679 | reg |= SPDSTS_1000 << SPEED_SHIFT; | |
680 | break; | |
681 | case SPEED_100: | |
682 | reg |= SPDSTS_100 << SPEED_SHIFT; | |
683 | break; | |
684 | } | |
685 | ||
686 | if (phydev->link) | |
687 | reg |= LINK_STS; | |
688 | if (phydev->duplex == DUPLEX_FULL) | |
689 | reg |= DUPLX_MODE; | |
690 | ||
0fe99338 | 691 | core_writel(priv, reg, offset); |
76da8706 FF |
692 | |
693 | if (!phydev->is_pseudo_fixed_link) | |
694 | p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev); | |
246d7f77 FF |
695 | } |
696 | ||
697 | static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port, | |
698 | struct fixed_phy_status *status) | |
699 | { | |
f458995b | 700 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
0fe99338 | 701 | u32 duplex, pause, offset; |
246d7f77 FF |
702 | u32 reg; |
703 | ||
0fe99338 FF |
704 | if (priv->type == BCM7445_DEVICE_ID) |
705 | offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); | |
706 | else | |
707 | offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); | |
708 | ||
246d7f77 FF |
709 | duplex = core_readl(priv, CORE_DUPSTS); |
710 | pause = core_readl(priv, CORE_PAUSESTS); | |
246d7f77 FF |
711 | |
712 | status->link = 0; | |
713 | ||
8b7c94e3 | 714 | /* MoCA port is special as we do not get link status from CORE_LNKSTS, |
246d7f77 FF |
715 | * which means that we need to force the link at the port override |
716 | * level to get the data to flow. We do use what the interrupt handler | |
717 | * did determine before. | |
7855f675 FF |
718 | * |
719 | * For the other ports, we just force the link status, since this is | |
720 | * a fixed PHY device. | |
246d7f77 | 721 | */ |
8b7c94e3 | 722 | if (port == priv->moca_port) { |
246d7f77 | 723 | status->link = priv->port_sts[port].link; |
4ab7f913 FF |
724 | /* For MoCA interfaces, also force a link down notification |
725 | * since some version of the user-space daemon (mocad) use | |
726 | * cmd->autoneg to force the link, which messes up the PHY | |
727 | * state machine and make it go in PHY_FORCING state instead. | |
728 | */ | |
729 | if (!status->link) | |
c8b09808 | 730 | netif_carrier_off(ds->ports[port].netdev); |
246d7f77 FF |
731 | status->duplex = 1; |
732 | } else { | |
7855f675 | 733 | status->link = 1; |
246d7f77 FF |
734 | status->duplex = !!(duplex & (1 << port)); |
735 | } | |
736 | ||
0fe99338 | 737 | reg = core_readl(priv, offset); |
7855f675 FF |
738 | reg |= SW_OVERRIDE; |
739 | if (status->link) | |
740 | reg |= LINK_STS; | |
741 | else | |
742 | reg &= ~LINK_STS; | |
0fe99338 | 743 | core_writel(priv, reg, offset); |
7855f675 | 744 | |
246d7f77 FF |
745 | if ((pause & (1 << port)) && |
746 | (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) { | |
747 | status->asym_pause = 1; | |
748 | status->pause = 1; | |
749 | } | |
750 | ||
751 | if (pause & (1 << port)) | |
752 | status->pause = 1; | |
753 | } | |
754 | ||
8cfa9498 FF |
755 | static int bcm_sf2_sw_suspend(struct dsa_switch *ds) |
756 | { | |
f458995b | 757 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
8cfa9498 FF |
758 | unsigned int port; |
759 | ||
691c9a8f | 760 | bcm_sf2_intr_disable(priv); |
8cfa9498 FF |
761 | |
762 | /* Disable all ports physically present including the IMP | |
763 | * port, the other ones have already been disabled during | |
764 | * bcm_sf2_sw_setup | |
765 | */ | |
766 | for (port = 0; port < DSA_MAX_PORTS; port++) { | |
74c3e2a5 | 767 | if ((1 << port) & ds->enabled_port_mask || |
8cfa9498 | 768 | dsa_is_cpu_port(ds, port)) |
b6d045db | 769 | bcm_sf2_port_disable(ds, port, NULL); |
8cfa9498 FF |
770 | } |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
8cfa9498 FF |
775 | static int bcm_sf2_sw_resume(struct dsa_switch *ds) |
776 | { | |
f458995b | 777 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
8cfa9498 | 778 | unsigned int port; |
8cfa9498 FF |
779 | int ret; |
780 | ||
781 | ret = bcm_sf2_sw_rst(priv); | |
782 | if (ret) { | |
783 | pr_err("%s: failed to software reset switch\n", __func__); | |
784 | return ret; | |
785 | } | |
786 | ||
b083668c FF |
787 | if (priv->hw_params.num_gphy == 1) |
788 | bcm_sf2_gphy_enable_set(ds, true); | |
8cfa9498 FF |
789 | |
790 | for (port = 0; port < DSA_MAX_PORTS; port++) { | |
74c3e2a5 | 791 | if ((1 << port) & ds->enabled_port_mask) |
b6d045db | 792 | bcm_sf2_port_setup(ds, port, NULL); |
8cfa9498 FF |
793 | else if (dsa_is_cpu_port(ds, port)) |
794 | bcm_sf2_imp_setup(ds, port); | |
795 | } | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
96e65d7f FF |
800 | static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, |
801 | struct ethtool_wolinfo *wol) | |
802 | { | |
6d3c8c0d | 803 | struct net_device *p = ds->dst[ds->index].cpu_dp->netdev; |
f458995b | 804 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
96e65d7f FF |
805 | struct ethtool_wolinfo pwol; |
806 | ||
807 | /* Get the parent device WoL settings */ | |
808 | p->ethtool_ops->get_wol(p, &pwol); | |
809 | ||
810 | /* Advertise the parent device supported settings */ | |
811 | wol->supported = pwol.supported; | |
812 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
813 | ||
814 | if (pwol.wolopts & WAKE_MAGICSECURE) | |
815 | memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); | |
816 | ||
817 | if (priv->wol_ports_mask & (1 << port)) | |
818 | wol->wolopts = pwol.wolopts; | |
819 | else | |
820 | wol->wolopts = 0; | |
821 | } | |
822 | ||
823 | static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, | |
824 | struct ethtool_wolinfo *wol) | |
825 | { | |
6d3c8c0d | 826 | struct net_device *p = ds->dst[ds->index].cpu_dp->netdev; |
f458995b | 827 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
8b0d3ea5 | 828 | s8 cpu_port = ds->dst->cpu_dp->index; |
96e65d7f FF |
829 | struct ethtool_wolinfo pwol; |
830 | ||
831 | p->ethtool_ops->get_wol(p, &pwol); | |
832 | if (wol->wolopts & ~pwol.supported) | |
833 | return -EINVAL; | |
834 | ||
835 | if (wol->wolopts) | |
836 | priv->wol_ports_mask |= (1 << port); | |
837 | else | |
838 | priv->wol_ports_mask &= ~(1 << port); | |
839 | ||
840 | /* If we have at least one port enabled, make sure the CPU port | |
841 | * is also enabled. If the CPU port is the last one enabled, we disable | |
842 | * it since this configuration does not make sense. | |
843 | */ | |
844 | if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) | |
845 | priv->wol_ports_mask |= (1 << cpu_port); | |
846 | else | |
847 | priv->wol_ports_mask &= ~(1 << cpu_port); | |
848 | ||
849 | return p->ethtool_ops->set_wol(p, wol); | |
850 | } | |
851 | ||
de0b9d3b | 852 | static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv) |
9c57a771 | 853 | { |
de0b9d3b FF |
854 | unsigned int timeout = 10; |
855 | u32 reg; | |
9c57a771 | 856 | |
de0b9d3b FF |
857 | do { |
858 | reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL); | |
859 | if (!(reg & ARLA_VTBL_STDN)) | |
860 | return 0; | |
9c57a771 | 861 | |
de0b9d3b FF |
862 | usleep_range(1000, 2000); |
863 | } while (timeout--); | |
9c57a771 | 864 | |
de0b9d3b FF |
865 | return -ETIMEDOUT; |
866 | } | |
9c57a771 | 867 | |
de0b9d3b FF |
868 | static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op) |
869 | { | |
870 | core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL); | |
871 | ||
872 | return bcm_sf2_vlan_op_wait(priv); | |
9c57a771 FF |
873 | } |
874 | ||
875 | static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds) | |
876 | { | |
f458995b | 877 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
9c57a771 FF |
878 | unsigned int port; |
879 | ||
880 | /* Clear all VLANs */ | |
881 | bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR); | |
882 | ||
883 | for (port = 0; port < priv->hw_params.num_ports; port++) { | |
884 | if (!((1 << port) & ds->enabled_port_mask)) | |
885 | continue; | |
886 | ||
887 | core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port)); | |
888 | } | |
889 | } | |
890 | ||
7fbb1a92 FF |
891 | static int bcm_sf2_sw_setup(struct dsa_switch *ds) |
892 | { | |
f458995b | 893 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
7fbb1a92 | 894 | unsigned int port; |
d9338023 FF |
895 | |
896 | /* Enable all valid ports and disable those unused */ | |
897 | for (port = 0; port < priv->hw_params.num_ports; port++) { | |
898 | /* IMP port receives special treatment */ | |
899 | if ((1 << port) & ds->enabled_port_mask) | |
900 | bcm_sf2_port_setup(ds, port, NULL); | |
901 | else if (dsa_is_cpu_port(ds, port)) | |
902 | bcm_sf2_imp_setup(ds, port); | |
903 | else | |
904 | bcm_sf2_port_disable(ds, port, NULL); | |
905 | } | |
906 | ||
907 | bcm_sf2_sw_configure_vlan(ds); | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
f458995b FF |
912 | /* The SWITCH_CORE register space is managed by b53 but operates on a page + |
913 | * register basis so we need to translate that into an address that the | |
914 | * bus-glue understands. | |
915 | */ | |
916 | #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) | |
917 | ||
918 | static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, | |
919 | u8 *val) | |
920 | { | |
921 | struct bcm_sf2_priv *priv = dev->priv; | |
922 | ||
923 | *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
928 | static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, | |
929 | u16 *val) | |
930 | { | |
931 | struct bcm_sf2_priv *priv = dev->priv; | |
932 | ||
933 | *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, | |
939 | u32 *val) | |
940 | { | |
941 | struct bcm_sf2_priv *priv = dev->priv; | |
942 | ||
943 | *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
948 | static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, | |
949 | u64 *val) | |
950 | { | |
951 | struct bcm_sf2_priv *priv = dev->priv; | |
952 | ||
953 | *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, | |
959 | u8 value) | |
960 | { | |
961 | struct bcm_sf2_priv *priv = dev->priv; | |
962 | ||
963 | core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, | |
969 | u16 value) | |
970 | { | |
971 | struct bcm_sf2_priv *priv = dev->priv; | |
972 | ||
973 | core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, | |
979 | u32 value) | |
980 | { | |
981 | struct bcm_sf2_priv *priv = dev->priv; | |
982 | ||
983 | core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, | |
989 | u64 value) | |
990 | { | |
991 | struct bcm_sf2_priv *priv = dev->priv; | |
992 | ||
993 | core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
0e26e5bd | 998 | static struct b53_io_ops bcm_sf2_io_ops = { |
f458995b FF |
999 | .read8 = bcm_sf2_core_read8, |
1000 | .read16 = bcm_sf2_core_read16, | |
1001 | .read32 = bcm_sf2_core_read32, | |
1002 | .read48 = bcm_sf2_core_read64, | |
1003 | .read64 = bcm_sf2_core_read64, | |
1004 | .write8 = bcm_sf2_core_write8, | |
1005 | .write16 = bcm_sf2_core_write16, | |
1006 | .write32 = bcm_sf2_core_write32, | |
1007 | .write48 = bcm_sf2_core_write64, | |
1008 | .write64 = bcm_sf2_core_write64, | |
1009 | }; | |
1010 | ||
a82f67af | 1011 | static const struct dsa_switch_ops bcm_sf2_ops = { |
73095cb1 FF |
1012 | .get_tag_protocol = bcm_sf2_sw_get_tag_protocol, |
1013 | .setup = bcm_sf2_sw_setup, | |
1014 | .get_strings = b53_get_strings, | |
1015 | .get_ethtool_stats = b53_get_ethtool_stats, | |
1016 | .get_sset_count = b53_get_sset_count, | |
1017 | .get_phy_flags = bcm_sf2_sw_get_phy_flags, | |
1018 | .adjust_link = bcm_sf2_sw_adjust_link, | |
1019 | .fixed_link_update = bcm_sf2_sw_fixed_link_update, | |
1020 | .suspend = bcm_sf2_sw_suspend, | |
1021 | .resume = bcm_sf2_sw_resume, | |
1022 | .get_wol = bcm_sf2_sw_get_wol, | |
1023 | .set_wol = bcm_sf2_sw_set_wol, | |
1024 | .port_enable = bcm_sf2_port_setup, | |
1025 | .port_disable = bcm_sf2_port_disable, | |
1026 | .get_eee = bcm_sf2_sw_get_eee, | |
1027 | .set_eee = bcm_sf2_sw_set_eee, | |
1028 | .port_bridge_join = b53_br_join, | |
1029 | .port_bridge_leave = b53_br_leave, | |
1030 | .port_stp_state_set = b53_br_set_stp_state, | |
1031 | .port_fast_age = b53_br_fast_age, | |
1032 | .port_vlan_filtering = b53_vlan_filtering, | |
1033 | .port_vlan_prepare = b53_vlan_prepare, | |
1034 | .port_vlan_add = b53_vlan_add, | |
1035 | .port_vlan_del = b53_vlan_del, | |
1036 | .port_vlan_dump = b53_vlan_dump, | |
1037 | .port_fdb_prepare = b53_fdb_prepare, | |
1038 | .port_fdb_dump = b53_fdb_dump, | |
1039 | .port_fdb_add = b53_fdb_add, | |
1040 | .port_fdb_del = b53_fdb_del, | |
7318166c FF |
1041 | .get_rxnfc = bcm_sf2_get_rxnfc, |
1042 | .set_rxnfc = bcm_sf2_set_rxnfc, | |
ec960de6 FF |
1043 | .port_mirror_add = b53_mirror_add, |
1044 | .port_mirror_del = b53_mirror_del, | |
73095cb1 FF |
1045 | }; |
1046 | ||
a78e86ed FF |
1047 | struct bcm_sf2_of_data { |
1048 | u32 type; | |
1049 | const u16 *reg_offsets; | |
1050 | unsigned int core_reg_align; | |
df191632 | 1051 | unsigned int num_cfp_rules; |
a78e86ed FF |
1052 | }; |
1053 | ||
1054 | /* Register offsets for the SWITCH_REG_* block */ | |
1055 | static const u16 bcm_sf2_7445_reg_offsets[] = { | |
1056 | [REG_SWITCH_CNTRL] = 0x00, | |
1057 | [REG_SWITCH_STATUS] = 0x04, | |
1058 | [REG_DIR_DATA_WRITE] = 0x08, | |
1059 | [REG_DIR_DATA_READ] = 0x0C, | |
1060 | [REG_SWITCH_REVISION] = 0x18, | |
1061 | [REG_PHY_REVISION] = 0x1C, | |
1062 | [REG_SPHY_CNTRL] = 0x2C, | |
1063 | [REG_RGMII_0_CNTRL] = 0x34, | |
1064 | [REG_RGMII_1_CNTRL] = 0x40, | |
1065 | [REG_RGMII_2_CNTRL] = 0x4c, | |
1066 | [REG_LED_0_CNTRL] = 0x90, | |
1067 | [REG_LED_1_CNTRL] = 0x94, | |
1068 | [REG_LED_2_CNTRL] = 0x98, | |
1069 | }; | |
1070 | ||
1071 | static const struct bcm_sf2_of_data bcm_sf2_7445_data = { | |
1072 | .type = BCM7445_DEVICE_ID, | |
1073 | .core_reg_align = 0, | |
1074 | .reg_offsets = bcm_sf2_7445_reg_offsets, | |
df191632 | 1075 | .num_cfp_rules = 256, |
a78e86ed FF |
1076 | }; |
1077 | ||
0fe99338 FF |
1078 | static const u16 bcm_sf2_7278_reg_offsets[] = { |
1079 | [REG_SWITCH_CNTRL] = 0x00, | |
1080 | [REG_SWITCH_STATUS] = 0x04, | |
1081 | [REG_DIR_DATA_WRITE] = 0x08, | |
1082 | [REG_DIR_DATA_READ] = 0x0c, | |
1083 | [REG_SWITCH_REVISION] = 0x10, | |
1084 | [REG_PHY_REVISION] = 0x14, | |
1085 | [REG_SPHY_CNTRL] = 0x24, | |
1086 | [REG_RGMII_0_CNTRL] = 0xe0, | |
1087 | [REG_RGMII_1_CNTRL] = 0xec, | |
1088 | [REG_RGMII_2_CNTRL] = 0xf8, | |
1089 | [REG_LED_0_CNTRL] = 0x40, | |
1090 | [REG_LED_1_CNTRL] = 0x4c, | |
1091 | [REG_LED_2_CNTRL] = 0x58, | |
1092 | }; | |
1093 | ||
1094 | static const struct bcm_sf2_of_data bcm_sf2_7278_data = { | |
1095 | .type = BCM7278_DEVICE_ID, | |
1096 | .core_reg_align = 1, | |
1097 | .reg_offsets = bcm_sf2_7278_reg_offsets, | |
df191632 | 1098 | .num_cfp_rules = 128, |
0fe99338 FF |
1099 | }; |
1100 | ||
a78e86ed FF |
1101 | static const struct of_device_id bcm_sf2_of_match[] = { |
1102 | { .compatible = "brcm,bcm7445-switch-v4.0", | |
1103 | .data = &bcm_sf2_7445_data | |
1104 | }, | |
0fe99338 FF |
1105 | { .compatible = "brcm,bcm7278-switch-v4.0", |
1106 | .data = &bcm_sf2_7278_data | |
1107 | }, | |
a78e86ed FF |
1108 | { /* sentinel */ }, |
1109 | }; | |
1110 | MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); | |
1111 | ||
d9338023 FF |
1112 | static int bcm_sf2_sw_probe(struct platform_device *pdev) |
1113 | { | |
1114 | const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; | |
1115 | struct device_node *dn = pdev->dev.of_node; | |
a78e86ed FF |
1116 | const struct of_device_id *of_id = NULL; |
1117 | const struct bcm_sf2_of_data *data; | |
f458995b | 1118 | struct b53_platform_data *pdata; |
a4c61b92 | 1119 | struct dsa_switch_ops *ops; |
d9338023 | 1120 | struct bcm_sf2_priv *priv; |
f458995b | 1121 | struct b53_device *dev; |
d9338023 FF |
1122 | struct dsa_switch *ds; |
1123 | void __iomem **base; | |
4bd11675 | 1124 | struct resource *r; |
7fbb1a92 FF |
1125 | unsigned int i; |
1126 | u32 reg, rev; | |
1127 | int ret; | |
1128 | ||
f458995b FF |
1129 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
1130 | if (!priv) | |
1131 | return -ENOMEM; | |
1132 | ||
a4c61b92 FF |
1133 | ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); |
1134 | if (!ops) | |
1135 | return -ENOMEM; | |
1136 | ||
f458995b FF |
1137 | dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); |
1138 | if (!dev) | |
d9338023 FF |
1139 | return -ENOMEM; |
1140 | ||
f458995b FF |
1141 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
1142 | if (!pdata) | |
1143 | return -ENOMEM; | |
1144 | ||
a78e86ed FF |
1145 | of_id = of_match_node(bcm_sf2_of_match, dn); |
1146 | if (!of_id || !of_id->data) | |
1147 | return -EINVAL; | |
1148 | ||
1149 | data = of_id->data; | |
1150 | ||
1151 | /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ | |
1152 | priv->type = data->type; | |
1153 | priv->reg_offsets = data->reg_offsets; | |
1154 | priv->core_reg_align = data->core_reg_align; | |
df191632 | 1155 | priv->num_cfp_rules = data->num_cfp_rules; |
a78e86ed | 1156 | |
f458995b FF |
1157 | /* Auto-detection using standard registers will not work, so |
1158 | * provide an indication of what kind of device we are for | |
1159 | * b53_common to work with | |
1160 | */ | |
a78e86ed | 1161 | pdata->chip_id = priv->type; |
f458995b FF |
1162 | dev->pdata = pdata; |
1163 | ||
1164 | priv->dev = dev; | |
1165 | ds = dev->ds; | |
73095cb1 | 1166 | ds->ops = &bcm_sf2_ops; |
d9338023 | 1167 | |
f458995b | 1168 | dev_set_drvdata(&pdev->dev, priv); |
d9338023 | 1169 | |
7fbb1a92 FF |
1170 | spin_lock_init(&priv->indir_lock); |
1171 | mutex_init(&priv->stats_mutex); | |
7318166c FF |
1172 | mutex_init(&priv->cfp.lock); |
1173 | ||
1174 | /* CFP rule #0 cannot be used for specific classifications, flag it as | |
1175 | * permanently used | |
1176 | */ | |
1177 | set_bit(0, priv->cfp.used); | |
7fbb1a92 | 1178 | |
d9338023 | 1179 | bcm_sf2_identify_ports(priv, dn->child); |
7fbb1a92 FF |
1180 | |
1181 | priv->irq0 = irq_of_parse_and_map(dn, 0); | |
1182 | priv->irq1 = irq_of_parse_and_map(dn, 1); | |
1183 | ||
1184 | base = &priv->core; | |
1185 | for (i = 0; i < BCM_SF2_REGS_NUM; i++) { | |
4bd11675 FF |
1186 | r = platform_get_resource(pdev, IORESOURCE_MEM, i); |
1187 | *base = devm_ioremap_resource(&pdev->dev, r); | |
1188 | if (IS_ERR(*base)) { | |
7fbb1a92 | 1189 | pr_err("unable to find register: %s\n", reg_names[i]); |
4bd11675 | 1190 | return PTR_ERR(*base); |
7fbb1a92 FF |
1191 | } |
1192 | base++; | |
1193 | } | |
1194 | ||
1195 | ret = bcm_sf2_sw_rst(priv); | |
1196 | if (ret) { | |
1197 | pr_err("unable to software reset switch: %d\n", ret); | |
4bd11675 | 1198 | return ret; |
7fbb1a92 FF |
1199 | } |
1200 | ||
1201 | ret = bcm_sf2_mdio_register(ds); | |
1202 | if (ret) { | |
1203 | pr_err("failed to register MDIO bus\n"); | |
4bd11675 | 1204 | return ret; |
7fbb1a92 FF |
1205 | } |
1206 | ||
7318166c FF |
1207 | ret = bcm_sf2_cfp_rst(priv); |
1208 | if (ret) { | |
1209 | pr_err("failed to reset CFP\n"); | |
1210 | goto out_mdio; | |
1211 | } | |
1212 | ||
7fbb1a92 FF |
1213 | /* Disable all interrupts and request them */ |
1214 | bcm_sf2_intr_disable(priv); | |
1215 | ||
4bd11675 FF |
1216 | ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, |
1217 | "switch_0", priv); | |
7fbb1a92 FF |
1218 | if (ret < 0) { |
1219 | pr_err("failed to request switch_0 IRQ\n"); | |
bb9c0fa3 | 1220 | goto out_mdio; |
7fbb1a92 FF |
1221 | } |
1222 | ||
4bd11675 FF |
1223 | ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, |
1224 | "switch_1", priv); | |
7fbb1a92 FF |
1225 | if (ret < 0) { |
1226 | pr_err("failed to request switch_1 IRQ\n"); | |
4bd11675 | 1227 | goto out_mdio; |
7fbb1a92 FF |
1228 | } |
1229 | ||
1230 | /* Reset the MIB counters */ | |
1231 | reg = core_readl(priv, CORE_GMNCFGCFG); | |
1232 | reg |= RST_MIB_CNT; | |
1233 | core_writel(priv, reg, CORE_GMNCFGCFG); | |
1234 | reg &= ~RST_MIB_CNT; | |
1235 | core_writel(priv, reg, CORE_GMNCFGCFG); | |
1236 | ||
1237 | /* Get the maximum number of ports for this switch */ | |
1238 | priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; | |
1239 | if (priv->hw_params.num_ports > DSA_MAX_PORTS) | |
1240 | priv->hw_params.num_ports = DSA_MAX_PORTS; | |
1241 | ||
1242 | /* Assume a single GPHY setup if we can't read that property */ | |
1243 | if (of_property_read_u32(dn, "brcm,num-gphy", | |
1244 | &priv->hw_params.num_gphy)) | |
1245 | priv->hw_params.num_gphy = 1; | |
1246 | ||
7fbb1a92 FF |
1247 | rev = reg_readl(priv, REG_SWITCH_REVISION); |
1248 | priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & | |
1249 | SWITCH_TOP_REV_MASK; | |
1250 | priv->hw_params.core_rev = (rev & SF2_REV_MASK); | |
1251 | ||
1252 | rev = reg_readl(priv, REG_PHY_REVISION); | |
1253 | priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; | |
1254 | ||
f458995b | 1255 | ret = b53_switch_register(dev); |
d9338023 | 1256 | if (ret) |
4bd11675 | 1257 | goto out_mdio; |
d9338023 | 1258 | |
7fbb1a92 FF |
1259 | pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n", |
1260 | priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, | |
1261 | priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, | |
1262 | priv->core, priv->irq0, priv->irq1); | |
1263 | ||
1264 | return 0; | |
1265 | ||
bb9c0fa3 FF |
1266 | out_mdio: |
1267 | bcm_sf2_mdio_unregister(priv); | |
7fbb1a92 FF |
1268 | return ret; |
1269 | } | |
1270 | ||
d9338023 | 1271 | static int bcm_sf2_sw_remove(struct platform_device *pdev) |
246d7f77 | 1272 | { |
f458995b | 1273 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); |
d9338023 FF |
1274 | |
1275 | /* Disable all ports and interrupts */ | |
1276 | priv->wol_ports_mask = 0; | |
f458995b FF |
1277 | bcm_sf2_sw_suspend(priv->dev->ds); |
1278 | dsa_unregister_switch(priv->dev->ds); | |
d9338023 | 1279 | bcm_sf2_mdio_unregister(priv); |
246d7f77 FF |
1280 | |
1281 | return 0; | |
1282 | } | |
246d7f77 | 1283 | |
2399d614 FF |
1284 | static void bcm_sf2_sw_shutdown(struct platform_device *pdev) |
1285 | { | |
1286 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); | |
1287 | ||
1288 | /* For a kernel about to be kexec'd we want to keep the GPHY on for a | |
1289 | * successful MDIO bus scan to occur. If we did turn off the GPHY | |
1290 | * before (e.g: port_disable), this will also power it back on. | |
4a2947e3 FF |
1291 | * |
1292 | * Do not rely on kexec_in_progress, just power the PHY on. | |
2399d614 FF |
1293 | */ |
1294 | if (priv->hw_params.num_gphy == 1) | |
4a2947e3 | 1295 | bcm_sf2_gphy_enable_set(priv->dev->ds, true); |
2399d614 FF |
1296 | } |
1297 | ||
d9338023 FF |
1298 | #ifdef CONFIG_PM_SLEEP |
1299 | static int bcm_sf2_suspend(struct device *dev) | |
246d7f77 | 1300 | { |
d9338023 | 1301 | struct platform_device *pdev = to_platform_device(dev); |
f458995b | 1302 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); |
d9338023 | 1303 | |
f458995b | 1304 | return dsa_switch_suspend(priv->dev->ds); |
246d7f77 | 1305 | } |
d9338023 FF |
1306 | |
1307 | static int bcm_sf2_resume(struct device *dev) | |
1308 | { | |
1309 | struct platform_device *pdev = to_platform_device(dev); | |
f458995b | 1310 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); |
d9338023 | 1311 | |
f458995b | 1312 | return dsa_switch_resume(priv->dev->ds); |
d9338023 FF |
1313 | } |
1314 | #endif /* CONFIG_PM_SLEEP */ | |
1315 | ||
1316 | static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, | |
1317 | bcm_sf2_suspend, bcm_sf2_resume); | |
1318 | ||
d9338023 FF |
1319 | |
1320 | static struct platform_driver bcm_sf2_driver = { | |
1321 | .probe = bcm_sf2_sw_probe, | |
1322 | .remove = bcm_sf2_sw_remove, | |
2399d614 | 1323 | .shutdown = bcm_sf2_sw_shutdown, |
d9338023 FF |
1324 | .driver = { |
1325 | .name = "brcm-sf2", | |
1326 | .of_match_table = bcm_sf2_of_match, | |
1327 | .pm = &bcm_sf2_pm_ops, | |
1328 | }, | |
1329 | }; | |
1330 | module_platform_driver(bcm_sf2_driver); | |
246d7f77 FF |
1331 | |
1332 | MODULE_AUTHOR("Broadcom Corporation"); | |
1333 | MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); | |
1334 | MODULE_LICENSE("GPL"); | |
1335 | MODULE_ALIAS("platform:brcm-sf2"); |