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Merge tag 'libata-5.10-2020-10-24' of git://git.kernel.dk/linux-block
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / dsa / lantiq_gswip.c
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HM		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Lantiq / Intel GSWIP switch driver for VRX200 SoCs
4 *
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
8206e0ce
HM		 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
8 *
9 * The VLAN and bridge model the GSWIP hardware uses does not directly
10 * matches the model DSA uses.
11 *
12 * The hardware has 64 possible table entries for bridges with one VLAN
13 * ID, one flow id and a list of ports for each bridge. All entries which
14 * match the same flow ID are combined in the mac learning table, they
15 * act as one global bridge.
16 * The hardware does not support VLAN filter on the port, but on the
17 * bridge, this driver converts the DSA model to the hardware.
18 *
19 * The CPU gets all the exception frames which do not match any forwarding
20 * rule and the CPU port is also added to all bridges. This makes it possible
21 * to handle all the special cases easily in software.
22 * At the initialization the driver allocates one bridge table entry for
23 * each switch port which is used when the port is used without an
24 * explicit bridge. This prevents the frames from being forwarded
25 * between all LAN ports by default.
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HM		 26 */
27
28#include <linux/clk.h>
29#include <linux/etherdevice.h>
30#include <linux/firmware.h>
31#include <linux/if_bridge.h>
32#include <linux/if_vlan.h>
33#include <linux/iopoll.h>
34#include <linux/mfd/syscon.h>
35#include <linux/module.h>
36#include <linux/of_mdio.h>
37#include <linux/of_net.h>
38#include <linux/of_platform.h>
39#include <linux/phy.h>
40#include <linux/phylink.h>
41#include <linux/platform_device.h>
42#include <linux/regmap.h>
43#include <linux/reset.h>
44#include <net/dsa.h>
45#include <dt-bindings/mips/lantiq_rcu_gphy.h>
46
47#include "lantiq_pce.h"
48
49/* GSWIP MDIO Registers */
50#define GSWIP_MDIO_GLOB 0x00
51#define GSWIP_MDIO_GLOB_ENABLE BIT(15)
52#define GSWIP_MDIO_CTRL 0x08
53#define GSWIP_MDIO_CTRL_BUSY BIT(12)
54#define GSWIP_MDIO_CTRL_RD BIT(11)
55#define GSWIP_MDIO_CTRL_WR BIT(10)
56#define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
57#define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
58#define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
59#define GSWIP_MDIO_READ 0x09
60#define GSWIP_MDIO_WRITE 0x0A
61#define GSWIP_MDIO_MDC_CFG0 0x0B
62#define GSWIP_MDIO_MDC_CFG1 0x0C
63#define GSWIP_MDIO_PHYp(p) (0x15 - (p))
64#define GSWIP_MDIO_PHY_LINK_MASK 0x6000
65#define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
66#define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
67#define GSWIP_MDIO_PHY_LINK_UP 0x2000
68#define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
69#define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
70#define GSWIP_MDIO_PHY_SPEED_M10 0x0000
71#define GSWIP_MDIO_PHY_SPEED_M100 0x0800
72#define GSWIP_MDIO_PHY_SPEED_G1 0x1000
73#define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
74#define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
75#define GSWIP_MDIO_PHY_FDUP_EN 0x0200
76#define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
77#define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
78#define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
79#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
80#define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
81#define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
82#define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
83#define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
84#define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
85#define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
86#define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
87 GSWIP_MDIO_PHY_FCONRX_MASK | \
88 GSWIP_MDIO_PHY_FCONTX_MASK | \
89 GSWIP_MDIO_PHY_LINK_MASK | \
90 GSWIP_MDIO_PHY_SPEED_MASK | \
91 GSWIP_MDIO_PHY_FDUP_MASK)
92
93/* GSWIP MII Registers */
94#define GSWIP_MII_CFG0 0x00
95#define GSWIP_MII_CFG1 0x02
96#define GSWIP_MII_CFG5 0x04
97#define GSWIP_MII_CFG_EN BIT(14)
98#define GSWIP_MII_CFG_LDCLKDIS BIT(12)
99#define GSWIP_MII_CFG_MODE_MIIP 0x0
100#define GSWIP_MII_CFG_MODE_MIIM 0x1
101#define GSWIP_MII_CFG_MODE_RMIIP 0x2
102#define GSWIP_MII_CFG_MODE_RMIIM 0x3
103#define GSWIP_MII_CFG_MODE_RGMII 0x4
104#define GSWIP_MII_CFG_MODE_MASK 0xf
105#define GSWIP_MII_CFG_RATE_M2P5 0x00
106#define GSWIP_MII_CFG_RATE_M25 0x10
107#define GSWIP_MII_CFG_RATE_M125 0x20
108#define GSWIP_MII_CFG_RATE_M50 0x30
109#define GSWIP_MII_CFG_RATE_AUTO 0x40
110#define GSWIP_MII_CFG_RATE_MASK 0x70
111#define GSWIP_MII_PCDU0 0x01
112#define GSWIP_MII_PCDU1 0x03
113#define GSWIP_MII_PCDU5 0x05
114#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
115#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
116
117/* GSWIP Core Registers */
118#define GSWIP_SWRES 0x000
119#define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
120#define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
121#define GSWIP_VERSION 0x013
122#define GSWIP_VERSION_REV_SHIFT 0
123#define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
124#define GSWIP_VERSION_MOD_SHIFT 8
125#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
126#define GSWIP_VERSION_2_0 0x100
127#define GSWIP_VERSION_2_1 0x021
128#define GSWIP_VERSION_2_2 0x122
129#define GSWIP_VERSION_2_2_ETC 0x022
130
131#define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
132#define GSWIP_BM_RAM_ADDR 0x044
133#define GSWIP_BM_RAM_CTRL 0x045
134#define GSWIP_BM_RAM_CTRL_BAS BIT(15)
135#define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
136#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
137#define GSWIP_BM_QUEUE_GCTRL 0x04A
138#define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
139/* buffer management Port Configuration Register */
140#define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
141#define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
142#define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
143/* buffer management Port Control Register */
144#define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
145#define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
146#define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
147
148/* PCE */
149#define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
150#define GSWIP_PCE_TBL_MASK 0x448
151#define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
152#define GSWIP_PCE_TBL_ADDR 0x44E
153#define GSWIP_PCE_TBL_CTRL 0x44F
154#define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
155#define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
156#define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
157#define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
158#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
159#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
160#define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
161#define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
162#define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
163#define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
164#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
165#define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
166#define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
167#define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
168#define GSWIP_PCE_GCTRL_0 0x456
8206e0ce 169#define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
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HM		 170#define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
171#define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
172#define GSWIP_PCE_GCTRL_1 0x457
173#define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
174#define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
175#define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
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HM		 176#define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
177#define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
178#define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
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HM		 179#define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
180#define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
181#define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
182#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
183#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
184#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
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HM		 185#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
186#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
187#define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
188#define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
189#define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
190#define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
191#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
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HM		 192
193#define GSWIP_MAC_FLEN 0x8C5
194#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
195#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
196
197/* Ethernet Switch Fetch DMA Port Control Register */
198#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
199#define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
200#define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
201#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
202#define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
203#define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
204#define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
205#define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
206#define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
207
208/* Ethernet Switch Store DMA Port Control Register */
209#define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
210#define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
211#define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
212#define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */
213
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HM		 214#define GSWIP_TABLE_ACTIVE_VLAN 0x01
215#define GSWIP_TABLE_VLAN_MAPPING 0x02
45813481
HM		 216#define GSWIP_TABLE_MAC_BRIDGE 0x0b
217#define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
8206e0ce 218
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HM		 219#define XRX200_GPHY_FW_ALIGN (16 * 1024)
220
221struct gswip_hw_info {
222 int max_ports;
223 int cpu_port;
224};
225
226struct xway_gphy_match_data {
227 char *fe_firmware_name;
228 char *ge_firmware_name;
229};
230
231struct gswip_gphy_fw {
232 struct clk *clk_gate;
233 struct reset_control *reset;
234 u32 fw_addr_offset;
235 char *fw_name;
236};
237
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HM		 238struct gswip_vlan {
239 struct net_device *bridge;
240 u16 vid;
241 u8 fid;
242};
243
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HM		 244struct gswip_priv {
245 __iomem void *gswip;
246 __iomem void *mdio;
247 __iomem void *mii;
248 const struct gswip_hw_info *hw_info;
249 const struct xway_gphy_match_data *gphy_fw_name_cfg;
250 struct dsa_switch *ds;
251 struct device *dev;
252 struct regmap *rcu_regmap;
8206e0ce 253 struct gswip_vlan vlans[64];
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HM		 254 int num_gphy_fw;
255 struct gswip_gphy_fw *gphy_fw;
9bbb1c05 256 u32 port_vlan_filter;
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HM		 257};
258
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HM		 259struct gswip_pce_table_entry {
260 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
261 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
262 u16 key[8];
263 u16 val[5];
264 u16 mask;
265 u8 gmap;
266 bool type;
267 bool valid;
268 bool key_mode;
269};
270
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HM		 271struct gswip_rmon_cnt_desc {
272 unsigned int size;
273 unsigned int offset;
274 const char *name;
275};
276
277#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
278
279static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
280 /** Receive Packet Count (only packets that are accepted and not discarded). */
281 MIB_DESC(1, 0x1F, "RxGoodPkts"),
282 MIB_DESC(1, 0x23, "RxUnicastPkts"),
283 MIB_DESC(1, 0x22, "RxMulticastPkts"),
284 MIB_DESC(1, 0x21, "RxFCSErrorPkts"),
285 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"),
286 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"),
287 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"),
288 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"),
289 MIB_DESC(1, 0x20, "RxGoodPausePkts"),
290 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"),
291 MIB_DESC(1, 0x12, "Rx64BytePkts"),
292 MIB_DESC(1, 0x13, "Rx127BytePkts"),
293 MIB_DESC(1, 0x14, "Rx255BytePkts"),
294 MIB_DESC(1, 0x15, "Rx511BytePkts"),
295 MIB_DESC(1, 0x16, "Rx1023BytePkts"),
296 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
297 MIB_DESC(1, 0x17, "RxMaxBytePkts"),
298 MIB_DESC(1, 0x18, "RxDroppedPkts"),
299 MIB_DESC(1, 0x19, "RxFilteredPkts"),
300 MIB_DESC(2, 0x24, "RxGoodBytes"),
301 MIB_DESC(2, 0x26, "RxBadBytes"),
302 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"),
303 MIB_DESC(1, 0x0C, "TxGoodPkts"),
304 MIB_DESC(1, 0x06, "TxUnicastPkts"),
305 MIB_DESC(1, 0x07, "TxMulticastPkts"),
306 MIB_DESC(1, 0x00, "Tx64BytePkts"),
307 MIB_DESC(1, 0x01, "Tx127BytePkts"),
308 MIB_DESC(1, 0x02, "Tx255BytePkts"),
309 MIB_DESC(1, 0x03, "Tx511BytePkts"),
310 MIB_DESC(1, 0x04, "Tx1023BytePkts"),
311 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
312 MIB_DESC(1, 0x05, "TxMaxBytePkts"),
313 MIB_DESC(1, 0x08, "TxSingleCollCount"),
314 MIB_DESC(1, 0x09, "TxMultCollCount"),
315 MIB_DESC(1, 0x0A, "TxLateCollCount"),
316 MIB_DESC(1, 0x0B, "TxExcessCollCount"),
317 MIB_DESC(1, 0x0D, "TxPauseCount"),
318 MIB_DESC(1, 0x10, "TxDroppedPkts"),
319 MIB_DESC(2, 0x0E, "TxGoodBytes"),
320};
321
322static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset)
323{
324 return __raw_readl(priv->gswip + (offset * 4));
325}
326
327static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset)
328{
329 __raw_writel(val, priv->gswip + (offset * 4));
330}
331
332static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
333 u32 offset)
334{
335 u32 val = gswip_switch_r(priv, offset);
336
337 val &= ~(clear);
338 val |= set;
339 gswip_switch_w(priv, val, offset);
340}
341
342static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
343 u32 cleared)
344{
345 u32 val;
346
347 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val,
348 (val & cleared) == 0, 20, 50000);
349}
350
351static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset)
352{
353 return __raw_readl(priv->mdio + (offset * 4));
354}
355
356static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset)
357{
358 __raw_writel(val, priv->mdio + (offset * 4));
359}
360
361static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
362 u32 offset)
363{
364 u32 val = gswip_mdio_r(priv, offset);
365
366 val &= ~(clear);
367 val |= set;
368 gswip_mdio_w(priv, val, offset);
369}
370
371static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset)
372{
373 return __raw_readl(priv->mii + (offset * 4));
374}
375
376static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset)
377{
378 __raw_writel(val, priv->mii + (offset * 4));
379}
380
381static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
382 u32 offset)
383{
384 u32 val = gswip_mii_r(priv, offset);
385
386 val &= ~(clear);
387 val |= set;
388 gswip_mii_w(priv, val, offset);
389}
390
391static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
392 int port)
393{
394 switch (port) {
395 case 0:
396 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0);
397 break;
398 case 1:
399 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1);
400 break;
401 case 5:
402 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5);
403 break;
404 }
405}
406
407static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
408 int port)
409{
410 switch (port) {
411 case 0:
412 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
413 break;
414 case 1:
415 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
416 break;
417 case 5:
418 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
419 break;
420 }
421}
422
423static int gswip_mdio_poll(struct gswip_priv *priv)
424{
425 int cnt = 100;
426
427 while (likely(cnt--)) {
428 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL);
429
430 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0)
431 return 0;
432 usleep_range(20, 40);
433 }
434
435 return -ETIMEDOUT;
436}
437
438static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
439{
440 struct gswip_priv *priv = bus->priv;
441 int err;
442
443 err = gswip_mdio_poll(priv);
444 if (err) {
445 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
446 return err;
447 }
448
449 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE);
450 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR |
451 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
452 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
453 GSWIP_MDIO_CTRL);
454
455 return 0;
456}
457
458static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)
459{
460 struct gswip_priv *priv = bus->priv;
461 int err;
462
463 err = gswip_mdio_poll(priv);
464 if (err) {
465 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
466 return err;
467 }
468
469 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD |
470 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) |
471 (reg & GSWIP_MDIO_CTRL_REGAD_MASK),
472 GSWIP_MDIO_CTRL);
473
474 err = gswip_mdio_poll(priv);
475 if (err) {
476 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n");
477 return err;
478 }
479
480 return gswip_mdio_r(priv, GSWIP_MDIO_READ);
481}
482
483static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)
484{
485 struct dsa_switch *ds = priv->ds;
486
487 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev);
488 if (!ds->slave_mii_bus)
489 return -ENOMEM;
490
491 ds->slave_mii_bus->priv = priv;
492 ds->slave_mii_bus->read = gswip_mdio_rd;
493 ds->slave_mii_bus->write = gswip_mdio_wr;
494 ds->slave_mii_bus->name = "lantiq,xrx200-mdio";
495 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii",
496 dev_name(priv->dev));
497 ds->slave_mii_bus->parent = priv->dev;
498 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
499
500 return of_mdiobus_register(ds->slave_mii_bus, mdio_np);
501}
502
8206e0ce
HM		 503static int gswip_pce_table_entry_read(struct gswip_priv *priv,
504 struct gswip_pce_table_entry *tbl)
505{
506 int i;
507 int err;
508 u16 crtl;
509 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD :
510 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD;
511
512 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
513 GSWIP_PCE_TBL_CTRL_BAS);
514 if (err)
515 return err;
516
517 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
518 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
519 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
520 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
521 GSWIP_PCE_TBL_CTRL);
522
523 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
524 GSWIP_PCE_TBL_CTRL_BAS);
525 if (err)
526 return err;
527
528 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
529 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i));
530
531 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
532 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i));
533
534 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK);
535
536 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
537
538 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE);
539 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD);
540 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7;
541
542 return 0;
543}
544
545static int gswip_pce_table_entry_write(struct gswip_priv *priv,
546 struct gswip_pce_table_entry *tbl)
547{
548 int i;
549 int err;
550 u16 crtl;
551 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR :
552 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR;
553
554 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
555 GSWIP_PCE_TBL_CTRL_BAS);
556 if (err)
557 return err;
558
559 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR);
560 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
561 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
562 tbl->table | addr_mode,
563 GSWIP_PCE_TBL_CTRL);
564
565 for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
566 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i));
567
568 for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
569 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i));
570
571 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
572 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
573 tbl->table | addr_mode,
574 GSWIP_PCE_TBL_CTRL);
575
576 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK);
577
578 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL);
579 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD |
580 GSWIP_PCE_TBL_CTRL_GMAP_MASK);
581 if (tbl->type)
582 crtl |= GSWIP_PCE_TBL_CTRL_TYPE;
583 if (tbl->valid)
584 crtl |= GSWIP_PCE_TBL_CTRL_VLD;
585 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK;
586 crtl |= GSWIP_PCE_TBL_CTRL_BAS;
587 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL);
588
589 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
590 GSWIP_PCE_TBL_CTRL_BAS);
591}
592
593/* Add the LAN port into a bridge with the CPU port by
594 * default. This prevents automatic forwarding of
595 * packages between the LAN ports when no explicit
596 * bridge is configured.
597 */
598static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
599{
600 struct gswip_pce_table_entry vlan_active = {0,};
601 struct gswip_pce_table_entry vlan_mapping = {0,};
602 unsigned int cpu_port = priv->hw_info->cpu_port;
603 unsigned int max_ports = priv->hw_info->max_ports;
604 int err;
605
606 if (port >= max_ports) {
607 dev_err(priv->dev, "single port for %i supported\n", port);
608 return -EIO;
609 }
610
611 vlan_active.index = port + 1;
612 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
613 vlan_active.key[0] = 0; /* vid */
614 vlan_active.val[0] = port + 1 /* fid */;
615 vlan_active.valid = add;
616 err = gswip_pce_table_entry_write(priv, &vlan_active);
617 if (err) {
618 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
619 return err;
620 }
621
622 if (!add)
623 return 0;
624
625 vlan_mapping.index = port + 1;
626 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
627 vlan_mapping.val[0] = 0 /* vid */;
628 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
629 vlan_mapping.val[2] = 0;
630 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
631 if (err) {
632 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
633 return err;
634 }
635
636 return 0;
637}
638
14fceff4
HM		 639static int gswip_port_enable(struct dsa_switch *ds, int port,
640 struct phy_device *phydev)
641{
642 struct gswip_priv *priv = ds->priv;
8206e0ce
HM		 643 int err;
644
74be4bab
VD		 645 if (!dsa_is_user_port(ds, port))
646 return 0;
647
8206e0ce
HM		 648 if (!dsa_is_cpu_port(ds, port)) {
649 err = gswip_add_single_port_br(priv, port, true);
650 if (err)
651 return err;
652 }
14fceff4
HM		 653
654 /* RMON Counter Enable for port */
655 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port));
656
657 /* enable port fetch/store dma & VLAN Modification */
658 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN |
659 GSWIP_FDMA_PCTRL_VLANMOD_BOTH,
660 GSWIP_FDMA_PCTRLp(port));
661 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
662 GSWIP_SDMA_PCTRLp(port));
14fceff4
HM		 663
664 if (!dsa_is_cpu_port(ds, port)) {
665 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO |
666 GSWIP_MDIO_PHY_SPEED_AUTO |
667 GSWIP_MDIO_PHY_FDUP_AUTO |
668 GSWIP_MDIO_PHY_FCONTX_AUTO |
669 GSWIP_MDIO_PHY_FCONRX_AUTO |
670 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK);
671
672 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port));
673 /* Activate MDIO auto polling */
674 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0);
675 }
676
677 return 0;
678}
679
75104db0 680static void gswip_port_disable(struct dsa_switch *ds, int port)
14fceff4
HM		 681{
682 struct gswip_priv *priv = ds->priv;
683
74be4bab
VD		 684 if (!dsa_is_user_port(ds, port))
685 return;
686
14fceff4
HM		 687 if (!dsa_is_cpu_port(ds, port)) {
688 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN,
689 GSWIP_MDIO_PHY_LINK_MASK,
690 GSWIP_MDIO_PHYp(port));
691 /* Deactivate MDIO auto polling */
692 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0);
693 }
694
695 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
696 GSWIP_FDMA_PCTRLp(port));
697 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
698 GSWIP_SDMA_PCTRLp(port));
699}
700
701static int gswip_pce_load_microcode(struct gswip_priv *priv)
702{
703 int i;
704 int err;
705
706 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
707 GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
708 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
709 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
710
711 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
712 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
713 gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
714 GSWIP_PCE_TBL_VAL(0));
715 gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
716 GSWIP_PCE_TBL_VAL(1));
717 gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
718 GSWIP_PCE_TBL_VAL(2));
719 gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
720 GSWIP_PCE_TBL_VAL(3));
721
722 /* start the table access: */
723 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS,
724 GSWIP_PCE_TBL_CTRL);
725 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
726 GSWIP_PCE_TBL_CTRL_BAS);
727 if (err)
728 return err;
729 }
730
731 /* tell the switch that the microcode is loaded */
732 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID,
733 GSWIP_PCE_GCTRL_0);
734
735 return 0;
736}
737
8206e0ce 738static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
2e554a7a
VO		 739 bool vlan_filtering,
740 struct switchdev_trans *trans)
8206e0ce
HM		 741{
742 struct gswip_priv *priv = ds->priv;
9bbb1c05
HM		 743
744 /* Do not allow changing the VLAN filtering options while in bridge */
2e554a7a
VO		 745 if (switchdev_trans_ph_prepare(trans)) {
746 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
747
748 if (!bridge)
749 return 0;
750
751 if (!!(priv->port_vlan_filter & BIT(port)) != vlan_filtering)
752 return -EIO;
753
754 return 0;
755 }
8206e0ce
HM		 756
757 if (vlan_filtering) {
758 /* Use port based VLAN tag */
759 gswip_switch_mask(priv,
760 GSWIP_PCE_VCTRL_VSR,
761 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
762 GSWIP_PCE_VCTRL_VEMR,
763 GSWIP_PCE_VCTRL(port));
764 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
765 GSWIP_PCE_PCTRL_0p(port));
766 } else {
767 /* Use port based VLAN tag */
768 gswip_switch_mask(priv,
769 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
770 GSWIP_PCE_VCTRL_VEMR,
771 GSWIP_PCE_VCTRL_VSR,
772 GSWIP_PCE_VCTRL(port));
773 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM,
774 GSWIP_PCE_PCTRL_0p(port));
775 }
776
777 return 0;
778}
779
14fceff4
HM		 780static int gswip_setup(struct dsa_switch *ds)
781{
782 struct gswip_priv *priv = ds->priv;
783 unsigned int cpu_port = priv->hw_info->cpu_port;
784 int i;
785 int err;
786
787 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
788 usleep_range(5000, 10000);
789 gswip_switch_w(priv, 0, GSWIP_SWRES);
790
791 /* disable port fetch/store dma on all ports */
8206e0ce 792 for (i = 0; i < priv->hw_info->max_ports; i++) {
2e554a7a
VO		 793 struct switchdev_trans trans;
794
795 /* Skip the prepare phase, this shouldn't return an error
796 * during setup.
797 */
798 trans.ph_prepare = false;
799
75104db0 800 gswip_port_disable(ds, i);
2e554a7a 801 gswip_port_vlan_filtering(ds, i, false, &trans);
8206e0ce 802 }
14fceff4
HM		 803
804 /* enable Switch */
805 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB);
806
807 err = gswip_pce_load_microcode(priv);
808 if (err) {
809 dev_err(priv->dev, "writing PCE microcode failed, %i", err);
810 return err;
811 }
812
813 /* Default unknown Broadcast/Multicast/Unicast port maps */
814 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
815 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
816 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
817
818 /* disable PHY auto polling */
819 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0);
820 /* Configure the MDIO Clock 2.5 MHz */
821 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
822
823 /* Disable the xMII link */
824 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0);
825 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1);
826 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5);
827
828 /* enable special tag insertion on cpu port */
829 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
830 GSWIP_FDMA_PCTRLp(cpu_port));
831
30d89383
HM		 832 /* accept special tag in ingress direction */
833 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
834 GSWIP_PCE_PCTRL_0p(cpu_port));
835
14fceff4
HM		 836 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,
837 GSWIP_MAC_CTRL_2p(cpu_port));
838 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN);
839 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
840 GSWIP_BM_QUEUE_GCTRL);
841
842 /* VLAN aware Switching */
843 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0);
844
8206e0ce
HM		 845 /* Flush MAC Table */
846 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0);
847
848 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0,
849 GSWIP_PCE_GCTRL_0_MTFL);
850 if (err) {
851 dev_err(priv->dev, "MAC flushing didn't finish\n");
852 return err;
853 }
14fceff4
HM		 854
855 gswip_port_enable(ds, cpu_port, NULL);
856 return 0;
857}
858
859static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds,
4d776482
FF		 860 int port,
861 enum dsa_tag_protocol mp)
14fceff4
HM		 862{
863 return DSA_TAG_PROTO_GSWIP;
864}
865
8206e0ce
HM		 866static int gswip_vlan_active_create(struct gswip_priv *priv,
867 struct net_device *bridge,
868 int fid, u16 vid)
869{
870 struct gswip_pce_table_entry vlan_active = {0,};
871 unsigned int max_ports = priv->hw_info->max_ports;
872 int idx = -1;
873 int err;
874 int i;
875
876 /* Look for a free slot */
877 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
878 if (!priv->vlans[i].bridge) {
879 idx = i;
880 break;
881 }
882 }
883
884 if (idx == -1)
885 return -ENOSPC;
886
887 if (fid == -1)
888 fid = idx;
889
890 vlan_active.index = idx;
891 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
892 vlan_active.key[0] = vid;
893 vlan_active.val[0] = fid;
894 vlan_active.valid = true;
895
896 err = gswip_pce_table_entry_write(priv, &vlan_active);
897 if (err) {
898 dev_err(priv->dev, "failed to write active VLAN: %d\n", err);
899 return err;
900 }
901
902 priv->vlans[idx].bridge = bridge;
903 priv->vlans[idx].vid = vid;
904 priv->vlans[idx].fid = fid;
905
906 return idx;
907}
908
909static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx)
910{
911 struct gswip_pce_table_entry vlan_active = {0,};
912 int err;
913
914 vlan_active.index = idx;
915 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
916 vlan_active.valid = false;
917 err = gswip_pce_table_entry_write(priv, &vlan_active);
918 if (err)
919 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err);
920 priv->vlans[idx].bridge = NULL;
921
922 return err;
923}
924
925static int gswip_vlan_add_unaware(struct gswip_priv *priv,
926 struct net_device *bridge, int port)
927{
928 struct gswip_pce_table_entry vlan_mapping = {0,};
929 unsigned int max_ports = priv->hw_info->max_ports;
930 unsigned int cpu_port = priv->hw_info->cpu_port;
931 bool active_vlan_created = false;
932 int idx = -1;
933 int i;
934 int err;
935
936 /* Check if there is already a page for this bridge */
937 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
938 if (priv->vlans[i].bridge == bridge) {
939 idx = i;
940 break;
941 }
942 }
943
944 /* If this bridge is not programmed yet, add a Active VLAN table
945 * entry in a free slot and prepare the VLAN mapping table entry.
946 */
947 if (idx == -1) {
948 idx = gswip_vlan_active_create(priv, bridge, -1, 0);
949 if (idx < 0)
950 return idx;
951 active_vlan_created = true;
952
953 vlan_mapping.index = idx;
954 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
955 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
956 vlan_mapping.val[0] = 0;
957 } else {
958 /* Read the existing VLAN mapping entry from the switch */
959 vlan_mapping.index = idx;
960 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
961 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
962 if (err) {
963 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
964 err);
965 return err;
966 }
967 }
968
969 /* Update the VLAN mapping entry and write it to the switch */
970 vlan_mapping.val[1] |= BIT(cpu_port);
971 vlan_mapping.val[1] |= BIT(port);
972 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
973 if (err) {
974 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
975 /* In case an Active VLAN was creaetd delete it again */
976 if (active_vlan_created)
977 gswip_vlan_active_remove(priv, idx);
978 return err;
979 }
980
981 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
982 return 0;
983}
984
9bbb1c05
HM		 985static int gswip_vlan_add_aware(struct gswip_priv *priv,
986 struct net_device *bridge, int port,
987 u16 vid, bool untagged,
988 bool pvid)
989{
990 struct gswip_pce_table_entry vlan_mapping = {0,};
991 unsigned int max_ports = priv->hw_info->max_ports;
992 unsigned int cpu_port = priv->hw_info->cpu_port;
993 bool active_vlan_created = false;
994 int idx = -1;
995 int fid = -1;
996 int i;
997 int err;
998
999 /* Check if there is already a page for this bridge */
1000 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1001 if (priv->vlans[i].bridge == bridge) {
1002 if (fid != -1 && fid != priv->vlans[i].fid)
1003 dev_err(priv->dev, "one bridge with multiple flow ids\n");
1004 fid = priv->vlans[i].fid;
1005 if (priv->vlans[i].vid == vid) {
1006 idx = i;
1007 break;
1008 }
1009 }
1010 }
1011
1012 /* If this bridge is not programmed yet, add a Active VLAN table
1013 * entry in a free slot and prepare the VLAN mapping table entry.
1014 */
1015 if (idx == -1) {
1016 idx = gswip_vlan_active_create(priv, bridge, fid, vid);
1017 if (idx < 0)
1018 return idx;
1019 active_vlan_created = true;
1020
1021 vlan_mapping.index = idx;
1022 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1023 /* VLAN ID byte, maps to the VLAN ID of vlan active table */
1024 vlan_mapping.val[0] = vid;
1025 } else {
1026 /* Read the existing VLAN mapping entry from the switch */
1027 vlan_mapping.index = idx;
1028 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1029 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1030 if (err) {
1031 dev_err(priv->dev, "failed to read VLAN mapping: %d\n",
1032 err);
1033 return err;
1034 }
1035 }
1036
1037 vlan_mapping.val[0] = vid;
1038 /* Update the VLAN mapping entry and write it to the switch */
1039 vlan_mapping.val[1] |= BIT(cpu_port);
1040 vlan_mapping.val[2] |= BIT(cpu_port);
1041 vlan_mapping.val[1] |= BIT(port);
1042 if (untagged)
1043 vlan_mapping.val[2] &= ~BIT(port);
1044 else
1045 vlan_mapping.val[2] |= BIT(port);
1046 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1047 if (err) {
1048 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1049 /* In case an Active VLAN was creaetd delete it again */
1050 if (active_vlan_created)
1051 gswip_vlan_active_remove(priv, idx);
1052 return err;
1053 }
1054
1055 if (pvid)
1056 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port));
1057
1058 return 0;
1059}
1060
8206e0ce
HM		 1061static int gswip_vlan_remove(struct gswip_priv *priv,
1062 struct net_device *bridge, int port,
1063 u16 vid, bool pvid, bool vlan_aware)
1064{
1065 struct gswip_pce_table_entry vlan_mapping = {0,};
1066 unsigned int max_ports = priv->hw_info->max_ports;
1067 unsigned int cpu_port = priv->hw_info->cpu_port;
1068 int idx = -1;
1069 int i;
1070 int err;
1071
1072 /* Check if there is already a page for this bridge */
1073 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1074 if (priv->vlans[i].bridge == bridge &&
1075 (!vlan_aware || priv->vlans[i].vid == vid)) {
1076 idx = i;
1077 break;
1078 }
1079 }
1080
1081 if (idx == -1) {
1082 dev_err(priv->dev, "bridge to leave does not exists\n");
1083 return -ENOENT;
1084 }
1085
1086 vlan_mapping.index = idx;
1087 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
1088 err = gswip_pce_table_entry_read(priv, &vlan_mapping);
1089 if (err) {
1090 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err);
1091 return err;
1092 }
1093
1094 vlan_mapping.val[1] &= ~BIT(port);
1095 vlan_mapping.val[2] &= ~BIT(port);
1096 err = gswip_pce_table_entry_write(priv, &vlan_mapping);
1097 if (err) {
1098 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err);
1099 return err;
1100 }
1101
1102 /* In case all ports are removed from the bridge, remove the VLAN */
1103 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1104 err = gswip_vlan_active_remove(priv, idx);
1105 if (err) {
1106 dev_err(priv->dev, "failed to write active VLAN: %d\n",
1107 err);
1108 return err;
1109 }
1110 }
1111
1112 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */
1113 if (pvid)
1114 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port));
1115
1116 return 0;
1117}
1118
1119static int gswip_port_bridge_join(struct dsa_switch *ds, int port,
1120 struct net_device *bridge)
1121{
1122 struct gswip_priv *priv = ds->priv;
1123 int err;
1124
9bbb1c05
HM		 1125 /* When the bridge uses VLAN filtering we have to configure VLAN
1126 * specific bridges. No bridge is configured here.
1127 */
1128 if (!br_vlan_enabled(bridge)) {
1129 err = gswip_vlan_add_unaware(priv, bridge, port);
1130 if (err)
1131 return err;
1132 priv->port_vlan_filter &= ~BIT(port);
1133 } else {
1134 priv->port_vlan_filter |= BIT(port);
1135 }
8206e0ce
HM		 1136 return gswip_add_single_port_br(priv, port, false);
1137}
1138
1139static void gswip_port_bridge_leave(struct dsa_switch *ds, int port,
1140 struct net_device *bridge)
1141{
1142 struct gswip_priv *priv = ds->priv;
1143
1144 gswip_add_single_port_br(priv, port, true);
1145
9bbb1c05
HM		 1146 /* When the bridge uses VLAN filtering we have to configure VLAN
1147 * specific bridges. No bridge is configured here.
1148 */
1149 if (!br_vlan_enabled(bridge))
1150 gswip_vlan_remove(priv, bridge, port, 0, true, false);
1151}
1152
1153static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port,
1154 const struct switchdev_obj_port_vlan *vlan)
1155{
1156 struct gswip_priv *priv = ds->priv;
1157 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1158 unsigned int max_ports = priv->hw_info->max_ports;
1159 u16 vid;
1160 int i;
1161 int pos = max_ports;
1162
1163 /* We only support VLAN filtering on bridges */
1164 if (!dsa_is_cpu_port(ds, port) && !bridge)
1165 return -EOPNOTSUPP;
1166
1167 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1168 int idx = -1;
1169
1170 /* Check if there is already a page for this VLAN */
1171 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) {
1172 if (priv->vlans[i].bridge == bridge &&
1173 priv->vlans[i].vid == vid) {
1174 idx = i;
1175 break;
1176 }
1177 }
1178
1179 /* If this VLAN is not programmed yet, we have to reserve
1180 * one entry in the VLAN table. Make sure we start at the
1181 * next position round.
1182 */
1183 if (idx == -1) {
1184 /* Look for a free slot */
1185 for (; pos < ARRAY_SIZE(priv->vlans); pos++) {
1186 if (!priv->vlans[pos].bridge) {
1187 idx = pos;
1188 pos++;
1189 break;
1190 }
1191 }
1192
1193 if (idx == -1)
1194 return -ENOSPC;
1195 }
1196 }
1197
1198 return 0;
1199}
1200
1201static void gswip_port_vlan_add(struct dsa_switch *ds, int port,
1202 const struct switchdev_obj_port_vlan *vlan)
1203{
1204 struct gswip_priv *priv = ds->priv;
1205 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1206 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1207 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1208 u16 vid;
1209
1210 /* We have to receive all packets on the CPU port and should not
1211 * do any VLAN filtering here. This is also called with bridge
1212 * NULL and then we do not know for which bridge to configure
1213 * this.
1214 */
1215 if (dsa_is_cpu_port(ds, port))
1216 return;
1217
1218 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1219 gswip_vlan_add_aware(priv, bridge, port, vid, untagged, pvid);
1220}
1221
1222static int gswip_port_vlan_del(struct dsa_switch *ds, int port,
1223 const struct switchdev_obj_port_vlan *vlan)
1224{
1225 struct gswip_priv *priv = ds->priv;
1226 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1227 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1228 u16 vid;
1229 int err;
1230
1231 /* We have to receive all packets on the CPU port and should not
1232 * do any VLAN filtering here. This is also called with bridge
1233 * NULL and then we do not know for which bridge to configure
1234 * this.
1235 */
1236 if (dsa_is_cpu_port(ds, port))
1237 return 0;
1238
1239 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1240 err = gswip_vlan_remove(priv, bridge, port, vid, pvid, true);
1241 if (err)
1242 return err;
1243 }
1244
1245 return 0;
8206e0ce
HM		 1246}
1247
45813481
HM		 1248static void gswip_port_fast_age(struct dsa_switch *ds, int port)
1249{
1250 struct gswip_priv *priv = ds->priv;
1251 struct gswip_pce_table_entry mac_bridge = {0,};
1252 int i;
1253 int err;
1254
1255 for (i = 0; i < 2048; i++) {
1256 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1257 mac_bridge.index = i;
1258
1259 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1260 if (err) {
d6759172 1261 dev_err(priv->dev, "failed to read mac bridge: %d\n",
45813481
HM		 1262 err);
1263 return;
1264 }
1265
1266 if (!mac_bridge.valid)
1267 continue;
1268
1269 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
1270 continue;
1271
1272 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
1273 continue;
1274
1275 mac_bridge.valid = false;
1276 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1277 if (err) {
d6759172 1278 dev_err(priv->dev, "failed to write mac bridge: %d\n",
45813481
HM		 1279 err);
1280 return;
1281 }
1282 }
1283}
1284
8206e0ce
HM		 1285static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1286{
1287 struct gswip_priv *priv = ds->priv;
1288 u32 stp_state;
1289
1290 switch (state) {
1291 case BR_STATE_DISABLED:
1292 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
1293 GSWIP_SDMA_PCTRLp(port));
1294 return;
1295 case BR_STATE_BLOCKING:
1296 case BR_STATE_LISTENING:
1297 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN;
1298 break;
1299 case BR_STATE_LEARNING:
1300 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING;
1301 break;
1302 case BR_STATE_FORWARDING:
1303 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING;
1304 break;
1305 default:
1306 dev_err(priv->dev, "invalid STP state: %d\n", state);
1307 return;
1308 }
1309
1310 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
1311 GSWIP_SDMA_PCTRLp(port));
1312 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
1313 GSWIP_PCE_PCTRL_0p(port));
1314}
1315
58c59ef9
HM		 1316static int gswip_port_fdb(struct dsa_switch *ds, int port,
1317 const unsigned char *addr, u16 vid, bool add)
1318{
1319 struct gswip_priv *priv = ds->priv;
1320 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev;
1321 struct gswip_pce_table_entry mac_bridge = {0,};
1322 unsigned int cpu_port = priv->hw_info->cpu_port;
1323 int fid = -1;
1324 int i;
1325 int err;
1326
1327 if (!bridge)
1328 return -EINVAL;
1329
1330 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) {
1331 if (priv->vlans[i].bridge == bridge) {
1332 fid = priv->vlans[i].fid;
1333 break;
1334 }
1335 }
1336
1337 if (fid == -1) {
1338 dev_err(priv->dev, "Port not part of a bridge\n");
1339 return -EINVAL;
1340 }
1341
1342 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1343 mac_bridge.key_mode = true;
1344 mac_bridge.key[0] = addr[5] | (addr[4] << 8);
1345 mac_bridge.key[1] = addr[3] | (addr[2] << 8);
1346 mac_bridge.key[2] = addr[1] | (addr[0] << 8);
1347 mac_bridge.key[3] = fid;
1348 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
1349 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
1350 mac_bridge.valid = add;
1351
1352 err = gswip_pce_table_entry_write(priv, &mac_bridge);
1353 if (err)
d6759172 1354 dev_err(priv->dev, "failed to write mac bridge: %d\n", err);
58c59ef9
HM		 1355
1356 return err;
1357}
1358
1359static int gswip_port_fdb_add(struct dsa_switch *ds, int port,
1360 const unsigned char *addr, u16 vid)
1361{
1362 return gswip_port_fdb(ds, port, addr, vid, true);
1363}
1364
1365static int gswip_port_fdb_del(struct dsa_switch *ds, int port,
1366 const unsigned char *addr, u16 vid)
1367{
1368 return gswip_port_fdb(ds, port, addr, vid, false);
1369}
1370
1371static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
1372 dsa_fdb_dump_cb_t *cb, void *data)
1373{
1374 struct gswip_priv *priv = ds->priv;
1375 struct gswip_pce_table_entry mac_bridge = {0,};
1376 unsigned char addr[6];
1377 int i;
1378 int err;
1379
1380 for (i = 0; i < 2048; i++) {
1381 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE;
1382 mac_bridge.index = i;
1383
1384 err = gswip_pce_table_entry_read(priv, &mac_bridge);
1385 if (err) {
d6759172 1386 dev_err(priv->dev, "failed to write mac bridge: %d\n",
58c59ef9
HM		 1387 err);
1388 return err;
1389 }
1390
1391 if (!mac_bridge.valid)
1392 continue;
1393
1394 addr[5] = mac_bridge.key[0] & 0xff;
1395 addr[4] = (mac_bridge.key[0] >> 8) & 0xff;
1396 addr[3] = mac_bridge.key[1] & 0xff;
1397 addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
1398 addr[1] = mac_bridge.key[2] & 0xff;
1399 addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
1400 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
1401 if (mac_bridge.val[0] & BIT(port))
1402 cb(addr, 0, true, data);
1403 } else {
1404 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port)
1405 cb(addr, 0, false, data);
1406 }
1407 }
1408 return 0;
1409}
1410
14fceff4
HM		 1411static void gswip_phylink_validate(struct dsa_switch *ds, int port,
1412 unsigned long *supported,
1413 struct phylink_link_state *state)
1414{
1415 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1416
1417 switch (port) {
1418 case 0:
1419 case 1:
1420 if (!phy_interface_mode_is_rgmii(state->interface) &&
1421 state->interface != PHY_INTERFACE_MODE_MII &&
1422 state->interface != PHY_INTERFACE_MODE_REVMII &&
0e630b59
HM		 1423 state->interface != PHY_INTERFACE_MODE_RMII)
1424 goto unsupported;
14fceff4
HM		 1425 break;
1426 case 2:
1427 case 3:
1428 case 4:
0e630b59
HM		 1429 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1430 goto unsupported;
14fceff4
HM		 1431 break;
1432 case 5:
1433 if (!phy_interface_mode_is_rgmii(state->interface) &&
0e630b59
HM		 1434 state->interface != PHY_INTERFACE_MODE_INTERNAL)
1435 goto unsupported;
14fceff4 1436 break;
0e630b59
HM		 1437 default:
1438 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1439 dev_err(ds->dev, "Unsupported port: %i\n", port);
1440 return;
14fceff4
HM		 1441 }
1442
1443 /* Allow all the expected bits */
1444 phylink_set(mask, Autoneg);
1445 phylink_set_port_modes(mask);
1446 phylink_set(mask, Pause);
1447 phylink_set(mask, Asym_Pause);
1448
1449 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1450 * including Half duplex
1451 */
1452 if (state->interface != PHY_INTERFACE_MODE_MII &&
1453 state->interface != PHY_INTERFACE_MODE_REVMII) {
1454 phylink_set(mask, 1000baseT_Full);
1455 phylink_set(mask, 1000baseT_Half);
1456 }
1457
1458 phylink_set(mask, 10baseT_Half);
1459 phylink_set(mask, 10baseT_Full);
1460 phylink_set(mask, 100baseT_Half);
1461 phylink_set(mask, 100baseT_Full);
1462
1463 bitmap_and(supported, supported, mask,
1464 __ETHTOOL_LINK_MODE_MASK_NBITS);
1465 bitmap_and(state->advertising, state->advertising, mask,
1466 __ETHTOOL_LINK_MODE_MASK_NBITS);
0e630b59
HM		 1467 return;
1468
1469unsupported:
1470 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
4d3da2d8
MB		 1471 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n",
1472 phy_modes(state->interface), port);
0e630b59 1473 return;
14fceff4
HM		 1474}
1475
1476static void gswip_phylink_mac_config(struct dsa_switch *ds, int port,
1477 unsigned int mode,
1478 const struct phylink_link_state *state)
1479{
1480 struct gswip_priv *priv = ds->priv;
1481 u32 miicfg = 0;
1482
1483 miicfg |= GSWIP_MII_CFG_LDCLKDIS;
1484
1485 switch (state->interface) {
1486 case PHY_INTERFACE_MODE_MII:
1487 case PHY_INTERFACE_MODE_INTERNAL:
1488 miicfg |= GSWIP_MII_CFG_MODE_MIIM;
1489 break;
1490 case PHY_INTERFACE_MODE_REVMII:
1491 miicfg |= GSWIP_MII_CFG_MODE_MIIP;
1492 break;
1493 case PHY_INTERFACE_MODE_RMII:
1494 miicfg |= GSWIP_MII_CFG_MODE_RMIIM;
1495 break;
1496 case PHY_INTERFACE_MODE_RGMII:
1497 case PHY_INTERFACE_MODE_RGMII_ID:
1498 case PHY_INTERFACE_MODE_RGMII_RXID:
1499 case PHY_INTERFACE_MODE_RGMII_TXID:
1500 miicfg |= GSWIP_MII_CFG_MODE_RGMII;
1501 break;
1502 default:
1503 dev_err(ds->dev,
1504 "Unsupported interface: %d\n", state->interface);
1505 return;
1506 }
1507 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port);
1508
1509 switch (state->interface) {
1510 case PHY_INTERFACE_MODE_RGMII_ID:
1511 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK |
1512 GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1513 break;
1514 case PHY_INTERFACE_MODE_RGMII_RXID:
1515 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port);
1516 break;
1517 case PHY_INTERFACE_MODE_RGMII_TXID:
1518 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port);
1519 break;
1520 default:
1521 break;
1522 }
1523}
1524
1525static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port,
1526 unsigned int mode,
1527 phy_interface_t interface)
1528{
1529 struct gswip_priv *priv = ds->priv;
1530
1531 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port);
1532}
1533
1534static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
1535 unsigned int mode,
1536 phy_interface_t interface,
5b502a7b
RK		 1537 struct phy_device *phydev,
1538 int speed, int duplex,
1539 bool tx_pause, bool rx_pause)
14fceff4
HM		 1540{
1541 struct gswip_priv *priv = ds->priv;
1542
1543 /* Enable the xMII interface only for the external PHY */
1544 if (interface != PHY_INTERFACE_MODE_INTERNAL)
1545 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1546}
1547
1548static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1549 uint8_t *data)
1550{
1551 int i;
1552
1553 if (stringset != ETH_SS_STATS)
1554 return;
1555
1556 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++)
1557 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name,
1558 ETH_GSTRING_LEN);
1559}
1560
1561static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
1562 u32 index)
1563{
1564 u32 result;
1565 int err;
1566
1567 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR);
1568 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
1569 GSWIP_BM_RAM_CTRL_OPMOD,
1570 table | GSWIP_BM_RAM_CTRL_BAS,
1571 GSWIP_BM_RAM_CTRL);
1572
1573 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
1574 GSWIP_BM_RAM_CTRL_BAS);
1575 if (err) {
1576 dev_err(priv->dev, "timeout while reading table: %u, index: %u",
1577 table, index);
1578 return 0;
1579 }
1580
1581 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0));
1582 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16;
1583
1584 return result;
1585}
1586
1587static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port,
1588 uint64_t *data)
1589{
1590 struct gswip_priv *priv = ds->priv;
1591 const struct gswip_rmon_cnt_desc *rmon_cnt;
1592 int i;
1593 u64 high;
1594
1595 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) {
1596 rmon_cnt = &gswip_rmon_cnt[i];
1597
1598 data[i] = gswip_bcm_ram_entry_read(priv, port,
1599 rmon_cnt->offset);
1600 if (rmon_cnt->size == 2) {
1601 high = gswip_bcm_ram_entry_read(priv, port,
1602 rmon_cnt->offset + 1);
1603 data[i] |= high << 32;
1604 }
1605 }
1606}
1607
1608static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset)
1609{
1610 if (sset != ETH_SS_STATS)
1611 return 0;
1612
1613 return ARRAY_SIZE(gswip_rmon_cnt);
1614}
1615
1616static const struct dsa_switch_ops gswip_switch_ops = {
1617 .get_tag_protocol = gswip_get_tag_protocol,
1618 .setup = gswip_setup,
1619 .port_enable = gswip_port_enable,
1620 .port_disable = gswip_port_disable,
8206e0ce
HM		 1621 .port_bridge_join = gswip_port_bridge_join,
1622 .port_bridge_leave = gswip_port_bridge_leave,
45813481 1623 .port_fast_age = gswip_port_fast_age,
9bbb1c05
HM		 1624 .port_vlan_filtering = gswip_port_vlan_filtering,
1625 .port_vlan_prepare = gswip_port_vlan_prepare,
1626 .port_vlan_add = gswip_port_vlan_add,
1627 .port_vlan_del = gswip_port_vlan_del,
8206e0ce 1628 .port_stp_state_set = gswip_port_stp_state_set,
58c59ef9
HM		 1629 .port_fdb_add = gswip_port_fdb_add,
1630 .port_fdb_del = gswip_port_fdb_del,
1631 .port_fdb_dump = gswip_port_fdb_dump,
14fceff4
HM		 1632 .phylink_validate = gswip_phylink_validate,
1633 .phylink_mac_config = gswip_phylink_mac_config,
1634 .phylink_mac_link_down = gswip_phylink_mac_link_down,
1635 .phylink_mac_link_up = gswip_phylink_mac_link_up,
1636 .get_strings = gswip_get_strings,
1637 .get_ethtool_stats = gswip_get_ethtool_stats,
1638 .get_sset_count = gswip_get_sset_count,
1639};
1640
1641static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
1642 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
1643 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
1644};
1645
1646static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
1647 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
1648 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
1649};
1650
1651static const struct xway_gphy_match_data xrx300_gphy_data = {
1652 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
1653 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
1654};
1655
1656static const struct of_device_id xway_gphy_match[] = {
1657 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1658 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1659 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1660 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1661 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1662 {},
1663};
1664
1665static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw)
1666{
1667 struct device *dev = priv->dev;
1668 const struct firmware *fw;
1669 void *fw_addr;
1670 dma_addr_t dma_addr;
1671 dma_addr_t dev_addr;
1672 size_t size;
1673 int ret;
1674
1675 ret = clk_prepare_enable(gphy_fw->clk_gate);
1676 if (ret)
1677 return ret;
1678
1679 reset_control_assert(gphy_fw->reset);
1680
1681 ret = request_firmware(&fw, gphy_fw->fw_name, dev);
1682 if (ret) {
1683 dev_err(dev, "failed to load firmware: %s, error: %i\n",
1684 gphy_fw->fw_name, ret);
1685 return ret;
1686 }
1687
1688 /* GPHY cores need the firmware code in a persistent and contiguous
1689 * memory area with a 16 kB boundary aligned start address.
1690 */
1691 size = fw->size + XRX200_GPHY_FW_ALIGN;
1692
1693 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
1694 if (fw_addr) {
1695 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
1696 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
1697 memcpy(fw_addr, fw->data, fw->size);
1698 } else {
1699 dev_err(dev, "failed to alloc firmware memory\n");
1700 release_firmware(fw);
1701 return -ENOMEM;
1702 }
1703
1704 release_firmware(fw);
1705
1706 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr);
1707 if (ret)
1708 return ret;
1709
1710 reset_control_deassert(gphy_fw->reset);
1711
1712 return ret;
1713}
1714
1715static int gswip_gphy_fw_probe(struct gswip_priv *priv,
1716 struct gswip_gphy_fw *gphy_fw,
1717 struct device_node *gphy_fw_np, int i)
1718{
1719 struct device *dev = priv->dev;
1720 u32 gphy_mode;
1721 int ret;
1722 char gphyname[10];
1723
1724 snprintf(gphyname, sizeof(gphyname), "gphy%d", i);
1725
1726 gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
1727 if (IS_ERR(gphy_fw->clk_gate)) {
1728 dev_err(dev, "Failed to lookup gate clock\n");
1729 return PTR_ERR(gphy_fw->clk_gate);
1730 }
1731
1732 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
1733 if (ret)
1734 return ret;
1735
1736 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode);
1737 /* Default to GE mode */
1738 if (ret)
1739 gphy_mode = GPHY_MODE_GE;
1740
1741 switch (gphy_mode) {
1742 case GPHY_MODE_FE:
1743 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name;
1744 break;
1745 case GPHY_MODE_GE:
1746 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
1747 break;
1748 default:
1749 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
1750 return -EINVAL;
1751 }
1752
1753 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
f592e0b9
WY		 1754 if (IS_ERR(gphy_fw->reset)) {
1755 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER)
14fceff4 1756 dev_err(dev, "Failed to lookup gphy reset\n");
f592e0b9 1757 return PTR_ERR(gphy_fw->reset);
14fceff4
HM		 1758 }
1759
1760 return gswip_gphy_fw_load(priv, gphy_fw);
1761}
1762
1763static void gswip_gphy_fw_remove(struct gswip_priv *priv,
1764 struct gswip_gphy_fw *gphy_fw)
1765{
1766 int ret;
1767
1768 /* check if the device was fully probed */
1769 if (!gphy_fw->fw_name)
1770 return;
1771
1772 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
1773 if (ret)
1774 dev_err(priv->dev, "can not reset GPHY FW pointer");
1775
1776 clk_disable_unprepare(gphy_fw->clk_gate);
1777
1778 reset_control_put(gphy_fw->reset);
1779}
1780
1781static int gswip_gphy_fw_list(struct gswip_priv *priv,
1782 struct device_node *gphy_fw_list_np, u32 version)
1783{
1784 struct device *dev = priv->dev;
1785 struct device_node *gphy_fw_np;
1786 const struct of_device_id *match;
1787 int err;
1788 int i = 0;
1789
0e630b59 1790 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older
14fceff4
HM		 1791 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also
1792 * needs a different GPHY firmware.
1793 */
1794 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) {
1795 switch (version) {
1796 case GSWIP_VERSION_2_0:
1797 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data;
1798 break;
1799 case GSWIP_VERSION_2_1:
1800 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
1801 break;
1802 default:
1803 dev_err(dev, "unknown GSWIP version: 0x%x", version);
1804 return -ENOENT;
1805 }
1806 }
1807
1808 match = of_match_node(xway_gphy_match, gphy_fw_list_np);
1809 if (match && match->data)
1810 priv->gphy_fw_name_cfg = match->data;
1811
1812 if (!priv->gphy_fw_name_cfg) {
1813 dev_err(dev, "GPHY compatible type not supported");
1814 return -ENOENT;
1815 }
1816
1817 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
1818 if (!priv->num_gphy_fw)
1819 return -ENOENT;
1820
1821 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np,
1822 "lantiq,rcu");
1823 if (IS_ERR(priv->rcu_regmap))
1824 return PTR_ERR(priv->rcu_regmap);
1825
1826 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw,
1827 sizeof(*priv->gphy_fw),
1828 GFP_KERNEL | __GFP_ZERO);
1829 if (!priv->gphy_fw)
1830 return -ENOMEM;
1831
1832 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) {
1833 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i],
1834 gphy_fw_np, i);
1835 if (err)
1836 goto remove_gphy;
1837 i++;
1838 }
1839
1840 return 0;
1841
1842remove_gphy:
1843 for (i = 0; i < priv->num_gphy_fw; i++)
1844 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1845 return err;
1846}
1847
1848static int gswip_probe(struct platform_device *pdev)
1849{
1850 struct gswip_priv *priv;
14fceff4
HM		 1851 struct device_node *mdio_np, *gphy_fw_np;
1852 struct device *dev = &pdev->dev;
1853 int err;
1854 int i;
1855 u32 version;
1856
1857 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1858 if (!priv)
1859 return -ENOMEM;
1860
6551c8c8 1861 priv->gswip = devm_platform_ioremap_resource(pdev, 0);
f5de8bfe
WY		 1862 if (IS_ERR(priv->gswip))
1863 return PTR_ERR(priv->gswip);
14fceff4 1864
6551c8c8 1865 priv->mdio = devm_platform_ioremap_resource(pdev, 1);
f5de8bfe
WY		 1866 if (IS_ERR(priv->mdio))
1867 return PTR_ERR(priv->mdio);
14fceff4 1868
6551c8c8 1869 priv->mii = devm_platform_ioremap_resource(pdev, 2);
f5de8bfe
WY		 1870 if (IS_ERR(priv->mii))
1871 return PTR_ERR(priv->mii);
14fceff4
HM		 1872
1873 priv->hw_info = of_device_get_match_data(dev);
1874 if (!priv->hw_info)
1875 return -EINVAL;
1876
7e99e347 1877 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
14fceff4
HM		 1878 if (!priv->ds)
1879 return -ENOMEM;
1880
7e99e347
VD		 1881 priv->ds->dev = dev;
1882 priv->ds->num_ports = priv->hw_info->max_ports;
14fceff4
HM		 1883 priv->ds->priv = priv;
1884 priv->ds->ops = &gswip_switch_ops;
1885 priv->dev = dev;
1886 version = gswip_switch_r(priv, GSWIP_VERSION);
1887
1888 /* bring up the mdio bus */
c8cbcb0d 1889 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw");
14fceff4
HM		 1890 if (gphy_fw_np) {
1891 err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
c8cbcb0d 1892 of_node_put(gphy_fw_np);
14fceff4
HM		 1893 if (err) {
1894 dev_err(dev, "gphy fw probe failed\n");
1895 return err;
1896 }
1897 }
1898
1899 /* bring up the mdio bus */
c8cbcb0d 1900 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio");
14fceff4
HM		 1901 if (mdio_np) {
1902 err = gswip_mdio(priv, mdio_np);
1903 if (err) {
1904 dev_err(dev, "mdio probe failed\n");
c8cbcb0d 1905 goto put_mdio_node;
14fceff4
HM		 1906 }
1907 }
1908
1909 err = dsa_register_switch(priv->ds);
1910 if (err) {
1911 dev_err(dev, "dsa switch register failed: %i\n", err);
1912 goto mdio_bus;
1913 }
0e630b59 1914 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
14fceff4
HM		 1915 dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
1916 priv->hw_info->cpu_port);
1917 err = -EINVAL;
aed13f2e 1918 goto disable_switch;
14fceff4
HM		 1919 }
1920
1921 platform_set_drvdata(pdev, priv);
1922
1923 dev_info(dev, "probed GSWIP version %lx mod %lx\n",
1924 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
1925 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
1926 return 0;
1927
aed13f2e
JH		 1928disable_switch:
1929 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
1930 dsa_unregister_switch(priv->ds);
14fceff4
HM		 1931mdio_bus:
1932 if (mdio_np)
1933 mdiobus_unregister(priv->ds->slave_mii_bus);
c8cbcb0d
JH		 1934put_mdio_node:
1935 of_node_put(mdio_np);
14fceff4
HM		 1936 for (i = 0; i < priv->num_gphy_fw; i++)
1937 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1938 return err;
1939}
1940
1941static int gswip_remove(struct platform_device *pdev)
1942{
1943 struct gswip_priv *priv = platform_get_drvdata(pdev);
1944 int i;
1945
14fceff4
HM		 1946 /* disable the switch */
1947 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);
1948
1949 dsa_unregister_switch(priv->ds);
1950
c8cbcb0d 1951 if (priv->ds->slave_mii_bus) {
14fceff4 1952 mdiobus_unregister(priv->ds->slave_mii_bus);
c8cbcb0d
JH		 1953 of_node_put(priv->ds->slave_mii_bus->dev.of_node);
1954 }
14fceff4
HM		 1955
1956 for (i = 0; i < priv->num_gphy_fw; i++)
1957 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]);
1958
1959 return 0;
1960}
1961
1962static const struct gswip_hw_info gswip_xrx200 = {
1963 .max_ports = 7,
1964 .cpu_port = 6,
1965};
1966
1967static const struct of_device_id gswip_of_match[] = {
1968 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
1969 {},
1970};
1971MODULE_DEVICE_TABLE(of, gswip_of_match);
1972
1973static struct platform_driver gswip_driver = {
1974 .probe = gswip_probe,
1975 .remove = gswip_remove,
1976 .driver = {
1977 .name = "gswip",
1978 .of_match_table = gswip_of_match,
1979 },
1980};
1981
1982module_platform_driver(gswip_driver);
1983
cffde201
HM		 1984MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
1985MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
1986MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
1987MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
1988MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
1989MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
14fceff4
HM		 1990MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
1991MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver");
1992MODULE_LICENSE("GPL v2");
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