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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b8f126a8 SW |
2 | /* |
3 | * Mediatek MT7530 DSA Switch driver | |
4 | * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> | |
b8f126a8 SW |
5 | */ |
6 | #include <linux/etherdevice.h> | |
7 | #include <linux/if_bridge.h> | |
8 | #include <linux/iopoll.h> | |
9 | #include <linux/mdio.h> | |
10 | #include <linux/mfd/syscon.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/netdevice.h> | |
b8f126a8 SW |
13 | #include <linux/of_mdio.h> |
14 | #include <linux/of_net.h> | |
15 | #include <linux/of_platform.h> | |
ca366d6c | 16 | #include <linux/phylink.h> |
b8f126a8 SW |
17 | #include <linux/regmap.h> |
18 | #include <linux/regulator/consumer.h> | |
19 | #include <linux/reset.h> | |
eb976a55 | 20 | #include <linux/gpio/consumer.h> |
b8f126a8 | 21 | #include <net/dsa.h> |
b8f126a8 SW |
22 | |
23 | #include "mt7530.h" | |
24 | ||
25 | /* String, offset, and register size in bytes if different from 4 bytes */ | |
26 | static const struct mt7530_mib_desc mt7530_mib[] = { | |
27 | MIB_DESC(1, 0x00, "TxDrop"), | |
28 | MIB_DESC(1, 0x04, "TxCrcErr"), | |
29 | MIB_DESC(1, 0x08, "TxUnicast"), | |
30 | MIB_DESC(1, 0x0c, "TxMulticast"), | |
31 | MIB_DESC(1, 0x10, "TxBroadcast"), | |
32 | MIB_DESC(1, 0x14, "TxCollision"), | |
33 | MIB_DESC(1, 0x18, "TxSingleCollision"), | |
34 | MIB_DESC(1, 0x1c, "TxMultipleCollision"), | |
35 | MIB_DESC(1, 0x20, "TxDeferred"), | |
36 | MIB_DESC(1, 0x24, "TxLateCollision"), | |
37 | MIB_DESC(1, 0x28, "TxExcessiveCollistion"), | |
38 | MIB_DESC(1, 0x2c, "TxPause"), | |
39 | MIB_DESC(1, 0x30, "TxPktSz64"), | |
40 | MIB_DESC(1, 0x34, "TxPktSz65To127"), | |
41 | MIB_DESC(1, 0x38, "TxPktSz128To255"), | |
42 | MIB_DESC(1, 0x3c, "TxPktSz256To511"), | |
43 | MIB_DESC(1, 0x40, "TxPktSz512To1023"), | |
44 | MIB_DESC(1, 0x44, "Tx1024ToMax"), | |
45 | MIB_DESC(2, 0x48, "TxBytes"), | |
46 | MIB_DESC(1, 0x60, "RxDrop"), | |
47 | MIB_DESC(1, 0x64, "RxFiltering"), | |
48 | MIB_DESC(1, 0x6c, "RxMulticast"), | |
49 | MIB_DESC(1, 0x70, "RxBroadcast"), | |
50 | MIB_DESC(1, 0x74, "RxAlignErr"), | |
51 | MIB_DESC(1, 0x78, "RxCrcErr"), | |
52 | MIB_DESC(1, 0x7c, "RxUnderSizeErr"), | |
53 | MIB_DESC(1, 0x80, "RxFragErr"), | |
54 | MIB_DESC(1, 0x84, "RxOverSzErr"), | |
55 | MIB_DESC(1, 0x88, "RxJabberErr"), | |
56 | MIB_DESC(1, 0x8c, "RxPause"), | |
57 | MIB_DESC(1, 0x90, "RxPktSz64"), | |
58 | MIB_DESC(1, 0x94, "RxPktSz65To127"), | |
59 | MIB_DESC(1, 0x98, "RxPktSz128To255"), | |
60 | MIB_DESC(1, 0x9c, "RxPktSz256To511"), | |
61 | MIB_DESC(1, 0xa0, "RxPktSz512To1023"), | |
62 | MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), | |
63 | MIB_DESC(2, 0xa8, "RxBytes"), | |
64 | MIB_DESC(1, 0xb0, "RxCtrlDrop"), | |
65 | MIB_DESC(1, 0xb4, "RxIngressDrop"), | |
66 | MIB_DESC(1, 0xb8, "RxArlDrop"), | |
67 | }; | |
68 | ||
69 | static int | |
70 | mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
71 | { | |
72 | int ret; | |
73 | ||
74 | ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); | |
75 | if (ret < 0) | |
76 | dev_err(priv->dev, | |
77 | "failed to priv write register\n"); | |
78 | return ret; | |
79 | } | |
80 | ||
81 | static u32 | |
82 | mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) | |
83 | { | |
84 | int ret; | |
85 | u32 val; | |
86 | ||
87 | ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); | |
88 | if (ret < 0) { | |
89 | dev_err(priv->dev, | |
90 | "failed to priv read register\n"); | |
91 | return ret; | |
92 | } | |
93 | ||
94 | return val; | |
95 | } | |
96 | ||
97 | static void | |
98 | mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, | |
99 | u32 mask, u32 set) | |
100 | { | |
101 | u32 val; | |
102 | ||
103 | val = mt7623_trgmii_read(priv, reg); | |
104 | val &= ~mask; | |
105 | val |= set; | |
106 | mt7623_trgmii_write(priv, reg, val); | |
107 | } | |
108 | ||
109 | static void | |
110 | mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) | |
111 | { | |
112 | mt7623_trgmii_rmw(priv, reg, 0, val); | |
113 | } | |
114 | ||
115 | static void | |
116 | mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) | |
117 | { | |
118 | mt7623_trgmii_rmw(priv, reg, val, 0); | |
119 | } | |
120 | ||
121 | static int | |
122 | core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) | |
123 | { | |
124 | struct mii_bus *bus = priv->bus; | |
125 | int value, ret; | |
126 | ||
127 | /* Write the desired MMD Devad */ | |
128 | ret = bus->write(bus, 0, MII_MMD_CTRL, devad); | |
129 | if (ret < 0) | |
130 | goto err; | |
131 | ||
132 | /* Write the desired MMD register address */ | |
133 | ret = bus->write(bus, 0, MII_MMD_DATA, prtad); | |
134 | if (ret < 0) | |
135 | goto err; | |
136 | ||
137 | /* Select the Function : DATA with no post increment */ | |
138 | ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); | |
139 | if (ret < 0) | |
140 | goto err; | |
141 | ||
142 | /* Read the content of the MMD's selected register */ | |
143 | value = bus->read(bus, 0, MII_MMD_DATA); | |
144 | ||
145 | return value; | |
146 | err: | |
147 | dev_err(&bus->dev, "failed to read mmd register\n"); | |
148 | ||
149 | return ret; | |
150 | } | |
151 | ||
152 | static int | |
153 | core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, | |
154 | int devad, u32 data) | |
155 | { | |
156 | struct mii_bus *bus = priv->bus; | |
157 | int ret; | |
158 | ||
159 | /* Write the desired MMD Devad */ | |
160 | ret = bus->write(bus, 0, MII_MMD_CTRL, devad); | |
161 | if (ret < 0) | |
162 | goto err; | |
163 | ||
164 | /* Write the desired MMD register address */ | |
165 | ret = bus->write(bus, 0, MII_MMD_DATA, prtad); | |
166 | if (ret < 0) | |
167 | goto err; | |
168 | ||
169 | /* Select the Function : DATA with no post increment */ | |
170 | ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); | |
171 | if (ret < 0) | |
172 | goto err; | |
173 | ||
174 | /* Write the data into MMD's selected register */ | |
175 | ret = bus->write(bus, 0, MII_MMD_DATA, data); | |
176 | err: | |
177 | if (ret < 0) | |
178 | dev_err(&bus->dev, | |
179 | "failed to write mmd register\n"); | |
180 | return ret; | |
181 | } | |
182 | ||
183 | static void | |
184 | core_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
185 | { | |
186 | struct mii_bus *bus = priv->bus; | |
187 | ||
188 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
189 | ||
190 | core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); | |
191 | ||
192 | mutex_unlock(&bus->mdio_lock); | |
193 | } | |
194 | ||
195 | static void | |
196 | core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) | |
197 | { | |
198 | struct mii_bus *bus = priv->bus; | |
199 | u32 val; | |
200 | ||
201 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
202 | ||
203 | val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); | |
204 | val &= ~mask; | |
205 | val |= set; | |
206 | core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); | |
207 | ||
208 | mutex_unlock(&bus->mdio_lock); | |
209 | } | |
210 | ||
211 | static void | |
212 | core_set(struct mt7530_priv *priv, u32 reg, u32 val) | |
213 | { | |
214 | core_rmw(priv, reg, 0, val); | |
215 | } | |
216 | ||
217 | static void | |
218 | core_clear(struct mt7530_priv *priv, u32 reg, u32 val) | |
219 | { | |
220 | core_rmw(priv, reg, val, 0); | |
221 | } | |
222 | ||
223 | static int | |
224 | mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
225 | { | |
226 | struct mii_bus *bus = priv->bus; | |
227 | u16 page, r, lo, hi; | |
228 | int ret; | |
229 | ||
230 | page = (reg >> 6) & 0x3ff; | |
231 | r = (reg >> 2) & 0xf; | |
232 | lo = val & 0xffff; | |
233 | hi = val >> 16; | |
234 | ||
235 | /* MT7530 uses 31 as the pseudo port */ | |
236 | ret = bus->write(bus, 0x1f, 0x1f, page); | |
237 | if (ret < 0) | |
238 | goto err; | |
239 | ||
240 | ret = bus->write(bus, 0x1f, r, lo); | |
241 | if (ret < 0) | |
242 | goto err; | |
243 | ||
244 | ret = bus->write(bus, 0x1f, 0x10, hi); | |
245 | err: | |
246 | if (ret < 0) | |
247 | dev_err(&bus->dev, | |
248 | "failed to write mt7530 register\n"); | |
249 | return ret; | |
250 | } | |
251 | ||
252 | static u32 | |
253 | mt7530_mii_read(struct mt7530_priv *priv, u32 reg) | |
254 | { | |
255 | struct mii_bus *bus = priv->bus; | |
256 | u16 page, r, lo, hi; | |
257 | int ret; | |
258 | ||
259 | page = (reg >> 6) & 0x3ff; | |
260 | r = (reg >> 2) & 0xf; | |
261 | ||
262 | /* MT7530 uses 31 as the pseudo port */ | |
263 | ret = bus->write(bus, 0x1f, 0x1f, page); | |
264 | if (ret < 0) { | |
265 | dev_err(&bus->dev, | |
266 | "failed to read mt7530 register\n"); | |
267 | return ret; | |
268 | } | |
269 | ||
270 | lo = bus->read(bus, 0x1f, r); | |
271 | hi = bus->read(bus, 0x1f, 0x10); | |
272 | ||
273 | return (hi << 16) | (lo & 0xffff); | |
274 | } | |
275 | ||
276 | static void | |
277 | mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
278 | { | |
279 | struct mii_bus *bus = priv->bus; | |
280 | ||
281 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
282 | ||
283 | mt7530_mii_write(priv, reg, val); | |
284 | ||
285 | mutex_unlock(&bus->mdio_lock); | |
286 | } | |
287 | ||
288 | static u32 | |
289 | _mt7530_read(struct mt7530_dummy_poll *p) | |
290 | { | |
291 | struct mii_bus *bus = p->priv->bus; | |
292 | u32 val; | |
293 | ||
294 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
295 | ||
296 | val = mt7530_mii_read(p->priv, p->reg); | |
297 | ||
298 | mutex_unlock(&bus->mdio_lock); | |
299 | ||
300 | return val; | |
301 | } | |
302 | ||
303 | static u32 | |
304 | mt7530_read(struct mt7530_priv *priv, u32 reg) | |
305 | { | |
306 | struct mt7530_dummy_poll p; | |
307 | ||
308 | INIT_MT7530_DUMMY_POLL(&p, priv, reg); | |
309 | return _mt7530_read(&p); | |
310 | } | |
311 | ||
312 | static void | |
313 | mt7530_rmw(struct mt7530_priv *priv, u32 reg, | |
314 | u32 mask, u32 set) | |
315 | { | |
316 | struct mii_bus *bus = priv->bus; | |
317 | u32 val; | |
318 | ||
319 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
320 | ||
321 | val = mt7530_mii_read(priv, reg); | |
322 | val &= ~mask; | |
323 | val |= set; | |
324 | mt7530_mii_write(priv, reg, val); | |
325 | ||
326 | mutex_unlock(&bus->mdio_lock); | |
327 | } | |
328 | ||
329 | static void | |
330 | mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) | |
331 | { | |
332 | mt7530_rmw(priv, reg, 0, val); | |
333 | } | |
334 | ||
335 | static void | |
336 | mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) | |
337 | { | |
338 | mt7530_rmw(priv, reg, val, 0); | |
339 | } | |
340 | ||
341 | static int | |
342 | mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) | |
343 | { | |
344 | u32 val; | |
345 | int ret; | |
346 | struct mt7530_dummy_poll p; | |
347 | ||
348 | /* Set the command operating upon the MAC address entries */ | |
349 | val = ATC_BUSY | ATC_MAT(0) | cmd; | |
350 | mt7530_write(priv, MT7530_ATC, val); | |
351 | ||
352 | INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); | |
353 | ret = readx_poll_timeout(_mt7530_read, &p, val, | |
354 | !(val & ATC_BUSY), 20, 20000); | |
355 | if (ret < 0) { | |
356 | dev_err(priv->dev, "reset timeout\n"); | |
357 | return ret; | |
358 | } | |
359 | ||
360 | /* Additional sanity for read command if the specified | |
361 | * entry is invalid | |
362 | */ | |
363 | val = mt7530_read(priv, MT7530_ATC); | |
364 | if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) | |
365 | return -EINVAL; | |
366 | ||
367 | if (rsp) | |
368 | *rsp = val; | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static void | |
374 | mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) | |
375 | { | |
376 | u32 reg[3]; | |
377 | int i; | |
378 | ||
379 | /* Read from ARL table into an array */ | |
380 | for (i = 0; i < 3; i++) { | |
381 | reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); | |
382 | ||
383 | dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", | |
384 | __func__, __LINE__, i, reg[i]); | |
385 | } | |
386 | ||
387 | fdb->vid = (reg[1] >> CVID) & CVID_MASK; | |
388 | fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; | |
389 | fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; | |
390 | fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; | |
391 | fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; | |
392 | fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; | |
393 | fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; | |
394 | fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; | |
395 | fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; | |
396 | fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; | |
397 | } | |
398 | ||
399 | static void | |
400 | mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, | |
401 | u8 port_mask, const u8 *mac, | |
402 | u8 aging, u8 type) | |
403 | { | |
404 | u32 reg[3] = { 0 }; | |
405 | int i; | |
406 | ||
407 | reg[1] |= vid & CVID_MASK; | |
408 | reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; | |
409 | reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; | |
410 | /* STATIC_ENT indicate that entry is static wouldn't | |
411 | * be aged out and STATIC_EMP specified as erasing an | |
412 | * entry | |
413 | */ | |
414 | reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; | |
415 | reg[1] |= mac[5] << MAC_BYTE_5; | |
416 | reg[1] |= mac[4] << MAC_BYTE_4; | |
417 | reg[0] |= mac[3] << MAC_BYTE_3; | |
418 | reg[0] |= mac[2] << MAC_BYTE_2; | |
419 | reg[0] |= mac[1] << MAC_BYTE_1; | |
420 | reg[0] |= mac[0] << MAC_BYTE_0; | |
421 | ||
422 | /* Write array into the ARL table */ | |
423 | for (i = 0; i < 3; i++) | |
424 | mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); | |
425 | } | |
426 | ||
427 | static int | |
428 | mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) | |
429 | { | |
430 | struct mt7530_priv *priv = ds->priv; | |
7ef6f6f8 RD |
431 | u32 ncpo1, ssc_delta, trgint, i, xtal; |
432 | ||
433 | xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; | |
434 | ||
435 | if (xtal == HWTRAP_XTAL_20MHZ) { | |
436 | dev_err(priv->dev, | |
437 | "%s: MT7530 with a 20MHz XTAL is not supported!\n", | |
438 | __func__); | |
439 | return -EINVAL; | |
440 | } | |
b8f126a8 SW |
441 | |
442 | switch (mode) { | |
443 | case PHY_INTERFACE_MODE_RGMII: | |
444 | trgint = 0; | |
7ef6f6f8 | 445 | /* PLL frequency: 125MHz */ |
b8f126a8 | 446 | ncpo1 = 0x0c80; |
b8f126a8 SW |
447 | break; |
448 | case PHY_INTERFACE_MODE_TRGMII: | |
449 | trgint = 1; | |
7ef6f6f8 RD |
450 | if (priv->id == ID_MT7621) { |
451 | /* PLL frequency: 150MHz: 1.2GBit */ | |
452 | if (xtal == HWTRAP_XTAL_40MHZ) | |
453 | ncpo1 = 0x0780; | |
454 | if (xtal == HWTRAP_XTAL_25MHZ) | |
455 | ncpo1 = 0x0a00; | |
456 | } else { /* PLL frequency: 250MHz: 2.0Gbit */ | |
457 | if (xtal == HWTRAP_XTAL_40MHZ) | |
458 | ncpo1 = 0x0c80; | |
459 | if (xtal == HWTRAP_XTAL_25MHZ) | |
460 | ncpo1 = 0x1400; | |
461 | } | |
b8f126a8 SW |
462 | break; |
463 | default: | |
464 | dev_err(priv->dev, "xMII mode %d not supported\n", mode); | |
465 | return -EINVAL; | |
466 | } | |
467 | ||
7ef6f6f8 RD |
468 | if (xtal == HWTRAP_XTAL_25MHZ) |
469 | ssc_delta = 0x57; | |
470 | else | |
471 | ssc_delta = 0x87; | |
472 | ||
b8f126a8 SW |
473 | mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, |
474 | P6_INTF_MODE(trgint)); | |
475 | ||
476 | /* Lower Tx Driving for TRGMII path */ | |
477 | for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) | |
478 | mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), | |
479 | TD_DM_DRVP(8) | TD_DM_DRVN(8)); | |
480 | ||
481 | /* Setup core clock for MT7530 */ | |
482 | if (!trgint) { | |
483 | /* Disable MT7530 core clock */ | |
484 | core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); | |
485 | ||
486 | /* Disable PLL, since phy_device has not yet been created | |
487 | * provided for phy_[read,write]_mmd_indirect is called, we | |
488 | * provide our own core_write_mmd_indirect to complete this | |
489 | * function. | |
490 | */ | |
491 | core_write_mmd_indirect(priv, | |
492 | CORE_GSWPLL_GRP1, | |
493 | MDIO_MMD_VEND2, | |
494 | 0); | |
495 | ||
496 | /* Set core clock into 500Mhz */ | |
497 | core_write(priv, CORE_GSWPLL_GRP2, | |
498 | RG_GSWPLL_POSDIV_500M(1) | | |
499 | RG_GSWPLL_FBKDIV_500M(25)); | |
500 | ||
501 | /* Enable PLL */ | |
502 | core_write(priv, CORE_GSWPLL_GRP1, | |
503 | RG_GSWPLL_EN_PRE | | |
504 | RG_GSWPLL_POSDIV_200M(2) | | |
505 | RG_GSWPLL_FBKDIV_200M(32)); | |
506 | ||
507 | /* Enable MT7530 core clock */ | |
508 | core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); | |
509 | } | |
510 | ||
511 | /* Setup the MT7530 TRGMII Tx Clock */ | |
512 | core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); | |
513 | core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); | |
514 | core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); | |
515 | core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); | |
516 | core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); | |
517 | core_write(priv, CORE_PLL_GROUP4, | |
518 | RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | | |
519 | RG_SYSPLL_BIAS_LPF_EN); | |
520 | core_write(priv, CORE_PLL_GROUP2, | |
521 | RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | | |
522 | RG_SYSPLL_POSDIV(1)); | |
523 | core_write(priv, CORE_PLL_GROUP7, | |
524 | RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | | |
525 | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); | |
526 | core_set(priv, CORE_TRGMII_GSW_CLK_CG, | |
527 | REG_GSWCK_EN | REG_TRGMIICK_EN); | |
528 | ||
529 | if (!trgint) | |
530 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) | |
531 | mt7530_rmw(priv, MT7530_TRGMII_RD(i), | |
532 | RD_TAP_MASK, RD_TAP(16)); | |
533 | else | |
7ef6f6f8 RD |
534 | if (priv->id != ID_MT7621) |
535 | mt7623_trgmii_set(priv, GSW_INTF_MODE, | |
536 | INTF_MODE_TRGMII); | |
b8f126a8 SW |
537 | |
538 | return 0; | |
539 | } | |
540 | ||
541 | static int | |
542 | mt7623_pad_clk_setup(struct dsa_switch *ds) | |
543 | { | |
544 | struct mt7530_priv *priv = ds->priv; | |
545 | int i; | |
546 | ||
547 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) | |
548 | mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), | |
549 | TD_DM_DRVP(8) | TD_DM_DRVN(8)); | |
550 | ||
551 | mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); | |
552 | mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static void | |
558 | mt7530_mib_reset(struct dsa_switch *ds) | |
559 | { | |
560 | struct mt7530_priv *priv = ds->priv; | |
561 | ||
562 | mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); | |
563 | mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); | |
564 | } | |
565 | ||
b8f126a8 SW |
566 | static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) |
567 | { | |
568 | struct mt7530_priv *priv = ds->priv; | |
569 | ||
570 | return mdiobus_read_nested(priv->bus, port, regnum); | |
571 | } | |
572 | ||
360cc342 CIK |
573 | static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, |
574 | u16 val) | |
b8f126a8 SW |
575 | { |
576 | struct mt7530_priv *priv = ds->priv; | |
577 | ||
578 | return mdiobus_write_nested(priv->bus, port, regnum, val); | |
579 | } | |
580 | ||
581 | static void | |
89f09048 FF |
582 | mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, |
583 | uint8_t *data) | |
b8f126a8 SW |
584 | { |
585 | int i; | |
586 | ||
89f09048 FF |
587 | if (stringset != ETH_SS_STATS) |
588 | return; | |
589 | ||
b8f126a8 SW |
590 | for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) |
591 | strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, | |
592 | ETH_GSTRING_LEN); | |
593 | } | |
594 | ||
595 | static void | |
596 | mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, | |
597 | uint64_t *data) | |
598 | { | |
599 | struct mt7530_priv *priv = ds->priv; | |
600 | const struct mt7530_mib_desc *mib; | |
601 | u32 reg, i; | |
602 | u64 hi; | |
603 | ||
604 | for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { | |
605 | mib = &mt7530_mib[i]; | |
606 | reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; | |
607 | ||
608 | data[i] = mt7530_read(priv, reg); | |
609 | if (mib->size == 2) { | |
610 | hi = mt7530_read(priv, reg + 4); | |
611 | data[i] |= hi << 32; | |
612 | } | |
613 | } | |
614 | } | |
615 | ||
616 | static int | |
89f09048 | 617 | mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) |
b8f126a8 | 618 | { |
89f09048 FF |
619 | if (sset != ETH_SS_STATS) |
620 | return 0; | |
621 | ||
b8f126a8 SW |
622 | return ARRAY_SIZE(mt7530_mib); |
623 | } | |
624 | ||
38f790a8 RD |
625 | static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) |
626 | { | |
627 | struct mt7530_priv *priv = ds->priv; | |
628 | u8 tx_delay = 0; | |
629 | int val; | |
630 | ||
631 | mutex_lock(&priv->reg_mutex); | |
632 | ||
633 | val = mt7530_read(priv, MT7530_MHWTRAP); | |
634 | ||
635 | val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; | |
636 | val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; | |
637 | ||
638 | switch (priv->p5_intf_sel) { | |
639 | case P5_INTF_SEL_PHY_P0: | |
640 | /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ | |
641 | val |= MHWTRAP_PHY0_SEL; | |
642 | /* fall through */ | |
643 | case P5_INTF_SEL_PHY_P4: | |
644 | /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ | |
645 | val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; | |
646 | ||
647 | /* Setup the MAC by default for the cpu port */ | |
648 | mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); | |
649 | break; | |
650 | case P5_INTF_SEL_GMAC5: | |
651 | /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ | |
652 | val &= ~MHWTRAP_P5_DIS; | |
653 | break; | |
654 | case P5_DISABLED: | |
655 | interface = PHY_INTERFACE_MODE_NA; | |
656 | break; | |
657 | default: | |
658 | dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", | |
659 | priv->p5_intf_sel); | |
660 | goto unlock_exit; | |
661 | } | |
662 | ||
663 | /* Setup RGMII settings */ | |
664 | if (phy_interface_mode_is_rgmii(interface)) { | |
665 | val |= MHWTRAP_P5_RGMII_MODE; | |
666 | ||
667 | /* P5 RGMII RX Clock Control: delay setting for 1000M */ | |
668 | mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); | |
669 | ||
670 | /* Don't set delay in DSA mode */ | |
671 | if (!dsa_is_dsa_port(priv->ds, 5) && | |
672 | (interface == PHY_INTERFACE_MODE_RGMII_TXID || | |
673 | interface == PHY_INTERFACE_MODE_RGMII_ID)) | |
674 | tx_delay = 4; /* n * 0.5 ns */ | |
675 | ||
676 | /* P5 RGMII TX Clock Control: delay x */ | |
677 | mt7530_write(priv, MT7530_P5RGMIITXCR, | |
678 | CSR_RGMII_TXC_CFG(0x10 + tx_delay)); | |
679 | ||
680 | /* reduce P5 RGMII Tx driving, 8mA */ | |
681 | mt7530_write(priv, MT7530_IO_DRV_CR, | |
682 | P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); | |
683 | } | |
684 | ||
685 | mt7530_write(priv, MT7530_MHWTRAP, val); | |
686 | ||
687 | dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", | |
688 | val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); | |
689 | ||
690 | priv->p5_interface = interface; | |
691 | ||
692 | unlock_exit: | |
693 | mutex_unlock(&priv->reg_mutex); | |
694 | } | |
695 | ||
b8f126a8 SW |
696 | static int |
697 | mt7530_cpu_port_enable(struct mt7530_priv *priv, | |
698 | int port) | |
699 | { | |
700 | /* Enable Mediatek header mode on the cpu port */ | |
701 | mt7530_write(priv, MT7530_PVC_P(port), | |
702 | PORT_SPEC_TAG); | |
703 | ||
b8f126a8 SW |
704 | /* Disable auto learning on the cpu port */ |
705 | mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); | |
706 | ||
707 | /* Unknown unicast frame fordwarding to the cpu port */ | |
708 | mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); | |
709 | ||
ddda1ac1 GU |
710 | /* Set CPU port number */ |
711 | if (priv->id == ID_MT7621) | |
712 | mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); | |
713 | ||
b8f126a8 SW |
714 | /* CPU port gets connected to all user ports of |
715 | * the switch | |
716 | */ | |
717 | mt7530_write(priv, MT7530_PCR_P(port), | |
02bc6e54 | 718 | PCR_MATRIX(dsa_user_ports(priv->ds))); |
b8f126a8 SW |
719 | |
720 | return 0; | |
721 | } | |
722 | ||
723 | static int | |
724 | mt7530_port_enable(struct dsa_switch *ds, int port, | |
725 | struct phy_device *phy) | |
726 | { | |
727 | struct mt7530_priv *priv = ds->priv; | |
728 | ||
74be4bab VD |
729 | if (!dsa_is_user_port(ds, port)) |
730 | return 0; | |
731 | ||
b8f126a8 SW |
732 | mutex_lock(&priv->reg_mutex); |
733 | ||
b8f126a8 SW |
734 | /* Allow the user port gets connected to the cpu port and also |
735 | * restore the port matrix if the port is the member of a certain | |
736 | * bridge. | |
737 | */ | |
738 | priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); | |
739 | priv->ports[port].enable = true; | |
740 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, | |
741 | priv->ports[port].pm); | |
1d01145f | 742 | mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); |
b8f126a8 SW |
743 | |
744 | mutex_unlock(&priv->reg_mutex); | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
749 | static void | |
75104db0 | 750 | mt7530_port_disable(struct dsa_switch *ds, int port) |
b8f126a8 SW |
751 | { |
752 | struct mt7530_priv *priv = ds->priv; | |
753 | ||
74be4bab VD |
754 | if (!dsa_is_user_port(ds, port)) |
755 | return; | |
756 | ||
b8f126a8 SW |
757 | mutex_lock(&priv->reg_mutex); |
758 | ||
759 | /* Clear up all port matrix which could be restored in the next | |
760 | * enablement for the port. | |
761 | */ | |
762 | priv->ports[port].enable = false; | |
763 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, | |
764 | PCR_MATRIX_CLR); | |
1d01145f | 765 | mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); |
b8f126a8 SW |
766 | |
767 | mutex_unlock(&priv->reg_mutex); | |
768 | } | |
769 | ||
770 | static void | |
771 | mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) | |
772 | { | |
773 | struct mt7530_priv *priv = ds->priv; | |
774 | u32 stp_state; | |
775 | ||
776 | switch (state) { | |
777 | case BR_STATE_DISABLED: | |
778 | stp_state = MT7530_STP_DISABLED; | |
779 | break; | |
780 | case BR_STATE_BLOCKING: | |
781 | stp_state = MT7530_STP_BLOCKING; | |
782 | break; | |
783 | case BR_STATE_LISTENING: | |
784 | stp_state = MT7530_STP_LISTENING; | |
785 | break; | |
786 | case BR_STATE_LEARNING: | |
787 | stp_state = MT7530_STP_LEARNING; | |
788 | break; | |
789 | case BR_STATE_FORWARDING: | |
790 | default: | |
791 | stp_state = MT7530_STP_FORWARDING; | |
792 | break; | |
793 | } | |
794 | ||
795 | mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); | |
796 | } | |
797 | ||
798 | static int | |
799 | mt7530_port_bridge_join(struct dsa_switch *ds, int port, | |
800 | struct net_device *bridge) | |
801 | { | |
802 | struct mt7530_priv *priv = ds->priv; | |
803 | u32 port_bitmap = BIT(MT7530_CPU_PORT); | |
804 | int i; | |
805 | ||
806 | mutex_lock(&priv->reg_mutex); | |
807 | ||
808 | for (i = 0; i < MT7530_NUM_PORTS; i++) { | |
809 | /* Add this port to the port matrix of the other ports in the | |
810 | * same bridge. If the port is disabled, port matrix is kept | |
811 | * and not being setup until the port becomes enabled. | |
812 | */ | |
4a5b85ff | 813 | if (dsa_is_user_port(ds, i) && i != port) { |
c8652c83 | 814 | if (dsa_to_port(ds, i)->bridge_dev != bridge) |
b8f126a8 SW |
815 | continue; |
816 | if (priv->ports[i].enable) | |
817 | mt7530_set(priv, MT7530_PCR_P(i), | |
818 | PCR_MATRIX(BIT(port))); | |
819 | priv->ports[i].pm |= PCR_MATRIX(BIT(port)); | |
820 | ||
821 | port_bitmap |= BIT(i); | |
822 | } | |
823 | } | |
824 | ||
825 | /* Add the all other ports to this port matrix. */ | |
826 | if (priv->ports[port].enable) | |
827 | mt7530_rmw(priv, MT7530_PCR_P(port), | |
828 | PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); | |
829 | priv->ports[port].pm |= PCR_MATRIX(port_bitmap); | |
830 | ||
831 | mutex_unlock(&priv->reg_mutex); | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
83163f7d SW |
836 | static void |
837 | mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) | |
838 | { | |
839 | struct mt7530_priv *priv = ds->priv; | |
840 | bool all_user_ports_removed = true; | |
841 | int i; | |
842 | ||
843 | /* When a port is removed from the bridge, the port would be set up | |
844 | * back to the default as is at initial boot which is a VLAN-unaware | |
845 | * port. | |
846 | */ | |
847 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, | |
848 | MT7530_PORT_MATRIX_MODE); | |
849 | mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, | |
850 | VLAN_ATTR(MT7530_VLAN_TRANSPARENT)); | |
851 | ||
83163f7d SW |
852 | for (i = 0; i < MT7530_NUM_PORTS; i++) { |
853 | if (dsa_is_user_port(ds, i) && | |
68bb8ea8 | 854 | dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { |
83163f7d SW |
855 | all_user_ports_removed = false; |
856 | break; | |
857 | } | |
858 | } | |
859 | ||
860 | /* CPU port also does the same thing until all user ports belonging to | |
861 | * the CPU port get out of VLAN filtering mode. | |
862 | */ | |
863 | if (all_user_ports_removed) { | |
864 | mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), | |
865 | PCR_MATRIX(dsa_user_ports(priv->ds))); | |
866 | mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), | |
867 | PORT_SPEC_TAG); | |
868 | } | |
869 | } | |
870 | ||
871 | static void | |
872 | mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) | |
873 | { | |
874 | struct mt7530_priv *priv = ds->priv; | |
875 | ||
876 | /* The real fabric path would be decided on the membership in the | |
877 | * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS | |
878 | * means potential VLAN can be consisting of certain subset of all | |
879 | * ports. | |
880 | */ | |
881 | mt7530_rmw(priv, MT7530_PCR_P(port), | |
882 | PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); | |
883 | ||
884 | /* Trapped into security mode allows packet forwarding through VLAN | |
885 | * table lookup. | |
886 | */ | |
887 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, | |
888 | MT7530_PORT_SECURITY_MODE); | |
889 | ||
890 | /* Set the port as a user port which is to be able to recognize VID | |
891 | * from incoming packets before fetching entry within the VLAN table. | |
892 | */ | |
893 | mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, | |
894 | VLAN_ATTR(MT7530_VLAN_USER)); | |
895 | } | |
896 | ||
b8f126a8 SW |
897 | static void |
898 | mt7530_port_bridge_leave(struct dsa_switch *ds, int port, | |
899 | struct net_device *bridge) | |
900 | { | |
901 | struct mt7530_priv *priv = ds->priv; | |
902 | int i; | |
903 | ||
904 | mutex_lock(&priv->reg_mutex); | |
905 | ||
906 | for (i = 0; i < MT7530_NUM_PORTS; i++) { | |
907 | /* Remove this port from the port matrix of the other ports | |
908 | * in the same bridge. If the port is disabled, port matrix | |
909 | * is kept and not being setup until the port becomes enabled. | |
83163f7d SW |
910 | * And the other port's port matrix cannot be broken when the |
911 | * other port is still a VLAN-aware port. | |
b8f126a8 | 912 | */ |
2a130551 | 913 | if (dsa_is_user_port(ds, i) && i != port && |
68bb8ea8 | 914 | !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { |
c8652c83 | 915 | if (dsa_to_port(ds, i)->bridge_dev != bridge) |
b8f126a8 SW |
916 | continue; |
917 | if (priv->ports[i].enable) | |
918 | mt7530_clear(priv, MT7530_PCR_P(i), | |
919 | PCR_MATRIX(BIT(port))); | |
920 | priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); | |
921 | } | |
922 | } | |
923 | ||
924 | /* Set the cpu port to be the only one in the port matrix of | |
925 | * this port. | |
926 | */ | |
927 | if (priv->ports[port].enable) | |
928 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, | |
929 | PCR_MATRIX(BIT(MT7530_CPU_PORT))); | |
930 | priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); | |
931 | ||
932 | mutex_unlock(&priv->reg_mutex); | |
933 | } | |
934 | ||
935 | static int | |
b8f126a8 | 936 | mt7530_port_fdb_add(struct dsa_switch *ds, int port, |
6c2c1dcb | 937 | const unsigned char *addr, u16 vid) |
b8f126a8 SW |
938 | { |
939 | struct mt7530_priv *priv = ds->priv; | |
1b6dd556 | 940 | int ret; |
b8f126a8 SW |
941 | u8 port_mask = BIT(port); |
942 | ||
943 | mutex_lock(&priv->reg_mutex); | |
6c2c1dcb | 944 | mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); |
18bd5949 | 945 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); |
b8f126a8 | 946 | mutex_unlock(&priv->reg_mutex); |
1b6dd556 AS |
947 | |
948 | return ret; | |
b8f126a8 SW |
949 | } |
950 | ||
951 | static int | |
952 | mt7530_port_fdb_del(struct dsa_switch *ds, int port, | |
6c2c1dcb | 953 | const unsigned char *addr, u16 vid) |
b8f126a8 SW |
954 | { |
955 | struct mt7530_priv *priv = ds->priv; | |
956 | int ret; | |
957 | u8 port_mask = BIT(port); | |
958 | ||
959 | mutex_lock(&priv->reg_mutex); | |
6c2c1dcb | 960 | mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); |
18bd5949 | 961 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); |
b8f126a8 SW |
962 | mutex_unlock(&priv->reg_mutex); |
963 | ||
964 | return ret; | |
965 | } | |
966 | ||
967 | static int | |
968 | mt7530_port_fdb_dump(struct dsa_switch *ds, int port, | |
2bedde1a | 969 | dsa_fdb_dump_cb_t *cb, void *data) |
b8f126a8 SW |
970 | { |
971 | struct mt7530_priv *priv = ds->priv; | |
972 | struct mt7530_fdb _fdb = { 0 }; | |
973 | int cnt = MT7530_NUM_FDB_RECORDS; | |
974 | int ret = 0; | |
975 | u32 rsp = 0; | |
976 | ||
977 | mutex_lock(&priv->reg_mutex); | |
978 | ||
979 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); | |
980 | if (ret < 0) | |
981 | goto err; | |
982 | ||
983 | do { | |
984 | if (rsp & ATC_SRCH_HIT) { | |
985 | mt7530_fdb_read(priv, &_fdb); | |
986 | if (_fdb.port_mask & BIT(port)) { | |
2bedde1a AS |
987 | ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, |
988 | data); | |
b8f126a8 SW |
989 | if (ret < 0) |
990 | break; | |
991 | } | |
992 | } | |
993 | } while (--cnt && | |
994 | !(rsp & ATC_SRCH_END) && | |
995 | !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); | |
996 | err: | |
997 | mutex_unlock(&priv->reg_mutex); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
83163f7d SW |
1002 | static int |
1003 | mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) | |
1004 | { | |
1005 | struct mt7530_dummy_poll p; | |
1006 | u32 val; | |
1007 | int ret; | |
1008 | ||
1009 | val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; | |
1010 | mt7530_write(priv, MT7530_VTCR, val); | |
1011 | ||
1012 | INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); | |
1013 | ret = readx_poll_timeout(_mt7530_read, &p, val, | |
1014 | !(val & VTCR_BUSY), 20, 20000); | |
1015 | if (ret < 0) { | |
1016 | dev_err(priv->dev, "poll timeout\n"); | |
1017 | return ret; | |
1018 | } | |
1019 | ||
1020 | val = mt7530_read(priv, MT7530_VTCR); | |
1021 | if (val & VTCR_INVALID) { | |
1022 | dev_err(priv->dev, "read VTCR invalid\n"); | |
1023 | return -EINVAL; | |
1024 | } | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static int | |
1030 | mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, | |
1031 | bool vlan_filtering) | |
1032 | { | |
83163f7d SW |
1033 | if (vlan_filtering) { |
1034 | /* The port is being kept as VLAN-unaware port when bridge is | |
1035 | * set up with vlan_filtering not being set, Otherwise, the | |
1036 | * port and the corresponding CPU port is required the setup | |
1037 | * for becoming a VLAN-aware port. | |
1038 | */ | |
1039 | mt7530_port_set_vlan_aware(ds, port); | |
1040 | mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); | |
e3ee07d1 VO |
1041 | } else { |
1042 | mt7530_port_set_vlan_unaware(ds, port); | |
83163f7d SW |
1043 | } |
1044 | ||
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | static int | |
1049 | mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, | |
1050 | const struct switchdev_obj_port_vlan *vlan) | |
1051 | { | |
1052 | /* nothing needed */ | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | static void | |
1058 | mt7530_hw_vlan_add(struct mt7530_priv *priv, | |
1059 | struct mt7530_hw_vlan_entry *entry) | |
1060 | { | |
1061 | u8 new_members; | |
1062 | u32 val; | |
1063 | ||
1064 | new_members = entry->old_members | BIT(entry->port) | | |
1065 | BIT(MT7530_CPU_PORT); | |
1066 | ||
1067 | /* Validate the entry with independent learning, create egress tag per | |
1068 | * VLAN and joining the port as one of the port members. | |
1069 | */ | |
1070 | val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; | |
1071 | mt7530_write(priv, MT7530_VAWD1, val); | |
1072 | ||
1073 | /* Decide whether adding tag or not for those outgoing packets from the | |
1074 | * port inside the VLAN. | |
1075 | */ | |
1076 | val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : | |
1077 | MT7530_VLAN_EGRESS_TAG; | |
1078 | mt7530_rmw(priv, MT7530_VAWD2, | |
1079 | ETAG_CTRL_P_MASK(entry->port), | |
1080 | ETAG_CTRL_P(entry->port, val)); | |
1081 | ||
1082 | /* CPU port is always taken as a tagged port for serving more than one | |
1083 | * VLANs across and also being applied with egress type stack mode for | |
1084 | * that VLAN tags would be appended after hardware special tag used as | |
1085 | * DSA tag. | |
1086 | */ | |
1087 | mt7530_rmw(priv, MT7530_VAWD2, | |
1088 | ETAG_CTRL_P_MASK(MT7530_CPU_PORT), | |
1089 | ETAG_CTRL_P(MT7530_CPU_PORT, | |
1090 | MT7530_VLAN_EGRESS_STACK)); | |
1091 | } | |
1092 | ||
1093 | static void | |
1094 | mt7530_hw_vlan_del(struct mt7530_priv *priv, | |
1095 | struct mt7530_hw_vlan_entry *entry) | |
1096 | { | |
1097 | u8 new_members; | |
1098 | u32 val; | |
1099 | ||
1100 | new_members = entry->old_members & ~BIT(entry->port); | |
1101 | ||
1102 | val = mt7530_read(priv, MT7530_VAWD1); | |
1103 | if (!(val & VLAN_VALID)) { | |
1104 | dev_err(priv->dev, | |
1105 | "Cannot be deleted due to invalid entry\n"); | |
1106 | return; | |
1107 | } | |
1108 | ||
1109 | /* If certain member apart from CPU port is still alive in the VLAN, | |
1110 | * the entry would be kept valid. Otherwise, the entry is got to be | |
1111 | * disabled. | |
1112 | */ | |
1113 | if (new_members && new_members != BIT(MT7530_CPU_PORT)) { | |
1114 | val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | | |
1115 | VLAN_VALID; | |
1116 | mt7530_write(priv, MT7530_VAWD1, val); | |
1117 | } else { | |
1118 | mt7530_write(priv, MT7530_VAWD1, 0); | |
1119 | mt7530_write(priv, MT7530_VAWD2, 0); | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | static void | |
1124 | mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, | |
1125 | struct mt7530_hw_vlan_entry *entry, | |
1126 | mt7530_vlan_op vlan_op) | |
1127 | { | |
1128 | u32 val; | |
1129 | ||
1130 | /* Fetch entry */ | |
1131 | mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); | |
1132 | ||
1133 | val = mt7530_read(priv, MT7530_VAWD1); | |
1134 | ||
1135 | entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; | |
1136 | ||
1137 | /* Manipulate entry */ | |
1138 | vlan_op(priv, entry); | |
1139 | ||
1140 | /* Flush result to hardware */ | |
1141 | mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); | |
1142 | } | |
1143 | ||
1144 | static void | |
1145 | mt7530_port_vlan_add(struct dsa_switch *ds, int port, | |
1146 | const struct switchdev_obj_port_vlan *vlan) | |
1147 | { | |
1148 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
1149 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
1150 | struct mt7530_hw_vlan_entry new_entry; | |
1151 | struct mt7530_priv *priv = ds->priv; | |
1152 | u16 vid; | |
1153 | ||
1154 | /* The port is kept as VLAN-unaware if bridge with vlan_filtering not | |
1155 | * being set. | |
1156 | */ | |
68bb8ea8 | 1157 | if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) |
83163f7d SW |
1158 | return; |
1159 | ||
1160 | mutex_lock(&priv->reg_mutex); | |
1161 | ||
1162 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { | |
1163 | mt7530_hw_vlan_entry_init(&new_entry, port, untagged); | |
1164 | mt7530_hw_vlan_update(priv, vid, &new_entry, | |
1165 | mt7530_hw_vlan_add); | |
1166 | } | |
1167 | ||
1168 | if (pvid) { | |
1169 | mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, | |
1170 | G0_PORT_VID(vlan->vid_end)); | |
1171 | priv->ports[port].pvid = vlan->vid_end; | |
1172 | } | |
1173 | ||
1174 | mutex_unlock(&priv->reg_mutex); | |
1175 | } | |
1176 | ||
1177 | static int | |
1178 | mt7530_port_vlan_del(struct dsa_switch *ds, int port, | |
1179 | const struct switchdev_obj_port_vlan *vlan) | |
1180 | { | |
1181 | struct mt7530_hw_vlan_entry target_entry; | |
1182 | struct mt7530_priv *priv = ds->priv; | |
1183 | u16 vid, pvid; | |
1184 | ||
1185 | /* The port is kept as VLAN-unaware if bridge with vlan_filtering not | |
1186 | * being set. | |
1187 | */ | |
68bb8ea8 | 1188 | if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) |
83163f7d SW |
1189 | return 0; |
1190 | ||
1191 | mutex_lock(&priv->reg_mutex); | |
1192 | ||
1193 | pvid = priv->ports[port].pvid; | |
1194 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { | |
1195 | mt7530_hw_vlan_entry_init(&target_entry, port, 0); | |
1196 | mt7530_hw_vlan_update(priv, vid, &target_entry, | |
1197 | mt7530_hw_vlan_del); | |
1198 | ||
1199 | /* PVID is being restored to the default whenever the PVID port | |
1200 | * is being removed from the VLAN. | |
1201 | */ | |
1202 | if (pvid == vid) | |
1203 | pvid = G0_PORT_VID_DEF; | |
1204 | } | |
1205 | ||
1206 | mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); | |
1207 | priv->ports[port].pvid = pvid; | |
1208 | ||
1209 | mutex_unlock(&priv->reg_mutex); | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
37feab60 DQ |
1214 | static int mt7530_port_mirror_add(struct dsa_switch *ds, int port, |
1215 | struct dsa_mall_mirror_tc_entry *mirror, | |
1216 | bool ingress) | |
1217 | { | |
1218 | struct mt7530_priv *priv = ds->priv; | |
1219 | u32 val; | |
1220 | ||
1221 | /* Check for existent entry */ | |
1222 | if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) | |
1223 | return -EEXIST; | |
1224 | ||
1225 | val = mt7530_read(priv, MT7530_MFC); | |
1226 | ||
1227 | /* MT7530 only supports one monitor port */ | |
1228 | if (val & MIRROR_EN && MIRROR_PORT(val) != mirror->to_local_port) | |
1229 | return -EEXIST; | |
1230 | ||
1231 | val |= MIRROR_EN; | |
1232 | val &= ~MIRROR_MASK; | |
1233 | val |= mirror->to_local_port; | |
1234 | mt7530_write(priv, MT7530_MFC, val); | |
1235 | ||
1236 | val = mt7530_read(priv, MT7530_PCR_P(port)); | |
1237 | if (ingress) { | |
1238 | val |= PORT_RX_MIR; | |
1239 | priv->mirror_rx |= BIT(port); | |
1240 | } else { | |
1241 | val |= PORT_TX_MIR; | |
1242 | priv->mirror_tx |= BIT(port); | |
1243 | } | |
1244 | mt7530_write(priv, MT7530_PCR_P(port), val); | |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | static void mt7530_port_mirror_del(struct dsa_switch *ds, int port, | |
1250 | struct dsa_mall_mirror_tc_entry *mirror) | |
1251 | { | |
1252 | struct mt7530_priv *priv = ds->priv; | |
1253 | u32 val; | |
1254 | ||
1255 | val = mt7530_read(priv, MT7530_PCR_P(port)); | |
1256 | if (mirror->ingress) { | |
1257 | val &= ~PORT_RX_MIR; | |
1258 | priv->mirror_rx &= ~BIT(port); | |
1259 | } else { | |
1260 | val &= ~PORT_TX_MIR; | |
1261 | priv->mirror_tx &= ~BIT(port); | |
1262 | } | |
1263 | mt7530_write(priv, MT7530_PCR_P(port), val); | |
1264 | ||
1265 | if (!priv->mirror_rx && !priv->mirror_tx) { | |
1266 | val = mt7530_read(priv, MT7530_MFC); | |
1267 | val &= ~MIRROR_EN; | |
1268 | mt7530_write(priv, MT7530_MFC, val); | |
1269 | } | |
1270 | } | |
1271 | ||
b8f126a8 | 1272 | static enum dsa_tag_protocol |
4d776482 FF |
1273 | mtk_get_tag_protocol(struct dsa_switch *ds, int port, |
1274 | enum dsa_tag_protocol mp) | |
b8f126a8 SW |
1275 | { |
1276 | struct mt7530_priv *priv = ds->priv; | |
1277 | ||
5ed4e3eb | 1278 | if (port != MT7530_CPU_PORT) { |
b8f126a8 SW |
1279 | dev_warn(priv->dev, |
1280 | "port not matched with tagging CPU port\n"); | |
1281 | return DSA_TAG_PROTO_NONE; | |
1282 | } else { | |
1283 | return DSA_TAG_PROTO_MTK; | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | static int | |
1288 | mt7530_setup(struct dsa_switch *ds) | |
1289 | { | |
1290 | struct mt7530_priv *priv = ds->priv; | |
38f790a8 RD |
1291 | struct device_node *phy_node; |
1292 | struct device_node *mac_np; | |
b8f126a8 | 1293 | struct mt7530_dummy_poll p; |
38f790a8 | 1294 | phy_interface_t interface; |
ca366d6c RD |
1295 | struct device_node *dn; |
1296 | u32 id, val; | |
1297 | int ret, i; | |
b8f126a8 | 1298 | |
0abfd494 | 1299 | /* The parent node of master netdev which holds the common system |
b8f126a8 SW |
1300 | * controller also is the container for two GMACs nodes representing |
1301 | * as two netdev instances. | |
1302 | */ | |
68bb8ea8 | 1303 | dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; |
b8f126a8 | 1304 | |
ddda1ac1 GU |
1305 | if (priv->id == ID_MT7530) { |
1306 | priv->ethernet = syscon_node_to_regmap(dn); | |
1307 | if (IS_ERR(priv->ethernet)) | |
1308 | return PTR_ERR(priv->ethernet); | |
1309 | ||
1310 | regulator_set_voltage(priv->core_pwr, 1000000, 1000000); | |
1311 | ret = regulator_enable(priv->core_pwr); | |
1312 | if (ret < 0) { | |
1313 | dev_err(priv->dev, | |
1314 | "Failed to enable core power: %d\n", ret); | |
1315 | return ret; | |
1316 | } | |
b8f126a8 | 1317 | |
ddda1ac1 GU |
1318 | regulator_set_voltage(priv->io_pwr, 3300000, 3300000); |
1319 | ret = regulator_enable(priv->io_pwr); | |
1320 | if (ret < 0) { | |
1321 | dev_err(priv->dev, "Failed to enable io pwr: %d\n", | |
1322 | ret); | |
1323 | return ret; | |
1324 | } | |
b8f126a8 SW |
1325 | } |
1326 | ||
1327 | /* Reset whole chip through gpio pin or memory-mapped registers for | |
1328 | * different type of hardware | |
1329 | */ | |
1330 | if (priv->mcm) { | |
1331 | reset_control_assert(priv->rstc); | |
1332 | usleep_range(1000, 1100); | |
1333 | reset_control_deassert(priv->rstc); | |
1334 | } else { | |
1335 | gpiod_set_value_cansleep(priv->reset, 0); | |
1336 | usleep_range(1000, 1100); | |
1337 | gpiod_set_value_cansleep(priv->reset, 1); | |
1338 | } | |
1339 | ||
1340 | /* Waiting for MT7530 got to stable */ | |
1341 | INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); | |
1342 | ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, | |
1343 | 20, 1000000); | |
1344 | if (ret < 0) { | |
1345 | dev_err(priv->dev, "reset timeout\n"); | |
1346 | return ret; | |
1347 | } | |
1348 | ||
1349 | id = mt7530_read(priv, MT7530_CREV); | |
1350 | id >>= CHIP_NAME_SHIFT; | |
1351 | if (id != MT7530_ID) { | |
1352 | dev_err(priv->dev, "chip %x can't be supported\n", id); | |
1353 | return -ENODEV; | |
1354 | } | |
1355 | ||
1356 | /* Reset the switch through internal reset */ | |
1357 | mt7530_write(priv, MT7530_SYS_CTRL, | |
1358 | SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | | |
1359 | SYS_CTRL_REG_RST); | |
1360 | ||
1361 | /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ | |
1362 | val = mt7530_read(priv, MT7530_MHWTRAP); | |
1363 | val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; | |
1364 | val |= MHWTRAP_MANUAL; | |
1365 | mt7530_write(priv, MT7530_MHWTRAP, val); | |
1366 | ||
ca366d6c RD |
1367 | priv->p6_interface = PHY_INTERFACE_MODE_NA; |
1368 | ||
b8f126a8 SW |
1369 | /* Enable and reset MIB counters */ |
1370 | mt7530_mib_reset(ds); | |
1371 | ||
1372 | mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); | |
1373 | ||
1374 | for (i = 0; i < MT7530_NUM_PORTS; i++) { | |
1375 | /* Disable forwarding by default on all ports */ | |
1376 | mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, | |
1377 | PCR_MATRIX_CLR); | |
1378 | ||
1379 | if (dsa_is_cpu_port(ds, i)) | |
1380 | mt7530_cpu_port_enable(priv, i); | |
1381 | else | |
75104db0 | 1382 | mt7530_port_disable(ds, i); |
b8f126a8 SW |
1383 | } |
1384 | ||
38f790a8 RD |
1385 | /* Setup port 5 */ |
1386 | priv->p5_intf_sel = P5_DISABLED; | |
1387 | interface = PHY_INTERFACE_MODE_NA; | |
1388 | ||
1389 | if (!dsa_is_unused_port(ds, 5)) { | |
1390 | priv->p5_intf_sel = P5_INTF_SEL_GMAC5; | |
0c65b2b9 AL |
1391 | ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); |
1392 | if (ret && ret != -ENODEV) | |
1393 | return ret; | |
38f790a8 RD |
1394 | } else { |
1395 | /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ | |
1396 | for_each_child_of_node(dn, mac_np) { | |
1397 | if (!of_device_is_compatible(mac_np, | |
1398 | "mediatek,eth-mac")) | |
1399 | continue; | |
1400 | ||
1401 | ret = of_property_read_u32(mac_np, "reg", &id); | |
1402 | if (ret < 0 || id != 1) | |
1403 | continue; | |
1404 | ||
1405 | phy_node = of_parse_phandle(mac_np, "phy-handle", 0); | |
1406 | if (phy_node->parent == priv->dev->of_node->parent) { | |
0c65b2b9 AL |
1407 | ret = of_get_phy_mode(mac_np, &interface); |
1408 | if (ret && ret != -ENODEV) | |
1409 | return ret; | |
38f790a8 RD |
1410 | id = of_mdio_parse_addr(ds->dev, phy_node); |
1411 | if (id == 0) | |
1412 | priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; | |
1413 | if (id == 4) | |
1414 | priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; | |
1415 | } | |
1416 | of_node_put(phy_node); | |
1417 | break; | |
1418 | } | |
1419 | } | |
1420 | ||
1421 | mt7530_setup_port5(ds, interface); | |
1422 | ||
b8f126a8 | 1423 | /* Flush the FDB table */ |
18bd5949 | 1424 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); |
b8f126a8 SW |
1425 | if (ret < 0) |
1426 | return ret; | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
ca366d6c RD |
1431 | static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port, |
1432 | unsigned int mode, | |
1433 | const struct phylink_link_state *state) | |
1434 | { | |
1435 | struct mt7530_priv *priv = ds->priv; | |
1436 | u32 mcr_cur, mcr_new; | |
1437 | ||
1438 | switch (port) { | |
1439 | case 0: /* Internal phy */ | |
1440 | case 1: | |
1441 | case 2: | |
1442 | case 3: | |
1443 | case 4: | |
1444 | if (state->interface != PHY_INTERFACE_MODE_GMII) | |
1445 | return; | |
1446 | break; | |
38f790a8 RD |
1447 | case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ |
1448 | if (priv->p5_interface == state->interface) | |
1449 | break; | |
1450 | if (!phy_interface_mode_is_rgmii(state->interface) && | |
1451 | state->interface != PHY_INTERFACE_MODE_MII && | |
1452 | state->interface != PHY_INTERFACE_MODE_GMII) | |
1453 | return; | |
1454 | ||
1455 | mt7530_setup_port5(ds, state->interface); | |
1456 | break; | |
ca366d6c RD |
1457 | case 6: /* 1st cpu port */ |
1458 | if (priv->p6_interface == state->interface) | |
1459 | break; | |
1460 | ||
1461 | if (state->interface != PHY_INTERFACE_MODE_RGMII && | |
1462 | state->interface != PHY_INTERFACE_MODE_TRGMII) | |
1463 | return; | |
1464 | ||
1465 | /* Setup TX circuit incluing relevant PAD and driving */ | |
1466 | mt7530_pad_clk_setup(ds, state->interface); | |
1467 | ||
1468 | if (priv->id == ID_MT7530) { | |
1469 | /* Setup RX circuit, relevant PAD and driving on the | |
1470 | * host which must be placed after the setup on the | |
1471 | * device side is all finished. | |
1472 | */ | |
1473 | mt7623_pad_clk_setup(ds); | |
1474 | } | |
1475 | ||
1476 | priv->p6_interface = state->interface; | |
1477 | break; | |
1478 | default: | |
1479 | dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); | |
1480 | return; | |
1481 | } | |
1482 | ||
1483 | if (phylink_autoneg_inband(mode)) { | |
1484 | dev_err(ds->dev, "%s: in-band negotiation unsupported\n", | |
1485 | __func__); | |
1486 | return; | |
1487 | } | |
1488 | ||
1489 | mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); | |
1490 | mcr_new = mcr_cur; | |
1d01145f | 1491 | mcr_new &= ~PMCR_LINK_SETTINGS_MASK; |
ca366d6c | 1492 | mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | |
22259471 | 1493 | PMCR_BACKPR_EN | PMCR_FORCE_MODE; |
ca366d6c | 1494 | |
38f790a8 RD |
1495 | /* Are we connected to external phy */ |
1496 | if (port == 5 && dsa_is_user_port(ds, 5)) | |
1497 | mcr_new |= PMCR_EXT_PHY; | |
1498 | ||
ca366d6c RD |
1499 | if (mcr_new != mcr_cur) |
1500 | mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); | |
1501 | } | |
1502 | ||
1503 | static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port, | |
1504 | unsigned int mode, | |
1505 | phy_interface_t interface) | |
1506 | { | |
1507 | struct mt7530_priv *priv = ds->priv; | |
1508 | ||
1d01145f | 1509 | mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); |
ca366d6c RD |
1510 | } |
1511 | ||
1512 | static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port, | |
1513 | unsigned int mode, | |
1514 | phy_interface_t interface, | |
5b502a7b RK |
1515 | struct phy_device *phydev, |
1516 | int speed, int duplex, | |
1517 | bool tx_pause, bool rx_pause) | |
ca366d6c RD |
1518 | { |
1519 | struct mt7530_priv *priv = ds->priv; | |
1d01145f RD |
1520 | u32 mcr; |
1521 | ||
1522 | mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; | |
1523 | ||
1524 | switch (speed) { | |
1525 | case SPEED_1000: | |
1526 | mcr |= PMCR_FORCE_SPEED_1000; | |
1527 | break; | |
1528 | case SPEED_100: | |
1529 | mcr |= PMCR_FORCE_SPEED_100; | |
1530 | break; | |
1531 | } | |
1532 | if (duplex == DUPLEX_FULL) { | |
1533 | mcr |= PMCR_FORCE_FDX; | |
1534 | if (tx_pause) | |
1535 | mcr |= PMCR_TX_FC_EN; | |
1536 | if (rx_pause) | |
1537 | mcr |= PMCR_RX_FC_EN; | |
1538 | } | |
ca366d6c | 1539 | |
1d01145f | 1540 | mt7530_set(priv, MT7530_PMCR_P(port), mcr); |
ca366d6c RD |
1541 | } |
1542 | ||
1543 | static void mt7530_phylink_validate(struct dsa_switch *ds, int port, | |
1544 | unsigned long *supported, | |
1545 | struct phylink_link_state *state) | |
1546 | { | |
1547 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; | |
1548 | ||
1549 | switch (port) { | |
1550 | case 0: /* Internal phy */ | |
1551 | case 1: | |
1552 | case 2: | |
1553 | case 3: | |
1554 | case 4: | |
1555 | if (state->interface != PHY_INTERFACE_MODE_NA && | |
1556 | state->interface != PHY_INTERFACE_MODE_GMII) | |
1557 | goto unsupported; | |
1558 | break; | |
38f790a8 RD |
1559 | case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ |
1560 | if (state->interface != PHY_INTERFACE_MODE_NA && | |
1561 | !phy_interface_mode_is_rgmii(state->interface) && | |
1562 | state->interface != PHY_INTERFACE_MODE_MII && | |
1563 | state->interface != PHY_INTERFACE_MODE_GMII) | |
1564 | goto unsupported; | |
1565 | break; | |
ca366d6c RD |
1566 | case 6: /* 1st cpu port */ |
1567 | if (state->interface != PHY_INTERFACE_MODE_NA && | |
1568 | state->interface != PHY_INTERFACE_MODE_RGMII && | |
1569 | state->interface != PHY_INTERFACE_MODE_TRGMII) | |
1570 | goto unsupported; | |
1571 | break; | |
1572 | default: | |
1573 | dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); | |
1574 | unsupported: | |
1575 | linkmode_zero(supported); | |
1576 | return; | |
1577 | } | |
1578 | ||
1579 | phylink_set_port_modes(mask); | |
1580 | phylink_set(mask, Autoneg); | |
1581 | ||
38f790a8 RD |
1582 | if (state->interface == PHY_INTERFACE_MODE_TRGMII) { |
1583 | phylink_set(mask, 1000baseT_Full); | |
1584 | } else { | |
ca366d6c RD |
1585 | phylink_set(mask, 10baseT_Half); |
1586 | phylink_set(mask, 10baseT_Full); | |
1587 | phylink_set(mask, 100baseT_Half); | |
1588 | phylink_set(mask, 100baseT_Full); | |
ca366d6c | 1589 | |
38f790a8 RD |
1590 | if (state->interface != PHY_INTERFACE_MODE_MII) { |
1591 | phylink_set(mask, 1000baseT_Half); | |
1592 | phylink_set(mask, 1000baseT_Full); | |
1593 | if (port == 5) | |
1594 | phylink_set(mask, 1000baseX_Full); | |
1595 | } | |
1596 | } | |
ca366d6c RD |
1597 | |
1598 | phylink_set(mask, Pause); | |
1599 | phylink_set(mask, Asym_Pause); | |
1600 | ||
1601 | linkmode_and(supported, supported, mask); | |
1602 | linkmode_and(state->advertising, state->advertising, mask); | |
1603 | } | |
1604 | ||
1605 | static int | |
1606 | mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, | |
1607 | struct phylink_link_state *state) | |
1608 | { | |
1609 | struct mt7530_priv *priv = ds->priv; | |
1610 | u32 pmsr; | |
1611 | ||
1612 | if (port < 0 || port >= MT7530_NUM_PORTS) | |
1613 | return -EINVAL; | |
1614 | ||
1615 | pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); | |
1616 | ||
1617 | state->link = (pmsr & PMSR_LINK); | |
1618 | state->an_complete = state->link; | |
1619 | state->duplex = !!(pmsr & PMSR_DPX); | |
1620 | ||
1621 | switch (pmsr & PMSR_SPEED_MASK) { | |
1622 | case PMSR_SPEED_10: | |
1623 | state->speed = SPEED_10; | |
1624 | break; | |
1625 | case PMSR_SPEED_100: | |
1626 | state->speed = SPEED_100; | |
1627 | break; | |
1628 | case PMSR_SPEED_1000: | |
1629 | state->speed = SPEED_1000; | |
1630 | break; | |
1631 | default: | |
1632 | state->speed = SPEED_UNKNOWN; | |
1633 | break; | |
1634 | } | |
1635 | ||
1636 | state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); | |
1637 | if (pmsr & PMSR_RX_FC) | |
1638 | state->pause |= MLO_PAUSE_RX; | |
1639 | if (pmsr & PMSR_TX_FC) | |
1640 | state->pause |= MLO_PAUSE_TX; | |
1641 | ||
1642 | return 1; | |
1643 | } | |
1644 | ||
d78d6776 | 1645 | static const struct dsa_switch_ops mt7530_switch_ops = { |
b8f126a8 SW |
1646 | .get_tag_protocol = mtk_get_tag_protocol, |
1647 | .setup = mt7530_setup, | |
1648 | .get_strings = mt7530_get_strings, | |
1649 | .phy_read = mt7530_phy_read, | |
1650 | .phy_write = mt7530_phy_write, | |
1651 | .get_ethtool_stats = mt7530_get_ethtool_stats, | |
1652 | .get_sset_count = mt7530_get_sset_count, | |
b8f126a8 SW |
1653 | .port_enable = mt7530_port_enable, |
1654 | .port_disable = mt7530_port_disable, | |
1655 | .port_stp_state_set = mt7530_stp_state_set, | |
1656 | .port_bridge_join = mt7530_port_bridge_join, | |
1657 | .port_bridge_leave = mt7530_port_bridge_leave, | |
b8f126a8 SW |
1658 | .port_fdb_add = mt7530_port_fdb_add, |
1659 | .port_fdb_del = mt7530_port_fdb_del, | |
1660 | .port_fdb_dump = mt7530_port_fdb_dump, | |
83163f7d SW |
1661 | .port_vlan_filtering = mt7530_port_vlan_filtering, |
1662 | .port_vlan_prepare = mt7530_port_vlan_prepare, | |
1663 | .port_vlan_add = mt7530_port_vlan_add, | |
1664 | .port_vlan_del = mt7530_port_vlan_del, | |
37feab60 DQ |
1665 | .port_mirror_add = mt7530_port_mirror_add, |
1666 | .port_mirror_del = mt7530_port_mirror_del, | |
ca366d6c RD |
1667 | .phylink_validate = mt7530_phylink_validate, |
1668 | .phylink_mac_link_state = mt7530_phylink_mac_link_state, | |
1669 | .phylink_mac_config = mt7530_phylink_mac_config, | |
1670 | .phylink_mac_link_down = mt7530_phylink_mac_link_down, | |
1671 | .phylink_mac_link_up = mt7530_phylink_mac_link_up, | |
b8f126a8 SW |
1672 | }; |
1673 | ||
ddda1ac1 GU |
1674 | static const struct of_device_id mt7530_of_match[] = { |
1675 | { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, }, | |
1676 | { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, }, | |
1677 | { /* sentinel */ }, | |
1678 | }; | |
1679 | MODULE_DEVICE_TABLE(of, mt7530_of_match); | |
1680 | ||
b8f126a8 SW |
1681 | static int |
1682 | mt7530_probe(struct mdio_device *mdiodev) | |
1683 | { | |
1684 | struct mt7530_priv *priv; | |
1685 | struct device_node *dn; | |
1686 | ||
1687 | dn = mdiodev->dev.of_node; | |
1688 | ||
1689 | priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); | |
1690 | if (!priv) | |
1691 | return -ENOMEM; | |
1692 | ||
7e99e347 | 1693 | priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); |
b8f126a8 SW |
1694 | if (!priv->ds) |
1695 | return -ENOMEM; | |
1696 | ||
7e99e347 VD |
1697 | priv->ds->dev = &mdiodev->dev; |
1698 | priv->ds->num_ports = DSA_MAX_PORTS; | |
1699 | ||
b8f126a8 SW |
1700 | /* Use medatek,mcm property to distinguish hardware type that would |
1701 | * casues a little bit differences on power-on sequence. | |
1702 | */ | |
1703 | priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); | |
1704 | if (priv->mcm) { | |
1705 | dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); | |
1706 | ||
1707 | priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); | |
1708 | if (IS_ERR(priv->rstc)) { | |
1709 | dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); | |
1710 | return PTR_ERR(priv->rstc); | |
1711 | } | |
1712 | } | |
1713 | ||
ddda1ac1 GU |
1714 | /* Get the hardware identifier from the devicetree node. |
1715 | * We will need it for some of the clock and regulator setup. | |
1716 | */ | |
1717 | priv->id = (unsigned int)(unsigned long) | |
1718 | of_device_get_match_data(&mdiodev->dev); | |
b8f126a8 | 1719 | |
ddda1ac1 GU |
1720 | if (priv->id == ID_MT7530) { |
1721 | priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); | |
1722 | if (IS_ERR(priv->core_pwr)) | |
1723 | return PTR_ERR(priv->core_pwr); | |
1724 | ||
1725 | priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); | |
1726 | if (IS_ERR(priv->io_pwr)) | |
1727 | return PTR_ERR(priv->io_pwr); | |
1728 | } | |
b8f126a8 SW |
1729 | |
1730 | /* Not MCM that indicates switch works as the remote standalone | |
1731 | * integrated circuit so the GPIO pin would be used to complete | |
1732 | * the reset, otherwise memory-mapped register accessing used | |
1733 | * through syscon provides in the case of MCM. | |
1734 | */ | |
1735 | if (!priv->mcm) { | |
1736 | priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", | |
1737 | GPIOD_OUT_LOW); | |
1738 | if (IS_ERR(priv->reset)) { | |
1739 | dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); | |
1740 | return PTR_ERR(priv->reset); | |
1741 | } | |
1742 | } | |
1743 | ||
1744 | priv->bus = mdiodev->bus; | |
1745 | priv->dev = &mdiodev->dev; | |
1746 | priv->ds->priv = priv; | |
1747 | priv->ds->ops = &mt7530_switch_ops; | |
1748 | mutex_init(&priv->reg_mutex); | |
1749 | dev_set_drvdata(&mdiodev->dev, priv); | |
1750 | ||
23c9ee49 | 1751 | return dsa_register_switch(priv->ds); |
b8f126a8 SW |
1752 | } |
1753 | ||
1754 | static void | |
1755 | mt7530_remove(struct mdio_device *mdiodev) | |
1756 | { | |
1757 | struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); | |
1758 | int ret = 0; | |
1759 | ||
1760 | ret = regulator_disable(priv->core_pwr); | |
1761 | if (ret < 0) | |
1762 | dev_err(priv->dev, | |
1763 | "Failed to disable core power: %d\n", ret); | |
1764 | ||
1765 | ret = regulator_disable(priv->io_pwr); | |
1766 | if (ret < 0) | |
1767 | dev_err(priv->dev, "Failed to disable io pwr: %d\n", | |
1768 | ret); | |
1769 | ||
1770 | dsa_unregister_switch(priv->ds); | |
1771 | mutex_destroy(&priv->reg_mutex); | |
1772 | } | |
1773 | ||
b8f126a8 SW |
1774 | static struct mdio_driver mt7530_mdio_driver = { |
1775 | .probe = mt7530_probe, | |
1776 | .remove = mt7530_remove, | |
1777 | .mdiodrv.driver = { | |
1778 | .name = "mt7530", | |
1779 | .of_match_table = mt7530_of_match, | |
1780 | }, | |
1781 | }; | |
1782 | ||
1783 | mdio_module_driver(mt7530_mdio_driver); | |
1784 | ||
1785 | MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); | |
1786 | MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); | |
1787 | MODULE_LICENSE("GPL"); |