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Merge tag 'sh-pfc-for-v5.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-focal-kernel.git] / drivers / net / dsa / mt7530.c
CommitLineData
b8f126a8
SW		 1/*
2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/etherdevice.h>
15#include <linux/if_bridge.h>
16#include <linux/iopoll.h>
17#include <linux/mdio.h>
18#include <linux/mfd/syscon.h>
19#include <linux/module.h>
20#include <linux/netdevice.h>
b8f126a8
SW		 21#include <linux/of_mdio.h>
22#include <linux/of_net.h>
23#include <linux/of_platform.h>
24#include <linux/phy.h>
25#include <linux/regmap.h>
26#include <linux/regulator/consumer.h>
27#include <linux/reset.h>
eb976a55 28#include <linux/gpio/consumer.h>
b8f126a8 29#include <net/dsa.h>
b8f126a8
SW		 30
31#include "mt7530.h"
32
33/* String, offset, and register size in bytes if different from 4 bytes */
34static const struct mt7530_mib_desc mt7530_mib[] = {
35 MIB_DESC(1, 0x00, "TxDrop"),
36 MIB_DESC(1, 0x04, "TxCrcErr"),
37 MIB_DESC(1, 0x08, "TxUnicast"),
38 MIB_DESC(1, 0x0c, "TxMulticast"),
39 MIB_DESC(1, 0x10, "TxBroadcast"),
40 MIB_DESC(1, 0x14, "TxCollision"),
41 MIB_DESC(1, 0x18, "TxSingleCollision"),
42 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
43 MIB_DESC(1, 0x20, "TxDeferred"),
44 MIB_DESC(1, 0x24, "TxLateCollision"),
45 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
46 MIB_DESC(1, 0x2c, "TxPause"),
47 MIB_DESC(1, 0x30, "TxPktSz64"),
48 MIB_DESC(1, 0x34, "TxPktSz65To127"),
49 MIB_DESC(1, 0x38, "TxPktSz128To255"),
50 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
51 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
52 MIB_DESC(1, 0x44, "Tx1024ToMax"),
53 MIB_DESC(2, 0x48, "TxBytes"),
54 MIB_DESC(1, 0x60, "RxDrop"),
55 MIB_DESC(1, 0x64, "RxFiltering"),
56 MIB_DESC(1, 0x6c, "RxMulticast"),
57 MIB_DESC(1, 0x70, "RxBroadcast"),
58 MIB_DESC(1, 0x74, "RxAlignErr"),
59 MIB_DESC(1, 0x78, "RxCrcErr"),
60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
61 MIB_DESC(1, 0x80, "RxFragErr"),
62 MIB_DESC(1, 0x84, "RxOverSzErr"),
63 MIB_DESC(1, 0x88, "RxJabberErr"),
64 MIB_DESC(1, 0x8c, "RxPause"),
65 MIB_DESC(1, 0x90, "RxPktSz64"),
66 MIB_DESC(1, 0x94, "RxPktSz65To127"),
67 MIB_DESC(1, 0x98, "RxPktSz128To255"),
68 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
71 MIB_DESC(2, 0xa8, "RxBytes"),
72 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
73 MIB_DESC(1, 0xb4, "RxIngressDrop"),
74 MIB_DESC(1, 0xb8, "RxArlDrop"),
75};
76
77static int
78mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
79{
80 int ret;
81
82 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
83 if (ret < 0)
84 dev_err(priv->dev,
85 "failed to priv write register\n");
86 return ret;
87}
88
89static u32
90mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
91{
92 int ret;
93 u32 val;
94
95 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
96 if (ret < 0) {
97 dev_err(priv->dev,
98 "failed to priv read register\n");
99 return ret;
100 }
101
102 return val;
103}
104
105static void
106mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
107 u32 mask, u32 set)
108{
109 u32 val;
110
111 val = mt7623_trgmii_read(priv, reg);
112 val &= ~mask;
113 val |= set;
114 mt7623_trgmii_write(priv, reg, val);
115}
116
117static void
118mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
119{
120 mt7623_trgmii_rmw(priv, reg, 0, val);
121}
122
123static void
124mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
125{
126 mt7623_trgmii_rmw(priv, reg, val, 0);
127}
128
129static int
130core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
131{
132 struct mii_bus *bus = priv->bus;
133 int value, ret;
134
135 /* Write the desired MMD Devad */
136 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
137 if (ret < 0)
138 goto err;
139
140 /* Write the desired MMD register address */
141 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
142 if (ret < 0)
143 goto err;
144
145 /* Select the Function : DATA with no post increment */
146 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
147 if (ret < 0)
148 goto err;
149
150 /* Read the content of the MMD's selected register */
151 value = bus->read(bus, 0, MII_MMD_DATA);
152
153 return value;
154err:
155 dev_err(&bus->dev, "failed to read mmd register\n");
156
157 return ret;
158}
159
160static int
161core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
162 int devad, u32 data)
163{
164 struct mii_bus *bus = priv->bus;
165 int ret;
166
167 /* Write the desired MMD Devad */
168 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
169 if (ret < 0)
170 goto err;
171
172 /* Write the desired MMD register address */
173 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
174 if (ret < 0)
175 goto err;
176
177 /* Select the Function : DATA with no post increment */
178 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
179 if (ret < 0)
180 goto err;
181
182 /* Write the data into MMD's selected register */
183 ret = bus->write(bus, 0, MII_MMD_DATA, data);
184err:
185 if (ret < 0)
186 dev_err(&bus->dev,
187 "failed to write mmd register\n");
188 return ret;
189}
190
191static void
192core_write(struct mt7530_priv *priv, u32 reg, u32 val)
193{
194 struct mii_bus *bus = priv->bus;
195
196 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
197
198 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
199
200 mutex_unlock(&bus->mdio_lock);
201}
202
203static void
204core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
205{
206 struct mii_bus *bus = priv->bus;
207 u32 val;
208
209 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
210
211 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
212 val &= ~mask;
213 val |= set;
214 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
215
216 mutex_unlock(&bus->mdio_lock);
217}
218
219static void
220core_set(struct mt7530_priv *priv, u32 reg, u32 val)
221{
222 core_rmw(priv, reg, 0, val);
223}
224
225static void
226core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
227{
228 core_rmw(priv, reg, val, 0);
229}
230
231static int
232mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
233{
234 struct mii_bus *bus = priv->bus;
235 u16 page, r, lo, hi;
236 int ret;
237
238 page = (reg >> 6) & 0x3ff;
239 r = (reg >> 2) & 0xf;
240 lo = val & 0xffff;
241 hi = val >> 16;
242
243 /* MT7530 uses 31 as the pseudo port */
244 ret = bus->write(bus, 0x1f, 0x1f, page);
245 if (ret < 0)
246 goto err;
247
248 ret = bus->write(bus, 0x1f, r, lo);
249 if (ret < 0)
250 goto err;
251
252 ret = bus->write(bus, 0x1f, 0x10, hi);
253err:
254 if (ret < 0)
255 dev_err(&bus->dev,
256 "failed to write mt7530 register\n");
257 return ret;
258}
259
260static u32
261mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
262{
263 struct mii_bus *bus = priv->bus;
264 u16 page, r, lo, hi;
265 int ret;
266
267 page = (reg >> 6) & 0x3ff;
268 r = (reg >> 2) & 0xf;
269
270 /* MT7530 uses 31 as the pseudo port */
271 ret = bus->write(bus, 0x1f, 0x1f, page);
272 if (ret < 0) {
273 dev_err(&bus->dev,
274 "failed to read mt7530 register\n");
275 return ret;
276 }
277
278 lo = bus->read(bus, 0x1f, r);
279 hi = bus->read(bus, 0x1f, 0x10);
280
281 return (hi << 16) | (lo & 0xffff);
282}
283
284static void
285mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
286{
287 struct mii_bus *bus = priv->bus;
288
289 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
290
291 mt7530_mii_write(priv, reg, val);
292
293 mutex_unlock(&bus->mdio_lock);
294}
295
296static u32
297_mt7530_read(struct mt7530_dummy_poll *p)
298{
299 struct mii_bus *bus = p->priv->bus;
300 u32 val;
301
302 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
303
304 val = mt7530_mii_read(p->priv, p->reg);
305
306 mutex_unlock(&bus->mdio_lock);
307
308 return val;
309}
310
311static u32
312mt7530_read(struct mt7530_priv *priv, u32 reg)
313{
314 struct mt7530_dummy_poll p;
315
316 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
317 return _mt7530_read(&p);
318}
319
320static void
321mt7530_rmw(struct mt7530_priv *priv, u32 reg,
322 u32 mask, u32 set)
323{
324 struct mii_bus *bus = priv->bus;
325 u32 val;
326
327 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
328
329 val = mt7530_mii_read(priv, reg);
330 val &= ~mask;
331 val |= set;
332 mt7530_mii_write(priv, reg, val);
333
334 mutex_unlock(&bus->mdio_lock);
335}
336
337static void
338mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
339{
340 mt7530_rmw(priv, reg, 0, val);
341}
342
343static void
344mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
345{
346 mt7530_rmw(priv, reg, val, 0);
347}
348
349static int
350mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
351{
352 u32 val;
353 int ret;
354 struct mt7530_dummy_poll p;
355
356 /* Set the command operating upon the MAC address entries */
357 val = ATC_BUSY | ATC_MAT(0) | cmd;
358 mt7530_write(priv, MT7530_ATC, val);
359
360 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
361 ret = readx_poll_timeout(_mt7530_read, &p, val,
362 !(val & ATC_BUSY), 20, 20000);
363 if (ret < 0) {
364 dev_err(priv->dev, "reset timeout\n");
365 return ret;
366 }
367
368 /* Additional sanity for read command if the specified
369 * entry is invalid
370 */
371 val = mt7530_read(priv, MT7530_ATC);
372 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
373 return -EINVAL;
374
375 if (rsp)
376 *rsp = val;
377
378 return 0;
379}
380
381static void
382mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
383{
384 u32 reg[3];
385 int i;
386
387 /* Read from ARL table into an array */
388 for (i = 0; i < 3; i++) {
389 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
390
391 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
392 __func__, __LINE__, i, reg[i]);
393 }
394
395 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
396 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
397 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
398 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
399 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
400 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
401 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
402 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
403 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
404 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
405}
406
407static void
408mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
409 u8 port_mask, const u8 *mac,
410 u8 aging, u8 type)
411{
412 u32 reg[3] = { 0 };
413 int i;
414
415 reg[1] |= vid & CVID_MASK;
416 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
417 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
418 /* STATIC_ENT indicate that entry is static wouldn't
419 * be aged out and STATIC_EMP specified as erasing an
420 * entry
421 */
422 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
423 reg[1] |= mac[5] << MAC_BYTE_5;
424 reg[1] |= mac[4] << MAC_BYTE_4;
425 reg[0] |= mac[3] << MAC_BYTE_3;
426 reg[0] |= mac[2] << MAC_BYTE_2;
427 reg[0] |= mac[1] << MAC_BYTE_1;
428 reg[0] |= mac[0] << MAC_BYTE_0;
429
430 /* Write array into the ARL table */
431 for (i = 0; i < 3; i++)
432 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
433}
434
435static int
436mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
437{
438 struct mt7530_priv *priv = ds->priv;
439 u32 ncpo1, ssc_delta, trgint, i;
440
441 switch (mode) {
442 case PHY_INTERFACE_MODE_RGMII:
443 trgint = 0;
444 ncpo1 = 0x0c80;
445 ssc_delta = 0x87;
446 break;
447 case PHY_INTERFACE_MODE_TRGMII:
448 trgint = 1;
449 ncpo1 = 0x1400;
450 ssc_delta = 0x57;
451 break;
452 default:
453 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
454 return -EINVAL;
455 }
456
457 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
458 P6_INTF_MODE(trgint));
459
460 /* Lower Tx Driving for TRGMII path */
461 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
462 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
463 TD_DM_DRVP(8) | TD_DM_DRVN(8));
464
465 /* Setup core clock for MT7530 */
466 if (!trgint) {
467 /* Disable MT7530 core clock */
468 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
469
470 /* Disable PLL, since phy_device has not yet been created
471 * provided for phy_[read,write]_mmd_indirect is called, we
472 * provide our own core_write_mmd_indirect to complete this
473 * function.
474 */
475 core_write_mmd_indirect(priv,
476 CORE_GSWPLL_GRP1,
477 MDIO_MMD_VEND2,
478 0);
479
480 /* Set core clock into 500Mhz */
481 core_write(priv, CORE_GSWPLL_GRP2,
482 RG_GSWPLL_POSDIV_500M(1) |
483 RG_GSWPLL_FBKDIV_500M(25));
484
485 /* Enable PLL */
486 core_write(priv, CORE_GSWPLL_GRP1,
487 RG_GSWPLL_EN_PRE |
488 RG_GSWPLL_POSDIV_200M(2) |
489 RG_GSWPLL_FBKDIV_200M(32));
490
491 /* Enable MT7530 core clock */
492 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
493 }
494
495 /* Setup the MT7530 TRGMII Tx Clock */
496 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
497 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
498 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
499 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
500 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
501 core_write(priv, CORE_PLL_GROUP4,
502 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
503 RG_SYSPLL_BIAS_LPF_EN);
504 core_write(priv, CORE_PLL_GROUP2,
505 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
506 RG_SYSPLL_POSDIV(1));
507 core_write(priv, CORE_PLL_GROUP7,
508 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
509 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
510 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
511 REG_GSWCK_EN | REG_TRGMIICK_EN);
512
513 if (!trgint)
514 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
515 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
516 RD_TAP_MASK, RD_TAP(16));
517 else
518 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
519
520 return 0;
521}
522
523static int
524mt7623_pad_clk_setup(struct dsa_switch *ds)
525{
526 struct mt7530_priv *priv = ds->priv;
527 int i;
528
529 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
530 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
531 TD_DM_DRVP(8) | TD_DM_DRVN(8));
532
533 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
534 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
535
536 return 0;
537}
538
539static void
540mt7530_mib_reset(struct dsa_switch *ds)
541{
542 struct mt7530_priv *priv = ds->priv;
543
544 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
546}
547
548static void
549mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
550{
551 u32 mask = PMCR_TX_EN | PMCR_RX_EN;
552
553 if (enable)
554 mt7530_set(priv, MT7530_PMCR_P(port), mask);
555 else
556 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
557}
558
559static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
560{
561 struct mt7530_priv *priv = ds->priv;
562
563 return mdiobus_read_nested(priv->bus, port, regnum);
564}
565
360cc342
CIK		 566static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
567 u16 val)
b8f126a8
SW		 568{
569 struct mt7530_priv *priv = ds->priv;
570
571 return mdiobus_write_nested(priv->bus, port, regnum, val);
572}
573
574static void
89f09048
FF		 575mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
576 uint8_t *data)
b8f126a8
SW		 577{
578 int i;
579
89f09048
FF		 580 if (stringset != ETH_SS_STATS)
581 return;
582
b8f126a8
SW		 583 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
584 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
585 ETH_GSTRING_LEN);
586}
587
588static void
589mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
590 uint64_t *data)
591{
592 struct mt7530_priv *priv = ds->priv;
593 const struct mt7530_mib_desc *mib;
594 u32 reg, i;
595 u64 hi;
596
597 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
598 mib = &mt7530_mib[i];
599 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
600
601 data[i] = mt7530_read(priv, reg);
602 if (mib->size == 2) {
603 hi = mt7530_read(priv, reg + 4);
604 data[i] |= hi << 32;
605 }
606 }
607}
608
609static int
89f09048 610mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 611{
89f09048
FF		 612 if (sset != ETH_SS_STATS)
613 return 0;
614
b8f126a8
SW		 615 return ARRAY_SIZE(mt7530_mib);
616}
617
618static void mt7530_adjust_link(struct dsa_switch *ds, int port,
619 struct phy_device *phydev)
620{
621 struct mt7530_priv *priv = ds->priv;
622
623 if (phy_is_pseudo_fixed_link(phydev)) {
624 dev_dbg(priv->dev, "phy-mode for master device = %x\n",
625 phydev->interface);
626
627 /* Setup TX circuit incluing relevant PAD and driving */
628 mt7530_pad_clk_setup(ds, phydev->interface);
629
630 /* Setup RX circuit, relevant PAD and driving on the host
631 * which must be placed after the setup on the device side is
632 * all finished.
633 */
634 mt7623_pad_clk_setup(ds);
8e6f1521
JC		 635 } else {
636 u16 lcl_adv = 0, rmt_adv = 0;
637 u8 flowctrl;
638 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
639
640 switch (phydev->speed) {
641 case SPEED_1000:
642 mcr |= PMCR_FORCE_SPEED_1000;
643 break;
644 case SPEED_100:
645 mcr |= PMCR_FORCE_SPEED_100;
646 break;
647 };
648
649 if (phydev->link)
650 mcr |= PMCR_FORCE_LNK;
651
652 if (phydev->duplex) {
653 mcr |= PMCR_FORCE_FDX;
654
655 if (phydev->pause)
656 rmt_adv = LPA_PAUSE_CAP;
657 if (phydev->asym_pause)
658 rmt_adv |= LPA_PAUSE_ASYM;
659
3c1bcc86
AL		 660 lcl_adv = linkmode_adv_to_lcl_adv_t(
661 phydev->advertising);
8e6f1521
JC		 662 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
663
664 if (flowctrl & FLOW_CTRL_TX)
665 mcr |= PMCR_TX_FC_EN;
666 if (flowctrl & FLOW_CTRL_RX)
667 mcr |= PMCR_RX_FC_EN;
668 }
669 mt7530_write(priv, MT7530_PMCR_P(port), mcr);
b8f126a8
SW		 670 }
671}
672
673static int
674mt7530_cpu_port_enable(struct mt7530_priv *priv,
675 int port)
676{
677 /* Enable Mediatek header mode on the cpu port */
678 mt7530_write(priv, MT7530_PVC_P(port),
679 PORT_SPEC_TAG);
680
681 /* Setup the MAC by default for the cpu port */
682 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
683
684 /* Disable auto learning on the cpu port */
685 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
686
687 /* Unknown unicast frame fordwarding to the cpu port */
688 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
689
690 /* CPU port gets connected to all user ports of
691 * the switch
692 */
693 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 694 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8
SW		 695
696 return 0;
697}
698
699static int
700mt7530_port_enable(struct dsa_switch *ds, int port,
701 struct phy_device *phy)
702{
703 struct mt7530_priv *priv = ds->priv;
704
705 mutex_lock(&priv->reg_mutex);
706
707 /* Setup the MAC for the user port */
708 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
709
710 /* Allow the user port gets connected to the cpu port and also
711 * restore the port matrix if the port is the member of a certain
712 * bridge.
713 */
714 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
715 priv->ports[port].enable = true;
716 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
717 priv->ports[port].pm);
718 mt7530_port_set_status(priv, port, 1);
719
720 mutex_unlock(&priv->reg_mutex);
721
722 return 0;
723}
724
725static void
726mt7530_port_disable(struct dsa_switch *ds, int port,
727 struct phy_device *phy)
728{
729 struct mt7530_priv *priv = ds->priv;
730
731 mutex_lock(&priv->reg_mutex);
732
733 /* Clear up all port matrix which could be restored in the next
734 * enablement for the port.
735 */
736 priv->ports[port].enable = false;
737 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
738 PCR_MATRIX_CLR);
739 mt7530_port_set_status(priv, port, 0);
740
741 mutex_unlock(&priv->reg_mutex);
742}
743
744static void
745mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
746{
747 struct mt7530_priv *priv = ds->priv;
748 u32 stp_state;
749
750 switch (state) {
751 case BR_STATE_DISABLED:
752 stp_state = MT7530_STP_DISABLED;
753 break;
754 case BR_STATE_BLOCKING:
755 stp_state = MT7530_STP_BLOCKING;
756 break;
757 case BR_STATE_LISTENING:
758 stp_state = MT7530_STP_LISTENING;
759 break;
760 case BR_STATE_LEARNING:
761 stp_state = MT7530_STP_LEARNING;
762 break;
763 case BR_STATE_FORWARDING:
764 default:
765 stp_state = MT7530_STP_FORWARDING;
766 break;
767 }
768
769 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
770}
771
772static int
773mt7530_port_bridge_join(struct dsa_switch *ds, int port,
774 struct net_device *bridge)
775{
776 struct mt7530_priv *priv = ds->priv;
777 u32 port_bitmap = BIT(MT7530_CPU_PORT);
778 int i;
779
780 mutex_lock(&priv->reg_mutex);
781
782 for (i = 0; i < MT7530_NUM_PORTS; i++) {
783 /* Add this port to the port matrix of the other ports in the
784 * same bridge. If the port is disabled, port matrix is kept
785 * and not being setup until the port becomes enabled.
786 */
4a5b85ff 787 if (dsa_is_user_port(ds, i) && i != port) {
c8652c83 788 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 789 continue;
790 if (priv->ports[i].enable)
791 mt7530_set(priv, MT7530_PCR_P(i),
792 PCR_MATRIX(BIT(port)));
793 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
794
795 port_bitmap |= BIT(i);
796 }
797 }
798
799 /* Add the all other ports to this port matrix. */
800 if (priv->ports[port].enable)
801 mt7530_rmw(priv, MT7530_PCR_P(port),
802 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
803 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
804
805 mutex_unlock(&priv->reg_mutex);
806
807 return 0;
808}
809
83163f7d
SW		 810static void
811mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
812{
813 struct mt7530_priv *priv = ds->priv;
814 bool all_user_ports_removed = true;
815 int i;
816
817 /* When a port is removed from the bridge, the port would be set up
818 * back to the default as is at initial boot which is a VLAN-unaware
819 * port.
820 */
821 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
822 MT7530_PORT_MATRIX_MODE);
823 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
824 VLAN_ATTR(MT7530_VLAN_TRANSPARENT));
825
826 priv->ports[port].vlan_filtering = false;
827
828 for (i = 0; i < MT7530_NUM_PORTS; i++) {
829 if (dsa_is_user_port(ds, i) &&
830 priv->ports[i].vlan_filtering) {
831 all_user_ports_removed = false;
832 break;
833 }
834 }
835
836 /* CPU port also does the same thing until all user ports belonging to
837 * the CPU port get out of VLAN filtering mode.
838 */
839 if (all_user_ports_removed) {
840 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
841 PCR_MATRIX(dsa_user_ports(priv->ds)));
842 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT),
843 PORT_SPEC_TAG);
844 }
845}
846
847static void
848mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
849{
850 struct mt7530_priv *priv = ds->priv;
851
852 /* The real fabric path would be decided on the membership in the
853 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
854 * means potential VLAN can be consisting of certain subset of all
855 * ports.
856 */
857 mt7530_rmw(priv, MT7530_PCR_P(port),
858 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
859
860 /* Trapped into security mode allows packet forwarding through VLAN
861 * table lookup.
862 */
863 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
864 MT7530_PORT_SECURITY_MODE);
865
866 /* Set the port as a user port which is to be able to recognize VID
867 * from incoming packets before fetching entry within the VLAN table.
868 */
869 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
870 VLAN_ATTR(MT7530_VLAN_USER));
871}
872
b8f126a8
SW		 873static void
874mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
875 struct net_device *bridge)
876{
877 struct mt7530_priv *priv = ds->priv;
878 int i;
879
880 mutex_lock(&priv->reg_mutex);
881
882 for (i = 0; i < MT7530_NUM_PORTS; i++) {
883 /* Remove this port from the port matrix of the other ports
884 * in the same bridge. If the port is disabled, port matrix
885 * is kept and not being setup until the port becomes enabled.
83163f7d
SW		 886 * And the other port's port matrix cannot be broken when the
887 * other port is still a VLAN-aware port.
b8f126a8 888 */
83163f7d
SW		 889 if (!priv->ports[i].vlan_filtering &&
890 dsa_is_user_port(ds, i) && i != port) {
c8652c83 891 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 892 continue;
893 if (priv->ports[i].enable)
894 mt7530_clear(priv, MT7530_PCR_P(i),
895 PCR_MATRIX(BIT(port)));
896 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
897 }
898 }
899
900 /* Set the cpu port to be the only one in the port matrix of
901 * this port.
902 */
903 if (priv->ports[port].enable)
904 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
905 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
906 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
907
83163f7d
SW		 908 mt7530_port_set_vlan_unaware(ds, port);
909
b8f126a8
SW		 910 mutex_unlock(&priv->reg_mutex);
911}
912
913static int
b8f126a8 914mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 915 const unsigned char *addr, u16 vid)
b8f126a8
SW		 916{
917 struct mt7530_priv *priv = ds->priv;
1b6dd556 918 int ret;
b8f126a8
SW		 919 u8 port_mask = BIT(port);
920
921 mutex_lock(&priv->reg_mutex);
6c2c1dcb 922 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 923 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 924 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 925
926 return ret;
b8f126a8
SW		 927}
928
929static int
930mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 931 const unsigned char *addr, u16 vid)
b8f126a8
SW		 932{
933 struct mt7530_priv *priv = ds->priv;
934 int ret;
935 u8 port_mask = BIT(port);
936
937 mutex_lock(&priv->reg_mutex);
6c2c1dcb 938 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 939 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 940 mutex_unlock(&priv->reg_mutex);
941
942 return ret;
943}
944
945static int
946mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 947 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 948{
949 struct mt7530_priv *priv = ds->priv;
950 struct mt7530_fdb _fdb = { 0 };
951 int cnt = MT7530_NUM_FDB_RECORDS;
952 int ret = 0;
953 u32 rsp = 0;
954
955 mutex_lock(&priv->reg_mutex);
956
957 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
958 if (ret < 0)
959 goto err;
960
961 do {
962 if (rsp & ATC_SRCH_HIT) {
963 mt7530_fdb_read(priv, &_fdb);
964 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 965 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
966 data);
b8f126a8
SW		 967 if (ret < 0)
968 break;
969 }
970 }
971 } while (--cnt &&
972 !(rsp & ATC_SRCH_END) &&
973 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
974err:
975 mutex_unlock(&priv->reg_mutex);
976
977 return 0;
978}
979
83163f7d
SW		 980static int
981mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
982{
983 struct mt7530_dummy_poll p;
984 u32 val;
985 int ret;
986
987 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
988 mt7530_write(priv, MT7530_VTCR, val);
989
990 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
991 ret = readx_poll_timeout(_mt7530_read, &p, val,
992 !(val & VTCR_BUSY), 20, 20000);
993 if (ret < 0) {
994 dev_err(priv->dev, "poll timeout\n");
995 return ret;
996 }
997
998 val = mt7530_read(priv, MT7530_VTCR);
999 if (val & VTCR_INVALID) {
1000 dev_err(priv->dev, "read VTCR invalid\n");
1001 return -EINVAL;
1002 }
1003
1004 return 0;
1005}
1006
1007static int
1008mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1009 bool vlan_filtering)
1010{
1011 struct mt7530_priv *priv = ds->priv;
1012
1013 priv->ports[port].vlan_filtering = vlan_filtering;
1014
1015 if (vlan_filtering) {
1016 /* The port is being kept as VLAN-unaware port when bridge is
1017 * set up with vlan_filtering not being set, Otherwise, the
1018 * port and the corresponding CPU port is required the setup
1019 * for becoming a VLAN-aware port.
1020 */
1021 mt7530_port_set_vlan_aware(ds, port);
1022 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1023 }
1024
1025 return 0;
1026}
1027
1028static int
1029mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1030 const struct switchdev_obj_port_vlan *vlan)
1031{
1032 /* nothing needed */
1033
1034 return 0;
1035}
1036
1037static void
1038mt7530_hw_vlan_add(struct mt7530_priv *priv,
1039 struct mt7530_hw_vlan_entry *entry)
1040{
1041 u8 new_members;
1042 u32 val;
1043
1044 new_members = entry->old_members | BIT(entry->port) |
1045 BIT(MT7530_CPU_PORT);
1046
1047 /* Validate the entry with independent learning, create egress tag per
1048 * VLAN and joining the port as one of the port members.
1049 */
1050 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1051 mt7530_write(priv, MT7530_VAWD1, val);
1052
1053 /* Decide whether adding tag or not for those outgoing packets from the
1054 * port inside the VLAN.
1055 */
1056 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1057 MT7530_VLAN_EGRESS_TAG;
1058 mt7530_rmw(priv, MT7530_VAWD2,
1059 ETAG_CTRL_P_MASK(entry->port),
1060 ETAG_CTRL_P(entry->port, val));
1061
1062 /* CPU port is always taken as a tagged port for serving more than one
1063 * VLANs across and also being applied with egress type stack mode for
1064 * that VLAN tags would be appended after hardware special tag used as
1065 * DSA tag.
1066 */
1067 mt7530_rmw(priv, MT7530_VAWD2,
1068 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1069 ETAG_CTRL_P(MT7530_CPU_PORT,
1070 MT7530_VLAN_EGRESS_STACK));
1071}
1072
1073static void
1074mt7530_hw_vlan_del(struct mt7530_priv *priv,
1075 struct mt7530_hw_vlan_entry *entry)
1076{
1077 u8 new_members;
1078 u32 val;
1079
1080 new_members = entry->old_members & ~BIT(entry->port);
1081
1082 val = mt7530_read(priv, MT7530_VAWD1);
1083 if (!(val & VLAN_VALID)) {
1084 dev_err(priv->dev,
1085 "Cannot be deleted due to invalid entry\n");
1086 return;
1087 }
1088
1089 /* If certain member apart from CPU port is still alive in the VLAN,
1090 * the entry would be kept valid. Otherwise, the entry is got to be
1091 * disabled.
1092 */
1093 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1094 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1095 VLAN_VALID;
1096 mt7530_write(priv, MT7530_VAWD1, val);
1097 } else {
1098 mt7530_write(priv, MT7530_VAWD1, 0);
1099 mt7530_write(priv, MT7530_VAWD2, 0);
1100 }
1101}
1102
1103static void
1104mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1105 struct mt7530_hw_vlan_entry *entry,
1106 mt7530_vlan_op vlan_op)
1107{
1108 u32 val;
1109
1110 /* Fetch entry */
1111 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1112
1113 val = mt7530_read(priv, MT7530_VAWD1);
1114
1115 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1116
1117 /* Manipulate entry */
1118 vlan_op(priv, entry);
1119
1120 /* Flush result to hardware */
1121 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1122}
1123
1124static void
1125mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1126 const struct switchdev_obj_port_vlan *vlan)
1127{
1128 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1129 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1130 struct mt7530_hw_vlan_entry new_entry;
1131 struct mt7530_priv *priv = ds->priv;
1132 u16 vid;
1133
1134 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1135 * being set.
1136 */
1137 if (!priv->ports[port].vlan_filtering)
1138 return;
1139
1140 mutex_lock(&priv->reg_mutex);
1141
1142 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1143 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1144 mt7530_hw_vlan_update(priv, vid, &new_entry,
1145 mt7530_hw_vlan_add);
1146 }
1147
1148 if (pvid) {
1149 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1150 G0_PORT_VID(vlan->vid_end));
1151 priv->ports[port].pvid = vlan->vid_end;
1152 }
1153
1154 mutex_unlock(&priv->reg_mutex);
1155}
1156
1157static int
1158mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1159 const struct switchdev_obj_port_vlan *vlan)
1160{
1161 struct mt7530_hw_vlan_entry target_entry;
1162 struct mt7530_priv *priv = ds->priv;
1163 u16 vid, pvid;
1164
1165 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1166 * being set.
1167 */
1168 if (!priv->ports[port].vlan_filtering)
1169 return 0;
1170
1171 mutex_lock(&priv->reg_mutex);
1172
1173 pvid = priv->ports[port].pvid;
1174 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1175 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1176 mt7530_hw_vlan_update(priv, vid, &target_entry,
1177 mt7530_hw_vlan_del);
1178
1179 /* PVID is being restored to the default whenever the PVID port
1180 * is being removed from the VLAN.
1181 */
1182 if (pvid == vid)
1183 pvid = G0_PORT_VID_DEF;
1184 }
1185
1186 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1187 priv->ports[port].pvid = pvid;
1188
1189 mutex_unlock(&priv->reg_mutex);
1190
1191 return 0;
1192}
1193
b8f126a8 1194static enum dsa_tag_protocol
5ed4e3eb 1195mtk_get_tag_protocol(struct dsa_switch *ds, int port)
b8f126a8
SW		 1196{
1197 struct mt7530_priv *priv = ds->priv;
1198
5ed4e3eb 1199 if (port != MT7530_CPU_PORT) {
b8f126a8
SW		 1200 dev_warn(priv->dev,
1201 "port not matched with tagging CPU port\n");
1202 return DSA_TAG_PROTO_NONE;
1203 } else {
1204 return DSA_TAG_PROTO_MTK;
1205 }
1206}
1207
1208static int
1209mt7530_setup(struct dsa_switch *ds)
1210{
1211 struct mt7530_priv *priv = ds->priv;
1212 int ret, i;
1213 u32 id, val;
1214 struct device_node *dn;
1215 struct mt7530_dummy_poll p;
1216
0abfd494 1217 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 1218 * controller also is the container for two GMACs nodes representing
1219 * as two netdev instances.
1220 */
f8b8b1cd 1221 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
b8f126a8
SW		 1222 priv->ethernet = syscon_node_to_regmap(dn);
1223 if (IS_ERR(priv->ethernet))
1224 return PTR_ERR(priv->ethernet);
1225
1226 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1227 ret = regulator_enable(priv->core_pwr);
1228 if (ret < 0) {
1229 dev_err(priv->dev,
1230 "Failed to enable core power: %d\n", ret);
1231 return ret;
1232 }
1233
1234 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1235 ret = regulator_enable(priv->io_pwr);
1236 if (ret < 0) {
1237 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1238 ret);
1239 return ret;
1240 }
1241
1242 /* Reset whole chip through gpio pin or memory-mapped registers for
1243 * different type of hardware
1244 */
1245 if (priv->mcm) {
1246 reset_control_assert(priv->rstc);
1247 usleep_range(1000, 1100);
1248 reset_control_deassert(priv->rstc);
1249 } else {
1250 gpiod_set_value_cansleep(priv->reset, 0);
1251 usleep_range(1000, 1100);
1252 gpiod_set_value_cansleep(priv->reset, 1);
1253 }
1254
1255 /* Waiting for MT7530 got to stable */
1256 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1257 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1258 20, 1000000);
1259 if (ret < 0) {
1260 dev_err(priv->dev, "reset timeout\n");
1261 return ret;
1262 }
1263
1264 id = mt7530_read(priv, MT7530_CREV);
1265 id >>= CHIP_NAME_SHIFT;
1266 if (id != MT7530_ID) {
1267 dev_err(priv->dev, "chip %x can't be supported\n", id);
1268 return -ENODEV;
1269 }
1270
1271 /* Reset the switch through internal reset */
1272 mt7530_write(priv, MT7530_SYS_CTRL,
1273 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1274 SYS_CTRL_REG_RST);
1275
1276 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1277 val = mt7530_read(priv, MT7530_MHWTRAP);
1278 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1279 val |= MHWTRAP_MANUAL;
1280 mt7530_write(priv, MT7530_MHWTRAP, val);
1281
1282 /* Enable and reset MIB counters */
1283 mt7530_mib_reset(ds);
1284
1285 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
1286
1287 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1288 /* Disable forwarding by default on all ports */
1289 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1290 PCR_MATRIX_CLR);
1291
1292 if (dsa_is_cpu_port(ds, i))
1293 mt7530_cpu_port_enable(priv, i);
1294 else
1295 mt7530_port_disable(ds, i, NULL);
1296 }
1297
1298 /* Flush the FDB table */
18bd5949 1299 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 1300 if (ret < 0)
1301 return ret;
1302
1303 return 0;
1304}
1305
d78d6776 1306static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8
SW		 1307 .get_tag_protocol = mtk_get_tag_protocol,
1308 .setup = mt7530_setup,
1309 .get_strings = mt7530_get_strings,
1310 .phy_read = mt7530_phy_read,
1311 .phy_write = mt7530_phy_write,
1312 .get_ethtool_stats = mt7530_get_ethtool_stats,
1313 .get_sset_count = mt7530_get_sset_count,
1314 .adjust_link = mt7530_adjust_link,
1315 .port_enable = mt7530_port_enable,
1316 .port_disable = mt7530_port_disable,
1317 .port_stp_state_set = mt7530_stp_state_set,
1318 .port_bridge_join = mt7530_port_bridge_join,
1319 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 1320 .port_fdb_add = mt7530_port_fdb_add,
1321 .port_fdb_del = mt7530_port_fdb_del,
1322 .port_fdb_dump = mt7530_port_fdb_dump,
83163f7d
SW		 1323 .port_vlan_filtering = mt7530_port_vlan_filtering,
1324 .port_vlan_prepare = mt7530_port_vlan_prepare,
1325 .port_vlan_add = mt7530_port_vlan_add,
1326 .port_vlan_del = mt7530_port_vlan_del,
b8f126a8
SW		 1327};
1328
1329static int
1330mt7530_probe(struct mdio_device *mdiodev)
1331{
1332 struct mt7530_priv *priv;
1333 struct device_node *dn;
1334
1335 dn = mdiodev->dev.of_node;
1336
1337 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1338 if (!priv)
1339 return -ENOMEM;
1340
1341 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1342 if (!priv->ds)
1343 return -ENOMEM;
1344
1345 /* Use medatek,mcm property to distinguish hardware type that would
1346 * casues a little bit differences on power-on sequence.
1347 */
1348 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1349 if (priv->mcm) {
1350 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1351
1352 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1353 if (IS_ERR(priv->rstc)) {
1354 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1355 return PTR_ERR(priv->rstc);
1356 }
1357 }
1358
1359 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1360 if (IS_ERR(priv->core_pwr))
1361 return PTR_ERR(priv->core_pwr);
1362
1363 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1364 if (IS_ERR(priv->io_pwr))
1365 return PTR_ERR(priv->io_pwr);
1366
1367 /* Not MCM that indicates switch works as the remote standalone
1368 * integrated circuit so the GPIO pin would be used to complete
1369 * the reset, otherwise memory-mapped register accessing used
1370 * through syscon provides in the case of MCM.
1371 */
1372 if (!priv->mcm) {
1373 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1374 GPIOD_OUT_LOW);
1375 if (IS_ERR(priv->reset)) {
1376 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1377 return PTR_ERR(priv->reset);
1378 }
1379 }
1380
1381 priv->bus = mdiodev->bus;
1382 priv->dev = &mdiodev->dev;
1383 priv->ds->priv = priv;
1384 priv->ds->ops = &mt7530_switch_ops;
1385 mutex_init(&priv->reg_mutex);
1386 dev_set_drvdata(&mdiodev->dev, priv);
1387
23c9ee49 1388 return dsa_register_switch(priv->ds);
b8f126a8
SW		 1389}
1390
1391static void
1392mt7530_remove(struct mdio_device *mdiodev)
1393{
1394 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1395 int ret = 0;
1396
1397 ret = regulator_disable(priv->core_pwr);
1398 if (ret < 0)
1399 dev_err(priv->dev,
1400 "Failed to disable core power: %d\n", ret);
1401
1402 ret = regulator_disable(priv->io_pwr);
1403 if (ret < 0)
1404 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1405 ret);
1406
1407 dsa_unregister_switch(priv->ds);
1408 mutex_destroy(&priv->reg_mutex);
1409}
1410
1411static const struct of_device_id mt7530_of_match[] = {
1412 { .compatible = "mediatek,mt7530" },
1413 { /* sentinel */ },
1414};
3c82b372 1415MODULE_DEVICE_TABLE(of, mt7530_of_match);
b8f126a8
SW		 1416
1417static struct mdio_driver mt7530_mdio_driver = {
1418 .probe = mt7530_probe,
1419 .remove = mt7530_remove,
1420 .mdiodrv.driver = {
1421 .name = "mt7530",
1422 .of_match_table = mt7530_of_match,
1423 },
1424};
1425
1426mdio_module_driver(mt7530_mdio_driver);
1427
1428MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1429MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1430MODULE_LICENSE("GPL");
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