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b8f126a8 SW |
1 | /* |
2 | * Mediatek MT7530 DSA Switch driver | |
3 | * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/if_bridge.h> | |
16 | #include <linux/iopoll.h> | |
17 | #include <linux/mdio.h> | |
18 | #include <linux/mfd/syscon.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/netdevice.h> | |
21 | #include <linux/of_gpio.h> | |
22 | #include <linux/of_mdio.h> | |
23 | #include <linux/of_net.h> | |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/phy.h> | |
26 | #include <linux/regmap.h> | |
27 | #include <linux/regulator/consumer.h> | |
28 | #include <linux/reset.h> | |
29 | #include <net/dsa.h> | |
30 | #include <net/switchdev.h> | |
31 | ||
32 | #include "mt7530.h" | |
33 | ||
34 | /* String, offset, and register size in bytes if different from 4 bytes */ | |
35 | static const struct mt7530_mib_desc mt7530_mib[] = { | |
36 | MIB_DESC(1, 0x00, "TxDrop"), | |
37 | MIB_DESC(1, 0x04, "TxCrcErr"), | |
38 | MIB_DESC(1, 0x08, "TxUnicast"), | |
39 | MIB_DESC(1, 0x0c, "TxMulticast"), | |
40 | MIB_DESC(1, 0x10, "TxBroadcast"), | |
41 | MIB_DESC(1, 0x14, "TxCollision"), | |
42 | MIB_DESC(1, 0x18, "TxSingleCollision"), | |
43 | MIB_DESC(1, 0x1c, "TxMultipleCollision"), | |
44 | MIB_DESC(1, 0x20, "TxDeferred"), | |
45 | MIB_DESC(1, 0x24, "TxLateCollision"), | |
46 | MIB_DESC(1, 0x28, "TxExcessiveCollistion"), | |
47 | MIB_DESC(1, 0x2c, "TxPause"), | |
48 | MIB_DESC(1, 0x30, "TxPktSz64"), | |
49 | MIB_DESC(1, 0x34, "TxPktSz65To127"), | |
50 | MIB_DESC(1, 0x38, "TxPktSz128To255"), | |
51 | MIB_DESC(1, 0x3c, "TxPktSz256To511"), | |
52 | MIB_DESC(1, 0x40, "TxPktSz512To1023"), | |
53 | MIB_DESC(1, 0x44, "Tx1024ToMax"), | |
54 | MIB_DESC(2, 0x48, "TxBytes"), | |
55 | MIB_DESC(1, 0x60, "RxDrop"), | |
56 | MIB_DESC(1, 0x64, "RxFiltering"), | |
57 | MIB_DESC(1, 0x6c, "RxMulticast"), | |
58 | MIB_DESC(1, 0x70, "RxBroadcast"), | |
59 | MIB_DESC(1, 0x74, "RxAlignErr"), | |
60 | MIB_DESC(1, 0x78, "RxCrcErr"), | |
61 | MIB_DESC(1, 0x7c, "RxUnderSizeErr"), | |
62 | MIB_DESC(1, 0x80, "RxFragErr"), | |
63 | MIB_DESC(1, 0x84, "RxOverSzErr"), | |
64 | MIB_DESC(1, 0x88, "RxJabberErr"), | |
65 | MIB_DESC(1, 0x8c, "RxPause"), | |
66 | MIB_DESC(1, 0x90, "RxPktSz64"), | |
67 | MIB_DESC(1, 0x94, "RxPktSz65To127"), | |
68 | MIB_DESC(1, 0x98, "RxPktSz128To255"), | |
69 | MIB_DESC(1, 0x9c, "RxPktSz256To511"), | |
70 | MIB_DESC(1, 0xa0, "RxPktSz512To1023"), | |
71 | MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), | |
72 | MIB_DESC(2, 0xa8, "RxBytes"), | |
73 | MIB_DESC(1, 0xb0, "RxCtrlDrop"), | |
74 | MIB_DESC(1, 0xb4, "RxIngressDrop"), | |
75 | MIB_DESC(1, 0xb8, "RxArlDrop"), | |
76 | }; | |
77 | ||
78 | static int | |
79 | mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
80 | { | |
81 | int ret; | |
82 | ||
83 | ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); | |
84 | if (ret < 0) | |
85 | dev_err(priv->dev, | |
86 | "failed to priv write register\n"); | |
87 | return ret; | |
88 | } | |
89 | ||
90 | static u32 | |
91 | mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) | |
92 | { | |
93 | int ret; | |
94 | u32 val; | |
95 | ||
96 | ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); | |
97 | if (ret < 0) { | |
98 | dev_err(priv->dev, | |
99 | "failed to priv read register\n"); | |
100 | return ret; | |
101 | } | |
102 | ||
103 | return val; | |
104 | } | |
105 | ||
106 | static void | |
107 | mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, | |
108 | u32 mask, u32 set) | |
109 | { | |
110 | u32 val; | |
111 | ||
112 | val = mt7623_trgmii_read(priv, reg); | |
113 | val &= ~mask; | |
114 | val |= set; | |
115 | mt7623_trgmii_write(priv, reg, val); | |
116 | } | |
117 | ||
118 | static void | |
119 | mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) | |
120 | { | |
121 | mt7623_trgmii_rmw(priv, reg, 0, val); | |
122 | } | |
123 | ||
124 | static void | |
125 | mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) | |
126 | { | |
127 | mt7623_trgmii_rmw(priv, reg, val, 0); | |
128 | } | |
129 | ||
130 | static int | |
131 | core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) | |
132 | { | |
133 | struct mii_bus *bus = priv->bus; | |
134 | int value, ret; | |
135 | ||
136 | /* Write the desired MMD Devad */ | |
137 | ret = bus->write(bus, 0, MII_MMD_CTRL, devad); | |
138 | if (ret < 0) | |
139 | goto err; | |
140 | ||
141 | /* Write the desired MMD register address */ | |
142 | ret = bus->write(bus, 0, MII_MMD_DATA, prtad); | |
143 | if (ret < 0) | |
144 | goto err; | |
145 | ||
146 | /* Select the Function : DATA with no post increment */ | |
147 | ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); | |
148 | if (ret < 0) | |
149 | goto err; | |
150 | ||
151 | /* Read the content of the MMD's selected register */ | |
152 | value = bus->read(bus, 0, MII_MMD_DATA); | |
153 | ||
154 | return value; | |
155 | err: | |
156 | dev_err(&bus->dev, "failed to read mmd register\n"); | |
157 | ||
158 | return ret; | |
159 | } | |
160 | ||
161 | static int | |
162 | core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, | |
163 | int devad, u32 data) | |
164 | { | |
165 | struct mii_bus *bus = priv->bus; | |
166 | int ret; | |
167 | ||
168 | /* Write the desired MMD Devad */ | |
169 | ret = bus->write(bus, 0, MII_MMD_CTRL, devad); | |
170 | if (ret < 0) | |
171 | goto err; | |
172 | ||
173 | /* Write the desired MMD register address */ | |
174 | ret = bus->write(bus, 0, MII_MMD_DATA, prtad); | |
175 | if (ret < 0) | |
176 | goto err; | |
177 | ||
178 | /* Select the Function : DATA with no post increment */ | |
179 | ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); | |
180 | if (ret < 0) | |
181 | goto err; | |
182 | ||
183 | /* Write the data into MMD's selected register */ | |
184 | ret = bus->write(bus, 0, MII_MMD_DATA, data); | |
185 | err: | |
186 | if (ret < 0) | |
187 | dev_err(&bus->dev, | |
188 | "failed to write mmd register\n"); | |
189 | return ret; | |
190 | } | |
191 | ||
192 | static void | |
193 | core_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
194 | { | |
195 | struct mii_bus *bus = priv->bus; | |
196 | ||
197 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
198 | ||
199 | core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); | |
200 | ||
201 | mutex_unlock(&bus->mdio_lock); | |
202 | } | |
203 | ||
204 | static void | |
205 | core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) | |
206 | { | |
207 | struct mii_bus *bus = priv->bus; | |
208 | u32 val; | |
209 | ||
210 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
211 | ||
212 | val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); | |
213 | val &= ~mask; | |
214 | val |= set; | |
215 | core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); | |
216 | ||
217 | mutex_unlock(&bus->mdio_lock); | |
218 | } | |
219 | ||
220 | static void | |
221 | core_set(struct mt7530_priv *priv, u32 reg, u32 val) | |
222 | { | |
223 | core_rmw(priv, reg, 0, val); | |
224 | } | |
225 | ||
226 | static void | |
227 | core_clear(struct mt7530_priv *priv, u32 reg, u32 val) | |
228 | { | |
229 | core_rmw(priv, reg, val, 0); | |
230 | } | |
231 | ||
232 | static int | |
233 | mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
234 | { | |
235 | struct mii_bus *bus = priv->bus; | |
236 | u16 page, r, lo, hi; | |
237 | int ret; | |
238 | ||
239 | page = (reg >> 6) & 0x3ff; | |
240 | r = (reg >> 2) & 0xf; | |
241 | lo = val & 0xffff; | |
242 | hi = val >> 16; | |
243 | ||
244 | /* MT7530 uses 31 as the pseudo port */ | |
245 | ret = bus->write(bus, 0x1f, 0x1f, page); | |
246 | if (ret < 0) | |
247 | goto err; | |
248 | ||
249 | ret = bus->write(bus, 0x1f, r, lo); | |
250 | if (ret < 0) | |
251 | goto err; | |
252 | ||
253 | ret = bus->write(bus, 0x1f, 0x10, hi); | |
254 | err: | |
255 | if (ret < 0) | |
256 | dev_err(&bus->dev, | |
257 | "failed to write mt7530 register\n"); | |
258 | return ret; | |
259 | } | |
260 | ||
261 | static u32 | |
262 | mt7530_mii_read(struct mt7530_priv *priv, u32 reg) | |
263 | { | |
264 | struct mii_bus *bus = priv->bus; | |
265 | u16 page, r, lo, hi; | |
266 | int ret; | |
267 | ||
268 | page = (reg >> 6) & 0x3ff; | |
269 | r = (reg >> 2) & 0xf; | |
270 | ||
271 | /* MT7530 uses 31 as the pseudo port */ | |
272 | ret = bus->write(bus, 0x1f, 0x1f, page); | |
273 | if (ret < 0) { | |
274 | dev_err(&bus->dev, | |
275 | "failed to read mt7530 register\n"); | |
276 | return ret; | |
277 | } | |
278 | ||
279 | lo = bus->read(bus, 0x1f, r); | |
280 | hi = bus->read(bus, 0x1f, 0x10); | |
281 | ||
282 | return (hi << 16) | (lo & 0xffff); | |
283 | } | |
284 | ||
285 | static void | |
286 | mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) | |
287 | { | |
288 | struct mii_bus *bus = priv->bus; | |
289 | ||
290 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
291 | ||
292 | mt7530_mii_write(priv, reg, val); | |
293 | ||
294 | mutex_unlock(&bus->mdio_lock); | |
295 | } | |
296 | ||
297 | static u32 | |
298 | _mt7530_read(struct mt7530_dummy_poll *p) | |
299 | { | |
300 | struct mii_bus *bus = p->priv->bus; | |
301 | u32 val; | |
302 | ||
303 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
304 | ||
305 | val = mt7530_mii_read(p->priv, p->reg); | |
306 | ||
307 | mutex_unlock(&bus->mdio_lock); | |
308 | ||
309 | return val; | |
310 | } | |
311 | ||
312 | static u32 | |
313 | mt7530_read(struct mt7530_priv *priv, u32 reg) | |
314 | { | |
315 | struct mt7530_dummy_poll p; | |
316 | ||
317 | INIT_MT7530_DUMMY_POLL(&p, priv, reg); | |
318 | return _mt7530_read(&p); | |
319 | } | |
320 | ||
321 | static void | |
322 | mt7530_rmw(struct mt7530_priv *priv, u32 reg, | |
323 | u32 mask, u32 set) | |
324 | { | |
325 | struct mii_bus *bus = priv->bus; | |
326 | u32 val; | |
327 | ||
328 | mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); | |
329 | ||
330 | val = mt7530_mii_read(priv, reg); | |
331 | val &= ~mask; | |
332 | val |= set; | |
333 | mt7530_mii_write(priv, reg, val); | |
334 | ||
335 | mutex_unlock(&bus->mdio_lock); | |
336 | } | |
337 | ||
338 | static void | |
339 | mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) | |
340 | { | |
341 | mt7530_rmw(priv, reg, 0, val); | |
342 | } | |
343 | ||
344 | static void | |
345 | mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) | |
346 | { | |
347 | mt7530_rmw(priv, reg, val, 0); | |
348 | } | |
349 | ||
350 | static int | |
351 | mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) | |
352 | { | |
353 | u32 val; | |
354 | int ret; | |
355 | struct mt7530_dummy_poll p; | |
356 | ||
357 | /* Set the command operating upon the MAC address entries */ | |
358 | val = ATC_BUSY | ATC_MAT(0) | cmd; | |
359 | mt7530_write(priv, MT7530_ATC, val); | |
360 | ||
361 | INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); | |
362 | ret = readx_poll_timeout(_mt7530_read, &p, val, | |
363 | !(val & ATC_BUSY), 20, 20000); | |
364 | if (ret < 0) { | |
365 | dev_err(priv->dev, "reset timeout\n"); | |
366 | return ret; | |
367 | } | |
368 | ||
369 | /* Additional sanity for read command if the specified | |
370 | * entry is invalid | |
371 | */ | |
372 | val = mt7530_read(priv, MT7530_ATC); | |
373 | if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) | |
374 | return -EINVAL; | |
375 | ||
376 | if (rsp) | |
377 | *rsp = val; | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static void | |
383 | mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) | |
384 | { | |
385 | u32 reg[3]; | |
386 | int i; | |
387 | ||
388 | /* Read from ARL table into an array */ | |
389 | for (i = 0; i < 3; i++) { | |
390 | reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); | |
391 | ||
392 | dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", | |
393 | __func__, __LINE__, i, reg[i]); | |
394 | } | |
395 | ||
396 | fdb->vid = (reg[1] >> CVID) & CVID_MASK; | |
397 | fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; | |
398 | fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; | |
399 | fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; | |
400 | fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; | |
401 | fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; | |
402 | fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; | |
403 | fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; | |
404 | fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; | |
405 | fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; | |
406 | } | |
407 | ||
408 | static void | |
409 | mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, | |
410 | u8 port_mask, const u8 *mac, | |
411 | u8 aging, u8 type) | |
412 | { | |
413 | u32 reg[3] = { 0 }; | |
414 | int i; | |
415 | ||
416 | reg[1] |= vid & CVID_MASK; | |
417 | reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; | |
418 | reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; | |
419 | /* STATIC_ENT indicate that entry is static wouldn't | |
420 | * be aged out and STATIC_EMP specified as erasing an | |
421 | * entry | |
422 | */ | |
423 | reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; | |
424 | reg[1] |= mac[5] << MAC_BYTE_5; | |
425 | reg[1] |= mac[4] << MAC_BYTE_4; | |
426 | reg[0] |= mac[3] << MAC_BYTE_3; | |
427 | reg[0] |= mac[2] << MAC_BYTE_2; | |
428 | reg[0] |= mac[1] << MAC_BYTE_1; | |
429 | reg[0] |= mac[0] << MAC_BYTE_0; | |
430 | ||
431 | /* Write array into the ARL table */ | |
432 | for (i = 0; i < 3; i++) | |
433 | mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); | |
434 | } | |
435 | ||
436 | static int | |
437 | mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) | |
438 | { | |
439 | struct mt7530_priv *priv = ds->priv; | |
440 | u32 ncpo1, ssc_delta, trgint, i; | |
441 | ||
442 | switch (mode) { | |
443 | case PHY_INTERFACE_MODE_RGMII: | |
444 | trgint = 0; | |
445 | ncpo1 = 0x0c80; | |
446 | ssc_delta = 0x87; | |
447 | break; | |
448 | case PHY_INTERFACE_MODE_TRGMII: | |
449 | trgint = 1; | |
450 | ncpo1 = 0x1400; | |
451 | ssc_delta = 0x57; | |
452 | break; | |
453 | default: | |
454 | dev_err(priv->dev, "xMII mode %d not supported\n", mode); | |
455 | return -EINVAL; | |
456 | } | |
457 | ||
458 | mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, | |
459 | P6_INTF_MODE(trgint)); | |
460 | ||
461 | /* Lower Tx Driving for TRGMII path */ | |
462 | for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) | |
463 | mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), | |
464 | TD_DM_DRVP(8) | TD_DM_DRVN(8)); | |
465 | ||
466 | /* Setup core clock for MT7530 */ | |
467 | if (!trgint) { | |
468 | /* Disable MT7530 core clock */ | |
469 | core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); | |
470 | ||
471 | /* Disable PLL, since phy_device has not yet been created | |
472 | * provided for phy_[read,write]_mmd_indirect is called, we | |
473 | * provide our own core_write_mmd_indirect to complete this | |
474 | * function. | |
475 | */ | |
476 | core_write_mmd_indirect(priv, | |
477 | CORE_GSWPLL_GRP1, | |
478 | MDIO_MMD_VEND2, | |
479 | 0); | |
480 | ||
481 | /* Set core clock into 500Mhz */ | |
482 | core_write(priv, CORE_GSWPLL_GRP2, | |
483 | RG_GSWPLL_POSDIV_500M(1) | | |
484 | RG_GSWPLL_FBKDIV_500M(25)); | |
485 | ||
486 | /* Enable PLL */ | |
487 | core_write(priv, CORE_GSWPLL_GRP1, | |
488 | RG_GSWPLL_EN_PRE | | |
489 | RG_GSWPLL_POSDIV_200M(2) | | |
490 | RG_GSWPLL_FBKDIV_200M(32)); | |
491 | ||
492 | /* Enable MT7530 core clock */ | |
493 | core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); | |
494 | } | |
495 | ||
496 | /* Setup the MT7530 TRGMII Tx Clock */ | |
497 | core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); | |
498 | core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); | |
499 | core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); | |
500 | core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); | |
501 | core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); | |
502 | core_write(priv, CORE_PLL_GROUP4, | |
503 | RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | | |
504 | RG_SYSPLL_BIAS_LPF_EN); | |
505 | core_write(priv, CORE_PLL_GROUP2, | |
506 | RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | | |
507 | RG_SYSPLL_POSDIV(1)); | |
508 | core_write(priv, CORE_PLL_GROUP7, | |
509 | RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | | |
510 | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); | |
511 | core_set(priv, CORE_TRGMII_GSW_CLK_CG, | |
512 | REG_GSWCK_EN | REG_TRGMIICK_EN); | |
513 | ||
514 | if (!trgint) | |
515 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) | |
516 | mt7530_rmw(priv, MT7530_TRGMII_RD(i), | |
517 | RD_TAP_MASK, RD_TAP(16)); | |
518 | else | |
519 | mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII); | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static int | |
525 | mt7623_pad_clk_setup(struct dsa_switch *ds) | |
526 | { | |
527 | struct mt7530_priv *priv = ds->priv; | |
528 | int i; | |
529 | ||
530 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) | |
531 | mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), | |
532 | TD_DM_DRVP(8) | TD_DM_DRVN(8)); | |
533 | ||
534 | mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); | |
535 | mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
540 | static void | |
541 | mt7530_mib_reset(struct dsa_switch *ds) | |
542 | { | |
543 | struct mt7530_priv *priv = ds->priv; | |
544 | ||
545 | mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); | |
546 | mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); | |
547 | } | |
548 | ||
549 | static void | |
550 | mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) | |
551 | { | |
552 | u32 mask = PMCR_TX_EN | PMCR_RX_EN; | |
553 | ||
554 | if (enable) | |
555 | mt7530_set(priv, MT7530_PMCR_P(port), mask); | |
556 | else | |
557 | mt7530_clear(priv, MT7530_PMCR_P(port), mask); | |
558 | } | |
559 | ||
560 | static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) | |
561 | { | |
562 | struct mt7530_priv *priv = ds->priv; | |
563 | ||
564 | return mdiobus_read_nested(priv->bus, port, regnum); | |
565 | } | |
566 | ||
567 | int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
568 | { | |
569 | struct mt7530_priv *priv = ds->priv; | |
570 | ||
571 | return mdiobus_write_nested(priv->bus, port, regnum, val); | |
572 | } | |
573 | ||
574 | static void | |
575 | mt7530_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
576 | { | |
577 | int i; | |
578 | ||
579 | for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) | |
580 | strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, | |
581 | ETH_GSTRING_LEN); | |
582 | } | |
583 | ||
584 | static void | |
585 | mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, | |
586 | uint64_t *data) | |
587 | { | |
588 | struct mt7530_priv *priv = ds->priv; | |
589 | const struct mt7530_mib_desc *mib; | |
590 | u32 reg, i; | |
591 | u64 hi; | |
592 | ||
593 | for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { | |
594 | mib = &mt7530_mib[i]; | |
595 | reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; | |
596 | ||
597 | data[i] = mt7530_read(priv, reg); | |
598 | if (mib->size == 2) { | |
599 | hi = mt7530_read(priv, reg + 4); | |
600 | data[i] |= hi << 32; | |
601 | } | |
602 | } | |
603 | } | |
604 | ||
605 | static int | |
606 | mt7530_get_sset_count(struct dsa_switch *ds) | |
607 | { | |
608 | return ARRAY_SIZE(mt7530_mib); | |
609 | } | |
610 | ||
611 | static void mt7530_adjust_link(struct dsa_switch *ds, int port, | |
612 | struct phy_device *phydev) | |
613 | { | |
614 | struct mt7530_priv *priv = ds->priv; | |
615 | ||
616 | if (phy_is_pseudo_fixed_link(phydev)) { | |
617 | dev_dbg(priv->dev, "phy-mode for master device = %x\n", | |
618 | phydev->interface); | |
619 | ||
620 | /* Setup TX circuit incluing relevant PAD and driving */ | |
621 | mt7530_pad_clk_setup(ds, phydev->interface); | |
622 | ||
623 | /* Setup RX circuit, relevant PAD and driving on the host | |
624 | * which must be placed after the setup on the device side is | |
625 | * all finished. | |
626 | */ | |
627 | mt7623_pad_clk_setup(ds); | |
628 | } | |
629 | } | |
630 | ||
631 | static int | |
632 | mt7530_cpu_port_enable(struct mt7530_priv *priv, | |
633 | int port) | |
634 | { | |
635 | /* Enable Mediatek header mode on the cpu port */ | |
636 | mt7530_write(priv, MT7530_PVC_P(port), | |
637 | PORT_SPEC_TAG); | |
638 | ||
639 | /* Setup the MAC by default for the cpu port */ | |
640 | mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK); | |
641 | ||
642 | /* Disable auto learning on the cpu port */ | |
643 | mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); | |
644 | ||
645 | /* Unknown unicast frame fordwarding to the cpu port */ | |
646 | mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); | |
647 | ||
648 | /* CPU port gets connected to all user ports of | |
649 | * the switch | |
650 | */ | |
651 | mt7530_write(priv, MT7530_PCR_P(port), | |
652 | PCR_MATRIX(priv->ds->enabled_port_mask)); | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | static int | |
658 | mt7530_port_enable(struct dsa_switch *ds, int port, | |
659 | struct phy_device *phy) | |
660 | { | |
661 | struct mt7530_priv *priv = ds->priv; | |
662 | ||
663 | mutex_lock(&priv->reg_mutex); | |
664 | ||
665 | /* Setup the MAC for the user port */ | |
666 | mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK); | |
667 | ||
668 | /* Allow the user port gets connected to the cpu port and also | |
669 | * restore the port matrix if the port is the member of a certain | |
670 | * bridge. | |
671 | */ | |
672 | priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); | |
673 | priv->ports[port].enable = true; | |
674 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, | |
675 | priv->ports[port].pm); | |
676 | mt7530_port_set_status(priv, port, 1); | |
677 | ||
678 | mutex_unlock(&priv->reg_mutex); | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | static void | |
684 | mt7530_port_disable(struct dsa_switch *ds, int port, | |
685 | struct phy_device *phy) | |
686 | { | |
687 | struct mt7530_priv *priv = ds->priv; | |
688 | ||
689 | mutex_lock(&priv->reg_mutex); | |
690 | ||
691 | /* Clear up all port matrix which could be restored in the next | |
692 | * enablement for the port. | |
693 | */ | |
694 | priv->ports[port].enable = false; | |
695 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, | |
696 | PCR_MATRIX_CLR); | |
697 | mt7530_port_set_status(priv, port, 0); | |
698 | ||
699 | mutex_unlock(&priv->reg_mutex); | |
700 | } | |
701 | ||
702 | static void | |
703 | mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) | |
704 | { | |
705 | struct mt7530_priv *priv = ds->priv; | |
706 | u32 stp_state; | |
707 | ||
708 | switch (state) { | |
709 | case BR_STATE_DISABLED: | |
710 | stp_state = MT7530_STP_DISABLED; | |
711 | break; | |
712 | case BR_STATE_BLOCKING: | |
713 | stp_state = MT7530_STP_BLOCKING; | |
714 | break; | |
715 | case BR_STATE_LISTENING: | |
716 | stp_state = MT7530_STP_LISTENING; | |
717 | break; | |
718 | case BR_STATE_LEARNING: | |
719 | stp_state = MT7530_STP_LEARNING; | |
720 | break; | |
721 | case BR_STATE_FORWARDING: | |
722 | default: | |
723 | stp_state = MT7530_STP_FORWARDING; | |
724 | break; | |
725 | } | |
726 | ||
727 | mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); | |
728 | } | |
729 | ||
730 | static int | |
731 | mt7530_port_bridge_join(struct dsa_switch *ds, int port, | |
732 | struct net_device *bridge) | |
733 | { | |
734 | struct mt7530_priv *priv = ds->priv; | |
735 | u32 port_bitmap = BIT(MT7530_CPU_PORT); | |
736 | int i; | |
737 | ||
738 | mutex_lock(&priv->reg_mutex); | |
739 | ||
740 | for (i = 0; i < MT7530_NUM_PORTS; i++) { | |
741 | /* Add this port to the port matrix of the other ports in the | |
742 | * same bridge. If the port is disabled, port matrix is kept | |
743 | * and not being setup until the port becomes enabled. | |
744 | */ | |
745 | if (ds->enabled_port_mask & BIT(i) && i != port) { | |
746 | if (ds->ports[i].bridge_dev != bridge) | |
747 | continue; | |
748 | if (priv->ports[i].enable) | |
749 | mt7530_set(priv, MT7530_PCR_P(i), | |
750 | PCR_MATRIX(BIT(port))); | |
751 | priv->ports[i].pm |= PCR_MATRIX(BIT(port)); | |
752 | ||
753 | port_bitmap |= BIT(i); | |
754 | } | |
755 | } | |
756 | ||
757 | /* Add the all other ports to this port matrix. */ | |
758 | if (priv->ports[port].enable) | |
759 | mt7530_rmw(priv, MT7530_PCR_P(port), | |
760 | PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); | |
761 | priv->ports[port].pm |= PCR_MATRIX(port_bitmap); | |
762 | ||
763 | mutex_unlock(&priv->reg_mutex); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | static void | |
769 | mt7530_port_bridge_leave(struct dsa_switch *ds, int port, | |
770 | struct net_device *bridge) | |
771 | { | |
772 | struct mt7530_priv *priv = ds->priv; | |
773 | int i; | |
774 | ||
775 | mutex_lock(&priv->reg_mutex); | |
776 | ||
777 | for (i = 0; i < MT7530_NUM_PORTS; i++) { | |
778 | /* Remove this port from the port matrix of the other ports | |
779 | * in the same bridge. If the port is disabled, port matrix | |
780 | * is kept and not being setup until the port becomes enabled. | |
781 | */ | |
782 | if (ds->enabled_port_mask & BIT(i) && i != port) { | |
783 | if (ds->ports[i].bridge_dev != bridge) | |
784 | continue; | |
785 | if (priv->ports[i].enable) | |
786 | mt7530_clear(priv, MT7530_PCR_P(i), | |
787 | PCR_MATRIX(BIT(port))); | |
788 | priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); | |
789 | } | |
790 | } | |
791 | ||
792 | /* Set the cpu port to be the only one in the port matrix of | |
793 | * this port. | |
794 | */ | |
795 | if (priv->ports[port].enable) | |
796 | mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, | |
797 | PCR_MATRIX(BIT(MT7530_CPU_PORT))); | |
798 | priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); | |
799 | ||
800 | mutex_unlock(&priv->reg_mutex); | |
801 | } | |
802 | ||
803 | static int | |
804 | mt7530_port_fdb_prepare(struct dsa_switch *ds, int port, | |
805 | const struct switchdev_obj_port_fdb *fdb, | |
806 | struct switchdev_trans *trans) | |
807 | { | |
808 | struct mt7530_priv *priv = ds->priv; | |
809 | int ret; | |
810 | ||
811 | /* Because auto-learned entrie shares the same FDB table. | |
812 | * an entry is reserved with no port_mask to make sure fdb_add | |
813 | * is called while the entry is still available. | |
814 | */ | |
815 | mutex_lock(&priv->reg_mutex); | |
816 | mt7530_fdb_write(priv, fdb->vid, 0, fdb->addr, -1, STATIC_ENT); | |
817 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); | |
818 | mutex_unlock(&priv->reg_mutex); | |
819 | ||
820 | return ret; | |
821 | } | |
822 | ||
823 | static void | |
824 | mt7530_port_fdb_add(struct dsa_switch *ds, int port, | |
825 | const struct switchdev_obj_port_fdb *fdb, | |
826 | struct switchdev_trans *trans) | |
827 | { | |
828 | struct mt7530_priv *priv = ds->priv; | |
829 | u8 port_mask = BIT(port); | |
830 | ||
831 | mutex_lock(&priv->reg_mutex); | |
832 | mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_ENT); | |
833 | mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); | |
834 | mutex_unlock(&priv->reg_mutex); | |
835 | } | |
836 | ||
837 | static int | |
838 | mt7530_port_fdb_del(struct dsa_switch *ds, int port, | |
839 | const struct switchdev_obj_port_fdb *fdb) | |
840 | { | |
841 | struct mt7530_priv *priv = ds->priv; | |
842 | int ret; | |
843 | u8 port_mask = BIT(port); | |
844 | ||
845 | mutex_lock(&priv->reg_mutex); | |
846 | mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_EMP); | |
847 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); | |
848 | mutex_unlock(&priv->reg_mutex); | |
849 | ||
850 | return ret; | |
851 | } | |
852 | ||
853 | static int | |
854 | mt7530_port_fdb_dump(struct dsa_switch *ds, int port, | |
855 | struct switchdev_obj_port_fdb *fdb, | |
856 | int (*cb)(struct switchdev_obj *obj)) | |
857 | { | |
858 | struct mt7530_priv *priv = ds->priv; | |
859 | struct mt7530_fdb _fdb = { 0 }; | |
860 | int cnt = MT7530_NUM_FDB_RECORDS; | |
861 | int ret = 0; | |
862 | u32 rsp = 0; | |
863 | ||
864 | mutex_lock(&priv->reg_mutex); | |
865 | ||
866 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); | |
867 | if (ret < 0) | |
868 | goto err; | |
869 | ||
870 | do { | |
871 | if (rsp & ATC_SRCH_HIT) { | |
872 | mt7530_fdb_read(priv, &_fdb); | |
873 | if (_fdb.port_mask & BIT(port)) { | |
874 | ether_addr_copy(fdb->addr, _fdb.mac); | |
875 | fdb->vid = _fdb.vid; | |
876 | fdb->ndm_state = _fdb.noarp ? | |
877 | NUD_NOARP : NUD_REACHABLE; | |
878 | ret = cb(&fdb->obj); | |
879 | if (ret < 0) | |
880 | break; | |
881 | } | |
882 | } | |
883 | } while (--cnt && | |
884 | !(rsp & ATC_SRCH_END) && | |
885 | !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); | |
886 | err: | |
887 | mutex_unlock(&priv->reg_mutex); | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | static enum dsa_tag_protocol | |
893 | mtk_get_tag_protocol(struct dsa_switch *ds) | |
894 | { | |
895 | struct mt7530_priv *priv = ds->priv; | |
896 | ||
897 | if (!dsa_is_cpu_port(ds, MT7530_CPU_PORT)) { | |
898 | dev_warn(priv->dev, | |
899 | "port not matched with tagging CPU port\n"); | |
900 | return DSA_TAG_PROTO_NONE; | |
901 | } else { | |
902 | return DSA_TAG_PROTO_MTK; | |
903 | } | |
904 | } | |
905 | ||
906 | static int | |
907 | mt7530_setup(struct dsa_switch *ds) | |
908 | { | |
909 | struct mt7530_priv *priv = ds->priv; | |
910 | int ret, i; | |
911 | u32 id, val; | |
912 | struct device_node *dn; | |
913 | struct mt7530_dummy_poll p; | |
914 | ||
915 | /* The parent node of master_netdev which holds the common system | |
916 | * controller also is the container for two GMACs nodes representing | |
917 | * as two netdev instances. | |
918 | */ | |
919 | dn = ds->master_netdev->dev.of_node->parent; | |
920 | priv->ethernet = syscon_node_to_regmap(dn); | |
921 | if (IS_ERR(priv->ethernet)) | |
922 | return PTR_ERR(priv->ethernet); | |
923 | ||
924 | regulator_set_voltage(priv->core_pwr, 1000000, 1000000); | |
925 | ret = regulator_enable(priv->core_pwr); | |
926 | if (ret < 0) { | |
927 | dev_err(priv->dev, | |
928 | "Failed to enable core power: %d\n", ret); | |
929 | return ret; | |
930 | } | |
931 | ||
932 | regulator_set_voltage(priv->io_pwr, 3300000, 3300000); | |
933 | ret = regulator_enable(priv->io_pwr); | |
934 | if (ret < 0) { | |
935 | dev_err(priv->dev, "Failed to enable io pwr: %d\n", | |
936 | ret); | |
937 | return ret; | |
938 | } | |
939 | ||
940 | /* Reset whole chip through gpio pin or memory-mapped registers for | |
941 | * different type of hardware | |
942 | */ | |
943 | if (priv->mcm) { | |
944 | reset_control_assert(priv->rstc); | |
945 | usleep_range(1000, 1100); | |
946 | reset_control_deassert(priv->rstc); | |
947 | } else { | |
948 | gpiod_set_value_cansleep(priv->reset, 0); | |
949 | usleep_range(1000, 1100); | |
950 | gpiod_set_value_cansleep(priv->reset, 1); | |
951 | } | |
952 | ||
953 | /* Waiting for MT7530 got to stable */ | |
954 | INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); | |
955 | ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, | |
956 | 20, 1000000); | |
957 | if (ret < 0) { | |
958 | dev_err(priv->dev, "reset timeout\n"); | |
959 | return ret; | |
960 | } | |
961 | ||
962 | id = mt7530_read(priv, MT7530_CREV); | |
963 | id >>= CHIP_NAME_SHIFT; | |
964 | if (id != MT7530_ID) { | |
965 | dev_err(priv->dev, "chip %x can't be supported\n", id); | |
966 | return -ENODEV; | |
967 | } | |
968 | ||
969 | /* Reset the switch through internal reset */ | |
970 | mt7530_write(priv, MT7530_SYS_CTRL, | |
971 | SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | | |
972 | SYS_CTRL_REG_RST); | |
973 | ||
974 | /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ | |
975 | val = mt7530_read(priv, MT7530_MHWTRAP); | |
976 | val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; | |
977 | val |= MHWTRAP_MANUAL; | |
978 | mt7530_write(priv, MT7530_MHWTRAP, val); | |
979 | ||
980 | /* Enable and reset MIB counters */ | |
981 | mt7530_mib_reset(ds); | |
982 | ||
983 | mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); | |
984 | ||
985 | for (i = 0; i < MT7530_NUM_PORTS; i++) { | |
986 | /* Disable forwarding by default on all ports */ | |
987 | mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, | |
988 | PCR_MATRIX_CLR); | |
989 | ||
990 | if (dsa_is_cpu_port(ds, i)) | |
991 | mt7530_cpu_port_enable(priv, i); | |
992 | else | |
993 | mt7530_port_disable(ds, i, NULL); | |
994 | } | |
995 | ||
996 | /* Flush the FDB table */ | |
997 | ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, 0); | |
998 | if (ret < 0) | |
999 | return ret; | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | static struct dsa_switch_ops mt7530_switch_ops = { | |
1005 | .get_tag_protocol = mtk_get_tag_protocol, | |
1006 | .setup = mt7530_setup, | |
1007 | .get_strings = mt7530_get_strings, | |
1008 | .phy_read = mt7530_phy_read, | |
1009 | .phy_write = mt7530_phy_write, | |
1010 | .get_ethtool_stats = mt7530_get_ethtool_stats, | |
1011 | .get_sset_count = mt7530_get_sset_count, | |
1012 | .adjust_link = mt7530_adjust_link, | |
1013 | .port_enable = mt7530_port_enable, | |
1014 | .port_disable = mt7530_port_disable, | |
1015 | .port_stp_state_set = mt7530_stp_state_set, | |
1016 | .port_bridge_join = mt7530_port_bridge_join, | |
1017 | .port_bridge_leave = mt7530_port_bridge_leave, | |
1018 | .port_fdb_prepare = mt7530_port_fdb_prepare, | |
1019 | .port_fdb_add = mt7530_port_fdb_add, | |
1020 | .port_fdb_del = mt7530_port_fdb_del, | |
1021 | .port_fdb_dump = mt7530_port_fdb_dump, | |
1022 | }; | |
1023 | ||
1024 | static int | |
1025 | mt7530_probe(struct mdio_device *mdiodev) | |
1026 | { | |
1027 | struct mt7530_priv *priv; | |
1028 | struct device_node *dn; | |
1029 | ||
1030 | dn = mdiodev->dev.of_node; | |
1031 | ||
1032 | priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); | |
1033 | if (!priv) | |
1034 | return -ENOMEM; | |
1035 | ||
1036 | priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS); | |
1037 | if (!priv->ds) | |
1038 | return -ENOMEM; | |
1039 | ||
1040 | /* Use medatek,mcm property to distinguish hardware type that would | |
1041 | * casues a little bit differences on power-on sequence. | |
1042 | */ | |
1043 | priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); | |
1044 | if (priv->mcm) { | |
1045 | dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); | |
1046 | ||
1047 | priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); | |
1048 | if (IS_ERR(priv->rstc)) { | |
1049 | dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); | |
1050 | return PTR_ERR(priv->rstc); | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); | |
1055 | if (IS_ERR(priv->core_pwr)) | |
1056 | return PTR_ERR(priv->core_pwr); | |
1057 | ||
1058 | priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); | |
1059 | if (IS_ERR(priv->io_pwr)) | |
1060 | return PTR_ERR(priv->io_pwr); | |
1061 | ||
1062 | /* Not MCM that indicates switch works as the remote standalone | |
1063 | * integrated circuit so the GPIO pin would be used to complete | |
1064 | * the reset, otherwise memory-mapped register accessing used | |
1065 | * through syscon provides in the case of MCM. | |
1066 | */ | |
1067 | if (!priv->mcm) { | |
1068 | priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", | |
1069 | GPIOD_OUT_LOW); | |
1070 | if (IS_ERR(priv->reset)) { | |
1071 | dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); | |
1072 | return PTR_ERR(priv->reset); | |
1073 | } | |
1074 | } | |
1075 | ||
1076 | priv->bus = mdiodev->bus; | |
1077 | priv->dev = &mdiodev->dev; | |
1078 | priv->ds->priv = priv; | |
1079 | priv->ds->ops = &mt7530_switch_ops; | |
1080 | mutex_init(&priv->reg_mutex); | |
1081 | dev_set_drvdata(&mdiodev->dev, priv); | |
1082 | ||
1083 | return dsa_register_switch(priv->ds, &mdiodev->dev); | |
1084 | } | |
1085 | ||
1086 | static void | |
1087 | mt7530_remove(struct mdio_device *mdiodev) | |
1088 | { | |
1089 | struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); | |
1090 | int ret = 0; | |
1091 | ||
1092 | ret = regulator_disable(priv->core_pwr); | |
1093 | if (ret < 0) | |
1094 | dev_err(priv->dev, | |
1095 | "Failed to disable core power: %d\n", ret); | |
1096 | ||
1097 | ret = regulator_disable(priv->io_pwr); | |
1098 | if (ret < 0) | |
1099 | dev_err(priv->dev, "Failed to disable io pwr: %d\n", | |
1100 | ret); | |
1101 | ||
1102 | dsa_unregister_switch(priv->ds); | |
1103 | mutex_destroy(&priv->reg_mutex); | |
1104 | } | |
1105 | ||
1106 | static const struct of_device_id mt7530_of_match[] = { | |
1107 | { .compatible = "mediatek,mt7530" }, | |
1108 | { /* sentinel */ }, | |
1109 | }; | |
1110 | ||
1111 | static struct mdio_driver mt7530_mdio_driver = { | |
1112 | .probe = mt7530_probe, | |
1113 | .remove = mt7530_remove, | |
1114 | .mdiodrv.driver = { | |
1115 | .name = "mt7530", | |
1116 | .of_match_table = mt7530_of_match, | |
1117 | }, | |
1118 | }; | |
1119 | ||
1120 | mdio_module_driver(mt7530_mdio_driver); | |
1121 | ||
1122 | MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); | |
1123 | MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); | |
1124 | MODULE_LICENSE("GPL"); | |
1125 | MODULE_ALIAS("platform:mediatek-mt7530"); |