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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mt7530.c
CommitLineData
b8f126a8
SW		 1/*
2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/etherdevice.h>
15#include <linux/if_bridge.h>
16#include <linux/iopoll.h>
17#include <linux/mdio.h>
18#include <linux/mfd/syscon.h>
19#include <linux/module.h>
20#include <linux/netdevice.h>
21#include <linux/of_gpio.h>
22#include <linux/of_mdio.h>
23#include <linux/of_net.h>
24#include <linux/of_platform.h>
25#include <linux/phy.h>
26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28#include <linux/reset.h>
eb976a55 29#include <linux/gpio/consumer.h>
b8f126a8 30#include <net/dsa.h>
b8f126a8
SW		 31
32#include "mt7530.h"
33
34/* String, offset, and register size in bytes if different from 4 bytes */
35static const struct mt7530_mib_desc mt7530_mib[] = {
36 MIB_DESC(1, 0x00, "TxDrop"),
37 MIB_DESC(1, 0x04, "TxCrcErr"),
38 MIB_DESC(1, 0x08, "TxUnicast"),
39 MIB_DESC(1, 0x0c, "TxMulticast"),
40 MIB_DESC(1, 0x10, "TxBroadcast"),
41 MIB_DESC(1, 0x14, "TxCollision"),
42 MIB_DESC(1, 0x18, "TxSingleCollision"),
43 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
44 MIB_DESC(1, 0x20, "TxDeferred"),
45 MIB_DESC(1, 0x24, "TxLateCollision"),
46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
47 MIB_DESC(1, 0x2c, "TxPause"),
48 MIB_DESC(1, 0x30, "TxPktSz64"),
49 MIB_DESC(1, 0x34, "TxPktSz65To127"),
50 MIB_DESC(1, 0x38, "TxPktSz128To255"),
51 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
52 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
53 MIB_DESC(1, 0x44, "Tx1024ToMax"),
54 MIB_DESC(2, 0x48, "TxBytes"),
55 MIB_DESC(1, 0x60, "RxDrop"),
56 MIB_DESC(1, 0x64, "RxFiltering"),
57 MIB_DESC(1, 0x6c, "RxMulticast"),
58 MIB_DESC(1, 0x70, "RxBroadcast"),
59 MIB_DESC(1, 0x74, "RxAlignErr"),
60 MIB_DESC(1, 0x78, "RxCrcErr"),
61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
62 MIB_DESC(1, 0x80, "RxFragErr"),
63 MIB_DESC(1, 0x84, "RxOverSzErr"),
64 MIB_DESC(1, 0x88, "RxJabberErr"),
65 MIB_DESC(1, 0x8c, "RxPause"),
66 MIB_DESC(1, 0x90, "RxPktSz64"),
67 MIB_DESC(1, 0x94, "RxPktSz65To127"),
68 MIB_DESC(1, 0x98, "RxPktSz128To255"),
69 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
72 MIB_DESC(2, 0xa8, "RxBytes"),
73 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
74 MIB_DESC(1, 0xb4, "RxIngressDrop"),
75 MIB_DESC(1, 0xb8, "RxArlDrop"),
76};
77
78static int
79mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
80{
81 int ret;
82
83 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
84 if (ret < 0)
85 dev_err(priv->dev,
86 "failed to priv write register\n");
87 return ret;
88}
89
90static u32
91mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
92{
93 int ret;
94 u32 val;
95
96 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
97 if (ret < 0) {
98 dev_err(priv->dev,
99 "failed to priv read register\n");
100 return ret;
101 }
102
103 return val;
104}
105
106static void
107mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
108 u32 mask, u32 set)
109{
110 u32 val;
111
112 val = mt7623_trgmii_read(priv, reg);
113 val &= ~mask;
114 val |= set;
115 mt7623_trgmii_write(priv, reg, val);
116}
117
118static void
119mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
120{
121 mt7623_trgmii_rmw(priv, reg, 0, val);
122}
123
124static void
125mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
126{
127 mt7623_trgmii_rmw(priv, reg, val, 0);
128}
129
130static int
131core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
132{
133 struct mii_bus *bus = priv->bus;
134 int value, ret;
135
136 /* Write the desired MMD Devad */
137 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
138 if (ret < 0)
139 goto err;
140
141 /* Write the desired MMD register address */
142 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
143 if (ret < 0)
144 goto err;
145
146 /* Select the Function : DATA with no post increment */
147 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
148 if (ret < 0)
149 goto err;
150
151 /* Read the content of the MMD's selected register */
152 value = bus->read(bus, 0, MII_MMD_DATA);
153
154 return value;
155err:
156 dev_err(&bus->dev, "failed to read mmd register\n");
157
158 return ret;
159}
160
161static int
162core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
163 int devad, u32 data)
164{
165 struct mii_bus *bus = priv->bus;
166 int ret;
167
168 /* Write the desired MMD Devad */
169 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
170 if (ret < 0)
171 goto err;
172
173 /* Write the desired MMD register address */
174 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
175 if (ret < 0)
176 goto err;
177
178 /* Select the Function : DATA with no post increment */
179 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
180 if (ret < 0)
181 goto err;
182
183 /* Write the data into MMD's selected register */
184 ret = bus->write(bus, 0, MII_MMD_DATA, data);
185err:
186 if (ret < 0)
187 dev_err(&bus->dev,
188 "failed to write mmd register\n");
189 return ret;
190}
191
192static void
193core_write(struct mt7530_priv *priv, u32 reg, u32 val)
194{
195 struct mii_bus *bus = priv->bus;
196
197 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
198
199 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
200
201 mutex_unlock(&bus->mdio_lock);
202}
203
204static void
205core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
206{
207 struct mii_bus *bus = priv->bus;
208 u32 val;
209
210 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
211
212 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
213 val &= ~mask;
214 val |= set;
215 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
216
217 mutex_unlock(&bus->mdio_lock);
218}
219
220static void
221core_set(struct mt7530_priv *priv, u32 reg, u32 val)
222{
223 core_rmw(priv, reg, 0, val);
224}
225
226static void
227core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
228{
229 core_rmw(priv, reg, val, 0);
230}
231
232static int
233mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
234{
235 struct mii_bus *bus = priv->bus;
236 u16 page, r, lo, hi;
237 int ret;
238
239 page = (reg >> 6) & 0x3ff;
240 r = (reg >> 2) & 0xf;
241 lo = val & 0xffff;
242 hi = val >> 16;
243
244 /* MT7530 uses 31 as the pseudo port */
245 ret = bus->write(bus, 0x1f, 0x1f, page);
246 if (ret < 0)
247 goto err;
248
249 ret = bus->write(bus, 0x1f, r, lo);
250 if (ret < 0)
251 goto err;
252
253 ret = bus->write(bus, 0x1f, 0x10, hi);
254err:
255 if (ret < 0)
256 dev_err(&bus->dev,
257 "failed to write mt7530 register\n");
258 return ret;
259}
260
261static u32
262mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
263{
264 struct mii_bus *bus = priv->bus;
265 u16 page, r, lo, hi;
266 int ret;
267
268 page = (reg >> 6) & 0x3ff;
269 r = (reg >> 2) & 0xf;
270
271 /* MT7530 uses 31 as the pseudo port */
272 ret = bus->write(bus, 0x1f, 0x1f, page);
273 if (ret < 0) {
274 dev_err(&bus->dev,
275 "failed to read mt7530 register\n");
276 return ret;
277 }
278
279 lo = bus->read(bus, 0x1f, r);
280 hi = bus->read(bus, 0x1f, 0x10);
281
282 return (hi << 16) | (lo & 0xffff);
283}
284
285static void
286mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
287{
288 struct mii_bus *bus = priv->bus;
289
290 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
291
292 mt7530_mii_write(priv, reg, val);
293
294 mutex_unlock(&bus->mdio_lock);
295}
296
297static u32
298_mt7530_read(struct mt7530_dummy_poll *p)
299{
300 struct mii_bus *bus = p->priv->bus;
301 u32 val;
302
303 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
304
305 val = mt7530_mii_read(p->priv, p->reg);
306
307 mutex_unlock(&bus->mdio_lock);
308
309 return val;
310}
311
312static u32
313mt7530_read(struct mt7530_priv *priv, u32 reg)
314{
315 struct mt7530_dummy_poll p;
316
317 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
318 return _mt7530_read(&p);
319}
320
321static void
322mt7530_rmw(struct mt7530_priv *priv, u32 reg,
323 u32 mask, u32 set)
324{
325 struct mii_bus *bus = priv->bus;
326 u32 val;
327
328 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
329
330 val = mt7530_mii_read(priv, reg);
331 val &= ~mask;
332 val |= set;
333 mt7530_mii_write(priv, reg, val);
334
335 mutex_unlock(&bus->mdio_lock);
336}
337
338static void
339mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
340{
341 mt7530_rmw(priv, reg, 0, val);
342}
343
344static void
345mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
346{
347 mt7530_rmw(priv, reg, val, 0);
348}
349
350static int
351mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
352{
353 u32 val;
354 int ret;
355 struct mt7530_dummy_poll p;
356
357 /* Set the command operating upon the MAC address entries */
358 val = ATC_BUSY | ATC_MAT(0) | cmd;
359 mt7530_write(priv, MT7530_ATC, val);
360
361 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
362 ret = readx_poll_timeout(_mt7530_read, &p, val,
363 !(val & ATC_BUSY), 20, 20000);
364 if (ret < 0) {
365 dev_err(priv->dev, "reset timeout\n");
366 return ret;
367 }
368
369 /* Additional sanity for read command if the specified
370 * entry is invalid
371 */
372 val = mt7530_read(priv, MT7530_ATC);
373 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
374 return -EINVAL;
375
376 if (rsp)
377 *rsp = val;
378
379 return 0;
380}
381
382static void
383mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
384{
385 u32 reg[3];
386 int i;
387
388 /* Read from ARL table into an array */
389 for (i = 0; i < 3; i++) {
390 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
391
392 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
393 __func__, __LINE__, i, reg[i]);
394 }
395
396 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
397 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
398 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
399 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
400 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
401 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
402 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
403 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
404 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
405 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
406}
407
408static void
409mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
410 u8 port_mask, const u8 *mac,
411 u8 aging, u8 type)
412{
413 u32 reg[3] = { 0 };
414 int i;
415
416 reg[1] |= vid & CVID_MASK;
417 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
418 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
419 /* STATIC_ENT indicate that entry is static wouldn't
420 * be aged out and STATIC_EMP specified as erasing an
421 * entry
422 */
423 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
424 reg[1] |= mac[5] << MAC_BYTE_5;
425 reg[1] |= mac[4] << MAC_BYTE_4;
426 reg[0] |= mac[3] << MAC_BYTE_3;
427 reg[0] |= mac[2] << MAC_BYTE_2;
428 reg[0] |= mac[1] << MAC_BYTE_1;
429 reg[0] |= mac[0] << MAC_BYTE_0;
430
431 /* Write array into the ARL table */
432 for (i = 0; i < 3; i++)
433 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
434}
435
436static int
437mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
438{
439 struct mt7530_priv *priv = ds->priv;
440 u32 ncpo1, ssc_delta, trgint, i;
441
442 switch (mode) {
443 case PHY_INTERFACE_MODE_RGMII:
444 trgint = 0;
445 ncpo1 = 0x0c80;
446 ssc_delta = 0x87;
447 break;
448 case PHY_INTERFACE_MODE_TRGMII:
449 trgint = 1;
450 ncpo1 = 0x1400;
451 ssc_delta = 0x57;
452 break;
453 default:
454 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
455 return -EINVAL;
456 }
457
458 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
459 P6_INTF_MODE(trgint));
460
461 /* Lower Tx Driving for TRGMII path */
462 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
463 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
464 TD_DM_DRVP(8) | TD_DM_DRVN(8));
465
466 /* Setup core clock for MT7530 */
467 if (!trgint) {
468 /* Disable MT7530 core clock */
469 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
470
471 /* Disable PLL, since phy_device has not yet been created
472 * provided for phy_[read,write]_mmd_indirect is called, we
473 * provide our own core_write_mmd_indirect to complete this
474 * function.
475 */
476 core_write_mmd_indirect(priv,
477 CORE_GSWPLL_GRP1,
478 MDIO_MMD_VEND2,
479 0);
480
481 /* Set core clock into 500Mhz */
482 core_write(priv, CORE_GSWPLL_GRP2,
483 RG_GSWPLL_POSDIV_500M(1) |
484 RG_GSWPLL_FBKDIV_500M(25));
485
486 /* Enable PLL */
487 core_write(priv, CORE_GSWPLL_GRP1,
488 RG_GSWPLL_EN_PRE |
489 RG_GSWPLL_POSDIV_200M(2) |
490 RG_GSWPLL_FBKDIV_200M(32));
491
492 /* Enable MT7530 core clock */
493 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
494 }
495
496 /* Setup the MT7530 TRGMII Tx Clock */
497 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
498 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
499 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
500 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
501 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
502 core_write(priv, CORE_PLL_GROUP4,
503 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
504 RG_SYSPLL_BIAS_LPF_EN);
505 core_write(priv, CORE_PLL_GROUP2,
506 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
507 RG_SYSPLL_POSDIV(1));
508 core_write(priv, CORE_PLL_GROUP7,
509 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
510 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
511 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
512 REG_GSWCK_EN | REG_TRGMIICK_EN);
513
514 if (!trgint)
515 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
516 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
517 RD_TAP_MASK, RD_TAP(16));
518 else
519 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
520
521 return 0;
522}
523
524static int
525mt7623_pad_clk_setup(struct dsa_switch *ds)
526{
527 struct mt7530_priv *priv = ds->priv;
528 int i;
529
530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
531 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
532 TD_DM_DRVP(8) | TD_DM_DRVN(8));
533
534 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
535 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
536
537 return 0;
538}
539
540static void
541mt7530_mib_reset(struct dsa_switch *ds)
542{
543 struct mt7530_priv *priv = ds->priv;
544
545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
547}
548
549static void
550mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
551{
552 u32 mask = PMCR_TX_EN | PMCR_RX_EN;
553
554 if (enable)
555 mt7530_set(priv, MT7530_PMCR_P(port), mask);
556 else
557 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
558}
559
560static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
561{
562 struct mt7530_priv *priv = ds->priv;
563
564 return mdiobus_read_nested(priv->bus, port, regnum);
565}
566
567int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
568{
569 struct mt7530_priv *priv = ds->priv;
570
571 return mdiobus_write_nested(priv->bus, port, regnum, val);
572}
573
574static void
575mt7530_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
576{
577 int i;
578
579 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
580 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
581 ETH_GSTRING_LEN);
582}
583
584static void
585mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
586 uint64_t *data)
587{
588 struct mt7530_priv *priv = ds->priv;
589 const struct mt7530_mib_desc *mib;
590 u32 reg, i;
591 u64 hi;
592
593 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
594 mib = &mt7530_mib[i];
595 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
596
597 data[i] = mt7530_read(priv, reg);
598 if (mib->size == 2) {
599 hi = mt7530_read(priv, reg + 4);
600 data[i] |= hi << 32;
601 }
602 }
603}
604
605static int
606mt7530_get_sset_count(struct dsa_switch *ds)
607{
608 return ARRAY_SIZE(mt7530_mib);
609}
610
611static void mt7530_adjust_link(struct dsa_switch *ds, int port,
612 struct phy_device *phydev)
613{
614 struct mt7530_priv *priv = ds->priv;
615
616 if (phy_is_pseudo_fixed_link(phydev)) {
617 dev_dbg(priv->dev, "phy-mode for master device = %x\n",
618 phydev->interface);
619
620 /* Setup TX circuit incluing relevant PAD and driving */
621 mt7530_pad_clk_setup(ds, phydev->interface);
622
623 /* Setup RX circuit, relevant PAD and driving on the host
624 * which must be placed after the setup on the device side is
625 * all finished.
626 */
627 mt7623_pad_clk_setup(ds);
8e6f1521
JC		 628 } else {
629 u16 lcl_adv = 0, rmt_adv = 0;
630 u8 flowctrl;
631 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
632
633 switch (phydev->speed) {
634 case SPEED_1000:
635 mcr |= PMCR_FORCE_SPEED_1000;
636 break;
637 case SPEED_100:
638 mcr |= PMCR_FORCE_SPEED_100;
639 break;
640 };
641
642 if (phydev->link)
643 mcr |= PMCR_FORCE_LNK;
644
645 if (phydev->duplex) {
646 mcr |= PMCR_FORCE_FDX;
647
648 if (phydev->pause)
649 rmt_adv = LPA_PAUSE_CAP;
650 if (phydev->asym_pause)
651 rmt_adv |= LPA_PAUSE_ASYM;
652
653 if (phydev->advertising & ADVERTISED_Pause)
654 lcl_adv |= ADVERTISE_PAUSE_CAP;
655 if (phydev->advertising & ADVERTISED_Asym_Pause)
656 lcl_adv |= ADVERTISE_PAUSE_ASYM;
657
658 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
659
660 if (flowctrl & FLOW_CTRL_TX)
661 mcr |= PMCR_TX_FC_EN;
662 if (flowctrl & FLOW_CTRL_RX)
663 mcr |= PMCR_RX_FC_EN;
664 }
665 mt7530_write(priv, MT7530_PMCR_P(port), mcr);
b8f126a8
SW		 666 }
667}
668
669static int
670mt7530_cpu_port_enable(struct mt7530_priv *priv,
671 int port)
672{
673 /* Enable Mediatek header mode on the cpu port */
674 mt7530_write(priv, MT7530_PVC_P(port),
675 PORT_SPEC_TAG);
676
677 /* Setup the MAC by default for the cpu port */
678 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
679
680 /* Disable auto learning on the cpu port */
681 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
682
683 /* Unknown unicast frame fordwarding to the cpu port */
684 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
685
686 /* CPU port gets connected to all user ports of
687 * the switch
688 */
689 mt7530_write(priv, MT7530_PCR_P(port),
690 PCR_MATRIX(priv->ds->enabled_port_mask));
691
692 return 0;
693}
694
695static int
696mt7530_port_enable(struct dsa_switch *ds, int port,
697 struct phy_device *phy)
698{
699 struct mt7530_priv *priv = ds->priv;
700
701 mutex_lock(&priv->reg_mutex);
702
703 /* Setup the MAC for the user port */
704 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
705
706 /* Allow the user port gets connected to the cpu port and also
707 * restore the port matrix if the port is the member of a certain
708 * bridge.
709 */
710 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
711 priv->ports[port].enable = true;
712 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
713 priv->ports[port].pm);
714 mt7530_port_set_status(priv, port, 1);
715
716 mutex_unlock(&priv->reg_mutex);
717
718 return 0;
719}
720
721static void
722mt7530_port_disable(struct dsa_switch *ds, int port,
723 struct phy_device *phy)
724{
725 struct mt7530_priv *priv = ds->priv;
726
727 mutex_lock(&priv->reg_mutex);
728
729 /* Clear up all port matrix which could be restored in the next
730 * enablement for the port.
731 */
732 priv->ports[port].enable = false;
733 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
734 PCR_MATRIX_CLR);
735 mt7530_port_set_status(priv, port, 0);
736
737 mutex_unlock(&priv->reg_mutex);
738}
739
740static void
741mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
742{
743 struct mt7530_priv *priv = ds->priv;
744 u32 stp_state;
745
746 switch (state) {
747 case BR_STATE_DISABLED:
748 stp_state = MT7530_STP_DISABLED;
749 break;
750 case BR_STATE_BLOCKING:
751 stp_state = MT7530_STP_BLOCKING;
752 break;
753 case BR_STATE_LISTENING:
754 stp_state = MT7530_STP_LISTENING;
755 break;
756 case BR_STATE_LEARNING:
757 stp_state = MT7530_STP_LEARNING;
758 break;
759 case BR_STATE_FORWARDING:
760 default:
761 stp_state = MT7530_STP_FORWARDING;
762 break;
763 }
764
765 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
766}
767
768static int
769mt7530_port_bridge_join(struct dsa_switch *ds, int port,
770 struct net_device *bridge)
771{
772 struct mt7530_priv *priv = ds->priv;
773 u32 port_bitmap = BIT(MT7530_CPU_PORT);
774 int i;
775
776 mutex_lock(&priv->reg_mutex);
777
778 for (i = 0; i < MT7530_NUM_PORTS; i++) {
779 /* Add this port to the port matrix of the other ports in the
780 * same bridge. If the port is disabled, port matrix is kept
781 * and not being setup until the port becomes enabled.
782 */
783 if (ds->enabled_port_mask & BIT(i) && i != port) {
784 if (ds->ports[i].bridge_dev != bridge)
785 continue;
786 if (priv->ports[i].enable)
787 mt7530_set(priv, MT7530_PCR_P(i),
788 PCR_MATRIX(BIT(port)));
789 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
790
791 port_bitmap |= BIT(i);
792 }
793 }
794
795 /* Add the all other ports to this port matrix. */
796 if (priv->ports[port].enable)
797 mt7530_rmw(priv, MT7530_PCR_P(port),
798 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
799 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
800
801 mutex_unlock(&priv->reg_mutex);
802
803 return 0;
804}
805
806static void
807mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
808 struct net_device *bridge)
809{
810 struct mt7530_priv *priv = ds->priv;
811 int i;
812
813 mutex_lock(&priv->reg_mutex);
814
815 for (i = 0; i < MT7530_NUM_PORTS; i++) {
816 /* Remove this port from the port matrix of the other ports
817 * in the same bridge. If the port is disabled, port matrix
818 * is kept and not being setup until the port becomes enabled.
819 */
820 if (ds->enabled_port_mask & BIT(i) && i != port) {
821 if (ds->ports[i].bridge_dev != bridge)
822 continue;
823 if (priv->ports[i].enable)
824 mt7530_clear(priv, MT7530_PCR_P(i),
825 PCR_MATRIX(BIT(port)));
826 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
827 }
828 }
829
830 /* Set the cpu port to be the only one in the port matrix of
831 * this port.
832 */
833 if (priv->ports[port].enable)
834 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
835 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
836 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
837
838 mutex_unlock(&priv->reg_mutex);
839}
840
841static int
842mt7530_port_fdb_prepare(struct dsa_switch *ds, int port,
843 const struct switchdev_obj_port_fdb *fdb,
844 struct switchdev_trans *trans)
845{
846 struct mt7530_priv *priv = ds->priv;
847 int ret;
848
849 /* Because auto-learned entrie shares the same FDB table.
850 * an entry is reserved with no port_mask to make sure fdb_add
851 * is called while the entry is still available.
852 */
853 mutex_lock(&priv->reg_mutex);
854 mt7530_fdb_write(priv, fdb->vid, 0, fdb->addr, -1, STATIC_ENT);
855 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
856 mutex_unlock(&priv->reg_mutex);
857
858 return ret;
859}
860
861static void
862mt7530_port_fdb_add(struct dsa_switch *ds, int port,
863 const struct switchdev_obj_port_fdb *fdb,
864 struct switchdev_trans *trans)
865{
866 struct mt7530_priv *priv = ds->priv;
867 u8 port_mask = BIT(port);
868
869 mutex_lock(&priv->reg_mutex);
870 mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_ENT);
871 mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
872 mutex_unlock(&priv->reg_mutex);
873}
874
875static int
876mt7530_port_fdb_del(struct dsa_switch *ds, int port,
877 const struct switchdev_obj_port_fdb *fdb)
878{
879 struct mt7530_priv *priv = ds->priv;
880 int ret;
881 u8 port_mask = BIT(port);
882
883 mutex_lock(&priv->reg_mutex);
884 mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_EMP);
885 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
886 mutex_unlock(&priv->reg_mutex);
887
888 return ret;
889}
890
891static int
892mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
893 struct switchdev_obj_port_fdb *fdb,
438ff537 894 switchdev_obj_dump_cb_t *cb)
b8f126a8
SW		 895{
896 struct mt7530_priv *priv = ds->priv;
897 struct mt7530_fdb _fdb = { 0 };
898 int cnt = MT7530_NUM_FDB_RECORDS;
899 int ret = 0;
900 u32 rsp = 0;
901
902 mutex_lock(&priv->reg_mutex);
903
904 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
905 if (ret < 0)
906 goto err;
907
908 do {
909 if (rsp & ATC_SRCH_HIT) {
910 mt7530_fdb_read(priv, &_fdb);
911 if (_fdb.port_mask & BIT(port)) {
912 ether_addr_copy(fdb->addr, _fdb.mac);
913 fdb->vid = _fdb.vid;
914 fdb->ndm_state = _fdb.noarp ?
915 NUD_NOARP : NUD_REACHABLE;
916 ret = cb(&fdb->obj);
917 if (ret < 0)
918 break;
919 }
920 }
921 } while (--cnt &&
922 !(rsp & ATC_SRCH_END) &&
923 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
924err:
925 mutex_unlock(&priv->reg_mutex);
926
927 return 0;
928}
929
930static enum dsa_tag_protocol
931mtk_get_tag_protocol(struct dsa_switch *ds)
932{
933 struct mt7530_priv *priv = ds->priv;
934
935 if (!dsa_is_cpu_port(ds, MT7530_CPU_PORT)) {
936 dev_warn(priv->dev,
937 "port not matched with tagging CPU port\n");
938 return DSA_TAG_PROTO_NONE;
939 } else {
940 return DSA_TAG_PROTO_MTK;
941 }
942}
943
944static int
945mt7530_setup(struct dsa_switch *ds)
946{
947 struct mt7530_priv *priv = ds->priv;
948 int ret, i;
949 u32 id, val;
950 struct device_node *dn;
951 struct mt7530_dummy_poll p;
952
6d3c8c0d 953 /* The parent node of cpu_dp->netdev which holds the common system
b8f126a8
SW		 954 * controller also is the container for two GMACs nodes representing
955 * as two netdev instances.
956 */
6d3c8c0d 957 dn = ds->dst->cpu_dp->netdev->dev.of_node->parent;
b8f126a8
SW		 958 priv->ethernet = syscon_node_to_regmap(dn);
959 if (IS_ERR(priv->ethernet))
960 return PTR_ERR(priv->ethernet);
961
962 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
963 ret = regulator_enable(priv->core_pwr);
964 if (ret < 0) {
965 dev_err(priv->dev,
966 "Failed to enable core power: %d\n", ret);
967 return ret;
968 }
969
970 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
971 ret = regulator_enable(priv->io_pwr);
972 if (ret < 0) {
973 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
974 ret);
975 return ret;
976 }
977
978 /* Reset whole chip through gpio pin or memory-mapped registers for
979 * different type of hardware
980 */
981 if (priv->mcm) {
982 reset_control_assert(priv->rstc);
983 usleep_range(1000, 1100);
984 reset_control_deassert(priv->rstc);
985 } else {
986 gpiod_set_value_cansleep(priv->reset, 0);
987 usleep_range(1000, 1100);
988 gpiod_set_value_cansleep(priv->reset, 1);
989 }
990
991 /* Waiting for MT7530 got to stable */
992 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
993 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
994 20, 1000000);
995 if (ret < 0) {
996 dev_err(priv->dev, "reset timeout\n");
997 return ret;
998 }
999
1000 id = mt7530_read(priv, MT7530_CREV);
1001 id >>= CHIP_NAME_SHIFT;
1002 if (id != MT7530_ID) {
1003 dev_err(priv->dev, "chip %x can't be supported\n", id);
1004 return -ENODEV;
1005 }
1006
1007 /* Reset the switch through internal reset */
1008 mt7530_write(priv, MT7530_SYS_CTRL,
1009 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1010 SYS_CTRL_REG_RST);
1011
1012 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1013 val = mt7530_read(priv, MT7530_MHWTRAP);
1014 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1015 val |= MHWTRAP_MANUAL;
1016 mt7530_write(priv, MT7530_MHWTRAP, val);
1017
1018 /* Enable and reset MIB counters */
1019 mt7530_mib_reset(ds);
1020
1021 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
1022
1023 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1024 /* Disable forwarding by default on all ports */
1025 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1026 PCR_MATRIX_CLR);
1027
1028 if (dsa_is_cpu_port(ds, i))
1029 mt7530_cpu_port_enable(priv, i);
1030 else
1031 mt7530_port_disable(ds, i, NULL);
1032 }
1033
1034 /* Flush the FDB table */
1035 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, 0);
1036 if (ret < 0)
1037 return ret;
1038
1039 return 0;
1040}
1041
1042static struct dsa_switch_ops mt7530_switch_ops = {
1043 .get_tag_protocol = mtk_get_tag_protocol,
1044 .setup = mt7530_setup,
1045 .get_strings = mt7530_get_strings,
1046 .phy_read = mt7530_phy_read,
1047 .phy_write = mt7530_phy_write,
1048 .get_ethtool_stats = mt7530_get_ethtool_stats,
1049 .get_sset_count = mt7530_get_sset_count,
1050 .adjust_link = mt7530_adjust_link,
1051 .port_enable = mt7530_port_enable,
1052 .port_disable = mt7530_port_disable,
1053 .port_stp_state_set = mt7530_stp_state_set,
1054 .port_bridge_join = mt7530_port_bridge_join,
1055 .port_bridge_leave = mt7530_port_bridge_leave,
1056 .port_fdb_prepare = mt7530_port_fdb_prepare,
1057 .port_fdb_add = mt7530_port_fdb_add,
1058 .port_fdb_del = mt7530_port_fdb_del,
1059 .port_fdb_dump = mt7530_port_fdb_dump,
1060};
1061
1062static int
1063mt7530_probe(struct mdio_device *mdiodev)
1064{
1065 struct mt7530_priv *priv;
1066 struct device_node *dn;
1067
1068 dn = mdiodev->dev.of_node;
1069
1070 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1071 if (!priv)
1072 return -ENOMEM;
1073
1074 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1075 if (!priv->ds)
1076 return -ENOMEM;
1077
1078 /* Use medatek,mcm property to distinguish hardware type that would
1079 * casues a little bit differences on power-on sequence.
1080 */
1081 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1082 if (priv->mcm) {
1083 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1084
1085 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1086 if (IS_ERR(priv->rstc)) {
1087 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1088 return PTR_ERR(priv->rstc);
1089 }
1090 }
1091
1092 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1093 if (IS_ERR(priv->core_pwr))
1094 return PTR_ERR(priv->core_pwr);
1095
1096 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1097 if (IS_ERR(priv->io_pwr))
1098 return PTR_ERR(priv->io_pwr);
1099
1100 /* Not MCM that indicates switch works as the remote standalone
1101 * integrated circuit so the GPIO pin would be used to complete
1102 * the reset, otherwise memory-mapped register accessing used
1103 * through syscon provides in the case of MCM.
1104 */
1105 if (!priv->mcm) {
1106 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1107 GPIOD_OUT_LOW);
1108 if (IS_ERR(priv->reset)) {
1109 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1110 return PTR_ERR(priv->reset);
1111 }
1112 }
1113
1114 priv->bus = mdiodev->bus;
1115 priv->dev = &mdiodev->dev;
1116 priv->ds->priv = priv;
1117 priv->ds->ops = &mt7530_switch_ops;
1118 mutex_init(&priv->reg_mutex);
1119 dev_set_drvdata(&mdiodev->dev, priv);
1120
23c9ee49 1121 return dsa_register_switch(priv->ds);
b8f126a8
SW		 1122}
1123
1124static void
1125mt7530_remove(struct mdio_device *mdiodev)
1126{
1127 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1128 int ret = 0;
1129
1130 ret = regulator_disable(priv->core_pwr);
1131 if (ret < 0)
1132 dev_err(priv->dev,
1133 "Failed to disable core power: %d\n", ret);
1134
1135 ret = regulator_disable(priv->io_pwr);
1136 if (ret < 0)
1137 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1138 ret);
1139
1140 dsa_unregister_switch(priv->ds);
1141 mutex_destroy(&priv->reg_mutex);
1142}
1143
1144static const struct of_device_id mt7530_of_match[] = {
1145 { .compatible = "mediatek,mt7530" },
1146 { /* sentinel */ },
1147};
1148
1149static struct mdio_driver mt7530_mdio_driver = {
1150 .probe = mt7530_probe,
1151 .remove = mt7530_remove,
1152 .mdiodrv.driver = {
1153 .name = "mt7530",
1154 .of_match_table = mt7530_of_match,
1155 },
1156};
1157
1158mdio_module_driver(mt7530_mdio_driver);
1159
1160MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1161MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1162MODULE_LICENSE("GPL");
1163MODULE_ALIAS("platform:mediatek-mt7530");
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