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406a4362 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2e16a77e LB |
2 | /* |
3 | * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips | |
e84665c9 | 4 | * Copyright (c) 2008-2009 Marvell Semiconductor |
2e16a77e LB |
5 | */ |
6 | ||
19b2f97e | 7 | #include <linux/delay.h> |
56c3ff9b | 8 | #include <linux/etherdevice.h> |
19b2f97e | 9 | #include <linux/jiffies.h> |
2e16a77e | 10 | #include <linux/list.h> |
2bbba277 | 11 | #include <linux/module.h> |
2e16a77e LB |
12 | #include <linux/netdevice.h> |
13 | #include <linux/phy.h> | |
c8f0b869 | 14 | #include <net/dsa.h> |
6a4b2980 | 15 | #include "mv88e6060.h" |
2e16a77e | 16 | |
3e8bc1b8 | 17 | static int reg_read(struct mv88e6060_priv *priv, int addr, int reg) |
2e16a77e | 18 | { |
a77d43f1 | 19 | return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg); |
2e16a77e LB |
20 | } |
21 | ||
3e8bc1b8 | 22 | static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val) |
2e16a77e | 23 | { |
a77d43f1 | 24 | return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val); |
2e16a77e LB |
25 | } |
26 | ||
0209d144 | 27 | static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr) |
2e16a77e LB |
28 | { |
29 | int ret; | |
30 | ||
6a4b2980 | 31 | ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID); |
2e16a77e | 32 | if (ret >= 0) { |
6a4b2980 | 33 | if (ret == PORT_SWITCH_ID_6060) |
3de6aa4c | 34 | return "Marvell 88E6060 (A0)"; |
6a4b2980 NA |
35 | if (ret == PORT_SWITCH_ID_6060_R1 || |
36 | ret == PORT_SWITCH_ID_6060_R2) | |
3de6aa4c | 37 | return "Marvell 88E6060 (B0)"; |
6a4b2980 | 38 | if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060) |
2e16a77e LB |
39 | return "Marvell 88E6060"; |
40 | } | |
41 | ||
42 | return NULL; | |
43 | } | |
44 | ||
5ed4e3eb | 45 | static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds, |
4d776482 FF |
46 | int port, |
47 | enum dsa_tag_protocol m) | |
7b314362 AL |
48 | { |
49 | return DSA_TAG_PROTO_TRAILER; | |
50 | } | |
51 | ||
3e8bc1b8 | 52 | static int mv88e6060_switch_reset(struct mv88e6060_priv *priv) |
2e16a77e LB |
53 | { |
54 | int i; | |
55 | int ret; | |
19b2f97e | 56 | unsigned long timeout; |
2e16a77e | 57 | |
3675c8d7 | 58 | /* Set all ports to the disabled state. */ |
6a4b2980 | 59 | for (i = 0; i < MV88E6060_PORTS; i++) { |
1ba22bf5 AL |
60 | ret = reg_read(priv, REG_PORT(i), PORT_CONTROL); |
61 | if (ret < 0) | |
62 | return ret; | |
c4362c37 AL |
63 | ret = reg_write(priv, REG_PORT(i), PORT_CONTROL, |
64 | ret & ~PORT_CONTROL_STATE_MASK); | |
65 | if (ret) | |
66 | return ret; | |
2e16a77e LB |
67 | } |
68 | ||
3675c8d7 | 69 | /* Wait for transmit queues to drain. */ |
19b2f97e | 70 | usleep_range(2000, 4000); |
2e16a77e | 71 | |
3675c8d7 | 72 | /* Reset the switch. */ |
c4362c37 AL |
73 | ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
74 | GLOBAL_ATU_CONTROL_SWRESET | | |
75 | GLOBAL_ATU_CONTROL_LEARNDIS); | |
76 | if (ret) | |
77 | return ret; | |
2e16a77e | 78 | |
3675c8d7 | 79 | /* Wait up to one second for reset to complete. */ |
19b2f97e BG |
80 | timeout = jiffies + 1 * HZ; |
81 | while (time_before(jiffies, timeout)) { | |
1ba22bf5 AL |
82 | ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS); |
83 | if (ret < 0) | |
84 | return ret; | |
85 | ||
6a4b2980 | 86 | if (ret & GLOBAL_STATUS_INIT_READY) |
2e16a77e LB |
87 | break; |
88 | ||
19b2f97e | 89 | usleep_range(1000, 2000); |
2e16a77e | 90 | } |
19b2f97e | 91 | if (time_after(jiffies, timeout)) |
2e16a77e LB |
92 | return -ETIMEDOUT; |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
3e8bc1b8 | 97 | static int mv88e6060_setup_global(struct mv88e6060_priv *priv) |
2e16a77e | 98 | { |
c4362c37 AL |
99 | int ret; |
100 | ||
3675c8d7 | 101 | /* Disable discarding of frames with excessive collisions, |
2e16a77e LB |
102 | * set the maximum frame size to 1536 bytes, and mask all |
103 | * interrupt sources. | |
104 | */ | |
c4362c37 AL |
105 | ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL, |
106 | GLOBAL_CONTROL_MAX_FRAME_1536); | |
107 | if (ret) | |
108 | return ret; | |
2e16a77e | 109 | |
a7451560 | 110 | /* Disable automatic address learning. |
2e16a77e | 111 | */ |
c4362c37 AL |
112 | return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
113 | GLOBAL_ATU_CONTROL_LEARNDIS); | |
2e16a77e LB |
114 | } |
115 | ||
3e8bc1b8 | 116 | static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p) |
2e16a77e LB |
117 | { |
118 | int addr = REG_PORT(p); | |
c4362c37 | 119 | int ret; |
2e16a77e | 120 | |
3675c8d7 | 121 | /* Do not force flow control, disable Ingress and Egress |
2e16a77e LB |
122 | * Header tagging, disable VLAN tunneling, and set the port |
123 | * state to Forwarding. Additionally, if this is the CPU | |
124 | * port, enable Ingress and Egress Trailer tagging mode. | |
125 | */ | |
c4362c37 AL |
126 | ret = reg_write(priv, addr, PORT_CONTROL, |
127 | dsa_is_cpu_port(priv->ds, p) ? | |
6a4b2980 NA |
128 | PORT_CONTROL_TRAILER | |
129 | PORT_CONTROL_INGRESS_MODE | | |
130 | PORT_CONTROL_STATE_FORWARDING : | |
131 | PORT_CONTROL_STATE_FORWARDING); | |
c4362c37 AL |
132 | if (ret) |
133 | return ret; | |
2e16a77e | 134 | |
3675c8d7 | 135 | /* Port based VLAN map: give each port its own address |
2e16a77e LB |
136 | * database, allow the CPU port to talk to each of the 'real' |
137 | * ports, and allow each of the 'real' ports to only talk to | |
138 | * the CPU port. | |
139 | */ | |
c4362c37 AL |
140 | ret = reg_write(priv, addr, PORT_VLAN_MAP, |
141 | ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) | | |
142 | (dsa_is_cpu_port(priv->ds, p) ? | |
143 | dsa_user_ports(priv->ds) : | |
144 | BIT(dsa_to_port(priv->ds, p)->cpu_dp->index))); | |
145 | if (ret) | |
146 | return ret; | |
2e16a77e | 147 | |
3675c8d7 | 148 | /* Port Association Vector: when learning source addresses |
2e16a77e LB |
149 | * of packets, add the address to the address database using |
150 | * a port bitmap that has only the bit for this port set and | |
151 | * the other bits clear. | |
152 | */ | |
c4362c37 | 153 | return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p)); |
2e16a77e LB |
154 | } |
155 | ||
3e8bc1b8 | 156 | static int mv88e6060_setup_addr(struct mv88e6060_priv *priv) |
56c3ff9b VD |
157 | { |
158 | u8 addr[ETH_ALEN]; | |
c4362c37 | 159 | int ret; |
56c3ff9b VD |
160 | u16 val; |
161 | ||
162 | eth_random_addr(addr); | |
163 | ||
164 | val = addr[0] << 8 | addr[1]; | |
165 | ||
166 | /* The multicast bit is always transmitted as a zero, so the switch uses | |
167 | * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA. | |
168 | */ | |
169 | val &= 0xfeff; | |
170 | ||
c4362c37 AL |
171 | ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val); |
172 | if (ret) | |
173 | return ret; | |
174 | ||
175 | ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23, | |
176 | (addr[2] << 8) | addr[3]); | |
177 | if (ret) | |
178 | return ret; | |
56c3ff9b | 179 | |
c4362c37 AL |
180 | return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45, |
181 | (addr[4] << 8) | addr[5]); | |
56c3ff9b VD |
182 | } |
183 | ||
2e16a77e LB |
184 | static int mv88e6060_setup(struct dsa_switch *ds) |
185 | { | |
3e8bc1b8 | 186 | struct mv88e6060_priv *priv = ds->priv; |
2e16a77e | 187 | int ret; |
a77d43f1 | 188 | int i; |
2e16a77e | 189 | |
3e8bc1b8 AL |
190 | priv->ds = ds; |
191 | ||
192 | ret = mv88e6060_switch_reset(priv); | |
2e16a77e LB |
193 | if (ret < 0) |
194 | return ret; | |
195 | ||
196 | /* @@@ initialise atu */ | |
197 | ||
3e8bc1b8 | 198 | ret = mv88e6060_setup_global(priv); |
2e16a77e LB |
199 | if (ret < 0) |
200 | return ret; | |
201 | ||
3e8bc1b8 | 202 | ret = mv88e6060_setup_addr(priv); |
56c3ff9b VD |
203 | if (ret < 0) |
204 | return ret; | |
205 | ||
6a4b2980 | 206 | for (i = 0; i < MV88E6060_PORTS; i++) { |
3e8bc1b8 | 207 | ret = mv88e6060_setup_port(priv, i); |
2e16a77e LB |
208 | if (ret < 0) |
209 | return ret; | |
210 | } | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
2e16a77e LB |
215 | static int mv88e6060_port_to_phy_addr(int port) |
216 | { | |
6a4b2980 | 217 | if (port >= 0 && port < MV88E6060_PORTS) |
2e16a77e LB |
218 | return port; |
219 | return -1; | |
220 | } | |
221 | ||
222 | static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum) | |
223 | { | |
3e8bc1b8 | 224 | struct mv88e6060_priv *priv = ds->priv; |
2e16a77e LB |
225 | int addr; |
226 | ||
227 | addr = mv88e6060_port_to_phy_addr(port); | |
228 | if (addr == -1) | |
229 | return 0xffff; | |
230 | ||
3e8bc1b8 | 231 | return reg_read(priv, addr, regnum); |
2e16a77e LB |
232 | } |
233 | ||
234 | static int | |
235 | mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
236 | { | |
3e8bc1b8 | 237 | struct mv88e6060_priv *priv = ds->priv; |
2e16a77e LB |
238 | int addr; |
239 | ||
240 | addr = mv88e6060_port_to_phy_addr(port); | |
241 | if (addr == -1) | |
242 | return 0xffff; | |
243 | ||
3e8bc1b8 | 244 | return reg_write(priv, addr, regnum, val); |
2e16a77e LB |
245 | } |
246 | ||
a82f67af | 247 | static const struct dsa_switch_ops mv88e6060_switch_ops = { |
7b314362 | 248 | .get_tag_protocol = mv88e6060_get_tag_protocol, |
2e16a77e | 249 | .setup = mv88e6060_setup, |
2e16a77e LB |
250 | .phy_read = mv88e6060_phy_read, |
251 | .phy_write = mv88e6060_phy_write, | |
2e16a77e LB |
252 | }; |
253 | ||
27761760 AL |
254 | static int mv88e6060_probe(struct mdio_device *mdiodev) |
255 | { | |
256 | struct device *dev = &mdiodev->dev; | |
257 | struct mv88e6060_priv *priv; | |
258 | struct dsa_switch *ds; | |
259 | const char *name; | |
260 | ||
261 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
262 | if (!priv) | |
263 | return -ENOMEM; | |
264 | ||
265 | priv->bus = mdiodev->bus; | |
266 | priv->sw_addr = mdiodev->addr; | |
267 | ||
268 | name = mv88e6060_get_name(priv->bus, priv->sw_addr); | |
269 | if (!name) | |
270 | return -ENODEV; | |
271 | ||
272 | dev_info(dev, "switch %s detected\n", name); | |
273 | ||
7e99e347 | 274 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); |
27761760 AL |
275 | if (!ds) |
276 | return -ENOMEM; | |
277 | ||
7e99e347 VD |
278 | ds->dev = dev; |
279 | ds->num_ports = MV88E6060_PORTS; | |
27761760 AL |
280 | ds->priv = priv; |
281 | ds->dev = dev; | |
282 | ds->ops = &mv88e6060_switch_ops; | |
283 | ||
284 | dev_set_drvdata(dev, ds); | |
285 | ||
286 | return dsa_register_switch(ds); | |
287 | } | |
288 | ||
289 | static void mv88e6060_remove(struct mdio_device *mdiodev) | |
290 | { | |
291 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
292 | ||
293 | dsa_unregister_switch(ds); | |
294 | } | |
295 | ||
296 | static const struct of_device_id mv88e6060_of_match[] = { | |
297 | { | |
298 | .compatible = "marvell,mv88e6060", | |
299 | }, | |
300 | { /* sentinel */ }, | |
301 | }; | |
302 | ||
303 | static struct mdio_driver mv88e6060_driver = { | |
304 | .probe = mv88e6060_probe, | |
305 | .remove = mv88e6060_remove, | |
306 | .mdiodrv.driver = { | |
307 | .name = "mv88e6060", | |
308 | .of_match_table = mv88e6060_of_match, | |
309 | }, | |
310 | }; | |
311 | ||
2f8e7ece | 312 | mdio_module_driver(mv88e6060_driver); |
3d825ede BH |
313 | |
314 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
315 | MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip"); | |
316 | MODULE_LICENSE("GPL"); | |
317 | MODULE_ALIAS("platform:mv88e6060"); |