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Commit | Line | Data |
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2e5f0320 | 1 | /* |
076d3e10 LB |
2 | * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support |
3 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
2e5f0320 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
2e5f0320 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
2e5f0320 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
2e5f0320 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
3675c8d7 | 20 | /* Switch product IDs */ |
ec80bfcb PK |
21 | #define ID_6085 0x04a0 |
22 | #define ID_6095 0x0950 | |
23 | #define ID_6131 0x1060 | |
a93e464a | 24 | #define ID_6131_B2 0x1066 |
ec80bfcb | 25 | |
b4d2394d | 26 | static char *mv88e6131_probe(struct device *host_dev, int sw_addr) |
2e5f0320 | 27 | { |
b4d2394d | 28 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
2e5f0320 LB |
29 | int ret; |
30 | ||
b4d2394d AD |
31 | if (bus == NULL) |
32 | return NULL; | |
33 | ||
2e5f0320 LB |
34 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); |
35 | if (ret >= 0) { | |
a93e464a GR |
36 | int ret_masked = ret & 0xfff0; |
37 | ||
38 | if (ret_masked == ID_6085) | |
ec80bfcb | 39 | return "Marvell 88E6085"; |
a93e464a | 40 | if (ret_masked == ID_6095) |
076d3e10 | 41 | return "Marvell 88E6095/88E6095F"; |
a93e464a GR |
42 | if (ret == ID_6131_B2) |
43 | return "Marvell 88E6131 (B2)"; | |
44 | if (ret_masked == ID_6131) | |
2e5f0320 LB |
45 | return "Marvell 88E6131"; |
46 | } | |
47 | ||
48 | return NULL; | |
49 | } | |
50 | ||
51 | static int mv88e6131_switch_reset(struct dsa_switch *ds) | |
52 | { | |
53 | int i; | |
54 | int ret; | |
19b2f97e | 55 | unsigned long timeout; |
2e5f0320 | 56 | |
3675c8d7 | 57 | /* Set all ports to the disabled state. */ |
076d3e10 | 58 | for (i = 0; i < 11; i++) { |
2e5f0320 LB |
59 | ret = REG_READ(REG_PORT(i), 0x04); |
60 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | |
61 | } | |
62 | ||
3675c8d7 | 63 | /* Wait for transmit queues to drain. */ |
19b2f97e | 64 | usleep_range(2000, 4000); |
2e5f0320 | 65 | |
3675c8d7 | 66 | /* Reset the switch. */ |
2e5f0320 LB |
67 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); |
68 | ||
3675c8d7 | 69 | /* Wait up to one second for reset to complete. */ |
19b2f97e BG |
70 | timeout = jiffies + 1 * HZ; |
71 | while (time_before(jiffies, timeout)) { | |
2e5f0320 LB |
72 | ret = REG_READ(REG_GLOBAL, 0x00); |
73 | if ((ret & 0xc800) == 0xc800) | |
74 | break; | |
75 | ||
19b2f97e | 76 | usleep_range(1000, 2000); |
2e5f0320 | 77 | } |
19b2f97e | 78 | if (time_after(jiffies, timeout)) |
2e5f0320 LB |
79 | return -ETIMEDOUT; |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
84 | static int mv88e6131_setup_global(struct dsa_switch *ds) | |
85 | { | |
86 | int ret; | |
87 | int i; | |
88 | ||
3675c8d7 | 89 | /* Enable the PHY polling unit, don't discard packets with |
2e5f0320 LB |
90 | * excessive collisions, use a weighted fair queueing scheme |
91 | * to arbitrate between packet queues, set the maximum frame | |
92 | * size to 1632, and mask all interrupt sources. | |
93 | */ | |
94 | REG_WRITE(REG_GLOBAL, 0x04, 0x4400); | |
95 | ||
3675c8d7 | 96 | /* Set the default address aging time to 5 minutes, and |
2e5f0320 LB |
97 | * enable address learn messages to be sent to all message |
98 | * ports. | |
99 | */ | |
100 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | |
101 | ||
3675c8d7 | 102 | /* Configure the priority mapping registers. */ |
2e5f0320 LB |
103 | ret = mv88e6xxx_config_prio(ds); |
104 | if (ret < 0) | |
105 | return ret; | |
106 | ||
3675c8d7 | 107 | /* Set the VLAN ethertype to 0x8100. */ |
2e5f0320 LB |
108 | REG_WRITE(REG_GLOBAL, 0x19, 0x8100); |
109 | ||
3675c8d7 | 110 | /* Disable ARP mirroring, and configure the upstream port as |
e84665c9 LB |
111 | * the port to which ingress and egress monitor frames are to |
112 | * be sent. | |
2e5f0320 | 113 | */ |
e84665c9 | 114 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0); |
2e5f0320 | 115 | |
3675c8d7 | 116 | /* Disable cascade port functionality unless this device |
81399ec6 | 117 | * is used in a cascade configuration, and set the switch's |
e84665c9 | 118 | * DSA device number. |
2e5f0320 | 119 | */ |
81399ec6 BG |
120 | if (ds->dst->pd->nr_chips > 1) |
121 | REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f)); | |
122 | else | |
123 | REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f)); | |
2e5f0320 | 124 | |
3675c8d7 | 125 | /* Send all frames with destination addresses matching |
2e5f0320 LB |
126 | * 01:80:c2:00:00:0x to the CPU port. |
127 | */ | |
128 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | |
129 | ||
3675c8d7 | 130 | /* Ignore removed tag data on doubly tagged packets, disable |
2e5f0320 LB |
131 | * flow control messages, force flow control priority to the |
132 | * highest, and send all special multicast frames to the CPU | |
25985edc | 133 | * port at the highest priority. |
2e5f0320 LB |
134 | */ |
135 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | |
136 | ||
3675c8d7 | 137 | /* Program the DSA routing table. */ |
e84665c9 LB |
138 | for (i = 0; i < 32; i++) { |
139 | int nexthop; | |
140 | ||
141 | nexthop = 0x1f; | |
6e0ba47f TW |
142 | if (ds->pd->rtable && |
143 | i != ds->index && i < ds->dst->pd->nr_chips) | |
e84665c9 LB |
144 | nexthop = ds->pd->rtable[i] & 0x1f; |
145 | ||
146 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); | |
147 | } | |
2e5f0320 | 148 | |
3675c8d7 | 149 | /* Clear all trunk masks. */ |
2e5f0320 | 150 | for (i = 0; i < 8; i++) |
076d3e10 | 151 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff); |
2e5f0320 | 152 | |
3675c8d7 | 153 | /* Clear all trunk mappings. */ |
2e5f0320 LB |
154 | for (i = 0; i < 16; i++) |
155 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | |
156 | ||
3675c8d7 | 157 | /* Force the priority of IGMP/MLD snoop frames and ARP frames |
2e5f0320 LB |
158 | * to the highest setting. |
159 | */ | |
160 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff); | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static int mv88e6131_setup_port(struct dsa_switch *ds, int p) | |
166 | { | |
a22adce5 | 167 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 168 | int addr = REG_PORT(p); |
e84665c9 | 169 | u16 val; |
2e5f0320 | 170 | |
3675c8d7 | 171 | /* MAC Forcing register: don't force link, speed, duplex |
076d3e10 | 172 | * or flow control state to any particular values on physical |
e84665c9 | 173 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s |
ec80bfcb | 174 | * (100 Mb/s on 6085) full duplex. |
2e5f0320 | 175 | */ |
e84665c9 | 176 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) |
ec80bfcb PK |
177 | if (ps->id == ID_6085) |
178 | REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */ | |
179 | else | |
180 | REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */ | |
076d3e10 LB |
181 | else |
182 | REG_WRITE(addr, 0x01, 0x0003); | |
2e5f0320 | 183 | |
3675c8d7 | 184 | /* Port Control: disable Core Tag, disable Drop-on-Lock, |
2e5f0320 LB |
185 | * transmit frames unmodified, disable Header mode, |
186 | * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN | |
187 | * tunneling, determine priority by looking at 802.1p and | |
188 | * IP priority fields (IP prio has precedence), and set STP | |
e84665c9 LB |
189 | * state to Forwarding. |
190 | * | |
191 | * If this is the upstream port for this switch, enable | |
192 | * forwarding of unknown unicasts, and enable DSA tagging | |
193 | * mode. | |
194 | * | |
195 | * If this is the link to another switch, use DSA tagging | |
196 | * mode, but do not enable forwarding of unknown unicasts. | |
2e5f0320 | 197 | */ |
e84665c9 | 198 | val = 0x0433; |
b3b27005 | 199 | if (p == dsa_upstream_port(ds)) { |
e84665c9 | 200 | val |= 0x0104; |
3675c8d7 | 201 | /* On 6085, unknown multicast forward is controlled |
b3b27005 PK |
202 | * here rather than in Port Control 2 register. |
203 | */ | |
204 | if (ps->id == ID_6085) | |
205 | val |= 0x0008; | |
206 | } | |
e84665c9 LB |
207 | if (ds->dsa_port_mask & (1 << p)) |
208 | val |= 0x0100; | |
209 | REG_WRITE(addr, 0x04, val); | |
2e5f0320 | 210 | |
3675c8d7 | 211 | /* Port Control 1: disable trunking. Also, if this is the |
2e5f0320 LB |
212 | * CPU port, enable learn messages to be sent to this port. |
213 | */ | |
e84665c9 | 214 | REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); |
2e5f0320 | 215 | |
3675c8d7 | 216 | /* Port based VLAN map: give each port its own address |
2e5f0320 LB |
217 | * database, allow the CPU port to talk to each of the 'real' |
218 | * ports, and allow each of the 'real' ports to only talk to | |
e84665c9 | 219 | * the upstream port. |
2e5f0320 | 220 | */ |
e84665c9 LB |
221 | val = (p & 0xf) << 12; |
222 | if (dsa_is_cpu_port(ds, p)) | |
223 | val |= ds->phys_port_mask; | |
224 | else | |
225 | val |= 1 << dsa_upstream_port(ds); | |
226 | REG_WRITE(addr, 0x06, val); | |
2e5f0320 | 227 | |
3675c8d7 | 228 | /* Default VLAN ID and priority: don't set a default VLAN |
2e5f0320 LB |
229 | * ID, and set the default packet priority to zero. |
230 | */ | |
231 | REG_WRITE(addr, 0x07, 0x0000); | |
232 | ||
3675c8d7 | 233 | /* Port Control 2: don't force a good FCS, don't use |
2e5f0320 LB |
234 | * VLAN-based, source address-based or destination |
235 | * address-based priority overrides, don't let the switch | |
236 | * add or strip 802.1q tags, don't discard tagged or | |
237 | * untagged frames on this port, do a destination address | |
238 | * lookup on received packets as usual, don't send a copy | |
239 | * of all transmitted/received frames on this port to the | |
e84665c9 LB |
240 | * CPU, and configure the upstream port number. |
241 | * | |
242 | * If this is the upstream port for this switch, enable | |
243 | * forwarding of unknown multicast addresses. | |
2e5f0320 | 244 | */ |
b3b27005 | 245 | if (ps->id == ID_6085) |
3675c8d7 | 246 | /* on 6085, bits 3:0 are reserved, bit 6 control ARP |
b3b27005 PK |
247 | * mirroring, and multicast forward is handled in |
248 | * Port Control register. | |
249 | */ | |
250 | REG_WRITE(addr, 0x08, 0x0080); | |
251 | else { | |
252 | val = 0x0080 | dsa_upstream_port(ds); | |
253 | if (p == dsa_upstream_port(ds)) | |
254 | val |= 0x0040; | |
255 | REG_WRITE(addr, 0x08, val); | |
256 | } | |
2e5f0320 | 257 | |
3675c8d7 | 258 | /* Rate Control: disable ingress rate limiting. */ |
2e5f0320 LB |
259 | REG_WRITE(addr, 0x09, 0x0000); |
260 | ||
3675c8d7 | 261 | /* Rate Control 2: disable egress rate limiting. */ |
2e5f0320 LB |
262 | REG_WRITE(addr, 0x0a, 0x0000); |
263 | ||
3675c8d7 | 264 | /* Port Association Vector: when learning source addresses |
2e5f0320 LB |
265 | * of packets, add the address to the address database using |
266 | * a port bitmap that has only the bit for this port set and | |
267 | * the other bits clear. | |
268 | */ | |
269 | REG_WRITE(addr, 0x0b, 1 << p); | |
270 | ||
3675c8d7 | 271 | /* Tag Remap: use an identity 802.1p prio -> switch prio |
2e5f0320 LB |
272 | * mapping. |
273 | */ | |
274 | REG_WRITE(addr, 0x18, 0x3210); | |
275 | ||
3675c8d7 | 276 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio |
2e5f0320 LB |
277 | * mapping. |
278 | */ | |
279 | REG_WRITE(addr, 0x19, 0x7654); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
284 | static int mv88e6131_setup(struct dsa_switch *ds) | |
285 | { | |
a22adce5 | 286 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
287 | int i; |
288 | int ret; | |
289 | ||
290 | mutex_init(&ps->smi_mutex); | |
291 | mv88e6xxx_ppu_state_init(ds); | |
292 | mutex_init(&ps->stats_mutex); | |
293 | ||
ec80bfcb PK |
294 | ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0; |
295 | ||
2e5f0320 LB |
296 | ret = mv88e6131_switch_reset(ds); |
297 | if (ret < 0) | |
298 | return ret; | |
299 | ||
300 | /* @@@ initialise vtu and atu */ | |
301 | ||
302 | ret = mv88e6131_setup_global(ds); | |
303 | if (ret < 0) | |
304 | return ret; | |
305 | ||
076d3e10 | 306 | for (i = 0; i < 11; i++) { |
2e5f0320 LB |
307 | ret = mv88e6131_setup_port(ds, i); |
308 | if (ret < 0) | |
309 | return ret; | |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | static int mv88e6131_port_to_phy_addr(int port) | |
316 | { | |
076d3e10 | 317 | if (port >= 0 && port <= 11) |
2e5f0320 LB |
318 | return port; |
319 | return -1; | |
320 | } | |
321 | ||
322 | static int | |
323 | mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum) | |
324 | { | |
325 | int addr = mv88e6131_port_to_phy_addr(port); | |
326 | return mv88e6xxx_phy_read_ppu(ds, addr, regnum); | |
327 | } | |
328 | ||
329 | static int | |
330 | mv88e6131_phy_write(struct dsa_switch *ds, | |
331 | int port, int regnum, u16 val) | |
332 | { | |
333 | int addr = mv88e6131_port_to_phy_addr(port); | |
334 | return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val); | |
335 | } | |
336 | ||
337 | static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = { | |
338 | { "in_good_octets", 8, 0x00, }, | |
339 | { "in_bad_octets", 4, 0x02, }, | |
340 | { "in_unicast", 4, 0x04, }, | |
341 | { "in_broadcasts", 4, 0x06, }, | |
342 | { "in_multicasts", 4, 0x07, }, | |
343 | { "in_pause", 4, 0x16, }, | |
344 | { "in_undersize", 4, 0x18, }, | |
345 | { "in_fragments", 4, 0x19, }, | |
346 | { "in_oversize", 4, 0x1a, }, | |
347 | { "in_jabber", 4, 0x1b, }, | |
348 | { "in_rx_error", 4, 0x1c, }, | |
349 | { "in_fcs_error", 4, 0x1d, }, | |
350 | { "out_octets", 8, 0x0e, }, | |
351 | { "out_unicast", 4, 0x10, }, | |
352 | { "out_broadcasts", 4, 0x13, }, | |
353 | { "out_multicasts", 4, 0x12, }, | |
354 | { "out_pause", 4, 0x15, }, | |
355 | { "excessive", 4, 0x11, }, | |
356 | { "collisions", 4, 0x1e, }, | |
357 | { "deferred", 4, 0x05, }, | |
358 | { "single", 4, 0x14, }, | |
359 | { "multiple", 4, 0x17, }, | |
360 | { "out_fcs_error", 4, 0x03, }, | |
361 | { "late", 4, 0x1f, }, | |
362 | { "hist_64bytes", 4, 0x08, }, | |
363 | { "hist_65_127bytes", 4, 0x09, }, | |
364 | { "hist_128_255bytes", 4, 0x0a, }, | |
365 | { "hist_256_511bytes", 4, 0x0b, }, | |
366 | { "hist_512_1023bytes", 4, 0x0c, }, | |
367 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
368 | }; | |
369 | ||
370 | static void | |
371 | mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
372 | { | |
373 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats), | |
374 | mv88e6131_hw_stats, port, data); | |
375 | } | |
376 | ||
377 | static void | |
378 | mv88e6131_get_ethtool_stats(struct dsa_switch *ds, | |
379 | int port, uint64_t *data) | |
380 | { | |
381 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats), | |
382 | mv88e6131_hw_stats, port, data); | |
383 | } | |
384 | ||
385 | static int mv88e6131_get_sset_count(struct dsa_switch *ds) | |
386 | { | |
387 | return ARRAY_SIZE(mv88e6131_hw_stats); | |
388 | } | |
389 | ||
98e67308 | 390 | struct dsa_switch_driver mv88e6131_switch_driver = { |
ac7a04c3 | 391 | .tag_protocol = DSA_TAG_PROTO_DSA, |
2e5f0320 LB |
392 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
393 | .probe = mv88e6131_probe, | |
394 | .setup = mv88e6131_setup, | |
395 | .set_addr = mv88e6xxx_set_addr_direct, | |
396 | .phy_read = mv88e6131_phy_read, | |
397 | .phy_write = mv88e6131_phy_write, | |
398 | .poll_link = mv88e6xxx_poll_link, | |
399 | .get_strings = mv88e6131_get_strings, | |
400 | .get_ethtool_stats = mv88e6131_get_ethtool_stats, | |
401 | .get_sset_count = mv88e6131_get_sset_count, | |
402 | }; | |
3d825ede BH |
403 | |
404 | MODULE_ALIAS("platform:mv88e6085"); | |
405 | MODULE_ALIAS("platform:mv88e6095"); | |
406 | MODULE_ALIAS("platform:mv88e6095f"); | |
407 | MODULE_ALIAS("platform:mv88e6131"); |