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2e5f0320 | 1 | /* |
076d3e10 LB |
2 | * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support |
3 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
2e5f0320 LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e BG |
11 | #include <linux/delay.h> |
12 | #include <linux/jiffies.h> | |
2e5f0320 | 13 | #include <linux/list.h> |
2bbba277 | 14 | #include <linux/module.h> |
2e5f0320 LB |
15 | #include <linux/netdevice.h> |
16 | #include <linux/phy.h> | |
c8f0b869 | 17 | #include <net/dsa.h> |
2e5f0320 LB |
18 | #include "mv88e6xxx.h" |
19 | ||
f6271e67 VD |
20 | static const struct mv88e6xxx_info mv88e6131_table[] = { |
21 | { | |
22 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, | |
22356476 | 23 | .family = MV88E6XXX_FAMILY_6095, |
f6271e67 | 24 | .name = "Marvell 88E6095/88E6095F", |
cd5a2c82 | 25 | .num_databases = 256, |
009a2b98 | 26 | .num_ports = 11, |
b5058d7a | 27 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
f6271e67 VD |
28 | }, { |
29 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, | |
22356476 | 30 | .family = MV88E6XXX_FAMILY_6097, |
f6271e67 | 31 | .name = "Marvell 88E6085", |
cd5a2c82 | 32 | .num_databases = 4096, |
009a2b98 | 33 | .num_ports = 10, |
b5058d7a | 34 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
f6271e67 VD |
35 | }, { |
36 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, | |
22356476 | 37 | .family = MV88E6XXX_FAMILY_6185, |
f6271e67 | 38 | .name = "Marvell 88E6131", |
cd5a2c82 | 39 | .num_databases = 256, |
009a2b98 | 40 | .num_ports = 8, |
b5058d7a | 41 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
f6271e67 VD |
42 | }, { |
43 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, | |
22356476 | 44 | .family = MV88E6XXX_FAMILY_6185, |
f6271e67 | 45 | .name = "Marvell 88E6185", |
cd5a2c82 | 46 | .num_databases = 256, |
009a2b98 | 47 | .num_ports = 10, |
b5058d7a | 48 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
f6271e67 | 49 | } |
b9b37713 VD |
50 | }; |
51 | ||
0209d144 VD |
52 | static const char *mv88e6131_drv_probe(struct device *dsa_dev, |
53 | struct device *host_dev, int sw_addr, | |
54 | void **priv) | |
2e5f0320 | 55 | { |
a77d43f1 AL |
56 | return mv88e6xxx_drv_probe(dsa_dev, host_dev, sw_addr, priv, |
57 | mv88e6131_table, | |
58 | ARRAY_SIZE(mv88e6131_table)); | |
2e5f0320 LB |
59 | } |
60 | ||
2e5f0320 LB |
61 | static int mv88e6131_setup_global(struct dsa_switch *ds) |
62 | { | |
158bc065 | 63 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
15966a2a | 64 | u32 upstream_port = dsa_upstream_port(ds); |
2e5f0320 | 65 | int ret; |
15966a2a | 66 | u32 reg; |
54d792f2 AL |
67 | |
68 | ret = mv88e6xxx_setup_global(ds); | |
69 | if (ret) | |
70 | return ret; | |
2e5f0320 | 71 | |
3675c8d7 | 72 | /* Enable the PHY polling unit, don't discard packets with |
2e5f0320 LB |
73 | * excessive collisions, use a weighted fair queueing scheme |
74 | * to arbitrate between packet queues, set the maximum frame | |
75 | * size to 1632, and mask all interrupt sources. | |
76 | */ | |
158bc065 | 77 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, |
48ace4ef AL |
78 | GLOBAL_CONTROL_PPU_ENABLE | |
79 | GLOBAL_CONTROL_MAX_FRAME_1632); | |
80 | if (ret) | |
81 | return ret; | |
2e5f0320 | 82 | |
3675c8d7 | 83 | /* Set the VLAN ethertype to 0x8100. */ |
158bc065 | 84 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100); |
48ace4ef AL |
85 | if (ret) |
86 | return ret; | |
2e5f0320 | 87 | |
3675c8d7 | 88 | /* Disable ARP mirroring, and configure the upstream port as |
e84665c9 LB |
89 | * the port to which ingress and egress monitor frames are to |
90 | * be sent. | |
2e5f0320 | 91 | */ |
15966a2a AL |
92 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | |
93 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
94 | GLOBAL_MONITOR_CONTROL_ARP_DISABLED; | |
158bc065 | 95 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); |
48ace4ef AL |
96 | if (ret) |
97 | return ret; | |
2e5f0320 | 98 | |
3675c8d7 | 99 | /* Disable cascade port functionality unless this device |
81399ec6 | 100 | * is used in a cascade configuration, and set the switch's |
e84665c9 | 101 | * DSA device number. |
2e5f0320 | 102 | */ |
81399ec6 | 103 | if (ds->dst->pd->nr_chips > 1) |
158bc065 | 104 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2, |
48ace4ef AL |
105 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | |
106 | (ds->index & 0x1f)); | |
81399ec6 | 107 | else |
158bc065 | 108 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2, |
48ace4ef AL |
109 | GLOBAL_CONTROL_2_NO_CASCADE | |
110 | (ds->index & 0x1f)); | |
111 | if (ret) | |
112 | return ret; | |
2e5f0320 | 113 | |
3675c8d7 | 114 | /* Force the priority of IGMP/MLD snoop frames and ARP frames |
2e5f0320 LB |
115 | * to the highest setting. |
116 | */ | |
158bc065 | 117 | return mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, |
48ace4ef AL |
118 | GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP | |
119 | 7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT | | |
120 | GLOBAL2_PRIO_OVERRIDE_FORCE_ARP | | |
121 | 7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT); | |
2e5f0320 LB |
122 | } |
123 | ||
2e5f0320 LB |
124 | static int mv88e6131_setup(struct dsa_switch *ds) |
125 | { | |
158bc065 | 126 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
127 | int ret; |
128 | ||
158bc065 AL |
129 | ps->ds = ds; |
130 | ||
131 | ret = mv88e6xxx_setup_common(ps); | |
0d65da4a GR |
132 | if (ret < 0) |
133 | return ret; | |
2e5f0320 | 134 | |
158bc065 | 135 | ret = mv88e6xxx_switch_reset(ps, false); |
2e5f0320 LB |
136 | if (ret < 0) |
137 | return ret; | |
138 | ||
2e5f0320 LB |
139 | ret = mv88e6131_setup_global(ds); |
140 | if (ret < 0) | |
141 | return ret; | |
142 | ||
dbde9e66 | 143 | return mv88e6xxx_setup_ports(ds); |
2e5f0320 LB |
144 | } |
145 | ||
98e67308 | 146 | struct dsa_switch_driver mv88e6131_switch_driver = { |
ac7a04c3 | 147 | .tag_protocol = DSA_TAG_PROTO_DSA, |
e49bad31 | 148 | .probe = mv88e6131_drv_probe, |
2e5f0320 | 149 | .setup = mv88e6131_setup, |
1d13a06e | 150 | .set_addr = mv88e6xxx_set_addr, |
8c9983a2 VD |
151 | .phy_read = mv88e6xxx_phy_read, |
152 | .phy_write = mv88e6xxx_phy_write, | |
aadbdb8a VD |
153 | .set_eee = mv88e6xxx_set_eee, |
154 | .get_eee = mv88e6xxx_get_eee, | |
e413e7e1 AL |
155 | .get_strings = mv88e6xxx_get_strings, |
156 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
157 | .get_sset_count = mv88e6xxx_get_sset_count, | |
d24645be VD |
158 | .get_eeprom = mv88e6xxx_get_eeprom, |
159 | .set_eeprom = mv88e6xxx_set_eeprom, | |
23062513 VD |
160 | .get_regs_len = mv88e6xxx_get_regs_len, |
161 | .get_regs = mv88e6xxx_get_regs, | |
6594f615 VD |
162 | #ifdef CONFIG_NET_DSA_HWMON |
163 | .get_temp = mv88e6xxx_get_temp, | |
164 | .get_temp_limit = mv88e6xxx_get_temp_limit, | |
165 | .set_temp_limit = mv88e6xxx_set_temp_limit, | |
166 | .get_temp_alarm = mv88e6xxx_get_temp_alarm, | |
167 | #endif | |
dea87024 | 168 | .adjust_link = mv88e6xxx_adjust_link, |
26892ffc VD |
169 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
170 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
171 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, | |
172 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
173 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
174 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
175 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, | |
176 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, | |
177 | .port_fdb_add = mv88e6xxx_port_fdb_add, | |
178 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
179 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
2e5f0320 | 180 | }; |
3d825ede BH |
181 | |
182 | MODULE_ALIAS("platform:mv88e6085"); | |
183 | MODULE_ALIAS("platform:mv88e6095"); | |
184 | MODULE_ALIAS("platform:mv88e6095f"); | |
185 | MODULE_ALIAS("platform:mv88e6131"); |