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3ad50cca GR |
1 | /* |
2 | * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support | |
3 | * | |
4 | * Copyright (c) 2014 Guenter Roeck | |
5 | * | |
6 | * Derived from mv88e6123_61_65.c | |
7 | * Copyright (c) 2008-2009 Marvell Semiconductor | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/jiffies.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/netdevice.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/phy.h> | |
22 | #include <net/dsa.h> | |
23 | #include "mv88e6xxx.h" | |
24 | ||
3ad50cca GR |
25 | static char *mv88e6352_probe(struct device *host_dev, int sw_addr) |
26 | { | |
27 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); | |
28 | int ret; | |
29 | ||
30 | if (bus == NULL) | |
31 | return NULL; | |
32 | ||
33 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); | |
34 | if (ret >= 0) { | |
2716777b GR |
35 | if ((ret & 0xfff0) == 0x1760) |
36 | return "Marvell 88E6176"; | |
3ad50cca GR |
37 | if (ret == 0x3521) |
38 | return "Marvell 88E6352 (A0)"; | |
39 | if (ret == 0x3522) | |
40 | return "Marvell 88E6352 (A1)"; | |
41 | if ((ret & 0xfff0) == 0x3520) | |
42 | return "Marvell 88E6352"; | |
43 | } | |
44 | ||
45 | return NULL; | |
46 | } | |
47 | ||
48 | static int mv88e6352_switch_reset(struct dsa_switch *ds) | |
49 | { | |
50 | unsigned long timeout; | |
51 | int ret; | |
52 | int i; | |
53 | ||
54 | /* Set all ports to the disabled state. */ | |
55 | for (i = 0; i < 7; i++) { | |
56 | ret = REG_READ(REG_PORT(i), 0x04); | |
57 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); | |
58 | } | |
59 | ||
60 | /* Wait for transmit queues to drain. */ | |
61 | usleep_range(2000, 4000); | |
62 | ||
63 | /* Reset the switch. Keep PPU active (bit 14, undocumented). | |
64 | * The PPU needs to be active to support indirect phy register | |
65 | * accesses through global registers 0x18 and 0x19. | |
66 | */ | |
67 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
68 | ||
69 | /* Wait up to one second for reset to complete. */ | |
70 | timeout = jiffies + 1 * HZ; | |
71 | while (time_before(jiffies, timeout)) { | |
72 | ret = REG_READ(REG_GLOBAL, 0x00); | |
73 | if ((ret & 0x8800) == 0x8800) | |
74 | break; | |
75 | usleep_range(1000, 2000); | |
76 | } | |
77 | if (time_after(jiffies, timeout)) | |
78 | return -ETIMEDOUT; | |
79 | ||
80 | return 0; | |
81 | } | |
82 | ||
83 | static int mv88e6352_setup_global(struct dsa_switch *ds) | |
84 | { | |
85 | int ret; | |
86 | int i; | |
87 | ||
88 | /* Discard packets with excessive collisions, | |
89 | * mask all interrupt sources, enable PPU (bit 14, undocumented). | |
90 | */ | |
91 | REG_WRITE(REG_GLOBAL, 0x04, 0x6000); | |
92 | ||
93 | /* Set the default address aging time to 5 minutes, and | |
94 | * enable address learn messages to be sent to all message | |
95 | * ports. | |
96 | */ | |
97 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); | |
98 | ||
99 | /* Configure the priority mapping registers. */ | |
100 | ret = mv88e6xxx_config_prio(ds); | |
101 | if (ret < 0) | |
102 | return ret; | |
103 | ||
104 | /* Configure the upstream port, and configure the upstream | |
105 | * port as the port to which ingress and egress monitor frames | |
106 | * are to be sent. | |
107 | */ | |
108 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); | |
109 | ||
110 | /* Disable remote management for now, and set the switch's | |
111 | * DSA device number. | |
112 | */ | |
113 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); | |
114 | ||
115 | /* Send all frames with destination addresses matching | |
116 | * 01:80:c2:00:00:2x to the CPU port. | |
117 | */ | |
118 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); | |
119 | ||
120 | /* Send all frames with destination addresses matching | |
121 | * 01:80:c2:00:00:0x to the CPU port. | |
122 | */ | |
123 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); | |
124 | ||
125 | /* Disable the loopback filter, disable flow control | |
126 | * messages, disable flood broadcast override, disable | |
127 | * removing of provider tags, disable ATU age violation | |
128 | * interrupts, disable tag flow control, force flow | |
129 | * control priority to the highest, and send all special | |
130 | * multicast frames to the CPU at the highest priority. | |
131 | */ | |
132 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); | |
133 | ||
134 | /* Program the DSA routing table. */ | |
135 | for (i = 0; i < 32; i++) { | |
136 | int nexthop = 0x1f; | |
137 | ||
138 | if (i != ds->index && i < ds->dst->pd->nr_chips) | |
139 | nexthop = ds->pd->rtable[i] & 0x1f; | |
140 | ||
141 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); | |
142 | } | |
143 | ||
144 | /* Clear all trunk masks. */ | |
145 | for (i = 0; i < 8; i++) | |
146 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f); | |
147 | ||
148 | /* Clear all trunk mappings. */ | |
149 | for (i = 0; i < 16; i++) | |
150 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); | |
151 | ||
152 | /* Disable ingress rate limiting by resetting all ingress | |
153 | * rate limit registers to their initial state. | |
154 | */ | |
155 | for (i = 0; i < 7; i++) | |
156 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); | |
157 | ||
158 | /* Initialise cross-chip port VLAN table to reset defaults. */ | |
159 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); | |
160 | ||
161 | /* Clear the priority override table. */ | |
162 | for (i = 0; i < 16; i++) | |
163 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); | |
164 | ||
165 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | static int mv88e6352_setup_port(struct dsa_switch *ds, int p) | |
171 | { | |
172 | int addr = REG_PORT(p); | |
173 | u16 val; | |
174 | ||
175 | /* MAC Forcing register: don't force link, speed, duplex | |
176 | * or flow control state to any particular values on physical | |
177 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s | |
178 | * full duplex. | |
179 | */ | |
180 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) | |
181 | REG_WRITE(addr, 0x01, 0x003e); | |
182 | else | |
183 | REG_WRITE(addr, 0x01, 0x0003); | |
184 | ||
185 | /* Do not limit the period of time that this port can be | |
186 | * paused for by the remote end or the period of time that | |
187 | * this port can pause the remote end. | |
188 | */ | |
189 | REG_WRITE(addr, 0x02, 0x0000); | |
190 | ||
191 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
192 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
193 | * tunneling, determine priority by looking at 802.1p and IP | |
194 | * priority fields (IP prio has precedence), and set STP state | |
195 | * to Forwarding. | |
196 | * | |
197 | * If this is the CPU link, use DSA or EDSA tagging depending | |
198 | * on which tagging mode was configured. | |
199 | * | |
200 | * If this is a link to another switch, use DSA tagging mode. | |
201 | * | |
202 | * If this is the upstream port for this switch, enable | |
203 | * forwarding of unknown unicasts and multicasts. | |
204 | */ | |
205 | val = 0x0433; | |
206 | if (dsa_is_cpu_port(ds, p)) { | |
207 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
208 | val |= 0x3300; | |
209 | else | |
210 | val |= 0x0100; | |
211 | } | |
212 | if (ds->dsa_port_mask & (1 << p)) | |
213 | val |= 0x0100; | |
214 | if (p == dsa_upstream_port(ds)) | |
215 | val |= 0x000c; | |
216 | REG_WRITE(addr, 0x04, val); | |
217 | ||
218 | /* Port Control 1: disable trunking. Also, if this is the | |
219 | * CPU port, enable learn messages to be sent to this port. | |
220 | */ | |
221 | REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); | |
222 | ||
223 | /* Port based VLAN map: give each port its own address | |
224 | * database, allow the CPU port to talk to each of the 'real' | |
225 | * ports, and allow each of the 'real' ports to only talk to | |
226 | * the upstream port. | |
227 | */ | |
228 | val = (p & 0xf) << 12; | |
229 | if (dsa_is_cpu_port(ds, p)) | |
230 | val |= ds->phys_port_mask; | |
231 | else | |
232 | val |= 1 << dsa_upstream_port(ds); | |
233 | REG_WRITE(addr, 0x06, val); | |
234 | ||
235 | /* Default VLAN ID and priority: don't set a default VLAN | |
236 | * ID, and set the default packet priority to zero. | |
237 | */ | |
238 | REG_WRITE(addr, 0x07, 0x0000); | |
239 | ||
240 | /* Port Control 2: don't force a good FCS, set the maximum | |
241 | * frame size to 10240 bytes, don't let the switch add or | |
242 | * strip 802.1q tags, don't discard tagged or untagged frames | |
243 | * on this port, do a destination address lookup on all | |
244 | * received packets as usual, disable ARP mirroring and don't | |
245 | * send a copy of all transmitted/received frames on this port | |
246 | * to the CPU. | |
247 | */ | |
248 | REG_WRITE(addr, 0x08, 0x2080); | |
249 | ||
250 | /* Egress rate control: disable egress rate control. */ | |
251 | REG_WRITE(addr, 0x09, 0x0001); | |
252 | ||
253 | /* Egress rate control 2: disable egress rate control. */ | |
254 | REG_WRITE(addr, 0x0a, 0x0000); | |
255 | ||
256 | /* Port Association Vector: when learning source addresses | |
257 | * of packets, add the address to the address database using | |
258 | * a port bitmap that has only the bit for this port set and | |
259 | * the other bits clear. | |
260 | */ | |
261 | REG_WRITE(addr, 0x0b, 1 << p); | |
262 | ||
263 | /* Port ATU control: disable limiting the number of address | |
264 | * database entries that this port is allowed to use. | |
265 | */ | |
266 | REG_WRITE(addr, 0x0c, 0x0000); | |
267 | ||
268 | /* Priority Override: disable DA, SA and VTU priority override. */ | |
269 | REG_WRITE(addr, 0x0d, 0x0000); | |
270 | ||
271 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ | |
272 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); | |
273 | ||
274 | /* Tag Remap: use an identity 802.1p prio -> switch prio | |
275 | * mapping. | |
276 | */ | |
277 | REG_WRITE(addr, 0x18, 0x3210); | |
278 | ||
279 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio | |
280 | * mapping. | |
281 | */ | |
282 | REG_WRITE(addr, 0x19, 0x7654); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
276db3b1 GR |
287 | #ifdef CONFIG_NET_DSA_HWMON |
288 | ||
289 | static int mv88e6352_phy_page_read(struct dsa_switch *ds, | |
290 | int port, int page, int reg) | |
291 | { | |
292 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
293 | int ret; | |
294 | ||
295 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 296 | ret = mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
276db3b1 GR |
297 | if (ret < 0) |
298 | goto error; | |
f3044683 | 299 | ret = mv88e6xxx_phy_read_indirect(ds, port, reg); |
276db3b1 | 300 | error: |
f3044683 | 301 | mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
276db3b1 GR |
302 | mutex_unlock(&ps->phy_mutex); |
303 | return ret; | |
304 | } | |
305 | ||
306 | static int mv88e6352_phy_page_write(struct dsa_switch *ds, | |
307 | int port, int page, int reg, int val) | |
308 | { | |
309 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
310 | int ret; | |
311 | ||
312 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 313 | ret = mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
276db3b1 GR |
314 | if (ret < 0) |
315 | goto error; | |
316 | ||
f3044683 | 317 | ret = mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
276db3b1 | 318 | error: |
f3044683 | 319 | mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
276db3b1 GR |
320 | mutex_unlock(&ps->phy_mutex); |
321 | return ret; | |
322 | } | |
323 | ||
324 | static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp) | |
325 | { | |
326 | int ret; | |
327 | ||
328 | *temp = 0; | |
329 | ||
330 | ret = mv88e6352_phy_page_read(ds, 0, 6, 27); | |
331 | if (ret < 0) | |
332 | return ret; | |
333 | ||
334 | *temp = (ret & 0xff) - 25; | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp) | |
340 | { | |
341 | int ret; | |
342 | ||
343 | *temp = 0; | |
344 | ||
345 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
346 | if (ret < 0) | |
347 | return ret; | |
348 | ||
349 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp) | |
355 | { | |
356 | int ret; | |
357 | ||
358 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
359 | if (ret < 0) | |
360 | return ret; | |
361 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); | |
362 | return mv88e6352_phy_page_write(ds, 0, 6, 26, | |
363 | (ret & 0xe0ff) | (temp << 8)); | |
364 | } | |
365 | ||
366 | static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm) | |
367 | { | |
368 | int ret; | |
369 | ||
370 | *alarm = false; | |
371 | ||
372 | ret = mv88e6352_phy_page_read(ds, 0, 6, 26); | |
373 | if (ret < 0) | |
374 | return ret; | |
375 | ||
376 | *alarm = !!(ret & 0x40); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | #endif /* CONFIG_NET_DSA_HWMON */ | |
381 | ||
3ad50cca GR |
382 | static int mv88e6352_setup(struct dsa_switch *ds) |
383 | { | |
384 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
385 | int ret; | |
386 | int i; | |
387 | ||
388 | mutex_init(&ps->smi_mutex); | |
389 | mutex_init(&ps->stats_mutex); | |
390 | mutex_init(&ps->phy_mutex); | |
33b43df4 | 391 | mutex_init(&ps->eeprom_mutex); |
3ad50cca GR |
392 | |
393 | ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0; | |
394 | ||
395 | ret = mv88e6352_switch_reset(ds); | |
396 | if (ret < 0) | |
397 | return ret; | |
398 | ||
399 | /* @@@ initialise vtu and atu */ | |
400 | ||
401 | ret = mv88e6352_setup_global(ds); | |
402 | if (ret < 0) | |
403 | return ret; | |
404 | ||
405 | for (i = 0; i < 7; i++) { | |
406 | ret = mv88e6352_setup_port(ds, i); | |
407 | if (ret < 0) | |
408 | return ret; | |
409 | } | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static int mv88e6352_port_to_phy_addr(int port) | |
415 | { | |
416 | if (port >= 0 && port <= 4) | |
417 | return port; | |
418 | return -EINVAL; | |
419 | } | |
420 | ||
421 | static int | |
422 | mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum) | |
423 | { | |
424 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
425 | int addr = mv88e6352_port_to_phy_addr(port); | |
426 | int ret; | |
427 | ||
428 | if (addr < 0) | |
429 | return addr; | |
430 | ||
431 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 432 | ret = mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3ad50cca GR |
433 | mutex_unlock(&ps->phy_mutex); |
434 | ||
435 | return ret; | |
436 | } | |
437 | ||
438 | static int | |
439 | mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
440 | { | |
441 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
442 | int addr = mv88e6352_port_to_phy_addr(port); | |
443 | int ret; | |
444 | ||
445 | if (addr < 0) | |
446 | return addr; | |
447 | ||
448 | mutex_lock(&ps->phy_mutex); | |
f3044683 | 449 | ret = mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3ad50cca GR |
450 | mutex_unlock(&ps->phy_mutex); |
451 | ||
452 | return ret; | |
453 | } | |
454 | ||
455 | static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = { | |
456 | { "in_good_octets", 8, 0x00, }, | |
457 | { "in_bad_octets", 4, 0x02, }, | |
458 | { "in_unicast", 4, 0x04, }, | |
459 | { "in_broadcasts", 4, 0x06, }, | |
460 | { "in_multicasts", 4, 0x07, }, | |
461 | { "in_pause", 4, 0x16, }, | |
462 | { "in_undersize", 4, 0x18, }, | |
463 | { "in_fragments", 4, 0x19, }, | |
464 | { "in_oversize", 4, 0x1a, }, | |
465 | { "in_jabber", 4, 0x1b, }, | |
466 | { "in_rx_error", 4, 0x1c, }, | |
467 | { "in_fcs_error", 4, 0x1d, }, | |
468 | { "out_octets", 8, 0x0e, }, | |
469 | { "out_unicast", 4, 0x10, }, | |
470 | { "out_broadcasts", 4, 0x13, }, | |
471 | { "out_multicasts", 4, 0x12, }, | |
472 | { "out_pause", 4, 0x15, }, | |
473 | { "excessive", 4, 0x11, }, | |
474 | { "collisions", 4, 0x1e, }, | |
475 | { "deferred", 4, 0x05, }, | |
476 | { "single", 4, 0x14, }, | |
477 | { "multiple", 4, 0x17, }, | |
478 | { "out_fcs_error", 4, 0x03, }, | |
479 | { "late", 4, 0x1f, }, | |
480 | { "hist_64bytes", 4, 0x08, }, | |
481 | { "hist_65_127bytes", 4, 0x09, }, | |
482 | { "hist_128_255bytes", 4, 0x0a, }, | |
483 | { "hist_256_511bytes", 4, 0x0b, }, | |
484 | { "hist_512_1023bytes", 4, 0x0c, }, | |
485 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
17ee3e04 GR |
486 | { "sw_in_discards", 4, 0x110, }, |
487 | { "sw_in_filtered", 2, 0x112, }, | |
488 | { "sw_out_filtered", 2, 0x113, }, | |
3ad50cca GR |
489 | }; |
490 | ||
33b43df4 GR |
491 | static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr) |
492 | { | |
493 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
494 | int ret; | |
495 | ||
496 | mutex_lock(&ps->eeprom_mutex); | |
497 | ||
498 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, | |
499 | 0xc000 | (addr & 0xff)); | |
500 | if (ret < 0) | |
501 | goto error; | |
502 | ||
f3044683 | 503 | ret = mv88e6xxx_eeprom_busy_wait(ds); |
33b43df4 GR |
504 | if (ret < 0) |
505 | goto error; | |
506 | ||
507 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15); | |
508 | error: | |
509 | mutex_unlock(&ps->eeprom_mutex); | |
510 | return ret; | |
511 | } | |
512 | ||
513 | static int mv88e6352_get_eeprom(struct dsa_switch *ds, | |
514 | struct ethtool_eeprom *eeprom, u8 *data) | |
515 | { | |
516 | int offset; | |
517 | int len; | |
518 | int ret; | |
519 | ||
520 | offset = eeprom->offset; | |
521 | len = eeprom->len; | |
522 | eeprom->len = 0; | |
523 | ||
524 | eeprom->magic = 0xc3ec4951; | |
525 | ||
f3044683 | 526 | ret = mv88e6xxx_eeprom_load_wait(ds); |
33b43df4 GR |
527 | if (ret < 0) |
528 | return ret; | |
529 | ||
530 | if (offset & 1) { | |
531 | int word; | |
532 | ||
533 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
534 | if (word < 0) | |
535 | return word; | |
536 | ||
537 | *data++ = (word >> 8) & 0xff; | |
538 | ||
539 | offset++; | |
540 | len--; | |
541 | eeprom->len++; | |
542 | } | |
543 | ||
544 | while (len >= 2) { | |
545 | int word; | |
546 | ||
547 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
548 | if (word < 0) | |
549 | return word; | |
550 | ||
551 | *data++ = word & 0xff; | |
552 | *data++ = (word >> 8) & 0xff; | |
553 | ||
554 | offset += 2; | |
555 | len -= 2; | |
556 | eeprom->len += 2; | |
557 | } | |
558 | ||
559 | if (len) { | |
560 | int word; | |
561 | ||
562 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
563 | if (word < 0) | |
564 | return word; | |
565 | ||
566 | *data++ = word & 0xff; | |
567 | ||
568 | offset++; | |
569 | len--; | |
570 | eeprom->len++; | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
576 | static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds) | |
577 | { | |
578 | int ret; | |
579 | ||
580 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14); | |
581 | if (ret < 0) | |
582 | return ret; | |
583 | ||
584 | if (!(ret & 0x0400)) | |
585 | return -EROFS; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr, | |
591 | u16 data) | |
592 | { | |
593 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
594 | int ret; | |
595 | ||
596 | mutex_lock(&ps->eeprom_mutex); | |
597 | ||
598 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data); | |
599 | if (ret < 0) | |
600 | goto error; | |
601 | ||
602 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14, | |
603 | 0xb000 | (addr & 0xff)); | |
604 | if (ret < 0) | |
605 | goto error; | |
606 | ||
f3044683 | 607 | ret = mv88e6xxx_eeprom_busy_wait(ds); |
33b43df4 GR |
608 | error: |
609 | mutex_unlock(&ps->eeprom_mutex); | |
610 | return ret; | |
611 | } | |
612 | ||
613 | static int mv88e6352_set_eeprom(struct dsa_switch *ds, | |
614 | struct ethtool_eeprom *eeprom, u8 *data) | |
615 | { | |
616 | int offset; | |
617 | int ret; | |
618 | int len; | |
619 | ||
620 | if (eeprom->magic != 0xc3ec4951) | |
621 | return -EINVAL; | |
622 | ||
623 | ret = mv88e6352_eeprom_is_readonly(ds); | |
624 | if (ret) | |
625 | return ret; | |
626 | ||
627 | offset = eeprom->offset; | |
628 | len = eeprom->len; | |
629 | eeprom->len = 0; | |
630 | ||
f3044683 | 631 | ret = mv88e6xxx_eeprom_load_wait(ds); |
33b43df4 GR |
632 | if (ret < 0) |
633 | return ret; | |
634 | ||
635 | if (offset & 1) { | |
636 | int word; | |
637 | ||
638 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
639 | if (word < 0) | |
640 | return word; | |
641 | ||
642 | word = (*data++ << 8) | (word & 0xff); | |
643 | ||
644 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
645 | if (ret < 0) | |
646 | return ret; | |
647 | ||
648 | offset++; | |
649 | len--; | |
650 | eeprom->len++; | |
651 | } | |
652 | ||
653 | while (len >= 2) { | |
654 | int word; | |
655 | ||
656 | word = *data++; | |
657 | word |= *data++ << 8; | |
658 | ||
659 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
660 | if (ret < 0) | |
661 | return ret; | |
662 | ||
663 | offset += 2; | |
664 | len -= 2; | |
665 | eeprom->len += 2; | |
666 | } | |
667 | ||
668 | if (len) { | |
669 | int word; | |
670 | ||
671 | word = mv88e6352_read_eeprom_word(ds, offset >> 1); | |
672 | if (word < 0) | |
673 | return word; | |
674 | ||
675 | word = (word & 0xff00) | *data++; | |
676 | ||
677 | ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word); | |
678 | if (ret < 0) | |
679 | return ret; | |
680 | ||
681 | offset++; | |
682 | len--; | |
683 | eeprom->len++; | |
684 | } | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
3ad50cca GR |
689 | static void |
690 | mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
691 | { | |
692 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats), | |
693 | mv88e6352_hw_stats, port, data); | |
694 | } | |
695 | ||
696 | static void | |
697 | mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) | |
698 | { | |
699 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats), | |
700 | mv88e6352_hw_stats, port, data); | |
701 | } | |
702 | ||
703 | static int mv88e6352_get_sset_count(struct dsa_switch *ds) | |
704 | { | |
705 | return ARRAY_SIZE(mv88e6352_hw_stats); | |
706 | } | |
707 | ||
708 | struct dsa_switch_driver mv88e6352_switch_driver = { | |
709 | .tag_protocol = DSA_TAG_PROTO_EDSA, | |
710 | .priv_size = sizeof(struct mv88e6xxx_priv_state), | |
711 | .probe = mv88e6352_probe, | |
712 | .setup = mv88e6352_setup, | |
713 | .set_addr = mv88e6xxx_set_addr_indirect, | |
714 | .phy_read = mv88e6352_phy_read, | |
715 | .phy_write = mv88e6352_phy_write, | |
716 | .poll_link = mv88e6xxx_poll_link, | |
717 | .get_strings = mv88e6352_get_strings, | |
718 | .get_ethtool_stats = mv88e6352_get_ethtool_stats, | |
719 | .get_sset_count = mv88e6352_get_sset_count, | |
276db3b1 GR |
720 | #ifdef CONFIG_NET_DSA_HWMON |
721 | .get_temp = mv88e6352_get_temp, | |
722 | .get_temp_limit = mv88e6352_get_temp_limit, | |
723 | .set_temp_limit = mv88e6352_set_temp_limit, | |
724 | .get_temp_alarm = mv88e6352_get_temp_alarm, | |
725 | #endif | |
33b43df4 GR |
726 | .get_eeprom = mv88e6352_get_eeprom, |
727 | .set_eeprom = mv88e6352_set_eeprom, | |
95d08b5a GR |
728 | .get_regs_len = mv88e6xxx_get_regs_len, |
729 | .get_regs = mv88e6xxx_get_regs, | |
3ad50cca GR |
730 | }; |
731 | ||
732 | MODULE_ALIAS("platform:mv88e6352"); |