[mirror_ubuntu-hirsute-kernel.git] / drivers / net / dsa / mv88e6352.c

/*
 * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
 *
 * Copyright (c) 2014 Guenter Roeck
 *
 * Derived from mv88e6123_61_65.c
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

static int mv88e6352_phy_wait(struct dsa_switch *ds)
{
	unsigned long timeout = jiffies + HZ / 10;

	while (time_before(jiffies, timeout)) {
		int ret;

		ret = REG_READ(REG_GLOBAL2, 0x18);
		if (ret < 0)
			return ret;

		if (!(ret & 0x8000))
			return 0;

		usleep_range(1000, 2000);
	}
	return -ETIMEDOUT;
}

static int __mv88e6352_phy_read(struct dsa_switch *ds, int addr, int regnum)
{
	int ret;

	REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);

	ret = mv88e6352_phy_wait(ds);
	if (ret < 0)
		return ret;

	return REG_READ(REG_GLOBAL2, 0x19);
}

static int __mv88e6352_phy_write(struct dsa_switch *ds, int addr, int regnum,
				 u16 val)
{
	REG_WRITE(REG_GLOBAL2, 0x19, val);
	REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);

	return mv88e6352_phy_wait(ds);
}

static char *mv88e6352_probe(struct device *host_dev, int sw_addr)
{
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
	int ret;

	if (bus == NULL)
		return NULL;

	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	if (ret >= 0) {
		if ((ret & 0xfff0) == 0x1760)
			return "Marvell 88E6176";
		if (ret == 0x3521)
			return "Marvell 88E6352 (A0)";
		if (ret == 0x3522)
			return "Marvell 88E6352 (A1)";
		if ((ret & 0xfff0) == 0x3520)
			return "Marvell 88E6352";
	}

	return NULL;
}

static int mv88e6352_switch_reset(struct dsa_switch *ds)
{
	unsigned long timeout;
	int ret;
	int i;

	/* Set all ports to the disabled state. */
	for (i = 0; i < 7; i++) {
		ret = REG_READ(REG_PORT(i), 0x04);
		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	}

	/* Wait for transmit queues to drain. */
	usleep_range(2000, 4000);

	/* Reset the switch. Keep PPU active (bit 14, undocumented).
	 * The PPU needs to be active to support indirect phy register
	 * accesses through global registers 0x18 and 0x19.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0xc000);

	/* Wait up to one second for reset to complete. */
	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		if ((ret & 0x8800) == 0x8800)
			break;
		usleep_range(1000, 2000);
	}
	if (time_after(jiffies, timeout))
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6352_setup_global(struct dsa_switch *ds)
{
	int ret;
	int i;

	/* Discard packets with excessive collisions,
	 * mask all interrupt sources, enable PPU (bit 14, undocumented).
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0x6000);

	/* Set the default address aging time to 5 minutes, and
	 * enable address learn messages to be sent to all message
	 * ports.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);

	/* Configure the priority mapping registers. */
	ret = mv88e6xxx_config_prio(ds);
	if (ret < 0)
		return ret;

	/* Configure the upstream port, and configure the upstream
	 * port as the port to which ingress and egress monitor frames
	 * are to be sent.
	 */
	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));

	/* Disable remote management for now, and set the switch's
	 * DSA device number.
	 */
	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);

	/* Send all frames with destination addresses matching
	 * 01:80:c2:00:00:2x to the CPU port.
	 */
	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);

	/* Send all frames with destination addresses matching
	 * 01:80:c2:00:00:0x to the CPU port.
	 */
	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);

	/* Disable the loopback filter, disable flow control
	 * messages, disable flood broadcast override, disable
	 * removing of provider tags, disable ATU age violation
	 * interrupts, disable tag flow control, force flow
	 * control priority to the highest, and send all special
	 * multicast frames to the CPU at the highest priority.
	 */
	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);

	/* Program the DSA routing table. */
	for (i = 0; i < 32; i++) {
		int nexthop = 0x1f;

		if (i != ds->index && i < ds->dst->pd->nr_chips)
			nexthop = ds->pd->rtable[i] & 0x1f;

		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
	}

	/* Clear all trunk masks. */
	for (i = 0; i < 8; i++)
		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f);

	/* Clear all trunk mappings. */
	for (i = 0; i < 16; i++)
		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));

	/* Disable ingress rate limiting by resetting all ingress
	 * rate limit registers to their initial state.
	 */
	for (i = 0; i < 7; i++)
		REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));

	/* Initialise cross-chip port VLAN table to reset defaults. */
	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);

	/* Clear the priority override table. */
	for (i = 0; i < 16; i++)
		REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));

	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */

	return 0;
}

static int mv88e6352_setup_port(struct dsa_switch *ds, int p)
{
	int addr = REG_PORT(p);
	u16 val;

	/* MAC Forcing register: don't force link, speed, duplex
	 * or flow control state to any particular values on physical
	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
	 * full duplex.
	 */
	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
		REG_WRITE(addr, 0x01, 0x003e);
	else
		REG_WRITE(addr, 0x01, 0x0003);

	/* Do not limit the period of time that this port can be
	 * paused for by the remote end or the period of time that
	 * this port can pause the remote end.
	 */
	REG_WRITE(addr, 0x02, 0x0000);

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
	val = 0x0433;
	if (dsa_is_cpu_port(ds, p)) {
		if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
			val |= 0x3300;
		else
			val |= 0x0100;
	}
	if (ds->dsa_port_mask & (1 << p))
		val |= 0x0100;
	if (p == dsa_upstream_port(ds))
		val |= 0x000c;
	REG_WRITE(addr, 0x04, val);

	/* Port Control 1: disable trunking.  Also, if this is the
	 * CPU port, enable learn messages to be sent to this port.
	 */
	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);

	/* Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the upstream port.
	 */
	val = (p & 0xf) << 12;
	if (dsa_is_cpu_port(ds, p))
		val |= ds->phys_port_mask;
	else
		val |= 1 << dsa_upstream_port(ds);
	REG_WRITE(addr, 0x06, val);

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
	REG_WRITE(addr, 0x07, 0x0000);

	/* Port Control 2: don't force a good FCS, set the maximum
	 * frame size to 10240 bytes, don't let the switch add or
	 * strip 802.1q tags, don't discard tagged or untagged frames
	 * on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't
	 * send a copy of all transmitted/received frames on this port
	 * to the CPU.
	 */
	REG_WRITE(addr, 0x08, 0x2080);

	/* Egress rate control: disable egress rate control. */
	REG_WRITE(addr, 0x09, 0x0001);

	/* Egress rate control 2: disable egress rate control. */
	REG_WRITE(addr, 0x0a, 0x0000);

	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, 0x0b, 1 << p);

	/* Port ATU control: disable limiting the number of address
	 * database entries that this port is allowed to use.
	 */
	REG_WRITE(addr, 0x0c, 0x0000);

	/* Priority Override: disable DA, SA and VTU priority override. */
	REG_WRITE(addr, 0x0d, 0x0000);

	/* Port Ethertype: use the Ethertype DSA Ethertype value. */
	REG_WRITE(addr, 0x0f, ETH_P_EDSA);

	/* Tag Remap: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x18, 0x3210);

	/* Tag Remap 2: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x19, 0x7654);

	return 0;
}

static int mv88e6352_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;
	int i;

	mutex_init(&ps->smi_mutex);
	mutex_init(&ps->stats_mutex);
	mutex_init(&ps->phy_mutex);

	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;

	ret = mv88e6352_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise vtu and atu */

	ret = mv88e6352_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < 7; i++) {
		ret = mv88e6352_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6352_port_to_phy_addr(int port)
{
	if (port >= 0 && port <= 4)
		return port;
	return -EINVAL;
}

static int
mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int addr = mv88e6352_port_to_phy_addr(port);
	int ret;

	if (addr < 0)
		return addr;

	mutex_lock(&ps->phy_mutex);
	ret = __mv88e6352_phy_read(ds, addr, regnum);
	mutex_unlock(&ps->phy_mutex);

	return ret;
}

static int
mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int addr = mv88e6352_port_to_phy_addr(port);
	int ret;

	if (addr < 0)
		return addr;

	mutex_lock(&ps->phy_mutex);
	ret = __mv88e6352_phy_write(ds, addr, regnum, val);
	mutex_unlock(&ps->phy_mutex);

	return ret;
}

static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = {
	{ "in_good_octets", 8, 0x00, },
	{ "in_bad_octets", 4, 0x02, },
	{ "in_unicast", 4, 0x04, },
	{ "in_broadcasts", 4, 0x06, },
	{ "in_multicasts", 4, 0x07, },
	{ "in_pause", 4, 0x16, },
	{ "in_undersize", 4, 0x18, },
	{ "in_fragments", 4, 0x19, },
	{ "in_oversize", 4, 0x1a, },
	{ "in_jabber", 4, 0x1b, },
	{ "in_rx_error", 4, 0x1c, },
	{ "in_fcs_error", 4, 0x1d, },
	{ "out_octets", 8, 0x0e, },
	{ "out_unicast", 4, 0x10, },
	{ "out_broadcasts", 4, 0x13, },
	{ "out_multicasts", 4, 0x12, },
	{ "out_pause", 4, 0x15, },
	{ "excessive", 4, 0x11, },
	{ "collisions", 4, 0x1e, },
	{ "deferred", 4, 0x05, },
	{ "single", 4, 0x14, },
	{ "multiple", 4, 0x17, },
	{ "out_fcs_error", 4, 0x03, },
	{ "late", 4, 0x1f, },
	{ "hist_64bytes", 4, 0x08, },
	{ "hist_65_127bytes", 4, 0x09, },
	{ "hist_128_255bytes", 4, 0x0a, },
	{ "hist_256_511bytes", 4, 0x0b, },
	{ "hist_512_1023bytes", 4, 0x0c, },
	{ "hist_1024_max_bytes", 4, 0x0d, },
};

static void
mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
{
	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats),
			      mv88e6352_hw_stats, port, data);
}

static void
mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
{
	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats),
				    mv88e6352_hw_stats, port, data);
}

static int mv88e6352_get_sset_count(struct dsa_switch *ds)
{
	return ARRAY_SIZE(mv88e6352_hw_stats);
}

struct dsa_switch_driver mv88e6352_switch_driver = {
	.tag_protocol		= DSA_TAG_PROTO_EDSA,
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6352_probe,
	.setup			= mv88e6352_setup,
	.set_addr		= mv88e6xxx_set_addr_indirect,
	.phy_read		= mv88e6352_phy_read,
	.phy_write		= mv88e6352_phy_write,
	.poll_link		= mv88e6xxx_poll_link,
	.get_strings		= mv88e6352_get_strings,
	.get_ethtool_stats	= mv88e6352_get_ethtool_stats,
	.get_sset_count		= mv88e6352_get_sset_count,
};

MODULE_ALIAS("platform:mv88e6352");
Commit	Line	Data
3ad50cca GR	1	/*
	2	* net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
	3	*
	4	* Copyright (c) 2014 Guenter Roeck
	5	*
	6	* Derived from mv88e6123_61_65.c
	7	* Copyright (c) 2008-2009 Marvell Semiconductor
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/delay.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/phy.h>
	22	#include <net/dsa.h>
	23	#include "mv88e6xxx.h"
	24
	25	static int mv88e6352_phy_wait(struct dsa_switch *ds)
	26	{
	27	unsigned long timeout = jiffies + HZ / 10;
	28
	29	while (time_before(jiffies, timeout)) {
	30	int ret;
	31
	32	ret = REG_READ(REG_GLOBAL2, 0x18);
	33	if (ret < 0)
	34	return ret;
	35
	36	if (!(ret & 0x8000))
	37	return 0;
	38
	39	usleep_range(1000, 2000);
	40	}
	41	return -ETIMEDOUT;
	42	}
	43
	44	static int __mv88e6352_phy_read(struct dsa_switch *ds, int addr, int regnum)
	45	{
	46	int ret;
	47
	48	REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 \| (addr << 5) \| regnum);
	49
	50	ret = mv88e6352_phy_wait(ds);
	51	if (ret < 0)
	52	return ret;
	53
	54	return REG_READ(REG_GLOBAL2, 0x19);
	55	}
	56
	57	static int __mv88e6352_phy_write(struct dsa_switch *ds, int addr, int regnum,
	58	u16 val)
	59	{
	60	REG_WRITE(REG_GLOBAL2, 0x19, val);
	61	REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 \| (addr << 5) \| regnum);
	62
	63	return mv88e6352_phy_wait(ds);
	64	}
65
66	static char mv88e6352_probe(struct device host_dev, int sw_addr)
67	{
68	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
69	int ret;
70
71	if (bus == NULL)
72	return NULL;
73
74	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
75	if (ret >= 0) {
2716777b GR	76	if ((ret & 0xfff0) == 0x1760)
2716777b GR	77	return "Marvell 88E6176";
3ad50cca GR	78	if (ret == 0x3521)
	79	return "Marvell 88E6352 (A0)";
	80	if (ret == 0x3522)
	81	return "Marvell 88E6352 (A1)";
	82	if ((ret & 0xfff0) == 0x3520)
	83	return "Marvell 88E6352";
	84	}
	85
	86	return NULL;
	87	}
	88
	89	static int mv88e6352_switch_reset(struct dsa_switch *ds)
	90	{
	91	unsigned long timeout;
	92	int ret;
	93	int i;
	94
	95	/* Set all ports to the disabled state. */
	96	for (i = 0; i < 7; i++) {
	97	ret = REG_READ(REG_PORT(i), 0x04);
	98	REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	99	}
	100
	101	/* Wait for transmit queues to drain. */
	102	usleep_range(2000, 4000);
	103
	104	/* Reset the switch. Keep PPU active (bit 14, undocumented).
	105	* The PPU needs to be active to support indirect phy register
	106	* accesses through global registers 0x18 and 0x19.
	107	*/
	108	REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
	109
	110	/* Wait up to one second for reset to complete. */
	111	timeout = jiffies + 1 * HZ;
	112	while (time_before(jiffies, timeout)) {
	113	ret = REG_READ(REG_GLOBAL, 0x00);
	114	if ((ret & 0x8800) == 0x8800)
	115	break;
	116	usleep_range(1000, 2000);
	117	}
	118	if (time_after(jiffies, timeout))
	119	return -ETIMEDOUT;
	120
	121	return 0;
	122	}
	123
	124	static int mv88e6352_setup_global(struct dsa_switch *ds)
	125	{
	126	int ret;
	127	int i;
	128
	129	/* Discard packets with excessive collisions,
	130	* mask all interrupt sources, enable PPU (bit 14, undocumented).
	131	*/
	132	REG_WRITE(REG_GLOBAL, 0x04, 0x6000);
	133
	134	/* Set the default address aging time to 5 minutes, and
	135	* enable address learn messages to be sent to all message
	136	* ports.
	137	*/
	138	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
	139
	140	/* Configure the priority mapping registers. */
	141	ret = mv88e6xxx_config_prio(ds);
142	if (ret < 0)
143	return ret;
144
145	/* Configure the upstream port, and configure the upstream
146	* port as the port to which ingress and egress monitor frames
147	* are to be sent.
148	*/
149	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
150
151	/* Disable remote management for now, and set the switch's
152	* DSA device number.
153	*/
154	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
155
156	/* Send all frames with destination addresses matching
157	* 01:80:c2:00:00:2x to the CPU port.
158	*/
159	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
160
161	/* Send all frames with destination addresses matching
162	* 01:80:c2:00:00:0x to the CPU port.
163	*/
164	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
165
166	/* Disable the loopback filter, disable flow control
167	* messages, disable flood broadcast override, disable
168	* removing of provider tags, disable ATU age violation
169	* interrupts, disable tag flow control, force flow
170	* control priority to the highest, and send all special
171	* multicast frames to the CPU at the highest priority.
172	*/
173	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
174
175	/* Program the DSA routing table. */
176	for (i = 0; i < 32; i++) {
177	int nexthop = 0x1f;
178
179	if (i != ds->index && i < ds->dst->pd->nr_chips)
180	nexthop = ds->pd->rtable[i] & 0x1f;
181
182	REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 \| (i << 8) \| nexthop);
183	}
184
185	/* Clear all trunk masks. */
186	for (i = 0; i < 8; i++)
187	REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 \| (i << 12) \| 0x7f);
188
189	/* Clear all trunk mappings. */
190	for (i = 0; i < 16; i++)
191	REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 \| (i << 11));
192
193	/* Disable ingress rate limiting by resetting all ingress
194	* rate limit registers to their initial state.
195	*/
196	for (i = 0; i < 7; i++)
197	REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 \| (i << 8));
198
199	/* Initialise cross-chip port VLAN table to reset defaults. */
200	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
201
202	/* Clear the priority override table. */
203	for (i = 0; i < 16; i++)
204	REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 \| (i << 8));
205
206	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
207
208	return 0;
209	}
210
211	static int mv88e6352_setup_port(struct dsa_switch *ds, int p)
212	{
213	int addr = REG_PORT(p);
214	u16 val;
215
216	/* MAC Forcing register: don't force link, speed, duplex
217	* or flow control state to any particular values on physical
218	* ports, but force the CPU port and all DSA ports to 1000 Mb/s
219	* full duplex.
220	*/
221	if (dsa_is_cpu_port(ds, p) \|\| ds->dsa_port_mask & (1 << p))
222	REG_WRITE(addr, 0x01, 0x003e);
223	else
224	REG_WRITE(addr, 0x01, 0x0003);
225
226	/* Do not limit the period of time that this port can be
227	* paused for by the remote end or the period of time that
228	* this port can pause the remote end.
229	*/
230	REG_WRITE(addr, 0x02, 0x0000);
231
232	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
233	* disable Header mode, enable IGMP/MLD snooping, disable VLAN
234	* tunneling, determine priority by looking at 802.1p and IP
235	* priority fields (IP prio has precedence), and set STP state
236	* to Forwarding.
237	*
238	* If this is the CPU link, use DSA or EDSA tagging depending
239	* on which tagging mode was configured.
240	*
241	* If this is a link to another switch, use DSA tagging mode.
242	*
243	* If this is the upstream port for this switch, enable
244	* forwarding of unknown unicasts and multicasts.
245	*/
246	val = 0x0433;
247	if (dsa_is_cpu_port(ds, p)) {
248	if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
249	val \|= 0x3300;
250	else
251	val \|= 0x0100;
252	}
253	if (ds->dsa_port_mask & (1 << p))
254	val \|= 0x0100;
255	if (p == dsa_upstream_port(ds))
256	val \|= 0x000c;
257	REG_WRITE(addr, 0x04, val);
258
259	/* Port Control 1: disable trunking. Also, if this is the
260	* CPU port, enable learn messages to be sent to this port.
261	*/
262	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
263
264	/* Port based VLAN map: give each port its own address
265	* database, allow the CPU port to talk to each of the 'real'
266	* ports, and allow each of the 'real' ports to only talk to
267	* the upstream port.
268	*/
269	val = (p & 0xf) << 12;
270	if (dsa_is_cpu_port(ds, p))
271	val \|= ds->phys_port_mask;
272	else
273	val \|= 1 << dsa_upstream_port(ds);
274	REG_WRITE(addr, 0x06, val);
275
276	/* Default VLAN ID and priority: don't set a default VLAN
277	* ID, and set the default packet priority to zero.
278	*/
279	REG_WRITE(addr, 0x07, 0x0000);
280
281	/* Port Control 2: don't force a good FCS, set the maximum
282	* frame size to 10240 bytes, don't let the switch add or
283	* strip 802.1q tags, don't discard tagged or untagged frames
284	* on this port, do a destination address lookup on all
285	* received packets as usual, disable ARP mirroring and don't
286	* send a copy of all transmitted/received frames on this port
287	* to the CPU.
288	*/
289	REG_WRITE(addr, 0x08, 0x2080);
290
291	/* Egress rate control: disable egress rate control. */
292	REG_WRITE(addr, 0x09, 0x0001);
293
294	/* Egress rate control 2: disable egress rate control. */
295	REG_WRITE(addr, 0x0a, 0x0000);
296
297	/* Port Association Vector: when learning source addresses
298	* of packets, add the address to the address database using
299	* a port bitmap that has only the bit for this port set and
300	* the other bits clear.
301	*/
302	REG_WRITE(addr, 0x0b, 1 << p);
303
304	/* Port ATU control: disable limiting the number of address
305	* database entries that this port is allowed to use.
306	*/
307	REG_WRITE(addr, 0x0c, 0x0000);
308
309	/* Priority Override: disable DA, SA and VTU priority override. */
310	REG_WRITE(addr, 0x0d, 0x0000);
311
312	/* Port Ethertype: use the Ethertype DSA Ethertype value. */
313	REG_WRITE(addr, 0x0f, ETH_P_EDSA);
314
315	/* Tag Remap: use an identity 802.1p prio -> switch prio
316	* mapping.
317	*/
318	REG_WRITE(addr, 0x18, 0x3210);
319
320	/* Tag Remap 2: use an identity 802.1p prio -> switch prio
321	* mapping.
322	*/
323	REG_WRITE(addr, 0x19, 0x7654);
324
325	return 0;
326	}
327
328	static int mv88e6352_setup(struct dsa_switch *ds)
329	{
330	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
331	int ret;
332	int i;
333
334	mutex_init(&ps->smi_mutex);
335	mutex_init(&ps->stats_mutex);
336	mutex_init(&ps->phy_mutex);
337
338	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
339
340	ret = mv88e6352_switch_reset(ds);
341	if (ret < 0)
342	return ret;
343
344	/* @@@ initialise vtu and atu */
345
346	ret = mv88e6352_setup_global(ds);
347	if (ret < 0)
348	return ret;
349
350	for (i = 0; i < 7; i++) {
351	ret = mv88e6352_setup_port(ds, i);
352	if (ret < 0)
353	return ret;
354	}
355
356	return 0;
357	}
358
359	static int mv88e6352_port_to_phy_addr(int port)
360	{
361	if (port >= 0 && port <= 4)
362	return port;
363	return -EINVAL;
364	}
365
366	static int
367	mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum)
368	{
369	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
370	int addr = mv88e6352_port_to_phy_addr(port);
371	int ret;
372
373	if (addr < 0)
374	return addr;
375
376	mutex_lock(&ps->phy_mutex);
377	ret = __mv88e6352_phy_read(ds, addr, regnum);
378	mutex_unlock(&ps->phy_mutex);
379
380	return ret;
381	}
382
383	static int
384	mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
385	{
386	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
387	int addr = mv88e6352_port_to_phy_addr(port);
388	int ret;
389
390	if (addr < 0)
391	return addr;
392
393	mutex_lock(&ps->phy_mutex);
394	ret = __mv88e6352_phy_write(ds, addr, regnum, val);
395	mutex_unlock(&ps->phy_mutex);
396
397	return ret;
398	}
399
400	static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = {
401	{ "in_good_octets", 8, 0x00, },
402	{ "in_bad_octets", 4, 0x02, },
403	{ "in_unicast", 4, 0x04, },
404	{ "in_broadcasts", 4, 0x06, },
405	{ "in_multicasts", 4, 0x07, },
406	{ "in_pause", 4, 0x16, },
407	{ "in_undersize", 4, 0x18, },
408	{ "in_fragments", 4, 0x19, },
409	{ "in_oversize", 4, 0x1a, },
410	{ "in_jabber", 4, 0x1b, },
411	{ "in_rx_error", 4, 0x1c, },
412	{ "in_fcs_error", 4, 0x1d, },
413	{ "out_octets", 8, 0x0e, },
414	{ "out_unicast", 4, 0x10, },
415	{ "out_broadcasts", 4, 0x13, },
416	{ "out_multicasts", 4, 0x12, },
417	{ "out_pause", 4, 0x15, },
418	{ "excessive", 4, 0x11, },
419	{ "collisions", 4, 0x1e, },
420	{ "deferred", 4, 0x05, },
421	{ "single", 4, 0x14, },
422	{ "multiple", 4, 0x17, },
423	{ "out_fcs_error", 4, 0x03, },
424	{ "late", 4, 0x1f, },
425	{ "hist_64bytes", 4, 0x08, },
426	{ "hist_65_127bytes", 4, 0x09, },
427	{ "hist_128_255bytes", 4, 0x0a, },
428	{ "hist_256_511bytes", 4, 0x0b, },
429	{ "hist_512_1023bytes", 4, 0x0c, },
430	{ "hist_1024_max_bytes", 4, 0x0d, },
431	};
432
433	static void
434	mv88e6352_get_strings(struct dsa_switch ds, int port, uint8_t data)
435	{
436	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats),
437	mv88e6352_hw_stats, port, data);
438	}
439
440	static void
441	mv88e6352_get_ethtool_stats(struct dsa_switch ds, int port, uint64_t data)
442	{
443	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats),
444	mv88e6352_hw_stats, port, data);
445	}
446
447	static int mv88e6352_get_sset_count(struct dsa_switch *ds)
448	{
449	return ARRAY_SIZE(mv88e6352_hw_stats);
450	}
451
452	struct dsa_switch_driver mv88e6352_switch_driver = {
453	.tag_protocol = DSA_TAG_PROTO_EDSA,
454	.priv_size = sizeof(struct mv88e6xxx_priv_state),
455	.probe = mv88e6352_probe,
456	.setup = mv88e6352_setup,
457	.set_addr = mv88e6xxx_set_addr_indirect,
458	.phy_read = mv88e6352_phy_read,
459	.phy_write = mv88e6352_phy_write,
460	.poll_link = mv88e6xxx_poll_link,
461	.get_strings = mv88e6352_get_strings,
462	.get_ethtool_stats = mv88e6352_get_ethtool_stats,
463	.get_sset_count = mv88e6352_get_sset_count,
464	};
465
466	MODULE_ALIAS("platform:mv88e6352");