[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6352.c

/*
 * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
 *
 * Copyright (c) 2014 Guenter Roeck
 *
 * Derived from mv88e6123_61_65.c
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

static const struct mv88e6xxx_switch_id mv88e6352_table[] = {
	{ PORT_SWITCH_ID_6172, "Marvell 88E6172" },
	{ PORT_SWITCH_ID_6176, "Marvell 88E6176" },
	{ PORT_SWITCH_ID_6320, "Marvell 88E6320" },
	{ PORT_SWITCH_ID_6320_A1, "Marvell 88E6320 (A1)" },
	{ PORT_SWITCH_ID_6320_A2, "Marvell 88e6320 (A2)" },
	{ PORT_SWITCH_ID_6321, "Marvell 88E6321" },
	{ PORT_SWITCH_ID_6321_A1, "Marvell 88E6321 (A1)" },
	{ PORT_SWITCH_ID_6321_A2, "Marvell 88e6321 (A2)" },
	{ PORT_SWITCH_ID_6352, "Marvell 88E6352" },
	{ PORT_SWITCH_ID_6352_A0, "Marvell 88E6352 (A0)" },
	{ PORT_SWITCH_ID_6352_A1, "Marvell 88E6352 (A1)" },
};

static char *mv88e6352_probe(struct device *host_dev, int sw_addr)
{
	return mv88e6xxx_lookup_name(host_dev, sw_addr, mv88e6352_table,
				     ARRAY_SIZE(mv88e6352_table));
}

static int mv88e6352_setup_global(struct dsa_switch *ds)
{
	u32 upstream_port = dsa_upstream_port(ds);
	int ret;
	u32 reg;

	ret = mv88e6xxx_setup_global(ds);
	if (ret)
		return ret;

	/* Discard packets with excessive collisions,
	 * mask all interrupt sources, enable PPU (bit 14, undocumented).
	 */
	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
		  GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_DISCARD_EXCESS);

	/* Configure the upstream port, and configure the upstream
	 * port as the port to which ingress and egress monitor frames
	 * are to be sent.
	 */
	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);

	/* Disable remote management for now, and set the switch's
	 * DSA device number.
	 */
	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);

	return 0;
}

static int mv88e6352_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	ret = mv88e6xxx_setup_common(ds);
	if (ret < 0)
		return ret;

	ps->num_ports = 7;

	mutex_init(&ps->eeprom_mutex);

	ret = mv88e6xxx_switch_reset(ds, true);
	if (ret < 0)
		return ret;

	ret = mv88e6352_setup_global(ds);
	if (ret < 0)
		return ret;

	return mv88e6xxx_setup_ports(ds);
}

static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->eeprom_mutex);

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
				  GLOBAL2_EEPROM_OP_READ |
				  (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_eeprom_busy_wait(ds);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
error:
	mutex_unlock(&ps->eeprom_mutex);
	return ret;
}

static int mv88e6352_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
	int offset;
	int len;
	int ret;

	offset = eeprom->offset;
	len = eeprom->len;
	eeprom->len = 0;

	eeprom->magic = 0xc3ec4951;

	ret = mv88e6xxx_eeprom_load_wait(ds);
	if (ret < 0)
		return ret;

	if (offset & 1) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = (word >> 8) & 0xff;

		offset++;
		len--;
		eeprom->len++;
	}

	while (len >= 2) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = word & 0xff;
		*data++ = (word >> 8) & 0xff;

		offset += 2;
		len -= 2;
		eeprom->len += 2;
	}

	if (len) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		*data++ = word & 0xff;

		offset++;
		len--;
		eeprom->len++;
	}

	return 0;
}

static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
{
	int ret;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
	if (ret < 0)
		return ret;

	if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
		return -EROFS;

	return 0;
}

static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
				       u16 data)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->eeprom_mutex);

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
				  GLOBAL2_EEPROM_OP_WRITE |
				  (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_eeprom_busy_wait(ds);
error:
	mutex_unlock(&ps->eeprom_mutex);
	return ret;
}

static int mv88e6352_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
	int offset;
	int ret;
	int len;

	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	ret = mv88e6352_eeprom_is_readonly(ds);
	if (ret)
		return ret;

	offset = eeprom->offset;
	len = eeprom->len;
	eeprom->len = 0;

	ret = mv88e6xxx_eeprom_load_wait(ds);
	if (ret < 0)
		return ret;

	if (offset & 1) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		word = (*data++ << 8) | (word & 0xff);

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset++;
		len--;
		eeprom->len++;
	}

	while (len >= 2) {
		int word;

		word = *data++;
		word |= *data++ << 8;

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset += 2;
		len -= 2;
		eeprom->len += 2;
	}

	if (len) {
		int word;

		word = mv88e6352_read_eeprom_word(ds, offset >> 1);
		if (word < 0)
			return word;

		word = (word & 0xff00) | *data++;

		ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
		if (ret < 0)
			return ret;

		offset++;
		len--;
		eeprom->len++;
	}

	return 0;
}

struct dsa_switch_driver mv88e6352_switch_driver = {
	.tag_protocol		= DSA_TAG_PROTO_EDSA,
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6352_probe,
	.setup			= mv88e6352_setup,
	.set_addr		= mv88e6xxx_set_addr_indirect,
	.phy_read		= mv88e6xxx_phy_read_indirect,
	.phy_write		= mv88e6xxx_phy_write_indirect,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
	.adjust_link		= mv88e6xxx_adjust_link,
	.set_eee		= mv88e6xxx_set_eee,
	.get_eee		= mv88e6xxx_get_eee,
#ifdef CONFIG_NET_DSA_HWMON
	.get_temp		= mv88e6xxx_get_temp,
	.get_temp_limit		= mv88e6xxx_get_temp_limit,
	.set_temp_limit		= mv88e6xxx_set_temp_limit,
	.get_temp_alarm		= mv88e6xxx_get_temp_alarm,
#endif
	.get_eeprom		= mv88e6352_get_eeprom,
	.set_eeprom		= mv88e6352_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
	.port_join_bridge	= mv88e6xxx_port_bridge_join,
	.port_leave_bridge	= mv88e6xxx_port_bridge_leave,
	.port_stp_update	= mv88e6xxx_port_stp_update,
	.port_pvid_get		= mv88e6xxx_port_pvid_get,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.vlan_getnext		= mv88e6xxx_vlan_getnext,
	.port_fdb_prepare	= mv88e6xxx_port_fdb_prepare,
	.port_fdb_add		= mv88e6xxx_port_fdb_add,
	.port_fdb_del		= mv88e6xxx_port_fdb_del,
	.port_fdb_dump		= mv88e6xxx_port_fdb_dump,
};

MODULE_ALIAS("platform:mv88e6172");
MODULE_ALIAS("platform:mv88e6176");
MODULE_ALIAS("platform:mv88e6320");
MODULE_ALIAS("platform:mv88e6321");
MODULE_ALIAS("platform:mv88e6352");
Commit	Line	Data
3ad50cca GR	1	/*
	2	* net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
	3	*
	4	* Copyright (c) 2014 Guenter Roeck
	5	*
	6	* Derived from mv88e6123_61_65.c
	7	* Copyright (c) 2008-2009 Marvell Semiconductor
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/delay.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/netdevice.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/phy.h>
	22	#include <net/dsa.h>
	23	#include "mv88e6xxx.h"
	24
b9b37713 VD	25	static const struct mv88e6xxx_switch_id mv88e6352_table[] = {
	26	{ PORT_SWITCH_ID_6172, "Marvell 88E6172" },
	27	{ PORT_SWITCH_ID_6176, "Marvell 88E6176" },
	28	{ PORT_SWITCH_ID_6320, "Marvell 88E6320" },
	29	{ PORT_SWITCH_ID_6320_A1, "Marvell 88E6320 (A1)" },
	30	{ PORT_SWITCH_ID_6320_A2, "Marvell 88e6320 (A2)" },
	31	{ PORT_SWITCH_ID_6321, "Marvell 88E6321" },
	32	{ PORT_SWITCH_ID_6321_A1, "Marvell 88E6321 (A1)" },
	33	{ PORT_SWITCH_ID_6321_A2, "Marvell 88e6321 (A2)" },
	34	{ PORT_SWITCH_ID_6352, "Marvell 88E6352" },
	35	{ PORT_SWITCH_ID_6352_A0, "Marvell 88E6352 (A0)" },
	36	{ PORT_SWITCH_ID_6352_A1, "Marvell 88E6352 (A1)" },
	37	};
	38
3ad50cca GR	39	static char mv88e6352_probe(struct device host_dev, int sw_addr)
3ad50cca GR	40	{
b9b37713 VD	41	return mv88e6xxx_lookup_name(host_dev, sw_addr, mv88e6352_table,
b9b37713 VD	42	ARRAY_SIZE(mv88e6352_table));
3ad50cca GR	43	}
3ad50cca GR	44
3ad50cca GR	45	static int mv88e6352_setup_global(struct dsa_switch *ds)
3ad50cca GR	46	{
15966a2a	47	u32 upstream_port = dsa_upstream_port(ds);
3ad50cca	48	int ret;
15966a2a	49	u32 reg;
54d792f2 AL	50
	51	ret = mv88e6xxx_setup_global(ds);
	52	if (ret)
	53	return ret;
3ad50cca GR	54
	55	/* Discard packets with excessive collisions,
	56	* mask all interrupt sources, enable PPU (bit 14, undocumented).
	57	*/
15966a2a AL	58	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
15966a2a AL	59	GLOBAL_CONTROL_PPU_ENABLE \| GLOBAL_CONTROL_DISCARD_EXCESS);
3ad50cca	60
3ad50cca GR	61	/* Configure the upstream port, and configure the upstream
	62	* port as the port to which ingress and egress monitor frames
	63	* are to be sent.
	64	*/
15966a2a AL	65	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT \|
	66	upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT \|
	67	upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
	68	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
3ad50cca GR	69
	70	/* Disable remote management for now, and set the switch's
	71	* DSA device number.
	72	*/
	73	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
	74
3ad50cca GR	75	return 0;
	76	}
	77
3ad50cca GR	78	static int mv88e6352_setup(struct dsa_switch *ds)
	79	{
	80	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	81	int ret;
3ad50cca	82
acdaffcc GR	83	ret = mv88e6xxx_setup_common(ds);
	84	if (ret < 0)
	85	return ret;
	86
44e50ddb AL	87	ps->num_ports = 7;
44e50ddb AL	88
33b43df4	89	mutex_init(&ps->eeprom_mutex);
3ad50cca	90
143a8307	91	ret = mv88e6xxx_switch_reset(ds, true);
3ad50cca GR	92	if (ret < 0)
	93	return ret;
	94
3ad50cca GR	95	ret = mv88e6352_setup_global(ds);
	96	if (ret < 0)
	97	return ret;
	98
dbde9e66	99	return mv88e6xxx_setup_ports(ds);
3ad50cca GR	100	}
3ad50cca GR	101
33b43df4 GR	102	static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
	103	{
	104	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	105	int ret;
	106
	107	mutex_lock(&ps->eeprom_mutex);
	108
966bce38 AL	109	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
	110	GLOBAL2_EEPROM_OP_READ \|
	111	(addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
33b43df4 GR	112	if (ret < 0)
	113	goto error;
	114
f3044683	115	ret = mv88e6xxx_eeprom_busy_wait(ds);
33b43df4 GR	116	if (ret < 0)
	117	goto error;
	118
966bce38	119	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
33b43df4 GR	120	error:
	121	mutex_unlock(&ps->eeprom_mutex);
	122	return ret;
	123	}
	124
	125	static int mv88e6352_get_eeprom(struct dsa_switch *ds,
	126	struct ethtool_eeprom eeprom, u8 data)
	127	{
	128	int offset;
	129	int len;
	130	int ret;
	131
	132	offset = eeprom->offset;
	133	len = eeprom->len;
	134	eeprom->len = 0;
	135
	136	eeprom->magic = 0xc3ec4951;
	137
f3044683	138	ret = mv88e6xxx_eeprom_load_wait(ds);
33b43df4 GR	139	if (ret < 0)
	140	return ret;
	141
	142	if (offset & 1) {
	143	int word;
	144
	145	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	146	if (word < 0)
	147	return word;
	148
	149	*data++ = (word >> 8) & 0xff;
	150
	151	offset++;
	152	len--;
	153	eeprom->len++;
	154	}
	155
	156	while (len >= 2) {
	157	int word;
	158
	159	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	160	if (word < 0)
	161	return word;
	162
	163	*data++ = word & 0xff;
	164	*data++ = (word >> 8) & 0xff;
	165
	166	offset += 2;
	167	len -= 2;
	168	eeprom->len += 2;
	169	}
	170
	171	if (len) {
	172	int word;
	173
	174	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	175	if (word < 0)
	176	return word;
	177
	178	*data++ = word & 0xff;
	179
	180	offset++;
	181	len--;
	182	eeprom->len++;
	183	}
	184
	185	return 0;
	186	}
	187
	188	static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
	189	{
	190	int ret;
	191
966bce38	192	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
33b43df4 GR	193	if (ret < 0)
	194	return ret;
	195
966bce38	196	if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
33b43df4 GR	197	return -EROFS;
	198
	199	return 0;
	200	}
	201
	202	static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
	203	u16 data)
	204	{
	205	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	206	int ret;
	207
	208	mutex_lock(&ps->eeprom_mutex);
	209
966bce38	210	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
33b43df4 GR	211	if (ret < 0)
	212	goto error;
	213
966bce38 AL	214	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
	215	GLOBAL2_EEPROM_OP_WRITE \|
	216	(addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
33b43df4 GR	217	if (ret < 0)
	218	goto error;
	219
f3044683	220	ret = mv88e6xxx_eeprom_busy_wait(ds);
33b43df4 GR	221	error:
	222	mutex_unlock(&ps->eeprom_mutex);
	223	return ret;
	224	}
	225
	226	static int mv88e6352_set_eeprom(struct dsa_switch *ds,
	227	struct ethtool_eeprom eeprom, u8 data)
	228	{
	229	int offset;
	230	int ret;
	231	int len;
	232
	233	if (eeprom->magic != 0xc3ec4951)
	234	return -EINVAL;
	235
	236	ret = mv88e6352_eeprom_is_readonly(ds);
	237	if (ret)
	238	return ret;
	239
	240	offset = eeprom->offset;
	241	len = eeprom->len;
	242	eeprom->len = 0;
	243
f3044683	244	ret = mv88e6xxx_eeprom_load_wait(ds);
33b43df4 GR	245	if (ret < 0)
	246	return ret;
	247
	248	if (offset & 1) {
	249	int word;
	250
	251	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	252	if (word < 0)
	253	return word;
	254
	255	word = (*data++ << 8) \| (word & 0xff);
	256
	257	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	258	if (ret < 0)
	259	return ret;
	260
	261	offset++;
	262	len--;
	263	eeprom->len++;
	264	}
	265
	266	while (len >= 2) {
	267	int word;
	268
	269	word = *data++;
	270	word \|= *data++ << 8;
	271
	272	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	273	if (ret < 0)
	274	return ret;
	275
	276	offset += 2;
	277	len -= 2;
	278	eeprom->len += 2;
	279	}
	280
	281	if (len) {
	282	int word;
	283
	284	word = mv88e6352_read_eeprom_word(ds, offset >> 1);
	285	if (word < 0)
	286	return word;
	287
	288	word = (word & 0xff00) \| *data++;
	289
	290	ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
	291	if (ret < 0)
	292	return ret;
	293
	294	offset++;
	295	len--;
	296	eeprom->len++;
	297	}
	298
	299	return 0;
	300	}
	301
3ad50cca GR	302	struct dsa_switch_driver mv88e6352_switch_driver = {
	303	.tag_protocol = DSA_TAG_PROTO_EDSA,
	304	.priv_size = sizeof(struct mv88e6xxx_priv_state),
	305	.probe = mv88e6352_probe,
	306	.setup = mv88e6352_setup,
	307	.set_addr = mv88e6xxx_set_addr_indirect,
fd3a0ee4 AL	308	.phy_read = mv88e6xxx_phy_read_indirect,
fd3a0ee4 AL	309	.phy_write = mv88e6xxx_phy_write_indirect,
e413e7e1 AL	310	.get_strings = mv88e6xxx_get_strings,
	311	.get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
	312	.get_sset_count = mv88e6xxx_get_sset_count,
dea87024	313	.adjust_link = mv88e6xxx_adjust_link,
04b0a80b GR	314	.set_eee = mv88e6xxx_set_eee,
04b0a80b GR	315	.get_eee = mv88e6xxx_get_eee,
276db3b1	316	#ifdef CONFIG_NET_DSA_HWMON
c22995c5 GR	317	.get_temp = mv88e6xxx_get_temp,
	318	.get_temp_limit = mv88e6xxx_get_temp_limit,
	319	.set_temp_limit = mv88e6xxx_set_temp_limit,
	320	.get_temp_alarm = mv88e6xxx_get_temp_alarm,
276db3b1	321	#endif
33b43df4 GR	322	.get_eeprom = mv88e6352_get_eeprom,
33b43df4 GR	323	.set_eeprom = mv88e6352_set_eeprom,
95d08b5a GR	324	.get_regs_len = mv88e6xxx_get_regs_len,
95d08b5a GR	325	.get_regs = mv88e6xxx_get_regs,
e79a8bcb VD	326	.port_join_bridge = mv88e6xxx_port_bridge_join,
e79a8bcb VD	327	.port_leave_bridge = mv88e6xxx_port_bridge_leave,
3f244abb	328	.port_stp_update = mv88e6xxx_port_stp_update,
b8fee957	329	.port_pvid_get = mv88e6xxx_port_pvid_get,
76e398a6	330	.port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
0d3b33e6	331	.port_vlan_add = mv88e6xxx_port_vlan_add,
7dad08d7	332	.port_vlan_del = mv88e6xxx_port_vlan_del,
b8fee957	333	.vlan_getnext = mv88e6xxx_vlan_getnext,
146a3206	334	.port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
2a778e1b VD	335	.port_fdb_add = mv88e6xxx_port_fdb_add,
2a778e1b VD	336	.port_fdb_del = mv88e6xxx_port_fdb_del,
f33475bd	337	.port_fdb_dump = mv88e6xxx_port_fdb_dump,
3ad50cca GR	338	};
3ad50cca GR	339
1636d883	340	MODULE_ALIAS("platform:mv88e6172");
7c3d0d67 AK	341	MODULE_ALIAS("platform:mv88e6176");
	342	MODULE_ALIAS("platform:mv88e6320");
	343	MODULE_ALIAS("platform:mv88e6321");
	344	MODULE_ALIAS("platform:mv88e6352");