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Commit | Line | Data |
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91da11f8 | 1 | /* |
0d3cd4b6 VD |
2 | * Marvell 88e6xxx Ethernet switch single-chip support |
3 | * | |
91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
5 | * | |
14c7b3c3 AL |
6 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
7 | * | |
4333d619 VD |
8 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
9 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> | |
10 | * | |
91da11f8 LB |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
19b2f97e | 17 | #include <linux/delay.h> |
defb05b9 | 18 | #include <linux/etherdevice.h> |
dea87024 | 19 | #include <linux/ethtool.h> |
facd95b2 | 20 | #include <linux/if_bridge.h> |
dc30c35b AL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
23 | #include <linux/irqdomain.h> | |
19b2f97e | 24 | #include <linux/jiffies.h> |
91da11f8 | 25 | #include <linux/list.h> |
14c7b3c3 | 26 | #include <linux/mdio.h> |
2bbba277 | 27 | #include <linux/module.h> |
caac8545 | 28 | #include <linux/of_device.h> |
dc30c35b | 29 | #include <linux/of_irq.h> |
b516d453 | 30 | #include <linux/of_mdio.h> |
91da11f8 | 31 | #include <linux/netdevice.h> |
c8c1b39a | 32 | #include <linux/gpio/consumer.h> |
91da11f8 | 33 | #include <linux/phy.h> |
c8f0b869 | 34 | #include <net/dsa.h> |
ec561276 | 35 | |
4d5f2ba7 | 36 | #include "chip.h" |
a935c052 | 37 | #include "global1.h" |
ec561276 | 38 | #include "global2.h" |
c6fe0ad2 | 39 | #include "hwtstamp.h" |
10fa5bfc | 40 | #include "phy.h" |
18abed21 | 41 | #include "port.h" |
2fa8d3af | 42 | #include "ptp.h" |
6d91782f | 43 | #include "serdes.h" |
91da11f8 | 44 | |
fad09c73 | 45 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
3996a4ff | 46 | { |
fad09c73 VD |
47 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
48 | dev_err(chip->dev, "Switch registers lock not held!\n"); | |
3996a4ff VD |
49 | dump_stack(); |
50 | } | |
51 | } | |
52 | ||
914b32f6 VD |
53 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
54 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). | |
55 | * | |
56 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it | |
57 | * is the only device connected to the SMI master. In this mode it responds to | |
58 | * all 32 possible SMI addresses, and thus maps directly the internal devices. | |
59 | * | |
60 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing | |
61 | * multiple devices to share the SMI interface. In this mode it responds to only | |
62 | * 2 registers, used to indirectly access the internal SMI devices. | |
91da11f8 | 63 | */ |
914b32f6 | 64 | |
fad09c73 | 65 | static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
66 | int addr, int reg, u16 *val) |
67 | { | |
fad09c73 | 68 | if (!chip->smi_ops) |
914b32f6 VD |
69 | return -EOPNOTSUPP; |
70 | ||
fad09c73 | 71 | return chip->smi_ops->read(chip, addr, reg, val); |
914b32f6 VD |
72 | } |
73 | ||
fad09c73 | 74 | static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
75 | int addr, int reg, u16 val) |
76 | { | |
fad09c73 | 77 | if (!chip->smi_ops) |
914b32f6 VD |
78 | return -EOPNOTSUPP; |
79 | ||
fad09c73 | 80 | return chip->smi_ops->write(chip, addr, reg, val); |
914b32f6 VD |
81 | } |
82 | ||
fad09c73 | 83 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
84 | int addr, int reg, u16 *val) |
85 | { | |
86 | int ret; | |
87 | ||
fad09c73 | 88 | ret = mdiobus_read_nested(chip->bus, addr, reg); |
914b32f6 VD |
89 | if (ret < 0) |
90 | return ret; | |
91 | ||
92 | *val = ret & 0xffff; | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
fad09c73 | 97 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 VD |
98 | int addr, int reg, u16 val) |
99 | { | |
100 | int ret; | |
101 | ||
fad09c73 | 102 | ret = mdiobus_write_nested(chip->bus, addr, reg, val); |
914b32f6 VD |
103 | if (ret < 0) |
104 | return ret; | |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
c08026ab | 109 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { |
914b32f6 VD |
110 | .read = mv88e6xxx_smi_single_chip_read, |
111 | .write = mv88e6xxx_smi_single_chip_write, | |
112 | }; | |
113 | ||
fad09c73 | 114 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) |
91da11f8 LB |
115 | { |
116 | int ret; | |
117 | int i; | |
118 | ||
119 | for (i = 0; i < 16; i++) { | |
fad09c73 | 120 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); |
91da11f8 LB |
121 | if (ret < 0) |
122 | return ret; | |
123 | ||
cca8b133 | 124 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
125 | return 0; |
126 | } | |
127 | ||
128 | return -ETIMEDOUT; | |
129 | } | |
130 | ||
fad09c73 | 131 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, |
914b32f6 | 132 | int addr, int reg, u16 *val) |
91da11f8 LB |
133 | { |
134 | int ret; | |
135 | ||
3675c8d7 | 136 | /* Wait for the bus to become free. */ |
fad09c73 | 137 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
138 | if (ret < 0) |
139 | return ret; | |
140 | ||
3675c8d7 | 141 | /* Transmit the read command. */ |
fad09c73 | 142 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 143 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
91da11f8 LB |
144 | if (ret < 0) |
145 | return ret; | |
146 | ||
3675c8d7 | 147 | /* Wait for the read command to complete. */ |
fad09c73 | 148 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
149 | if (ret < 0) |
150 | return ret; | |
151 | ||
3675c8d7 | 152 | /* Read the data. */ |
fad09c73 | 153 | ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); |
bb92ea5e VD |
154 | if (ret < 0) |
155 | return ret; | |
156 | ||
914b32f6 | 157 | *val = ret & 0xffff; |
91da11f8 | 158 | |
914b32f6 | 159 | return 0; |
8d6d09e7 GR |
160 | } |
161 | ||
fad09c73 | 162 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, |
914b32f6 | 163 | int addr, int reg, u16 val) |
91da11f8 LB |
164 | { |
165 | int ret; | |
166 | ||
3675c8d7 | 167 | /* Wait for the bus to become free. */ |
fad09c73 | 168 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
169 | if (ret < 0) |
170 | return ret; | |
171 | ||
3675c8d7 | 172 | /* Transmit the data to write. */ |
fad09c73 | 173 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); |
91da11f8 LB |
174 | if (ret < 0) |
175 | return ret; | |
176 | ||
3675c8d7 | 177 | /* Transmit the write command. */ |
fad09c73 | 178 | ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, |
6e899e6c | 179 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
91da11f8 LB |
180 | if (ret < 0) |
181 | return ret; | |
182 | ||
3675c8d7 | 183 | /* Wait for the write command to complete. */ |
fad09c73 | 184 | ret = mv88e6xxx_smi_multi_chip_wait(chip); |
91da11f8 LB |
185 | if (ret < 0) |
186 | return ret; | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
c08026ab | 191 | static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { |
914b32f6 VD |
192 | .read = mv88e6xxx_smi_multi_chip_read, |
193 | .write = mv88e6xxx_smi_multi_chip_write, | |
194 | }; | |
195 | ||
ec561276 | 196 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
914b32f6 VD |
197 | { |
198 | int err; | |
199 | ||
fad09c73 | 200 | assert_reg_lock(chip); |
914b32f6 | 201 | |
fad09c73 | 202 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
914b32f6 VD |
203 | if (err) |
204 | return err; | |
205 | ||
fad09c73 | 206 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
914b32f6 VD |
207 | addr, reg, *val); |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
ec561276 | 212 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
91da11f8 | 213 | { |
914b32f6 VD |
214 | int err; |
215 | ||
fad09c73 | 216 | assert_reg_lock(chip); |
91da11f8 | 217 | |
fad09c73 | 218 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
914b32f6 VD |
219 | if (err) |
220 | return err; | |
221 | ||
fad09c73 | 222 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
bb92ea5e VD |
223 | addr, reg, val); |
224 | ||
914b32f6 VD |
225 | return 0; |
226 | } | |
227 | ||
10fa5bfc | 228 | struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) |
a3c53be5 AL |
229 | { |
230 | struct mv88e6xxx_mdio_bus *mdio_bus; | |
231 | ||
232 | mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, | |
233 | list); | |
234 | if (!mdio_bus) | |
235 | return NULL; | |
236 | ||
237 | return mdio_bus->bus; | |
238 | } | |
239 | ||
dc30c35b AL |
240 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
241 | { | |
242 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
243 | unsigned int n = d->hwirq; | |
244 | ||
245 | chip->g1_irq.masked |= (1 << n); | |
246 | } | |
247 | ||
248 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) | |
249 | { | |
250 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
251 | unsigned int n = d->hwirq; | |
252 | ||
253 | chip->g1_irq.masked &= ~(1 << n); | |
254 | } | |
255 | ||
294d711e | 256 | static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) |
dc30c35b | 257 | { |
dc30c35b AL |
258 | unsigned int nhandled = 0; |
259 | unsigned int sub_irq; | |
260 | unsigned int n; | |
261 | u16 reg; | |
262 | int err; | |
263 | ||
264 | mutex_lock(&chip->reg_lock); | |
82466921 | 265 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
dc30c35b AL |
266 | mutex_unlock(&chip->reg_lock); |
267 | ||
268 | if (err) | |
269 | goto out; | |
270 | ||
271 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { | |
272 | if (reg & (1 << n)) { | |
273 | sub_irq = irq_find_mapping(chip->g1_irq.domain, n); | |
274 | handle_nested_irq(sub_irq); | |
275 | ++nhandled; | |
276 | } | |
277 | } | |
278 | out: | |
279 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); | |
280 | } | |
281 | ||
294d711e AL |
282 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) |
283 | { | |
284 | struct mv88e6xxx_chip *chip = dev_id; | |
285 | ||
286 | return mv88e6xxx_g1_irq_thread_work(chip); | |
287 | } | |
288 | ||
dc30c35b AL |
289 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) |
290 | { | |
291 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
292 | ||
293 | mutex_lock(&chip->reg_lock); | |
294 | } | |
295 | ||
296 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) | |
297 | { | |
298 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
299 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); | |
300 | u16 reg; | |
301 | int err; | |
302 | ||
d77f4321 | 303 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); |
dc30c35b AL |
304 | if (err) |
305 | goto out; | |
306 | ||
307 | reg &= ~mask; | |
308 | reg |= (~chip->g1_irq.masked & mask); | |
309 | ||
d77f4321 | 310 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); |
dc30c35b AL |
311 | if (err) |
312 | goto out; | |
313 | ||
314 | out: | |
315 | mutex_unlock(&chip->reg_lock); | |
316 | } | |
317 | ||
6eb15e21 | 318 | static const struct irq_chip mv88e6xxx_g1_irq_chip = { |
dc30c35b AL |
319 | .name = "mv88e6xxx-g1", |
320 | .irq_mask = mv88e6xxx_g1_irq_mask, | |
321 | .irq_unmask = mv88e6xxx_g1_irq_unmask, | |
322 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, | |
323 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, | |
324 | }; | |
325 | ||
326 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, | |
327 | unsigned int irq, | |
328 | irq_hw_number_t hwirq) | |
329 | { | |
330 | struct mv88e6xxx_chip *chip = d->host_data; | |
331 | ||
332 | irq_set_chip_data(irq, d->host_data); | |
333 | irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); | |
334 | irq_set_noprobe(irq); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { | |
340 | .map = mv88e6xxx_g1_irq_domain_map, | |
341 | .xlate = irq_domain_xlate_twocell, | |
342 | }; | |
343 | ||
294d711e | 344 | static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) |
dc30c35b AL |
345 | { |
346 | int irq, virq; | |
3460a577 AL |
347 | u16 mask; |
348 | ||
d77f4321 | 349 | mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); |
3d5fdba1 | 350 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
d77f4321 | 351 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
3460a577 | 352 | |
5edef2f2 | 353 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { |
a3db3d3a | 354 | virq = irq_find_mapping(chip->g1_irq.domain, irq); |
dc30c35b AL |
355 | irq_dispose_mapping(virq); |
356 | } | |
357 | ||
a3db3d3a | 358 | irq_domain_remove(chip->g1_irq.domain); |
dc30c35b AL |
359 | } |
360 | ||
294d711e AL |
361 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) |
362 | { | |
b19e5c15 | 363 | mv88e6xxx_g1_irq_free_common(chip); |
294d711e AL |
364 | |
365 | free_irq(chip->irq, chip); | |
366 | } | |
367 | ||
368 | static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) | |
dc30c35b | 369 | { |
3dd0ef05 AL |
370 | int err, irq, virq; |
371 | u16 reg, mask; | |
dc30c35b AL |
372 | |
373 | chip->g1_irq.nirqs = chip->info->g1_irqs; | |
374 | chip->g1_irq.domain = irq_domain_add_simple( | |
375 | NULL, chip->g1_irq.nirqs, 0, | |
376 | &mv88e6xxx_g1_irq_domain_ops, chip); | |
377 | if (!chip->g1_irq.domain) | |
378 | return -ENOMEM; | |
379 | ||
380 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) | |
381 | irq_create_mapping(chip->g1_irq.domain, irq); | |
382 | ||
383 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; | |
384 | chip->g1_irq.masked = ~0; | |
385 | ||
d77f4321 | 386 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); |
dc30c35b | 387 | if (err) |
3dd0ef05 | 388 | goto out_mapping; |
dc30c35b | 389 | |
3dd0ef05 | 390 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
dc30c35b | 391 | |
d77f4321 | 392 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
dc30c35b | 393 | if (err) |
3dd0ef05 | 394 | goto out_disable; |
dc30c35b AL |
395 | |
396 | /* Reading the interrupt status clears (most of) them */ | |
82466921 | 397 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
dc30c35b | 398 | if (err) |
3dd0ef05 | 399 | goto out_disable; |
dc30c35b | 400 | |
dc30c35b AL |
401 | return 0; |
402 | ||
3dd0ef05 | 403 | out_disable: |
3d5fdba1 | 404 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
d77f4321 | 405 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
3dd0ef05 AL |
406 | |
407 | out_mapping: | |
408 | for (irq = 0; irq < 16; irq++) { | |
409 | virq = irq_find_mapping(chip->g1_irq.domain, irq); | |
410 | irq_dispose_mapping(virq); | |
411 | } | |
412 | ||
413 | irq_domain_remove(chip->g1_irq.domain); | |
dc30c35b AL |
414 | |
415 | return err; | |
416 | } | |
417 | ||
294d711e AL |
418 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) |
419 | { | |
420 | int err; | |
421 | ||
422 | err = mv88e6xxx_g1_irq_setup_common(chip); | |
423 | if (err) | |
424 | return err; | |
425 | ||
426 | err = request_threaded_irq(chip->irq, NULL, | |
427 | mv88e6xxx_g1_irq_thread_fn, | |
428 | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, | |
429 | dev_name(chip->dev), chip); | |
430 | if (err) | |
431 | mv88e6xxx_g1_irq_free_common(chip); | |
432 | ||
433 | return err; | |
434 | } | |
435 | ||
436 | static void mv88e6xxx_irq_poll(struct kthread_work *work) | |
437 | { | |
438 | struct mv88e6xxx_chip *chip = container_of(work, | |
439 | struct mv88e6xxx_chip, | |
440 | irq_poll_work.work); | |
441 | mv88e6xxx_g1_irq_thread_work(chip); | |
442 | ||
443 | kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, | |
444 | msecs_to_jiffies(100)); | |
445 | } | |
446 | ||
447 | static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) | |
448 | { | |
449 | int err; | |
450 | ||
451 | err = mv88e6xxx_g1_irq_setup_common(chip); | |
452 | if (err) | |
453 | return err; | |
454 | ||
455 | kthread_init_delayed_work(&chip->irq_poll_work, | |
456 | mv88e6xxx_irq_poll); | |
457 | ||
458 | chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); | |
459 | if (IS_ERR(chip->kworker)) | |
460 | return PTR_ERR(chip->kworker); | |
461 | ||
462 | kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, | |
463 | msecs_to_jiffies(100)); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
468 | static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) | |
469 | { | |
470 | kthread_cancel_delayed_work_sync(&chip->irq_poll_work); | |
471 | kthread_destroy_worker(chip->kworker); | |
472 | } | |
473 | ||
ec561276 | 474 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) |
2d79af6e | 475 | { |
6441e669 | 476 | int i; |
2d79af6e | 477 | |
6441e669 | 478 | for (i = 0; i < 16; i++) { |
2d79af6e VD |
479 | u16 val; |
480 | int err; | |
481 | ||
482 | err = mv88e6xxx_read(chip, addr, reg, &val); | |
483 | if (err) | |
484 | return err; | |
485 | ||
486 | if (!(val & mask)) | |
487 | return 0; | |
488 | ||
489 | usleep_range(1000, 2000); | |
490 | } | |
491 | ||
30853553 | 492 | dev_err(chip->dev, "Timeout while waiting for switch\n"); |
2d79af6e VD |
493 | return -ETIMEDOUT; |
494 | } | |
495 | ||
f22ab641 | 496 | /* Indirect write to single pointer-data register with an Update bit */ |
ec561276 | 497 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) |
f22ab641 VD |
498 | { |
499 | u16 val; | |
0f02b4f7 | 500 | int err; |
f22ab641 VD |
501 | |
502 | /* Wait until the previous operation is completed */ | |
0f02b4f7 AL |
503 | err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); |
504 | if (err) | |
505 | return err; | |
f22ab641 VD |
506 | |
507 | /* Set the Update bit to trigger a write operation */ | |
508 | val = BIT(15) | update; | |
509 | ||
510 | return mv88e6xxx_write(chip, addr, reg, val); | |
511 | } | |
512 | ||
d78343d2 VD |
513 | static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, |
514 | int link, int speed, int duplex, | |
515 | phy_interface_t mode) | |
516 | { | |
517 | int err; | |
518 | ||
519 | if (!chip->info->ops->port_set_link) | |
520 | return 0; | |
521 | ||
522 | /* Port's MAC control must not be changed unless the link is down */ | |
523 | err = chip->info->ops->port_set_link(chip, port, 0); | |
524 | if (err) | |
525 | return err; | |
526 | ||
527 | if (chip->info->ops->port_set_speed) { | |
528 | err = chip->info->ops->port_set_speed(chip, port, speed); | |
529 | if (err && err != -EOPNOTSUPP) | |
530 | goto restore_link; | |
531 | } | |
532 | ||
533 | if (chip->info->ops->port_set_duplex) { | |
534 | err = chip->info->ops->port_set_duplex(chip, port, duplex); | |
535 | if (err && err != -EOPNOTSUPP) | |
536 | goto restore_link; | |
537 | } | |
538 | ||
539 | if (chip->info->ops->port_set_rgmii_delay) { | |
540 | err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); | |
541 | if (err && err != -EOPNOTSUPP) | |
542 | goto restore_link; | |
543 | } | |
544 | ||
f39908d3 AL |
545 | if (chip->info->ops->port_set_cmode) { |
546 | err = chip->info->ops->port_set_cmode(chip, port, mode); | |
547 | if (err && err != -EOPNOTSUPP) | |
548 | goto restore_link; | |
549 | } | |
550 | ||
d78343d2 VD |
551 | err = 0; |
552 | restore_link: | |
553 | if (chip->info->ops->port_set_link(chip, port, link)) | |
774439e5 | 554 | dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); |
d78343d2 VD |
555 | |
556 | return err; | |
557 | } | |
558 | ||
dea87024 AL |
559 | /* We expect the switch to perform auto negotiation if there is a real |
560 | * phy. However, in the case of a fixed link phy, we force the port | |
561 | * settings from the fixed link settings. | |
562 | */ | |
f81ec90f VD |
563 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
564 | struct phy_device *phydev) | |
dea87024 | 565 | { |
04bed143 | 566 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 | 567 | int err; |
dea87024 AL |
568 | |
569 | if (!phy_is_pseudo_fixed_link(phydev)) | |
570 | return; | |
571 | ||
fad09c73 | 572 | mutex_lock(&chip->reg_lock); |
d78343d2 VD |
573 | err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, |
574 | phydev->duplex, phydev->interface); | |
fad09c73 | 575 | mutex_unlock(&chip->reg_lock); |
d78343d2 VD |
576 | |
577 | if (err && err != -EOPNOTSUPP) | |
774439e5 | 578 | dev_err(ds->dev, "p%d: failed to configure MAC\n", port); |
dea87024 AL |
579 | } |
580 | ||
a605a0fe | 581 | static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
91da11f8 | 582 | { |
a605a0fe AL |
583 | if (!chip->info->ops->stats_snapshot) |
584 | return -EOPNOTSUPP; | |
91da11f8 | 585 | |
a605a0fe | 586 | return chip->info->ops->stats_snapshot(chip, port); |
91da11f8 LB |
587 | } |
588 | ||
e413e7e1 | 589 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
dfafe449 AL |
590 | { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, |
591 | { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, | |
592 | { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, | |
593 | { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, | |
594 | { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, | |
595 | { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, | |
596 | { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, | |
597 | { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, | |
598 | { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, | |
599 | { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, | |
600 | { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, | |
601 | { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, | |
602 | { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, | |
603 | { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, | |
604 | { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, | |
605 | { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, | |
606 | { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, | |
607 | { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, | |
608 | { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, | |
609 | { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, | |
610 | { "single", 4, 0x14, STATS_TYPE_BANK0, }, | |
611 | { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, | |
612 | { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, | |
613 | { "late", 4, 0x1f, STATS_TYPE_BANK0, }, | |
614 | { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, | |
615 | { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, | |
616 | { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, | |
617 | { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, | |
618 | { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, | |
619 | { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, | |
620 | { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, | |
621 | { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, | |
622 | { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, | |
623 | { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, | |
624 | { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, | |
625 | { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, | |
626 | { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, | |
627 | { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, | |
628 | { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, | |
629 | { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, | |
630 | { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, | |
631 | { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, | |
632 | { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, | |
633 | { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, | |
634 | { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, | |
635 | { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, | |
636 | { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, | |
637 | { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, | |
638 | { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, | |
639 | { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, | |
640 | { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, | |
641 | { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, | |
642 | { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, | |
643 | { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, | |
644 | { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, | |
645 | { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, | |
646 | { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, | |
647 | { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, | |
648 | { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, | |
e413e7e1 AL |
649 | }; |
650 | ||
fad09c73 | 651 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 652 | struct mv88e6xxx_hw_stat *s, |
e0d8b615 AL |
653 | int port, u16 bank1_select, |
654 | u16 histogram) | |
80c4627b | 655 | { |
80c4627b AL |
656 | u32 low; |
657 | u32 high = 0; | |
dfafe449 | 658 | u16 reg = 0; |
0e7b9925 | 659 | int err; |
80c4627b AL |
660 | u64 value; |
661 | ||
f5e2ed02 | 662 | switch (s->type) { |
dfafe449 | 663 | case STATS_TYPE_PORT: |
0e7b9925 AL |
664 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
665 | if (err) | |
80c4627b AL |
666 | return UINT64_MAX; |
667 | ||
0e7b9925 | 668 | low = reg; |
cda9f4aa | 669 | if (s->size == 4) { |
0e7b9925 AL |
670 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
671 | if (err) | |
80c4627b | 672 | return UINT64_MAX; |
0e7b9925 | 673 | high = reg; |
80c4627b | 674 | } |
f5e2ed02 | 675 | break; |
dfafe449 | 676 | case STATS_TYPE_BANK1: |
e0d8b615 | 677 | reg = bank1_select; |
dfafe449 AL |
678 | /* fall through */ |
679 | case STATS_TYPE_BANK0: | |
e0d8b615 | 680 | reg |= s->reg | histogram; |
7f9ef3af | 681 | mv88e6xxx_g1_stats_read(chip, reg, &low); |
cda9f4aa | 682 | if (s->size == 8) |
7f9ef3af | 683 | mv88e6xxx_g1_stats_read(chip, reg + 1, &high); |
9fc3e4dc GS |
684 | break; |
685 | default: | |
686 | return UINT64_MAX; | |
80c4627b AL |
687 | } |
688 | value = (((u64)high) << 16) | low; | |
689 | return value; | |
690 | } | |
691 | ||
436fe17d AL |
692 | static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, |
693 | uint8_t *data, int types) | |
91da11f8 | 694 | { |
f5e2ed02 AL |
695 | struct mv88e6xxx_hw_stat *stat; |
696 | int i, j; | |
91da11f8 | 697 | |
f5e2ed02 AL |
698 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
699 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 700 | if (stat->type & types) { |
f5e2ed02 AL |
701 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
702 | ETH_GSTRING_LEN); | |
703 | j++; | |
704 | } | |
91da11f8 | 705 | } |
436fe17d AL |
706 | |
707 | return j; | |
e413e7e1 AL |
708 | } |
709 | ||
436fe17d AL |
710 | static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, |
711 | uint8_t *data) | |
dfafe449 | 712 | { |
436fe17d AL |
713 | return mv88e6xxx_stats_get_strings(chip, data, |
714 | STATS_TYPE_BANK0 | STATS_TYPE_PORT); | |
dfafe449 AL |
715 | } |
716 | ||
436fe17d AL |
717 | static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, |
718 | uint8_t *data) | |
dfafe449 | 719 | { |
436fe17d AL |
720 | return mv88e6xxx_stats_get_strings(chip, data, |
721 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1); | |
dfafe449 AL |
722 | } |
723 | ||
724 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, | |
725 | uint8_t *data) | |
e413e7e1 | 726 | { |
04bed143 | 727 | struct mv88e6xxx_chip *chip = ds->priv; |
436fe17d | 728 | int count = 0; |
dfafe449 | 729 | |
c6c8cd5e AL |
730 | mutex_lock(&chip->reg_lock); |
731 | ||
dfafe449 | 732 | if (chip->info->ops->stats_get_strings) |
436fe17d AL |
733 | count = chip->info->ops->stats_get_strings(chip, data); |
734 | ||
735 | if (chip->info->ops->serdes_get_strings) { | |
736 | data += count * ETH_GSTRING_LEN; | |
737 | chip->info->ops->serdes_get_strings(chip, port, data); | |
738 | } | |
c6c8cd5e AL |
739 | |
740 | mutex_unlock(&chip->reg_lock); | |
dfafe449 AL |
741 | } |
742 | ||
743 | static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, | |
744 | int types) | |
745 | { | |
f5e2ed02 AL |
746 | struct mv88e6xxx_hw_stat *stat; |
747 | int i, j; | |
748 | ||
749 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
750 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 751 | if (stat->type & types) |
f5e2ed02 AL |
752 | j++; |
753 | } | |
754 | return j; | |
e413e7e1 AL |
755 | } |
756 | ||
dfafe449 AL |
757 | static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
758 | { | |
759 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
760 | STATS_TYPE_PORT); | |
761 | } | |
762 | ||
763 | static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) | |
764 | { | |
765 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
766 | STATS_TYPE_BANK1); | |
767 | } | |
768 | ||
88c06054 | 769 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port) |
dfafe449 AL |
770 | { |
771 | struct mv88e6xxx_chip *chip = ds->priv; | |
436fe17d AL |
772 | int serdes_count = 0; |
773 | int count = 0; | |
dfafe449 | 774 | |
c6c8cd5e | 775 | mutex_lock(&chip->reg_lock); |
dfafe449 | 776 | if (chip->info->ops->stats_get_sset_count) |
436fe17d AL |
777 | count = chip->info->ops->stats_get_sset_count(chip); |
778 | if (count < 0) | |
779 | goto out; | |
780 | ||
781 | if (chip->info->ops->serdes_get_sset_count) | |
782 | serdes_count = chip->info->ops->serdes_get_sset_count(chip, | |
783 | port); | |
784 | if (serdes_count < 0) | |
785 | count = serdes_count; | |
786 | else | |
787 | count += serdes_count; | |
788 | out: | |
c6c8cd5e | 789 | mutex_unlock(&chip->reg_lock); |
dfafe449 | 790 | |
436fe17d | 791 | return count; |
dfafe449 AL |
792 | } |
793 | ||
436fe17d AL |
794 | static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
795 | uint64_t *data, int types, | |
796 | u16 bank1_select, u16 histogram) | |
052f947f AL |
797 | { |
798 | struct mv88e6xxx_hw_stat *stat; | |
799 | int i, j; | |
800 | ||
801 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
802 | stat = &mv88e6xxx_hw_stats[i]; | |
803 | if (stat->type & types) { | |
377cda13 | 804 | mutex_lock(&chip->reg_lock); |
e0d8b615 AL |
805 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, |
806 | bank1_select, | |
807 | histogram); | |
377cda13 AL |
808 | mutex_unlock(&chip->reg_lock); |
809 | ||
052f947f AL |
810 | j++; |
811 | } | |
812 | } | |
436fe17d | 813 | return j; |
052f947f AL |
814 | } |
815 | ||
436fe17d AL |
816 | static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
817 | uint64_t *data) | |
052f947f AL |
818 | { |
819 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 | 820 | STATS_TYPE_BANK0 | STATS_TYPE_PORT, |
57d1ef38 | 821 | 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); |
052f947f AL |
822 | } |
823 | ||
436fe17d AL |
824 | static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
825 | uint64_t *data) | |
052f947f AL |
826 | { |
827 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 | 828 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, |
57d1ef38 VD |
829 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, |
830 | MV88E6XXX_G1_STATS_OP_HIST_RX_TX); | |
e0d8b615 AL |
831 | } |
832 | ||
436fe17d AL |
833 | static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
834 | uint64_t *data) | |
e0d8b615 AL |
835 | { |
836 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
837 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, | |
57d1ef38 VD |
838 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, |
839 | 0); | |
052f947f AL |
840 | } |
841 | ||
842 | static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, | |
843 | uint64_t *data) | |
844 | { | |
436fe17d AL |
845 | int count = 0; |
846 | ||
052f947f | 847 | if (chip->info->ops->stats_get_stats) |
436fe17d AL |
848 | count = chip->info->ops->stats_get_stats(chip, port, data); |
849 | ||
850 | if (chip->info->ops->serdes_get_stats) { | |
851 | data += count; | |
ef44d78d | 852 | mutex_lock(&chip->reg_lock); |
436fe17d | 853 | chip->info->ops->serdes_get_stats(chip, port, data); |
ef44d78d | 854 | mutex_unlock(&chip->reg_lock); |
436fe17d | 855 | } |
052f947f AL |
856 | } |
857 | ||
f81ec90f VD |
858 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
859 | uint64_t *data) | |
e413e7e1 | 860 | { |
04bed143 | 861 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 | 862 | int ret; |
f5e2ed02 | 863 | |
fad09c73 | 864 | mutex_lock(&chip->reg_lock); |
f5e2ed02 | 865 | |
a605a0fe | 866 | ret = mv88e6xxx_stats_snapshot(chip, port); |
377cda13 AL |
867 | mutex_unlock(&chip->reg_lock); |
868 | ||
869 | if (ret < 0) | |
f5e2ed02 | 870 | return; |
052f947f AL |
871 | |
872 | mv88e6xxx_get_stats(chip, port, data); | |
f5e2ed02 | 873 | |
e413e7e1 AL |
874 | } |
875 | ||
de227387 AL |
876 | static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) |
877 | { | |
878 | if (chip->info->ops->stats_set_histogram) | |
879 | return chip->info->ops->stats_set_histogram(chip); | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
f81ec90f | 884 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
a1ab91f3 GR |
885 | { |
886 | return 32 * sizeof(u16); | |
887 | } | |
888 | ||
f81ec90f VD |
889 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
890 | struct ethtool_regs *regs, void *_p) | |
a1ab91f3 | 891 | { |
04bed143 | 892 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 AL |
893 | int err; |
894 | u16 reg; | |
a1ab91f3 GR |
895 | u16 *p = _p; |
896 | int i; | |
897 | ||
898 | regs->version = 0; | |
899 | ||
900 | memset(p, 0xff, 32 * sizeof(u16)); | |
901 | ||
fad09c73 | 902 | mutex_lock(&chip->reg_lock); |
23062513 | 903 | |
a1ab91f3 | 904 | for (i = 0; i < 32; i++) { |
a1ab91f3 | 905 | |
0e7b9925 AL |
906 | err = mv88e6xxx_port_read(chip, port, i, ®); |
907 | if (!err) | |
908 | p[i] = reg; | |
a1ab91f3 | 909 | } |
23062513 | 910 | |
fad09c73 | 911 | mutex_unlock(&chip->reg_lock); |
a1ab91f3 GR |
912 | } |
913 | ||
08f50061 VD |
914 | static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, |
915 | struct ethtool_eee *e) | |
68b8f60c | 916 | { |
5480db69 VD |
917 | /* Nothing to do on the port's MAC */ |
918 | return 0; | |
11b3b45d GR |
919 | } |
920 | ||
08f50061 VD |
921 | static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, |
922 | struct ethtool_eee *e) | |
11b3b45d | 923 | { |
5480db69 VD |
924 | /* Nothing to do on the port's MAC */ |
925 | return 0; | |
11b3b45d GR |
926 | } |
927 | ||
e5887a2a | 928 | static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) |
facd95b2 | 929 | { |
e5887a2a VD |
930 | struct dsa_switch *ds = NULL; |
931 | struct net_device *br; | |
932 | u16 pvlan; | |
b7666efe VD |
933 | int i; |
934 | ||
e5887a2a VD |
935 | if (dev < DSA_MAX_SWITCHES) |
936 | ds = chip->ds->dst->ds[dev]; | |
937 | ||
938 | /* Prevent frames from unknown switch or port */ | |
939 | if (!ds || port >= ds->num_ports) | |
940 | return 0; | |
941 | ||
942 | /* Frames from DSA links and CPU ports can egress any local port */ | |
943 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
944 | return mv88e6xxx_port_mask(chip); | |
945 | ||
946 | br = ds->ports[port].bridge_dev; | |
947 | pvlan = 0; | |
948 | ||
949 | /* Frames from user ports can egress any local DSA links and CPU ports, | |
950 | * as well as any local member of their bridge group. | |
951 | */ | |
952 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) | |
953 | if (dsa_is_cpu_port(chip->ds, i) || | |
954 | dsa_is_dsa_port(chip->ds, i) || | |
c8652c83 | 955 | (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) |
e5887a2a VD |
956 | pvlan |= BIT(i); |
957 | ||
958 | return pvlan; | |
959 | } | |
960 | ||
240ea3ef | 961 | static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) |
e5887a2a VD |
962 | { |
963 | u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); | |
b7666efe VD |
964 | |
965 | /* prevent frames from going back out of the port they came in on */ | |
966 | output_ports &= ~BIT(port); | |
facd95b2 | 967 | |
5a7921f4 | 968 | return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); |
facd95b2 GR |
969 | } |
970 | ||
f81ec90f VD |
971 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
972 | u8 state) | |
facd95b2 | 973 | { |
04bed143 | 974 | struct mv88e6xxx_chip *chip = ds->priv; |
553eb544 | 975 | int err; |
facd95b2 | 976 | |
fad09c73 | 977 | mutex_lock(&chip->reg_lock); |
f894c29c | 978 | err = mv88e6xxx_port_set_state(chip, port, state); |
fad09c73 | 979 | mutex_unlock(&chip->reg_lock); |
553eb544 VD |
980 | |
981 | if (err) | |
774439e5 | 982 | dev_err(ds->dev, "p%d: failed to update state\n", port); |
facd95b2 GR |
983 | } |
984 | ||
9e907d73 VD |
985 | static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) |
986 | { | |
987 | if (chip->info->ops->pot_clear) | |
988 | return chip->info->ops->pot_clear(chip); | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
51c901a7 VD |
993 | static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) |
994 | { | |
995 | if (chip->info->ops->mgmt_rsvd2cpu) | |
996 | return chip->info->ops->mgmt_rsvd2cpu(chip); | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
a2ac29d2 VD |
1001 | static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) |
1002 | { | |
c3a7d4ad VD |
1003 | int err; |
1004 | ||
daefc943 VD |
1005 | err = mv88e6xxx_g1_atu_flush(chip, 0, true); |
1006 | if (err) | |
1007 | return err; | |
1008 | ||
c3a7d4ad VD |
1009 | err = mv88e6xxx_g1_atu_set_learn2all(chip, true); |
1010 | if (err) | |
1011 | return err; | |
1012 | ||
a2ac29d2 VD |
1013 | return mv88e6xxx_g1_atu_set_age_time(chip, 300000); |
1014 | } | |
1015 | ||
cd8da8bb VD |
1016 | static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) |
1017 | { | |
1018 | int port; | |
1019 | int err; | |
1020 | ||
1021 | if (!chip->info->ops->irl_init_all) | |
1022 | return 0; | |
1023 | ||
1024 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { | |
1025 | /* Disable ingress rate limiting by resetting all per port | |
1026 | * ingress rate limit resources to their initial state. | |
1027 | */ | |
1028 | err = chip->info->ops->irl_init_all(chip, port); | |
1029 | if (err) | |
1030 | return err; | |
1031 | } | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
04a69a17 VD |
1036 | static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) |
1037 | { | |
1038 | if (chip->info->ops->set_switch_mac) { | |
1039 | u8 addr[ETH_ALEN]; | |
1040 | ||
1041 | eth_random_addr(addr); | |
1042 | ||
1043 | return chip->info->ops->set_switch_mac(chip, addr); | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
17a1594e VD |
1049 | static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) |
1050 | { | |
1051 | u16 pvlan = 0; | |
1052 | ||
1053 | if (!mv88e6xxx_has_pvt(chip)) | |
1054 | return -EOPNOTSUPP; | |
1055 | ||
1056 | /* Skip the local source device, which uses in-chip port VLAN */ | |
1057 | if (dev != chip->ds->index) | |
aec5ac88 | 1058 | pvlan = mv88e6xxx_port_vlan(chip, dev, port); |
17a1594e VD |
1059 | |
1060 | return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); | |
1061 | } | |
1062 | ||
81228996 VD |
1063 | static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) |
1064 | { | |
17a1594e VD |
1065 | int dev, port; |
1066 | int err; | |
1067 | ||
81228996 VD |
1068 | if (!mv88e6xxx_has_pvt(chip)) |
1069 | return 0; | |
1070 | ||
1071 | /* Clear 5 Bit Port for usage with Marvell Link Street devices: | |
1072 | * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. | |
1073 | */ | |
17a1594e VD |
1074 | err = mv88e6xxx_g2_misc_4_bit_port(chip); |
1075 | if (err) | |
1076 | return err; | |
1077 | ||
1078 | for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { | |
1079 | for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { | |
1080 | err = mv88e6xxx_pvt_map(chip, dev, port); | |
1081 | if (err) | |
1082 | return err; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | return 0; | |
81228996 VD |
1087 | } |
1088 | ||
749efcb8 VD |
1089 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
1090 | { | |
1091 | struct mv88e6xxx_chip *chip = ds->priv; | |
1092 | int err; | |
1093 | ||
1094 | mutex_lock(&chip->reg_lock); | |
e606ca36 | 1095 | err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); |
749efcb8 VD |
1096 | mutex_unlock(&chip->reg_lock); |
1097 | ||
1098 | if (err) | |
774439e5 | 1099 | dev_err(ds->dev, "p%d: failed to flush ATU\n", port); |
749efcb8 VD |
1100 | } |
1101 | ||
b486d7c9 VD |
1102 | static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) |
1103 | { | |
1104 | if (!chip->info->max_vid) | |
1105 | return 0; | |
1106 | ||
1107 | return mv88e6xxx_g1_vtu_flush(chip); | |
1108 | } | |
1109 | ||
f1394b78 VD |
1110 | static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, |
1111 | struct mv88e6xxx_vtu_entry *entry) | |
1112 | { | |
1113 | if (!chip->info->ops->vtu_getnext) | |
1114 | return -EOPNOTSUPP; | |
1115 | ||
1116 | return chip->info->ops->vtu_getnext(chip, entry); | |
1117 | } | |
1118 | ||
0ad5daf6 VD |
1119 | static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
1120 | struct mv88e6xxx_vtu_entry *entry) | |
1121 | { | |
1122 | if (!chip->info->ops->vtu_loadpurge) | |
1123 | return -EOPNOTSUPP; | |
1124 | ||
1125 | return chip->info->ops->vtu_loadpurge(chip, entry); | |
1126 | } | |
1127 | ||
d7f435f9 | 1128 | static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) |
3285f9e8 VD |
1129 | { |
1130 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); | |
3afb4bde VD |
1131 | struct mv88e6xxx_vtu_entry vlan = { |
1132 | .vid = chip->info->max_vid, | |
1133 | }; | |
2db9ce1f | 1134 | int i, err; |
3285f9e8 VD |
1135 | |
1136 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); | |
1137 | ||
2db9ce1f | 1138 | /* Set every FID bit used by the (un)bridged ports */ |
370b4ffb | 1139 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
b4e48c50 | 1140 | err = mv88e6xxx_port_get_fid(chip, i, fid); |
2db9ce1f VD |
1141 | if (err) |
1142 | return err; | |
1143 | ||
1144 | set_bit(*fid, fid_bitmap); | |
1145 | } | |
1146 | ||
3285f9e8 | 1147 | /* Set every FID bit used by the VLAN entries */ |
3285f9e8 | 1148 | do { |
f1394b78 | 1149 | err = mv88e6xxx_vtu_getnext(chip, &vlan); |
3285f9e8 VD |
1150 | if (err) |
1151 | return err; | |
1152 | ||
1153 | if (!vlan.valid) | |
1154 | break; | |
1155 | ||
1156 | set_bit(vlan.fid, fid_bitmap); | |
3cf3c846 | 1157 | } while (vlan.vid < chip->info->max_vid); |
3285f9e8 VD |
1158 | |
1159 | /* The reset value 0x000 is used to indicate that multiple address | |
1160 | * databases are not needed. Return the next positive available. | |
1161 | */ | |
1162 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); | |
fad09c73 | 1163 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
3285f9e8 VD |
1164 | return -ENOSPC; |
1165 | ||
1166 | /* Clear the database */ | |
daefc943 | 1167 | return mv88e6xxx_g1_atu_flush(chip, *fid, true); |
3285f9e8 VD |
1168 | } |
1169 | ||
567aa59a VD |
1170 | static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
1171 | struct mv88e6xxx_vtu_entry *entry, bool new) | |
2fb5ef09 VD |
1172 | { |
1173 | int err; | |
1174 | ||
1175 | if (!vid) | |
1176 | return -EINVAL; | |
1177 | ||
3afb4bde VD |
1178 | entry->vid = vid - 1; |
1179 | entry->valid = false; | |
2fb5ef09 | 1180 | |
f1394b78 | 1181 | err = mv88e6xxx_vtu_getnext(chip, entry); |
2fb5ef09 VD |
1182 | if (err) |
1183 | return err; | |
1184 | ||
567aa59a VD |
1185 | if (entry->vid == vid && entry->valid) |
1186 | return 0; | |
2fb5ef09 | 1187 | |
567aa59a VD |
1188 | if (new) { |
1189 | int i; | |
1190 | ||
1191 | /* Initialize a fresh VLAN entry */ | |
1192 | memset(entry, 0, sizeof(*entry)); | |
1193 | entry->valid = true; | |
1194 | entry->vid = vid; | |
1195 | ||
553a768d | 1196 | /* Exclude all ports */ |
567aa59a | 1197 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
553a768d | 1198 | entry->member[i] = |
7ec60d6e | 1199 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
567aa59a VD |
1200 | |
1201 | return mv88e6xxx_atu_new(chip, &entry->fid); | |
2fb5ef09 VD |
1202 | } |
1203 | ||
567aa59a VD |
1204 | /* switchdev expects -EOPNOTSUPP to honor software VLANs */ |
1205 | return -EOPNOTSUPP; | |
2fb5ef09 VD |
1206 | } |
1207 | ||
da9c359e VD |
1208 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
1209 | u16 vid_begin, u16 vid_end) | |
1210 | { | |
04bed143 | 1211 | struct mv88e6xxx_chip *chip = ds->priv; |
3afb4bde VD |
1212 | struct mv88e6xxx_vtu_entry vlan = { |
1213 | .vid = vid_begin - 1, | |
1214 | }; | |
da9c359e VD |
1215 | int i, err; |
1216 | ||
db06ae41 AL |
1217 | /* DSA and CPU ports have to be members of multiple vlans */ |
1218 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) | |
1219 | return 0; | |
1220 | ||
da9c359e VD |
1221 | if (!vid_begin) |
1222 | return -EOPNOTSUPP; | |
1223 | ||
fad09c73 | 1224 | mutex_lock(&chip->reg_lock); |
da9c359e | 1225 | |
da9c359e | 1226 | do { |
f1394b78 | 1227 | err = mv88e6xxx_vtu_getnext(chip, &vlan); |
da9c359e VD |
1228 | if (err) |
1229 | goto unlock; | |
1230 | ||
1231 | if (!vlan.valid) | |
1232 | break; | |
1233 | ||
1234 | if (vlan.vid > vid_end) | |
1235 | break; | |
1236 | ||
370b4ffb | 1237 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
da9c359e VD |
1238 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
1239 | continue; | |
1240 | ||
cd886469 | 1241 | if (!ds->ports[i].slave) |
66e2809d AL |
1242 | continue; |
1243 | ||
bd00e053 | 1244 | if (vlan.member[i] == |
7ec60d6e | 1245 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
da9c359e VD |
1246 | continue; |
1247 | ||
c8652c83 | 1248 | if (dsa_to_port(ds, i)->bridge_dev == |
fae8a25e | 1249 | ds->ports[port].bridge_dev) |
da9c359e VD |
1250 | break; /* same bridge, check next VLAN */ |
1251 | ||
c8652c83 | 1252 | if (!dsa_to_port(ds, i)->bridge_dev) |
66e2809d AL |
1253 | continue; |
1254 | ||
743fcc28 AL |
1255 | dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", |
1256 | port, vlan.vid, i, | |
c8652c83 | 1257 | netdev_name(dsa_to_port(ds, i)->bridge_dev)); |
da9c359e VD |
1258 | err = -EOPNOTSUPP; |
1259 | goto unlock; | |
1260 | } | |
1261 | } while (vlan.vid < vid_end); | |
1262 | ||
1263 | unlock: | |
fad09c73 | 1264 | mutex_unlock(&chip->reg_lock); |
da9c359e VD |
1265 | |
1266 | return err; | |
1267 | } | |
1268 | ||
f81ec90f VD |
1269 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
1270 | bool vlan_filtering) | |
214cdb99 | 1271 | { |
04bed143 | 1272 | struct mv88e6xxx_chip *chip = ds->priv; |
81c6edb2 VD |
1273 | u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : |
1274 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; | |
0e7b9925 | 1275 | int err; |
214cdb99 | 1276 | |
3cf3c846 | 1277 | if (!chip->info->max_vid) |
54d77b5b VD |
1278 | return -EOPNOTSUPP; |
1279 | ||
fad09c73 | 1280 | mutex_lock(&chip->reg_lock); |
385a0995 | 1281 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
fad09c73 | 1282 | mutex_unlock(&chip->reg_lock); |
214cdb99 | 1283 | |
0e7b9925 | 1284 | return err; |
214cdb99 VD |
1285 | } |
1286 | ||
57d32310 VD |
1287 | static int |
1288 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, | |
80e02360 | 1289 | const struct switchdev_obj_port_vlan *vlan) |
76e398a6 | 1290 | { |
04bed143 | 1291 | struct mv88e6xxx_chip *chip = ds->priv; |
da9c359e VD |
1292 | int err; |
1293 | ||
3cf3c846 | 1294 | if (!chip->info->max_vid) |
54d77b5b VD |
1295 | return -EOPNOTSUPP; |
1296 | ||
da9c359e VD |
1297 | /* If the requested port doesn't belong to the same bridge as the VLAN |
1298 | * members, do not support it (yet) and fallback to software VLAN. | |
1299 | */ | |
1300 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, | |
1301 | vlan->vid_end); | |
1302 | if (err) | |
1303 | return err; | |
1304 | ||
76e398a6 VD |
1305 | /* We don't need any dynamic resource from the kernel (yet), |
1306 | * so skip the prepare phase. | |
1307 | */ | |
1308 | return 0; | |
1309 | } | |
1310 | ||
a4c93ae1 AL |
1311 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
1312 | const unsigned char *addr, u16 vid, | |
1313 | u8 state) | |
1314 | { | |
1315 | struct mv88e6xxx_vtu_entry vlan; | |
1316 | struct mv88e6xxx_atu_entry entry; | |
1317 | int err; | |
1318 | ||
1319 | /* Null VLAN ID corresponds to the port private database */ | |
1320 | if (vid == 0) | |
1321 | err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); | |
1322 | else | |
1323 | err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); | |
1324 | if (err) | |
1325 | return err; | |
1326 | ||
1327 | entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; | |
1328 | ether_addr_copy(entry.mac, addr); | |
1329 | eth_addr_dec(entry.mac); | |
1330 | ||
1331 | err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); | |
1332 | if (err) | |
1333 | return err; | |
1334 | ||
1335 | /* Initialize a fresh ATU entry if it isn't found */ | |
1336 | if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || | |
1337 | !ether_addr_equal(entry.mac, addr)) { | |
1338 | memset(&entry, 0, sizeof(entry)); | |
1339 | ether_addr_copy(entry.mac, addr); | |
1340 | } | |
1341 | ||
1342 | /* Purge the ATU entry only if no port is using it anymore */ | |
1343 | if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { | |
1344 | entry.portvec &= ~BIT(port); | |
1345 | if (!entry.portvec) | |
1346 | entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; | |
1347 | } else { | |
1348 | entry.portvec |= BIT(port); | |
1349 | entry.state = state; | |
1350 | } | |
1351 | ||
1352 | return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); | |
1353 | } | |
1354 | ||
87fa886e AL |
1355 | static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, |
1356 | u16 vid) | |
1357 | { | |
1358 | const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
1359 | u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; | |
1360 | ||
1361 | return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); | |
1362 | } | |
1363 | ||
1364 | static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) | |
1365 | { | |
1366 | int port; | |
1367 | int err; | |
1368 | ||
1369 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { | |
1370 | err = mv88e6xxx_port_add_broadcast(chip, port, vid); | |
1371 | if (err) | |
1372 | return err; | |
1373 | } | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
fad09c73 | 1378 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, |
c91498e1 | 1379 | u16 vid, u8 member) |
0d3b33e6 | 1380 | { |
b4e47c0f | 1381 | struct mv88e6xxx_vtu_entry vlan; |
0d3b33e6 VD |
1382 | int err; |
1383 | ||
567aa59a | 1384 | err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); |
0d3b33e6 | 1385 | if (err) |
76e398a6 | 1386 | return err; |
0d3b33e6 | 1387 | |
c91498e1 | 1388 | vlan.member[port] = member; |
0d3b33e6 | 1389 | |
87fa886e AL |
1390 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); |
1391 | if (err) | |
1392 | return err; | |
1393 | ||
1394 | return mv88e6xxx_broadcast_setup(chip, vid); | |
76e398a6 VD |
1395 | } |
1396 | ||
f81ec90f | 1397 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
80e02360 | 1398 | const struct switchdev_obj_port_vlan *vlan) |
76e398a6 | 1399 | { |
04bed143 | 1400 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1401 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
1402 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
c91498e1 | 1403 | u8 member; |
76e398a6 | 1404 | u16 vid; |
76e398a6 | 1405 | |
3cf3c846 | 1406 | if (!chip->info->max_vid) |
54d77b5b VD |
1407 | return; |
1408 | ||
c91498e1 | 1409 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) |
7ec60d6e | 1410 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; |
c91498e1 | 1411 | else if (untagged) |
7ec60d6e | 1412 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; |
c91498e1 | 1413 | else |
7ec60d6e | 1414 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; |
c91498e1 | 1415 | |
fad09c73 | 1416 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1417 | |
4d5770b3 | 1418 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
c91498e1 | 1419 | if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) |
774439e5 VD |
1420 | dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, |
1421 | vid, untagged ? 'u' : 't'); | |
76e398a6 | 1422 | |
77064f37 | 1423 | if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) |
774439e5 VD |
1424 | dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, |
1425 | vlan->vid_end); | |
0d3b33e6 | 1426 | |
fad09c73 | 1427 | mutex_unlock(&chip->reg_lock); |
0d3b33e6 VD |
1428 | } |
1429 | ||
fad09c73 | 1430 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, |
158bc065 | 1431 | int port, u16 vid) |
7dad08d7 | 1432 | { |
b4e47c0f | 1433 | struct mv88e6xxx_vtu_entry vlan; |
7dad08d7 VD |
1434 | int i, err; |
1435 | ||
567aa59a | 1436 | err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); |
7dad08d7 | 1437 | if (err) |
76e398a6 | 1438 | return err; |
7dad08d7 | 1439 | |
2fb5ef09 | 1440 | /* Tell switchdev if this VLAN is handled in software */ |
7ec60d6e | 1441 | if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
3c06f08b | 1442 | return -EOPNOTSUPP; |
7dad08d7 | 1443 | |
7ec60d6e | 1444 | vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
7dad08d7 VD |
1445 | |
1446 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 1447 | vlan.valid = false; |
370b4ffb | 1448 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
7ec60d6e VD |
1449 | if (vlan.member[i] != |
1450 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 1451 | vlan.valid = true; |
7dad08d7 VD |
1452 | break; |
1453 | } | |
1454 | } | |
1455 | ||
0ad5daf6 | 1456 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
1457 | if (err) |
1458 | return err; | |
1459 | ||
e606ca36 | 1460 | return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); |
76e398a6 VD |
1461 | } |
1462 | ||
f81ec90f VD |
1463 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
1464 | const struct switchdev_obj_port_vlan *vlan) | |
76e398a6 | 1465 | { |
04bed143 | 1466 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
1467 | u16 pvid, vid; |
1468 | int err = 0; | |
1469 | ||
3cf3c846 | 1470 | if (!chip->info->max_vid) |
54d77b5b VD |
1471 | return -EOPNOTSUPP; |
1472 | ||
fad09c73 | 1473 | mutex_lock(&chip->reg_lock); |
76e398a6 | 1474 | |
77064f37 | 1475 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
7dad08d7 VD |
1476 | if (err) |
1477 | goto unlock; | |
1478 | ||
76e398a6 | 1479 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
fad09c73 | 1480 | err = _mv88e6xxx_port_vlan_del(chip, port, vid); |
76e398a6 VD |
1481 | if (err) |
1482 | goto unlock; | |
1483 | ||
1484 | if (vid == pvid) { | |
77064f37 | 1485 | err = mv88e6xxx_port_set_pvid(chip, port, 0); |
76e398a6 VD |
1486 | if (err) |
1487 | goto unlock; | |
1488 | } | |
1489 | } | |
1490 | ||
7dad08d7 | 1491 | unlock: |
fad09c73 | 1492 | mutex_unlock(&chip->reg_lock); |
7dad08d7 VD |
1493 | |
1494 | return err; | |
1495 | } | |
1496 | ||
1b6dd556 AS |
1497 | static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
1498 | const unsigned char *addr, u16 vid) | |
87820510 | 1499 | { |
04bed143 | 1500 | struct mv88e6xxx_chip *chip = ds->priv; |
1b6dd556 | 1501 | int err; |
87820510 | 1502 | |
fad09c73 | 1503 | mutex_lock(&chip->reg_lock); |
1b6dd556 AS |
1504 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, |
1505 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); | |
fad09c73 | 1506 | mutex_unlock(&chip->reg_lock); |
1b6dd556 AS |
1507 | |
1508 | return err; | |
87820510 VD |
1509 | } |
1510 | ||
f81ec90f | 1511 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
6c2c1dcb | 1512 | const unsigned char *addr, u16 vid) |
87820510 | 1513 | { |
04bed143 | 1514 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f | 1515 | int err; |
87820510 | 1516 | |
fad09c73 | 1517 | mutex_lock(&chip->reg_lock); |
6c2c1dcb | 1518 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, |
27c0e600 | 1519 | MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); |
fad09c73 | 1520 | mutex_unlock(&chip->reg_lock); |
87820510 | 1521 | |
83dabd1f | 1522 | return err; |
87820510 VD |
1523 | } |
1524 | ||
83dabd1f VD |
1525 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
1526 | u16 fid, u16 vid, int port, | |
2bedde1a | 1527 | dsa_fdb_dump_cb_t *cb, void *data) |
74b6ba0d | 1528 | { |
dabc1a96 | 1529 | struct mv88e6xxx_atu_entry addr; |
2bedde1a | 1530 | bool is_static; |
74b6ba0d VD |
1531 | int err; |
1532 | ||
27c0e600 | 1533 | addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; |
dabc1a96 | 1534 | eth_broadcast_addr(addr.mac); |
74b6ba0d VD |
1535 | |
1536 | do { | |
a61e5406 | 1537 | mutex_lock(&chip->reg_lock); |
dabc1a96 | 1538 | err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); |
a61e5406 | 1539 | mutex_unlock(&chip->reg_lock); |
74b6ba0d | 1540 | if (err) |
83dabd1f | 1541 | return err; |
74b6ba0d | 1542 | |
27c0e600 | 1543 | if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) |
74b6ba0d VD |
1544 | break; |
1545 | ||
01bd96c8 | 1546 | if (addr.trunk || (addr.portvec & BIT(port)) == 0) |
83dabd1f VD |
1547 | continue; |
1548 | ||
2bedde1a AS |
1549 | if (!is_unicast_ether_addr(addr.mac)) |
1550 | continue; | |
83dabd1f | 1551 | |
2bedde1a AS |
1552 | is_static = (addr.state == |
1553 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); | |
1554 | err = cb(addr.mac, vid, is_static, data); | |
83dabd1f VD |
1555 | if (err) |
1556 | return err; | |
74b6ba0d VD |
1557 | } while (!is_broadcast_ether_addr(addr.mac)); |
1558 | ||
1559 | return err; | |
1560 | } | |
1561 | ||
83dabd1f | 1562 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
2bedde1a | 1563 | dsa_fdb_dump_cb_t *cb, void *data) |
f33475bd | 1564 | { |
b4e47c0f | 1565 | struct mv88e6xxx_vtu_entry vlan = { |
3cf3c846 | 1566 | .vid = chip->info->max_vid, |
f33475bd | 1567 | }; |
2db9ce1f | 1568 | u16 fid; |
f33475bd VD |
1569 | int err; |
1570 | ||
2db9ce1f | 1571 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
a61e5406 | 1572 | mutex_lock(&chip->reg_lock); |
b4e48c50 | 1573 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
a61e5406 AL |
1574 | mutex_unlock(&chip->reg_lock); |
1575 | ||
2db9ce1f | 1576 | if (err) |
83dabd1f | 1577 | return err; |
2db9ce1f | 1578 | |
2bedde1a | 1579 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); |
2db9ce1f | 1580 | if (err) |
83dabd1f | 1581 | return err; |
2db9ce1f | 1582 | |
74b6ba0d | 1583 | /* Dump VLANs' Filtering Information Databases */ |
f33475bd | 1584 | do { |
a61e5406 | 1585 | mutex_lock(&chip->reg_lock); |
f1394b78 | 1586 | err = mv88e6xxx_vtu_getnext(chip, &vlan); |
a61e5406 | 1587 | mutex_unlock(&chip->reg_lock); |
f33475bd | 1588 | if (err) |
83dabd1f | 1589 | return err; |
f33475bd VD |
1590 | |
1591 | if (!vlan.valid) | |
1592 | break; | |
1593 | ||
83dabd1f | 1594 | err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, |
2bedde1a | 1595 | cb, data); |
f33475bd | 1596 | if (err) |
83dabd1f | 1597 | return err; |
3cf3c846 | 1598 | } while (vlan.vid < chip->info->max_vid); |
f33475bd | 1599 | |
83dabd1f VD |
1600 | return err; |
1601 | } | |
1602 | ||
1603 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, | |
2bedde1a | 1604 | dsa_fdb_dump_cb_t *cb, void *data) |
83dabd1f | 1605 | { |
04bed143 | 1606 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f | 1607 | |
a61e5406 | 1608 | return mv88e6xxx_port_db_dump(chip, port, cb, data); |
f33475bd VD |
1609 | } |
1610 | ||
240ea3ef VD |
1611 | static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, |
1612 | struct net_device *br) | |
e79a8bcb | 1613 | { |
e96a6e02 | 1614 | struct dsa_switch *ds; |
240ea3ef | 1615 | int port; |
e96a6e02 | 1616 | int dev; |
240ea3ef | 1617 | int err; |
466dfa07 | 1618 | |
240ea3ef VD |
1619 | /* Remap the Port VLAN of each local bridge group member */ |
1620 | for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { | |
1621 | if (chip->ds->ports[port].bridge_dev == br) { | |
1622 | err = mv88e6xxx_port_vlan_map(chip, port); | |
b7666efe | 1623 | if (err) |
240ea3ef | 1624 | return err; |
b7666efe VD |
1625 | } |
1626 | } | |
1627 | ||
e96a6e02 VD |
1628 | if (!mv88e6xxx_has_pvt(chip)) |
1629 | return 0; | |
1630 | ||
1631 | /* Remap the Port VLAN of each cross-chip bridge group member */ | |
1632 | for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { | |
1633 | ds = chip->ds->dst->ds[dev]; | |
1634 | if (!ds) | |
1635 | break; | |
1636 | ||
1637 | for (port = 0; port < ds->num_ports; ++port) { | |
1638 | if (ds->ports[port].bridge_dev == br) { | |
1639 | err = mv88e6xxx_pvt_map(chip, dev, port); | |
1640 | if (err) | |
1641 | return err; | |
1642 | } | |
1643 | } | |
1644 | } | |
1645 | ||
240ea3ef VD |
1646 | return 0; |
1647 | } | |
1648 | ||
1649 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, | |
1650 | struct net_device *br) | |
1651 | { | |
1652 | struct mv88e6xxx_chip *chip = ds->priv; | |
1653 | int err; | |
1654 | ||
1655 | mutex_lock(&chip->reg_lock); | |
1656 | err = mv88e6xxx_bridge_map(chip, br); | |
fad09c73 | 1657 | mutex_unlock(&chip->reg_lock); |
a6692754 | 1658 | |
466dfa07 | 1659 | return err; |
e79a8bcb VD |
1660 | } |
1661 | ||
f123f2fb VD |
1662 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, |
1663 | struct net_device *br) | |
66d9cd0f | 1664 | { |
04bed143 | 1665 | struct mv88e6xxx_chip *chip = ds->priv; |
466dfa07 | 1666 | |
fad09c73 | 1667 | mutex_lock(&chip->reg_lock); |
240ea3ef VD |
1668 | if (mv88e6xxx_bridge_map(chip, br) || |
1669 | mv88e6xxx_port_vlan_map(chip, port)) | |
1670 | dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); | |
fad09c73 | 1671 | mutex_unlock(&chip->reg_lock); |
66d9cd0f VD |
1672 | } |
1673 | ||
aec5ac88 VD |
1674 | static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, |
1675 | int port, struct net_device *br) | |
1676 | { | |
1677 | struct mv88e6xxx_chip *chip = ds->priv; | |
1678 | int err; | |
1679 | ||
1680 | if (!mv88e6xxx_has_pvt(chip)) | |
1681 | return 0; | |
1682 | ||
1683 | mutex_lock(&chip->reg_lock); | |
1684 | err = mv88e6xxx_pvt_map(chip, dev, port); | |
1685 | mutex_unlock(&chip->reg_lock); | |
1686 | ||
1687 | return err; | |
1688 | } | |
1689 | ||
1690 | static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, | |
1691 | int port, struct net_device *br) | |
1692 | { | |
1693 | struct mv88e6xxx_chip *chip = ds->priv; | |
1694 | ||
1695 | if (!mv88e6xxx_has_pvt(chip)) | |
1696 | return; | |
1697 | ||
1698 | mutex_lock(&chip->reg_lock); | |
1699 | if (mv88e6xxx_pvt_map(chip, dev, port)) | |
1700 | dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); | |
1701 | mutex_unlock(&chip->reg_lock); | |
1702 | } | |
1703 | ||
17e708ba VD |
1704 | static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) |
1705 | { | |
1706 | if (chip->info->ops->reset) | |
1707 | return chip->info->ops->reset(chip); | |
1708 | ||
1709 | return 0; | |
1710 | } | |
1711 | ||
309eca6d VD |
1712 | static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) |
1713 | { | |
1714 | struct gpio_desc *gpiod = chip->reset; | |
1715 | ||
1716 | /* If there is a GPIO connected to the reset pin, toggle it */ | |
1717 | if (gpiod) { | |
1718 | gpiod_set_value_cansleep(gpiod, 1); | |
1719 | usleep_range(10000, 20000); | |
1720 | gpiod_set_value_cansleep(gpiod, 0); | |
1721 | usleep_range(10000, 20000); | |
1722 | } | |
1723 | } | |
1724 | ||
4ac4b5a6 | 1725 | static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) |
552238b5 | 1726 | { |
4ac4b5a6 | 1727 | int i, err; |
552238b5 | 1728 | |
4ac4b5a6 | 1729 | /* Set all ports to the Disabled state */ |
370b4ffb | 1730 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
f894c29c | 1731 | err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); |
0e7b9925 AL |
1732 | if (err) |
1733 | return err; | |
552238b5 VD |
1734 | } |
1735 | ||
4ac4b5a6 VD |
1736 | /* Wait for transmit queues to drain, |
1737 | * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. | |
1738 | */ | |
552238b5 VD |
1739 | usleep_range(2000, 4000); |
1740 | ||
4ac4b5a6 VD |
1741 | return 0; |
1742 | } | |
1743 | ||
1744 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) | |
1745 | { | |
4ac4b5a6 VD |
1746 | int err; |
1747 | ||
1748 | err = mv88e6xxx_disable_ports(chip); | |
1749 | if (err) | |
1750 | return err; | |
1751 | ||
309eca6d | 1752 | mv88e6xxx_hardware_reset(chip); |
552238b5 | 1753 | |
17e708ba | 1754 | return mv88e6xxx_software_reset(chip); |
552238b5 VD |
1755 | } |
1756 | ||
4314557c | 1757 | static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, |
31bef4e9 VD |
1758 | enum mv88e6xxx_frame_mode frame, |
1759 | enum mv88e6xxx_egress_mode egress, u16 etype) | |
56995cbc AL |
1760 | { |
1761 | int err; | |
1762 | ||
4314557c VD |
1763 | if (!chip->info->ops->port_set_frame_mode) |
1764 | return -EOPNOTSUPP; | |
1765 | ||
1766 | err = mv88e6xxx_port_set_egress_mode(chip, port, egress); | |
56995cbc AL |
1767 | if (err) |
1768 | return err; | |
1769 | ||
4314557c VD |
1770 | err = chip->info->ops->port_set_frame_mode(chip, port, frame); |
1771 | if (err) | |
1772 | return err; | |
1773 | ||
1774 | if (chip->info->ops->port_set_ether_type) | |
1775 | return chip->info->ops->port_set_ether_type(chip, port, etype); | |
1776 | ||
1777 | return 0; | |
56995cbc AL |
1778 | } |
1779 | ||
4314557c | 1780 | static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) |
56995cbc | 1781 | { |
4314557c | 1782 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, |
31bef4e9 | 1783 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
b8109594 | 1784 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
4314557c | 1785 | } |
56995cbc | 1786 | |
4314557c VD |
1787 | static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) |
1788 | { | |
1789 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, | |
31bef4e9 | 1790 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
b8109594 | 1791 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
4314557c | 1792 | } |
56995cbc | 1793 | |
4314557c VD |
1794 | static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) |
1795 | { | |
1796 | return mv88e6xxx_set_port_mode(chip, port, | |
1797 | MV88E6XXX_FRAME_MODE_ETHERTYPE, | |
31bef4e9 VD |
1798 | MV88E6XXX_EGRESS_MODE_ETHERTYPE, |
1799 | ETH_P_EDSA); | |
4314557c | 1800 | } |
56995cbc | 1801 | |
4314557c VD |
1802 | static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) |
1803 | { | |
1804 | if (dsa_is_dsa_port(chip->ds, port)) | |
1805 | return mv88e6xxx_set_port_mode_dsa(chip, port); | |
56995cbc | 1806 | |
2b3e9891 | 1807 | if (dsa_is_user_port(chip->ds, port)) |
4314557c | 1808 | return mv88e6xxx_set_port_mode_normal(chip, port); |
56995cbc | 1809 | |
4314557c VD |
1810 | /* Setup CPU port mode depending on its supported tag format */ |
1811 | if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) | |
1812 | return mv88e6xxx_set_port_mode_dsa(chip, port); | |
56995cbc | 1813 | |
4314557c VD |
1814 | if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) |
1815 | return mv88e6xxx_set_port_mode_edsa(chip, port); | |
56995cbc | 1816 | |
4314557c | 1817 | return -EINVAL; |
56995cbc AL |
1818 | } |
1819 | ||
601aeed3 | 1820 | static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) |
56995cbc | 1821 | { |
601aeed3 | 1822 | bool message = dsa_is_dsa_port(chip->ds, port); |
56995cbc | 1823 | |
601aeed3 | 1824 | return mv88e6xxx_port_set_message_port(chip, port, message); |
4314557c | 1825 | } |
56995cbc | 1826 | |
601aeed3 | 1827 | static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) |
4314557c | 1828 | { |
3ee50cbf VD |
1829 | struct dsa_switch *ds = chip->ds; |
1830 | bool flood; | |
56995cbc | 1831 | |
601aeed3 | 1832 | /* Upstream ports flood frames with unknown unicast or multicast DA */ |
3ee50cbf | 1833 | flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); |
601aeed3 VD |
1834 | if (chip->info->ops->port_set_egress_floods) |
1835 | return chip->info->ops->port_set_egress_floods(chip, port, | |
1836 | flood, flood); | |
ea698f4f | 1837 | |
601aeed3 | 1838 | return 0; |
ea698f4f VD |
1839 | } |
1840 | ||
6d91782f AL |
1841 | static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, |
1842 | bool on) | |
1843 | { | |
523a8904 VD |
1844 | if (chip->info->ops->serdes_power) |
1845 | return chip->info->ops->serdes_power(chip, port, on); | |
04aca993 | 1846 | |
523a8904 | 1847 | return 0; |
6d91782f AL |
1848 | } |
1849 | ||
fa371c80 VD |
1850 | static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) |
1851 | { | |
1852 | struct dsa_switch *ds = chip->ds; | |
1853 | int upstream_port; | |
1854 | int err; | |
1855 | ||
07073c79 | 1856 | upstream_port = dsa_upstream_port(ds, port); |
fa371c80 VD |
1857 | if (chip->info->ops->port_set_upstream_port) { |
1858 | err = chip->info->ops->port_set_upstream_port(chip, port, | |
1859 | upstream_port); | |
1860 | if (err) | |
1861 | return err; | |
1862 | } | |
1863 | ||
0ea54dda VD |
1864 | if (port == upstream_port) { |
1865 | if (chip->info->ops->set_cpu_port) { | |
1866 | err = chip->info->ops->set_cpu_port(chip, | |
1867 | upstream_port); | |
1868 | if (err) | |
1869 | return err; | |
1870 | } | |
1871 | ||
1872 | if (chip->info->ops->set_egress_port) { | |
1873 | err = chip->info->ops->set_egress_port(chip, | |
1874 | upstream_port); | |
1875 | if (err) | |
1876 | return err; | |
1877 | } | |
1878 | } | |
1879 | ||
fa371c80 VD |
1880 | return 0; |
1881 | } | |
1882 | ||
fad09c73 | 1883 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
d827e88a | 1884 | { |
fad09c73 | 1885 | struct dsa_switch *ds = chip->ds; |
0e7b9925 | 1886 | int err; |
54d792f2 | 1887 | u16 reg; |
d827e88a | 1888 | |
d78343d2 VD |
1889 | /* MAC Forcing register: don't force link, speed, duplex or flow control |
1890 | * state to any particular values on physical ports, but force the CPU | |
1891 | * port and all DSA ports to their maximum bandwidth and full duplex. | |
1892 | */ | |
1893 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
1894 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, | |
1895 | SPEED_MAX, DUPLEX_FULL, | |
1896 | PHY_INTERFACE_MODE_NA); | |
1897 | else | |
1898 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, | |
1899 | SPEED_UNFORCED, DUPLEX_UNFORCED, | |
1900 | PHY_INTERFACE_MODE_NA); | |
1901 | if (err) | |
1902 | return err; | |
54d792f2 AL |
1903 | |
1904 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1905 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1906 | * tunneling, determine priority by looking at 802.1p and IP | |
1907 | * priority fields (IP prio has precedence), and set STP state | |
1908 | * to Forwarding. | |
1909 | * | |
1910 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1911 | * on which tagging mode was configured. | |
1912 | * | |
1913 | * If this is a link to another switch, use DSA tagging mode. | |
1914 | * | |
1915 | * If this is the upstream port for this switch, enable | |
1916 | * forwarding of unknown unicasts and multicasts. | |
1917 | */ | |
a89b433b VD |
1918 | reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | |
1919 | MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | | |
1920 | MV88E6XXX_PORT_CTL0_STATE_FORWARDING; | |
1921 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); | |
56995cbc AL |
1922 | if (err) |
1923 | return err; | |
6083ce71 | 1924 | |
601aeed3 | 1925 | err = mv88e6xxx_setup_port_mode(chip, port); |
56995cbc AL |
1926 | if (err) |
1927 | return err; | |
54d792f2 | 1928 | |
601aeed3 | 1929 | err = mv88e6xxx_setup_egress_floods(chip, port); |
4314557c VD |
1930 | if (err) |
1931 | return err; | |
1932 | ||
04aca993 AL |
1933 | /* Enable the SERDES interface for DSA and CPU ports. Normal |
1934 | * ports SERDES are enabled when the port is enabled, thus | |
1935 | * saving a bit of power. | |
13a7ebb3 | 1936 | */ |
04aca993 AL |
1937 | if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { |
1938 | err = mv88e6xxx_serdes_power(chip, port, true); | |
1939 | if (err) | |
1940 | return err; | |
1941 | } | |
13a7ebb3 | 1942 | |
8efdda4a | 1943 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
46fbe5e5 | 1944 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
8efdda4a VD |
1945 | * untagged frames on this port, do a destination address lookup on all |
1946 | * received packets as usual, disable ARP mirroring and don't send a | |
1947 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 | 1948 | */ |
a23b2961 AL |
1949 | err = mv88e6xxx_port_set_map_da(chip, port); |
1950 | if (err) | |
1951 | return err; | |
8efdda4a | 1952 | |
fa371c80 VD |
1953 | err = mv88e6xxx_setup_upstream_port(chip, port); |
1954 | if (err) | |
1955 | return err; | |
54d792f2 | 1956 | |
a23b2961 | 1957 | err = mv88e6xxx_port_set_8021q_mode(chip, port, |
81c6edb2 | 1958 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); |
a23b2961 AL |
1959 | if (err) |
1960 | return err; | |
1961 | ||
cd782656 VD |
1962 | if (chip->info->ops->port_set_jumbo_size) { |
1963 | err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); | |
5f436666 AL |
1964 | if (err) |
1965 | return err; | |
1966 | } | |
1967 | ||
54d792f2 AL |
1968 | /* Port Association Vector: when learning source addresses |
1969 | * of packets, add the address to the address database using | |
1970 | * a port bitmap that has only the bit for this port set and | |
1971 | * the other bits clear. | |
1972 | */ | |
4c7ea3c0 | 1973 | reg = 1 << port; |
996ecb82 VD |
1974 | /* Disable learning for CPU port */ |
1975 | if (dsa_is_cpu_port(ds, port)) | |
65fa4027 | 1976 | reg = 0; |
4c7ea3c0 | 1977 | |
2a4614e4 VD |
1978 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, |
1979 | reg); | |
0e7b9925 AL |
1980 | if (err) |
1981 | return err; | |
54d792f2 AL |
1982 | |
1983 | /* Egress rate control 2: disable egress rate control. */ | |
2cb8cb14 VD |
1984 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, |
1985 | 0x0000); | |
0e7b9925 AL |
1986 | if (err) |
1987 | return err; | |
54d792f2 | 1988 | |
0898432c VD |
1989 | if (chip->info->ops->port_pause_limit) { |
1990 | err = chip->info->ops->port_pause_limit(chip, port, 0, 0); | |
0e7b9925 AL |
1991 | if (err) |
1992 | return err; | |
b35d322a | 1993 | } |
54d792f2 | 1994 | |
c8c94891 VD |
1995 | if (chip->info->ops->port_disable_learn_limit) { |
1996 | err = chip->info->ops->port_disable_learn_limit(chip, port); | |
1997 | if (err) | |
1998 | return err; | |
1999 | } | |
2000 | ||
9dbfb4e1 VD |
2001 | if (chip->info->ops->port_disable_pri_override) { |
2002 | err = chip->info->ops->port_disable_pri_override(chip, port); | |
0e7b9925 AL |
2003 | if (err) |
2004 | return err; | |
ef0a7318 | 2005 | } |
2bbb33be | 2006 | |
ef0a7318 AL |
2007 | if (chip->info->ops->port_tag_remap) { |
2008 | err = chip->info->ops->port_tag_remap(chip, port); | |
0e7b9925 AL |
2009 | if (err) |
2010 | return err; | |
54d792f2 AL |
2011 | } |
2012 | ||
ef70b111 AL |
2013 | if (chip->info->ops->port_egress_rate_limiting) { |
2014 | err = chip->info->ops->port_egress_rate_limiting(chip, port); | |
0e7b9925 AL |
2015 | if (err) |
2016 | return err; | |
54d792f2 AL |
2017 | } |
2018 | ||
ea698f4f | 2019 | err = mv88e6xxx_setup_message_port(chip, port); |
0e7b9925 AL |
2020 | if (err) |
2021 | return err; | |
d827e88a | 2022 | |
207afda1 | 2023 | /* Port based VLAN map: give each port the same default address |
b7666efe VD |
2024 | * database, and allow bidirectional communication between the |
2025 | * CPU and DSA port(s), and the other ports. | |
d827e88a | 2026 | */ |
b4e48c50 | 2027 | err = mv88e6xxx_port_set_fid(chip, port, 0); |
0e7b9925 AL |
2028 | if (err) |
2029 | return err; | |
2db9ce1f | 2030 | |
240ea3ef | 2031 | err = mv88e6xxx_port_vlan_map(chip, port); |
0e7b9925 AL |
2032 | if (err) |
2033 | return err; | |
d827e88a GR |
2034 | |
2035 | /* Default VLAN ID and priority: don't set a default VLAN | |
2036 | * ID, and set the default packet priority to zero. | |
2037 | */ | |
b7929fb3 | 2038 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); |
dbde9e66 AL |
2039 | } |
2040 | ||
04aca993 AL |
2041 | static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, |
2042 | struct phy_device *phydev) | |
2043 | { | |
2044 | struct mv88e6xxx_chip *chip = ds->priv; | |
523a8904 | 2045 | int err; |
04aca993 AL |
2046 | |
2047 | mutex_lock(&chip->reg_lock); | |
523a8904 | 2048 | err = mv88e6xxx_serdes_power(chip, port, true); |
04aca993 AL |
2049 | mutex_unlock(&chip->reg_lock); |
2050 | ||
2051 | return err; | |
2052 | } | |
2053 | ||
2054 | static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, | |
2055 | struct phy_device *phydev) | |
2056 | { | |
2057 | struct mv88e6xxx_chip *chip = ds->priv; | |
2058 | ||
2059 | mutex_lock(&chip->reg_lock); | |
523a8904 VD |
2060 | if (mv88e6xxx_serdes_power(chip, port, false)) |
2061 | dev_err(chip->dev, "failed to power off SERDES\n"); | |
04aca993 AL |
2062 | mutex_unlock(&chip->reg_lock); |
2063 | } | |
2064 | ||
2cfcd964 VD |
2065 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
2066 | unsigned int ageing_time) | |
2067 | { | |
04bed143 | 2068 | struct mv88e6xxx_chip *chip = ds->priv; |
2cfcd964 VD |
2069 | int err; |
2070 | ||
2071 | mutex_lock(&chip->reg_lock); | |
720c6343 | 2072 | err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); |
2cfcd964 VD |
2073 | mutex_unlock(&chip->reg_lock); |
2074 | ||
2075 | return err; | |
2076 | } | |
2077 | ||
9729934c | 2078 | static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) |
acdaffcc | 2079 | { |
fad09c73 | 2080 | struct dsa_switch *ds = chip->ds; |
552238b5 | 2081 | int err; |
54d792f2 | 2082 | |
50484ff4 | 2083 | /* Disable remote management, and set the switch's DSA device number. */ |
d77f4321 VD |
2084 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, |
2085 | MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | | |
a935c052 | 2086 | (ds->index & 0x1f)); |
50484ff4 VD |
2087 | if (err) |
2088 | return err; | |
2089 | ||
54d792f2 | 2090 | /* Configure the IP ToS mapping registers. */ |
ccba8f3a | 2091 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); |
48ace4ef | 2092 | if (err) |
08a01261 | 2093 | return err; |
ccba8f3a | 2094 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); |
48ace4ef | 2095 | if (err) |
08a01261 | 2096 | return err; |
ccba8f3a | 2097 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); |
48ace4ef | 2098 | if (err) |
08a01261 | 2099 | return err; |
ccba8f3a | 2100 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); |
48ace4ef | 2101 | if (err) |
08a01261 | 2102 | return err; |
ccba8f3a | 2103 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); |
48ace4ef | 2104 | if (err) |
08a01261 | 2105 | return err; |
ccba8f3a | 2106 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); |
48ace4ef | 2107 | if (err) |
08a01261 | 2108 | return err; |
ccba8f3a | 2109 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); |
48ace4ef | 2110 | if (err) |
08a01261 | 2111 | return err; |
ccba8f3a | 2112 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); |
48ace4ef | 2113 | if (err) |
08a01261 | 2114 | return err; |
54d792f2 AL |
2115 | |
2116 | /* Configure the IEEE 802.1p priority mapping register. */ | |
ccba8f3a | 2117 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); |
48ace4ef | 2118 | if (err) |
08a01261 | 2119 | return err; |
54d792f2 | 2120 | |
de227387 AL |
2121 | /* Initialize the statistics unit */ |
2122 | err = mv88e6xxx_stats_set_histogram(chip); | |
2123 | if (err) | |
2124 | return err; | |
2125 | ||
40cff8fc | 2126 | return mv88e6xxx_g1_stats_clear(chip); |
9729934c VD |
2127 | } |
2128 | ||
f81ec90f | 2129 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
08a01261 | 2130 | { |
04bed143 | 2131 | struct mv88e6xxx_chip *chip = ds->priv; |
08a01261 | 2132 | int err; |
a1a6a4d1 VD |
2133 | int i; |
2134 | ||
fad09c73 | 2135 | chip->ds = ds; |
a3c53be5 | 2136 | ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); |
08a01261 | 2137 | |
fad09c73 | 2138 | mutex_lock(&chip->reg_lock); |
08a01261 | 2139 | |
9729934c | 2140 | /* Setup Switch Port Registers */ |
370b4ffb | 2141 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
91dee144 VD |
2142 | if (dsa_is_unused_port(ds, i)) |
2143 | continue; | |
2144 | ||
9729934c VD |
2145 | err = mv88e6xxx_setup_port(chip, i); |
2146 | if (err) | |
2147 | goto unlock; | |
2148 | } | |
2149 | ||
2150 | /* Setup Switch Global 1 Registers */ | |
2151 | err = mv88e6xxx_g1_setup(chip); | |
a1a6a4d1 VD |
2152 | if (err) |
2153 | goto unlock; | |
2154 | ||
9729934c | 2155 | /* Setup Switch Global 2 Registers */ |
9069c13a | 2156 | if (chip->info->global2_addr) { |
9729934c | 2157 | err = mv88e6xxx_g2_setup(chip); |
a1a6a4d1 VD |
2158 | if (err) |
2159 | goto unlock; | |
2160 | } | |
08a01261 | 2161 | |
cd8da8bb VD |
2162 | err = mv88e6xxx_irl_setup(chip); |
2163 | if (err) | |
2164 | goto unlock; | |
2165 | ||
04a69a17 VD |
2166 | err = mv88e6xxx_mac_setup(chip); |
2167 | if (err) | |
2168 | goto unlock; | |
2169 | ||
1b17aedf VD |
2170 | err = mv88e6xxx_phy_setup(chip); |
2171 | if (err) | |
2172 | goto unlock; | |
2173 | ||
b486d7c9 VD |
2174 | err = mv88e6xxx_vtu_setup(chip); |
2175 | if (err) | |
2176 | goto unlock; | |
2177 | ||
81228996 VD |
2178 | err = mv88e6xxx_pvt_setup(chip); |
2179 | if (err) | |
2180 | goto unlock; | |
2181 | ||
a2ac29d2 VD |
2182 | err = mv88e6xxx_atu_setup(chip); |
2183 | if (err) | |
2184 | goto unlock; | |
2185 | ||
87fa886e AL |
2186 | err = mv88e6xxx_broadcast_setup(chip, 0); |
2187 | if (err) | |
2188 | goto unlock; | |
2189 | ||
9e907d73 VD |
2190 | err = mv88e6xxx_pot_setup(chip); |
2191 | if (err) | |
2192 | goto unlock; | |
2193 | ||
51c901a7 VD |
2194 | err = mv88e6xxx_rsvd2cpu_setup(chip); |
2195 | if (err) | |
2196 | goto unlock; | |
6e55f698 | 2197 | |
c6fe0ad2 | 2198 | /* Setup PTP Hardware Clock and timestamping */ |
2fa8d3af BS |
2199 | if (chip->info->ptp_support) { |
2200 | err = mv88e6xxx_ptp_setup(chip); | |
2201 | if (err) | |
2202 | goto unlock; | |
c6fe0ad2 BS |
2203 | |
2204 | err = mv88e6xxx_hwtstamp_setup(chip); | |
2205 | if (err) | |
2206 | goto unlock; | |
2fa8d3af BS |
2207 | } |
2208 | ||
6b17e864 | 2209 | unlock: |
fad09c73 | 2210 | mutex_unlock(&chip->reg_lock); |
db687a56 | 2211 | |
48ace4ef | 2212 | return err; |
54d792f2 AL |
2213 | } |
2214 | ||
e57e5e77 | 2215 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
fd3a0ee4 | 2216 | { |
0dd12d54 AL |
2217 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
2218 | struct mv88e6xxx_chip *chip = mdio_bus->chip; | |
e57e5e77 VD |
2219 | u16 val; |
2220 | int err; | |
fd3a0ee4 | 2221 | |
ee26a228 AL |
2222 | if (!chip->info->ops->phy_read) |
2223 | return -EOPNOTSUPP; | |
2224 | ||
fad09c73 | 2225 | mutex_lock(&chip->reg_lock); |
ee26a228 | 2226 | err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); |
fad09c73 | 2227 | mutex_unlock(&chip->reg_lock); |
e57e5e77 | 2228 | |
da9f3301 AL |
2229 | if (reg == MII_PHYSID2) { |
2230 | /* Some internal PHYS don't have a model number. Use | |
2231 | * the mv88e6390 family model number instead. | |
2232 | */ | |
2233 | if (!(val & 0x3f0)) | |
107fcc10 | 2234 | val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; |
da9f3301 AL |
2235 | } |
2236 | ||
e57e5e77 | 2237 | return err ? err : val; |
fd3a0ee4 AL |
2238 | } |
2239 | ||
e57e5e77 | 2240 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
fd3a0ee4 | 2241 | { |
0dd12d54 AL |
2242 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
2243 | struct mv88e6xxx_chip *chip = mdio_bus->chip; | |
e57e5e77 | 2244 | int err; |
fd3a0ee4 | 2245 | |
ee26a228 AL |
2246 | if (!chip->info->ops->phy_write) |
2247 | return -EOPNOTSUPP; | |
2248 | ||
fad09c73 | 2249 | mutex_lock(&chip->reg_lock); |
ee26a228 | 2250 | err = chip->info->ops->phy_write(chip, bus, phy, reg, val); |
fad09c73 | 2251 | mutex_unlock(&chip->reg_lock); |
e57e5e77 VD |
2252 | |
2253 | return err; | |
fd3a0ee4 AL |
2254 | } |
2255 | ||
fad09c73 | 2256 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
a3c53be5 AL |
2257 | struct device_node *np, |
2258 | bool external) | |
b516d453 AL |
2259 | { |
2260 | static int index; | |
0dd12d54 | 2261 | struct mv88e6xxx_mdio_bus *mdio_bus; |
b516d453 AL |
2262 | struct mii_bus *bus; |
2263 | int err; | |
2264 | ||
2510babc AL |
2265 | if (external) { |
2266 | mutex_lock(&chip->reg_lock); | |
2267 | err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); | |
2268 | mutex_unlock(&chip->reg_lock); | |
2269 | ||
2270 | if (err) | |
2271 | return err; | |
2272 | } | |
2273 | ||
0dd12d54 | 2274 | bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); |
b516d453 AL |
2275 | if (!bus) |
2276 | return -ENOMEM; | |
2277 | ||
0dd12d54 | 2278 | mdio_bus = bus->priv; |
a3c53be5 | 2279 | mdio_bus->bus = bus; |
0dd12d54 | 2280 | mdio_bus->chip = chip; |
a3c53be5 AL |
2281 | INIT_LIST_HEAD(&mdio_bus->list); |
2282 | mdio_bus->external = external; | |
0dd12d54 | 2283 | |
b516d453 AL |
2284 | if (np) { |
2285 | bus->name = np->full_name; | |
f7ce9103 | 2286 | snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); |
b516d453 AL |
2287 | } else { |
2288 | bus->name = "mv88e6xxx SMI"; | |
2289 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); | |
2290 | } | |
2291 | ||
2292 | bus->read = mv88e6xxx_mdio_read; | |
2293 | bus->write = mv88e6xxx_mdio_write; | |
fad09c73 | 2294 | bus->parent = chip->dev; |
b516d453 | 2295 | |
6f88284f AL |
2296 | if (!external) { |
2297 | err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); | |
2298 | if (err) | |
2299 | return err; | |
2300 | } | |
2301 | ||
a3c53be5 AL |
2302 | if (np) |
2303 | err = of_mdiobus_register(bus, np); | |
b516d453 AL |
2304 | else |
2305 | err = mdiobus_register(bus); | |
2306 | if (err) { | |
fad09c73 | 2307 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
6f88284f | 2308 | mv88e6xxx_g2_irq_mdio_free(chip, bus); |
a3c53be5 | 2309 | return err; |
b516d453 | 2310 | } |
a3c53be5 AL |
2311 | |
2312 | if (external) | |
2313 | list_add_tail(&mdio_bus->list, &chip->mdios); | |
2314 | else | |
2315 | list_add(&mdio_bus->list, &chip->mdios); | |
b516d453 AL |
2316 | |
2317 | return 0; | |
a3c53be5 | 2318 | } |
b516d453 | 2319 | |
a3c53be5 AL |
2320 | static const struct of_device_id mv88e6xxx_mdio_external_match[] = { |
2321 | { .compatible = "marvell,mv88e6xxx-mdio-external", | |
2322 | .data = (void *)true }, | |
2323 | { }, | |
2324 | }; | |
b516d453 | 2325 | |
3126aeec AL |
2326 | static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) |
2327 | ||
2328 | { | |
2329 | struct mv88e6xxx_mdio_bus *mdio_bus; | |
2330 | struct mii_bus *bus; | |
2331 | ||
2332 | list_for_each_entry(mdio_bus, &chip->mdios, list) { | |
2333 | bus = mdio_bus->bus; | |
2334 | ||
6f88284f AL |
2335 | if (!mdio_bus->external) |
2336 | mv88e6xxx_g2_irq_mdio_free(chip, bus); | |
2337 | ||
3126aeec AL |
2338 | mdiobus_unregister(bus); |
2339 | } | |
2340 | } | |
2341 | ||
a3c53be5 AL |
2342 | static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, |
2343 | struct device_node *np) | |
2344 | { | |
2345 | const struct of_device_id *match; | |
2346 | struct device_node *child; | |
2347 | int err; | |
2348 | ||
2349 | /* Always register one mdio bus for the internal/default mdio | |
2350 | * bus. This maybe represented in the device tree, but is | |
2351 | * optional. | |
2352 | */ | |
2353 | child = of_get_child_by_name(np, "mdio"); | |
2354 | err = mv88e6xxx_mdio_register(chip, child, false); | |
2355 | if (err) | |
2356 | return err; | |
2357 | ||
2358 | /* Walk the device tree, and see if there are any other nodes | |
2359 | * which say they are compatible with the external mdio | |
2360 | * bus. | |
2361 | */ | |
2362 | for_each_available_child_of_node(np, child) { | |
2363 | match = of_match_node(mv88e6xxx_mdio_external_match, child); | |
2364 | if (match) { | |
2365 | err = mv88e6xxx_mdio_register(chip, child, true); | |
3126aeec AL |
2366 | if (err) { |
2367 | mv88e6xxx_mdios_unregister(chip); | |
a3c53be5 | 2368 | return err; |
3126aeec | 2369 | } |
a3c53be5 AL |
2370 | } |
2371 | } | |
2372 | ||
2373 | return 0; | |
b516d453 AL |
2374 | } |
2375 | ||
855b1932 VD |
2376 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
2377 | { | |
04bed143 | 2378 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
2379 | |
2380 | return chip->eeprom_len; | |
2381 | } | |
2382 | ||
855b1932 VD |
2383 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
2384 | struct ethtool_eeprom *eeprom, u8 *data) | |
2385 | { | |
04bed143 | 2386 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
2387 | int err; |
2388 | ||
ee4dc2e7 VD |
2389 | if (!chip->info->ops->get_eeprom) |
2390 | return -EOPNOTSUPP; | |
855b1932 | 2391 | |
ee4dc2e7 VD |
2392 | mutex_lock(&chip->reg_lock); |
2393 | err = chip->info->ops->get_eeprom(chip, eeprom, data); | |
855b1932 VD |
2394 | mutex_unlock(&chip->reg_lock); |
2395 | ||
2396 | if (err) | |
2397 | return err; | |
2398 | ||
2399 | eeprom->magic = 0xc3ec4951; | |
2400 | ||
2401 | return 0; | |
2402 | } | |
2403 | ||
855b1932 VD |
2404 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
2405 | struct ethtool_eeprom *eeprom, u8 *data) | |
2406 | { | |
04bed143 | 2407 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
2408 | int err; |
2409 | ||
ee4dc2e7 VD |
2410 | if (!chip->info->ops->set_eeprom) |
2411 | return -EOPNOTSUPP; | |
2412 | ||
855b1932 VD |
2413 | if (eeprom->magic != 0xc3ec4951) |
2414 | return -EINVAL; | |
2415 | ||
2416 | mutex_lock(&chip->reg_lock); | |
ee4dc2e7 | 2417 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
855b1932 VD |
2418 | mutex_unlock(&chip->reg_lock); |
2419 | ||
2420 | return err; | |
2421 | } | |
2422 | ||
b3469dd8 | 2423 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
4b325d8c | 2424 | /* MV88E6XXX_FAMILY_6097 */ |
cd8da8bb | 2425 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 2426 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2427 | .phy_read = mv88e6185_phy_ppu_read, |
2428 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2429 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2430 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2431 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2432 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2433 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2434 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2435 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
ef70b111 | 2436 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2437 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2438 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2439 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2440 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 2441 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2442 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2443 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2444 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2445 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2446 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2447 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2448 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2449 | .pot_clear = mv88e6xxx_g2_pot_clear, |
a199d8b6 VD |
2450 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2451 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2452 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2453 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2454 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2455 | }; |
2456 | ||
2457 | static const struct mv88e6xxx_ops mv88e6095_ops = { | |
4b325d8c | 2458 | /* MV88E6XXX_FAMILY_6095 */ |
b073d4e2 | 2459 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2460 | .phy_read = mv88e6185_phy_ppu_read, |
2461 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2462 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2463 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2464 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc | 2465 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
601aeed3 | 2466 | .port_set_egress_floods = mv88e6185_port_set_egress_floods, |
a23b2961 | 2467 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
a605a0fe | 2468 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 2469 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2470 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2471 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2472 | .stats_get_stats = mv88e6095_stats_get_stats, |
51c901a7 | 2473 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
a199d8b6 VD |
2474 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2475 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2476 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2477 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2478 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2479 | }; |
2480 | ||
7d381a02 | 2481 | static const struct mv88e6xxx_ops mv88e6097_ops = { |
15da3cc8 | 2482 | /* MV88E6XXX_FAMILY_6097 */ |
cd8da8bb | 2483 | .irl_init_all = mv88e6352_g2_irl_init_all, |
7d381a02 SE |
2484 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2485 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2486 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2487 | .port_set_link = mv88e6xxx_port_set_link, | |
2488 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2489 | .port_set_speed = mv88e6185_port_set_speed, | |
ef0a7318 | 2490 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2491 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2492 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2493 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2494 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2495 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
0898432c | 2496 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2497 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2498 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
7d381a02 | 2499 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 2500 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
7d381a02 SE |
2501 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2502 | .stats_get_strings = mv88e6095_stats_get_strings, | |
2503 | .stats_get_stats = mv88e6095_stats_get_stats, | |
fa8d1179 VD |
2504 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2505 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
91eaa475 | 2506 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2507 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2508 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2509 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2510 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2511 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
7d381a02 SE |
2512 | }; |
2513 | ||
b3469dd8 | 2514 | static const struct mv88e6xxx_ops mv88e6123_ops = { |
4b325d8c | 2515 | /* MV88E6XXX_FAMILY_6165 */ |
cd8da8bb | 2516 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 2517 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
ec8378bb AL |
2518 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2519 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2520 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2521 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2522 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc | 2523 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
601aeed3 | 2524 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
c8c94891 | 2525 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2526 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
0ac64c39 | 2527 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 2528 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2529 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2530 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2531 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2532 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2533 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2534 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2535 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2536 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2537 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2538 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2539 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2540 | }; |
2541 | ||
2542 | static const struct mv88e6xxx_ops mv88e6131_ops = { | |
4b325d8c | 2543 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 2544 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2545 | .phy_read = mv88e6185_phy_ppu_read, |
2546 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2547 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2548 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2549 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2550 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2551 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2552 | .port_set_egress_floods = mv88e6185_port_set_egress_floods, |
56995cbc | 2553 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
a23b2961 | 2554 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
cd782656 | 2555 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2556 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2557 | .port_pause_limit = mv88e6097_port_pause_limit, |
a605a0fe | 2558 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 2559 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2560 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2561 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2562 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2563 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2564 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2565 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2566 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
a199d8b6 VD |
2567 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2568 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2569 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2570 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2571 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2572 | }; |
2573 | ||
990e27b0 VD |
2574 | static const struct mv88e6xxx_ops mv88e6141_ops = { |
2575 | /* MV88E6XXX_FAMILY_6341 */ | |
cd8da8bb | 2576 | .irl_init_all = mv88e6352_g2_irl_init_all, |
990e27b0 VD |
2577 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2578 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
2579 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
2580 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2581 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2582 | .port_set_link = mv88e6xxx_port_set_link, | |
2583 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2584 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2585 | .port_set_speed = mv88e6390_port_set_speed, | |
2586 | .port_tag_remap = mv88e6095_port_tag_remap, | |
2587 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, | |
2588 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, | |
2589 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
cd782656 | 2590 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
990e27b0 | 2591 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2592 | .port_pause_limit = mv88e6097_port_pause_limit, |
990e27b0 VD |
2593 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
2594 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
2595 | .stats_snapshot = mv88e6390_g1_stats_snapshot, | |
40cff8fc | 2596 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
990e27b0 VD |
2597 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2598 | .stats_get_strings = mv88e6320_stats_get_strings, | |
2599 | .stats_get_stats = mv88e6390_stats_get_stats, | |
fa8d1179 VD |
2600 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2601 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
990e27b0 VD |
2602 | .watchdog_ops = &mv88e6390_watchdog_ops, |
2603 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, | |
9e907d73 | 2604 | .pot_clear = mv88e6xxx_g2_pot_clear, |
990e27b0 | 2605 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2606 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2607 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
a73ccd61 | 2608 | .gpio_ops = &mv88e6352_gpio_ops, |
990e27b0 VD |
2609 | }; |
2610 | ||
b3469dd8 | 2611 | static const struct mv88e6xxx_ops mv88e6161_ops = { |
4b325d8c | 2612 | /* MV88E6XXX_FAMILY_6165 */ |
cd8da8bb | 2613 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 2614 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
ec8378bb AL |
2615 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2616 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2617 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2618 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2619 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2620 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2621 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2622 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2623 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2624 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2625 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2626 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2627 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2628 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
0ac64c39 | 2629 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 2630 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2631 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2632 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2633 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2634 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2635 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2636 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2637 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2638 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2639 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2640 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2641 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2642 | }; |
2643 | ||
2644 | static const struct mv88e6xxx_ops mv88e6165_ops = { | |
4b325d8c | 2645 | /* MV88E6XXX_FAMILY_6165 */ |
cd8da8bb | 2646 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 2647 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
efb3e74d AL |
2648 | .phy_read = mv88e6165_phy_read, |
2649 | .phy_write = mv88e6165_phy_write, | |
08ef7f10 | 2650 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2651 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2652 | .port_set_speed = mv88e6185_port_set_speed, |
c8c94891 | 2653 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2654 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2655 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 2656 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2657 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2658 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2659 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2660 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2661 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2662 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2663 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2664 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2665 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2666 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2667 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2668 | }; |
2669 | ||
2670 | static const struct mv88e6xxx_ops mv88e6171_ops = { | |
4b325d8c | 2671 | /* MV88E6XXX_FAMILY_6351 */ |
cd8da8bb | 2672 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 2673 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2674 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2675 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2676 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2677 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 2678 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2679 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2680 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2681 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2682 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2683 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2684 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2685 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2686 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2687 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2688 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2689 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 2690 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2691 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2692 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2693 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2694 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2695 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2696 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2697 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2698 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2699 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2700 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2701 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2702 | }; |
2703 | ||
2704 | static const struct mv88e6xxx_ops mv88e6172_ops = { | |
4b325d8c | 2705 | /* MV88E6XXX_FAMILY_6352 */ |
cd8da8bb | 2706 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
2707 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2708 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2709 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2710 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2711 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2712 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2713 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 2714 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2715 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 2716 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2717 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2718 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2719 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2720 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2721 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2722 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2723 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2724 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2725 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 2726 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2727 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2728 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2729 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2730 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2731 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2732 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2733 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2734 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2735 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2736 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2737 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 2738 | .serdes_power = mv88e6352_serdes_power, |
a73ccd61 | 2739 | .gpio_ops = &mv88e6352_gpio_ops, |
b3469dd8 VD |
2740 | }; |
2741 | ||
2742 | static const struct mv88e6xxx_ops mv88e6175_ops = { | |
4b325d8c | 2743 | /* MV88E6XXX_FAMILY_6351 */ |
cd8da8bb | 2744 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 2745 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2746 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2747 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2748 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2749 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 2750 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2751 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 2752 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2753 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2754 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2755 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2756 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2757 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2758 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2759 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2760 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2761 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 2762 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2763 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2764 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2765 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2766 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2767 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2768 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2769 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2770 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2771 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2772 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2773 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
2774 | }; |
2775 | ||
2776 | static const struct mv88e6xxx_ops mv88e6176_ops = { | |
4b325d8c | 2777 | /* MV88E6XXX_FAMILY_6352 */ |
cd8da8bb | 2778 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
2779 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2780 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2781 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2782 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2783 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2784 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2785 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 2786 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2787 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 2788 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2789 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2790 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2791 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2792 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2793 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2794 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2795 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2796 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2797 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 2798 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2799 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2800 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2801 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2802 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2803 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2804 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2805 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2806 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2807 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2808 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2809 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 2810 | .serdes_power = mv88e6352_serdes_power, |
a73ccd61 | 2811 | .gpio_ops = &mv88e6352_gpio_ops, |
b3469dd8 VD |
2812 | }; |
2813 | ||
2814 | static const struct mv88e6xxx_ops mv88e6185_ops = { | |
4b325d8c | 2815 | /* MV88E6XXX_FAMILY_6185 */ |
b073d4e2 | 2816 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
2817 | .phy_read = mv88e6185_phy_ppu_read, |
2818 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 2819 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2820 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 2821 | .port_set_speed = mv88e6185_port_set_speed, |
56995cbc | 2822 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
601aeed3 | 2823 | .port_set_egress_floods = mv88e6185_port_set_egress_floods, |
ef70b111 | 2824 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
a23b2961 | 2825 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
a605a0fe | 2826 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 2827 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2828 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2829 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2830 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2831 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2832 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2833 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2834 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
a199d8b6 VD |
2835 | .ppu_enable = mv88e6185_g1_ppu_enable, |
2836 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 2837 | .reset = mv88e6185_g1_reset, |
f1394b78 | 2838 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 2839 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
b3469dd8 VD |
2840 | }; |
2841 | ||
1a3b39ec | 2842 | static const struct mv88e6xxx_ops mv88e6190_ops = { |
4b325d8c | 2843 | /* MV88E6XXX_FAMILY_6390 */ |
cd8da8bb | 2844 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
2845 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2846 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2847 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2848 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2849 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2850 | .port_set_link = mv88e6xxx_port_set_link, | |
2851 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2852 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2853 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 2854 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 2855 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2856 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2857 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 2858 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 2859 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2860 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 2861 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 2862 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
2863 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2864 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 2865 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
2866 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2867 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 2868 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 2869 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 2870 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2871 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
2872 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
2873 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 2874 | .serdes_power = mv88e6390_serdes_power, |
a73ccd61 | 2875 | .gpio_ops = &mv88e6352_gpio_ops, |
1a3b39ec AL |
2876 | }; |
2877 | ||
2878 | static const struct mv88e6xxx_ops mv88e6190x_ops = { | |
4b325d8c | 2879 | /* MV88E6XXX_FAMILY_6390 */ |
cd8da8bb | 2880 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
2881 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2882 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2883 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2884 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2885 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2886 | .port_set_link = mv88e6xxx_port_set_link, | |
2887 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2888 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2889 | .port_set_speed = mv88e6390x_port_set_speed, | |
ef0a7318 | 2890 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 2891 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2892 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2893 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 2894 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 2895 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2896 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 2897 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 2898 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
2899 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2900 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 2901 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
2902 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2903 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 2904 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 2905 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 2906 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2907 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
2908 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
2909 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 2910 | .serdes_power = mv88e6390_serdes_power, |
a73ccd61 | 2911 | .gpio_ops = &mv88e6352_gpio_ops, |
1a3b39ec AL |
2912 | }; |
2913 | ||
2914 | static const struct mv88e6xxx_ops mv88e6191_ops = { | |
4b325d8c | 2915 | /* MV88E6XXX_FAMILY_6390 */ |
cd8da8bb | 2916 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
2917 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2918 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2919 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2920 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2921 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2922 | .port_set_link = mv88e6xxx_port_set_link, | |
2923 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2924 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2925 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 2926 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 2927 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2928 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2929 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 2930 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 2931 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2932 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 2933 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 2934 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
2935 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
2936 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 2937 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
2938 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
2939 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 2940 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 2941 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 2942 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2943 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
2944 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
2945 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 2946 | .serdes_power = mv88e6390_serdes_power, |
1a3b39ec AL |
2947 | }; |
2948 | ||
b3469dd8 | 2949 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
4b325d8c | 2950 | /* MV88E6XXX_FAMILY_6352 */ |
cd8da8bb | 2951 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
2952 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
2953 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 2954 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
2955 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
2956 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 2957 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 2958 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 2959 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 2960 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 2961 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 2962 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 2963 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 2964 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 2965 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 2966 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 2967 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 2968 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 2969 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 2970 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 2971 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
2972 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
2973 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 2974 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
2975 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
2976 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 2977 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 2978 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 2979 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 2980 | .reset = mv88e6352_g1_reset, |
f1394b78 | 2981 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 2982 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 2983 | .serdes_power = mv88e6352_serdes_power, |
a73ccd61 | 2984 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 2985 | .avb_ops = &mv88e6352_avb_ops, |
b3469dd8 VD |
2986 | }; |
2987 | ||
1a3b39ec | 2988 | static const struct mv88e6xxx_ops mv88e6290_ops = { |
4b325d8c | 2989 | /* MV88E6XXX_FAMILY_6390 */ |
cd8da8bb | 2990 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
2991 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
2992 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
2993 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
2994 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
2995 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
2996 | .port_set_link = mv88e6xxx_port_set_link, | |
2997 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
2998 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
2999 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3000 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 3001 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3002 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3003 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 3004 | .port_pause_limit = mv88e6390_port_pause_limit, |
f39908d3 | 3005 | .port_set_cmode = mv88e6390x_port_set_cmode, |
c8c94891 | 3006 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3007 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 3008 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3009 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3010 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3011 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3012 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
3013 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
3014 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 3015 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 3016 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 3017 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3018 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
3019 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
3020 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 3021 | .serdes_power = mv88e6390_serdes_power, |
a73ccd61 | 3022 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 3023 | .avb_ops = &mv88e6390_avb_ops, |
1a3b39ec AL |
3024 | }; |
3025 | ||
b3469dd8 | 3026 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
4b325d8c | 3027 | /* MV88E6XXX_FAMILY_6320 */ |
cd8da8bb | 3028 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
3029 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3030 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3031 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3032 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3033 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3034 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3035 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3036 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3037 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3038 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3039 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3040 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3041 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3042 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3043 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3044 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3045 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 3046 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3047 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3048 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3049 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 3050 | .stats_get_stats = mv88e6320_stats_get_stats, |
fa8d1179 VD |
3051 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3052 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
51c901a7 | 3053 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3054 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3055 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3056 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 3057 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
a73ccd61 | 3058 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 3059 | .avb_ops = &mv88e6352_avb_ops, |
b3469dd8 VD |
3060 | }; |
3061 | ||
3062 | static const struct mv88e6xxx_ops mv88e6321_ops = { | |
bd807204 | 3063 | /* MV88E6XXX_FAMILY_6320 */ |
cd8da8bb | 3064 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
3065 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3066 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3067 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3068 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3069 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3070 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3071 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
96a2b40c | 3072 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3073 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3074 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3075 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3076 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3077 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3078 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3079 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3080 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3081 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 3082 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3083 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3084 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3085 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 3086 | .stats_get_stats = mv88e6320_stats_get_stats, |
fa8d1179 VD |
3087 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3088 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
17e708ba | 3089 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3090 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 3091 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
a73ccd61 | 3092 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 3093 | .avb_ops = &mv88e6352_avb_ops, |
b3469dd8 VD |
3094 | }; |
3095 | ||
16e329ae VD |
3096 | static const struct mv88e6xxx_ops mv88e6341_ops = { |
3097 | /* MV88E6XXX_FAMILY_6341 */ | |
cd8da8bb | 3098 | .irl_init_all = mv88e6352_g2_irl_init_all, |
16e329ae VD |
3099 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
3100 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
3101 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
3102 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3103 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3104 | .port_set_link = mv88e6xxx_port_set_link, | |
3105 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3106 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3107 | .port_set_speed = mv88e6390_port_set_speed, | |
3108 | .port_tag_remap = mv88e6095_port_tag_remap, | |
3109 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, | |
3110 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, | |
3111 | .port_set_ether_type = mv88e6351_port_set_ether_type, | |
cd782656 | 3112 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
16e329ae | 3113 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3114 | .port_pause_limit = mv88e6097_port_pause_limit, |
16e329ae VD |
3115 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
3116 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
3117 | .stats_snapshot = mv88e6390_g1_stats_snapshot, | |
40cff8fc | 3118 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
16e329ae VD |
3119 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3120 | .stats_get_strings = mv88e6320_stats_get_strings, | |
3121 | .stats_get_stats = mv88e6390_stats_get_stats, | |
fa8d1179 VD |
3122 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
3123 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
16e329ae VD |
3124 | .watchdog_ops = &mv88e6390_watchdog_ops, |
3125 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, | |
9e907d73 | 3126 | .pot_clear = mv88e6xxx_g2_pot_clear, |
16e329ae | 3127 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3128 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3129 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
a73ccd61 | 3130 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 3131 | .avb_ops = &mv88e6390_avb_ops, |
16e329ae VD |
3132 | }; |
3133 | ||
b3469dd8 | 3134 | static const struct mv88e6xxx_ops mv88e6350_ops = { |
4b325d8c | 3135 | /* MV88E6XXX_FAMILY_6351 */ |
cd8da8bb | 3136 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3137 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3138 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3139 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3140 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3141 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3142 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3143 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3144 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3145 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3146 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3147 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3148 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3149 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3150 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3151 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3152 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 3153 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3154 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3155 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3156 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3157 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3158 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3159 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3160 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3161 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3162 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3163 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3164 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3165 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
b3469dd8 VD |
3166 | }; |
3167 | ||
3168 | static const struct mv88e6xxx_ops mv88e6351_ops = { | |
4b325d8c | 3169 | /* MV88E6XXX_FAMILY_6351 */ |
cd8da8bb | 3170 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3171 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3172 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3173 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3174 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3175 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
94d66ae6 | 3176 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3177 | .port_set_speed = mv88e6185_port_set_speed, |
ef0a7318 | 3178 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3179 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3180 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3181 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3182 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3183 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3184 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3185 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3186 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 3187 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3188 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3189 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3190 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3191 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3192 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3193 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3194 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3195 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3196 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3197 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3198 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3199 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
0d632c3d | 3200 | .avb_ops = &mv88e6352_avb_ops, |
b3469dd8 VD |
3201 | }; |
3202 | ||
3203 | static const struct mv88e6xxx_ops mv88e6352_ops = { | |
4b325d8c | 3204 | /* MV88E6XXX_FAMILY_6352 */ |
cd8da8bb | 3205 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
3206 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3207 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3208 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3209 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3210 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3211 | .port_set_link = mv88e6xxx_port_set_link, |
7f1ae07b | 3212 | .port_set_duplex = mv88e6xxx_port_set_duplex, |
a0a0f622 | 3213 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
96a2b40c | 3214 | .port_set_speed = mv88e6352_port_set_speed, |
ef0a7318 | 3215 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3216 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3217 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3218 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3219 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3220 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3221 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3222 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3223 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
a605a0fe | 3224 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3225 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3226 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3227 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3228 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3229 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3230 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3231 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3232 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3233 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3234 | .reset = mv88e6352_g1_reset, |
f1394b78 | 3235 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3236 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6d91782f | 3237 | .serdes_power = mv88e6352_serdes_power, |
a73ccd61 | 3238 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 3239 | .avb_ops = &mv88e6352_avb_ops, |
cda9f4aa AL |
3240 | .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, |
3241 | .serdes_get_strings = mv88e6352_serdes_get_strings, | |
3242 | .serdes_get_stats = mv88e6352_serdes_get_stats, | |
b3469dd8 VD |
3243 | }; |
3244 | ||
1a3b39ec | 3245 | static const struct mv88e6xxx_ops mv88e6390_ops = { |
4b325d8c | 3246 | /* MV88E6XXX_FAMILY_6390 */ |
cd8da8bb | 3247 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
3248 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
3249 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
3250 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3251 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3252 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3253 | .port_set_link = mv88e6xxx_port_set_link, | |
3254 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3255 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3256 | .port_set_speed = mv88e6390_port_set_speed, | |
ef0a7318 | 3257 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 3258 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3259 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3260 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3261 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3262 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3263 | .port_pause_limit = mv88e6390_port_pause_limit, |
f39908d3 | 3264 | .port_set_cmode = mv88e6390x_port_set_cmode, |
c8c94891 | 3265 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3266 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 3267 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3268 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3269 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3270 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3271 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
3272 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
3273 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 3274 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 3275 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 3276 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3277 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
3278 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
3279 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 3280 | .serdes_power = mv88e6390_serdes_power, |
a73ccd61 | 3281 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 3282 | .avb_ops = &mv88e6390_avb_ops, |
1a3b39ec AL |
3283 | }; |
3284 | ||
3285 | static const struct mv88e6xxx_ops mv88e6390x_ops = { | |
4b325d8c | 3286 | /* MV88E6XXX_FAMILY_6390 */ |
cd8da8bb | 3287 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
3288 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
3289 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
3290 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3291 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3292 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3293 | .port_set_link = mv88e6xxx_port_set_link, | |
3294 | .port_set_duplex = mv88e6xxx_port_set_duplex, | |
3295 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
3296 | .port_set_speed = mv88e6390x_port_set_speed, | |
ef0a7318 | 3297 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 3298 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
601aeed3 | 3299 | .port_set_egress_floods = mv88e6352_port_set_egress_floods, |
56995cbc | 3300 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3301 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3302 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3303 | .port_pause_limit = mv88e6390_port_pause_limit, |
bb0a2675 | 3304 | .port_set_cmode = mv88e6390x_port_set_cmode, |
c8c94891 | 3305 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3306 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
79523473 | 3307 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 3308 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
3309 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3310 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 3311 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
3312 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
3313 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 3314 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 3315 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 3316 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3317 | .reset = mv88e6352_g1_reset, |
931d1822 VD |
3318 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
3319 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 3320 | .serdes_power = mv88e6390_serdes_power, |
a73ccd61 | 3321 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 3322 | .avb_ops = &mv88e6390_avb_ops, |
1a3b39ec AL |
3323 | }; |
3324 | ||
f81ec90f VD |
3325 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
3326 | [MV88E6085] = { | |
107fcc10 | 3327 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, |
f81ec90f VD |
3328 | .family = MV88E6XXX_FAMILY_6097, |
3329 | .name = "Marvell 88E6085", | |
3330 | .num_databases = 4096, | |
3331 | .num_ports = 10, | |
bc393155 | 3332 | .num_internal_phys = 5, |
3cf3c846 | 3333 | .max_vid = 4095, |
9dddd478 | 3334 | .port_base_addr = 0x10, |
a935c052 | 3335 | .global1_addr = 0x1b, |
9069c13a | 3336 | .global2_addr = 0x1c, |
acddbd21 | 3337 | .age_time_coeff = 15000, |
dc30c35b | 3338 | .g1_irqs = 8, |
d6c5e6af | 3339 | .g2_irqs = 10, |
e606ca36 | 3340 | .atu_move_port_mask = 0xf, |
f3645652 | 3341 | .pvt = true, |
b3e05aa1 | 3342 | .multi_chip = true, |
443d5a1b | 3343 | .tag_protocol = DSA_TAG_PROTO_DSA, |
b3469dd8 | 3344 | .ops = &mv88e6085_ops, |
f81ec90f VD |
3345 | }, |
3346 | ||
3347 | [MV88E6095] = { | |
107fcc10 | 3348 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, |
f81ec90f VD |
3349 | .family = MV88E6XXX_FAMILY_6095, |
3350 | .name = "Marvell 88E6095/88E6095F", | |
3351 | .num_databases = 256, | |
3352 | .num_ports = 11, | |
bc393155 | 3353 | .num_internal_phys = 0, |
3cf3c846 | 3354 | .max_vid = 4095, |
9dddd478 | 3355 | .port_base_addr = 0x10, |
a935c052 | 3356 | .global1_addr = 0x1b, |
9069c13a | 3357 | .global2_addr = 0x1c, |
acddbd21 | 3358 | .age_time_coeff = 15000, |
dc30c35b | 3359 | .g1_irqs = 8, |
e606ca36 | 3360 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 3361 | .multi_chip = true, |
443d5a1b | 3362 | .tag_protocol = DSA_TAG_PROTO_DSA, |
b3469dd8 | 3363 | .ops = &mv88e6095_ops, |
f81ec90f VD |
3364 | }, |
3365 | ||
7d381a02 | 3366 | [MV88E6097] = { |
107fcc10 | 3367 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, |
7d381a02 SE |
3368 | .family = MV88E6XXX_FAMILY_6097, |
3369 | .name = "Marvell 88E6097/88E6097F", | |
3370 | .num_databases = 4096, | |
3371 | .num_ports = 11, | |
bc393155 | 3372 | .num_internal_phys = 8, |
3cf3c846 | 3373 | .max_vid = 4095, |
7d381a02 SE |
3374 | .port_base_addr = 0x10, |
3375 | .global1_addr = 0x1b, | |
9069c13a | 3376 | .global2_addr = 0x1c, |
7d381a02 | 3377 | .age_time_coeff = 15000, |
c534178b | 3378 | .g1_irqs = 8, |
d6c5e6af | 3379 | .g2_irqs = 10, |
e606ca36 | 3380 | .atu_move_port_mask = 0xf, |
f3645652 | 3381 | .pvt = true, |
b3e05aa1 | 3382 | .multi_chip = true, |
2bfcfcd3 | 3383 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
7d381a02 SE |
3384 | .ops = &mv88e6097_ops, |
3385 | }, | |
3386 | ||
f81ec90f | 3387 | [MV88E6123] = { |
107fcc10 | 3388 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, |
f81ec90f VD |
3389 | .family = MV88E6XXX_FAMILY_6165, |
3390 | .name = "Marvell 88E6123", | |
3391 | .num_databases = 4096, | |
3392 | .num_ports = 3, | |
bc393155 | 3393 | .num_internal_phys = 5, |
3cf3c846 | 3394 | .max_vid = 4095, |
9dddd478 | 3395 | .port_base_addr = 0x10, |
a935c052 | 3396 | .global1_addr = 0x1b, |
9069c13a | 3397 | .global2_addr = 0x1c, |
acddbd21 | 3398 | .age_time_coeff = 15000, |
dc30c35b | 3399 | .g1_irqs = 9, |
d6c5e6af | 3400 | .g2_irqs = 10, |
e606ca36 | 3401 | .atu_move_port_mask = 0xf, |
f3645652 | 3402 | .pvt = true, |
b3e05aa1 | 3403 | .multi_chip = true, |
5ebe31d7 | 3404 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3405 | .ops = &mv88e6123_ops, |
f81ec90f VD |
3406 | }, |
3407 | ||
3408 | [MV88E6131] = { | |
107fcc10 | 3409 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, |
f81ec90f VD |
3410 | .family = MV88E6XXX_FAMILY_6185, |
3411 | .name = "Marvell 88E6131", | |
3412 | .num_databases = 256, | |
3413 | .num_ports = 8, | |
bc393155 | 3414 | .num_internal_phys = 0, |
3cf3c846 | 3415 | .max_vid = 4095, |
9dddd478 | 3416 | .port_base_addr = 0x10, |
a935c052 | 3417 | .global1_addr = 0x1b, |
9069c13a | 3418 | .global2_addr = 0x1c, |
acddbd21 | 3419 | .age_time_coeff = 15000, |
dc30c35b | 3420 | .g1_irqs = 9, |
e606ca36 | 3421 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 3422 | .multi_chip = true, |
443d5a1b | 3423 | .tag_protocol = DSA_TAG_PROTO_DSA, |
b3469dd8 | 3424 | .ops = &mv88e6131_ops, |
f81ec90f VD |
3425 | }, |
3426 | ||
990e27b0 | 3427 | [MV88E6141] = { |
107fcc10 | 3428 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, |
990e27b0 | 3429 | .family = MV88E6XXX_FAMILY_6341, |
79a68b26 | 3430 | .name = "Marvell 88E6141", |
990e27b0 VD |
3431 | .num_databases = 4096, |
3432 | .num_ports = 6, | |
bc393155 | 3433 | .num_internal_phys = 5, |
a73ccd61 | 3434 | .num_gpio = 11, |
3cf3c846 | 3435 | .max_vid = 4095, |
990e27b0 VD |
3436 | .port_base_addr = 0x10, |
3437 | .global1_addr = 0x1b, | |
9069c13a | 3438 | .global2_addr = 0x1c, |
990e27b0 VD |
3439 | .age_time_coeff = 3750, |
3440 | .atu_move_port_mask = 0x1f, | |
adfccf11 | 3441 | .g1_irqs = 9, |
d6c5e6af | 3442 | .g2_irqs = 10, |
f3645652 | 3443 | .pvt = true, |
b3e05aa1 | 3444 | .multi_chip = true, |
990e27b0 | 3445 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
990e27b0 VD |
3446 | .ops = &mv88e6141_ops, |
3447 | }, | |
3448 | ||
f81ec90f | 3449 | [MV88E6161] = { |
107fcc10 | 3450 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, |
f81ec90f VD |
3451 | .family = MV88E6XXX_FAMILY_6165, |
3452 | .name = "Marvell 88E6161", | |
3453 | .num_databases = 4096, | |
3454 | .num_ports = 6, | |
bc393155 | 3455 | .num_internal_phys = 5, |
3cf3c846 | 3456 | .max_vid = 4095, |
9dddd478 | 3457 | .port_base_addr = 0x10, |
a935c052 | 3458 | .global1_addr = 0x1b, |
9069c13a | 3459 | .global2_addr = 0x1c, |
acddbd21 | 3460 | .age_time_coeff = 15000, |
dc30c35b | 3461 | .g1_irqs = 9, |
d6c5e6af | 3462 | .g2_irqs = 10, |
e606ca36 | 3463 | .atu_move_port_mask = 0xf, |
f3645652 | 3464 | .pvt = true, |
b3e05aa1 | 3465 | .multi_chip = true, |
5ebe31d7 | 3466 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3467 | .ops = &mv88e6161_ops, |
f81ec90f VD |
3468 | }, |
3469 | ||
3470 | [MV88E6165] = { | |
107fcc10 | 3471 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, |
f81ec90f VD |
3472 | .family = MV88E6XXX_FAMILY_6165, |
3473 | .name = "Marvell 88E6165", | |
3474 | .num_databases = 4096, | |
3475 | .num_ports = 6, | |
bc393155 | 3476 | .num_internal_phys = 0, |
3cf3c846 | 3477 | .max_vid = 4095, |
9dddd478 | 3478 | .port_base_addr = 0x10, |
a935c052 | 3479 | .global1_addr = 0x1b, |
9069c13a | 3480 | .global2_addr = 0x1c, |
acddbd21 | 3481 | .age_time_coeff = 15000, |
dc30c35b | 3482 | .g1_irqs = 9, |
d6c5e6af | 3483 | .g2_irqs = 10, |
e606ca36 | 3484 | .atu_move_port_mask = 0xf, |
f3645652 | 3485 | .pvt = true, |
b3e05aa1 | 3486 | .multi_chip = true, |
443d5a1b | 3487 | .tag_protocol = DSA_TAG_PROTO_DSA, |
b3469dd8 | 3488 | .ops = &mv88e6165_ops, |
f81ec90f VD |
3489 | }, |
3490 | ||
3491 | [MV88E6171] = { | |
107fcc10 | 3492 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, |
f81ec90f VD |
3493 | .family = MV88E6XXX_FAMILY_6351, |
3494 | .name = "Marvell 88E6171", | |
3495 | .num_databases = 4096, | |
3496 | .num_ports = 7, | |
bc393155 | 3497 | .num_internal_phys = 5, |
3cf3c846 | 3498 | .max_vid = 4095, |
9dddd478 | 3499 | .port_base_addr = 0x10, |
a935c052 | 3500 | .global1_addr = 0x1b, |
9069c13a | 3501 | .global2_addr = 0x1c, |
acddbd21 | 3502 | .age_time_coeff = 15000, |
dc30c35b | 3503 | .g1_irqs = 9, |
d6c5e6af | 3504 | .g2_irqs = 10, |
e606ca36 | 3505 | .atu_move_port_mask = 0xf, |
f3645652 | 3506 | .pvt = true, |
b3e05aa1 | 3507 | .multi_chip = true, |
443d5a1b | 3508 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3509 | .ops = &mv88e6171_ops, |
f81ec90f VD |
3510 | }, |
3511 | ||
3512 | [MV88E6172] = { | |
107fcc10 | 3513 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, |
f81ec90f VD |
3514 | .family = MV88E6XXX_FAMILY_6352, |
3515 | .name = "Marvell 88E6172", | |
3516 | .num_databases = 4096, | |
3517 | .num_ports = 7, | |
bc393155 | 3518 | .num_internal_phys = 5, |
a73ccd61 | 3519 | .num_gpio = 15, |
3cf3c846 | 3520 | .max_vid = 4095, |
9dddd478 | 3521 | .port_base_addr = 0x10, |
a935c052 | 3522 | .global1_addr = 0x1b, |
9069c13a | 3523 | .global2_addr = 0x1c, |
acddbd21 | 3524 | .age_time_coeff = 15000, |
dc30c35b | 3525 | .g1_irqs = 9, |
d6c5e6af | 3526 | .g2_irqs = 10, |
e606ca36 | 3527 | .atu_move_port_mask = 0xf, |
f3645652 | 3528 | .pvt = true, |
b3e05aa1 | 3529 | .multi_chip = true, |
443d5a1b | 3530 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3531 | .ops = &mv88e6172_ops, |
f81ec90f VD |
3532 | }, |
3533 | ||
3534 | [MV88E6175] = { | |
107fcc10 | 3535 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, |
f81ec90f VD |
3536 | .family = MV88E6XXX_FAMILY_6351, |
3537 | .name = "Marvell 88E6175", | |
3538 | .num_databases = 4096, | |
3539 | .num_ports = 7, | |
bc393155 | 3540 | .num_internal_phys = 5, |
3cf3c846 | 3541 | .max_vid = 4095, |
9dddd478 | 3542 | .port_base_addr = 0x10, |
a935c052 | 3543 | .global1_addr = 0x1b, |
9069c13a | 3544 | .global2_addr = 0x1c, |
acddbd21 | 3545 | .age_time_coeff = 15000, |
dc30c35b | 3546 | .g1_irqs = 9, |
d6c5e6af | 3547 | .g2_irqs = 10, |
e606ca36 | 3548 | .atu_move_port_mask = 0xf, |
f3645652 | 3549 | .pvt = true, |
b3e05aa1 | 3550 | .multi_chip = true, |
443d5a1b | 3551 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3552 | .ops = &mv88e6175_ops, |
f81ec90f VD |
3553 | }, |
3554 | ||
3555 | [MV88E6176] = { | |
107fcc10 | 3556 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, |
f81ec90f VD |
3557 | .family = MV88E6XXX_FAMILY_6352, |
3558 | .name = "Marvell 88E6176", | |
3559 | .num_databases = 4096, | |
3560 | .num_ports = 7, | |
bc393155 | 3561 | .num_internal_phys = 5, |
a73ccd61 | 3562 | .num_gpio = 15, |
3cf3c846 | 3563 | .max_vid = 4095, |
9dddd478 | 3564 | .port_base_addr = 0x10, |
a935c052 | 3565 | .global1_addr = 0x1b, |
9069c13a | 3566 | .global2_addr = 0x1c, |
acddbd21 | 3567 | .age_time_coeff = 15000, |
dc30c35b | 3568 | .g1_irqs = 9, |
d6c5e6af | 3569 | .g2_irqs = 10, |
e606ca36 | 3570 | .atu_move_port_mask = 0xf, |
f3645652 | 3571 | .pvt = true, |
b3e05aa1 | 3572 | .multi_chip = true, |
443d5a1b | 3573 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3574 | .ops = &mv88e6176_ops, |
f81ec90f VD |
3575 | }, |
3576 | ||
3577 | [MV88E6185] = { | |
107fcc10 | 3578 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, |
f81ec90f VD |
3579 | .family = MV88E6XXX_FAMILY_6185, |
3580 | .name = "Marvell 88E6185", | |
3581 | .num_databases = 256, | |
3582 | .num_ports = 10, | |
bc393155 | 3583 | .num_internal_phys = 0, |
3cf3c846 | 3584 | .max_vid = 4095, |
9dddd478 | 3585 | .port_base_addr = 0x10, |
a935c052 | 3586 | .global1_addr = 0x1b, |
9069c13a | 3587 | .global2_addr = 0x1c, |
acddbd21 | 3588 | .age_time_coeff = 15000, |
dc30c35b | 3589 | .g1_irqs = 8, |
e606ca36 | 3590 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 3591 | .multi_chip = true, |
443d5a1b | 3592 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3593 | .ops = &mv88e6185_ops, |
f81ec90f VD |
3594 | }, |
3595 | ||
1a3b39ec | 3596 | [MV88E6190] = { |
107fcc10 | 3597 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, |
1a3b39ec AL |
3598 | .family = MV88E6XXX_FAMILY_6390, |
3599 | .name = "Marvell 88E6190", | |
3600 | .num_databases = 4096, | |
3601 | .num_ports = 11, /* 10 + Z80 */ | |
bc393155 | 3602 | .num_internal_phys = 11, |
a73ccd61 | 3603 | .num_gpio = 16, |
931d1822 | 3604 | .max_vid = 8191, |
1a3b39ec AL |
3605 | .port_base_addr = 0x0, |
3606 | .global1_addr = 0x1b, | |
9069c13a | 3607 | .global2_addr = 0x1c, |
443d5a1b | 3608 | .tag_protocol = DSA_TAG_PROTO_DSA, |
b91e055c | 3609 | .age_time_coeff = 3750, |
1a3b39ec | 3610 | .g1_irqs = 9, |
d6c5e6af | 3611 | .g2_irqs = 14, |
f3645652 | 3612 | .pvt = true, |
b3e05aa1 | 3613 | .multi_chip = true, |
e606ca36 | 3614 | .atu_move_port_mask = 0x1f, |
1a3b39ec AL |
3615 | .ops = &mv88e6190_ops, |
3616 | }, | |
3617 | ||
3618 | [MV88E6190X] = { | |
107fcc10 | 3619 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, |
1a3b39ec AL |
3620 | .family = MV88E6XXX_FAMILY_6390, |
3621 | .name = "Marvell 88E6190X", | |
3622 | .num_databases = 4096, | |
3623 | .num_ports = 11, /* 10 + Z80 */ | |
bc393155 | 3624 | .num_internal_phys = 11, |
a73ccd61 | 3625 | .num_gpio = 16, |
931d1822 | 3626 | .max_vid = 8191, |
1a3b39ec AL |
3627 | .port_base_addr = 0x0, |
3628 | .global1_addr = 0x1b, | |
9069c13a | 3629 | .global2_addr = 0x1c, |
b91e055c | 3630 | .age_time_coeff = 3750, |
1a3b39ec | 3631 | .g1_irqs = 9, |
d6c5e6af | 3632 | .g2_irqs = 14, |
e606ca36 | 3633 | .atu_move_port_mask = 0x1f, |
f3645652 | 3634 | .pvt = true, |
b3e05aa1 | 3635 | .multi_chip = true, |
443d5a1b | 3636 | .tag_protocol = DSA_TAG_PROTO_DSA, |
1a3b39ec AL |
3637 | .ops = &mv88e6190x_ops, |
3638 | }, | |
3639 | ||
3640 | [MV88E6191] = { | |
107fcc10 | 3641 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, |
1a3b39ec AL |
3642 | .family = MV88E6XXX_FAMILY_6390, |
3643 | .name = "Marvell 88E6191", | |
3644 | .num_databases = 4096, | |
3645 | .num_ports = 11, /* 10 + Z80 */ | |
bc393155 | 3646 | .num_internal_phys = 11, |
931d1822 | 3647 | .max_vid = 8191, |
1a3b39ec AL |
3648 | .port_base_addr = 0x0, |
3649 | .global1_addr = 0x1b, | |
9069c13a | 3650 | .global2_addr = 0x1c, |
b91e055c | 3651 | .age_time_coeff = 3750, |
443d5a1b | 3652 | .g1_irqs = 9, |
d6c5e6af | 3653 | .g2_irqs = 14, |
e606ca36 | 3654 | .atu_move_port_mask = 0x1f, |
f3645652 | 3655 | .pvt = true, |
b3e05aa1 | 3656 | .multi_chip = true, |
443d5a1b | 3657 | .tag_protocol = DSA_TAG_PROTO_DSA, |
2fa8d3af | 3658 | .ptp_support = true, |
2cf4cefb | 3659 | .ops = &mv88e6191_ops, |
1a3b39ec AL |
3660 | }, |
3661 | ||
f81ec90f | 3662 | [MV88E6240] = { |
107fcc10 | 3663 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, |
f81ec90f VD |
3664 | .family = MV88E6XXX_FAMILY_6352, |
3665 | .name = "Marvell 88E6240", | |
3666 | .num_databases = 4096, | |
3667 | .num_ports = 7, | |
bc393155 | 3668 | .num_internal_phys = 5, |
a73ccd61 | 3669 | .num_gpio = 15, |
3cf3c846 | 3670 | .max_vid = 4095, |
9dddd478 | 3671 | .port_base_addr = 0x10, |
a935c052 | 3672 | .global1_addr = 0x1b, |
9069c13a | 3673 | .global2_addr = 0x1c, |
acddbd21 | 3674 | .age_time_coeff = 15000, |
dc30c35b | 3675 | .g1_irqs = 9, |
d6c5e6af | 3676 | .g2_irqs = 10, |
e606ca36 | 3677 | .atu_move_port_mask = 0xf, |
f3645652 | 3678 | .pvt = true, |
b3e05aa1 | 3679 | .multi_chip = true, |
443d5a1b | 3680 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
2fa8d3af | 3681 | .ptp_support = true, |
b3469dd8 | 3682 | .ops = &mv88e6240_ops, |
f81ec90f VD |
3683 | }, |
3684 | ||
1a3b39ec | 3685 | [MV88E6290] = { |
107fcc10 | 3686 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, |
1a3b39ec AL |
3687 | .family = MV88E6XXX_FAMILY_6390, |
3688 | .name = "Marvell 88E6290", | |
3689 | .num_databases = 4096, | |
3690 | .num_ports = 11, /* 10 + Z80 */ | |
bc393155 | 3691 | .num_internal_phys = 11, |
a73ccd61 | 3692 | .num_gpio = 16, |
931d1822 | 3693 | .max_vid = 8191, |
1a3b39ec AL |
3694 | .port_base_addr = 0x0, |
3695 | .global1_addr = 0x1b, | |
9069c13a | 3696 | .global2_addr = 0x1c, |
b91e055c | 3697 | .age_time_coeff = 3750, |
1a3b39ec | 3698 | .g1_irqs = 9, |
d6c5e6af | 3699 | .g2_irqs = 14, |
e606ca36 | 3700 | .atu_move_port_mask = 0x1f, |
f3645652 | 3701 | .pvt = true, |
b3e05aa1 | 3702 | .multi_chip = true, |
443d5a1b | 3703 | .tag_protocol = DSA_TAG_PROTO_DSA, |
2fa8d3af | 3704 | .ptp_support = true, |
1a3b39ec AL |
3705 | .ops = &mv88e6290_ops, |
3706 | }, | |
3707 | ||
f81ec90f | 3708 | [MV88E6320] = { |
107fcc10 | 3709 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, |
f81ec90f VD |
3710 | .family = MV88E6XXX_FAMILY_6320, |
3711 | .name = "Marvell 88E6320", | |
3712 | .num_databases = 4096, | |
3713 | .num_ports = 7, | |
bc393155 | 3714 | .num_internal_phys = 5, |
a73ccd61 | 3715 | .num_gpio = 15, |
3cf3c846 | 3716 | .max_vid = 4095, |
9dddd478 | 3717 | .port_base_addr = 0x10, |
a935c052 | 3718 | .global1_addr = 0x1b, |
9069c13a | 3719 | .global2_addr = 0x1c, |
acddbd21 | 3720 | .age_time_coeff = 15000, |
dc30c35b | 3721 | .g1_irqs = 8, |
bc393155 | 3722 | .g2_irqs = 10, |
e606ca36 | 3723 | .atu_move_port_mask = 0xf, |
f3645652 | 3724 | .pvt = true, |
b3e05aa1 | 3725 | .multi_chip = true, |
443d5a1b | 3726 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
2fa8d3af | 3727 | .ptp_support = true, |
b3469dd8 | 3728 | .ops = &mv88e6320_ops, |
f81ec90f VD |
3729 | }, |
3730 | ||
3731 | [MV88E6321] = { | |
107fcc10 | 3732 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, |
f81ec90f VD |
3733 | .family = MV88E6XXX_FAMILY_6320, |
3734 | .name = "Marvell 88E6321", | |
3735 | .num_databases = 4096, | |
3736 | .num_ports = 7, | |
bc393155 | 3737 | .num_internal_phys = 5, |
a73ccd61 | 3738 | .num_gpio = 15, |
3cf3c846 | 3739 | .max_vid = 4095, |
9dddd478 | 3740 | .port_base_addr = 0x10, |
a935c052 | 3741 | .global1_addr = 0x1b, |
9069c13a | 3742 | .global2_addr = 0x1c, |
acddbd21 | 3743 | .age_time_coeff = 15000, |
dc30c35b | 3744 | .g1_irqs = 8, |
bc393155 | 3745 | .g2_irqs = 10, |
e606ca36 | 3746 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 3747 | .multi_chip = true, |
443d5a1b | 3748 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
2fa8d3af | 3749 | .ptp_support = true, |
b3469dd8 | 3750 | .ops = &mv88e6321_ops, |
f81ec90f VD |
3751 | }, |
3752 | ||
a75961d0 | 3753 | [MV88E6341] = { |
107fcc10 | 3754 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, |
a75961d0 GC |
3755 | .family = MV88E6XXX_FAMILY_6341, |
3756 | .name = "Marvell 88E6341", | |
3757 | .num_databases = 4096, | |
bc393155 | 3758 | .num_internal_phys = 5, |
a75961d0 | 3759 | .num_ports = 6, |
a73ccd61 | 3760 | .num_gpio = 11, |
3cf3c846 | 3761 | .max_vid = 4095, |
a75961d0 GC |
3762 | .port_base_addr = 0x10, |
3763 | .global1_addr = 0x1b, | |
9069c13a | 3764 | .global2_addr = 0x1c, |
a75961d0 | 3765 | .age_time_coeff = 3750, |
e606ca36 | 3766 | .atu_move_port_mask = 0x1f, |
adfccf11 | 3767 | .g1_irqs = 9, |
d6c5e6af | 3768 | .g2_irqs = 10, |
f3645652 | 3769 | .pvt = true, |
b3e05aa1 | 3770 | .multi_chip = true, |
a75961d0 | 3771 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
2fa8d3af | 3772 | .ptp_support = true, |
a75961d0 GC |
3773 | .ops = &mv88e6341_ops, |
3774 | }, | |
3775 | ||
f81ec90f | 3776 | [MV88E6350] = { |
107fcc10 | 3777 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, |
f81ec90f VD |
3778 | .family = MV88E6XXX_FAMILY_6351, |
3779 | .name = "Marvell 88E6350", | |
3780 | .num_databases = 4096, | |
3781 | .num_ports = 7, | |
bc393155 | 3782 | .num_internal_phys = 5, |
3cf3c846 | 3783 | .max_vid = 4095, |
9dddd478 | 3784 | .port_base_addr = 0x10, |
a935c052 | 3785 | .global1_addr = 0x1b, |
9069c13a | 3786 | .global2_addr = 0x1c, |
acddbd21 | 3787 | .age_time_coeff = 15000, |
dc30c35b | 3788 | .g1_irqs = 9, |
d6c5e6af | 3789 | .g2_irqs = 10, |
e606ca36 | 3790 | .atu_move_port_mask = 0xf, |
f3645652 | 3791 | .pvt = true, |
b3e05aa1 | 3792 | .multi_chip = true, |
443d5a1b | 3793 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3794 | .ops = &mv88e6350_ops, |
f81ec90f VD |
3795 | }, |
3796 | ||
3797 | [MV88E6351] = { | |
107fcc10 | 3798 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, |
f81ec90f VD |
3799 | .family = MV88E6XXX_FAMILY_6351, |
3800 | .name = "Marvell 88E6351", | |
3801 | .num_databases = 4096, | |
3802 | .num_ports = 7, | |
bc393155 | 3803 | .num_internal_phys = 5, |
3cf3c846 | 3804 | .max_vid = 4095, |
9dddd478 | 3805 | .port_base_addr = 0x10, |
a935c052 | 3806 | .global1_addr = 0x1b, |
9069c13a | 3807 | .global2_addr = 0x1c, |
acddbd21 | 3808 | .age_time_coeff = 15000, |
dc30c35b | 3809 | .g1_irqs = 9, |
d6c5e6af | 3810 | .g2_irqs = 10, |
e606ca36 | 3811 | .atu_move_port_mask = 0xf, |
f3645652 | 3812 | .pvt = true, |
b3e05aa1 | 3813 | .multi_chip = true, |
443d5a1b | 3814 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
b3469dd8 | 3815 | .ops = &mv88e6351_ops, |
f81ec90f VD |
3816 | }, |
3817 | ||
3818 | [MV88E6352] = { | |
107fcc10 | 3819 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, |
f81ec90f VD |
3820 | .family = MV88E6XXX_FAMILY_6352, |
3821 | .name = "Marvell 88E6352", | |
3822 | .num_databases = 4096, | |
3823 | .num_ports = 7, | |
bc393155 | 3824 | .num_internal_phys = 5, |
a73ccd61 | 3825 | .num_gpio = 15, |
3cf3c846 | 3826 | .max_vid = 4095, |
9dddd478 | 3827 | .port_base_addr = 0x10, |
a935c052 | 3828 | .global1_addr = 0x1b, |
9069c13a | 3829 | .global2_addr = 0x1c, |
acddbd21 | 3830 | .age_time_coeff = 15000, |
dc30c35b | 3831 | .g1_irqs = 9, |
d6c5e6af | 3832 | .g2_irqs = 10, |
e606ca36 | 3833 | .atu_move_port_mask = 0xf, |
f3645652 | 3834 | .pvt = true, |
b3e05aa1 | 3835 | .multi_chip = true, |
443d5a1b | 3836 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
2fa8d3af | 3837 | .ptp_support = true, |
b3469dd8 | 3838 | .ops = &mv88e6352_ops, |
f81ec90f | 3839 | }, |
1a3b39ec | 3840 | [MV88E6390] = { |
107fcc10 | 3841 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, |
1a3b39ec AL |
3842 | .family = MV88E6XXX_FAMILY_6390, |
3843 | .name = "Marvell 88E6390", | |
3844 | .num_databases = 4096, | |
3845 | .num_ports = 11, /* 10 + Z80 */ | |
bc393155 | 3846 | .num_internal_phys = 11, |
a73ccd61 | 3847 | .num_gpio = 16, |
931d1822 | 3848 | .max_vid = 8191, |
1a3b39ec AL |
3849 | .port_base_addr = 0x0, |
3850 | .global1_addr = 0x1b, | |
9069c13a | 3851 | .global2_addr = 0x1c, |
b91e055c | 3852 | .age_time_coeff = 3750, |
1a3b39ec | 3853 | .g1_irqs = 9, |
d6c5e6af | 3854 | .g2_irqs = 14, |
e606ca36 | 3855 | .atu_move_port_mask = 0x1f, |
f3645652 | 3856 | .pvt = true, |
b3e05aa1 | 3857 | .multi_chip = true, |
443d5a1b | 3858 | .tag_protocol = DSA_TAG_PROTO_DSA, |
2fa8d3af | 3859 | .ptp_support = true, |
1a3b39ec AL |
3860 | .ops = &mv88e6390_ops, |
3861 | }, | |
3862 | [MV88E6390X] = { | |
107fcc10 | 3863 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, |
1a3b39ec AL |
3864 | .family = MV88E6XXX_FAMILY_6390, |
3865 | .name = "Marvell 88E6390X", | |
3866 | .num_databases = 4096, | |
3867 | .num_ports = 11, /* 10 + Z80 */ | |
bc393155 | 3868 | .num_internal_phys = 11, |
a73ccd61 | 3869 | .num_gpio = 16, |
931d1822 | 3870 | .max_vid = 8191, |
1a3b39ec AL |
3871 | .port_base_addr = 0x0, |
3872 | .global1_addr = 0x1b, | |
9069c13a | 3873 | .global2_addr = 0x1c, |
b91e055c | 3874 | .age_time_coeff = 3750, |
1a3b39ec | 3875 | .g1_irqs = 9, |
d6c5e6af | 3876 | .g2_irqs = 14, |
e606ca36 | 3877 | .atu_move_port_mask = 0x1f, |
f3645652 | 3878 | .pvt = true, |
b3e05aa1 | 3879 | .multi_chip = true, |
443d5a1b | 3880 | .tag_protocol = DSA_TAG_PROTO_DSA, |
2fa8d3af | 3881 | .ptp_support = true, |
1a3b39ec AL |
3882 | .ops = &mv88e6390x_ops, |
3883 | }, | |
f81ec90f VD |
3884 | }; |
3885 | ||
5f7c0367 | 3886 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
b9b37713 | 3887 | { |
a439c061 | 3888 | int i; |
b9b37713 | 3889 | |
5f7c0367 VD |
3890 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
3891 | if (mv88e6xxx_table[i].prod_num == prod_num) | |
3892 | return &mv88e6xxx_table[i]; | |
b9b37713 | 3893 | |
b9b37713 VD |
3894 | return NULL; |
3895 | } | |
3896 | ||
fad09c73 | 3897 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
bc46a3d5 VD |
3898 | { |
3899 | const struct mv88e6xxx_info *info; | |
8f6345b2 VD |
3900 | unsigned int prod_num, rev; |
3901 | u16 id; | |
3902 | int err; | |
bc46a3d5 | 3903 | |
8f6345b2 | 3904 | mutex_lock(&chip->reg_lock); |
107fcc10 | 3905 | err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); |
8f6345b2 VD |
3906 | mutex_unlock(&chip->reg_lock); |
3907 | if (err) | |
3908 | return err; | |
bc46a3d5 | 3909 | |
107fcc10 VD |
3910 | prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; |
3911 | rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; | |
bc46a3d5 VD |
3912 | |
3913 | info = mv88e6xxx_lookup_info(prod_num); | |
3914 | if (!info) | |
3915 | return -ENODEV; | |
3916 | ||
caac8545 | 3917 | /* Update the compatible info with the probed one */ |
fad09c73 | 3918 | chip->info = info; |
bc46a3d5 | 3919 | |
ca070c10 VD |
3920 | err = mv88e6xxx_g2_require(chip); |
3921 | if (err) | |
3922 | return err; | |
3923 | ||
fad09c73 VD |
3924 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
3925 | chip->info->prod_num, chip->info->name, rev); | |
bc46a3d5 VD |
3926 | |
3927 | return 0; | |
3928 | } | |
3929 | ||
fad09c73 | 3930 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
469d729f | 3931 | { |
fad09c73 | 3932 | struct mv88e6xxx_chip *chip; |
469d729f | 3933 | |
fad09c73 VD |
3934 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
3935 | if (!chip) | |
469d729f VD |
3936 | return NULL; |
3937 | ||
fad09c73 | 3938 | chip->dev = dev; |
469d729f | 3939 | |
fad09c73 | 3940 | mutex_init(&chip->reg_lock); |
a3c53be5 | 3941 | INIT_LIST_HEAD(&chip->mdios); |
469d729f | 3942 | |
fad09c73 | 3943 | return chip; |
469d729f VD |
3944 | } |
3945 | ||
fad09c73 | 3946 | static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, |
4a70c4ab VD |
3947 | struct mii_bus *bus, int sw_addr) |
3948 | { | |
914b32f6 | 3949 | if (sw_addr == 0) |
fad09c73 | 3950 | chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; |
b3e05aa1 | 3951 | else if (chip->info->multi_chip) |
fad09c73 | 3952 | chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; |
914b32f6 VD |
3953 | else |
3954 | return -EINVAL; | |
3955 | ||
fad09c73 VD |
3956 | chip->bus = bus; |
3957 | chip->sw_addr = sw_addr; | |
4a70c4ab VD |
3958 | |
3959 | return 0; | |
3960 | } | |
3961 | ||
5ed4e3eb FF |
3962 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, |
3963 | int port) | |
7b314362 | 3964 | { |
04bed143 | 3965 | struct mv88e6xxx_chip *chip = ds->priv; |
2bbb33be | 3966 | |
443d5a1b | 3967 | return chip->info->tag_protocol; |
7b314362 AL |
3968 | } |
3969 | ||
2a93c1a3 | 3970 | #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) |
fcdce7d0 AL |
3971 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
3972 | struct device *host_dev, int sw_addr, | |
3973 | void **priv) | |
a77d43f1 | 3974 | { |
fad09c73 | 3975 | struct mv88e6xxx_chip *chip; |
a439c061 | 3976 | struct mii_bus *bus; |
b516d453 | 3977 | int err; |
a77d43f1 | 3978 | |
a439c061 | 3979 | bus = dsa_host_dev_to_mii_bus(host_dev); |
c156913b AL |
3980 | if (!bus) |
3981 | return NULL; | |
3982 | ||
fad09c73 VD |
3983 | chip = mv88e6xxx_alloc_chip(dsa_dev); |
3984 | if (!chip) | |
469d729f VD |
3985 | return NULL; |
3986 | ||
caac8545 | 3987 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
fad09c73 | 3988 | chip->info = &mv88e6xxx_table[MV88E6085]; |
caac8545 | 3989 | |
fad09c73 | 3990 | err = mv88e6xxx_smi_init(chip, bus, sw_addr); |
4a70c4ab VD |
3991 | if (err) |
3992 | goto free; | |
3993 | ||
fad09c73 | 3994 | err = mv88e6xxx_detect(chip); |
bc46a3d5 | 3995 | if (err) |
469d729f | 3996 | goto free; |
a439c061 | 3997 | |
dc30c35b AL |
3998 | mutex_lock(&chip->reg_lock); |
3999 | err = mv88e6xxx_switch_reset(chip); | |
4000 | mutex_unlock(&chip->reg_lock); | |
4001 | if (err) | |
4002 | goto free; | |
4003 | ||
e57e5e77 VD |
4004 | mv88e6xxx_phy_init(chip); |
4005 | ||
a3c53be5 | 4006 | err = mv88e6xxx_mdios_register(chip, NULL); |
b516d453 | 4007 | if (err) |
469d729f | 4008 | goto free; |
b516d453 | 4009 | |
fad09c73 | 4010 | *priv = chip; |
a439c061 | 4011 | |
fad09c73 | 4012 | return chip->info->name; |
469d729f | 4013 | free: |
fad09c73 | 4014 | devm_kfree(dsa_dev, chip); |
469d729f VD |
4015 | |
4016 | return NULL; | |
a77d43f1 | 4017 | } |
2a93c1a3 | 4018 | #endif |
a77d43f1 | 4019 | |
7df8fbdd | 4020 | static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, |
3709aadc | 4021 | const struct switchdev_obj_port_mdb *mdb) |
7df8fbdd VD |
4022 | { |
4023 | /* We don't need any dynamic resource from the kernel (yet), | |
4024 | * so skip the prepare phase. | |
4025 | */ | |
4026 | ||
4027 | return 0; | |
4028 | } | |
4029 | ||
4030 | static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, | |
3709aadc | 4031 | const struct switchdev_obj_port_mdb *mdb) |
7df8fbdd | 4032 | { |
04bed143 | 4033 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
4034 | |
4035 | mutex_lock(&chip->reg_lock); | |
4036 | if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
27c0e600 | 4037 | MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) |
774439e5 VD |
4038 | dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", |
4039 | port); | |
7df8fbdd VD |
4040 | mutex_unlock(&chip->reg_lock); |
4041 | } | |
4042 | ||
4043 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, | |
4044 | const struct switchdev_obj_port_mdb *mdb) | |
4045 | { | |
04bed143 | 4046 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
4047 | int err; |
4048 | ||
4049 | mutex_lock(&chip->reg_lock); | |
4050 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, | |
27c0e600 | 4051 | MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); |
7df8fbdd VD |
4052 | mutex_unlock(&chip->reg_lock); |
4053 | ||
4054 | return err; | |
4055 | } | |
4056 | ||
a82f67af | 4057 | static const struct dsa_switch_ops mv88e6xxx_switch_ops = { |
2a93c1a3 | 4058 | #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) |
fcdce7d0 | 4059 | .probe = mv88e6xxx_drv_probe, |
2a93c1a3 | 4060 | #endif |
7b314362 | 4061 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
f81ec90f | 4062 | .setup = mv88e6xxx_setup, |
f81ec90f VD |
4063 | .adjust_link = mv88e6xxx_adjust_link, |
4064 | .get_strings = mv88e6xxx_get_strings, | |
4065 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
4066 | .get_sset_count = mv88e6xxx_get_sset_count, | |
04aca993 AL |
4067 | .port_enable = mv88e6xxx_port_enable, |
4068 | .port_disable = mv88e6xxx_port_disable, | |
08f50061 VD |
4069 | .get_mac_eee = mv88e6xxx_get_mac_eee, |
4070 | .set_mac_eee = mv88e6xxx_set_mac_eee, | |
f8cd8753 | 4071 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
f81ec90f VD |
4072 | .get_eeprom = mv88e6xxx_get_eeprom, |
4073 | .set_eeprom = mv88e6xxx_set_eeprom, | |
4074 | .get_regs_len = mv88e6xxx_get_regs_len, | |
4075 | .get_regs = mv88e6xxx_get_regs, | |
2cfcd964 | 4076 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
f81ec90f VD |
4077 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
4078 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
4079 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, | |
749efcb8 | 4080 | .port_fast_age = mv88e6xxx_port_fast_age, |
f81ec90f VD |
4081 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
4082 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
4083 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
4084 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
f81ec90f VD |
4085 | .port_fdb_add = mv88e6xxx_port_fdb_add, |
4086 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
4087 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
7df8fbdd VD |
4088 | .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, |
4089 | .port_mdb_add = mv88e6xxx_port_mdb_add, | |
4090 | .port_mdb_del = mv88e6xxx_port_mdb_del, | |
aec5ac88 VD |
4091 | .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, |
4092 | .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, | |
c6fe0ad2 BS |
4093 | .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, |
4094 | .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, | |
4095 | .port_txtstamp = mv88e6xxx_port_txtstamp, | |
4096 | .port_rxtstamp = mv88e6xxx_port_rxtstamp, | |
4097 | .get_ts_info = mv88e6xxx_get_ts_info, | |
f81ec90f VD |
4098 | }; |
4099 | ||
ab3d408d FF |
4100 | static struct dsa_switch_driver mv88e6xxx_switch_drv = { |
4101 | .ops = &mv88e6xxx_switch_ops, | |
4102 | }; | |
4103 | ||
55ed0ce0 | 4104 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 4105 | { |
fad09c73 | 4106 | struct device *dev = chip->dev; |
b7e66a5f VD |
4107 | struct dsa_switch *ds; |
4108 | ||
73b1204d | 4109 | ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); |
b7e66a5f VD |
4110 | if (!ds) |
4111 | return -ENOMEM; | |
4112 | ||
fad09c73 | 4113 | ds->priv = chip; |
9d490b4e | 4114 | ds->ops = &mv88e6xxx_switch_ops; |
9ff74f24 VD |
4115 | ds->ageing_time_min = chip->info->age_time_coeff; |
4116 | ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; | |
b7e66a5f VD |
4117 | |
4118 | dev_set_drvdata(dev, ds); | |
4119 | ||
23c9ee49 | 4120 | return dsa_register_switch(ds); |
b7e66a5f VD |
4121 | } |
4122 | ||
fad09c73 | 4123 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 4124 | { |
fad09c73 | 4125 | dsa_unregister_switch(chip->ds); |
b7e66a5f VD |
4126 | } |
4127 | ||
57d32310 | 4128 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
98e67308 | 4129 | { |
14c7b3c3 | 4130 | struct device *dev = &mdiodev->dev; |
f8cd8753 | 4131 | struct device_node *np = dev->of_node; |
caac8545 | 4132 | const struct mv88e6xxx_info *compat_info; |
fad09c73 | 4133 | struct mv88e6xxx_chip *chip; |
f8cd8753 | 4134 | u32 eeprom_len; |
52638f71 | 4135 | int err; |
14c7b3c3 | 4136 | |
caac8545 VD |
4137 | compat_info = of_device_get_match_data(dev); |
4138 | if (!compat_info) | |
4139 | return -EINVAL; | |
4140 | ||
fad09c73 VD |
4141 | chip = mv88e6xxx_alloc_chip(dev); |
4142 | if (!chip) | |
14c7b3c3 AL |
4143 | return -ENOMEM; |
4144 | ||
fad09c73 | 4145 | chip->info = compat_info; |
caac8545 | 4146 | |
fad09c73 | 4147 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
4a70c4ab VD |
4148 | if (err) |
4149 | return err; | |
14c7b3c3 | 4150 | |
b4308f04 AL |
4151 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); |
4152 | if (IS_ERR(chip->reset)) | |
4153 | return PTR_ERR(chip->reset); | |
4154 | ||
fad09c73 | 4155 | err = mv88e6xxx_detect(chip); |
bc46a3d5 VD |
4156 | if (err) |
4157 | return err; | |
14c7b3c3 | 4158 | |
e57e5e77 VD |
4159 | mv88e6xxx_phy_init(chip); |
4160 | ||
ee4dc2e7 | 4161 | if (chip->info->ops->get_eeprom && |
f8cd8753 | 4162 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) |
fad09c73 | 4163 | chip->eeprom_len = eeprom_len; |
f8cd8753 | 4164 | |
dc30c35b AL |
4165 | mutex_lock(&chip->reg_lock); |
4166 | err = mv88e6xxx_switch_reset(chip); | |
4167 | mutex_unlock(&chip->reg_lock); | |
4168 | if (err) | |
4169 | goto out; | |
4170 | ||
4171 | chip->irq = of_irq_get(np, 0); | |
4172 | if (chip->irq == -EPROBE_DEFER) { | |
4173 | err = chip->irq; | |
4174 | goto out; | |
4175 | } | |
4176 | ||
294d711e AL |
4177 | /* Has to be performed before the MDIO bus is created, because |
4178 | * the PHYs will link there interrupts to these interrupt | |
4179 | * controllers | |
4180 | */ | |
4181 | mutex_lock(&chip->reg_lock); | |
4182 | if (chip->irq > 0) | |
dc30c35b | 4183 | err = mv88e6xxx_g1_irq_setup(chip); |
294d711e AL |
4184 | else |
4185 | err = mv88e6xxx_irq_poll_setup(chip); | |
4186 | mutex_unlock(&chip->reg_lock); | |
0977644c | 4187 | |
294d711e AL |
4188 | if (err) |
4189 | goto out; | |
62eb1162 | 4190 | |
294d711e AL |
4191 | if (chip->info->g2_irqs > 0) { |
4192 | err = mv88e6xxx_g2_irq_setup(chip); | |
62eb1162 | 4193 | if (err) |
294d711e | 4194 | goto out_g1_irq; |
dc30c35b AL |
4195 | } |
4196 | ||
294d711e AL |
4197 | err = mv88e6xxx_g1_atu_prob_irq_setup(chip); |
4198 | if (err) | |
4199 | goto out_g2_irq; | |
4200 | ||
4201 | err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); | |
4202 | if (err) | |
4203 | goto out_g1_atu_prob_irq; | |
4204 | ||
a3c53be5 | 4205 | err = mv88e6xxx_mdios_register(chip, np); |
b516d453 | 4206 | if (err) |
62eb1162 | 4207 | goto out_g1_vtu_prob_irq; |
b516d453 | 4208 | |
55ed0ce0 | 4209 | err = mv88e6xxx_register_switch(chip); |
dc30c35b AL |
4210 | if (err) |
4211 | goto out_mdio; | |
83c0afae | 4212 | |
98e67308 | 4213 | return 0; |
dc30c35b AL |
4214 | |
4215 | out_mdio: | |
a3c53be5 | 4216 | mv88e6xxx_mdios_unregister(chip); |
62eb1162 | 4217 | out_g1_vtu_prob_irq: |
294d711e | 4218 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
0977644c | 4219 | out_g1_atu_prob_irq: |
294d711e | 4220 | mv88e6xxx_g1_atu_prob_irq_free(chip); |
dc30c35b | 4221 | out_g2_irq: |
294d711e | 4222 | if (chip->info->g2_irqs > 0) |
dc30c35b AL |
4223 | mv88e6xxx_g2_irq_free(chip); |
4224 | out_g1_irq: | |
294d711e AL |
4225 | mutex_lock(&chip->reg_lock); |
4226 | if (chip->irq > 0) | |
46712644 | 4227 | mv88e6xxx_g1_irq_free(chip); |
294d711e AL |
4228 | else |
4229 | mv88e6xxx_irq_poll_free(chip); | |
4230 | mutex_unlock(&chip->reg_lock); | |
dc30c35b AL |
4231 | out: |
4232 | return err; | |
98e67308 | 4233 | } |
14c7b3c3 AL |
4234 | |
4235 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) | |
4236 | { | |
4237 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
04bed143 | 4238 | struct mv88e6xxx_chip *chip = ds->priv; |
14c7b3c3 | 4239 | |
c6fe0ad2 BS |
4240 | if (chip->info->ptp_support) { |
4241 | mv88e6xxx_hwtstamp_free(chip); | |
2fa8d3af | 4242 | mv88e6xxx_ptp_free(chip); |
c6fe0ad2 | 4243 | } |
2fa8d3af | 4244 | |
930188ce | 4245 | mv88e6xxx_phy_destroy(chip); |
fad09c73 | 4246 | mv88e6xxx_unregister_switch(chip); |
a3c53be5 | 4247 | mv88e6xxx_mdios_unregister(chip); |
dc30c35b | 4248 | |
76f38f1f AL |
4249 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
4250 | mv88e6xxx_g1_atu_prob_irq_free(chip); | |
4251 | ||
4252 | if (chip->info->g2_irqs > 0) | |
4253 | mv88e6xxx_g2_irq_free(chip); | |
4254 | ||
4255 | mutex_lock(&chip->reg_lock); | |
4256 | if (chip->irq > 0) | |
46712644 | 4257 | mv88e6xxx_g1_irq_free(chip); |
76f38f1f AL |
4258 | else |
4259 | mv88e6xxx_irq_poll_free(chip); | |
4260 | mutex_unlock(&chip->reg_lock); | |
14c7b3c3 AL |
4261 | } |
4262 | ||
4263 | static const struct of_device_id mv88e6xxx_of_match[] = { | |
caac8545 VD |
4264 | { |
4265 | .compatible = "marvell,mv88e6085", | |
4266 | .data = &mv88e6xxx_table[MV88E6085], | |
4267 | }, | |
1a3b39ec AL |
4268 | { |
4269 | .compatible = "marvell,mv88e6190", | |
4270 | .data = &mv88e6xxx_table[MV88E6190], | |
4271 | }, | |
14c7b3c3 AL |
4272 | { /* sentinel */ }, |
4273 | }; | |
4274 | ||
4275 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); | |
4276 | ||
4277 | static struct mdio_driver mv88e6xxx_driver = { | |
4278 | .probe = mv88e6xxx_probe, | |
4279 | .remove = mv88e6xxx_remove, | |
4280 | .mdiodrv.driver = { | |
4281 | .name = "mv88e6085", | |
4282 | .of_match_table = mv88e6xxx_of_match, | |
4283 | }, | |
4284 | }; | |
4285 | ||
4286 | static int __init mv88e6xxx_init(void) | |
4287 | { | |
ab3d408d | 4288 | register_switch_driver(&mv88e6xxx_switch_drv); |
14c7b3c3 AL |
4289 | return mdio_driver_register(&mv88e6xxx_driver); |
4290 | } | |
98e67308 BH |
4291 | module_init(mv88e6xxx_init); |
4292 | ||
4293 | static void __exit mv88e6xxx_cleanup(void) | |
4294 | { | |
14c7b3c3 | 4295 | mdio_driver_unregister(&mv88e6xxx_driver); |
ab3d408d | 4296 | unregister_switch_driver(&mv88e6xxx_switch_drv); |
98e67308 BH |
4297 | } |
4298 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
4299 | |
4300 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
4301 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
4302 | MODULE_LICENSE("GPL"); |