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net: dsa: mv88e6xxx: reorder 88E6341 definitions
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
ee26a228
AL		 225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
efb3e74d
AL		 228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
ee26a228
AL		 232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
efb3e74d
AL		 235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
a3c53be5
AL		 239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
e57e5e77
VD		 251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 255 struct mii_bus *bus;
e57e5e77 256
a3c53be5
AL		 257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
e57e5e77
VD		 259 return -EOPNOTSUPP;
260
a3c53be5 261 if (!chip->info->ops->phy_read)
ee26a228
AL		 262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 271 struct mii_bus *bus;
e57e5e77 272
a3c53be5
AL		 273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
e57e5e77
VD		 275 return -EOPNOTSUPP;
276
a3c53be5 277 if (!chip->info->ops->phy_write)
ee26a228
AL		 278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 281}
282
09cb7dfd
VD		 283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
dc30c35b
AL		 351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
3460a577
AL		 452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
dc30c35b 459
5edef2f2 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 462 irq_dispose_mapping(virq);
463 }
464
a3db3d3a 465 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
3dd0ef05
AL		 470 int err, irq, virq;
471 u16 reg, mask;
dc30c35b
AL		 472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
3dd0ef05 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 487 if (err)
3dd0ef05 488 goto out_mapping;
dc30c35b 489
3dd0ef05 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 491
3dd0ef05 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 493 if (err)
3dd0ef05 494 goto out_disable;
dc30c35b
AL		 495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
3dd0ef05 499 goto out_disable;
dc30c35b
AL		 500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
3dd0ef05 506 goto out_disable;
dc30c35b
AL		 507
508 return 0;
509
3dd0ef05
AL		 510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 521
522 return err;
523}
524
ec561276 525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 526{
6441e669 527 int i;
2d79af6e 528
6441e669 529 for (i = 0; i < 16; i++) {
2d79af6e
VD		 530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
30853553 543 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 544 return -ETIMEDOUT;
545}
546
f22ab641 547/* Indirect write to single pointer-data register with an Update bit */
ec561276 548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 549{
550 u16 val;
0f02b4f7 551 int err;
f22ab641
VD		 552
553 /* Wait until the previous operation is completed */
0f02b4f7
AL		 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
f22ab641
VD		 557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
a935c052 564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 565{
a199d8b6
VD		 566 if (!chip->info->ops->ppu_disable)
567 return 0;
2e5f0320 568
a199d8b6 569 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 570}
571
fad09c73 572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 573{
a199d8b6
VD		 574 if (!chip->info->ops->ppu_enable)
575 return 0;
2e5f0320 576
a199d8b6 577 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
fad09c73 582 struct mv88e6xxx_chip *chip;
2e5f0320 583
fad09c73 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 585
fad09c73 586 mutex_lock(&chip->reg_lock);
762eb67b 587
fad09c73
VD		 588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
2e5f0320 592 }
762eb67b 593
fad09c73 594 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
fad09c73 599 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 600
fad09c73 601 schedule_work(&chip->ppu_work);
2e5f0320
LB		 602}
603
fad09c73 604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 605{
2e5f0320
LB		 606 int ret;
607
fad09c73 608 mutex_lock(&chip->ppu_mutex);
2e5f0320 609
3675c8d7 610 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
fad09c73
VD		 615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
85686581 617 if (ret < 0) {
fad09c73 618 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 619 return ret;
620 }
fad09c73 621 chip->ppu_disabled = 1;
2e5f0320 622 } else {
fad09c73 623 del_timer(&chip->ppu_timer);
85686581 624 ret = 0;
2e5f0320
LB		 625 }
626
627 return ret;
628}
629
fad09c73 630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 631{
3675c8d7 632 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 635}
636
fad09c73 637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 638{
fad09c73
VD		 639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
2e5f0320
LB		 643}
644
930188ce
AL		 645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
ee26a228
AL		 650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
2e5f0320 653{
e57e5e77 654 int err;
2e5f0320 655
e57e5e77
VD		 656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 659 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 660 }
661
e57e5e77 662 return err;
2e5f0320
LB		 663}
664
ee26a228
AL		 665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 688}
689
a75961d0
GC		 690static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
691{
692 return chip->info->family == MV88E6XXX_FAMILY_6341;
693}
694
fad09c73 695static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 696{
fad09c73 697 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 698}
699
fad09c73 700static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 703}
704
d78343d2
VD		 705static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
706 int link, int speed, int duplex,
707 phy_interface_t mode)
708{
709 int err;
710
711 if (!chip->info->ops->port_set_link)
712 return 0;
713
714 /* Port's MAC control must not be changed unless the link is down */
715 err = chip->info->ops->port_set_link(chip, port, 0);
716 if (err)
717 return err;
718
719 if (chip->info->ops->port_set_speed) {
720 err = chip->info->ops->port_set_speed(chip, port, speed);
721 if (err && err != -EOPNOTSUPP)
722 goto restore_link;
723 }
724
725 if (chip->info->ops->port_set_duplex) {
726 err = chip->info->ops->port_set_duplex(chip, port, duplex);
727 if (err && err != -EOPNOTSUPP)
728 goto restore_link;
729 }
730
731 if (chip->info->ops->port_set_rgmii_delay) {
732 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
733 if (err && err != -EOPNOTSUPP)
734 goto restore_link;
735 }
736
f39908d3
AL		 737 if (chip->info->ops->port_set_cmode) {
738 err = chip->info->ops->port_set_cmode(chip, port, mode);
739 if (err && err != -EOPNOTSUPP)
740 goto restore_link;
741 }
742
d78343d2
VD		 743 err = 0;
744restore_link:
745 if (chip->info->ops->port_set_link(chip, port, link))
746 netdev_err(chip->ds->ports[port].netdev,
747 "failed to restore MAC's link\n");
748
749 return err;
750}
751
dea87024
AL		 752/* We expect the switch to perform auto negotiation if there is a real
753 * phy. However, in the case of a fixed link phy, we force the port
754 * settings from the fixed link settings.
755 */
f81ec90f
VD		 756static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
757 struct phy_device *phydev)
dea87024 758{
04bed143 759 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 760 int err;
dea87024
AL		 761
762 if (!phy_is_pseudo_fixed_link(phydev))
763 return;
764
fad09c73 765 mutex_lock(&chip->reg_lock);
d78343d2
VD		 766 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
767 phydev->duplex, phydev->interface);
fad09c73 768 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 769
770 if (err && err != -EOPNOTSUPP)
771 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 772}
773
a605a0fe 774static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 775{
a605a0fe
AL		 776 if (!chip->info->ops->stats_snapshot)
777 return -EOPNOTSUPP;
91da11f8 778
a605a0fe 779 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 780}
781
e413e7e1 782static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 783 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
784 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
785 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
786 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
787 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
788 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
789 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
790 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
791 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
792 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
793 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
794 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
795 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
796 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
797 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
798 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
799 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
800 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
801 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
802 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
803 { "single", 4, 0x14, STATS_TYPE_BANK0, },
804 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
805 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
806 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
807 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
808 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
809 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
810 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
811 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
812 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
813 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
814 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
815 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
816 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
817 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
818 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
819 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
820 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
821 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
822 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
823 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
824 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
825 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
826 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
827 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
828 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
829 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
830 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
831 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
832 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
833 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
834 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
835 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
836 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
837 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
838 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
839 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
840 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
841 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 842};
843
fad09c73 844static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 845 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 846 int port, u16 bank1_select,
847 u16 histogram)
80c4627b 848{
80c4627b
AL		 849 u32 low;
850 u32 high = 0;
dfafe449 851 u16 reg = 0;
0e7b9925 852 int err;
80c4627b
AL		 853 u64 value;
854
f5e2ed02 855 switch (s->type) {
dfafe449 856 case STATS_TYPE_PORT:
0e7b9925
AL		 857 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
858 if (err)
80c4627b
AL		 859 return UINT64_MAX;
860
0e7b9925 861 low = reg;
80c4627b 862 if (s->sizeof_stat == 4) {
0e7b9925
AL		 863 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
864 if (err)
80c4627b 865 return UINT64_MAX;
0e7b9925 866 high = reg;
80c4627b 867 }
f5e2ed02 868 break;
dfafe449 869 case STATS_TYPE_BANK1:
e0d8b615 870 reg = bank1_select;
dfafe449
AL		 871 /* fall through */
872 case STATS_TYPE_BANK0:
e0d8b615 873 reg |= s->reg | histogram;
7f9ef3af 874 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 875 if (s->sizeof_stat == 8)
7f9ef3af 876 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 877 }
878 value = (((u64)high) << 16) | low;
879 return value;
880}
881
dfafe449
AL		 882static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
883 uint8_t *data, int types)
91da11f8 884{
f5e2ed02
AL		 885 struct mv88e6xxx_hw_stat *stat;
886 int i, j;
91da11f8 887
f5e2ed02
AL		 888 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
889 stat = &mv88e6xxx_hw_stats[i];
dfafe449 890 if (stat->type & types) {
f5e2ed02
AL		 891 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
892 ETH_GSTRING_LEN);
893 j++;
894 }
91da11f8 895 }
e413e7e1
AL		 896}
897
dfafe449
AL		 898static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
899 uint8_t *data)
900{
901 mv88e6xxx_stats_get_strings(chip, data,
902 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
903}
904
905static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
906 uint8_t *data)
907{
908 mv88e6xxx_stats_get_strings(chip, data,
909 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
910}
911
912static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
913 uint8_t *data)
e413e7e1 914{
04bed143 915 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 916
917 if (chip->info->ops->stats_get_strings)
918 chip->info->ops->stats_get_strings(chip, data);
919}
920
921static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
922 int types)
923{
f5e2ed02
AL		 924 struct mv88e6xxx_hw_stat *stat;
925 int i, j;
926
927 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
928 stat = &mv88e6xxx_hw_stats[i];
dfafe449 929 if (stat->type & types)
f5e2ed02
AL		 930 j++;
931 }
932 return j;
e413e7e1
AL		 933}
934
dfafe449
AL		 935static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
936{
937 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
938 STATS_TYPE_PORT);
939}
940
941static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
942{
943 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
944 STATS_TYPE_BANK1);
945}
946
947static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
948{
949 struct mv88e6xxx_chip *chip = ds->priv;
950
951 if (chip->info->ops->stats_get_sset_count)
952 return chip->info->ops->stats_get_sset_count(chip);
953
954 return 0;
955}
956
052f947f 957static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 958 uint64_t *data, int types,
959 u16 bank1_select, u16 histogram)
052f947f
AL		 960{
961 struct mv88e6xxx_hw_stat *stat;
962 int i, j;
963
964 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
965 stat = &mv88e6xxx_hw_stats[i];
966 if (stat->type & types) {
e0d8b615
AL		 967 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
968 bank1_select,
969 histogram);
052f947f
AL		 970 j++;
971 }
972 }
973}
974
975static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
976 uint64_t *data)
977{
978 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 979 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
980 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 981}
982
983static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
984 uint64_t *data)
985{
986 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 987 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
988 GLOBAL_STATS_OP_BANK_1_BIT_9,
989 GLOBAL_STATS_OP_HIST_RX_TX);
990}
991
992static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
993 uint64_t *data)
994{
995 return mv88e6xxx_stats_get_stats(chip, port, data,
996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
997 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 998}
999
1000static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1001 uint64_t *data)
1002{
1003 if (chip->info->ops->stats_get_stats)
1004 chip->info->ops->stats_get_stats(chip, port, data);
1005}
1006
f81ec90f
VD		 1007static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1008 uint64_t *data)
e413e7e1 1009{
04bed143 1010 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1011 int ret;
f5e2ed02 1012
fad09c73 1013 mutex_lock(&chip->reg_lock);
f5e2ed02 1014
a605a0fe 1015 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1016 if (ret < 0) {
fad09c73 1017 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1018 return;
1019 }
052f947f
AL		 1020
1021 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1022
fad09c73 1023 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1024}
1025
de227387
AL		 1026static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1027{
1028 if (chip->info->ops->stats_set_histogram)
1029 return chip->info->ops->stats_set_histogram(chip);
1030
1031 return 0;
1032}
1033
f81ec90f 1034static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1035{
1036 return 32 * sizeof(u16);
1037}
1038
f81ec90f
VD		 1039static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1040 struct ethtool_regs *regs, void *_p)
a1ab91f3 1041{
04bed143 1042 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1043 int err;
1044 u16 reg;
a1ab91f3
GR		 1045 u16 *p = _p;
1046 int i;
1047
1048 regs->version = 0;
1049
1050 memset(p, 0xff, 32 * sizeof(u16));
1051
fad09c73 1052 mutex_lock(&chip->reg_lock);
23062513 1053
a1ab91f3 1054 for (i = 0; i < 32; i++) {
a1ab91f3 1055
0e7b9925
AL		 1056 err = mv88e6xxx_port_read(chip, port, i, &reg);
1057 if (!err)
1058 p[i] = reg;
a1ab91f3 1059 }
23062513 1060
fad09c73 1061 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1062}
1063
f81ec90f
VD		 1064static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1065 struct ethtool_eee *e)
11b3b45d 1066{
04bed143 1067 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1068 u16 reg;
1069 int err;
11b3b45d 1070
fad09c73 1071 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1072 return -EOPNOTSUPP;
1073
fad09c73 1074 mutex_lock(&chip->reg_lock);
2f40c698 1075
9c93829c
VD		 1076 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1077 if (err)
2f40c698 1078 goto out;
11b3b45d
GR		 1079
1080 e->eee_enabled = !!(reg & 0x0200);
1081 e->tx_lpi_enabled = !!(reg & 0x0100);
1082
0e7b9925 1083 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1084 if (err)
2f40c698 1085 goto out;
11b3b45d 1086
cca8b133 1087 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1088out:
fad09c73 1089 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1090
1091 return err;
11b3b45d
GR		 1092}
1093
f81ec90f
VD		 1094static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1095 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1096{
04bed143 1097 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1098 u16 reg;
1099 int err;
11b3b45d 1100
fad09c73 1101 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1102 return -EOPNOTSUPP;
1103
fad09c73 1104 mutex_lock(&chip->reg_lock);
11b3b45d 1105
9c93829c
VD		 1106 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1107 if (err)
2f40c698
AL		 1108 goto out;
1109
9c93829c 1110 reg &= ~0x0300;
2f40c698
AL		 1111 if (e->eee_enabled)
1112 reg |= 0x0200;
1113 if (e->tx_lpi_enabled)
1114 reg |= 0x0100;
1115
9c93829c 1116 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1117out:
fad09c73 1118 mutex_unlock(&chip->reg_lock);
2f40c698 1119
9c93829c 1120 return err;
11b3b45d
GR		 1121}
1122
fad09c73 1123static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1124{
fad09c73 1125 struct dsa_switch *ds = chip->ds;
fae8a25e 1126 struct net_device *bridge = ds->ports[port].bridge_dev;
b7666efe 1127 u16 output_ports = 0;
b7666efe
VD		 1128 int i;
1129
1130 /* allow CPU port or DSA link(s) to send frames to every port */
1131 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1132 output_ports = ~0;
b7666efe 1133 } else {
370b4ffb 1134 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1135 /* allow sending frames to every group member */
fae8a25e 1136 if (bridge && ds->ports[i].bridge_dev == bridge)
b7666efe
VD		 1137 output_ports |= BIT(i);
1138
1139 /* allow sending frames to CPU port and DSA link(s) */
1140 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1141 output_ports |= BIT(i);
1142 }
1143 }
1144
1145 /* prevent frames from going back out of the port they came in on */
1146 output_ports &= ~BIT(port);
facd95b2 1147
5a7921f4 1148 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1149}
1150
f81ec90f
VD		 1151static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1152 u8 state)
facd95b2 1153{
04bed143 1154 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1155 int stp_state;
553eb544 1156 int err;
facd95b2
GR		 1157
1158 switch (state) {
1159 case BR_STATE_DISABLED:
cca8b133 1160 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1161 break;
1162 case BR_STATE_BLOCKING:
1163 case BR_STATE_LISTENING:
cca8b133 1164 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1165 break;
1166 case BR_STATE_LEARNING:
cca8b133 1167 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1168 break;
1169 case BR_STATE_FORWARDING:
1170 default:
cca8b133 1171 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1172 break;
1173 }
1174
fad09c73 1175 mutex_lock(&chip->reg_lock);
e28def33 1176 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1177 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1178
1179 if (err)
e28def33 1180 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1181}
1182
a2ac29d2
VD		 1183static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1184{
c3a7d4ad
VD		 1185 int err;
1186
daefc943
VD		 1187 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1188 if (err)
1189 return err;
1190
c3a7d4ad
VD		 1191 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1192 if (err)
1193 return err;
1194
a2ac29d2
VD		 1195 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1196}
1197
749efcb8
VD		 1198static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1199{
1200 struct mv88e6xxx_chip *chip = ds->priv;
1201 int err;
1202
1203 mutex_lock(&chip->reg_lock);
e606ca36 1204 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1205 mutex_unlock(&chip->reg_lock);
1206
1207 if (err)
1208 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1209}
1210
fad09c73 1211static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1212{
a935c052 1213 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1214}
1215
fad09c73 1216static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1217{
a935c052 1218 int err;
6b17e864 1219
a935c052
VD		 1220 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1221 if (err)
1222 return err;
6b17e864 1223
fad09c73 1224 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1225}
1226
fad09c73 1227static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1228{
1229 int ret;
1230
fad09c73 1231 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1232 if (ret < 0)
1233 return ret;
1234
fad09c73 1235 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1236}
1237
fad09c73 1238static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1239 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1240 unsigned int nibble_offset)
1241{
b8fee957 1242 u16 regs[3];
a935c052 1243 int i, err;
b8fee957
VD		 1244
1245 for (i = 0; i < 3; ++i) {
a935c052 1246 u16 *reg = &regs[i];
b8fee957 1247
a935c052
VD		 1248 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1249 if (err)
1250 return err;
b8fee957
VD		 1251 }
1252
370b4ffb 1253 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1254 unsigned int shift = (i % 4) * 4 + nibble_offset;
1255 u16 reg = regs[i / 4];
1256
1257 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1258 }
1259
1260 return 0;
1261}
1262
fad09c73 1263static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1264 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1265{
fad09c73 1266 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1267}
1268
fad09c73 1269static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1270 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1271{
fad09c73 1272 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1273}
1274
fad09c73 1275static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1276 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1277 unsigned int nibble_offset)
1278{
7dad08d7 1279 u16 regs[3] = { 0 };
a935c052 1280 int i, err;
7dad08d7 1281
370b4ffb 1282 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1283 unsigned int shift = (i % 4) * 4 + nibble_offset;
1284 u8 data = entry->data[i];
1285
1286 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1287 }
1288
1289 for (i = 0; i < 3; ++i) {
a935c052
VD		 1290 u16 reg = regs[i];
1291
1292 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1293 if (err)
1294 return err;
7dad08d7
VD		 1295 }
1296
1297 return 0;
1298}
1299
fad09c73 1300static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1301 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1302{
fad09c73 1303 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1304}
1305
fad09c73 1306static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1307 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1308{
fad09c73 1309 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1310}
1311
fad09c73 1312static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1313{
a935c052
VD		 1314 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1315 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1316}
1317
fad09c73 1318static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1319 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1320{
b4e47c0f 1321 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1322 u16 val;
1323 int err;
b8fee957 1324
a935c052
VD		 1325 err = _mv88e6xxx_vtu_wait(chip);
1326 if (err)
1327 return err;
b8fee957 1328
a935c052
VD		 1329 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1330 if (err)
1331 return err;
b8fee957 1332
a935c052
VD		 1333 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1334 if (err)
1335 return err;
b8fee957 1336
a935c052
VD		 1337 next.vid = val & GLOBAL_VTU_VID_MASK;
1338 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1339
1340 if (next.valid) {
a935c052
VD		 1341 err = mv88e6xxx_vtu_data_read(chip, &next);
1342 if (err)
1343 return err;
b8fee957 1344
6dc10bbc 1345 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1346 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1347 if (err)
1348 return err;
b8fee957 1349
a935c052 1350 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1351 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1352 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1353 * VTU DBNum[3:0] are located in VTU Operation 3:0
1354 */
a935c052
VD		 1355 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1356 if (err)
1357 return err;
11ea809f 1358
a935c052
VD		 1359 next.fid = (val & 0xf00) >> 4;
1360 next.fid |= val & 0xf;
2e7bd5ef 1361 }
b8fee957 1362
fad09c73 1363 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1364 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1365 if (err)
1366 return err;
b8fee957 1367
a935c052 1368 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1369 }
1370 }
1371
1372 *entry = next;
1373 return 0;
1374}
1375
f81ec90f
VD		 1376static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1377 struct switchdev_obj_port_vlan *vlan,
1378 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1379{
04bed143 1380 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1381 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1382 u16 pvid;
1383 int err;
1384
fad09c73 1385 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1386 return -EOPNOTSUPP;
1387
fad09c73 1388 mutex_lock(&chip->reg_lock);
ceff5eff 1389
77064f37 1390 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1391 if (err)
1392 goto unlock;
1393
fad09c73 1394 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1395 if (err)
1396 goto unlock;
1397
1398 do {
fad09c73 1399 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1400 if (err)
1401 break;
1402
1403 if (!next.valid)
1404 break;
1405
1406 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1407 continue;
1408
1409 /* reinit and dump this VLAN obj */
57d32310
VD		 1410 vlan->vid_begin = next.vid;
1411 vlan->vid_end = next.vid;
ceff5eff
VD		 1412 vlan->flags = 0;
1413
1414 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1415 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1416
1417 if (next.vid == pvid)
1418 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1419
1420 err = cb(&vlan->obj);
1421 if (err)
1422 break;
1423 } while (next.vid < GLOBAL_VTU_VID_MASK);
1424
1425unlock:
fad09c73 1426 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1427
1428 return err;
1429}
1430
fad09c73 1431static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1432 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1433{
11ea809f 1434 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1435 u16 reg = 0;
a935c052 1436 int err;
7dad08d7 1437
a935c052
VD		 1438 err = _mv88e6xxx_vtu_wait(chip);
1439 if (err)
1440 return err;
7dad08d7
VD		 1441
1442 if (!entry->valid)
1443 goto loadpurge;
1444
1445 /* Write port member tags */
a935c052
VD		 1446 err = mv88e6xxx_vtu_data_write(chip, entry);
1447 if (err)
1448 return err;
7dad08d7 1449
fad09c73 1450 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1451 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1452 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1453 if (err)
1454 return err;
b426e5f7 1455 }
7dad08d7 1456
6dc10bbc 1457 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1458 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1459 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1460 if (err)
1461 return err;
fad09c73 1462 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1463 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1464 * VTU DBNum[3:0] are located in VTU Operation 3:0
1465 */
1466 op |= (entry->fid & 0xf0) << 8;
1467 op |= entry->fid & 0xf;
7dad08d7
VD		 1468 }
1469
1470 reg = GLOBAL_VTU_VID_VALID;
1471loadpurge:
1472 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1473 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1474 if (err)
1475 return err;
7dad08d7 1476
fad09c73 1477 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1478}
1479
fad09c73 1480static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1481 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1482{
b4e47c0f 1483 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1484 u16 val;
1485 int err;
0d3b33e6 1486
a935c052
VD		 1487 err = _mv88e6xxx_vtu_wait(chip);
1488 if (err)
1489 return err;
0d3b33e6 1490
a935c052
VD		 1491 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1492 sid & GLOBAL_VTU_SID_MASK);
1493 if (err)
1494 return err;
0d3b33e6 1495
a935c052
VD		 1496 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1497 if (err)
1498 return err;
0d3b33e6 1499
a935c052
VD		 1500 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1501 if (err)
1502 return err;
0d3b33e6 1503
a935c052 1504 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1505
a935c052
VD		 1506 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1507 if (err)
1508 return err;
0d3b33e6 1509
a935c052 1510 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1511
1512 if (next.valid) {
a935c052
VD		 1513 err = mv88e6xxx_stu_data_read(chip, &next);
1514 if (err)
1515 return err;
0d3b33e6
VD		 1516 }
1517
1518 *entry = next;
1519 return 0;
1520}
1521
fad09c73 1522static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1523 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1524{
1525 u16 reg = 0;
a935c052 1526 int err;
0d3b33e6 1527
a935c052
VD		 1528 err = _mv88e6xxx_vtu_wait(chip);
1529 if (err)
1530 return err;
0d3b33e6
VD		 1531
1532 if (!entry->valid)
1533 goto loadpurge;
1534
1535 /* Write port states */
a935c052
VD		 1536 err = mv88e6xxx_stu_data_write(chip, entry);
1537 if (err)
1538 return err;
0d3b33e6
VD		 1539
1540 reg = GLOBAL_VTU_VID_VALID;
1541loadpurge:
a935c052
VD		 1542 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1543 if (err)
1544 return err;
0d3b33e6
VD		 1545
1546 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1547 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1548 if (err)
1549 return err;
0d3b33e6 1550
fad09c73 1551 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1552}
1553
d7f435f9 1554static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1555{
1556 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1557 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1558 int i, err;
3285f9e8
VD		 1559
1560 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1561
2db9ce1f 1562 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1563 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1564 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1565 if (err)
1566 return err;
1567
1568 set_bit(*fid, fid_bitmap);
1569 }
1570
3285f9e8 1571 /* Set every FID bit used by the VLAN entries */
fad09c73 1572 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1573 if (err)
1574 return err;
1575
1576 do {
fad09c73 1577 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1578 if (err)
1579 return err;
1580
1581 if (!vlan.valid)
1582 break;
1583
1584 set_bit(vlan.fid, fid_bitmap);
1585 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1586
1587 /* The reset value 0x000 is used to indicate that multiple address
1588 * databases are not needed. Return the next positive available.
1589 */
1590 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1591 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1592 return -ENOSPC;
1593
1594 /* Clear the database */
daefc943 1595 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1596}
1597
fad09c73 1598static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1599 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1600{
fad09c73 1601 struct dsa_switch *ds = chip->ds;
b4e47c0f 1602 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1603 .valid = true,
1604 .vid = vid,
1605 };
3285f9e8
VD		 1606 int i, err;
1607
d7f435f9 1608 err = mv88e6xxx_atu_new(chip, &vlan.fid);
3285f9e8
VD		 1609 if (err)
1610 return err;
0d3b33e6 1611
3d131f07 1612 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1613 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1614 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1615 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1616 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1617
fad09c73 1618 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
a75961d0
GC		 1619 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1620 mv88e6xxx_6341_family(chip)) {
b4e47c0f 1621 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1622
1623 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1624 * implemented, only one STU entry is needed to cover all VTU
1625 * entries. Thus, validate the SID 0.
1626 */
1627 vlan.sid = 0;
fad09c73 1628 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1629 if (err)
1630 return err;
1631
1632 if (vstp.sid != vlan.sid || !vstp.valid) {
1633 memset(&vstp, 0, sizeof(vstp));
1634 vstp.valid = true;
1635 vstp.sid = vlan.sid;
1636
fad09c73 1637 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1638 if (err)
1639 return err;
1640 }
0d3b33e6
VD		 1641 }
1642
1643 *entry = vlan;
1644 return 0;
1645}
1646
fad09c73 1647static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1648 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1649{
1650 int err;
1651
1652 if (!vid)
1653 return -EINVAL;
1654
fad09c73 1655 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1656 if (err)
1657 return err;
1658
fad09c73 1659 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1660 if (err)
1661 return err;
1662
1663 if (entry->vid != vid || !entry->valid) {
1664 if (!creat)
1665 return -EOPNOTSUPP;
1666 /* -ENOENT would've been more appropriate, but switchdev expects
1667 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1668 */
1669
fad09c73 1670 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1671 }
1672
1673 return err;
1674}
1675
da9c359e
VD		 1676static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1677 u16 vid_begin, u16 vid_end)
1678{
04bed143 1679 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1680 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1681 int i, err;
1682
1683 if (!vid_begin)
1684 return -EOPNOTSUPP;
1685
fad09c73 1686 mutex_lock(&chip->reg_lock);
da9c359e 1687
fad09c73 1688 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1689 if (err)
1690 goto unlock;
1691
1692 do {
fad09c73 1693 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1694 if (err)
1695 goto unlock;
1696
1697 if (!vlan.valid)
1698 break;
1699
1700 if (vlan.vid > vid_end)
1701 break;
1702
370b4ffb 1703 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1704 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1705 continue;
1706
66e2809d
AL		 1707 if (!ds->ports[port].netdev)
1708 continue;
1709
da9c359e
VD		 1710 if (vlan.data[i] ==
1711 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1712 continue;
1713
fae8a25e
VD		 1714 if (ds->ports[i].bridge_dev ==
1715 ds->ports[port].bridge_dev)
da9c359e
VD		 1716 break; /* same bridge, check next VLAN */
1717
fae8a25e 1718 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1719 continue;
1720
c8b09808 1721 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1722 "hardware VLAN %d already used by %s\n",
1723 vlan.vid,
fae8a25e 1724 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1725 err = -EOPNOTSUPP;
1726 goto unlock;
1727 }
1728 } while (vlan.vid < vid_end);
1729
1730unlock:
fad09c73 1731 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1732
1733 return err;
1734}
1735
f81ec90f
VD		 1736static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1737 bool vlan_filtering)
214cdb99 1738{
04bed143 1739 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1740 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1741 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1742 int err;
214cdb99 1743
fad09c73 1744 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1745 return -EOPNOTSUPP;
1746
fad09c73 1747 mutex_lock(&chip->reg_lock);
385a0995 1748 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1749 mutex_unlock(&chip->reg_lock);
214cdb99 1750
0e7b9925 1751 return err;
214cdb99
VD		 1752}
1753
57d32310
VD		 1754static int
1755mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1756 const struct switchdev_obj_port_vlan *vlan,
1757 struct switchdev_trans *trans)
76e398a6 1758{
04bed143 1759 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1760 int err;
1761
fad09c73 1762 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1763 return -EOPNOTSUPP;
1764
da9c359e
VD		 1765 /* If the requested port doesn't belong to the same bridge as the VLAN
1766 * members, do not support it (yet) and fallback to software VLAN.
1767 */
1768 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1769 vlan->vid_end);
1770 if (err)
1771 return err;
1772
76e398a6
VD		 1773 /* We don't need any dynamic resource from the kernel (yet),
1774 * so skip the prepare phase.
1775 */
1776 return 0;
1777}
1778
fad09c73 1779static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1780 u16 vid, bool untagged)
0d3b33e6 1781{
b4e47c0f 1782 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1783 int err;
1784
fad09c73 1785 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1786 if (err)
76e398a6 1787 return err;
0d3b33e6 1788
0d3b33e6
VD		 1789 vlan.data[port] = untagged ?
1790 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1791 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1792
fad09c73 1793 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1794}
1795
f81ec90f
VD		 1796static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1797 const struct switchdev_obj_port_vlan *vlan,
1798 struct switchdev_trans *trans)
76e398a6 1799{
04bed143 1800 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1801 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1802 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1803 u16 vid;
76e398a6 1804
fad09c73 1805 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1806 return;
1807
fad09c73 1808 mutex_lock(&chip->reg_lock);
76e398a6 1809
4d5770b3 1810 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1811 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1812 netdev_err(ds->ports[port].netdev,
1813 "failed to add VLAN %d%c\n",
4d5770b3 1814 vid, untagged ? 'u' : 't');
76e398a6 1815
77064f37 1816 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1817 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1818 vlan->vid_end);
0d3b33e6 1819
fad09c73 1820 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1821}
1822
fad09c73 1823static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1824 int port, u16 vid)
7dad08d7 1825{
fad09c73 1826 struct dsa_switch *ds = chip->ds;
b4e47c0f 1827 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1828 int i, err;
1829
fad09c73 1830 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1831 if (err)
76e398a6 1832 return err;
7dad08d7 1833
2fb5ef09
VD		 1834 /* Tell switchdev if this VLAN is handled in software */
1835 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1836 return -EOPNOTSUPP;
7dad08d7
VD		 1837
1838 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1839
1840 /* keep the VLAN unless all ports are excluded */
f02bdffc 1841 vlan.valid = false;
370b4ffb 1842 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1843 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1844 continue;
1845
1846 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1847 vlan.valid = true;
7dad08d7
VD		 1848 break;
1849 }
1850 }
1851
fad09c73 1852 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1853 if (err)
1854 return err;
1855
e606ca36 1856 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1857}
1858
f81ec90f
VD		 1859static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1860 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1861{
04bed143 1862 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1863 u16 pvid, vid;
1864 int err = 0;
1865
fad09c73 1866 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1867 return -EOPNOTSUPP;
1868
fad09c73 1869 mutex_lock(&chip->reg_lock);
76e398a6 1870
77064f37 1871 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1872 if (err)
1873 goto unlock;
1874
76e398a6 1875 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1876 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1877 if (err)
1878 goto unlock;
1879
1880 if (vid == pvid) {
77064f37 1881 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1882 if (err)
1883 goto unlock;
1884 }
1885 }
1886
7dad08d7 1887unlock:
fad09c73 1888 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1889
1890 return err;
1891}
1892
83dabd1f
VD		 1893static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1894 const unsigned char *addr, u16 vid,
1895 u8 state)
fd231c82 1896{
b4e47c0f 1897 struct mv88e6xxx_vtu_entry vlan;
88472939 1898 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1899 int err;
1900
2db9ce1f
VD		 1901 /* Null VLAN ID corresponds to the port private database */
1902 if (vid == 0)
b4e48c50 1903 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1904 else
fad09c73 1905 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1906 if (err)
1907 return err;
fd231c82 1908
dabc1a96
VD		 1909 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1910 ether_addr_copy(entry.mac, addr);
1911 eth_addr_dec(entry.mac);
1912
1913 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1914 if (err)
1915 return err;
1916
dabc1a96
VD		 1917 /* Initialize a fresh ATU entry if it isn't found */
1918 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1919 !ether_addr_equal(entry.mac, addr)) {
1920 memset(&entry, 0, sizeof(entry));
1921 ether_addr_copy(entry.mac, addr);
1922 }
1923
88472939
VD		 1924 /* Purge the ATU entry only if no port is using it anymore */
1925 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1926 entry.portvec &= ~BIT(port);
1927 if (!entry.portvec)
88472939
VD		 1928 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1929 } else {
01bd96c8 1930 entry.portvec |= BIT(port);
88472939 1931 entry.state = state;
fd231c82
VD		 1932 }
1933
9c13c026 1934 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1935}
1936
f81ec90f
VD		 1937static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1938 const struct switchdev_obj_port_fdb *fdb,
1939 struct switchdev_trans *trans)
146a3206
VD		 1940{
1941 /* We don't need any dynamic resource from the kernel (yet),
1942 * so skip the prepare phase.
1943 */
1944 return 0;
1945}
1946
f81ec90f
VD		 1947static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1948 const struct switchdev_obj_port_fdb *fdb,
1949 struct switchdev_trans *trans)
87820510 1950{
04bed143 1951 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1952
fad09c73 1953 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1954 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1955 GLOBAL_ATU_DATA_STATE_UC_STATIC))
1956 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 1957 mutex_unlock(&chip->reg_lock);
87820510
VD		 1958}
1959
f81ec90f
VD		 1960static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1961 const struct switchdev_obj_port_fdb *fdb)
87820510 1962{
04bed143 1963 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1964 int err;
87820510 1965
fad09c73 1966 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1967 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1968 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 1969 mutex_unlock(&chip->reg_lock);
87820510 1970
83dabd1f 1971 return err;
87820510
VD		 1972}
1973
83dabd1f
VD		 1974static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1975 u16 fid, u16 vid, int port,
1976 struct switchdev_obj *obj,
1977 int (*cb)(struct switchdev_obj *obj))
74b6ba0d 1978{
dabc1a96 1979 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 1980 int err;
1981
dabc1a96
VD		 1982 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1983 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1984
1985 do {
dabc1a96 1986 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1987 if (err)
83dabd1f 1988 return err;
74b6ba0d
VD		 1989
1990 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1991 break;
1992
01bd96c8 1993 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1994 continue;
1995
1996 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1997 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 1998
83dabd1f
VD		 1999 if (!is_unicast_ether_addr(addr.mac))
2000 continue;
2001
2002 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2003 fdb->vid = vid;
2004 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2005 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2006 fdb->ndm_state = NUD_NOARP;
2007 else
2008 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2009 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2010 struct switchdev_obj_port_mdb *mdb;
2011
2012 if (!is_multicast_ether_addr(addr.mac))
2013 continue;
2014
2015 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2016 mdb->vid = vid;
2017 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2018 } else {
2019 return -EOPNOTSUPP;
74b6ba0d 2020 }
83dabd1f
VD		 2021
2022 err = cb(obj);
2023 if (err)
2024 return err;
74b6ba0d
VD		 2025 } while (!is_broadcast_ether_addr(addr.mac));
2026
2027 return err;
2028}
2029
83dabd1f
VD		 2030static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2031 struct switchdev_obj *obj,
2032 int (*cb)(struct switchdev_obj *obj))
f33475bd 2033{
b4e47c0f 2034 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2035 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2036 };
2db9ce1f 2037 u16 fid;
f33475bd
VD		 2038 int err;
2039
2db9ce1f 2040 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2041 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2042 if (err)
83dabd1f 2043 return err;
2db9ce1f 2044
83dabd1f 2045 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2046 if (err)
83dabd1f 2047 return err;
2db9ce1f 2048
74b6ba0d 2049 /* Dump VLANs' Filtering Information Databases */
fad09c73 2050 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2051 if (err)
83dabd1f 2052 return err;
f33475bd
VD		 2053
2054 do {
fad09c73 2055 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2056 if (err)
83dabd1f 2057 return err;
f33475bd
VD		 2058
2059 if (!vlan.valid)
2060 break;
2061
83dabd1f
VD		 2062 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2063 obj, cb);
f33475bd 2064 if (err)
83dabd1f 2065 return err;
f33475bd
VD		 2066 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2067
83dabd1f
VD		 2068 return err;
2069}
2070
2071static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2072 struct switchdev_obj_port_fdb *fdb,
2073 int (*cb)(struct switchdev_obj *obj))
2074{
04bed143 2075 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2076 int err;
2077
2078 mutex_lock(&chip->reg_lock);
2079 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2080 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2081
2082 return err;
2083}
2084
f81ec90f 2085static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
fae8a25e 2086 struct net_device *br)
e79a8bcb 2087{
04bed143 2088 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2089 int i, err = 0;
466dfa07 2090
fad09c73 2091 mutex_lock(&chip->reg_lock);
466dfa07 2092
fae8a25e 2093 /* Remap each port's VLANTable */
370b4ffb 2094 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fae8a25e 2095 if (ds->ports[i].bridge_dev == br) {
fad09c73 2096 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2097 if (err)
2098 break;
2099 }
2100 }
2101
fad09c73 2102 mutex_unlock(&chip->reg_lock);
a6692754 2103
466dfa07 2104 return err;
e79a8bcb
VD		 2105}
2106
f123f2fb
VD		 2107static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2108 struct net_device *br)
66d9cd0f 2109{
04bed143 2110 struct mv88e6xxx_chip *chip = ds->priv;
16bfa702 2111 int i;
466dfa07 2112
fad09c73 2113 mutex_lock(&chip->reg_lock);
466dfa07 2114
fae8a25e 2115 /* Remap each port's VLANTable */
370b4ffb 2116 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fae8a25e 2117 if (i == port || ds->ports[i].bridge_dev == br)
fad09c73 2118 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2119 netdev_warn(ds->ports[i].netdev,
2120 "failed to remap\n");
b7666efe 2121
fad09c73 2122 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2123}
2124
17e708ba
VD		 2125static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2126{
2127 if (chip->info->ops->reset)
2128 return chip->info->ops->reset(chip);
2129
2130 return 0;
2131}
2132
309eca6d
VD		 2133static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2134{
2135 struct gpio_desc *gpiod = chip->reset;
2136
2137 /* If there is a GPIO connected to the reset pin, toggle it */
2138 if (gpiod) {
2139 gpiod_set_value_cansleep(gpiod, 1);
2140 usleep_range(10000, 20000);
2141 gpiod_set_value_cansleep(gpiod, 0);
2142 usleep_range(10000, 20000);
2143 }
2144}
2145
4ac4b5a6 2146static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2147{
4ac4b5a6 2148 int i, err;
552238b5 2149
4ac4b5a6 2150 /* Set all ports to the Disabled state */
370b4ffb 2151 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2152 err = mv88e6xxx_port_set_state(chip, i,
2153 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2154 if (err)
2155 return err;
552238b5
VD		 2156 }
2157
4ac4b5a6
VD		 2158 /* Wait for transmit queues to drain,
2159 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2160 */
552238b5
VD		 2161 usleep_range(2000, 4000);
2162
4ac4b5a6
VD		 2163 return 0;
2164}
2165
2166static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2167{
4ac4b5a6
VD		 2168 int err;
2169
2170 err = mv88e6xxx_disable_ports(chip);
2171 if (err)
2172 return err;
2173
309eca6d 2174 mv88e6xxx_hardware_reset(chip);
552238b5 2175
17e708ba 2176 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2177}
2178
09cb7dfd 2179static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2180{
09cb7dfd
VD		 2181 u16 val;
2182 int err;
13a7ebb3 2183
09cb7dfd
VD		 2184 /* Clear Power Down bit */
2185 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2186 if (err)
2187 return err;
13a7ebb3 2188
09cb7dfd
VD		 2189 if (val & BMCR_PDOWN) {
2190 val &= ~BMCR_PDOWN;
2191 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2192 }
2193
09cb7dfd 2194 return err;
13a7ebb3
PU		 2195}
2196
4314557c
VD		 2197static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2198 enum mv88e6xxx_frame_mode frame, u16 egress,
2199 u16 etype)
56995cbc
AL		 2200{
2201 int err;
2202
4314557c
VD		 2203 if (!chip->info->ops->port_set_frame_mode)
2204 return -EOPNOTSUPP;
2205
2206 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 2207 if (err)
2208 return err;
2209
4314557c
VD		 2210 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2211 if (err)
2212 return err;
2213
2214 if (chip->info->ops->port_set_ether_type)
2215 return chip->info->ops->port_set_ether_type(chip, port, etype);
2216
2217 return 0;
56995cbc
AL		 2218}
2219
4314557c 2220static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 2221{
4314557c
VD		 2222 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2223 PORT_CONTROL_EGRESS_UNMODIFIED,
2224 PORT_ETH_TYPE_DEFAULT);
2225}
56995cbc 2226
4314557c
VD		 2227static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2228{
2229 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2230 PORT_CONTROL_EGRESS_UNMODIFIED,
2231 PORT_ETH_TYPE_DEFAULT);
2232}
56995cbc 2233
4314557c
VD		 2234static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2235{
2236 return mv88e6xxx_set_port_mode(chip, port,
2237 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2238 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2239}
56995cbc 2240
4314557c
VD		 2241static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2242{
2243 if (dsa_is_dsa_port(chip->ds, port))
2244 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2245
4314557c
VD		 2246 if (dsa_is_normal_port(chip->ds, port))
2247 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 2248
4314557c
VD		 2249 /* Setup CPU port mode depending on its supported tag format */
2250 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2251 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2252
4314557c
VD		 2253 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2254 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 2255
4314557c 2256 return -EINVAL;
56995cbc
AL		 2257}
2258
601aeed3 2259static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 2260{
601aeed3 2261 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 2262
601aeed3 2263 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 2264}
56995cbc 2265
601aeed3 2266static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 2267{
601aeed3 2268 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 2269
601aeed3
VD		 2270 /* Upstream ports flood frames with unknown unicast or multicast DA */
2271 if (chip->info->ops->port_set_egress_floods)
2272 return chip->info->ops->port_set_egress_floods(chip, port,
2273 flood, flood);
ea698f4f 2274
601aeed3 2275 return 0;
ea698f4f
VD		 2276}
2277
fad09c73 2278static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2279{
fad09c73 2280 struct dsa_switch *ds = chip->ds;
0e7b9925 2281 int err;
54d792f2 2282 u16 reg;
d827e88a 2283
d78343d2
VD		 2284 /* MAC Forcing register: don't force link, speed, duplex or flow control
2285 * state to any particular values on physical ports, but force the CPU
2286 * port and all DSA ports to their maximum bandwidth and full duplex.
2287 */
2288 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2289 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2290 SPEED_MAX, DUPLEX_FULL,
2291 PHY_INTERFACE_MODE_NA);
2292 else
2293 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2294 SPEED_UNFORCED, DUPLEX_UNFORCED,
2295 PHY_INTERFACE_MODE_NA);
2296 if (err)
2297 return err;
54d792f2
AL		 2298
2299 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2300 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2301 * tunneling, determine priority by looking at 802.1p and IP
2302 * priority fields (IP prio has precedence), and set STP state
2303 * to Forwarding.
2304 *
2305 * If this is the CPU link, use DSA or EDSA tagging depending
2306 * on which tagging mode was configured.
2307 *
2308 * If this is a link to another switch, use DSA tagging mode.
2309 *
2310 * If this is the upstream port for this switch, enable
2311 * forwarding of unknown unicasts and multicasts.
2312 */
56995cbc 2313 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2314 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2315 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2316 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2317 if (err)
2318 return err;
6083ce71 2319
601aeed3 2320 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 2321 if (err)
2322 return err;
54d792f2 2323
601aeed3 2324 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 2325 if (err)
2326 return err;
2327
13a7ebb3
PU		 2328 /* If this port is connected to a SerDes, make sure the SerDes is not
2329 * powered down.
2330 */
09cb7dfd 2331 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2332 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2333 if (err)
2334 return err;
2335 reg &= PORT_STATUS_CMODE_MASK;
2336 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2337 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2338 (reg == PORT_STATUS_CMODE_SGMII)) {
2339 err = mv88e6xxx_serdes_power_on(chip);
2340 if (err < 0)
2341 return err;
13a7ebb3
PU		 2342 }
2343 }
2344
8efdda4a 2345 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2346 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2347 * untagged frames on this port, do a destination address lookup on all
2348 * received packets as usual, disable ARP mirroring and don't send a
2349 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2350 */
a23b2961
AL		 2351 err = mv88e6xxx_port_set_map_da(chip, port);
2352 if (err)
2353 return err;
8efdda4a 2354
a23b2961
AL		 2355 reg = 0;
2356 if (chip->info->ops->port_set_upstream_port) {
2357 err = chip->info->ops->port_set_upstream_port(
2358 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 2359 if (err)
2360 return err;
54d792f2
AL		 2361 }
2362
a23b2961
AL		 2363 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2364 PORT_CONTROL_2_8021Q_DISABLED);
2365 if (err)
2366 return err;
2367
5f436666
AL		 2368 if (chip->info->ops->port_jumbo_config) {
2369 err = chip->info->ops->port_jumbo_config(chip, port);
2370 if (err)
2371 return err;
2372 }
2373
54d792f2
AL		 2374 /* Port Association Vector: when learning source addresses
2375 * of packets, add the address to the address database using
2376 * a port bitmap that has only the bit for this port set and
2377 * the other bits clear.
2378 */
4c7ea3c0 2379 reg = 1 << port;
996ecb82
VD		 2380 /* Disable learning for CPU port */
2381 if (dsa_is_cpu_port(ds, port))
65fa4027 2382 reg = 0;
4c7ea3c0 2383
0e7b9925
AL		 2384 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2385 if (err)
2386 return err;
54d792f2
AL		 2387
2388 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2389 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2390 if (err)
2391 return err;
54d792f2 2392
b35d322a
AL		 2393 if (chip->info->ops->port_pause_config) {
2394 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2395 if (err)
2396 return err;
b35d322a 2397 }
54d792f2 2398
c8c94891
VD		 2399 if (chip->info->ops->port_disable_learn_limit) {
2400 err = chip->info->ops->port_disable_learn_limit(chip, port);
2401 if (err)
2402 return err;
2403 }
2404
9dbfb4e1
VD		 2405 if (chip->info->ops->port_disable_pri_override) {
2406 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 2407 if (err)
2408 return err;
ef0a7318 2409 }
2bbb33be 2410
ef0a7318
AL		 2411 if (chip->info->ops->port_tag_remap) {
2412 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2413 if (err)
2414 return err;
54d792f2
AL		 2415 }
2416
ef70b111
AL		 2417 if (chip->info->ops->port_egress_rate_limiting) {
2418 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2419 if (err)
2420 return err;
54d792f2
AL		 2421 }
2422
ea698f4f 2423 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 2424 if (err)
2425 return err;
d827e88a 2426
207afda1 2427 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2428 * database, and allow bidirectional communication between the
2429 * CPU and DSA port(s), and the other ports.
d827e88a 2430 */
b4e48c50 2431 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2432 if (err)
2433 return err;
2db9ce1f 2434
0e7b9925
AL		 2435 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2436 if (err)
2437 return err;
d827e88a
GR		 2438
2439 /* Default VLAN ID and priority: don't set a default VLAN
2440 * ID, and set the default packet priority to zero.
2441 */
0e7b9925 2442 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2443}
2444
aa0938c6 2445static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2446{
2447 int err;
2448
a935c052 2449 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2450 if (err)
2451 return err;
2452
a935c052 2453 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2454 if (err)
2455 return err;
2456
a935c052
VD		 2457 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2458 if (err)
2459 return err;
2460
2461 return 0;
3b4caa1b
VD		 2462}
2463
2cfcd964
VD		 2464static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2465 unsigned int ageing_time)
2466{
04bed143 2467 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2468 int err;
2469
2470 mutex_lock(&chip->reg_lock);
720c6343 2471 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2472 mutex_unlock(&chip->reg_lock);
2473
2474 return err;
2475}
2476
9729934c 2477static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2478{
fad09c73 2479 struct dsa_switch *ds = chip->ds;
b0745e87 2480 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2481 int err;
54d792f2 2482
119477bd
VD		 2483 /* Enable the PHY Polling Unit if present, don't discard any packets,
2484 * and mask all interrupt sources.
2485 */
a199d8b6 2486 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2487 if (err)
2488 return err;
2489
33641994
AL		 2490 if (chip->info->ops->g1_set_cpu_port) {
2491 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2492 if (err)
2493 return err;
2494 }
2495
2496 if (chip->info->ops->g1_set_egress_port) {
2497 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2498 if (err)
2499 return err;
2500 }
b0745e87 2501
50484ff4 2502 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2503 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2504 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2505 (ds->index & 0x1f));
50484ff4
VD		 2506 if (err)
2507 return err;
2508
acddbd21
VD		 2509 /* Clear all the VTU and STU entries */
2510 err = _mv88e6xxx_vtu_stu_flush(chip);
2511 if (err < 0)
2512 return err;
2513
54d792f2 2514 /* Configure the IP ToS mapping registers. */
a935c052 2515 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2516 if (err)
08a01261 2517 return err;
a935c052 2518 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2519 if (err)
08a01261 2520 return err;
a935c052 2521 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2522 if (err)
08a01261 2523 return err;
a935c052 2524 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2525 if (err)
08a01261 2526 return err;
a935c052 2527 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2528 if (err)
08a01261 2529 return err;
a935c052 2530 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2531 if (err)
08a01261 2532 return err;
a935c052 2533 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2534 if (err)
08a01261 2535 return err;
a935c052 2536 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2537 if (err)
08a01261 2538 return err;
54d792f2
AL		 2539
2540 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2541 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2542 if (err)
08a01261 2543 return err;
54d792f2 2544
de227387
AL		 2545 /* Initialize the statistics unit */
2546 err = mv88e6xxx_stats_set_histogram(chip);
2547 if (err)
2548 return err;
2549
9729934c 2550 /* Clear the statistics counters for all ports */
a935c052
VD		 2551 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2552 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2553 if (err)
2554 return err;
2555
2556 /* Wait for the flush to complete. */
7f9ef3af 2557 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2558 if (err)
2559 return err;
2560
2561 return 0;
2562}
2563
f81ec90f 2564static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2565{
04bed143 2566 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2567 int err;
a1a6a4d1
VD		 2568 int i;
2569
fad09c73 2570 chip->ds = ds;
a3c53be5 2571 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2572
fad09c73 2573 mutex_lock(&chip->reg_lock);
08a01261 2574
9729934c 2575 /* Setup Switch Port Registers */
370b4ffb 2576 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2577 err = mv88e6xxx_setup_port(chip, i);
2578 if (err)
2579 goto unlock;
2580 }
2581
2582 /* Setup Switch Global 1 Registers */
2583 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2584 if (err)
2585 goto unlock;
2586
9729934c
VD		 2587 /* Setup Switch Global 2 Registers */
2588 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2589 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2590 if (err)
2591 goto unlock;
2592 }
08a01261 2593
a2ac29d2
VD		 2594 err = mv88e6xxx_atu_setup(chip);
2595 if (err)
2596 goto unlock;
2597
6e55f698
AL		 2598 /* Some generations have the configuration of sending reserved
2599 * management frames to the CPU in global2, others in
2600 * global1. Hence it does not fit the two setup functions
2601 * above.
2602 */
2603 if (chip->info->ops->mgmt_rsvd2cpu) {
2604 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2605 if (err)
2606 goto unlock;
2607 }
2608
6b17e864 2609unlock:
fad09c73 2610 mutex_unlock(&chip->reg_lock);
db687a56 2611
48ace4ef 2612 return err;
54d792f2
AL		 2613}
2614
3b4caa1b
VD		 2615static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2616{
04bed143 2617 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2618 int err;
2619
b073d4e2
VD		 2620 if (!chip->info->ops->set_switch_mac)
2621 return -EOPNOTSUPP;
3b4caa1b 2622
b073d4e2
VD		 2623 mutex_lock(&chip->reg_lock);
2624 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2625 mutex_unlock(&chip->reg_lock);
2626
2627 return err;
2628}
2629
e57e5e77 2630static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2631{
0dd12d54
AL		 2632 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2633 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2634 u16 val;
2635 int err;
fd3a0ee4 2636
ee26a228
AL		 2637 if (!chip->info->ops->phy_read)
2638 return -EOPNOTSUPP;
2639
fad09c73 2640 mutex_lock(&chip->reg_lock);
ee26a228 2641 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2642 mutex_unlock(&chip->reg_lock);
e57e5e77 2643
da9f3301
AL		 2644 if (reg == MII_PHYSID2) {
2645 /* Some internal PHYS don't have a model number. Use
2646 * the mv88e6390 family model number instead.
2647 */
2648 if (!(val & 0x3f0))
2649 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2650 }
2651
e57e5e77 2652 return err ? err : val;
fd3a0ee4
AL		 2653}
2654
e57e5e77 2655static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2656{
0dd12d54
AL		 2657 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2658 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2659 int err;
fd3a0ee4 2660
ee26a228
AL		 2661 if (!chip->info->ops->phy_write)
2662 return -EOPNOTSUPP;
2663
fad09c73 2664 mutex_lock(&chip->reg_lock);
ee26a228 2665 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2666 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2667
2668 return err;
fd3a0ee4
AL		 2669}
2670
fad09c73 2671static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2672 struct device_node *np,
2673 bool external)
b516d453
AL		 2674{
2675 static int index;
0dd12d54 2676 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2677 struct mii_bus *bus;
2678 int err;
2679
0dd12d54 2680 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2681 if (!bus)
2682 return -ENOMEM;
2683
0dd12d54 2684 mdio_bus = bus->priv;
a3c53be5 2685 mdio_bus->bus = bus;
0dd12d54 2686 mdio_bus->chip = chip;
a3c53be5
AL		 2687 INIT_LIST_HEAD(&mdio_bus->list);
2688 mdio_bus->external = external;
0dd12d54 2689
b516d453
AL		 2690 if (np) {
2691 bus->name = np->full_name;
2692 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2693 } else {
2694 bus->name = "mv88e6xxx SMI";
2695 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2696 }
2697
2698 bus->read = mv88e6xxx_mdio_read;
2699 bus->write = mv88e6xxx_mdio_write;
fad09c73 2700 bus->parent = chip->dev;
b516d453 2701
a3c53be5
AL		 2702 if (np)
2703 err = of_mdiobus_register(bus, np);
b516d453
AL		 2704 else
2705 err = mdiobus_register(bus);
2706 if (err) {
fad09c73 2707 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2708 return err;
b516d453 2709 }
a3c53be5
AL		 2710
2711 if (external)
2712 list_add_tail(&mdio_bus->list, &chip->mdios);
2713 else
2714 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2715
2716 return 0;
a3c53be5 2717}
b516d453 2718
a3c53be5
AL		 2719static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2720 { .compatible = "marvell,mv88e6xxx-mdio-external",
2721 .data = (void *)true },
2722 { },
2723};
b516d453 2724
a3c53be5
AL		 2725static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2726 struct device_node *np)
2727{
2728 const struct of_device_id *match;
2729 struct device_node *child;
2730 int err;
2731
2732 /* Always register one mdio bus for the internal/default mdio
2733 * bus. This maybe represented in the device tree, but is
2734 * optional.
2735 */
2736 child = of_get_child_by_name(np, "mdio");
2737 err = mv88e6xxx_mdio_register(chip, child, false);
2738 if (err)
2739 return err;
2740
2741 /* Walk the device tree, and see if there are any other nodes
2742 * which say they are compatible with the external mdio
2743 * bus.
2744 */
2745 for_each_available_child_of_node(np, child) {
2746 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2747 if (match) {
2748 err = mv88e6xxx_mdio_register(chip, child, true);
2749 if (err)
2750 return err;
2751 }
2752 }
2753
2754 return 0;
b516d453
AL		 2755}
2756
a3c53be5 2757static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2758
2759{
a3c53be5
AL		 2760 struct mv88e6xxx_mdio_bus *mdio_bus;
2761 struct mii_bus *bus;
b516d453 2762
a3c53be5
AL		 2763 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2764 bus = mdio_bus->bus;
b516d453 2765
a3c53be5
AL		 2766 mdiobus_unregister(bus);
2767 }
b516d453
AL		 2768}
2769
855b1932
VD		 2770static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2771{
04bed143 2772 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2773
2774 return chip->eeprom_len;
2775}
2776
855b1932
VD		 2777static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2778 struct ethtool_eeprom *eeprom, u8 *data)
2779{
04bed143 2780 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2781 int err;
2782
ee4dc2e7
VD		 2783 if (!chip->info->ops->get_eeprom)
2784 return -EOPNOTSUPP;
855b1932 2785
ee4dc2e7
VD		 2786 mutex_lock(&chip->reg_lock);
2787 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2788 mutex_unlock(&chip->reg_lock);
2789
2790 if (err)
2791 return err;
2792
2793 eeprom->magic = 0xc3ec4951;
2794
2795 return 0;
2796}
2797
855b1932
VD		 2798static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2799 struct ethtool_eeprom *eeprom, u8 *data)
2800{
04bed143 2801 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2802 int err;
2803
ee4dc2e7
VD		 2804 if (!chip->info->ops->set_eeprom)
2805 return -EOPNOTSUPP;
2806
855b1932
VD		 2807 if (eeprom->magic != 0xc3ec4951)
2808 return -EINVAL;
2809
2810 mutex_lock(&chip->reg_lock);
ee4dc2e7 2811 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2812 mutex_unlock(&chip->reg_lock);
2813
2814 return err;
2815}
2816
b3469dd8 2817static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2818 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 2819 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2820 .phy_read = mv88e6xxx_phy_ppu_read,
2821 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2822 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2823 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2824 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2825 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2826 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2827 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2828 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2829 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2830 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2831 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2832 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2833 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2834 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2835 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2836 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2837 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2838 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2839 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2840 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2841 .ppu_enable = mv88e6185_g1_ppu_enable,
2842 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2843 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2844};
2845
2846static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2847 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2848 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2849 .phy_read = mv88e6xxx_phy_ppu_read,
2850 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2851 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2852 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2853 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2854 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2855 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2856 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2857 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2858 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2859 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2860 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 2861 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2862 .ppu_enable = mv88e6185_g1_ppu_enable,
2863 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2864 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2865};
2866
7d381a02 2867static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2868 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 2869 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2870 .phy_read = mv88e6xxx_g2_smi_phy_read,
2871 .phy_write = mv88e6xxx_g2_smi_phy_write,
2872 .port_set_link = mv88e6xxx_port_set_link,
2873 .port_set_duplex = mv88e6xxx_port_set_duplex,
2874 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2875 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2876 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2877 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2878 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 2879 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2880 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 2881 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2882 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2883 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2884 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2885 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2886 .stats_get_strings = mv88e6095_stats_get_strings,
2887 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2888 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2889 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2890 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2891 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2892 .reset = mv88e6352_g1_reset,
7d381a02
SE		 2893};
2894
b3469dd8 2895static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2896 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2897 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2898 .phy_read = mv88e6165_phy_read,
2899 .phy_write = mv88e6165_phy_write,
08ef7f10 2900 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2901 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2902 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2903 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2904 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2905 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2906 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2907 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2908 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2909 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2910 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2911 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2912 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2913 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2914 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2915 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 2916};
2917
2918static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2919 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2920 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2921 .phy_read = mv88e6xxx_phy_ppu_read,
2922 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2923 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2924 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2925 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2926 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2927 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2928 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2929 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2930 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
5f436666 2931 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2932 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2933 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 2934 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2935 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2936 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2937 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2938 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2939 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2940 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2941 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2942 .ppu_enable = mv88e6185_g1_ppu_enable,
2943 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2944 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2945};
2946
990e27b0
VD		 2947static const struct mv88e6xxx_ops mv88e6141_ops = {
2948 /* MV88E6XXX_FAMILY_6341 */
2949 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2950 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2951 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2952 .phy_read = mv88e6xxx_g2_smi_phy_read,
2953 .phy_write = mv88e6xxx_g2_smi_phy_write,
2954 .port_set_link = mv88e6xxx_port_set_link,
2955 .port_set_duplex = mv88e6xxx_port_set_duplex,
2956 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2957 .port_set_speed = mv88e6390_port_set_speed,
2958 .port_tag_remap = mv88e6095_port_tag_remap,
2959 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2960 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2961 .port_set_ether_type = mv88e6351_port_set_ether_type,
2962 .port_jumbo_config = mv88e6165_port_jumbo_config,
2963 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2964 .port_pause_config = mv88e6097_port_pause_config,
2965 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2966 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2967 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2968 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2969 .stats_get_strings = mv88e6320_stats_get_strings,
2970 .stats_get_stats = mv88e6390_stats_get_stats,
2971 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
2972 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
2973 .watchdog_ops = &mv88e6390_watchdog_ops,
2974 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2975 .reset = mv88e6352_g1_reset,
2976};
2977
b3469dd8 2978static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2979 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2980 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2981 .phy_read = mv88e6165_phy_read,
2982 .phy_write = mv88e6165_phy_write,
08ef7f10 2983 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2984 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2985 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2986 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2987 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2988 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2989 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 2990 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2991 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2992 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2993 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2994 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2995 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2996 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2997 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2998 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2999 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3000 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3001 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3002 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3003 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3004};
3005
3006static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3007 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3008 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3009 .phy_read = mv88e6165_phy_read,
3010 .phy_write = mv88e6165_phy_write,
08ef7f10 3011 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3012 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3013 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 3014 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3015 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3016 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3017 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3018 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3019 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3020 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3021 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3022 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3023 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3024 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3025};
3026
3027static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3028 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3030 .phy_read = mv88e6xxx_g2_smi_phy_read,
3031 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3032 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3033 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3034 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3035 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3036 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3037 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3038 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3039 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3040 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3041 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3042 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3043 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3044 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3045 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3046 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3047 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3048 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3049 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3050 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3051 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3052 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3053 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3054};
3055
3056static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3057 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3058 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3059 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3060 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3061 .phy_read = mv88e6xxx_g2_smi_phy_read,
3062 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3063 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3064 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3065 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3066 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3067 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3068 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3069 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3070 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3071 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3072 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3073 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3074 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3075 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3076 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3077 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3078 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3079 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3080 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3081 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3082 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3083 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3084 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3085};
3086
3087static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3088 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3089 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3090 .phy_read = mv88e6xxx_g2_smi_phy_read,
3091 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3092 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3093 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3094 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3095 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3096 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3097 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3098 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3099 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3100 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3101 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3102 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3103 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3104 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3105 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3106 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3107 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3108 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3109 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3110 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3111 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3112 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3113 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3114};
3115
3116static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3117 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3118 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3119 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3120 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3121 .phy_read = mv88e6xxx_g2_smi_phy_read,
3122 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3123 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3124 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3125 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3126 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3127 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3128 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3129 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3130 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3131 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3132 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3133 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3134 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3135 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3136 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3137 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3138 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3139 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3140 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3141 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3142 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3143 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3144 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3145};
3146
3147static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3148 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3149 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3150 .phy_read = mv88e6xxx_phy_ppu_read,
3151 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3152 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3153 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3154 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3155 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 3156 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 3157 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 3158 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3159 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3160 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3161 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3162 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3163 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3164 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3165 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3166 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3167 .ppu_enable = mv88e6185_g1_ppu_enable,
3168 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3169 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3170};
3171
1a3b39ec 3172static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3173 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3174 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3175 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3176 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3177 .phy_read = mv88e6xxx_g2_smi_phy_read,
3178 .phy_write = mv88e6xxx_g2_smi_phy_write,
3179 .port_set_link = mv88e6xxx_port_set_link,
3180 .port_set_duplex = mv88e6xxx_port_set_duplex,
3181 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3182 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3183 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3184 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3185 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3186 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3187 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3188 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3189 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3190 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3191 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3192 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3193 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3194 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3195 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3196 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3197 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3198 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3199 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3200};
3201
3202static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3203 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3204 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3205 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3206 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3207 .phy_read = mv88e6xxx_g2_smi_phy_read,
3208 .phy_write = mv88e6xxx_g2_smi_phy_write,
3209 .port_set_link = mv88e6xxx_port_set_link,
3210 .port_set_duplex = mv88e6xxx_port_set_duplex,
3211 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3212 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3213 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3214 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3215 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3216 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3217 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3218 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3219 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3220 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3221 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3222 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3223 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3224 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3225 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3226 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3227 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3228 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3229 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3230};
3231
3232static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3233 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3234 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3235 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3236 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3237 .phy_read = mv88e6xxx_g2_smi_phy_read,
3238 .phy_write = mv88e6xxx_g2_smi_phy_write,
3239 .port_set_link = mv88e6xxx_port_set_link,
3240 .port_set_duplex = mv88e6xxx_port_set_duplex,
3241 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3242 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3243 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3244 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3245 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3246 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3247 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3248 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3249 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3250 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3251 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3252 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3253 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3254 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3255 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3256 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3257 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3258 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3259 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3260};
3261
b3469dd8 3262static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3263 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3264 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3265 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3266 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3267 .phy_read = mv88e6xxx_g2_smi_phy_read,
3268 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3269 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3270 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3271 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3272 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3273 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3274 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3275 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3276 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3277 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3278 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3279 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3280 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3281 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3282 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3283 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3284 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3285 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3286 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3287 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3288 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3289 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3290 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3291};
3292
1a3b39ec 3293static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3294 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3295 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3296 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3297 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3298 .phy_read = mv88e6xxx_g2_smi_phy_read,
3299 .phy_write = mv88e6xxx_g2_smi_phy_write,
3300 .port_set_link = mv88e6xxx_port_set_link,
3301 .port_set_duplex = mv88e6xxx_port_set_duplex,
3302 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3303 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3304 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3305 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3306 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3307 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3308 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3309 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3310 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3311 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3312 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3313 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3314 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3315 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3316 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3317 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3318 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3319 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3320 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3321 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3322};
3323
b3469dd8 3324static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3325 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3326 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3327 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3328 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3329 .phy_read = mv88e6xxx_g2_smi_phy_read,
3330 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3331 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3332 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3333 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3334 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3335 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3336 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3337 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3338 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3339 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3340 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3341 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3342 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3343 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3344 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3345 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3346 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3347 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3348 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3349 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3350 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3351};
3352
3353static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3354 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3355 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3356 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3357 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3358 .phy_read = mv88e6xxx_g2_smi_phy_read,
3359 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3360 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3361 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3362 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3363 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3364 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3365 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3366 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3367 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3368 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3369 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3370 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3371 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3372 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3373 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3374 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3375 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3376 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3377 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3378 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3379};
3380
16e329ae
VD		 3381static const struct mv88e6xxx_ops mv88e6341_ops = {
3382 /* MV88E6XXX_FAMILY_6341 */
3383 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3384 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3385 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3386 .phy_read = mv88e6xxx_g2_smi_phy_read,
3387 .phy_write = mv88e6xxx_g2_smi_phy_write,
3388 .port_set_link = mv88e6xxx_port_set_link,
3389 .port_set_duplex = mv88e6xxx_port_set_duplex,
3390 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3391 .port_set_speed = mv88e6390_port_set_speed,
3392 .port_tag_remap = mv88e6095_port_tag_remap,
3393 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3394 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3395 .port_set_ether_type = mv88e6351_port_set_ether_type,
3396 .port_jumbo_config = mv88e6165_port_jumbo_config,
3397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3398 .port_pause_config = mv88e6097_port_pause_config,
3399 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3400 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3401 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3402 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3403 .stats_get_strings = mv88e6320_stats_get_strings,
3404 .stats_get_stats = mv88e6390_stats_get_stats,
3405 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3406 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3407 .watchdog_ops = &mv88e6390_watchdog_ops,
3408 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3409 .reset = mv88e6352_g1_reset,
3410};
3411
b3469dd8 3412static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3413 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3414 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3415 .phy_read = mv88e6xxx_g2_smi_phy_read,
3416 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3417 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3418 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3419 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3420 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3421 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3422 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3423 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3424 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3425 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3426 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3427 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3428 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3429 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3430 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3431 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3432 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3433 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3434 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3435 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3436 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3437 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3438 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3439};
3440
3441static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3442 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3443 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3444 .phy_read = mv88e6xxx_g2_smi_phy_read,
3445 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3446 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3447 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3448 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3449 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3450 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3451 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3452 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3453 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3454 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3455 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3456 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3457 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3458 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3459 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3460 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3461 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3462 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3463 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3464 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3465 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3466 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3467 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3468};
3469
3470static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3471 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3472 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3473 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3475 .phy_read = mv88e6xxx_g2_smi_phy_read,
3476 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3477 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3478 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3479 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3480 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3481 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3482 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3483 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3484 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3485 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3486 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3487 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3488 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3489 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3490 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3491 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3492 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3493 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3494 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3495 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3496 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3497 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3498 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3499};
3500
1a3b39ec 3501static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3502 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3503 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3504 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3505 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3506 .phy_read = mv88e6xxx_g2_smi_phy_read,
3507 .phy_write = mv88e6xxx_g2_smi_phy_write,
3508 .port_set_link = mv88e6xxx_port_set_link,
3509 .port_set_duplex = mv88e6xxx_port_set_duplex,
3510 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3511 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3512 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3513 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3514 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3515 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3516 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3517 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3518 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3519 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3520 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3521 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3522 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3523 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3524 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3525 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3526 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3527 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3528 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3529 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3530 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3531 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3532};
3533
3534static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3535 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3536 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3537 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3538 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3539 .phy_read = mv88e6xxx_g2_smi_phy_read,
3540 .phy_write = mv88e6xxx_g2_smi_phy_write,
3541 .port_set_link = mv88e6xxx_port_set_link,
3542 .port_set_duplex = mv88e6xxx_port_set_duplex,
3543 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3544 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3545 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3546 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3547 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3548 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3549 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3550 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3551 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3552 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3553 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3554 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3555 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3556 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3557 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3558 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3559 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3560 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3561 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3562 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3563 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3564};
3565
3566static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3567 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3568 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3569 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3570 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3571 .phy_read = mv88e6xxx_g2_smi_phy_read,
3572 .phy_write = mv88e6xxx_g2_smi_phy_write,
3573 .port_set_link = mv88e6xxx_port_set_link,
3574 .port_set_duplex = mv88e6xxx_port_set_duplex,
3575 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3576 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3577 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3578 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3579 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3580 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3581 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3582 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3583 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3584 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3585 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3586 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3587 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3588 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3589 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3590 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3591 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3592 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3593 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3594};
3595
f81ec90f
VD		 3596static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3597 [MV88E6085] = {
3598 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3599 .family = MV88E6XXX_FAMILY_6097,
3600 .name = "Marvell 88E6085",
3601 .num_databases = 4096,
3602 .num_ports = 10,
9dddd478 3603 .port_base_addr = 0x10,
a935c052 3604 .global1_addr = 0x1b,
acddbd21 3605 .age_time_coeff = 15000,
dc30c35b 3606 .g1_irqs = 8,
e606ca36 3607 .atu_move_port_mask = 0xf,
443d5a1b 3608 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3609 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3610 .ops = &mv88e6085_ops,
f81ec90f
VD		 3611 },
3612
3613 [MV88E6095] = {
3614 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3615 .family = MV88E6XXX_FAMILY_6095,
3616 .name = "Marvell 88E6095/88E6095F",
3617 .num_databases = 256,
3618 .num_ports = 11,
9dddd478 3619 .port_base_addr = 0x10,
a935c052 3620 .global1_addr = 0x1b,
acddbd21 3621 .age_time_coeff = 15000,
dc30c35b 3622 .g1_irqs = 8,
e606ca36 3623 .atu_move_port_mask = 0xf,
443d5a1b 3624 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3625 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3626 .ops = &mv88e6095_ops,
f81ec90f
VD		 3627 },
3628
7d381a02
SE		 3629 [MV88E6097] = {
3630 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3631 .family = MV88E6XXX_FAMILY_6097,
3632 .name = "Marvell 88E6097/88E6097F",
3633 .num_databases = 4096,
3634 .num_ports = 11,
3635 .port_base_addr = 0x10,
3636 .global1_addr = 0x1b,
3637 .age_time_coeff = 15000,
c534178b 3638 .g1_irqs = 8,
e606ca36 3639 .atu_move_port_mask = 0xf,
2bfcfcd3 3640 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3641 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3642 .ops = &mv88e6097_ops,
3643 },
3644
f81ec90f
VD		 3645 [MV88E6123] = {
3646 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3647 .family = MV88E6XXX_FAMILY_6165,
3648 .name = "Marvell 88E6123",
3649 .num_databases = 4096,
3650 .num_ports = 3,
9dddd478 3651 .port_base_addr = 0x10,
a935c052 3652 .global1_addr = 0x1b,
acddbd21 3653 .age_time_coeff = 15000,
dc30c35b 3654 .g1_irqs = 9,
e606ca36 3655 .atu_move_port_mask = 0xf,
443d5a1b 3656 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3657 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3658 .ops = &mv88e6123_ops,
f81ec90f
VD		 3659 },
3660
3661 [MV88E6131] = {
3662 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3663 .family = MV88E6XXX_FAMILY_6185,
3664 .name = "Marvell 88E6131",
3665 .num_databases = 256,
3666 .num_ports = 8,
9dddd478 3667 .port_base_addr = 0x10,
a935c052 3668 .global1_addr = 0x1b,
acddbd21 3669 .age_time_coeff = 15000,
dc30c35b 3670 .g1_irqs = 9,
e606ca36 3671 .atu_move_port_mask = 0xf,
443d5a1b 3672 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3673 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3674 .ops = &mv88e6131_ops,
f81ec90f
VD		 3675 },
3676
990e27b0
VD		 3677 [MV88E6141] = {
3678 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3679 .family = MV88E6XXX_FAMILY_6341,
3680 .name = "Marvell 88E6341",
3681 .num_databases = 4096,
3682 .num_ports = 6,
3683 .port_base_addr = 0x10,
3684 .global1_addr = 0x1b,
3685 .age_time_coeff = 3750,
3686 .atu_move_port_mask = 0x1f,
3687 .tag_protocol = DSA_TAG_PROTO_EDSA,
3688 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3689 .ops = &mv88e6141_ops,
3690 },
3691
f81ec90f
VD		 3692 [MV88E6161] = {
3693 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3694 .family = MV88E6XXX_FAMILY_6165,
3695 .name = "Marvell 88E6161",
3696 .num_databases = 4096,
3697 .num_ports = 6,
9dddd478 3698 .port_base_addr = 0x10,
a935c052 3699 .global1_addr = 0x1b,
acddbd21 3700 .age_time_coeff = 15000,
dc30c35b 3701 .g1_irqs = 9,
e606ca36 3702 .atu_move_port_mask = 0xf,
443d5a1b 3703 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3704 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3705 .ops = &mv88e6161_ops,
f81ec90f
VD		 3706 },
3707
3708 [MV88E6165] = {
3709 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3710 .family = MV88E6XXX_FAMILY_6165,
3711 .name = "Marvell 88E6165",
3712 .num_databases = 4096,
3713 .num_ports = 6,
9dddd478 3714 .port_base_addr = 0x10,
a935c052 3715 .global1_addr = 0x1b,
acddbd21 3716 .age_time_coeff = 15000,
dc30c35b 3717 .g1_irqs = 9,
e606ca36 3718 .atu_move_port_mask = 0xf,
443d5a1b 3719 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3720 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3721 .ops = &mv88e6165_ops,
f81ec90f
VD		 3722 },
3723
3724 [MV88E6171] = {
3725 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3726 .family = MV88E6XXX_FAMILY_6351,
3727 .name = "Marvell 88E6171",
3728 .num_databases = 4096,
3729 .num_ports = 7,
9dddd478 3730 .port_base_addr = 0x10,
a935c052 3731 .global1_addr = 0x1b,
acddbd21 3732 .age_time_coeff = 15000,
dc30c35b 3733 .g1_irqs = 9,
e606ca36 3734 .atu_move_port_mask = 0xf,
443d5a1b 3735 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3736 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3737 .ops = &mv88e6171_ops,
f81ec90f
VD		 3738 },
3739
3740 [MV88E6172] = {
3741 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3742 .family = MV88E6XXX_FAMILY_6352,
3743 .name = "Marvell 88E6172",
3744 .num_databases = 4096,
3745 .num_ports = 7,
9dddd478 3746 .port_base_addr = 0x10,
a935c052 3747 .global1_addr = 0x1b,
acddbd21 3748 .age_time_coeff = 15000,
dc30c35b 3749 .g1_irqs = 9,
e606ca36 3750 .atu_move_port_mask = 0xf,
443d5a1b 3751 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3752 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3753 .ops = &mv88e6172_ops,
f81ec90f
VD		 3754 },
3755
3756 [MV88E6175] = {
3757 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3758 .family = MV88E6XXX_FAMILY_6351,
3759 .name = "Marvell 88E6175",
3760 .num_databases = 4096,
3761 .num_ports = 7,
9dddd478 3762 .port_base_addr = 0x10,
a935c052 3763 .global1_addr = 0x1b,
acddbd21 3764 .age_time_coeff = 15000,
dc30c35b 3765 .g1_irqs = 9,
e606ca36 3766 .atu_move_port_mask = 0xf,
443d5a1b 3767 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3768 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3769 .ops = &mv88e6175_ops,
f81ec90f
VD		 3770 },
3771
3772 [MV88E6176] = {
3773 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3774 .family = MV88E6XXX_FAMILY_6352,
3775 .name = "Marvell 88E6176",
3776 .num_databases = 4096,
3777 .num_ports = 7,
9dddd478 3778 .port_base_addr = 0x10,
a935c052 3779 .global1_addr = 0x1b,
acddbd21 3780 .age_time_coeff = 15000,
dc30c35b 3781 .g1_irqs = 9,
e606ca36 3782 .atu_move_port_mask = 0xf,
443d5a1b 3783 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3784 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3785 .ops = &mv88e6176_ops,
f81ec90f
VD		 3786 },
3787
3788 [MV88E6185] = {
3789 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3790 .family = MV88E6XXX_FAMILY_6185,
3791 .name = "Marvell 88E6185",
3792 .num_databases = 256,
3793 .num_ports = 10,
9dddd478 3794 .port_base_addr = 0x10,
a935c052 3795 .global1_addr = 0x1b,
acddbd21 3796 .age_time_coeff = 15000,
dc30c35b 3797 .g1_irqs = 8,
e606ca36 3798 .atu_move_port_mask = 0xf,
443d5a1b 3799 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3800 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3801 .ops = &mv88e6185_ops,
f81ec90f
VD		 3802 },
3803
1a3b39ec
AL		 3804 [MV88E6190] = {
3805 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3806 .family = MV88E6XXX_FAMILY_6390,
3807 .name = "Marvell 88E6190",
3808 .num_databases = 4096,
3809 .num_ports = 11, /* 10 + Z80 */
3810 .port_base_addr = 0x0,
3811 .global1_addr = 0x1b,
443d5a1b 3812 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3813 .age_time_coeff = 3750,
1a3b39ec 3814 .g1_irqs = 9,
e606ca36 3815 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3816 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3817 .ops = &mv88e6190_ops,
3818 },
3819
3820 [MV88E6190X] = {
3821 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3822 .family = MV88E6XXX_FAMILY_6390,
3823 .name = "Marvell 88E6190X",
3824 .num_databases = 4096,
3825 .num_ports = 11, /* 10 + Z80 */
3826 .port_base_addr = 0x0,
3827 .global1_addr = 0x1b,
b91e055c 3828 .age_time_coeff = 3750,
1a3b39ec 3829 .g1_irqs = 9,
e606ca36 3830 .atu_move_port_mask = 0x1f,
443d5a1b 3831 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3832 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3833 .ops = &mv88e6190x_ops,
3834 },
3835
3836 [MV88E6191] = {
3837 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3838 .family = MV88E6XXX_FAMILY_6390,
3839 .name = "Marvell 88E6191",
3840 .num_databases = 4096,
3841 .num_ports = 11, /* 10 + Z80 */
3842 .port_base_addr = 0x0,
3843 .global1_addr = 0x1b,
b91e055c 3844 .age_time_coeff = 3750,
443d5a1b 3845 .g1_irqs = 9,
e606ca36 3846 .atu_move_port_mask = 0x1f,
443d5a1b 3847 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3848 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3849 .ops = &mv88e6391_ops,
3850 },
3851
f81ec90f
VD		 3852 [MV88E6240] = {
3853 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3854 .family = MV88E6XXX_FAMILY_6352,
3855 .name = "Marvell 88E6240",
3856 .num_databases = 4096,
3857 .num_ports = 7,
9dddd478 3858 .port_base_addr = 0x10,
a935c052 3859 .global1_addr = 0x1b,
acddbd21 3860 .age_time_coeff = 15000,
dc30c35b 3861 .g1_irqs = 9,
e606ca36 3862 .atu_move_port_mask = 0xf,
443d5a1b 3863 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3864 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3865 .ops = &mv88e6240_ops,
f81ec90f
VD		 3866 },
3867
1a3b39ec
AL		 3868 [MV88E6290] = {
3869 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3870 .family = MV88E6XXX_FAMILY_6390,
3871 .name = "Marvell 88E6290",
3872 .num_databases = 4096,
3873 .num_ports = 11, /* 10 + Z80 */
3874 .port_base_addr = 0x0,
3875 .global1_addr = 0x1b,
b91e055c 3876 .age_time_coeff = 3750,
1a3b39ec 3877 .g1_irqs = 9,
e606ca36 3878 .atu_move_port_mask = 0x1f,
443d5a1b 3879 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3880 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3881 .ops = &mv88e6290_ops,
3882 },
3883
f81ec90f
VD		 3884 [MV88E6320] = {
3885 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3886 .family = MV88E6XXX_FAMILY_6320,
3887 .name = "Marvell 88E6320",
3888 .num_databases = 4096,
3889 .num_ports = 7,
9dddd478 3890 .port_base_addr = 0x10,
a935c052 3891 .global1_addr = 0x1b,
acddbd21 3892 .age_time_coeff = 15000,
dc30c35b 3893 .g1_irqs = 8,
e606ca36 3894 .atu_move_port_mask = 0xf,
443d5a1b 3895 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3896 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3897 .ops = &mv88e6320_ops,
f81ec90f
VD		 3898 },
3899
3900 [MV88E6321] = {
3901 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3902 .family = MV88E6XXX_FAMILY_6320,
3903 .name = "Marvell 88E6321",
3904 .num_databases = 4096,
3905 .num_ports = 7,
9dddd478 3906 .port_base_addr = 0x10,
a935c052 3907 .global1_addr = 0x1b,
acddbd21 3908 .age_time_coeff = 15000,
dc30c35b 3909 .g1_irqs = 8,
e606ca36 3910 .atu_move_port_mask = 0xf,
443d5a1b 3911 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3912 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3913 .ops = &mv88e6321_ops,
f81ec90f
VD		 3914 },
3915
a75961d0
GC		 3916 [MV88E6341] = {
3917 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
3918 .family = MV88E6XXX_FAMILY_6341,
3919 .name = "Marvell 88E6341",
3920 .num_databases = 4096,
3921 .num_ports = 6,
3922 .port_base_addr = 0x10,
3923 .global1_addr = 0x1b,
3924 .age_time_coeff = 3750,
e606ca36 3925 .atu_move_port_mask = 0x1f,
a75961d0
GC		 3926 .tag_protocol = DSA_TAG_PROTO_EDSA,
3927 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3928 .ops = &mv88e6341_ops,
3929 },
3930
f81ec90f
VD		 3931 [MV88E6350] = {
3932 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3933 .family = MV88E6XXX_FAMILY_6351,
3934 .name = "Marvell 88E6350",
3935 .num_databases = 4096,
3936 .num_ports = 7,
9dddd478 3937 .port_base_addr = 0x10,
a935c052 3938 .global1_addr = 0x1b,
acddbd21 3939 .age_time_coeff = 15000,
dc30c35b 3940 .g1_irqs = 9,
e606ca36 3941 .atu_move_port_mask = 0xf,
443d5a1b 3942 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3943 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3944 .ops = &mv88e6350_ops,
f81ec90f
VD		 3945 },
3946
3947 [MV88E6351] = {
3948 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3949 .family = MV88E6XXX_FAMILY_6351,
3950 .name = "Marvell 88E6351",
3951 .num_databases = 4096,
3952 .num_ports = 7,
9dddd478 3953 .port_base_addr = 0x10,
a935c052 3954 .global1_addr = 0x1b,
acddbd21 3955 .age_time_coeff = 15000,
dc30c35b 3956 .g1_irqs = 9,
e606ca36 3957 .atu_move_port_mask = 0xf,
443d5a1b 3958 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3959 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3960 .ops = &mv88e6351_ops,
f81ec90f
VD		 3961 },
3962
3963 [MV88E6352] = {
3964 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3965 .family = MV88E6XXX_FAMILY_6352,
3966 .name = "Marvell 88E6352",
3967 .num_databases = 4096,
3968 .num_ports = 7,
9dddd478 3969 .port_base_addr = 0x10,
a935c052 3970 .global1_addr = 0x1b,
acddbd21 3971 .age_time_coeff = 15000,
dc30c35b 3972 .g1_irqs = 9,
e606ca36 3973 .atu_move_port_mask = 0xf,
443d5a1b 3974 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3975 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3976 .ops = &mv88e6352_ops,
f81ec90f 3977 },
1a3b39ec
AL		 3978 [MV88E6390] = {
3979 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3980 .family = MV88E6XXX_FAMILY_6390,
3981 .name = "Marvell 88E6390",
3982 .num_databases = 4096,
3983 .num_ports = 11, /* 10 + Z80 */
3984 .port_base_addr = 0x0,
3985 .global1_addr = 0x1b,
b91e055c 3986 .age_time_coeff = 3750,
1a3b39ec 3987 .g1_irqs = 9,
e606ca36 3988 .atu_move_port_mask = 0x1f,
443d5a1b 3989 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3990 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3991 .ops = &mv88e6390_ops,
3992 },
3993 [MV88E6390X] = {
3994 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3995 .family = MV88E6XXX_FAMILY_6390,
3996 .name = "Marvell 88E6390X",
3997 .num_databases = 4096,
3998 .num_ports = 11, /* 10 + Z80 */
3999 .port_base_addr = 0x0,
4000 .global1_addr = 0x1b,
b91e055c 4001 .age_time_coeff = 3750,
1a3b39ec 4002 .g1_irqs = 9,
e606ca36 4003 .atu_move_port_mask = 0x1f,
443d5a1b 4004 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4005 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4006 .ops = &mv88e6390x_ops,
4007 },
f81ec90f
VD		 4008};
4009
5f7c0367 4010static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4011{
a439c061 4012 int i;
b9b37713 4013
5f7c0367
VD		 4014 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4015 if (mv88e6xxx_table[i].prod_num == prod_num)
4016 return &mv88e6xxx_table[i];
b9b37713 4017
b9b37713
VD		 4018 return NULL;
4019}
4020
fad09c73 4021static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4022{
4023 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4024 unsigned int prod_num, rev;
4025 u16 id;
4026 int err;
bc46a3d5 4027
8f6345b2
VD		 4028 mutex_lock(&chip->reg_lock);
4029 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4030 mutex_unlock(&chip->reg_lock);
4031 if (err)
4032 return err;
bc46a3d5
VD		 4033
4034 prod_num = (id & 0xfff0) >> 4;
4035 rev = id & 0x000f;
4036
4037 info = mv88e6xxx_lookup_info(prod_num);
4038 if (!info)
4039 return -ENODEV;
4040
caac8545 4041 /* Update the compatible info with the probed one */
fad09c73 4042 chip->info = info;
bc46a3d5 4043
ca070c10
VD		 4044 err = mv88e6xxx_g2_require(chip);
4045 if (err)
4046 return err;
4047
fad09c73
VD		 4048 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4049 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4050
4051 return 0;
4052}
4053
fad09c73 4054static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4055{
fad09c73 4056 struct mv88e6xxx_chip *chip;
469d729f 4057
fad09c73
VD		 4058 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4059 if (!chip)
469d729f
VD		 4060 return NULL;
4061
fad09c73 4062 chip->dev = dev;
469d729f 4063
fad09c73 4064 mutex_init(&chip->reg_lock);
a3c53be5 4065 INIT_LIST_HEAD(&chip->mdios);
469d729f 4066
fad09c73 4067 return chip;
469d729f
VD		 4068}
4069
e57e5e77
VD		 4070static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4071{
a199d8b6 4072 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4073 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4074}
4075
930188ce
AL		 4076static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4077{
a199d8b6 4078 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4079 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4080}
4081
fad09c73 4082static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4083 struct mii_bus *bus, int sw_addr)
4084{
914b32f6 4085 if (sw_addr == 0)
fad09c73 4086 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4087 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4088 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4089 else
4090 return -EINVAL;
4091
fad09c73
VD		 4092 chip->bus = bus;
4093 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4094
4095 return 0;
4096}
4097
7b314362
AL		 4098static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4099{
04bed143 4100 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4101
443d5a1b 4102 return chip->info->tag_protocol;
7b314362
AL		 4103}
4104
fcdce7d0
AL		 4105static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4106 struct device *host_dev, int sw_addr,
4107 void **priv)
a77d43f1 4108{
fad09c73 4109 struct mv88e6xxx_chip *chip;
a439c061 4110 struct mii_bus *bus;
b516d453 4111 int err;
a77d43f1 4112
a439c061 4113 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4114 if (!bus)
4115 return NULL;
4116
fad09c73
VD		 4117 chip = mv88e6xxx_alloc_chip(dsa_dev);
4118 if (!chip)
469d729f
VD		 4119 return NULL;
4120
caac8545 4121 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4122 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4123
fad09c73 4124 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4125 if (err)
4126 goto free;
4127
fad09c73 4128 err = mv88e6xxx_detect(chip);
bc46a3d5 4129 if (err)
469d729f 4130 goto free;
a439c061 4131
dc30c35b
AL		 4132 mutex_lock(&chip->reg_lock);
4133 err = mv88e6xxx_switch_reset(chip);
4134 mutex_unlock(&chip->reg_lock);
4135 if (err)
4136 goto free;
4137
e57e5e77
VD		 4138 mv88e6xxx_phy_init(chip);
4139
a3c53be5 4140 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4141 if (err)
469d729f 4142 goto free;
b516d453 4143
fad09c73 4144 *priv = chip;
a439c061 4145
fad09c73 4146 return chip->info->name;
469d729f 4147free:
fad09c73 4148 devm_kfree(dsa_dev, chip);
469d729f
VD		 4149
4150 return NULL;
a77d43f1
AL		 4151}
4152
7df8fbdd
VD		 4153static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4154 const struct switchdev_obj_port_mdb *mdb,
4155 struct switchdev_trans *trans)
4156{
4157 /* We don't need any dynamic resource from the kernel (yet),
4158 * so skip the prepare phase.
4159 */
4160
4161 return 0;
4162}
4163
4164static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4165 const struct switchdev_obj_port_mdb *mdb,
4166 struct switchdev_trans *trans)
4167{
04bed143 4168 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4169
4170 mutex_lock(&chip->reg_lock);
4171 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4172 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4173 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4174 mutex_unlock(&chip->reg_lock);
4175}
4176
4177static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4178 const struct switchdev_obj_port_mdb *mdb)
4179{
04bed143 4180 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4181 int err;
4182
4183 mutex_lock(&chip->reg_lock);
4184 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4185 GLOBAL_ATU_DATA_STATE_UNUSED);
4186 mutex_unlock(&chip->reg_lock);
4187
4188 return err;
4189}
4190
4191static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4192 struct switchdev_obj_port_mdb *mdb,
4193 int (*cb)(struct switchdev_obj *obj))
4194{
04bed143 4195 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4196 int err;
4197
4198 mutex_lock(&chip->reg_lock);
4199 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4200 mutex_unlock(&chip->reg_lock);
4201
4202 return err;
4203}
4204
a82f67af 4205static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4206 .probe = mv88e6xxx_drv_probe,
7b314362 4207 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4208 .setup = mv88e6xxx_setup,
4209 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4210 .adjust_link = mv88e6xxx_adjust_link,
4211 .get_strings = mv88e6xxx_get_strings,
4212 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4213 .get_sset_count = mv88e6xxx_get_sset_count,
4214 .set_eee = mv88e6xxx_set_eee,
4215 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4216 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4217 .get_eeprom = mv88e6xxx_get_eeprom,
4218 .set_eeprom = mv88e6xxx_set_eeprom,
4219 .get_regs_len = mv88e6xxx_get_regs_len,
4220 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4221 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4222 .port_bridge_join = mv88e6xxx_port_bridge_join,
4223 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4224 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4225 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4226 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4227 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4228 .port_vlan_add = mv88e6xxx_port_vlan_add,
4229 .port_vlan_del = mv88e6xxx_port_vlan_del,
4230 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4231 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4232 .port_fdb_add = mv88e6xxx_port_fdb_add,
4233 .port_fdb_del = mv88e6xxx_port_fdb_del,
4234 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4235 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4236 .port_mdb_add = mv88e6xxx_port_mdb_add,
4237 .port_mdb_del = mv88e6xxx_port_mdb_del,
4238 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4239};
4240
ab3d408d
FF		 4241static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4242 .ops = &mv88e6xxx_switch_ops,
4243};
4244
55ed0ce0 4245static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4246{
fad09c73 4247 struct device *dev = chip->dev;
b7e66a5f
VD		 4248 struct dsa_switch *ds;
4249
a0c02161 4250 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
b7e66a5f
VD		 4251 if (!ds)
4252 return -ENOMEM;
4253
fad09c73 4254 ds->priv = chip;
9d490b4e 4255 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 4256 ds->ageing_time_min = chip->info->age_time_coeff;
4257 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 4258
4259 dev_set_drvdata(dev, ds);
4260
55ed0ce0 4261 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4262}
4263
fad09c73 4264static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4265{
fad09c73 4266 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4267}
4268
57d32310 4269static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4270{
14c7b3c3 4271 struct device *dev = &mdiodev->dev;
f8cd8753 4272 struct device_node *np = dev->of_node;
caac8545 4273 const struct mv88e6xxx_info *compat_info;
fad09c73 4274 struct mv88e6xxx_chip *chip;
f8cd8753 4275 u32 eeprom_len;
52638f71 4276 int err;
14c7b3c3 4277
caac8545
VD		 4278 compat_info = of_device_get_match_data(dev);
4279 if (!compat_info)
4280 return -EINVAL;
4281
fad09c73
VD		 4282 chip = mv88e6xxx_alloc_chip(dev);
4283 if (!chip)
14c7b3c3
AL		 4284 return -ENOMEM;
4285
fad09c73 4286 chip->info = compat_info;
caac8545 4287
fad09c73 4288 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4289 if (err)
4290 return err;
14c7b3c3 4291
b4308f04
AL		 4292 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4293 if (IS_ERR(chip->reset))
4294 return PTR_ERR(chip->reset);
4295
fad09c73 4296 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4297 if (err)
4298 return err;
14c7b3c3 4299
e57e5e77
VD		 4300 mv88e6xxx_phy_init(chip);
4301
ee4dc2e7 4302 if (chip->info->ops->get_eeprom &&
f8cd8753 4303 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4304 chip->eeprom_len = eeprom_len;
f8cd8753 4305
dc30c35b
AL		 4306 mutex_lock(&chip->reg_lock);
4307 err = mv88e6xxx_switch_reset(chip);
4308 mutex_unlock(&chip->reg_lock);
4309 if (err)
4310 goto out;
4311
4312 chip->irq = of_irq_get(np, 0);
4313 if (chip->irq == -EPROBE_DEFER) {
4314 err = chip->irq;
4315 goto out;
4316 }
4317
4318 if (chip->irq > 0) {
4319 /* Has to be performed before the MDIO bus is created,
4320 * because the PHYs will link there interrupts to these
4321 * interrupt controllers
4322 */
4323 mutex_lock(&chip->reg_lock);
4324 err = mv88e6xxx_g1_irq_setup(chip);
4325 mutex_unlock(&chip->reg_lock);
4326
4327 if (err)
4328 goto out;
4329
4330 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4331 err = mv88e6xxx_g2_irq_setup(chip);
4332 if (err)
4333 goto out_g1_irq;
4334 }
4335 }
4336
a3c53be5 4337 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4338 if (err)
dc30c35b 4339 goto out_g2_irq;
b516d453 4340
55ed0ce0 4341 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4342 if (err)
4343 goto out_mdio;
83c0afae 4344
98e67308 4345 return 0;
dc30c35b
AL		 4346
4347out_mdio:
a3c53be5 4348 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4349out_g2_irq:
46712644 4350 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4351 mv88e6xxx_g2_irq_free(chip);
4352out_g1_irq:
61f7c3f8
AL		 4353 if (chip->irq > 0) {
4354 mutex_lock(&chip->reg_lock);
46712644 4355 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4356 mutex_unlock(&chip->reg_lock);
4357 }
dc30c35b
AL		 4358out:
4359 return err;
98e67308 4360}
14c7b3c3
AL		 4361
4362static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4363{
4364 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4365 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4366
930188ce 4367 mv88e6xxx_phy_destroy(chip);
fad09c73 4368 mv88e6xxx_unregister_switch(chip);
a3c53be5 4369 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4370
46712644
AL		 4371 if (chip->irq > 0) {
4372 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4373 mv88e6xxx_g2_irq_free(chip);
4374 mv88e6xxx_g1_irq_free(chip);
4375 }
14c7b3c3
AL		 4376}
4377
4378static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4379 {
4380 .compatible = "marvell,mv88e6085",
4381 .data = &mv88e6xxx_table[MV88E6085],
4382 },
1a3b39ec
AL		 4383 {
4384 .compatible = "marvell,mv88e6190",
4385 .data = &mv88e6xxx_table[MV88E6190],
4386 },
14c7b3c3
AL		 4387 { /* sentinel */ },
4388};
4389
4390MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4391
4392static struct mdio_driver mv88e6xxx_driver = {
4393 .probe = mv88e6xxx_probe,
4394 .remove = mv88e6xxx_remove,
4395 .mdiodrv.driver = {
4396 .name = "mv88e6085",
4397 .of_match_table = mv88e6xxx_of_match,
4398 },
4399};
4400
4401static int __init mv88e6xxx_init(void)
4402{
ab3d408d 4403 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4404 return mdio_driver_register(&mv88e6xxx_driver);
4405}
98e67308
BH		 4406module_init(mv88e6xxx_init);
4407
4408static void __exit mv88e6xxx_cleanup(void)
4409{
14c7b3c3 4410 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4411 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4412}
4413module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4414
4415MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4416MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4417MODULE_LICENSE("GPL");
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