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[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
91da11f8 40
fad09c73 41static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 42{
fad09c73
VD		 43 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
44 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 45 dump_stack();
46 }
47}
48
914b32f6
VD		 49/* The switch ADDR[4:1] configuration pins define the chip SMI device address
50 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
51 *
52 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
53 * is the only device connected to the SMI master. In this mode it responds to
54 * all 32 possible SMI addresses, and thus maps directly the internal devices.
55 *
56 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
57 * multiple devices to share the SMI interface. In this mode it responds to only
58 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 59 */
914b32f6 60
fad09c73 61static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 62 int addr, int reg, u16 *val)
63{
fad09c73 64 if (!chip->smi_ops)
914b32f6
VD		 65 return -EOPNOTSUPP;
66
fad09c73 67 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 68}
69
fad09c73 70static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 71 int addr, int reg, u16 val)
72{
fad09c73 73 if (!chip->smi_ops)
914b32f6
VD		 74 return -EOPNOTSUPP;
75
fad09c73 76 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 77}
78
fad09c73 79static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 80 int addr, int reg, u16 *val)
81{
82 int ret;
83
fad09c73 84 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 85 if (ret < 0)
86 return ret;
87
88 *val = ret & 0xffff;
89
90 return 0;
91}
92
fad09c73 93static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 94 int addr, int reg, u16 val)
95{
96 int ret;
97
fad09c73 98 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 99 if (ret < 0)
100 return ret;
101
102 return 0;
103}
104
c08026ab 105static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 106 .read = mv88e6xxx_smi_single_chip_read,
107 .write = mv88e6xxx_smi_single_chip_write,
108};
109
fad09c73 110static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 111{
112 int ret;
113 int i;
114
115 for (i = 0; i < 16; i++) {
fad09c73 116 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 117 if (ret < 0)
118 return ret;
119
cca8b133 120 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 121 return 0;
122 }
123
124 return -ETIMEDOUT;
125}
126
fad09c73 127static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 128 int addr, int reg, u16 *val)
91da11f8
LB		 129{
130 int ret;
131
3675c8d7 132 /* Wait for the bus to become free. */
fad09c73 133 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 134 if (ret < 0)
135 return ret;
136
3675c8d7 137 /* Transmit the read command. */
fad09c73 138 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 139 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 140 if (ret < 0)
141 return ret;
142
3675c8d7 143 /* Wait for the read command to complete. */
fad09c73 144 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 145 if (ret < 0)
146 return ret;
147
3675c8d7 148 /* Read the data. */
fad09c73 149 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 150 if (ret < 0)
151 return ret;
152
914b32f6 153 *val = ret & 0xffff;
91da11f8 154
914b32f6 155 return 0;
8d6d09e7
GR		 156}
157
fad09c73 158static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 159 int addr, int reg, u16 val)
91da11f8
LB		 160{
161 int ret;
162
3675c8d7 163 /* Wait for the bus to become free. */
fad09c73 164 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 165 if (ret < 0)
166 return ret;
167
3675c8d7 168 /* Transmit the data to write. */
fad09c73 169 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 170 if (ret < 0)
171 return ret;
172
3675c8d7 173 /* Transmit the write command. */
fad09c73 174 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 175 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 176 if (ret < 0)
177 return ret;
178
3675c8d7 179 /* Wait for the write command to complete. */
fad09c73 180 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 181 if (ret < 0)
182 return ret;
183
184 return 0;
185}
186
c08026ab 187static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 188 .read = mv88e6xxx_smi_multi_chip_read,
189 .write = mv88e6xxx_smi_multi_chip_write,
190};
191
ec561276 192int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 193{
194 int err;
195
fad09c73 196 assert_reg_lock(chip);
914b32f6 197
fad09c73 198 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 199 if (err)
200 return err;
201
fad09c73 202 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 203 addr, reg, *val);
204
205 return 0;
206}
207
ec561276 208int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 209{
914b32f6
VD		 210 int err;
211
fad09c73 212 assert_reg_lock(chip);
91da11f8 213
fad09c73 214 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 215 if (err)
216 return err;
217
fad09c73 218 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 219 addr, reg, val);
220
914b32f6
VD		 221 return 0;
222}
223
b3f5bf64
WY		 224static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
225 u16 *val)
0e7b9925
AL		 226{
227 int addr = chip->info->port_base_addr + port;
228
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
b3f5bf64
WY		 232static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
233 u16 val)
0e7b9925
AL		 234{
235 int addr = chip->info->port_base_addr + port;
236
237 return mv88e6xxx_write(chip, addr, reg, val);
238}
239
e57e5e77
VD		 240static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
241 int reg, u16 *val)
242{
243 int addr = phy; /* PHY devices addresses start at 0x0 */
244
b3469dd8 245 if (!chip->info->ops->phy_read)
e57e5e77
VD		 246 return -EOPNOTSUPP;
247
b3469dd8 248 return chip->info->ops->phy_read(chip, addr, reg, val);
e57e5e77
VD		 249}
250
251static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
255
b3469dd8 256 if (!chip->info->ops->phy_write)
e57e5e77
VD		 257 return -EOPNOTSUPP;
258
b3469dd8 259 return chip->info->ops->phy_write(chip, addr, reg, val);
e57e5e77
VD		 260}
261
09cb7dfd
VD		 262static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
263{
264 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
265 return -EOPNOTSUPP;
266
267 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
268}
269
270static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
271{
272 int err;
273
274 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
275 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
276 if (unlikely(err)) {
277 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
278 phy, err);
279 }
280}
281
282static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
283 u8 page, int reg, u16 *val)
284{
285 int err;
286
287 /* There is no paging for registers 22 */
288 if (reg == PHY_PAGE)
289 return -EINVAL;
290
291 err = mv88e6xxx_phy_page_get(chip, phy, page);
292 if (!err) {
293 err = mv88e6xxx_phy_read(chip, phy, reg, val);
294 mv88e6xxx_phy_page_put(chip, phy);
295 }
296
297 return err;
298}
299
300static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
301 u8 page, int reg, u16 val)
302{
303 int err;
304
305 /* There is no paging for registers 22 */
306 if (reg == PHY_PAGE)
307 return -EINVAL;
308
309 err = mv88e6xxx_phy_page_get(chip, phy, page);
310 if (!err) {
311 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
312 mv88e6xxx_phy_page_put(chip, phy);
313 }
314
315 return err;
316}
317
318static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
319{
320 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
321 reg, val);
322}
323
324static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
325{
326 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
327 reg, val);
328}
329
dc30c35b
AL		 330static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
331{
332 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
333 unsigned int n = d->hwirq;
334
335 chip->g1_irq.masked |= (1 << n);
336}
337
338static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
339{
340 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
341 unsigned int n = d->hwirq;
342
343 chip->g1_irq.masked &= ~(1 << n);
344}
345
346static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
347{
348 struct mv88e6xxx_chip *chip = dev_id;
349 unsigned int nhandled = 0;
350 unsigned int sub_irq;
351 unsigned int n;
352 u16 reg;
353 int err;
354
355 mutex_lock(&chip->reg_lock);
356 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
357 mutex_unlock(&chip->reg_lock);
358
359 if (err)
360 goto out;
361
362 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
363 if (reg & (1 << n)) {
364 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
365 handle_nested_irq(sub_irq);
366 ++nhandled;
367 }
368 }
369out:
370 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
371}
372
373static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
374{
375 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
376
377 mutex_lock(&chip->reg_lock);
378}
379
380static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
381{
382 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
383 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
384 u16 reg;
385 int err;
386
387 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
388 if (err)
389 goto out;
390
391 reg &= ~mask;
392 reg |= (~chip->g1_irq.masked & mask);
393
394 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
395 if (err)
396 goto out;
397
398out:
399 mutex_unlock(&chip->reg_lock);
400}
401
402static struct irq_chip mv88e6xxx_g1_irq_chip = {
403 .name = "mv88e6xxx-g1",
404 .irq_mask = mv88e6xxx_g1_irq_mask,
405 .irq_unmask = mv88e6xxx_g1_irq_unmask,
406 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
407 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
408};
409
410static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
411 unsigned int irq,
412 irq_hw_number_t hwirq)
413{
414 struct mv88e6xxx_chip *chip = d->host_data;
415
416 irq_set_chip_data(irq, d->host_data);
417 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
418 irq_set_noprobe(irq);
419
420 return 0;
421}
422
423static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
424 .map = mv88e6xxx_g1_irq_domain_map,
425 .xlate = irq_domain_xlate_twocell,
426};
427
428static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
429{
430 int irq, virq;
431
432 for (irq = 0; irq < 16; irq++) {
433 virq = irq_find_mapping(chip->g2_irq.domain, irq);
434 irq_dispose_mapping(virq);
435 }
436
437 irq_domain_remove(chip->g2_irq.domain);
438}
439
440static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
441{
442 int err, irq;
443 u16 reg;
444
445 chip->g1_irq.nirqs = chip->info->g1_irqs;
446 chip->g1_irq.domain = irq_domain_add_simple(
447 NULL, chip->g1_irq.nirqs, 0,
448 &mv88e6xxx_g1_irq_domain_ops, chip);
449 if (!chip->g1_irq.domain)
450 return -ENOMEM;
451
452 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
453 irq_create_mapping(chip->g1_irq.domain, irq);
454
455 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
456 chip->g1_irq.masked = ~0;
457
458 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
459 if (err)
460 goto out;
461
462 reg &= ~GENMASK(chip->g1_irq.nirqs, 0);
463
464 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
465 if (err)
466 goto out;
467
468 /* Reading the interrupt status clears (most of) them */
469 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
470 if (err)
471 goto out;
472
473 err = request_threaded_irq(chip->irq, NULL,
474 mv88e6xxx_g1_irq_thread_fn,
475 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
476 dev_name(chip->dev), chip);
477 if (err)
478 goto out;
479
480 return 0;
481
482out:
483 mv88e6xxx_g1_irq_free(chip);
484
485 return err;
486}
487
ec561276 488int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 489{
6441e669 490 int i;
2d79af6e 491
6441e669 492 for (i = 0; i < 16; i++) {
2d79af6e
VD		 493 u16 val;
494 int err;
495
496 err = mv88e6xxx_read(chip, addr, reg, &val);
497 if (err)
498 return err;
499
500 if (!(val & mask))
501 return 0;
502
503 usleep_range(1000, 2000);
504 }
505
30853553 506 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 507 return -ETIMEDOUT;
508}
509
f22ab641 510/* Indirect write to single pointer-data register with an Update bit */
ec561276 511int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 512{
513 u16 val;
0f02b4f7 514 int err;
f22ab641
VD		 515
516 /* Wait until the previous operation is completed */
0f02b4f7
AL		 517 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
518 if (err)
519 return err;
f22ab641
VD		 520
521 /* Set the Update bit to trigger a write operation */
522 val = BIT(15) | update;
523
524 return mv88e6xxx_write(chip, addr, reg, val);
525}
526
a935c052 527static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6
VD		 528{
529 u16 val;
a935c052 530 int i, err;
914b32f6 531
a935c052 532 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
914b32f6
VD		 533 if (err)
534 return err;
535
a935c052
VD		 536 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
537 val & ~GLOBAL_CONTROL_PPU_ENABLE);
538 if (err)
539 return err;
2e5f0320 540
6441e669 541 for (i = 0; i < 16; i++) {
a935c052
VD		 542 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
543 if (err)
544 return err;
48ace4ef 545
19b2f97e 546 usleep_range(1000, 2000);
a935c052 547 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
85686581 548 return 0;
2e5f0320
LB		 549 }
550
551 return -ETIMEDOUT;
552}
553
fad09c73 554static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 555{
a935c052
VD		 556 u16 val;
557 int i, err;
2e5f0320 558
a935c052
VD		 559 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
560 if (err)
561 return err;
48ace4ef 562
a935c052
VD		 563 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
564 val | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 565 if (err)
566 return err;
2e5f0320 567
6441e669 568 for (i = 0; i < 16; i++) {
a935c052
VD		 569 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
570 if (err)
571 return err;
48ace4ef 572
19b2f97e 573 usleep_range(1000, 2000);
a935c052 574 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
85686581 575 return 0;
2e5f0320
LB		 576 }
577
578 return -ETIMEDOUT;
579}
580
581static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
582{
fad09c73 583 struct mv88e6xxx_chip *chip;
2e5f0320 584
fad09c73 585 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 586
fad09c73 587 mutex_lock(&chip->reg_lock);
762eb67b 588
fad09c73
VD		 589 if (mutex_trylock(&chip->ppu_mutex)) {
590 if (mv88e6xxx_ppu_enable(chip) == 0)
591 chip->ppu_disabled = 0;
592 mutex_unlock(&chip->ppu_mutex);
2e5f0320 593 }
762eb67b 594
fad09c73 595 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 596}
597
598static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
599{
fad09c73 600 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 601
fad09c73 602 schedule_work(&chip->ppu_work);
2e5f0320
LB		 603}
604
fad09c73 605static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 606{
2e5f0320
LB		 607 int ret;
608
fad09c73 609 mutex_lock(&chip->ppu_mutex);
2e5f0320 610
3675c8d7 611 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 612 * we can access the PHY registers. If it was already
613 * disabled, cancel the timer that is going to re-enable
614 * it.
615 */
fad09c73
VD		 616 if (!chip->ppu_disabled) {
617 ret = mv88e6xxx_ppu_disable(chip);
85686581 618 if (ret < 0) {
fad09c73 619 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 620 return ret;
621 }
fad09c73 622 chip->ppu_disabled = 1;
2e5f0320 623 } else {
fad09c73 624 del_timer(&chip->ppu_timer);
85686581 625 ret = 0;
2e5f0320
LB		 626 }
627
628 return ret;
629}
630
fad09c73 631static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 632{
3675c8d7 633 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 634 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
635 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 636}
637
fad09c73 638static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 639{
fad09c73
VD		 640 mutex_init(&chip->ppu_mutex);
641 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
642 init_timer(&chip->ppu_timer);
643 chip->ppu_timer.data = (unsigned long)chip;
644 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 645}
646
930188ce
AL		 647static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
648{
649 del_timer_sync(&chip->ppu_timer);
650}
651
e57e5e77
VD		 652static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
653 int reg, u16 *val)
2e5f0320 654{
e57e5e77 655 int err;
2e5f0320 656
e57e5e77
VD		 657 err = mv88e6xxx_ppu_access_get(chip);
658 if (!err) {
659 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 660 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 661 }
662
e57e5e77 663 return err;
2e5f0320
LB		 664}
665
e57e5e77
VD		 666static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
667 int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 693}
694
fad09c73 695static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 696{
fad09c73 697 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 698}
699
fad09c73 700static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 703}
704
fad09c73 705static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 708}
709
fad09c73 710static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 711{
fad09c73 712 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 713}
714
fad09c73 715static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 716{
fad09c73 717 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 718}
719
dea87024
AL		 720/* We expect the switch to perform auto negotiation if there is a real
721 * phy. However, in the case of a fixed link phy, we force the port
722 * settings from the fixed link settings.
723 */
f81ec90f
VD		 724static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
725 struct phy_device *phydev)
dea87024 726{
04bed143 727 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 728 u16 reg;
729 int err;
dea87024
AL		 730
731 if (!phy_is_pseudo_fixed_link(phydev))
732 return;
733
fad09c73 734 mutex_lock(&chip->reg_lock);
dea87024 735
0e7b9925
AL		 736 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
737 if (err)
dea87024
AL		 738 goto out;
739
0e7b9925
AL		 740 reg &= ~(PORT_PCS_CTRL_LINK_UP |
741 PORT_PCS_CTRL_FORCE_LINK |
742 PORT_PCS_CTRL_DUPLEX_FULL |
743 PORT_PCS_CTRL_FORCE_DUPLEX |
744 PORT_PCS_CTRL_UNFORCED);
dea87024
AL		 745
746 reg |= PORT_PCS_CTRL_FORCE_LINK;
747 if (phydev->link)
57d32310 748 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 749
fad09c73 750 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 751 goto out;
752
753 switch (phydev->speed) {
754 case SPEED_1000:
755 reg |= PORT_PCS_CTRL_1000;
756 break;
757 case SPEED_100:
758 reg |= PORT_PCS_CTRL_100;
759 break;
760 case SPEED_10:
761 reg |= PORT_PCS_CTRL_10;
762 break;
763 default:
764 pr_info("Unknown speed");
765 goto out;
766 }
767
768 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
769 if (phydev->duplex == DUPLEX_FULL)
770 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
771
fad09c73 772 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
370b4ffb 773 (port >= mv88e6xxx_num_ports(chip) - 2)) {
e7e72ac0
AL		 774 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
775 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
776 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
777 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
778 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
779 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
780 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
781 }
0e7b9925 782 mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
dea87024
AL		 783
784out:
fad09c73 785 mutex_unlock(&chip->reg_lock);
dea87024
AL		 786}
787
fad09c73 788static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8 789{
a935c052
VD		 790 u16 val;
791 int i, err;
91da11f8
LB		 792
793 for (i = 0; i < 10; i++) {
a935c052
VD		 794 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
795 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 796 return 0;
797 }
798
799 return -ETIMEDOUT;
800}
801
fad09c73 802static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 803{
a935c052 804 int err;
91da11f8 805
fad09c73 806 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 807 port = (port + 1) << 5;
808
3675c8d7 809 /* Snapshot the hardware statistics counters for this port. */
a935c052
VD		 810 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
811 GLOBAL_STATS_OP_CAPTURE_PORT |
812 GLOBAL_STATS_OP_HIST_RX_TX | port);
813 if (err)
814 return err;
91da11f8 815
3675c8d7 816 /* Wait for the snapshotting to complete. */
a935c052 817 return _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 818}
819
fad09c73 820static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 821 int stat, u32 *val)
91da11f8 822{
a935c052
VD		 823 u32 value;
824 u16 reg;
825 int err;
91da11f8
LB		 826
827 *val = 0;
828
a935c052
VD		 829 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
830 GLOBAL_STATS_OP_READ_CAPTURED |
831 GLOBAL_STATS_OP_HIST_RX_TX | stat);
832 if (err)
91da11f8
LB		 833 return;
834
a935c052
VD		 835 err = _mv88e6xxx_stats_wait(chip);
836 if (err)
91da11f8
LB		 837 return;
838
a935c052
VD		 839 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
840 if (err)
91da11f8
LB		 841 return;
842
a935c052 843 value = reg << 16;
91da11f8 844
a935c052
VD		 845 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
846 if (err)
91da11f8
LB		 847 return;
848
a935c052 849 *val = value | reg;
91da11f8
LB		 850}
851
e413e7e1 852static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 853 { "in_good_octets", 8, 0x00, BANK0, },
854 { "in_bad_octets", 4, 0x02, BANK0, },
855 { "in_unicast", 4, 0x04, BANK0, },
856 { "in_broadcasts", 4, 0x06, BANK0, },
857 { "in_multicasts", 4, 0x07, BANK0, },
858 { "in_pause", 4, 0x16, BANK0, },
859 { "in_undersize", 4, 0x18, BANK0, },
860 { "in_fragments", 4, 0x19, BANK0, },
861 { "in_oversize", 4, 0x1a, BANK0, },
862 { "in_jabber", 4, 0x1b, BANK0, },
863 { "in_rx_error", 4, 0x1c, BANK0, },
864 { "in_fcs_error", 4, 0x1d, BANK0, },
865 { "out_octets", 8, 0x0e, BANK0, },
866 { "out_unicast", 4, 0x10, BANK0, },
867 { "out_broadcasts", 4, 0x13, BANK0, },
868 { "out_multicasts", 4, 0x12, BANK0, },
869 { "out_pause", 4, 0x15, BANK0, },
870 { "excessive", 4, 0x11, BANK0, },
871 { "collisions", 4, 0x1e, BANK0, },
872 { "deferred", 4, 0x05, BANK0, },
873 { "single", 4, 0x14, BANK0, },
874 { "multiple", 4, 0x17, BANK0, },
875 { "out_fcs_error", 4, 0x03, BANK0, },
876 { "late", 4, 0x1f, BANK0, },
877 { "hist_64bytes", 4, 0x08, BANK0, },
878 { "hist_65_127bytes", 4, 0x09, BANK0, },
879 { "hist_128_255bytes", 4, 0x0a, BANK0, },
880 { "hist_256_511bytes", 4, 0x0b, BANK0, },
881 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
882 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
883 { "sw_in_discards", 4, 0x10, PORT, },
884 { "sw_in_filtered", 2, 0x12, PORT, },
885 { "sw_out_filtered", 2, 0x13, PORT, },
886 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
887 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
888 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
889 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
890 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
891 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
892 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
893 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
894 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
895 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
896 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
897 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
898 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
899 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
900 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
901 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
902 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
903 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
904 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
905 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
906 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
907 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
908 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
909 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
910 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
911 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 912};
913
fad09c73 914static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 915 struct mv88e6xxx_hw_stat *stat)
e413e7e1 916{
f5e2ed02
AL		 917 switch (stat->type) {
918 case BANK0:
e413e7e1 919 return true;
f5e2ed02 920 case BANK1:
fad09c73 921 return mv88e6xxx_6320_family(chip);
f5e2ed02 922 case PORT:
fad09c73
VD		 923 return mv88e6xxx_6095_family(chip) ||
924 mv88e6xxx_6185_family(chip) ||
925 mv88e6xxx_6097_family(chip) ||
926 mv88e6xxx_6165_family(chip) ||
927 mv88e6xxx_6351_family(chip) ||
928 mv88e6xxx_6352_family(chip);
91da11f8 929 }
f5e2ed02 930 return false;
91da11f8
LB		 931}
932
fad09c73 933static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 934 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 935 int port)
936{
80c4627b
AL		 937 u32 low;
938 u32 high = 0;
0e7b9925
AL		 939 int err;
940 u16 reg;
80c4627b
AL		 941 u64 value;
942
f5e2ed02
AL		 943 switch (s->type) {
944 case PORT:
0e7b9925
AL		 945 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
946 if (err)
80c4627b
AL		 947 return UINT64_MAX;
948
0e7b9925 949 low = reg;
80c4627b 950 if (s->sizeof_stat == 4) {
0e7b9925
AL		 951 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
952 if (err)
80c4627b 953 return UINT64_MAX;
0e7b9925 954 high = reg;
80c4627b 955 }
f5e2ed02
AL		 956 break;
957 case BANK0:
958 case BANK1:
fad09c73 959 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 960 if (s->sizeof_stat == 8)
fad09c73 961 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 962 }
963 value = (((u64)high) << 16) | low;
964 return value;
965}
966
f81ec90f
VD		 967static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
968 uint8_t *data)
91da11f8 969{
04bed143 970 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 971 struct mv88e6xxx_hw_stat *stat;
972 int i, j;
91da11f8 973
f5e2ed02
AL		 974 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
975 stat = &mv88e6xxx_hw_stats[i];
fad09c73 976 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 977 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
978 ETH_GSTRING_LEN);
979 j++;
980 }
91da11f8 981 }
e413e7e1
AL		 982}
983
f81ec90f 984static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 985{
04bed143 986 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 987 struct mv88e6xxx_hw_stat *stat;
988 int i, j;
989
990 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
991 stat = &mv88e6xxx_hw_stats[i];
fad09c73 992 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 993 j++;
994 }
995 return j;
e413e7e1
AL		 996}
997
f81ec90f
VD		 998static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
999 uint64_t *data)
e413e7e1 1000{
04bed143 1001 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 1002 struct mv88e6xxx_hw_stat *stat;
1003 int ret;
1004 int i, j;
1005
fad09c73 1006 mutex_lock(&chip->reg_lock);
f5e2ed02 1007
fad09c73 1008 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1009 if (ret < 0) {
fad09c73 1010 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1011 return;
1012 }
1013 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1014 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 1015 if (mv88e6xxx_has_stat(chip, stat)) {
1016 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 1017 j++;
1018 }
1019 }
1020
fad09c73 1021 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1022}
1023
f81ec90f 1024static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1025{
1026 return 32 * sizeof(u16);
1027}
1028
f81ec90f
VD		 1029static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1030 struct ethtool_regs *regs, void *_p)
a1ab91f3 1031{
04bed143 1032 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1033 int err;
1034 u16 reg;
a1ab91f3
GR		 1035 u16 *p = _p;
1036 int i;
1037
1038 regs->version = 0;
1039
1040 memset(p, 0xff, 32 * sizeof(u16));
1041
fad09c73 1042 mutex_lock(&chip->reg_lock);
23062513 1043
a1ab91f3 1044 for (i = 0; i < 32; i++) {
a1ab91f3 1045
0e7b9925
AL		 1046 err = mv88e6xxx_port_read(chip, port, i, &reg);
1047 if (!err)
1048 p[i] = reg;
a1ab91f3 1049 }
23062513 1050
fad09c73 1051 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1052}
1053
fad09c73 1054static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1055{
a935c052 1056 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1057}
1058
f81ec90f
VD		 1059static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1060 struct ethtool_eee *e)
11b3b45d 1061{
04bed143 1062 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1063 u16 reg;
1064 int err;
11b3b45d 1065
fad09c73 1066 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1067 return -EOPNOTSUPP;
1068
fad09c73 1069 mutex_lock(&chip->reg_lock);
2f40c698 1070
9c93829c
VD		 1071 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1072 if (err)
2f40c698 1073 goto out;
11b3b45d
GR		 1074
1075 e->eee_enabled = !!(reg & 0x0200);
1076 e->tx_lpi_enabled = !!(reg & 0x0100);
1077
0e7b9925 1078 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1079 if (err)
2f40c698 1080 goto out;
11b3b45d 1081
cca8b133 1082 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1083out:
fad09c73 1084 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1085
1086 return err;
11b3b45d
GR		 1087}
1088
f81ec90f
VD		 1089static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1090 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1091{
04bed143 1092 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1093 u16 reg;
1094 int err;
11b3b45d 1095
fad09c73 1096 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1097 return -EOPNOTSUPP;
1098
fad09c73 1099 mutex_lock(&chip->reg_lock);
11b3b45d 1100
9c93829c
VD		 1101 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1102 if (err)
2f40c698
AL		 1103 goto out;
1104
9c93829c 1105 reg &= ~0x0300;
2f40c698
AL		 1106 if (e->eee_enabled)
1107 reg |= 0x0200;
1108 if (e->tx_lpi_enabled)
1109 reg |= 0x0100;
1110
9c93829c 1111 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1112out:
fad09c73 1113 mutex_unlock(&chip->reg_lock);
2f40c698 1114
9c93829c 1115 return err;
11b3b45d
GR		 1116}
1117
fad09c73 1118static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1119{
a935c052
VD		 1120 u16 val;
1121 int err;
facd95b2 1122
6dc10bbc 1123 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1124 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1125 if (err)
1126 return err;
fad09c73 1127 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1128 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1129 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1130 if (err)
1131 return err;
11ea809f 1132
a935c052
VD		 1133 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1134 (val & 0xfff) | ((fid << 8) & 0xf000));
1135 if (err)
1136 return err;
11ea809f
VD		 1137
1138 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1139 cmd |= fid & 0xf;
b426e5f7
VD		 1140 }
1141
a935c052
VD		 1142 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1143 if (err)
1144 return err;
facd95b2 1145
fad09c73 1146 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1147}
1148
fad09c73 1149static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1150 struct mv88e6xxx_atu_entry *entry)
1151{
1152 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1153
1154 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1155 unsigned int mask, shift;
1156
1157 if (entry->trunk) {
1158 data |= GLOBAL_ATU_DATA_TRUNK;
1159 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1160 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1161 } else {
1162 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1163 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1164 }
1165
1166 data |= (entry->portv_trunkid << shift) & mask;
1167 }
1168
a935c052 1169 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1170}
1171
fad09c73 1172static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1173 struct mv88e6xxx_atu_entry *entry,
1174 bool static_too)
facd95b2 1175{
7fb5e755
VD		 1176 int op;
1177 int err;
facd95b2 1178
fad09c73 1179 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1180 if (err)
1181 return err;
facd95b2 1182
fad09c73 1183 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1184 if (err)
1185 return err;
1186
1187 if (entry->fid) {
7fb5e755
VD		 1188 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1189 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1190 } else {
1191 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1192 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1193 }
1194
fad09c73 1195 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1196}
1197
fad09c73 1198static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1199 u16 fid, bool static_too)
7fb5e755
VD		 1200{
1201 struct mv88e6xxx_atu_entry entry = {
1202 .fid = fid,
1203 .state = 0, /* EntryState bits must be 0 */
1204 };
70cc99d1 1205
fad09c73 1206 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1207}
1208
fad09c73 1209static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1210 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1211{
1212 struct mv88e6xxx_atu_entry entry = {
1213 .trunk = false,
1214 .fid = fid,
1215 };
1216
1217 /* EntryState bits must be 0xF */
1218 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1219
1220 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1221 entry.portv_trunkid = (to_port & 0x0f) << 4;
1222 entry.portv_trunkid |= from_port & 0x0f;
1223
fad09c73 1224 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1225}
1226
fad09c73 1227static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1228 int port, bool static_too)
9f4d55d2
VD		 1229{
1230 /* Destination port 0xF means remove the entries */
fad09c73 1231 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1232}
1233
2d9deae4
VD		 1234static const char * const mv88e6xxx_port_state_names[] = {
1235 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1236 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1237 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1238 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1239};
1240
fad09c73 1241static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1242 u8 state)
facd95b2 1243{
fad09c73 1244 struct dsa_switch *ds = chip->ds;
0e7b9925
AL		 1245 u16 reg;
1246 int err;
facd95b2
GR		 1247 u8 oldstate;
1248
0e7b9925
AL		 1249 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
1250 if (err)
1251 return err;
facd95b2 1252
cca8b133 1253 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1254
749efcb8
VD		 1255 reg &= ~PORT_CONTROL_STATE_MASK;
1256 reg |= state;
2d9deae4 1257
749efcb8
VD		 1258 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
1259 if (err)
1260 return err;
2d9deae4 1261
749efcb8
VD		 1262 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1263 mv88e6xxx_port_state_names[state],
1264 mv88e6xxx_port_state_names[oldstate]);
facd95b2 1265
749efcb8 1266 return 0;
facd95b2
GR		 1267}
1268
fad09c73 1269static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1270{
fad09c73 1271 struct net_device *bridge = chip->ports[port].bridge_dev;
370b4ffb 1272 const u16 mask = (1 << mv88e6xxx_num_ports(chip)) - 1;
fad09c73 1273 struct dsa_switch *ds = chip->ds;
b7666efe 1274 u16 output_ports = 0;
0e7b9925
AL		 1275 u16 reg;
1276 int err;
b7666efe
VD		 1277 int i;
1278
1279 /* allow CPU port or DSA link(s) to send frames to every port */
1280 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1281 output_ports = mask;
1282 } else {
370b4ffb 1283 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1284 /* allow sending frames to every group member */
fad09c73 1285 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1286 output_ports |= BIT(i);
1287
1288 /* allow sending frames to CPU port and DSA link(s) */
1289 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1290 output_ports |= BIT(i);
1291 }
1292 }
1293
1294 /* prevent frames from going back out of the port they came in on */
1295 output_ports &= ~BIT(port);
facd95b2 1296
0e7b9925
AL		 1297 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1298 if (err)
1299 return err;
facd95b2 1300
ede8098d
VD		 1301 reg &= ~mask;
1302 reg |= output_ports & mask;
facd95b2 1303
0e7b9925 1304 return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
facd95b2
GR		 1305}
1306
f81ec90f
VD		 1307static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1308 u8 state)
facd95b2 1309{
04bed143 1310 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1311 int stp_state;
553eb544 1312 int err;
facd95b2
GR		 1313
1314 switch (state) {
1315 case BR_STATE_DISABLED:
cca8b133 1316 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1317 break;
1318 case BR_STATE_BLOCKING:
1319 case BR_STATE_LISTENING:
cca8b133 1320 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1321 break;
1322 case BR_STATE_LEARNING:
cca8b133 1323 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1324 break;
1325 case BR_STATE_FORWARDING:
1326 default:
cca8b133 1327 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1328 break;
1329 }
1330
fad09c73
VD		 1331 mutex_lock(&chip->reg_lock);
1332 err = _mv88e6xxx_port_state(chip, port, stp_state);
1333 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1334
1335 if (err)
c8b09808
AL		 1336 netdev_err(ds->ports[port].netdev,
1337 "failed to update state to %s\n",
553eb544 1338 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1339}
1340
749efcb8
VD		 1341static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1342{
1343 struct mv88e6xxx_chip *chip = ds->priv;
1344 int err;
1345
1346 mutex_lock(&chip->reg_lock);
1347 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1348 mutex_unlock(&chip->reg_lock);
1349
1350 if (err)
1351 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1352}
1353
fad09c73 1354static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1355 u16 *new, u16 *old)
76e398a6 1356{
fad09c73 1357 struct dsa_switch *ds = chip->ds;
0e7b9925
AL		 1358 u16 pvid, reg;
1359 int err;
76e398a6 1360
0e7b9925
AL		 1361 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
1362 if (err)
1363 return err;
76e398a6 1364
0e7b9925 1365 pvid = reg & PORT_DEFAULT_VLAN_MASK;
5da96031
VD		 1366
1367 if (new) {
0e7b9925
AL		 1368 reg &= ~PORT_DEFAULT_VLAN_MASK;
1369 reg |= *new & PORT_DEFAULT_VLAN_MASK;
5da96031 1370
0e7b9925
AL		 1371 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
1372 if (err)
1373 return err;
5da96031 1374
c8b09808
AL		 1375 netdev_dbg(ds->ports[port].netdev,
1376 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1377 }
1378
1379 if (old)
1380 *old = pvid;
76e398a6
VD		 1381
1382 return 0;
1383}
1384
fad09c73 1385static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1386 int port, u16 *pvid)
5da96031 1387{
fad09c73 1388 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1389}
1390
fad09c73 1391static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1392 int port, u16 pvid)
0d3b33e6 1393{
fad09c73 1394 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1395}
1396
fad09c73 1397static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1398{
a935c052 1399 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1400}
1401
fad09c73 1402static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1403{
a935c052 1404 int err;
6b17e864 1405
a935c052
VD		 1406 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1407 if (err)
1408 return err;
6b17e864 1409
fad09c73 1410 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1411}
1412
fad09c73 1413static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1414{
1415 int ret;
1416
fad09c73 1417 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1418 if (ret < 0)
1419 return ret;
1420
fad09c73 1421 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1422}
1423
fad09c73 1424static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1425 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1426 unsigned int nibble_offset)
1427{
b8fee957 1428 u16 regs[3];
a935c052 1429 int i, err;
b8fee957
VD		 1430
1431 for (i = 0; i < 3; ++i) {
a935c052 1432 u16 *reg = &regs[i];
b8fee957 1433
a935c052
VD		 1434 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1435 if (err)
1436 return err;
b8fee957
VD		 1437 }
1438
370b4ffb 1439 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1440 unsigned int shift = (i % 4) * 4 + nibble_offset;
1441 u16 reg = regs[i / 4];
1442
1443 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1444 }
1445
1446 return 0;
1447}
1448
fad09c73 1449static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1450 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1451{
fad09c73 1452 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1453}
1454
fad09c73 1455static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1456 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1457{
fad09c73 1458 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1459}
1460
fad09c73 1461static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1462 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1463 unsigned int nibble_offset)
1464{
7dad08d7 1465 u16 regs[3] = { 0 };
a935c052 1466 int i, err;
7dad08d7 1467
370b4ffb 1468 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1469 unsigned int shift = (i % 4) * 4 + nibble_offset;
1470 u8 data = entry->data[i];
1471
1472 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1473 }
1474
1475 for (i = 0; i < 3; ++i) {
a935c052
VD		 1476 u16 reg = regs[i];
1477
1478 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1479 if (err)
1480 return err;
7dad08d7
VD		 1481 }
1482
1483 return 0;
1484}
1485
fad09c73 1486static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1487 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1488{
fad09c73 1489 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1490}
1491
fad09c73 1492static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1493 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1494{
fad09c73 1495 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1496}
1497
fad09c73 1498static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1499{
a935c052
VD		 1500 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1501 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1502}
1503
fad09c73 1504static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1505 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1506{
b4e47c0f 1507 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1508 u16 val;
1509 int err;
b8fee957 1510
a935c052
VD		 1511 err = _mv88e6xxx_vtu_wait(chip);
1512 if (err)
1513 return err;
b8fee957 1514
a935c052
VD		 1515 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1516 if (err)
1517 return err;
b8fee957 1518
a935c052
VD		 1519 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1520 if (err)
1521 return err;
b8fee957 1522
a935c052
VD		 1523 next.vid = val & GLOBAL_VTU_VID_MASK;
1524 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1525
1526 if (next.valid) {
a935c052
VD		 1527 err = mv88e6xxx_vtu_data_read(chip, &next);
1528 if (err)
1529 return err;
b8fee957 1530
6dc10bbc 1531 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1532 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1533 if (err)
1534 return err;
b8fee957 1535
a935c052 1536 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1537 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1538 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1539 * VTU DBNum[3:0] are located in VTU Operation 3:0
1540 */
a935c052
VD		 1541 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1542 if (err)
1543 return err;
11ea809f 1544
a935c052
VD		 1545 next.fid = (val & 0xf00) >> 4;
1546 next.fid |= val & 0xf;
2e7bd5ef 1547 }
b8fee957 1548
fad09c73 1549 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1550 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1551 if (err)
1552 return err;
b8fee957 1553
a935c052 1554 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1555 }
1556 }
1557
1558 *entry = next;
1559 return 0;
1560}
1561
f81ec90f
VD		 1562static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1563 struct switchdev_obj_port_vlan *vlan,
1564 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1565{
04bed143 1566 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1567 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1568 u16 pvid;
1569 int err;
1570
fad09c73 1571 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1572 return -EOPNOTSUPP;
1573
fad09c73 1574 mutex_lock(&chip->reg_lock);
ceff5eff 1575
fad09c73 1576 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1577 if (err)
1578 goto unlock;
1579
fad09c73 1580 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1581 if (err)
1582 goto unlock;
1583
1584 do {
fad09c73 1585 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1586 if (err)
1587 break;
1588
1589 if (!next.valid)
1590 break;
1591
1592 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1593 continue;
1594
1595 /* reinit and dump this VLAN obj */
57d32310
VD		 1596 vlan->vid_begin = next.vid;
1597 vlan->vid_end = next.vid;
ceff5eff
VD		 1598 vlan->flags = 0;
1599
1600 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1601 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1602
1603 if (next.vid == pvid)
1604 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1605
1606 err = cb(&vlan->obj);
1607 if (err)
1608 break;
1609 } while (next.vid < GLOBAL_VTU_VID_MASK);
1610
1611unlock:
fad09c73 1612 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1613
1614 return err;
1615}
1616
fad09c73 1617static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1618 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1619{
11ea809f 1620 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1621 u16 reg = 0;
a935c052 1622 int err;
7dad08d7 1623
a935c052
VD		 1624 err = _mv88e6xxx_vtu_wait(chip);
1625 if (err)
1626 return err;
7dad08d7
VD		 1627
1628 if (!entry->valid)
1629 goto loadpurge;
1630
1631 /* Write port member tags */
a935c052
VD		 1632 err = mv88e6xxx_vtu_data_write(chip, entry);
1633 if (err)
1634 return err;
7dad08d7 1635
fad09c73 1636 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1637 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1638 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1639 if (err)
1640 return err;
b426e5f7 1641 }
7dad08d7 1642
6dc10bbc 1643 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1644 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1645 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1646 if (err)
1647 return err;
fad09c73 1648 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1649 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1650 * VTU DBNum[3:0] are located in VTU Operation 3:0
1651 */
1652 op |= (entry->fid & 0xf0) << 8;
1653 op |= entry->fid & 0xf;
7dad08d7
VD		 1654 }
1655
1656 reg = GLOBAL_VTU_VID_VALID;
1657loadpurge:
1658 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1659 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1660 if (err)
1661 return err;
7dad08d7 1662
fad09c73 1663 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1664}
1665
fad09c73 1666static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1667 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1668{
b4e47c0f 1669 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1670 u16 val;
1671 int err;
0d3b33e6 1672
a935c052
VD		 1673 err = _mv88e6xxx_vtu_wait(chip);
1674 if (err)
1675 return err;
0d3b33e6 1676
a935c052
VD		 1677 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1678 sid & GLOBAL_VTU_SID_MASK);
1679 if (err)
1680 return err;
0d3b33e6 1681
a935c052
VD		 1682 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1683 if (err)
1684 return err;
0d3b33e6 1685
a935c052
VD		 1686 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1687 if (err)
1688 return err;
0d3b33e6 1689
a935c052 1690 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1691
a935c052
VD		 1692 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1693 if (err)
1694 return err;
0d3b33e6 1695
a935c052 1696 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1697
1698 if (next.valid) {
a935c052
VD		 1699 err = mv88e6xxx_stu_data_read(chip, &next);
1700 if (err)
1701 return err;
0d3b33e6
VD		 1702 }
1703
1704 *entry = next;
1705 return 0;
1706}
1707
fad09c73 1708static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1709 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1710{
1711 u16 reg = 0;
a935c052 1712 int err;
0d3b33e6 1713
a935c052
VD		 1714 err = _mv88e6xxx_vtu_wait(chip);
1715 if (err)
1716 return err;
0d3b33e6
VD		 1717
1718 if (!entry->valid)
1719 goto loadpurge;
1720
1721 /* Write port states */
a935c052
VD		 1722 err = mv88e6xxx_stu_data_write(chip, entry);
1723 if (err)
1724 return err;
0d3b33e6
VD		 1725
1726 reg = GLOBAL_VTU_VID_VALID;
1727loadpurge:
a935c052
VD		 1728 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1729 if (err)
1730 return err;
0d3b33e6
VD		 1731
1732 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1733 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1734 if (err)
1735 return err;
0d3b33e6 1736
fad09c73 1737 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1738}
1739
fad09c73 1740static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1741 u16 *new, u16 *old)
2db9ce1f 1742{
fad09c73 1743 struct dsa_switch *ds = chip->ds;
f74df0be 1744 u16 upper_mask;
2db9ce1f 1745 u16 fid;
0e7b9925
AL		 1746 u16 reg;
1747 int err;
2db9ce1f 1748
fad09c73 1749 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1750 upper_mask = 0xff;
fad09c73 1751 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1752 upper_mask = 0xf;
f74df0be
VD		 1753 else
1754 return -EOPNOTSUPP;
1755
2db9ce1f 1756 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
0e7b9925
AL		 1757 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1758 if (err)
1759 return err;
2db9ce1f 1760
0e7b9925 1761 fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
2db9ce1f
VD		 1762
1763 if (new) {
0e7b9925
AL		 1764 reg &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1765 reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
2db9ce1f 1766
0e7b9925
AL		 1767 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1768 if (err)
1769 return err;
2db9ce1f
VD		 1770 }
1771
1772 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
0e7b9925
AL		 1773 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
1774 if (err)
1775 return err;
2db9ce1f 1776
0e7b9925 1777 fid |= (reg & upper_mask) << 4;
2db9ce1f
VD		 1778
1779 if (new) {
0e7b9925
AL		 1780 reg &= ~upper_mask;
1781 reg |= (*new >> 4) & upper_mask;
2db9ce1f 1782
0e7b9925
AL		 1783 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
1784 if (err)
1785 return err;
2db9ce1f 1786
c8b09808
AL		 1787 netdev_dbg(ds->ports[port].netdev,
1788 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1789 }
1790
1791 if (old)
1792 *old = fid;
1793
1794 return 0;
1795}
1796
fad09c73 1797static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1798 int port, u16 *fid)
2db9ce1f 1799{
fad09c73 1800 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1801}
1802
fad09c73 1803static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1804 int port, u16 fid)
2db9ce1f 1805{
fad09c73 1806 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1807}
1808
fad09c73 1809static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1810{
1811 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1812 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1813 int i, err;
3285f9e8
VD		 1814
1815 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1816
2db9ce1f 1817 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1818 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73 1819 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1820 if (err)
1821 return err;
1822
1823 set_bit(*fid, fid_bitmap);
1824 }
1825
3285f9e8 1826 /* Set every FID bit used by the VLAN entries */
fad09c73 1827 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1828 if (err)
1829 return err;
1830
1831 do {
fad09c73 1832 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1833 if (err)
1834 return err;
1835
1836 if (!vlan.valid)
1837 break;
1838
1839 set_bit(vlan.fid, fid_bitmap);
1840 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1841
1842 /* The reset value 0x000 is used to indicate that multiple address
1843 * databases are not needed. Return the next positive available.
1844 */
1845 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1846 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1847 return -ENOSPC;
1848
1849 /* Clear the database */
fad09c73 1850 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1851}
1852
fad09c73 1853static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1854 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1855{
fad09c73 1856 struct dsa_switch *ds = chip->ds;
b4e47c0f 1857 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1858 .valid = true,
1859 .vid = vid,
1860 };
3285f9e8
VD		 1861 int i, err;
1862
fad09c73 1863 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1864 if (err)
1865 return err;
0d3b33e6 1866
3d131f07 1867 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1868 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1869 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1870 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1871 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1872
fad09c73
VD		 1873 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1874 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1875 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1876
1877 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1878 * implemented, only one STU entry is needed to cover all VTU
1879 * entries. Thus, validate the SID 0.
1880 */
1881 vlan.sid = 0;
fad09c73 1882 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1883 if (err)
1884 return err;
1885
1886 if (vstp.sid != vlan.sid || !vstp.valid) {
1887 memset(&vstp, 0, sizeof(vstp));
1888 vstp.valid = true;
1889 vstp.sid = vlan.sid;
1890
fad09c73 1891 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1892 if (err)
1893 return err;
1894 }
0d3b33e6
VD		 1895 }
1896
1897 *entry = vlan;
1898 return 0;
1899}
1900
fad09c73 1901static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1902 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1903{
1904 int err;
1905
1906 if (!vid)
1907 return -EINVAL;
1908
fad09c73 1909 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1910 if (err)
1911 return err;
1912
fad09c73 1913 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1914 if (err)
1915 return err;
1916
1917 if (entry->vid != vid || !entry->valid) {
1918 if (!creat)
1919 return -EOPNOTSUPP;
1920 /* -ENOENT would've been more appropriate, but switchdev expects
1921 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1922 */
1923
fad09c73 1924 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1925 }
1926
1927 return err;
1928}
1929
da9c359e
VD		 1930static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1931 u16 vid_begin, u16 vid_end)
1932{
04bed143 1933 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1934 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1935 int i, err;
1936
1937 if (!vid_begin)
1938 return -EOPNOTSUPP;
1939
fad09c73 1940 mutex_lock(&chip->reg_lock);
da9c359e 1941
fad09c73 1942 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1943 if (err)
1944 goto unlock;
1945
1946 do {
fad09c73 1947 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1948 if (err)
1949 goto unlock;
1950
1951 if (!vlan.valid)
1952 break;
1953
1954 if (vlan.vid > vid_end)
1955 break;
1956
370b4ffb 1957 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1958 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1959 continue;
1960
1961 if (vlan.data[i] ==
1962 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1963 continue;
1964
fad09c73
VD		 1965 if (chip->ports[i].bridge_dev ==
1966 chip->ports[port].bridge_dev)
da9c359e
VD		 1967 break; /* same bridge, check next VLAN */
1968
c8b09808 1969 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1970 "hardware VLAN %d already used by %s\n",
1971 vlan.vid,
fad09c73 1972 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1973 err = -EOPNOTSUPP;
1974 goto unlock;
1975 }
1976 } while (vlan.vid < vid_end);
1977
1978unlock:
fad09c73 1979 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1980
1981 return err;
1982}
1983
214cdb99
VD		 1984static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1985 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1986 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1987 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1988 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1989};
1990
f81ec90f
VD		 1991static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1992 bool vlan_filtering)
214cdb99 1993{
04bed143 1994 struct mv88e6xxx_chip *chip = ds->priv;
214cdb99
VD		 1995 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1996 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925
AL		 1997 u16 reg;
1998 int err;
214cdb99 1999
fad09c73 2000 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2001 return -EOPNOTSUPP;
2002
fad09c73 2003 mutex_lock(&chip->reg_lock);
214cdb99 2004
0e7b9925
AL		 2005 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
2006 if (err)
214cdb99
VD		 2007 goto unlock;
2008
0e7b9925 2009 old = reg & PORT_CONTROL_2_8021Q_MASK;
214cdb99 2010
5220ef1e 2011 if (new != old) {
0e7b9925
AL		 2012 reg &= ~PORT_CONTROL_2_8021Q_MASK;
2013 reg |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 2014
0e7b9925
AL		 2015 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2016 if (err)
5220ef1e
VD		 2017 goto unlock;
2018
c8b09808 2019 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 2020 mv88e6xxx_port_8021q_mode_names[new],
2021 mv88e6xxx_port_8021q_mode_names[old]);
2022 }
214cdb99 2023
0e7b9925 2024 err = 0;
214cdb99 2025unlock:
fad09c73 2026 mutex_unlock(&chip->reg_lock);
214cdb99 2027
0e7b9925 2028 return err;
214cdb99
VD		 2029}
2030
57d32310
VD		 2031static int
2032mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2033 const struct switchdev_obj_port_vlan *vlan,
2034 struct switchdev_trans *trans)
76e398a6 2035{
04bed143 2036 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 2037 int err;
2038
fad09c73 2039 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2040 return -EOPNOTSUPP;
2041
da9c359e
VD		 2042 /* If the requested port doesn't belong to the same bridge as the VLAN
2043 * members, do not support it (yet) and fallback to software VLAN.
2044 */
2045 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2046 vlan->vid_end);
2047 if (err)
2048 return err;
2049
76e398a6
VD		 2050 /* We don't need any dynamic resource from the kernel (yet),
2051 * so skip the prepare phase.
2052 */
2053 return 0;
2054}
2055
fad09c73 2056static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 2057 u16 vid, bool untagged)
0d3b33e6 2058{
b4e47c0f 2059 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 2060 int err;
2061
fad09c73 2062 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 2063 if (err)
76e398a6 2064 return err;
0d3b33e6 2065
0d3b33e6
VD		 2066 vlan.data[port] = untagged ?
2067 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2068 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2069
fad09c73 2070 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2071}
2072
f81ec90f
VD		 2073static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2074 const struct switchdev_obj_port_vlan *vlan,
2075 struct switchdev_trans *trans)
76e398a6 2076{
04bed143 2077 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 2078 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2079 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2080 u16 vid;
76e398a6 2081
fad09c73 2082 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2083 return;
2084
fad09c73 2085 mutex_lock(&chip->reg_lock);
76e398a6 2086
4d5770b3 2087 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 2088 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 2089 netdev_err(ds->ports[port].netdev,
2090 "failed to add VLAN %d%c\n",
4d5770b3 2091 vid, untagged ? 'u' : 't');
76e398a6 2092
fad09c73 2093 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 2094 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 2095 vlan->vid_end);
0d3b33e6 2096
fad09c73 2097 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 2098}
2099
fad09c73 2100static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 2101 int port, u16 vid)
7dad08d7 2102{
fad09c73 2103 struct dsa_switch *ds = chip->ds;
b4e47c0f 2104 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 2105 int i, err;
2106
fad09c73 2107 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 2108 if (err)
76e398a6 2109 return err;
7dad08d7 2110
2fb5ef09
VD		 2111 /* Tell switchdev if this VLAN is handled in software */
2112 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2113 return -EOPNOTSUPP;
7dad08d7
VD		 2114
2115 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2116
2117 /* keep the VLAN unless all ports are excluded */
f02bdffc 2118 vlan.valid = false;
370b4ffb 2119 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 2120 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 2121 continue;
2122
2123 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2124 vlan.valid = true;
7dad08d7
VD		 2125 break;
2126 }
2127 }
2128
fad09c73 2129 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2130 if (err)
2131 return err;
2132
fad09c73 2133 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 2134}
2135
f81ec90f
VD		 2136static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2137 const struct switchdev_obj_port_vlan *vlan)
76e398a6 2138{
04bed143 2139 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 2140 u16 pvid, vid;
2141 int err = 0;
2142
fad09c73 2143 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2144 return -EOPNOTSUPP;
2145
fad09c73 2146 mutex_lock(&chip->reg_lock);
76e398a6 2147
fad09c73 2148 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 2149 if (err)
2150 goto unlock;
2151
76e398a6 2152 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 2153 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 2154 if (err)
2155 goto unlock;
2156
2157 if (vid == pvid) {
fad09c73 2158 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 2159 if (err)
2160 goto unlock;
2161 }
2162 }
2163
7dad08d7 2164unlock:
fad09c73 2165 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2166
2167 return err;
2168}
2169
fad09c73 2170static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2171 const unsigned char *addr)
defb05b9 2172{
a935c052 2173 int i, err;
defb05b9
GR		 2174
2175 for (i = 0; i < 3; i++) {
a935c052
VD		 2176 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2177 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2178 if (err)
2179 return err;
defb05b9
GR		 2180 }
2181
2182 return 0;
2183}
2184
fad09c73 2185static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2186 unsigned char *addr)
defb05b9 2187{
a935c052
VD		 2188 u16 val;
2189 int i, err;
defb05b9
GR		 2190
2191 for (i = 0; i < 3; i++) {
a935c052
VD		 2192 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2193 if (err)
2194 return err;
2195
2196 addr[i * 2] = val >> 8;
2197 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2198 }
2199
2200 return 0;
2201}
2202
fad09c73 2203static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2204 struct mv88e6xxx_atu_entry *entry)
defb05b9 2205{
6630e236
VD		 2206 int ret;
2207
fad09c73 2208 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2209 if (ret < 0)
2210 return ret;
2211
fad09c73 2212 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2213 if (ret < 0)
2214 return ret;
2215
fad09c73 2216 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2217 if (ret < 0)
87820510
VD		 2218 return ret;
2219
fad09c73 2220 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2221}
87820510 2222
88472939
VD		 2223static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2224 struct mv88e6xxx_atu_entry *entry);
2225
2226static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2227 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2228{
2229 struct mv88e6xxx_atu_entry next;
2230 int err;
2231
2232 eth_broadcast_addr(next.mac);
2233
2234 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2235 if (err)
2236 return err;
2237
2238 do {
2239 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2240 if (err)
2241 return err;
2242
2243 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2244 break;
2245
2246 if (ether_addr_equal(next.mac, addr)) {
2247 *entry = next;
2248 return 0;
2249 }
2250 } while (!is_broadcast_ether_addr(next.mac));
2251
2252 memset(entry, 0, sizeof(*entry));
2253 entry->fid = fid;
2254 ether_addr_copy(entry->mac, addr);
2255
2256 return 0;
2257}
2258
83dabd1f
VD		 2259static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2260 const unsigned char *addr, u16 vid,
2261 u8 state)
fd231c82 2262{
b4e47c0f 2263 struct mv88e6xxx_vtu_entry vlan;
88472939 2264 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2265 int err;
2266
2db9ce1f
VD		 2267 /* Null VLAN ID corresponds to the port private database */
2268 if (vid == 0)
fad09c73 2269 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2270 else
fad09c73 2271 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2272 if (err)
2273 return err;
fd231c82 2274
88472939
VD		 2275 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2276 if (err)
2277 return err;
2278
2279 /* Purge the ATU entry only if no port is using it anymore */
2280 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2281 entry.portv_trunkid &= ~BIT(port);
2282 if (!entry.portv_trunkid)
2283 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2284 } else {
2285 entry.portv_trunkid |= BIT(port);
2286 entry.state = state;
fd231c82
VD		 2287 }
2288
fad09c73 2289 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2290}
2291
f81ec90f
VD		 2292static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2293 const struct switchdev_obj_port_fdb *fdb,
2294 struct switchdev_trans *trans)
146a3206
VD		 2295{
2296 /* We don't need any dynamic resource from the kernel (yet),
2297 * so skip the prepare phase.
2298 */
2299 return 0;
2300}
2301
f81ec90f
VD		 2302static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2303 const struct switchdev_obj_port_fdb *fdb,
2304 struct switchdev_trans *trans)
87820510 2305{
04bed143 2306 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2307
fad09c73 2308 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2309 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2310 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2311 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2312 mutex_unlock(&chip->reg_lock);
87820510
VD		 2313}
2314
f81ec90f
VD		 2315static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2316 const struct switchdev_obj_port_fdb *fdb)
87820510 2317{
04bed143 2318 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2319 int err;
87820510 2320
fad09c73 2321 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2322 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2323 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2324 mutex_unlock(&chip->reg_lock);
87820510 2325
83dabd1f 2326 return err;
87820510
VD		 2327}
2328
fad09c73 2329static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2330 struct mv88e6xxx_atu_entry *entry)
6630e236 2331{
1d194046 2332 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2333 u16 val;
2334 int err;
1d194046
VD		 2335
2336 next.fid = fid;
defb05b9 2337
a935c052
VD		 2338 err = _mv88e6xxx_atu_wait(chip);
2339 if (err)
2340 return err;
6630e236 2341
a935c052
VD		 2342 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2343 if (err)
2344 return err;
6630e236 2345
a935c052
VD		 2346 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2347 if (err)
2348 return err;
6630e236 2349
a935c052
VD		 2350 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2351 if (err)
2352 return err;
6630e236 2353
a935c052 2354 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2355 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2356 unsigned int mask, shift;
2357
a935c052 2358 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2359 next.trunk = true;
2360 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2361 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2362 } else {
2363 next.trunk = false;
2364 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2365 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2366 }
2367
a935c052 2368 next.portv_trunkid = (val & mask) >> shift;
1d194046 2369 }
cdf09697 2370
1d194046 2371 *entry = next;
cdf09697
DM		 2372 return 0;
2373}
2374
83dabd1f
VD		 2375static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2376 u16 fid, u16 vid, int port,
2377 struct switchdev_obj *obj,
2378 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2379{
2380 struct mv88e6xxx_atu_entry addr = {
2381 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2382 };
2383 int err;
2384
fad09c73 2385 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2386 if (err)
2387 return err;
2388
2389 do {
fad09c73 2390 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2391 if (err)
83dabd1f 2392 return err;
74b6ba0d
VD		 2393
2394 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2395 break;
2396
83dabd1f
VD		 2397 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2398 continue;
2399
2400 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2401 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2402
83dabd1f
VD		 2403 if (!is_unicast_ether_addr(addr.mac))
2404 continue;
2405
2406 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2407 fdb->vid = vid;
2408 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2409 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2410 fdb->ndm_state = NUD_NOARP;
2411 else
2412 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2413 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2414 struct switchdev_obj_port_mdb *mdb;
2415
2416 if (!is_multicast_ether_addr(addr.mac))
2417 continue;
2418
2419 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2420 mdb->vid = vid;
2421 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2422 } else {
2423 return -EOPNOTSUPP;
74b6ba0d 2424 }
83dabd1f
VD		 2425
2426 err = cb(obj);
2427 if (err)
2428 return err;
74b6ba0d
VD		 2429 } while (!is_broadcast_ether_addr(addr.mac));
2430
2431 return err;
2432}
2433
83dabd1f
VD		 2434static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2435 struct switchdev_obj *obj,
2436 int (*cb)(struct switchdev_obj *obj))
f33475bd 2437{
b4e47c0f 2438 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2439 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2440 };
2db9ce1f 2441 u16 fid;
f33475bd
VD		 2442 int err;
2443
2db9ce1f 2444 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2445 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f 2446 if (err)
83dabd1f 2447 return err;
2db9ce1f 2448
83dabd1f 2449 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2450 if (err)
83dabd1f 2451 return err;
2db9ce1f 2452
74b6ba0d 2453 /* Dump VLANs' Filtering Information Databases */
fad09c73 2454 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2455 if (err)
83dabd1f 2456 return err;
f33475bd
VD		 2457
2458 do {
fad09c73 2459 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2460 if (err)
83dabd1f 2461 return err;
f33475bd
VD		 2462
2463 if (!vlan.valid)
2464 break;
2465
83dabd1f
VD		 2466 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2467 obj, cb);
f33475bd 2468 if (err)
83dabd1f 2469 return err;
f33475bd
VD		 2470 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2471
83dabd1f
VD		 2472 return err;
2473}
2474
2475static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2476 struct switchdev_obj_port_fdb *fdb,
2477 int (*cb)(struct switchdev_obj *obj))
2478{
04bed143 2479 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2480 int err;
2481
2482 mutex_lock(&chip->reg_lock);
2483 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2484 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2485
2486 return err;
2487}
2488
f81ec90f
VD		 2489static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2490 struct net_device *bridge)
e79a8bcb 2491{
04bed143 2492 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2493 int i, err = 0;
466dfa07 2494
fad09c73 2495 mutex_lock(&chip->reg_lock);
466dfa07 2496
b7666efe 2497 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2498 chip->ports[port].bridge_dev = bridge;
b7666efe 2499
370b4ffb 2500 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2501 if (chip->ports[i].bridge_dev == bridge) {
2502 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2503 if (err)
2504 break;
2505 }
2506 }
2507
fad09c73 2508 mutex_unlock(&chip->reg_lock);
a6692754 2509
466dfa07 2510 return err;
e79a8bcb
VD		 2511}
2512
f81ec90f 2513static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2514{
04bed143 2515 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2516 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2517 int i;
466dfa07 2518
fad09c73 2519 mutex_lock(&chip->reg_lock);
466dfa07 2520
b7666efe 2521 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2522 chip->ports[port].bridge_dev = NULL;
b7666efe 2523
370b4ffb 2524 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2525 if (i == port || chip->ports[i].bridge_dev == bridge)
2526 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2527 netdev_warn(ds->ports[i].netdev,
2528 "failed to remap\n");
b7666efe 2529
fad09c73 2530 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2531}
2532
fad09c73 2533static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2534{
fad09c73 2535 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2536 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2537 struct gpio_desc *gpiod = chip->reset;
552238b5 2538 unsigned long timeout;
0e7b9925 2539 u16 reg;
a935c052 2540 int err;
552238b5
VD		 2541 int i;
2542
2543 /* Set all ports to the disabled state. */
370b4ffb 2544 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
0e7b9925
AL		 2545 err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, &reg);
2546 if (err)
2547 return err;
552238b5 2548
0e7b9925
AL		 2549 err = mv88e6xxx_port_write(chip, i, PORT_CONTROL,
2550 reg & 0xfffc);
2551 if (err)
2552 return err;
552238b5
VD		 2553 }
2554
2555 /* Wait for transmit queues to drain. */
2556 usleep_range(2000, 4000);
2557
2558 /* If there is a gpio connected to the reset pin, toggle it */
2559 if (gpiod) {
2560 gpiod_set_value_cansleep(gpiod, 1);
2561 usleep_range(10000, 20000);
2562 gpiod_set_value_cansleep(gpiod, 0);
2563 usleep_range(10000, 20000);
2564 }
2565
2566 /* Reset the switch. Keep the PPU active if requested. The PPU
2567 * needs to be active to support indirect phy register access
2568 * through global registers 0x18 and 0x19.
2569 */
2570 if (ppu_active)
a935c052 2571 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
552238b5 2572 else
a935c052 2573 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
0e7b9925
AL		 2574 if (err)
2575 return err;
552238b5
VD		 2576
2577 /* Wait up to one second for reset to complete. */
2578 timeout = jiffies + 1 * HZ;
2579 while (time_before(jiffies, timeout)) {
a935c052
VD		 2580 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2581 if (err)
2582 return err;
552238b5 2583
a935c052 2584 if ((reg & is_reset) == is_reset)
552238b5
VD		 2585 break;
2586 usleep_range(1000, 2000);
2587 }
2588 if (time_after(jiffies, timeout))
0e7b9925 2589 err = -ETIMEDOUT;
552238b5 2590 else
0e7b9925 2591 err = 0;
552238b5 2592
0e7b9925 2593 return err;
552238b5
VD		 2594}
2595
09cb7dfd 2596static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2597{
09cb7dfd
VD		 2598 u16 val;
2599 int err;
13a7ebb3 2600
09cb7dfd
VD		 2601 /* Clear Power Down bit */
2602 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2603 if (err)
2604 return err;
13a7ebb3 2605
09cb7dfd
VD		 2606 if (val & BMCR_PDOWN) {
2607 val &= ~BMCR_PDOWN;
2608 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2609 }
2610
09cb7dfd 2611 return err;
13a7ebb3
PU		 2612}
2613
fad09c73 2614static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2615{
fad09c73 2616 struct dsa_switch *ds = chip->ds;
0e7b9925 2617 int err;
54d792f2 2618 u16 reg;
d827e88a 2619
fad09c73
VD		 2620 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2621 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2622 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2623 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2624 /* MAC Forcing register: don't force link, speed,
2625 * duplex or flow control state to any particular
2626 * values on physical ports, but force the CPU port
2627 * and all DSA ports to their maximum bandwidth and
2628 * full duplex.
2629 */
0e7b9925 2630 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
60045cbf 2631 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2632 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2633 reg |= PORT_PCS_CTRL_FORCE_LINK |
2634 PORT_PCS_CTRL_LINK_UP |
2635 PORT_PCS_CTRL_DUPLEX_FULL |
2636 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2637 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2638 reg |= PORT_PCS_CTRL_100;
2639 else
2640 reg |= PORT_PCS_CTRL_1000;
2641 } else {
2642 reg |= PORT_PCS_CTRL_UNFORCED;
2643 }
2644
0e7b9925
AL		 2645 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
2646 if (err)
2647 return err;
54d792f2
AL		 2648 }
2649
2650 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2651 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2652 * tunneling, determine priority by looking at 802.1p and IP
2653 * priority fields (IP prio has precedence), and set STP state
2654 * to Forwarding.
2655 *
2656 * If this is the CPU link, use DSA or EDSA tagging depending
2657 * on which tagging mode was configured.
2658 *
2659 * If this is a link to another switch, use DSA tagging mode.
2660 *
2661 * If this is the upstream port for this switch, enable
2662 * forwarding of unknown unicasts and multicasts.
2663 */
2664 reg = 0;
fad09c73
VD		 2665 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2666 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2667 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2668 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2669 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2670 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2671 PORT_CONTROL_STATE_FORWARDING;
2672 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2673 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2674 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2675 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2676 else
2677 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2678 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2679 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2680 }
6083ce71 2681 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2682 if (mv88e6xxx_6095_family(chip) ||
2683 mv88e6xxx_6185_family(chip))
6083ce71 2684 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2685 if (mv88e6xxx_6352_family(chip) ||
2686 mv88e6xxx_6351_family(chip) ||
2687 mv88e6xxx_6165_family(chip) ||
2688 mv88e6xxx_6097_family(chip) ||
2689 mv88e6xxx_6320_family(chip)) {
54d792f2 2690 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2691 }
2692
54d792f2
AL		 2693 if (port == dsa_upstream_port(ds))
2694 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2695 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2696 }
2697 if (reg) {
0e7b9925
AL		 2698 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2699 if (err)
2700 return err;
54d792f2
AL		 2701 }
2702
13a7ebb3
PU		 2703 /* If this port is connected to a SerDes, make sure the SerDes is not
2704 * powered down.
2705 */
09cb7dfd 2706 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2707 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2708 if (err)
2709 return err;
2710 reg &= PORT_STATUS_CMODE_MASK;
2711 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2712 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2713 (reg == PORT_STATUS_CMODE_SGMII)) {
2714 err = mv88e6xxx_serdes_power_on(chip);
2715 if (err < 0)
2716 return err;
13a7ebb3
PU		 2717 }
2718 }
2719
8efdda4a 2720 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2721 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2722 * untagged frames on this port, do a destination address lookup on all
2723 * received packets as usual, disable ARP mirroring and don't send a
2724 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2725 */
2726 reg = 0;
fad09c73
VD		 2727 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2728 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2729 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2730 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2731 reg = PORT_CONTROL_2_MAP_DA;
2732
fad09c73
VD		 2733 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2734 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2735 reg |= PORT_CONTROL_2_JUMBO_10240;
2736
fad09c73 2737 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2738 /* Set the upstream port this port should use */
2739 reg |= dsa_upstream_port(ds);
2740 /* enable forwarding of unknown multicast addresses to
2741 * the upstream port
2742 */
2743 if (port == dsa_upstream_port(ds))
2744 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2745 }
2746
46fbe5e5 2747 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2748
54d792f2 2749 if (reg) {
0e7b9925
AL		 2750 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2751 if (err)
2752 return err;
54d792f2
AL		 2753 }
2754
2755 /* Port Association Vector: when learning source addresses
2756 * of packets, add the address to the address database using
2757 * a port bitmap that has only the bit for this port set and
2758 * the other bits clear.
2759 */
4c7ea3c0 2760 reg = 1 << port;
996ecb82
VD		 2761 /* Disable learning for CPU port */
2762 if (dsa_is_cpu_port(ds, port))
65fa4027 2763 reg = 0;
4c7ea3c0 2764
0e7b9925
AL		 2765 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2766 if (err)
2767 return err;
54d792f2
AL		 2768
2769 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2770 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2771 if (err)
2772 return err;
54d792f2 2773
fad09c73
VD		 2774 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2775 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2776 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2777 /* Do not limit the period of time that this port can
2778 * be paused for by the remote end or the period of
2779 * time that this port can pause the remote end.
2780 */
0e7b9925
AL		 2781 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2782 if (err)
2783 return err;
54d792f2
AL		 2784
2785 /* Port ATU control: disable limiting the number of
2786 * address database entries that this port is allowed
2787 * to use.
2788 */
0e7b9925
AL		 2789 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2790 0x0000);
54d792f2
AL		 2791 /* Priority Override: disable DA, SA and VTU priority
2792 * override.
2793 */
0e7b9925
AL		 2794 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2795 0x0000);
2796 if (err)
2797 return err;
54d792f2
AL		 2798
2799 /* Port Ethertype: use the Ethertype DSA Ethertype
2800 * value.
2801 */
2bbb33be 2802 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
0e7b9925
AL		 2803 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2804 ETH_P_EDSA);
2805 if (err)
2806 return err;
2bbb33be
AL		 2807 }
2808
54d792f2
AL		 2809 /* Tag Remap: use an identity 802.1p prio -> switch
2810 * prio mapping.
2811 */
0e7b9925
AL		 2812 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2813 0x3210);
2814 if (err)
2815 return err;
54d792f2
AL		 2816
2817 /* Tag Remap 2: use an identity 802.1p prio -> switch
2818 * prio mapping.
2819 */
0e7b9925
AL		 2820 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2821 0x7654);
2822 if (err)
2823 return err;
54d792f2
AL		 2824 }
2825
1bc261fa 2826 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2827 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2828 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2829 mv88e6xxx_6320_family(chip)) {
0e7b9925
AL		 2830 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2831 0x0001);
2832 if (err)
2833 return err;
1bc261fa 2834 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
0e7b9925
AL		 2835 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2836 0x0000);
2837 if (err)
2838 return err;
54d792f2
AL		 2839 }
2840
366f0a0f
GR		 2841 /* Port Control 1: disable trunking, disable sending
2842 * learning messages to this port.
d827e88a 2843 */
0e7b9925
AL		 2844 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2845 if (err)
2846 return err;
d827e88a 2847
207afda1 2848 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2849 * database, and allow bidirectional communication between the
2850 * CPU and DSA port(s), and the other ports.
d827e88a 2851 */
0e7b9925
AL		 2852 err = _mv88e6xxx_port_fid_set(chip, port, 0);
2853 if (err)
2854 return err;
2db9ce1f 2855
0e7b9925
AL		 2856 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2857 if (err)
2858 return err;
d827e88a
GR		 2859
2860 /* Default VLAN ID and priority: don't set a default VLAN
2861 * ID, and set the default packet priority to zero.
2862 */
0e7b9925 2863 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2864}
2865
aa0938c6 2866static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2867{
2868 int err;
2869
a935c052 2870 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2871 if (err)
2872 return err;
2873
a935c052 2874 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2875 if (err)
2876 return err;
2877
a935c052
VD		 2878 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2879 if (err)
2880 return err;
2881
2882 return 0;
3b4caa1b
VD		 2883}
2884
acddbd21
VD		 2885static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2886 unsigned int msecs)
2887{
2888 const unsigned int coeff = chip->info->age_time_coeff;
2889 const unsigned int min = 0x01 * coeff;
2890 const unsigned int max = 0xff * coeff;
2891 u8 age_time;
2892 u16 val;
2893 int err;
2894
2895 if (msecs < min || msecs > max)
2896 return -ERANGE;
2897
2898 /* Round to nearest multiple of coeff */
2899 age_time = (msecs + coeff / 2) / coeff;
2900
a935c052 2901 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2902 if (err)
2903 return err;
2904
2905 /* AgeTime is 11:4 bits */
2906 val &= ~0xff0;
2907 val |= age_time << 4;
2908
a935c052 2909 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2910}
2911
2cfcd964
VD		 2912static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2913 unsigned int ageing_time)
2914{
04bed143 2915 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2916 int err;
2917
2918 mutex_lock(&chip->reg_lock);
2919 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2920 mutex_unlock(&chip->reg_lock);
2921
2922 return err;
2923}
2924
9729934c 2925static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2926{
fad09c73 2927 struct dsa_switch *ds = chip->ds;
b0745e87 2928 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2929 u16 reg;
552238b5 2930 int err;
54d792f2 2931
119477bd
VD		 2932 /* Enable the PHY Polling Unit if present, don't discard any packets,
2933 * and mask all interrupt sources.
2934 */
dc30c35b
AL		 2935 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2936 if (err < 0)
2937 return err;
2938
2939 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
fad09c73
VD		 2940 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2941 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2942 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2943
a935c052 2944 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
119477bd
VD		 2945 if (err)
2946 return err;
2947
b0745e87
VD		 2948 /* Configure the upstream port, and configure it as the port to which
2949 * ingress and egress and ARP monitor frames are to be sent.
2950 */
2951 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2952 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2953 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
a935c052 2954 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
b0745e87
VD		 2955 if (err)
2956 return err;
2957
50484ff4 2958 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2959 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2960 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2961 (ds->index & 0x1f));
50484ff4
VD		 2962 if (err)
2963 return err;
2964
acddbd21
VD		 2965 /* Clear all the VTU and STU entries */
2966 err = _mv88e6xxx_vtu_stu_flush(chip);
2967 if (err < 0)
2968 return err;
2969
54d792f2
AL		 2970 /* Set the default address aging time to 5 minutes, and
2971 * enable address learn messages to be sent to all message
2972 * ports.
2973 */
a935c052
VD		 2974 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2975 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2976 if (err)
08a01261 2977 return err;
54d792f2 2978
acddbd21
VD		 2979 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2980 if (err)
9729934c
VD		 2981 return err;
2982
2983 /* Clear all ATU entries */
2984 err = _mv88e6xxx_atu_flush(chip, 0, true);
2985 if (err)
2986 return err;
2987
54d792f2 2988 /* Configure the IP ToS mapping registers. */
a935c052 2989 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2990 if (err)
08a01261 2991 return err;
a935c052 2992 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2993 if (err)
08a01261 2994 return err;
a935c052 2995 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2996 if (err)
08a01261 2997 return err;
a935c052 2998 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2999 if (err)
08a01261 3000 return err;
a935c052 3001 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 3002 if (err)
08a01261 3003 return err;
a935c052 3004 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 3005 if (err)
08a01261 3006 return err;
a935c052 3007 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 3008 if (err)
08a01261 3009 return err;
a935c052 3010 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 3011 if (err)
08a01261 3012 return err;
54d792f2
AL		 3013
3014 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 3015 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 3016 if (err)
08a01261 3017 return err;
54d792f2 3018
9729934c 3019 /* Clear the statistics counters for all ports */
a935c052
VD		 3020 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
3021 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 3022 if (err)
3023 return err;
3024
3025 /* Wait for the flush to complete. */
3026 err = _mv88e6xxx_stats_wait(chip);
3027 if (err)
3028 return err;
3029
3030 return 0;
3031}
3032
f81ec90f 3033static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3034{
04bed143 3035 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 3036 int err;
a1a6a4d1
VD		 3037 int i;
3038
fad09c73
VD		 3039 chip->ds = ds;
3040 ds->slave_mii_bus = chip->mdio_bus;
08a01261 3041
fad09c73 3042 mutex_lock(&chip->reg_lock);
08a01261 3043
9729934c 3044 /* Setup Switch Port Registers */
370b4ffb 3045 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 3046 err = mv88e6xxx_setup_port(chip, i);
3047 if (err)
3048 goto unlock;
3049 }
3050
3051 /* Setup Switch Global 1 Registers */
3052 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 3053 if (err)
3054 goto unlock;
3055
9729934c
VD		 3056 /* Setup Switch Global 2 Registers */
3057 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3058 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 3059 if (err)
3060 goto unlock;
3061 }
08a01261 3062
6b17e864 3063unlock:
fad09c73 3064 mutex_unlock(&chip->reg_lock);
db687a56 3065
48ace4ef 3066 return err;
54d792f2
AL		 3067}
3068
3b4caa1b
VD		 3069static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3070{
04bed143 3071 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 3072 int err;
3073
b073d4e2
VD		 3074 if (!chip->info->ops->set_switch_mac)
3075 return -EOPNOTSUPP;
3b4caa1b 3076
b073d4e2
VD		 3077 mutex_lock(&chip->reg_lock);
3078 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 3079 mutex_unlock(&chip->reg_lock);
3080
3081 return err;
3082}
3083
e57e5e77 3084static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 3085{
fad09c73 3086 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 3087 u16 val;
3088 int err;
fd3a0ee4 3089
370b4ffb 3090 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 3091 return 0xffff;
fd3a0ee4 3092
fad09c73 3093 mutex_lock(&chip->reg_lock);
e57e5e77 3094 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 3095 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 3096
3097 return err ? err : val;
fd3a0ee4
AL		 3098}
3099
e57e5e77 3100static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 3101{
fad09c73 3102 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 3103 int err;
fd3a0ee4 3104
370b4ffb 3105 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 3106 return 0xffff;
fd3a0ee4 3107
fad09c73 3108 mutex_lock(&chip->reg_lock);
e57e5e77 3109 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 3110 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 3111
3112 return err;
fd3a0ee4
AL		 3113}
3114
fad09c73 3115static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 3116 struct device_node *np)
3117{
3118 static int index;
3119 struct mii_bus *bus;
3120 int err;
3121
b516d453 3122 if (np)
fad09c73 3123 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 3124
fad09c73 3125 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 3126 if (!bus)
3127 return -ENOMEM;
3128
fad09c73 3129 bus->priv = (void *)chip;
b516d453
AL		 3130 if (np) {
3131 bus->name = np->full_name;
3132 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3133 } else {
3134 bus->name = "mv88e6xxx SMI";
3135 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3136 }
3137
3138 bus->read = mv88e6xxx_mdio_read;
3139 bus->write = mv88e6xxx_mdio_write;
fad09c73 3140 bus->parent = chip->dev;
b516d453 3141
fad09c73
VD		 3142 if (chip->mdio_np)
3143 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 3144 else
3145 err = mdiobus_register(bus);
3146 if (err) {
fad09c73 3147 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3148 goto out;
3149 }
fad09c73 3150 chip->mdio_bus = bus;
b516d453
AL		 3151
3152 return 0;
3153
3154out:
fad09c73
VD		 3155 if (chip->mdio_np)
3156 of_node_put(chip->mdio_np);
b516d453
AL		 3157
3158 return err;
3159}
3160
fad09c73 3161static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3162
3163{
fad09c73 3164 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3165
3166 mdiobus_unregister(bus);
3167
fad09c73
VD		 3168 if (chip->mdio_np)
3169 of_node_put(chip->mdio_np);
b516d453
AL		 3170}
3171
c22995c5
GR		 3172#ifdef CONFIG_NET_DSA_HWMON
3173
3174static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3175{
04bed143 3176 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 3177 u16 val;
c22995c5 3178 int ret;
c22995c5
GR		 3179
3180 *temp = 0;
3181
fad09c73 3182 mutex_lock(&chip->reg_lock);
c22995c5 3183
9c93829c 3184 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3185 if (ret < 0)
3186 goto error;
3187
3188 /* Enable temperature sensor */
9c93829c 3189 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3190 if (ret < 0)
3191 goto error;
3192
9c93829c 3193 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3194 if (ret < 0)
3195 goto error;
3196
3197 /* Wait for temperature to stabilize */
3198 usleep_range(10000, 12000);
3199
9c93829c
VD		 3200 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3201 if (ret < 0)
c22995c5 3202 goto error;
c22995c5
GR		 3203
3204 /* Disable temperature sensor */
9c93829c 3205 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3206 if (ret < 0)
3207 goto error;
3208
3209 *temp = ((val & 0x1f) - 5) * 5;
3210
3211error:
9c93829c 3212 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3213 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3214 return ret;
3215}
3216
3217static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3218{
04bed143 3219 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3220 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3221 u16 val;
c22995c5
GR		 3222 int ret;
3223
3224 *temp = 0;
3225
9c93829c
VD		 3226 mutex_lock(&chip->reg_lock);
3227 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3228 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3229 if (ret < 0)
3230 return ret;
3231
9c93829c 3232 *temp = (val & 0xff) - 25;
c22995c5
GR		 3233
3234 return 0;
3235}
3236
f81ec90f 3237static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3238{
04bed143 3239 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3240
fad09c73 3241 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3242 return -EOPNOTSUPP;
3243
fad09c73 3244 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3245 return mv88e63xx_get_temp(ds, temp);
3246
3247 return mv88e61xx_get_temp(ds, temp);
3248}
3249
f81ec90f 3250static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3251{
04bed143 3252 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3253 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3254 u16 val;
c22995c5
GR		 3255 int ret;
3256
fad09c73 3257 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3258 return -EOPNOTSUPP;
3259
3260 *temp = 0;
3261
9c93829c
VD		 3262 mutex_lock(&chip->reg_lock);
3263 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3264 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3265 if (ret < 0)
3266 return ret;
3267
9c93829c 3268 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3269
3270 return 0;
3271}
3272
f81ec90f 3273static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3274{
04bed143 3275 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3276 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3277 u16 val;
3278 int err;
c22995c5 3279
fad09c73 3280 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3281 return -EOPNOTSUPP;
3282
9c93829c
VD		 3283 mutex_lock(&chip->reg_lock);
3284 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3285 if (err)
3286 goto unlock;
c22995c5 3287 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3288 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3289 (val & 0xe0ff) | (temp << 8));
3290unlock:
3291 mutex_unlock(&chip->reg_lock);
3292
3293 return err;
c22995c5
GR		 3294}
3295
f81ec90f 3296static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3297{
04bed143 3298 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3299 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3300 u16 val;
c22995c5
GR		 3301 int ret;
3302
fad09c73 3303 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3304 return -EOPNOTSUPP;
3305
3306 *alarm = false;
3307
9c93829c
VD		 3308 mutex_lock(&chip->reg_lock);
3309 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3310 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3311 if (ret < 0)
3312 return ret;
3313
9c93829c 3314 *alarm = !!(val & 0x40);
c22995c5
GR		 3315
3316 return 0;
3317}
3318#endif /* CONFIG_NET_DSA_HWMON */
3319
855b1932
VD		 3320static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3321{
04bed143 3322 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3323
3324 return chip->eeprom_len;
3325}
3326
855b1932
VD		 3327static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3328 struct ethtool_eeprom *eeprom, u8 *data)
3329{
04bed143 3330 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3331 int err;
3332
ee4dc2e7
VD		 3333 if (!chip->info->ops->get_eeprom)
3334 return -EOPNOTSUPP;
855b1932 3335
ee4dc2e7
VD		 3336 mutex_lock(&chip->reg_lock);
3337 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3338 mutex_unlock(&chip->reg_lock);
3339
3340 if (err)
3341 return err;
3342
3343 eeprom->magic = 0xc3ec4951;
3344
3345 return 0;
3346}
3347
855b1932
VD		 3348static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3349 struct ethtool_eeprom *eeprom, u8 *data)
3350{
04bed143 3351 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3352 int err;
3353
ee4dc2e7
VD		 3354 if (!chip->info->ops->set_eeprom)
3355 return -EOPNOTSUPP;
3356
855b1932
VD		 3357 if (eeprom->magic != 0xc3ec4951)
3358 return -EINVAL;
3359
3360 mutex_lock(&chip->reg_lock);
ee4dc2e7 3361 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3362 mutex_unlock(&chip->reg_lock);
3363
3364 return err;
3365}
3366
b3469dd8 3367static const struct mv88e6xxx_ops mv88e6085_ops = {
b073d4e2 3368 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3369 .phy_read = mv88e6xxx_phy_ppu_read,
3370 .phy_write = mv88e6xxx_phy_ppu_write,
3371};
3372
3373static const struct mv88e6xxx_ops mv88e6095_ops = {
b073d4e2 3374 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3375 .phy_read = mv88e6xxx_phy_ppu_read,
3376 .phy_write = mv88e6xxx_phy_ppu_write,
3377};
3378
3379static const struct mv88e6xxx_ops mv88e6123_ops = {
b073d4e2 3380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3381 .phy_read = mv88e6xxx_read,
3382 .phy_write = mv88e6xxx_write,
3383};
3384
3385static const struct mv88e6xxx_ops mv88e6131_ops = {
b073d4e2 3386 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3387 .phy_read = mv88e6xxx_phy_ppu_read,
3388 .phy_write = mv88e6xxx_phy_ppu_write,
3389};
3390
3391static const struct mv88e6xxx_ops mv88e6161_ops = {
b073d4e2 3392 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3393 .phy_read = mv88e6xxx_read,
3394 .phy_write = mv88e6xxx_write,
3395};
3396
3397static const struct mv88e6xxx_ops mv88e6165_ops = {
b073d4e2 3398 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3399 .phy_read = mv88e6xxx_read,
3400 .phy_write = mv88e6xxx_write,
3401};
3402
3403static const struct mv88e6xxx_ops mv88e6171_ops = {
b073d4e2 3404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3405 .phy_read = mv88e6xxx_g2_smi_phy_read,
3406 .phy_write = mv88e6xxx_g2_smi_phy_write,
3407};
3408
3409static const struct mv88e6xxx_ops mv88e6172_ops = {
ee4dc2e7
VD		 3410 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3411 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3412 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3413 .phy_read = mv88e6xxx_g2_smi_phy_read,
3414 .phy_write = mv88e6xxx_g2_smi_phy_write,
3415};
3416
3417static const struct mv88e6xxx_ops mv88e6175_ops = {
b073d4e2 3418 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3419 .phy_read = mv88e6xxx_g2_smi_phy_read,
3420 .phy_write = mv88e6xxx_g2_smi_phy_write,
3421};
3422
3423static const struct mv88e6xxx_ops mv88e6176_ops = {
ee4dc2e7
VD		 3424 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3425 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3426 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3427 .phy_read = mv88e6xxx_g2_smi_phy_read,
3428 .phy_write = mv88e6xxx_g2_smi_phy_write,
3429};
3430
3431static const struct mv88e6xxx_ops mv88e6185_ops = {
b073d4e2 3432 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3433 .phy_read = mv88e6xxx_phy_ppu_read,
3434 .phy_write = mv88e6xxx_phy_ppu_write,
3435};
3436
3437static const struct mv88e6xxx_ops mv88e6240_ops = {
ee4dc2e7
VD		 3438 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3439 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3440 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3441 .phy_read = mv88e6xxx_g2_smi_phy_read,
3442 .phy_write = mv88e6xxx_g2_smi_phy_write,
3443};
3444
3445static const struct mv88e6xxx_ops mv88e6320_ops = {
ee4dc2e7
VD		 3446 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3447 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3448 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3449 .phy_read = mv88e6xxx_g2_smi_phy_read,
3450 .phy_write = mv88e6xxx_g2_smi_phy_write,
3451};
3452
3453static const struct mv88e6xxx_ops mv88e6321_ops = {
ee4dc2e7
VD		 3454 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3455 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3456 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3457 .phy_read = mv88e6xxx_g2_smi_phy_read,
3458 .phy_write = mv88e6xxx_g2_smi_phy_write,
3459};
3460
3461static const struct mv88e6xxx_ops mv88e6350_ops = {
b073d4e2 3462 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3463 .phy_read = mv88e6xxx_g2_smi_phy_read,
3464 .phy_write = mv88e6xxx_g2_smi_phy_write,
3465};
3466
3467static const struct mv88e6xxx_ops mv88e6351_ops = {
b073d4e2 3468 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3469 .phy_read = mv88e6xxx_g2_smi_phy_read,
3470 .phy_write = mv88e6xxx_g2_smi_phy_write,
3471};
3472
3473static const struct mv88e6xxx_ops mv88e6352_ops = {
ee4dc2e7
VD		 3474 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3475 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3476 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3477 .phy_read = mv88e6xxx_g2_smi_phy_read,
3478 .phy_write = mv88e6xxx_g2_smi_phy_write,
3479};
3480
f81ec90f
VD		 3481static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3482 [MV88E6085] = {
3483 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3484 .family = MV88E6XXX_FAMILY_6097,
3485 .name = "Marvell 88E6085",
3486 .num_databases = 4096,
3487 .num_ports = 10,
9dddd478 3488 .port_base_addr = 0x10,
a935c052 3489 .global1_addr = 0x1b,
acddbd21 3490 .age_time_coeff = 15000,
dc30c35b 3491 .g1_irqs = 8,
f81ec90f 3492 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3493 .ops = &mv88e6085_ops,
f81ec90f
VD		 3494 },
3495
3496 [MV88E6095] = {
3497 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3498 .family = MV88E6XXX_FAMILY_6095,
3499 .name = "Marvell 88E6095/88E6095F",
3500 .num_databases = 256,
3501 .num_ports = 11,
9dddd478 3502 .port_base_addr = 0x10,
a935c052 3503 .global1_addr = 0x1b,
acddbd21 3504 .age_time_coeff = 15000,
dc30c35b 3505 .g1_irqs = 8,
f81ec90f 3506 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3507 .ops = &mv88e6095_ops,
f81ec90f
VD		 3508 },
3509
3510 [MV88E6123] = {
3511 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3512 .family = MV88E6XXX_FAMILY_6165,
3513 .name = "Marvell 88E6123",
3514 .num_databases = 4096,
3515 .num_ports = 3,
9dddd478 3516 .port_base_addr = 0x10,
a935c052 3517 .global1_addr = 0x1b,
acddbd21 3518 .age_time_coeff = 15000,
dc30c35b 3519 .g1_irqs = 9,
f81ec90f 3520 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3521 .ops = &mv88e6123_ops,
f81ec90f
VD		 3522 },
3523
3524 [MV88E6131] = {
3525 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3526 .family = MV88E6XXX_FAMILY_6185,
3527 .name = "Marvell 88E6131",
3528 .num_databases = 256,
3529 .num_ports = 8,
9dddd478 3530 .port_base_addr = 0x10,
a935c052 3531 .global1_addr = 0x1b,
acddbd21 3532 .age_time_coeff = 15000,
dc30c35b 3533 .g1_irqs = 9,
f81ec90f 3534 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3535 .ops = &mv88e6131_ops,
f81ec90f
VD		 3536 },
3537
3538 [MV88E6161] = {
3539 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3540 .family = MV88E6XXX_FAMILY_6165,
3541 .name = "Marvell 88E6161",
3542 .num_databases = 4096,
3543 .num_ports = 6,
9dddd478 3544 .port_base_addr = 0x10,
a935c052 3545 .global1_addr = 0x1b,
acddbd21 3546 .age_time_coeff = 15000,
dc30c35b 3547 .g1_irqs = 9,
f81ec90f 3548 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3549 .ops = &mv88e6161_ops,
f81ec90f
VD		 3550 },
3551
3552 [MV88E6165] = {
3553 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3554 .family = MV88E6XXX_FAMILY_6165,
3555 .name = "Marvell 88E6165",
3556 .num_databases = 4096,
3557 .num_ports = 6,
9dddd478 3558 .port_base_addr = 0x10,
a935c052 3559 .global1_addr = 0x1b,
acddbd21 3560 .age_time_coeff = 15000,
dc30c35b 3561 .g1_irqs = 9,
f81ec90f 3562 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3563 .ops = &mv88e6165_ops,
f81ec90f
VD		 3564 },
3565
3566 [MV88E6171] = {
3567 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3568 .family = MV88E6XXX_FAMILY_6351,
3569 .name = "Marvell 88E6171",
3570 .num_databases = 4096,
3571 .num_ports = 7,
9dddd478 3572 .port_base_addr = 0x10,
a935c052 3573 .global1_addr = 0x1b,
acddbd21 3574 .age_time_coeff = 15000,
dc30c35b 3575 .g1_irqs = 9,
f81ec90f 3576 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3577 .ops = &mv88e6171_ops,
f81ec90f
VD		 3578 },
3579
3580 [MV88E6172] = {
3581 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3582 .family = MV88E6XXX_FAMILY_6352,
3583 .name = "Marvell 88E6172",
3584 .num_databases = 4096,
3585 .num_ports = 7,
9dddd478 3586 .port_base_addr = 0x10,
a935c052 3587 .global1_addr = 0x1b,
acddbd21 3588 .age_time_coeff = 15000,
dc30c35b 3589 .g1_irqs = 9,
f81ec90f 3590 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3591 .ops = &mv88e6172_ops,
f81ec90f
VD		 3592 },
3593
3594 [MV88E6175] = {
3595 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3596 .family = MV88E6XXX_FAMILY_6351,
3597 .name = "Marvell 88E6175",
3598 .num_databases = 4096,
3599 .num_ports = 7,
9dddd478 3600 .port_base_addr = 0x10,
a935c052 3601 .global1_addr = 0x1b,
acddbd21 3602 .age_time_coeff = 15000,
dc30c35b 3603 .g1_irqs = 9,
f81ec90f 3604 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3605 .ops = &mv88e6175_ops,
f81ec90f
VD		 3606 },
3607
3608 [MV88E6176] = {
3609 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3610 .family = MV88E6XXX_FAMILY_6352,
3611 .name = "Marvell 88E6176",
3612 .num_databases = 4096,
3613 .num_ports = 7,
9dddd478 3614 .port_base_addr = 0x10,
a935c052 3615 .global1_addr = 0x1b,
acddbd21 3616 .age_time_coeff = 15000,
dc30c35b 3617 .g1_irqs = 9,
f81ec90f 3618 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3619 .ops = &mv88e6176_ops,
f81ec90f
VD		 3620 },
3621
3622 [MV88E6185] = {
3623 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3624 .family = MV88E6XXX_FAMILY_6185,
3625 .name = "Marvell 88E6185",
3626 .num_databases = 256,
3627 .num_ports = 10,
9dddd478 3628 .port_base_addr = 0x10,
a935c052 3629 .global1_addr = 0x1b,
acddbd21 3630 .age_time_coeff = 15000,
dc30c35b 3631 .g1_irqs = 8,
f81ec90f 3632 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3633 .ops = &mv88e6185_ops,
f81ec90f
VD		 3634 },
3635
3636 [MV88E6240] = {
3637 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3638 .family = MV88E6XXX_FAMILY_6352,
3639 .name = "Marvell 88E6240",
3640 .num_databases = 4096,
3641 .num_ports = 7,
9dddd478 3642 .port_base_addr = 0x10,
a935c052 3643 .global1_addr = 0x1b,
acddbd21 3644 .age_time_coeff = 15000,
dc30c35b 3645 .g1_irqs = 9,
f81ec90f 3646 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3647 .ops = &mv88e6240_ops,
f81ec90f
VD		 3648 },
3649
3650 [MV88E6320] = {
3651 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3652 .family = MV88E6XXX_FAMILY_6320,
3653 .name = "Marvell 88E6320",
3654 .num_databases = 4096,
3655 .num_ports = 7,
9dddd478 3656 .port_base_addr = 0x10,
a935c052 3657 .global1_addr = 0x1b,
acddbd21 3658 .age_time_coeff = 15000,
dc30c35b 3659 .g1_irqs = 8,
f81ec90f 3660 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3661 .ops = &mv88e6320_ops,
f81ec90f
VD		 3662 },
3663
3664 [MV88E6321] = {
3665 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3666 .family = MV88E6XXX_FAMILY_6320,
3667 .name = "Marvell 88E6321",
3668 .num_databases = 4096,
3669 .num_ports = 7,
9dddd478 3670 .port_base_addr = 0x10,
a935c052 3671 .global1_addr = 0x1b,
acddbd21 3672 .age_time_coeff = 15000,
dc30c35b 3673 .g1_irqs = 8,
f81ec90f 3674 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3675 .ops = &mv88e6321_ops,
f81ec90f
VD		 3676 },
3677
3678 [MV88E6350] = {
3679 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3680 .family = MV88E6XXX_FAMILY_6351,
3681 .name = "Marvell 88E6350",
3682 .num_databases = 4096,
3683 .num_ports = 7,
9dddd478 3684 .port_base_addr = 0x10,
a935c052 3685 .global1_addr = 0x1b,
acddbd21 3686 .age_time_coeff = 15000,
dc30c35b 3687 .g1_irqs = 9,
f81ec90f 3688 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3689 .ops = &mv88e6350_ops,
f81ec90f
VD		 3690 },
3691
3692 [MV88E6351] = {
3693 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3694 .family = MV88E6XXX_FAMILY_6351,
3695 .name = "Marvell 88E6351",
3696 .num_databases = 4096,
3697 .num_ports = 7,
9dddd478 3698 .port_base_addr = 0x10,
a935c052 3699 .global1_addr = 0x1b,
acddbd21 3700 .age_time_coeff = 15000,
dc30c35b 3701 .g1_irqs = 9,
f81ec90f 3702 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3703 .ops = &mv88e6351_ops,
f81ec90f
VD		 3704 },
3705
3706 [MV88E6352] = {
3707 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3708 .family = MV88E6XXX_FAMILY_6352,
3709 .name = "Marvell 88E6352",
3710 .num_databases = 4096,
3711 .num_ports = 7,
9dddd478 3712 .port_base_addr = 0x10,
a935c052 3713 .global1_addr = 0x1b,
acddbd21 3714 .age_time_coeff = 15000,
dc30c35b 3715 .g1_irqs = 9,
f81ec90f 3716 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3717 .ops = &mv88e6352_ops,
f81ec90f
VD		 3718 },
3719};
3720
5f7c0367 3721static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3722{
a439c061 3723 int i;
b9b37713 3724
5f7c0367
VD		 3725 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3726 if (mv88e6xxx_table[i].prod_num == prod_num)
3727 return &mv88e6xxx_table[i];
b9b37713 3728
b9b37713
VD		 3729 return NULL;
3730}
3731
fad09c73 3732static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3733{
3734 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3735 unsigned int prod_num, rev;
3736 u16 id;
3737 int err;
bc46a3d5 3738
8f6345b2
VD		 3739 mutex_lock(&chip->reg_lock);
3740 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3741 mutex_unlock(&chip->reg_lock);
3742 if (err)
3743 return err;
bc46a3d5
VD		 3744
3745 prod_num = (id & 0xfff0) >> 4;
3746 rev = id & 0x000f;
3747
3748 info = mv88e6xxx_lookup_info(prod_num);
3749 if (!info)
3750 return -ENODEV;
3751
caac8545 3752 /* Update the compatible info with the probed one */
fad09c73 3753 chip->info = info;
bc46a3d5 3754
ca070c10
VD		 3755 err = mv88e6xxx_g2_require(chip);
3756 if (err)
3757 return err;
3758
fad09c73
VD		 3759 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3760 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3761
3762 return 0;
3763}
3764
fad09c73 3765static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3766{
fad09c73 3767 struct mv88e6xxx_chip *chip;
469d729f 3768
fad09c73
VD		 3769 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3770 if (!chip)
469d729f
VD		 3771 return NULL;
3772
fad09c73 3773 chip->dev = dev;
469d729f 3774
fad09c73 3775 mutex_init(&chip->reg_lock);
469d729f 3776
fad09c73 3777 return chip;
469d729f
VD		 3778}
3779
e57e5e77
VD		 3780static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3781{
b3469dd8 3782 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
e57e5e77 3783 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 3784}
3785
930188ce
AL		 3786static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3787{
b3469dd8 3788 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
930188ce 3789 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 3790}
3791
fad09c73 3792static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3793 struct mii_bus *bus, int sw_addr)
3794{
3795 /* ADDR[0] pin is unavailable externally and considered zero */
3796 if (sw_addr & 0x1)
3797 return -EINVAL;
3798
914b32f6 3799 if (sw_addr == 0)
fad09c73 3800 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3801 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3802 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3803 else
3804 return -EINVAL;
3805
fad09c73
VD		 3806 chip->bus = bus;
3807 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3808
3809 return 0;
3810}
3811
7b314362
AL		 3812static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3813{
04bed143 3814 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be
AL		 3815
3816 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3817 return DSA_TAG_PROTO_EDSA;
3818
3819 return DSA_TAG_PROTO_DSA;
7b314362
AL		 3820}
3821
fcdce7d0
AL		 3822static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3823 struct device *host_dev, int sw_addr,
3824 void **priv)
a77d43f1 3825{
fad09c73 3826 struct mv88e6xxx_chip *chip;
a439c061 3827 struct mii_bus *bus;
b516d453 3828 int err;
a77d43f1 3829
a439c061 3830 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3831 if (!bus)
3832 return NULL;
3833
fad09c73
VD		 3834 chip = mv88e6xxx_alloc_chip(dsa_dev);
3835 if (!chip)
469d729f
VD		 3836 return NULL;
3837
caac8545 3838 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3839 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3840
fad09c73 3841 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3842 if (err)
3843 goto free;
3844
fad09c73 3845 err = mv88e6xxx_detect(chip);
bc46a3d5 3846 if (err)
469d729f 3847 goto free;
a439c061 3848
dc30c35b
AL		 3849 mutex_lock(&chip->reg_lock);
3850 err = mv88e6xxx_switch_reset(chip);
3851 mutex_unlock(&chip->reg_lock);
3852 if (err)
3853 goto free;
3854
e57e5e77
VD		 3855 mv88e6xxx_phy_init(chip);
3856
fad09c73 3857 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3858 if (err)
469d729f 3859 goto free;
b516d453 3860
fad09c73 3861 *priv = chip;
a439c061 3862
fad09c73 3863 return chip->info->name;
469d729f 3864free:
fad09c73 3865 devm_kfree(dsa_dev, chip);
469d729f
VD		 3866
3867 return NULL;
a77d43f1
AL		 3868}
3869
7df8fbdd
VD		 3870static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3871 const struct switchdev_obj_port_mdb *mdb,
3872 struct switchdev_trans *trans)
3873{
3874 /* We don't need any dynamic resource from the kernel (yet),
3875 * so skip the prepare phase.
3876 */
3877
3878 return 0;
3879}
3880
3881static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3882 const struct switchdev_obj_port_mdb *mdb,
3883 struct switchdev_trans *trans)
3884{
04bed143 3885 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3886
3887 mutex_lock(&chip->reg_lock);
3888 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3889 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3890 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3891 mutex_unlock(&chip->reg_lock);
3892}
3893
3894static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3895 const struct switchdev_obj_port_mdb *mdb)
3896{
04bed143 3897 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3898 int err;
3899
3900 mutex_lock(&chip->reg_lock);
3901 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3902 GLOBAL_ATU_DATA_STATE_UNUSED);
3903 mutex_unlock(&chip->reg_lock);
3904
3905 return err;
3906}
3907
3908static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3909 struct switchdev_obj_port_mdb *mdb,
3910 int (*cb)(struct switchdev_obj *obj))
3911{
04bed143 3912 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3913 int err;
3914
3915 mutex_lock(&chip->reg_lock);
3916 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3917 mutex_unlock(&chip->reg_lock);
3918
3919 return err;
3920}
3921
9d490b4e 3922static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3923 .probe = mv88e6xxx_drv_probe,
7b314362 3924 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3925 .setup = mv88e6xxx_setup,
3926 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3927 .adjust_link = mv88e6xxx_adjust_link,
3928 .get_strings = mv88e6xxx_get_strings,
3929 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3930 .get_sset_count = mv88e6xxx_get_sset_count,
3931 .set_eee = mv88e6xxx_set_eee,
3932 .get_eee = mv88e6xxx_get_eee,
3933#ifdef CONFIG_NET_DSA_HWMON
3934 .get_temp = mv88e6xxx_get_temp,
3935 .get_temp_limit = mv88e6xxx_get_temp_limit,
3936 .set_temp_limit = mv88e6xxx_set_temp_limit,
3937 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3938#endif
f8cd8753 3939 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3940 .get_eeprom = mv88e6xxx_get_eeprom,
3941 .set_eeprom = mv88e6xxx_set_eeprom,
3942 .get_regs_len = mv88e6xxx_get_regs_len,
3943 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3944 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3945 .port_bridge_join = mv88e6xxx_port_bridge_join,
3946 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3947 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3948 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3949 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3950 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3951 .port_vlan_add = mv88e6xxx_port_vlan_add,
3952 .port_vlan_del = mv88e6xxx_port_vlan_del,
3953 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3954 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3955 .port_fdb_add = mv88e6xxx_port_fdb_add,
3956 .port_fdb_del = mv88e6xxx_port_fdb_del,
3957 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3958 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3959 .port_mdb_add = mv88e6xxx_port_mdb_add,
3960 .port_mdb_del = mv88e6xxx_port_mdb_del,
3961 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 3962};
3963
fad09c73 3964static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3965 struct device_node *np)
3966{
fad09c73 3967 struct device *dev = chip->dev;
b7e66a5f
VD		 3968 struct dsa_switch *ds;
3969
3970 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3971 if (!ds)
3972 return -ENOMEM;
3973
3974 ds->dev = dev;
fad09c73 3975 ds->priv = chip;
9d490b4e 3976 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 3977
3978 dev_set_drvdata(dev, ds);
3979
3980 return dsa_register_switch(ds, np);
3981}
3982
fad09c73 3983static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3984{
fad09c73 3985 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3986}
3987
57d32310 3988static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3989{
14c7b3c3 3990 struct device *dev = &mdiodev->dev;
f8cd8753 3991 struct device_node *np = dev->of_node;
caac8545 3992 const struct mv88e6xxx_info *compat_info;
fad09c73 3993 struct mv88e6xxx_chip *chip;
f8cd8753 3994 u32 eeprom_len;
52638f71 3995 int err;
14c7b3c3 3996
caac8545
VD		 3997 compat_info = of_device_get_match_data(dev);
3998 if (!compat_info)
3999 return -EINVAL;
4000
fad09c73
VD		 4001 chip = mv88e6xxx_alloc_chip(dev);
4002 if (!chip)
14c7b3c3
AL		 4003 return -ENOMEM;
4004
fad09c73 4005 chip->info = compat_info;
caac8545 4006
fad09c73 4007 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4008 if (err)
4009 return err;
14c7b3c3 4010
fad09c73 4011 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4012 if (err)
4013 return err;
14c7b3c3 4014
e57e5e77
VD		 4015 mv88e6xxx_phy_init(chip);
4016
fad09c73
VD		 4017 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4018 if (IS_ERR(chip->reset))
4019 return PTR_ERR(chip->reset);
52638f71 4020
ee4dc2e7 4021 if (chip->info->ops->get_eeprom &&
f8cd8753 4022 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4023 chip->eeprom_len = eeprom_len;
f8cd8753 4024
dc30c35b
AL		 4025 mutex_lock(&chip->reg_lock);
4026 err = mv88e6xxx_switch_reset(chip);
4027 mutex_unlock(&chip->reg_lock);
4028 if (err)
4029 goto out;
4030
4031 chip->irq = of_irq_get(np, 0);
4032 if (chip->irq == -EPROBE_DEFER) {
4033 err = chip->irq;
4034 goto out;
4035 }
4036
4037 if (chip->irq > 0) {
4038 /* Has to be performed before the MDIO bus is created,
4039 * because the PHYs will link there interrupts to these
4040 * interrupt controllers
4041 */
4042 mutex_lock(&chip->reg_lock);
4043 err = mv88e6xxx_g1_irq_setup(chip);
4044 mutex_unlock(&chip->reg_lock);
4045
4046 if (err)
4047 goto out;
4048
4049 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4050 err = mv88e6xxx_g2_irq_setup(chip);
4051 if (err)
4052 goto out_g1_irq;
4053 }
4054 }
4055
fad09c73 4056 err = mv88e6xxx_mdio_register(chip, np);
b516d453 4057 if (err)
dc30c35b 4058 goto out_g2_irq;
b516d453 4059
fad09c73 4060 err = mv88e6xxx_register_switch(chip, np);
dc30c35b
AL		 4061 if (err)
4062 goto out_mdio;
83c0afae 4063
98e67308 4064 return 0;
dc30c35b
AL		 4065
4066out_mdio:
4067 mv88e6xxx_mdio_unregister(chip);
4068out_g2_irq:
4069 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4070 mv88e6xxx_g2_irq_free(chip);
4071out_g1_irq:
4072 mv88e6xxx_g1_irq_free(chip);
4073out:
4074 return err;
98e67308 4075}
14c7b3c3
AL		 4076
4077static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4078{
4079 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4080 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4081
930188ce 4082 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 4083 mv88e6xxx_unregister_switch(chip);
4084 mv88e6xxx_mdio_unregister(chip);
dc30c35b
AL		 4085
4086 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4087 mv88e6xxx_g2_irq_free(chip);
4088 mv88e6xxx_g1_irq_free(chip);
14c7b3c3
AL		 4089}
4090
4091static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4092 {
4093 .compatible = "marvell,mv88e6085",
4094 .data = &mv88e6xxx_table[MV88E6085],
4095 },
14c7b3c3
AL		 4096 { /* sentinel */ },
4097};
4098
4099MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4100
4101static struct mdio_driver mv88e6xxx_driver = {
4102 .probe = mv88e6xxx_probe,
4103 .remove = mv88e6xxx_remove,
4104 .mdiodrv.driver = {
4105 .name = "mv88e6085",
4106 .of_match_table = mv88e6xxx_of_match,
4107 },
4108};
4109
4110static int __init mv88e6xxx_init(void)
4111{
9d490b4e 4112 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 4113 return mdio_driver_register(&mv88e6xxx_driver);
4114}
98e67308
BH		 4115module_init(mv88e6xxx_init);
4116
4117static void __exit mv88e6xxx_cleanup(void)
4118{
14c7b3c3 4119 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 4120 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 4121}
4122module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4123
4124MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4125MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4126MODULE_LICENSE("GPL");
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