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Merge branch 'ravb-gigabit-R-Car-H3-ES1.1-and-R-Car-M3-W'
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
ee26a228
AL		 225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
efb3e74d
AL		 228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
ee26a228
AL		 232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
efb3e74d
AL		 235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
a3c53be5
AL		 239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
e57e5e77
VD		 251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 255 struct mii_bus *bus;
e57e5e77 256
a3c53be5
AL		 257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
e57e5e77
VD		 259 return -EOPNOTSUPP;
260
a3c53be5 261 if (!chip->info->ops->phy_read)
ee26a228
AL		 262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 271 struct mii_bus *bus;
e57e5e77 272
a3c53be5
AL		 273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
e57e5e77
VD		 275 return -EOPNOTSUPP;
276
a3c53be5 277 if (!chip->info->ops->phy_write)
ee26a228
AL		 278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 281}
282
09cb7dfd
VD		 283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
dc30c35b
AL		 351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
3460a577
AL		 452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
dc30c35b 459
5edef2f2 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 462 irq_dispose_mapping(virq);
463 }
464
a3db3d3a 465 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
3dd0ef05
AL		 470 int err, irq, virq;
471 u16 reg, mask;
dc30c35b
AL		 472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
3dd0ef05 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 487 if (err)
3dd0ef05 488 goto out_mapping;
dc30c35b 489
3dd0ef05 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 491
3dd0ef05 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 493 if (err)
3dd0ef05 494 goto out_disable;
dc30c35b
AL		 495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
3dd0ef05 499 goto out_disable;
dc30c35b
AL		 500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
3dd0ef05 506 goto out_disable;
dc30c35b
AL		 507
508 return 0;
509
3dd0ef05
AL		 510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 521
522 return err;
523}
524
ec561276 525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 526{
6441e669 527 int i;
2d79af6e 528
6441e669 529 for (i = 0; i < 16; i++) {
2d79af6e
VD		 530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
30853553 543 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 544 return -ETIMEDOUT;
545}
546
f22ab641 547/* Indirect write to single pointer-data register with an Update bit */
ec561276 548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 549{
550 u16 val;
0f02b4f7 551 int err;
f22ab641
VD		 552
553 /* Wait until the previous operation is completed */
0f02b4f7
AL		 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
f22ab641
VD		 557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
a935c052 564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 565{
a199d8b6
VD		 566 if (!chip->info->ops->ppu_disable)
567 return 0;
2e5f0320 568
a199d8b6 569 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 570}
571
fad09c73 572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 573{
a199d8b6
VD		 574 if (!chip->info->ops->ppu_enable)
575 return 0;
2e5f0320 576
a199d8b6 577 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
fad09c73 582 struct mv88e6xxx_chip *chip;
2e5f0320 583
fad09c73 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 585
fad09c73 586 mutex_lock(&chip->reg_lock);
762eb67b 587
fad09c73
VD		 588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
2e5f0320 592 }
762eb67b 593
fad09c73 594 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
fad09c73 599 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 600
fad09c73 601 schedule_work(&chip->ppu_work);
2e5f0320
LB		 602}
603
fad09c73 604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 605{
2e5f0320
LB		 606 int ret;
607
fad09c73 608 mutex_lock(&chip->ppu_mutex);
2e5f0320 609
3675c8d7 610 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
fad09c73
VD		 615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
85686581 617 if (ret < 0) {
fad09c73 618 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 619 return ret;
620 }
fad09c73 621 chip->ppu_disabled = 1;
2e5f0320 622 } else {
fad09c73 623 del_timer(&chip->ppu_timer);
85686581 624 ret = 0;
2e5f0320
LB		 625 }
626
627 return ret;
628}
629
fad09c73 630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 631{
3675c8d7 632 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 635}
636
fad09c73 637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 638{
fad09c73
VD		 639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
2e5f0320
LB		 643}
644
930188ce
AL		 645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
ee26a228
AL		 650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
2e5f0320 653{
e57e5e77 654 int err;
2e5f0320 655
e57e5e77
VD		 656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 659 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 660 }
661
e57e5e77 662 return err;
2e5f0320
LB		 663}
664
ee26a228
AL		 665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 693}
694
fad09c73 695static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 696{
fad09c73 697 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 698}
699
fad09c73 700static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 703}
704
fad09c73 705static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 708}
709
fad09c73 710static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 711{
fad09c73 712 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 713}
714
d78343d2
VD		 715static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
716 int link, int speed, int duplex,
717 phy_interface_t mode)
718{
719 int err;
720
721 if (!chip->info->ops->port_set_link)
722 return 0;
723
724 /* Port's MAC control must not be changed unless the link is down */
725 err = chip->info->ops->port_set_link(chip, port, 0);
726 if (err)
727 return err;
728
729 if (chip->info->ops->port_set_speed) {
730 err = chip->info->ops->port_set_speed(chip, port, speed);
731 if (err && err != -EOPNOTSUPP)
732 goto restore_link;
733 }
734
735 if (chip->info->ops->port_set_duplex) {
736 err = chip->info->ops->port_set_duplex(chip, port, duplex);
737 if (err && err != -EOPNOTSUPP)
738 goto restore_link;
739 }
740
741 if (chip->info->ops->port_set_rgmii_delay) {
742 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
743 if (err && err != -EOPNOTSUPP)
744 goto restore_link;
745 }
746
747 err = 0;
748restore_link:
749 if (chip->info->ops->port_set_link(chip, port, link))
750 netdev_err(chip->ds->ports[port].netdev,
751 "failed to restore MAC's link\n");
752
753 return err;
754}
755
dea87024
AL		 756/* We expect the switch to perform auto negotiation if there is a real
757 * phy. However, in the case of a fixed link phy, we force the port
758 * settings from the fixed link settings.
759 */
f81ec90f
VD		 760static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
761 struct phy_device *phydev)
dea87024 762{
04bed143 763 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 764 int err;
dea87024
AL		 765
766 if (!phy_is_pseudo_fixed_link(phydev))
767 return;
768
fad09c73 769 mutex_lock(&chip->reg_lock);
d78343d2
VD		 770 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
771 phydev->duplex, phydev->interface);
fad09c73 772 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 773
774 if (err && err != -EOPNOTSUPP)
775 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 776}
777
a605a0fe 778static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 779{
a605a0fe
AL		 780 if (!chip->info->ops->stats_snapshot)
781 return -EOPNOTSUPP;
91da11f8 782
a605a0fe 783 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 784}
785
e413e7e1 786static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 787 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
788 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
789 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
790 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
791 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
792 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
793 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
794 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
795 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
796 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
797 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
798 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
799 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
800 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
801 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
802 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
803 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
804 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
805 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
806 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
807 { "single", 4, 0x14, STATS_TYPE_BANK0, },
808 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
809 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
810 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
811 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
812 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
813 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
814 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
815 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
816 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
817 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
818 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
819 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
820 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
821 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
822 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
823 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
824 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
826 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
828 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
829 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
830 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
831 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
832 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
833 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
834 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
835 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
836 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
837 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
838 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
839 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
840 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
841 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
842 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
843 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
844 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
845 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 846};
847
fad09c73 848static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 849 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 850 int port, u16 bank1_select,
851 u16 histogram)
80c4627b 852{
80c4627b
AL		 853 u32 low;
854 u32 high = 0;
dfafe449 855 u16 reg = 0;
0e7b9925 856 int err;
80c4627b
AL		 857 u64 value;
858
f5e2ed02 859 switch (s->type) {
dfafe449 860 case STATS_TYPE_PORT:
0e7b9925
AL		 861 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
862 if (err)
80c4627b
AL		 863 return UINT64_MAX;
864
0e7b9925 865 low = reg;
80c4627b 866 if (s->sizeof_stat == 4) {
0e7b9925
AL		 867 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
868 if (err)
80c4627b 869 return UINT64_MAX;
0e7b9925 870 high = reg;
80c4627b 871 }
f5e2ed02 872 break;
dfafe449 873 case STATS_TYPE_BANK1:
e0d8b615 874 reg = bank1_select;
dfafe449
AL		 875 /* fall through */
876 case STATS_TYPE_BANK0:
e0d8b615 877 reg |= s->reg | histogram;
7f9ef3af 878 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 879 if (s->sizeof_stat == 8)
7f9ef3af 880 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 881 }
882 value = (((u64)high) << 16) | low;
883 return value;
884}
885
dfafe449
AL		 886static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
887 uint8_t *data, int types)
91da11f8 888{
f5e2ed02
AL		 889 struct mv88e6xxx_hw_stat *stat;
890 int i, j;
91da11f8 891
f5e2ed02
AL		 892 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
893 stat = &mv88e6xxx_hw_stats[i];
dfafe449 894 if (stat->type & types) {
f5e2ed02
AL		 895 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
896 ETH_GSTRING_LEN);
897 j++;
898 }
91da11f8 899 }
e413e7e1
AL		 900}
901
dfafe449
AL		 902static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
903 uint8_t *data)
904{
905 mv88e6xxx_stats_get_strings(chip, data,
906 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
907}
908
909static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
910 uint8_t *data)
911{
912 mv88e6xxx_stats_get_strings(chip, data,
913 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
914}
915
916static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
917 uint8_t *data)
e413e7e1 918{
04bed143 919 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 920
921 if (chip->info->ops->stats_get_strings)
922 chip->info->ops->stats_get_strings(chip, data);
923}
924
925static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
926 int types)
927{
f5e2ed02
AL		 928 struct mv88e6xxx_hw_stat *stat;
929 int i, j;
930
931 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
932 stat = &mv88e6xxx_hw_stats[i];
dfafe449 933 if (stat->type & types)
f5e2ed02
AL		 934 j++;
935 }
936 return j;
e413e7e1
AL		 937}
938
dfafe449
AL		 939static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
940{
941 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
942 STATS_TYPE_PORT);
943}
944
945static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
946{
947 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
948 STATS_TYPE_BANK1);
949}
950
951static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
952{
953 struct mv88e6xxx_chip *chip = ds->priv;
954
955 if (chip->info->ops->stats_get_sset_count)
956 return chip->info->ops->stats_get_sset_count(chip);
957
958 return 0;
959}
960
052f947f 961static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 962 uint64_t *data, int types,
963 u16 bank1_select, u16 histogram)
052f947f
AL		 964{
965 struct mv88e6xxx_hw_stat *stat;
966 int i, j;
967
968 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
969 stat = &mv88e6xxx_hw_stats[i];
970 if (stat->type & types) {
e0d8b615
AL		 971 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
972 bank1_select,
973 histogram);
052f947f
AL		 974 j++;
975 }
976 }
977}
978
979static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
980 uint64_t *data)
981{
982 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 983 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
984 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 985}
986
987static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
988 uint64_t *data)
989{
990 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 991 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
992 GLOBAL_STATS_OP_BANK_1_BIT_9,
993 GLOBAL_STATS_OP_HIST_RX_TX);
994}
995
996static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
997 uint64_t *data)
998{
999 return mv88e6xxx_stats_get_stats(chip, port, data,
1000 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1001 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1002}
1003
1004static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1005 uint64_t *data)
1006{
1007 if (chip->info->ops->stats_get_stats)
1008 chip->info->ops->stats_get_stats(chip, port, data);
1009}
1010
f81ec90f
VD		 1011static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1012 uint64_t *data)
e413e7e1 1013{
04bed143 1014 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1015 int ret;
f5e2ed02 1016
fad09c73 1017 mutex_lock(&chip->reg_lock);
f5e2ed02 1018
a605a0fe 1019 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1020 if (ret < 0) {
fad09c73 1021 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1022 return;
1023 }
052f947f
AL		 1024
1025 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1026
fad09c73 1027 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1028}
1029
de227387
AL		 1030static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1031{
1032 if (chip->info->ops->stats_set_histogram)
1033 return chip->info->ops->stats_set_histogram(chip);
1034
1035 return 0;
1036}
1037
f81ec90f 1038static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1039{
1040 return 32 * sizeof(u16);
1041}
1042
f81ec90f
VD		 1043static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1044 struct ethtool_regs *regs, void *_p)
a1ab91f3 1045{
04bed143 1046 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1047 int err;
1048 u16 reg;
a1ab91f3
GR		 1049 u16 *p = _p;
1050 int i;
1051
1052 regs->version = 0;
1053
1054 memset(p, 0xff, 32 * sizeof(u16));
1055
fad09c73 1056 mutex_lock(&chip->reg_lock);
23062513 1057
a1ab91f3 1058 for (i = 0; i < 32; i++) {
a1ab91f3 1059
0e7b9925
AL		 1060 err = mv88e6xxx_port_read(chip, port, i, &reg);
1061 if (!err)
1062 p[i] = reg;
a1ab91f3 1063 }
23062513 1064
fad09c73 1065 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1066}
1067
fad09c73 1068static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1069{
a935c052 1070 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1071}
1072
f81ec90f
VD		 1073static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1074 struct ethtool_eee *e)
11b3b45d 1075{
04bed143 1076 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1077 u16 reg;
1078 int err;
11b3b45d 1079
fad09c73 1080 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1081 return -EOPNOTSUPP;
1082
fad09c73 1083 mutex_lock(&chip->reg_lock);
2f40c698 1084
9c93829c
VD		 1085 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1086 if (err)
2f40c698 1087 goto out;
11b3b45d
GR		 1088
1089 e->eee_enabled = !!(reg & 0x0200);
1090 e->tx_lpi_enabled = !!(reg & 0x0100);
1091
0e7b9925 1092 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1093 if (err)
2f40c698 1094 goto out;
11b3b45d 1095
cca8b133 1096 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1097out:
fad09c73 1098 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1099
1100 return err;
11b3b45d
GR		 1101}
1102
f81ec90f
VD		 1103static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1104 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1105{
04bed143 1106 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1107 u16 reg;
1108 int err;
11b3b45d 1109
fad09c73 1110 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1111 return -EOPNOTSUPP;
1112
fad09c73 1113 mutex_lock(&chip->reg_lock);
11b3b45d 1114
9c93829c
VD		 1115 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1116 if (err)
2f40c698
AL		 1117 goto out;
1118
9c93829c 1119 reg &= ~0x0300;
2f40c698
AL		 1120 if (e->eee_enabled)
1121 reg |= 0x0200;
1122 if (e->tx_lpi_enabled)
1123 reg |= 0x0100;
1124
9c93829c 1125 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1126out:
fad09c73 1127 mutex_unlock(&chip->reg_lock);
2f40c698 1128
9c93829c 1129 return err;
11b3b45d
GR		 1130}
1131
fad09c73 1132static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1133{
a935c052
VD		 1134 u16 val;
1135 int err;
facd95b2 1136
6dc10bbc 1137 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1138 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1139 if (err)
1140 return err;
fad09c73 1141 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1142 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1143 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1144 if (err)
1145 return err;
11ea809f 1146
a935c052
VD		 1147 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1148 (val & 0xfff) | ((fid << 8) & 0xf000));
1149 if (err)
1150 return err;
11ea809f
VD		 1151
1152 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1153 cmd |= fid & 0xf;
b426e5f7
VD		 1154 }
1155
a935c052
VD		 1156 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1157 if (err)
1158 return err;
facd95b2 1159
fad09c73 1160 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1161}
1162
fad09c73 1163static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1164 struct mv88e6xxx_atu_entry *entry)
1165{
1166 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1167
1168 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1169 unsigned int mask, shift;
1170
1171 if (entry->trunk) {
1172 data |= GLOBAL_ATU_DATA_TRUNK;
1173 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1174 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1175 } else {
1176 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1177 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1178 }
1179
1180 data |= (entry->portv_trunkid << shift) & mask;
1181 }
1182
a935c052 1183 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1184}
1185
fad09c73 1186static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1187 struct mv88e6xxx_atu_entry *entry,
1188 bool static_too)
facd95b2 1189{
7fb5e755
VD		 1190 int op;
1191 int err;
facd95b2 1192
fad09c73 1193 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1194 if (err)
1195 return err;
facd95b2 1196
fad09c73 1197 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1198 if (err)
1199 return err;
1200
1201 if (entry->fid) {
7fb5e755
VD		 1202 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1203 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1204 } else {
1205 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1206 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1207 }
1208
fad09c73 1209 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1210}
1211
fad09c73 1212static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1213 u16 fid, bool static_too)
7fb5e755
VD		 1214{
1215 struct mv88e6xxx_atu_entry entry = {
1216 .fid = fid,
1217 .state = 0, /* EntryState bits must be 0 */
1218 };
70cc99d1 1219
fad09c73 1220 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1221}
1222
fad09c73 1223static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1224 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1225{
1226 struct mv88e6xxx_atu_entry entry = {
1227 .trunk = false,
1228 .fid = fid,
1229 };
1230
1231 /* EntryState bits must be 0xF */
1232 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1233
1234 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1235 entry.portv_trunkid = (to_port & 0x0f) << 4;
1236 entry.portv_trunkid |= from_port & 0x0f;
1237
fad09c73 1238 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1239}
1240
fad09c73 1241static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1242 int port, bool static_too)
9f4d55d2
VD		 1243{
1244 /* Destination port 0xF means remove the entries */
fad09c73 1245 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1246}
1247
fad09c73 1248static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1249{
fad09c73 1250 struct net_device *bridge = chip->ports[port].bridge_dev;
fad09c73 1251 struct dsa_switch *ds = chip->ds;
b7666efe 1252 u16 output_ports = 0;
b7666efe
VD		 1253 int i;
1254
1255 /* allow CPU port or DSA link(s) to send frames to every port */
1256 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1257 output_ports = ~0;
b7666efe 1258 } else {
370b4ffb 1259 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1260 /* allow sending frames to every group member */
fad09c73 1261 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1262 output_ports |= BIT(i);
1263
1264 /* allow sending frames to CPU port and DSA link(s) */
1265 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1266 output_ports |= BIT(i);
1267 }
1268 }
1269
1270 /* prevent frames from going back out of the port they came in on */
1271 output_ports &= ~BIT(port);
facd95b2 1272
5a7921f4 1273 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1274}
1275
f81ec90f
VD		 1276static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1277 u8 state)
facd95b2 1278{
04bed143 1279 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1280 int stp_state;
553eb544 1281 int err;
facd95b2
GR		 1282
1283 switch (state) {
1284 case BR_STATE_DISABLED:
cca8b133 1285 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1286 break;
1287 case BR_STATE_BLOCKING:
1288 case BR_STATE_LISTENING:
cca8b133 1289 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1290 break;
1291 case BR_STATE_LEARNING:
cca8b133 1292 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1293 break;
1294 case BR_STATE_FORWARDING:
1295 default:
cca8b133 1296 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1297 break;
1298 }
1299
fad09c73 1300 mutex_lock(&chip->reg_lock);
e28def33 1301 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1302 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1303
1304 if (err)
e28def33 1305 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1306}
1307
749efcb8
VD		 1308static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1309{
1310 struct mv88e6xxx_chip *chip = ds->priv;
1311 int err;
1312
1313 mutex_lock(&chip->reg_lock);
1314 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1315 mutex_unlock(&chip->reg_lock);
1316
1317 if (err)
1318 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1319}
1320
fad09c73 1321static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1322{
a935c052 1323 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1324}
1325
fad09c73 1326static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1327{
a935c052 1328 int err;
6b17e864 1329
a935c052
VD		 1330 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1331 if (err)
1332 return err;
6b17e864 1333
fad09c73 1334 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1335}
1336
fad09c73 1337static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1338{
1339 int ret;
1340
fad09c73 1341 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1342 if (ret < 0)
1343 return ret;
1344
fad09c73 1345 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1346}
1347
fad09c73 1348static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1349 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1350 unsigned int nibble_offset)
1351{
b8fee957 1352 u16 regs[3];
a935c052 1353 int i, err;
b8fee957
VD		 1354
1355 for (i = 0; i < 3; ++i) {
a935c052 1356 u16 *reg = &regs[i];
b8fee957 1357
a935c052
VD		 1358 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1359 if (err)
1360 return err;
b8fee957
VD		 1361 }
1362
370b4ffb 1363 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1364 unsigned int shift = (i % 4) * 4 + nibble_offset;
1365 u16 reg = regs[i / 4];
1366
1367 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1368 }
1369
1370 return 0;
1371}
1372
fad09c73 1373static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1374 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1375{
fad09c73 1376 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1377}
1378
fad09c73 1379static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1380 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1381{
fad09c73 1382 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1383}
1384
fad09c73 1385static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1386 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1387 unsigned int nibble_offset)
1388{
7dad08d7 1389 u16 regs[3] = { 0 };
a935c052 1390 int i, err;
7dad08d7 1391
370b4ffb 1392 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1393 unsigned int shift = (i % 4) * 4 + nibble_offset;
1394 u8 data = entry->data[i];
1395
1396 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1397 }
1398
1399 for (i = 0; i < 3; ++i) {
a935c052
VD		 1400 u16 reg = regs[i];
1401
1402 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1403 if (err)
1404 return err;
7dad08d7
VD		 1405 }
1406
1407 return 0;
1408}
1409
fad09c73 1410static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1411 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1412{
fad09c73 1413 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1414}
1415
fad09c73 1416static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1417 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1418{
fad09c73 1419 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1420}
1421
fad09c73 1422static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1423{
a935c052
VD		 1424 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1425 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1426}
1427
fad09c73 1428static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1429 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1430{
b4e47c0f 1431 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1432 u16 val;
1433 int err;
b8fee957 1434
a935c052
VD		 1435 err = _mv88e6xxx_vtu_wait(chip);
1436 if (err)
1437 return err;
b8fee957 1438
a935c052
VD		 1439 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1440 if (err)
1441 return err;
b8fee957 1442
a935c052
VD		 1443 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1444 if (err)
1445 return err;
b8fee957 1446
a935c052
VD		 1447 next.vid = val & GLOBAL_VTU_VID_MASK;
1448 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1449
1450 if (next.valid) {
a935c052
VD		 1451 err = mv88e6xxx_vtu_data_read(chip, &next);
1452 if (err)
1453 return err;
b8fee957 1454
6dc10bbc 1455 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1456 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1457 if (err)
1458 return err;
b8fee957 1459
a935c052 1460 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1461 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1462 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1463 * VTU DBNum[3:0] are located in VTU Operation 3:0
1464 */
a935c052
VD		 1465 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1466 if (err)
1467 return err;
11ea809f 1468
a935c052
VD		 1469 next.fid = (val & 0xf00) >> 4;
1470 next.fid |= val & 0xf;
2e7bd5ef 1471 }
b8fee957 1472
fad09c73 1473 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1474 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1475 if (err)
1476 return err;
b8fee957 1477
a935c052 1478 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1479 }
1480 }
1481
1482 *entry = next;
1483 return 0;
1484}
1485
f81ec90f
VD		 1486static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1487 struct switchdev_obj_port_vlan *vlan,
1488 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1489{
04bed143 1490 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1491 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1492 u16 pvid;
1493 int err;
1494
fad09c73 1495 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1496 return -EOPNOTSUPP;
1497
fad09c73 1498 mutex_lock(&chip->reg_lock);
ceff5eff 1499
77064f37 1500 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1501 if (err)
1502 goto unlock;
1503
fad09c73 1504 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1505 if (err)
1506 goto unlock;
1507
1508 do {
fad09c73 1509 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1510 if (err)
1511 break;
1512
1513 if (!next.valid)
1514 break;
1515
1516 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1517 continue;
1518
1519 /* reinit and dump this VLAN obj */
57d32310
VD		 1520 vlan->vid_begin = next.vid;
1521 vlan->vid_end = next.vid;
ceff5eff
VD		 1522 vlan->flags = 0;
1523
1524 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1525 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1526
1527 if (next.vid == pvid)
1528 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1529
1530 err = cb(&vlan->obj);
1531 if (err)
1532 break;
1533 } while (next.vid < GLOBAL_VTU_VID_MASK);
1534
1535unlock:
fad09c73 1536 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1537
1538 return err;
1539}
1540
fad09c73 1541static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1542 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1543{
11ea809f 1544 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1545 u16 reg = 0;
a935c052 1546 int err;
7dad08d7 1547
a935c052
VD		 1548 err = _mv88e6xxx_vtu_wait(chip);
1549 if (err)
1550 return err;
7dad08d7
VD		 1551
1552 if (!entry->valid)
1553 goto loadpurge;
1554
1555 /* Write port member tags */
a935c052
VD		 1556 err = mv88e6xxx_vtu_data_write(chip, entry);
1557 if (err)
1558 return err;
7dad08d7 1559
fad09c73 1560 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1561 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1562 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1563 if (err)
1564 return err;
b426e5f7 1565 }
7dad08d7 1566
6dc10bbc 1567 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1568 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1569 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1570 if (err)
1571 return err;
fad09c73 1572 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1573 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1574 * VTU DBNum[3:0] are located in VTU Operation 3:0
1575 */
1576 op |= (entry->fid & 0xf0) << 8;
1577 op |= entry->fid & 0xf;
7dad08d7
VD		 1578 }
1579
1580 reg = GLOBAL_VTU_VID_VALID;
1581loadpurge:
1582 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1583 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1584 if (err)
1585 return err;
7dad08d7 1586
fad09c73 1587 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1588}
1589
fad09c73 1590static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1591 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1592{
b4e47c0f 1593 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1594 u16 val;
1595 int err;
0d3b33e6 1596
a935c052
VD		 1597 err = _mv88e6xxx_vtu_wait(chip);
1598 if (err)
1599 return err;
0d3b33e6 1600
a935c052
VD		 1601 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1602 sid & GLOBAL_VTU_SID_MASK);
1603 if (err)
1604 return err;
0d3b33e6 1605
a935c052
VD		 1606 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1607 if (err)
1608 return err;
0d3b33e6 1609
a935c052
VD		 1610 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1611 if (err)
1612 return err;
0d3b33e6 1613
a935c052 1614 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1615
a935c052
VD		 1616 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1617 if (err)
1618 return err;
0d3b33e6 1619
a935c052 1620 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1621
1622 if (next.valid) {
a935c052
VD		 1623 err = mv88e6xxx_stu_data_read(chip, &next);
1624 if (err)
1625 return err;
0d3b33e6
VD		 1626 }
1627
1628 *entry = next;
1629 return 0;
1630}
1631
fad09c73 1632static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1633 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1634{
1635 u16 reg = 0;
a935c052 1636 int err;
0d3b33e6 1637
a935c052
VD		 1638 err = _mv88e6xxx_vtu_wait(chip);
1639 if (err)
1640 return err;
0d3b33e6
VD		 1641
1642 if (!entry->valid)
1643 goto loadpurge;
1644
1645 /* Write port states */
a935c052
VD		 1646 err = mv88e6xxx_stu_data_write(chip, entry);
1647 if (err)
1648 return err;
0d3b33e6
VD		 1649
1650 reg = GLOBAL_VTU_VID_VALID;
1651loadpurge:
a935c052
VD		 1652 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1653 if (err)
1654 return err;
0d3b33e6
VD		 1655
1656 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1657 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1658 if (err)
1659 return err;
0d3b33e6 1660
fad09c73 1661 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1662}
1663
fad09c73 1664static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1665{
1666 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1667 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1668 int i, err;
3285f9e8
VD		 1669
1670 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1671
2db9ce1f 1672 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1673 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1674 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1675 if (err)
1676 return err;
1677
1678 set_bit(*fid, fid_bitmap);
1679 }
1680
3285f9e8 1681 /* Set every FID bit used by the VLAN entries */
fad09c73 1682 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1683 if (err)
1684 return err;
1685
1686 do {
fad09c73 1687 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1688 if (err)
1689 return err;
1690
1691 if (!vlan.valid)
1692 break;
1693
1694 set_bit(vlan.fid, fid_bitmap);
1695 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1696
1697 /* The reset value 0x000 is used to indicate that multiple address
1698 * databases are not needed. Return the next positive available.
1699 */
1700 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1701 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1702 return -ENOSPC;
1703
1704 /* Clear the database */
fad09c73 1705 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1706}
1707
fad09c73 1708static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1709 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1710{
fad09c73 1711 struct dsa_switch *ds = chip->ds;
b4e47c0f 1712 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1713 .valid = true,
1714 .vid = vid,
1715 };
3285f9e8
VD		 1716 int i, err;
1717
fad09c73 1718 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1719 if (err)
1720 return err;
0d3b33e6 1721
3d131f07 1722 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1723 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1724 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1725 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1726 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1727
fad09c73
VD		 1728 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1729 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1730 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1731
1732 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1733 * implemented, only one STU entry is needed to cover all VTU
1734 * entries. Thus, validate the SID 0.
1735 */
1736 vlan.sid = 0;
fad09c73 1737 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1738 if (err)
1739 return err;
1740
1741 if (vstp.sid != vlan.sid || !vstp.valid) {
1742 memset(&vstp, 0, sizeof(vstp));
1743 vstp.valid = true;
1744 vstp.sid = vlan.sid;
1745
fad09c73 1746 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1747 if (err)
1748 return err;
1749 }
0d3b33e6
VD		 1750 }
1751
1752 *entry = vlan;
1753 return 0;
1754}
1755
fad09c73 1756static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1757 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1758{
1759 int err;
1760
1761 if (!vid)
1762 return -EINVAL;
1763
fad09c73 1764 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1765 if (err)
1766 return err;
1767
fad09c73 1768 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1769 if (err)
1770 return err;
1771
1772 if (entry->vid != vid || !entry->valid) {
1773 if (!creat)
1774 return -EOPNOTSUPP;
1775 /* -ENOENT would've been more appropriate, but switchdev expects
1776 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1777 */
1778
fad09c73 1779 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1780 }
1781
1782 return err;
1783}
1784
da9c359e
VD		 1785static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1786 u16 vid_begin, u16 vid_end)
1787{
04bed143 1788 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1789 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1790 int i, err;
1791
1792 if (!vid_begin)
1793 return -EOPNOTSUPP;
1794
fad09c73 1795 mutex_lock(&chip->reg_lock);
da9c359e 1796
fad09c73 1797 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1798 if (err)
1799 goto unlock;
1800
1801 do {
fad09c73 1802 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1803 if (err)
1804 goto unlock;
1805
1806 if (!vlan.valid)
1807 break;
1808
1809 if (vlan.vid > vid_end)
1810 break;
1811
370b4ffb 1812 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1813 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1814 continue;
1815
66e2809d
AL		 1816 if (!ds->ports[port].netdev)
1817 continue;
1818
da9c359e
VD		 1819 if (vlan.data[i] ==
1820 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1821 continue;
1822
fad09c73
VD		 1823 if (chip->ports[i].bridge_dev ==
1824 chip->ports[port].bridge_dev)
da9c359e
VD		 1825 break; /* same bridge, check next VLAN */
1826
66e2809d
AL		 1827 if (!chip->ports[i].bridge_dev)
1828 continue;
1829
c8b09808 1830 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1831 "hardware VLAN %d already used by %s\n",
1832 vlan.vid,
fad09c73 1833 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1834 err = -EOPNOTSUPP;
1835 goto unlock;
1836 }
1837 } while (vlan.vid < vid_end);
1838
1839unlock:
fad09c73 1840 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1841
1842 return err;
1843}
1844
f81ec90f
VD		 1845static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1846 bool vlan_filtering)
214cdb99 1847{
04bed143 1848 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1849 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1850 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1851 int err;
214cdb99 1852
fad09c73 1853 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1854 return -EOPNOTSUPP;
1855
fad09c73 1856 mutex_lock(&chip->reg_lock);
385a0995 1857 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1858 mutex_unlock(&chip->reg_lock);
214cdb99 1859
0e7b9925 1860 return err;
214cdb99
VD		 1861}
1862
57d32310
VD		 1863static int
1864mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1865 const struct switchdev_obj_port_vlan *vlan,
1866 struct switchdev_trans *trans)
76e398a6 1867{
04bed143 1868 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1869 int err;
1870
fad09c73 1871 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1872 return -EOPNOTSUPP;
1873
da9c359e
VD		 1874 /* If the requested port doesn't belong to the same bridge as the VLAN
1875 * members, do not support it (yet) and fallback to software VLAN.
1876 */
1877 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1878 vlan->vid_end);
1879 if (err)
1880 return err;
1881
76e398a6
VD		 1882 /* We don't need any dynamic resource from the kernel (yet),
1883 * so skip the prepare phase.
1884 */
1885 return 0;
1886}
1887
fad09c73 1888static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1889 u16 vid, bool untagged)
0d3b33e6 1890{
b4e47c0f 1891 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1892 int err;
1893
fad09c73 1894 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1895 if (err)
76e398a6 1896 return err;
0d3b33e6 1897
0d3b33e6
VD		 1898 vlan.data[port] = untagged ?
1899 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1900 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1901
fad09c73 1902 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1903}
1904
f81ec90f
VD		 1905static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1906 const struct switchdev_obj_port_vlan *vlan,
1907 struct switchdev_trans *trans)
76e398a6 1908{
04bed143 1909 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1910 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1911 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1912 u16 vid;
76e398a6 1913
fad09c73 1914 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1915 return;
1916
fad09c73 1917 mutex_lock(&chip->reg_lock);
76e398a6 1918
4d5770b3 1919 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1920 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1921 netdev_err(ds->ports[port].netdev,
1922 "failed to add VLAN %d%c\n",
4d5770b3 1923 vid, untagged ? 'u' : 't');
76e398a6 1924
77064f37 1925 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1926 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1927 vlan->vid_end);
0d3b33e6 1928
fad09c73 1929 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1930}
1931
fad09c73 1932static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1933 int port, u16 vid)
7dad08d7 1934{
fad09c73 1935 struct dsa_switch *ds = chip->ds;
b4e47c0f 1936 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1937 int i, err;
1938
fad09c73 1939 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1940 if (err)
76e398a6 1941 return err;
7dad08d7 1942
2fb5ef09
VD		 1943 /* Tell switchdev if this VLAN is handled in software */
1944 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1945 return -EOPNOTSUPP;
7dad08d7
VD		 1946
1947 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1948
1949 /* keep the VLAN unless all ports are excluded */
f02bdffc 1950 vlan.valid = false;
370b4ffb 1951 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1952 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1953 continue;
1954
1955 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1956 vlan.valid = true;
7dad08d7
VD		 1957 break;
1958 }
1959 }
1960
fad09c73 1961 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1962 if (err)
1963 return err;
1964
fad09c73 1965 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1966}
1967
f81ec90f
VD		 1968static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1969 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1970{
04bed143 1971 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1972 u16 pvid, vid;
1973 int err = 0;
1974
fad09c73 1975 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1976 return -EOPNOTSUPP;
1977
fad09c73 1978 mutex_lock(&chip->reg_lock);
76e398a6 1979
77064f37 1980 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1981 if (err)
1982 goto unlock;
1983
76e398a6 1984 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1985 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1986 if (err)
1987 goto unlock;
1988
1989 if (vid == pvid) {
77064f37 1990 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1991 if (err)
1992 goto unlock;
1993 }
1994 }
1995
7dad08d7 1996unlock:
fad09c73 1997 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1998
1999 return err;
2000}
2001
fad09c73 2002static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2003 const unsigned char *addr)
defb05b9 2004{
a935c052 2005 int i, err;
defb05b9
GR		 2006
2007 for (i = 0; i < 3; i++) {
a935c052
VD		 2008 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2009 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2010 if (err)
2011 return err;
defb05b9
GR		 2012 }
2013
2014 return 0;
2015}
2016
fad09c73 2017static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2018 unsigned char *addr)
defb05b9 2019{
a935c052
VD		 2020 u16 val;
2021 int i, err;
defb05b9
GR		 2022
2023 for (i = 0; i < 3; i++) {
a935c052
VD		 2024 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2025 if (err)
2026 return err;
2027
2028 addr[i * 2] = val >> 8;
2029 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2030 }
2031
2032 return 0;
2033}
2034
fad09c73 2035static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2036 struct mv88e6xxx_atu_entry *entry)
defb05b9 2037{
6630e236
VD		 2038 int ret;
2039
fad09c73 2040 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2041 if (ret < 0)
2042 return ret;
2043
fad09c73 2044 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2045 if (ret < 0)
2046 return ret;
2047
fad09c73 2048 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2049 if (ret < 0)
87820510
VD		 2050 return ret;
2051
fad09c73 2052 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2053}
87820510 2054
88472939
VD		 2055static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2056 struct mv88e6xxx_atu_entry *entry);
2057
2058static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2059 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2060{
2061 struct mv88e6xxx_atu_entry next;
2062 int err;
2063
59527581
AL		 2064 memcpy(next.mac, addr, ETH_ALEN);
2065 eth_addr_dec(next.mac);
88472939
VD		 2066
2067 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2068 if (err)
2069 return err;
2070
2071 do {
2072 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2073 if (err)
2074 return err;
2075
2076 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2077 break;
2078
2079 if (ether_addr_equal(next.mac, addr)) {
2080 *entry = next;
2081 return 0;
2082 }
59527581 2083 } while (ether_addr_greater(addr, next.mac));
88472939
VD		 2084
2085 memset(entry, 0, sizeof(*entry));
2086 entry->fid = fid;
2087 ether_addr_copy(entry->mac, addr);
2088
2089 return 0;
2090}
2091
83dabd1f
VD		 2092static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2093 const unsigned char *addr, u16 vid,
2094 u8 state)
fd231c82 2095{
b4e47c0f 2096 struct mv88e6xxx_vtu_entry vlan;
88472939 2097 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2098 int err;
2099
2db9ce1f
VD		 2100 /* Null VLAN ID corresponds to the port private database */
2101 if (vid == 0)
b4e48c50 2102 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2103 else
fad09c73 2104 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2105 if (err)
2106 return err;
fd231c82 2107
88472939
VD		 2108 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2109 if (err)
2110 return err;
2111
2112 /* Purge the ATU entry only if no port is using it anymore */
2113 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2114 entry.portv_trunkid &= ~BIT(port);
2115 if (!entry.portv_trunkid)
2116 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2117 } else {
2118 entry.portv_trunkid |= BIT(port);
2119 entry.state = state;
fd231c82
VD		 2120 }
2121
fad09c73 2122 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2123}
2124
f81ec90f
VD		 2125static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2126 const struct switchdev_obj_port_fdb *fdb,
2127 struct switchdev_trans *trans)
146a3206
VD		 2128{
2129 /* We don't need any dynamic resource from the kernel (yet),
2130 * so skip the prepare phase.
2131 */
2132 return 0;
2133}
2134
f81ec90f
VD		 2135static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2136 const struct switchdev_obj_port_fdb *fdb,
2137 struct switchdev_trans *trans)
87820510 2138{
04bed143 2139 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2140
fad09c73 2141 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2142 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2143 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2144 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2145 mutex_unlock(&chip->reg_lock);
87820510
VD		 2146}
2147
f81ec90f
VD		 2148static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2149 const struct switchdev_obj_port_fdb *fdb)
87820510 2150{
04bed143 2151 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2152 int err;
87820510 2153
fad09c73 2154 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2155 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2156 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2157 mutex_unlock(&chip->reg_lock);
87820510 2158
83dabd1f 2159 return err;
87820510
VD		 2160}
2161
fad09c73 2162static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2163 struct mv88e6xxx_atu_entry *entry)
6630e236 2164{
1d194046 2165 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2166 u16 val;
2167 int err;
1d194046
VD		 2168
2169 next.fid = fid;
defb05b9 2170
a935c052
VD		 2171 err = _mv88e6xxx_atu_wait(chip);
2172 if (err)
2173 return err;
6630e236 2174
a935c052
VD		 2175 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2176 if (err)
2177 return err;
6630e236 2178
a935c052
VD		 2179 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2180 if (err)
2181 return err;
6630e236 2182
a935c052
VD		 2183 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2184 if (err)
2185 return err;
6630e236 2186
a935c052 2187 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2188 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2189 unsigned int mask, shift;
2190
a935c052 2191 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2192 next.trunk = true;
2193 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2194 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2195 } else {
2196 next.trunk = false;
2197 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2198 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2199 }
2200
a935c052 2201 next.portv_trunkid = (val & mask) >> shift;
1d194046 2202 }
cdf09697 2203
1d194046 2204 *entry = next;
cdf09697
DM		 2205 return 0;
2206}
2207
83dabd1f
VD		 2208static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2209 u16 fid, u16 vid, int port,
2210 struct switchdev_obj *obj,
2211 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2212{
2213 struct mv88e6xxx_atu_entry addr = {
2214 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2215 };
2216 int err;
2217
fad09c73 2218 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2219 if (err)
2220 return err;
2221
2222 do {
fad09c73 2223 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2224 if (err)
83dabd1f 2225 return err;
74b6ba0d
VD		 2226
2227 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2228 break;
2229
83dabd1f
VD		 2230 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2231 continue;
2232
2233 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2234 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2235
83dabd1f
VD		 2236 if (!is_unicast_ether_addr(addr.mac))
2237 continue;
2238
2239 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2240 fdb->vid = vid;
2241 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2242 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2243 fdb->ndm_state = NUD_NOARP;
2244 else
2245 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2246 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2247 struct switchdev_obj_port_mdb *mdb;
2248
2249 if (!is_multicast_ether_addr(addr.mac))
2250 continue;
2251
2252 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2253 mdb->vid = vid;
2254 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2255 } else {
2256 return -EOPNOTSUPP;
74b6ba0d 2257 }
83dabd1f
VD		 2258
2259 err = cb(obj);
2260 if (err)
2261 return err;
74b6ba0d
VD		 2262 } while (!is_broadcast_ether_addr(addr.mac));
2263
2264 return err;
2265}
2266
83dabd1f
VD		 2267static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2268 struct switchdev_obj *obj,
2269 int (*cb)(struct switchdev_obj *obj))
f33475bd 2270{
b4e47c0f 2271 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2272 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2273 };
2db9ce1f 2274 u16 fid;
f33475bd
VD		 2275 int err;
2276
2db9ce1f 2277 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2278 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2279 if (err)
83dabd1f 2280 return err;
2db9ce1f 2281
83dabd1f 2282 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2283 if (err)
83dabd1f 2284 return err;
2db9ce1f 2285
74b6ba0d 2286 /* Dump VLANs' Filtering Information Databases */
fad09c73 2287 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2288 if (err)
83dabd1f 2289 return err;
f33475bd
VD		 2290
2291 do {
fad09c73 2292 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2293 if (err)
83dabd1f 2294 return err;
f33475bd
VD		 2295
2296 if (!vlan.valid)
2297 break;
2298
83dabd1f
VD		 2299 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2300 obj, cb);
f33475bd 2301 if (err)
83dabd1f 2302 return err;
f33475bd
VD		 2303 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2304
83dabd1f
VD		 2305 return err;
2306}
2307
2308static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2309 struct switchdev_obj_port_fdb *fdb,
2310 int (*cb)(struct switchdev_obj *obj))
2311{
04bed143 2312 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2313 int err;
2314
2315 mutex_lock(&chip->reg_lock);
2316 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2317 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2318
2319 return err;
2320}
2321
f81ec90f
VD		 2322static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2323 struct net_device *bridge)
e79a8bcb 2324{
04bed143 2325 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2326 int i, err = 0;
466dfa07 2327
fad09c73 2328 mutex_lock(&chip->reg_lock);
466dfa07 2329
b7666efe 2330 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2331 chip->ports[port].bridge_dev = bridge;
b7666efe 2332
370b4ffb 2333 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2334 if (chip->ports[i].bridge_dev == bridge) {
2335 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2336 if (err)
2337 break;
2338 }
2339 }
2340
fad09c73 2341 mutex_unlock(&chip->reg_lock);
a6692754 2342
466dfa07 2343 return err;
e79a8bcb
VD		 2344}
2345
f81ec90f 2346static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2347{
04bed143 2348 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2349 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2350 int i;
466dfa07 2351
fad09c73 2352 mutex_lock(&chip->reg_lock);
466dfa07 2353
b7666efe 2354 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2355 chip->ports[port].bridge_dev = NULL;
b7666efe 2356
370b4ffb 2357 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2358 if (i == port || chip->ports[i].bridge_dev == bridge)
2359 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2360 netdev_warn(ds->ports[i].netdev,
2361 "failed to remap\n");
b7666efe 2362
fad09c73 2363 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2364}
2365
17e708ba
VD		 2366static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2367{
2368 if (chip->info->ops->reset)
2369 return chip->info->ops->reset(chip);
2370
2371 return 0;
2372}
2373
309eca6d
VD		 2374static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2375{
2376 struct gpio_desc *gpiod = chip->reset;
2377
2378 /* If there is a GPIO connected to the reset pin, toggle it */
2379 if (gpiod) {
2380 gpiod_set_value_cansleep(gpiod, 1);
2381 usleep_range(10000, 20000);
2382 gpiod_set_value_cansleep(gpiod, 0);
2383 usleep_range(10000, 20000);
2384 }
2385}
2386
4ac4b5a6 2387static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2388{
4ac4b5a6 2389 int i, err;
552238b5 2390
4ac4b5a6 2391 /* Set all ports to the Disabled state */
370b4ffb 2392 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2393 err = mv88e6xxx_port_set_state(chip, i,
2394 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2395 if (err)
2396 return err;
552238b5
VD		 2397 }
2398
4ac4b5a6
VD		 2399 /* Wait for transmit queues to drain,
2400 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2401 */
552238b5
VD		 2402 usleep_range(2000, 4000);
2403
4ac4b5a6
VD		 2404 return 0;
2405}
2406
2407static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2408{
4ac4b5a6
VD		 2409 int err;
2410
2411 err = mv88e6xxx_disable_ports(chip);
2412 if (err)
2413 return err;
2414
309eca6d 2415 mv88e6xxx_hardware_reset(chip);
552238b5 2416
17e708ba 2417 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2418}
2419
09cb7dfd 2420static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2421{
09cb7dfd
VD		 2422 u16 val;
2423 int err;
13a7ebb3 2424
09cb7dfd
VD		 2425 /* Clear Power Down bit */
2426 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2427 if (err)
2428 return err;
13a7ebb3 2429
09cb7dfd
VD		 2430 if (val & BMCR_PDOWN) {
2431 val &= ~BMCR_PDOWN;
2432 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2433 }
2434
09cb7dfd 2435 return err;
13a7ebb3
PU		 2436}
2437
56995cbc
AL		 2438static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2439 int upstream_port)
2440{
2441 int err;
2442
2443 err = chip->info->ops->port_set_frame_mode(
2444 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2445 if (err)
2446 return err;
2447
2448 return chip->info->ops->port_set_egress_unknowns(
2449 chip, port, port == upstream_port);
2450}
2451
2452static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2453{
2454 int err;
2455
2456 switch (chip->info->tag_protocol) {
2457 case DSA_TAG_PROTO_EDSA:
2458 err = chip->info->ops->port_set_frame_mode(
2459 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2460 if (err)
2461 return err;
2462
2463 err = mv88e6xxx_port_set_egress_mode(
2464 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2465 if (err)
2466 return err;
2467
2468 if (chip->info->ops->port_set_ether_type)
2469 err = chip->info->ops->port_set_ether_type(
2470 chip, port, ETH_P_EDSA);
2471 break;
2472
2473 case DSA_TAG_PROTO_DSA:
2474 err = chip->info->ops->port_set_frame_mode(
2475 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2476 if (err)
2477 return err;
2478
2479 err = mv88e6xxx_port_set_egress_mode(
2480 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2481 break;
2482 default:
2483 err = -EINVAL;
2484 }
2485
2486 if (err)
2487 return err;
2488
2489 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2490}
2491
2492static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2493{
2494 int err;
2495
2496 err = chip->info->ops->port_set_frame_mode(
2497 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2498 if (err)
2499 return err;
2500
2501 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2502}
2503
fad09c73 2504static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2505{
fad09c73 2506 struct dsa_switch *ds = chip->ds;
0e7b9925 2507 int err;
54d792f2 2508 u16 reg;
d827e88a 2509
d78343d2
VD		 2510 /* MAC Forcing register: don't force link, speed, duplex or flow control
2511 * state to any particular values on physical ports, but force the CPU
2512 * port and all DSA ports to their maximum bandwidth and full duplex.
2513 */
2514 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2515 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2516 SPEED_MAX, DUPLEX_FULL,
2517 PHY_INTERFACE_MODE_NA);
2518 else
2519 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2520 SPEED_UNFORCED, DUPLEX_UNFORCED,
2521 PHY_INTERFACE_MODE_NA);
2522 if (err)
2523 return err;
54d792f2
AL		 2524
2525 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2526 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2527 * tunneling, determine priority by looking at 802.1p and IP
2528 * priority fields (IP prio has precedence), and set STP state
2529 * to Forwarding.
2530 *
2531 * If this is the CPU link, use DSA or EDSA tagging depending
2532 * on which tagging mode was configured.
2533 *
2534 * If this is a link to another switch, use DSA tagging mode.
2535 *
2536 * If this is the upstream port for this switch, enable
2537 * forwarding of unknown unicasts and multicasts.
2538 */
56995cbc 2539 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2540 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2541 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2542 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2543 if (err)
2544 return err;
6083ce71 2545
56995cbc
AL		 2546 if (dsa_is_cpu_port(ds, port)) {
2547 err = mv88e6xxx_setup_port_cpu(chip, port);
2548 } else if (dsa_is_dsa_port(ds, port)) {
2549 err = mv88e6xxx_setup_port_dsa(chip, port,
2550 dsa_upstream_port(ds));
2551 } else {
2552 err = mv88e6xxx_setup_port_normal(chip, port);
54d792f2 2553 }
56995cbc
AL		 2554 if (err)
2555 return err;
54d792f2 2556
13a7ebb3
PU		 2557 /* If this port is connected to a SerDes, make sure the SerDes is not
2558 * powered down.
2559 */
09cb7dfd 2560 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2561 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2562 if (err)
2563 return err;
2564 reg &= PORT_STATUS_CMODE_MASK;
2565 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2566 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2567 (reg == PORT_STATUS_CMODE_SGMII)) {
2568 err = mv88e6xxx_serdes_power_on(chip);
2569 if (err < 0)
2570 return err;
13a7ebb3
PU		 2571 }
2572 }
2573
8efdda4a 2574 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2575 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2576 * untagged frames on this port, do a destination address lookup on all
2577 * received packets as usual, disable ARP mirroring and don't send a
2578 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2579 */
2580 reg = 0;
fad09c73
VD		 2581 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2582 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2583 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2584 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2585 reg = PORT_CONTROL_2_MAP_DA;
2586
fad09c73 2587 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2588 /* Set the upstream port this port should use */
2589 reg |= dsa_upstream_port(ds);
2590 /* enable forwarding of unknown multicast addresses to
2591 * the upstream port
2592 */
2593 if (port == dsa_upstream_port(ds))
2594 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2595 }
2596
46fbe5e5 2597 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2598
54d792f2 2599 if (reg) {
0e7b9925
AL		 2600 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2601 if (err)
2602 return err;
54d792f2
AL		 2603 }
2604
5f436666
AL		 2605 if (chip->info->ops->port_jumbo_config) {
2606 err = chip->info->ops->port_jumbo_config(chip, port);
2607 if (err)
2608 return err;
2609 }
2610
54d792f2
AL		 2611 /* Port Association Vector: when learning source addresses
2612 * of packets, add the address to the address database using
2613 * a port bitmap that has only the bit for this port set and
2614 * the other bits clear.
2615 */
4c7ea3c0 2616 reg = 1 << port;
996ecb82
VD		 2617 /* Disable learning for CPU port */
2618 if (dsa_is_cpu_port(ds, port))
65fa4027 2619 reg = 0;
4c7ea3c0 2620
0e7b9925
AL		 2621 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2622 if (err)
2623 return err;
54d792f2
AL		 2624
2625 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2626 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2627 if (err)
2628 return err;
54d792f2 2629
b35d322a
AL		 2630 if (chip->info->ops->port_pause_config) {
2631 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2632 if (err)
2633 return err;
b35d322a 2634 }
54d792f2 2635
b35d322a
AL		 2636 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2637 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2638 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2639 /* Port ATU control: disable limiting the number of
2640 * address database entries that this port is allowed
2641 * to use.
2642 */
0e7b9925
AL		 2643 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2644 0x0000);
54d792f2
AL		 2645 /* Priority Override: disable DA, SA and VTU priority
2646 * override.
2647 */
0e7b9925
AL		 2648 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2649 0x0000);
2650 if (err)
2651 return err;
ef0a7318 2652 }
2bbb33be 2653
ef0a7318
AL		 2654 if (chip->info->ops->port_tag_remap) {
2655 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2656 if (err)
2657 return err;
54d792f2
AL		 2658 }
2659
ef70b111
AL		 2660 if (chip->info->ops->port_egress_rate_limiting) {
2661 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2662 if (err)
2663 return err;
54d792f2
AL		 2664 }
2665
366f0a0f
GR		 2666 /* Port Control 1: disable trunking, disable sending
2667 * learning messages to this port.
d827e88a 2668 */
0e7b9925
AL		 2669 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2670 if (err)
2671 return err;
d827e88a 2672
207afda1 2673 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2674 * database, and allow bidirectional communication between the
2675 * CPU and DSA port(s), and the other ports.
d827e88a 2676 */
b4e48c50 2677 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2678 if (err)
2679 return err;
2db9ce1f 2680
0e7b9925
AL		 2681 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2682 if (err)
2683 return err;
d827e88a
GR		 2684
2685 /* Default VLAN ID and priority: don't set a default VLAN
2686 * ID, and set the default packet priority to zero.
2687 */
0e7b9925 2688 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2689}
2690
aa0938c6 2691static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2692{
2693 int err;
2694
a935c052 2695 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2696 if (err)
2697 return err;
2698
a935c052 2699 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2700 if (err)
2701 return err;
2702
a935c052
VD		 2703 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2704 if (err)
2705 return err;
2706
2707 return 0;
3b4caa1b
VD		 2708}
2709
acddbd21
VD		 2710static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2711 unsigned int msecs)
2712{
2713 const unsigned int coeff = chip->info->age_time_coeff;
2714 const unsigned int min = 0x01 * coeff;
2715 const unsigned int max = 0xff * coeff;
2716 u8 age_time;
2717 u16 val;
2718 int err;
2719
2720 if (msecs < min || msecs > max)
2721 return -ERANGE;
2722
2723 /* Round to nearest multiple of coeff */
2724 age_time = (msecs + coeff / 2) / coeff;
2725
a935c052 2726 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2727 if (err)
2728 return err;
2729
2730 /* AgeTime is 11:4 bits */
2731 val &= ~0xff0;
2732 val |= age_time << 4;
2733
a935c052 2734 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2735}
2736
2cfcd964
VD		 2737static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2738 unsigned int ageing_time)
2739{
04bed143 2740 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2741 int err;
2742
2743 mutex_lock(&chip->reg_lock);
2744 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2745 mutex_unlock(&chip->reg_lock);
2746
2747 return err;
2748}
2749
9729934c 2750static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2751{
fad09c73 2752 struct dsa_switch *ds = chip->ds;
b0745e87 2753 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2754 int err;
54d792f2 2755
119477bd
VD		 2756 /* Enable the PHY Polling Unit if present, don't discard any packets,
2757 * and mask all interrupt sources.
2758 */
a199d8b6 2759 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2760 if (err)
2761 return err;
2762
33641994
AL		 2763 if (chip->info->ops->g1_set_cpu_port) {
2764 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2765 if (err)
2766 return err;
2767 }
2768
2769 if (chip->info->ops->g1_set_egress_port) {
2770 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2771 if (err)
2772 return err;
2773 }
b0745e87 2774
50484ff4 2775 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2776 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2777 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2778 (ds->index & 0x1f));
50484ff4
VD		 2779 if (err)
2780 return err;
2781
acddbd21
VD		 2782 /* Clear all the VTU and STU entries */
2783 err = _mv88e6xxx_vtu_stu_flush(chip);
2784 if (err < 0)
2785 return err;
2786
54d792f2
AL		 2787 /* Set the default address aging time to 5 minutes, and
2788 * enable address learn messages to be sent to all message
2789 * ports.
2790 */
a935c052
VD		 2791 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2792 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2793 if (err)
08a01261 2794 return err;
54d792f2 2795
acddbd21
VD		 2796 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2797 if (err)
9729934c
VD		 2798 return err;
2799
2800 /* Clear all ATU entries */
2801 err = _mv88e6xxx_atu_flush(chip, 0, true);
2802 if (err)
2803 return err;
2804
54d792f2 2805 /* Configure the IP ToS mapping registers. */
a935c052 2806 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2807 if (err)
08a01261 2808 return err;
a935c052 2809 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2810 if (err)
08a01261 2811 return err;
a935c052 2812 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2813 if (err)
08a01261 2814 return err;
a935c052 2815 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2816 if (err)
08a01261 2817 return err;
a935c052 2818 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2819 if (err)
08a01261 2820 return err;
a935c052 2821 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2822 if (err)
08a01261 2823 return err;
a935c052 2824 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2825 if (err)
08a01261 2826 return err;
a935c052 2827 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2828 if (err)
08a01261 2829 return err;
54d792f2
AL		 2830
2831 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2832 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2833 if (err)
08a01261 2834 return err;
54d792f2 2835
de227387
AL		 2836 /* Initialize the statistics unit */
2837 err = mv88e6xxx_stats_set_histogram(chip);
2838 if (err)
2839 return err;
2840
9729934c 2841 /* Clear the statistics counters for all ports */
a935c052
VD		 2842 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2843 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2844 if (err)
2845 return err;
2846
2847 /* Wait for the flush to complete. */
7f9ef3af 2848 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2849 if (err)
2850 return err;
2851
2852 return 0;
2853}
2854
f81ec90f 2855static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2856{
04bed143 2857 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2858 int err;
a1a6a4d1
VD		 2859 int i;
2860
fad09c73 2861 chip->ds = ds;
a3c53be5 2862 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2863
fad09c73 2864 mutex_lock(&chip->reg_lock);
08a01261 2865
9729934c 2866 /* Setup Switch Port Registers */
370b4ffb 2867 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2868 err = mv88e6xxx_setup_port(chip, i);
2869 if (err)
2870 goto unlock;
2871 }
2872
2873 /* Setup Switch Global 1 Registers */
2874 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2875 if (err)
2876 goto unlock;
2877
9729934c
VD		 2878 /* Setup Switch Global 2 Registers */
2879 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2880 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2881 if (err)
2882 goto unlock;
2883 }
08a01261 2884
6e55f698
AL		 2885 /* Some generations have the configuration of sending reserved
2886 * management frames to the CPU in global2, others in
2887 * global1. Hence it does not fit the two setup functions
2888 * above.
2889 */
2890 if (chip->info->ops->mgmt_rsvd2cpu) {
2891 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2892 if (err)
2893 goto unlock;
2894 }
2895
6b17e864 2896unlock:
fad09c73 2897 mutex_unlock(&chip->reg_lock);
db687a56 2898
48ace4ef 2899 return err;
54d792f2
AL		 2900}
2901
3b4caa1b
VD		 2902static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2903{
04bed143 2904 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2905 int err;
2906
b073d4e2
VD		 2907 if (!chip->info->ops->set_switch_mac)
2908 return -EOPNOTSUPP;
3b4caa1b 2909
b073d4e2
VD		 2910 mutex_lock(&chip->reg_lock);
2911 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2912 mutex_unlock(&chip->reg_lock);
2913
2914 return err;
2915}
2916
e57e5e77 2917static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2918{
0dd12d54
AL		 2919 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2920 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2921 u16 val;
2922 int err;
fd3a0ee4 2923
370b4ffb 2924 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2925 return 0xffff;
fd3a0ee4 2926
ee26a228
AL		 2927 if (!chip->info->ops->phy_read)
2928 return -EOPNOTSUPP;
2929
fad09c73 2930 mutex_lock(&chip->reg_lock);
ee26a228 2931 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2932 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2933
2934 return err ? err : val;
fd3a0ee4
AL		 2935}
2936
e57e5e77 2937static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2938{
0dd12d54
AL		 2939 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2940 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2941 int err;
fd3a0ee4 2942
370b4ffb 2943 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2944 return 0xffff;
fd3a0ee4 2945
ee26a228
AL		 2946 if (!chip->info->ops->phy_write)
2947 return -EOPNOTSUPP;
2948
fad09c73 2949 mutex_lock(&chip->reg_lock);
ee26a228 2950 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2951 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2952
2953 return err;
fd3a0ee4
AL		 2954}
2955
fad09c73 2956static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2957 struct device_node *np,
2958 bool external)
b516d453
AL		 2959{
2960 static int index;
0dd12d54 2961 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2962 struct mii_bus *bus;
2963 int err;
2964
0dd12d54 2965 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2966 if (!bus)
2967 return -ENOMEM;
2968
0dd12d54 2969 mdio_bus = bus->priv;
a3c53be5 2970 mdio_bus->bus = bus;
0dd12d54 2971 mdio_bus->chip = chip;
a3c53be5
AL		 2972 INIT_LIST_HEAD(&mdio_bus->list);
2973 mdio_bus->external = external;
0dd12d54 2974
b516d453
AL		 2975 if (np) {
2976 bus->name = np->full_name;
2977 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2978 } else {
2979 bus->name = "mv88e6xxx SMI";
2980 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2981 }
2982
2983 bus->read = mv88e6xxx_mdio_read;
2984 bus->write = mv88e6xxx_mdio_write;
fad09c73 2985 bus->parent = chip->dev;
b516d453 2986
a3c53be5
AL		 2987 if (np)
2988 err = of_mdiobus_register(bus, np);
b516d453
AL		 2989 else
2990 err = mdiobus_register(bus);
2991 if (err) {
fad09c73 2992 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2993 return err;
b516d453 2994 }
a3c53be5
AL		 2995
2996 if (external)
2997 list_add_tail(&mdio_bus->list, &chip->mdios);
2998 else
2999 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 3000
3001 return 0;
a3c53be5 3002}
b516d453 3003
a3c53be5
AL		 3004static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
3005 { .compatible = "marvell,mv88e6xxx-mdio-external",
3006 .data = (void *)true },
3007 { },
3008};
b516d453 3009
a3c53be5
AL		 3010static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3011 struct device_node *np)
3012{
3013 const struct of_device_id *match;
3014 struct device_node *child;
3015 int err;
3016
3017 /* Always register one mdio bus for the internal/default mdio
3018 * bus. This maybe represented in the device tree, but is
3019 * optional.
3020 */
3021 child = of_get_child_by_name(np, "mdio");
3022 err = mv88e6xxx_mdio_register(chip, child, false);
3023 if (err)
3024 return err;
3025
3026 /* Walk the device tree, and see if there are any other nodes
3027 * which say they are compatible with the external mdio
3028 * bus.
3029 */
3030 for_each_available_child_of_node(np, child) {
3031 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3032 if (match) {
3033 err = mv88e6xxx_mdio_register(chip, child, true);
3034 if (err)
3035 return err;
3036 }
3037 }
3038
3039 return 0;
b516d453
AL		 3040}
3041
a3c53be5 3042static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3043
3044{
a3c53be5
AL		 3045 struct mv88e6xxx_mdio_bus *mdio_bus;
3046 struct mii_bus *bus;
b516d453 3047
a3c53be5
AL		 3048 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3049 bus = mdio_bus->bus;
b516d453 3050
a3c53be5
AL		 3051 mdiobus_unregister(bus);
3052 }
b516d453
AL		 3053}
3054
855b1932
VD		 3055static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3056{
04bed143 3057 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3058
3059 return chip->eeprom_len;
3060}
3061
855b1932
VD		 3062static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3063 struct ethtool_eeprom *eeprom, u8 *data)
3064{
04bed143 3065 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3066 int err;
3067
ee4dc2e7
VD		 3068 if (!chip->info->ops->get_eeprom)
3069 return -EOPNOTSUPP;
855b1932 3070
ee4dc2e7
VD		 3071 mutex_lock(&chip->reg_lock);
3072 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3073 mutex_unlock(&chip->reg_lock);
3074
3075 if (err)
3076 return err;
3077
3078 eeprom->magic = 0xc3ec4951;
3079
3080 return 0;
3081}
3082
855b1932
VD		 3083static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3084 struct ethtool_eeprom *eeprom, u8 *data)
3085{
04bed143 3086 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3087 int err;
3088
ee4dc2e7
VD		 3089 if (!chip->info->ops->set_eeprom)
3090 return -EOPNOTSUPP;
3091
855b1932
VD		 3092 if (eeprom->magic != 0xc3ec4951)
3093 return -EINVAL;
3094
3095 mutex_lock(&chip->reg_lock);
ee4dc2e7 3096 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3097 mutex_unlock(&chip->reg_lock);
3098
3099 return err;
3100}
3101
b3469dd8 3102static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3103 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3104 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3105 .phy_read = mv88e6xxx_phy_ppu_read,
3106 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3107 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3108 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3109 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3110 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3111 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3112 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3113 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3114 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3115 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3116 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3117 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3118 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3119 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3120 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3121 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3122 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3123 .ppu_enable = mv88e6185_g1_ppu_enable,
3124 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3125 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3126};
3127
3128static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3129 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3130 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3131 .phy_read = mv88e6xxx_phy_ppu_read,
3132 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3133 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3134 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3135 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3136 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3137 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3138 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3139 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3140 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3141 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 3142 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3143 .ppu_enable = mv88e6185_g1_ppu_enable,
3144 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3145 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3146};
3147
7d381a02 3148static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3149 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 3150 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3151 .phy_read = mv88e6xxx_g2_smi_phy_read,
3152 .phy_write = mv88e6xxx_g2_smi_phy_write,
3153 .port_set_link = mv88e6xxx_port_set_link,
3154 .port_set_duplex = mv88e6xxx_port_set_duplex,
3155 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3156 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3157 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3158 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3159 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3160 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3161 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 3162 .port_pause_config = mv88e6097_port_pause_config,
7d381a02
SE		 3163 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3164 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3165 .stats_get_strings = mv88e6095_stats_get_strings,
3166 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3167 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3168 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3169 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3170 .reset = mv88e6352_g1_reset,
7d381a02
SE		 3171};
3172
b3469dd8 3173static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3174 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3175 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3176 .phy_read = mv88e6165_phy_read,
3177 .phy_write = mv88e6165_phy_write,
08ef7f10 3178 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3179 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3180 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3181 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3182 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3183 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3184 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3185 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3186 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3187 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3188 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3189 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3190 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3191};
3192
3193static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3194 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3195 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3196 .phy_read = mv88e6xxx_phy_ppu_read,
3197 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3198 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3199 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3200 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3201 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3202 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3203 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3204 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3205 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3206 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3207 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3208 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3209 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3210 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3211 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3212 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3213 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3214 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3215 .ppu_enable = mv88e6185_g1_ppu_enable,
3216 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3217 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3218};
3219
3220static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3221 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3222 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3223 .phy_read = mv88e6165_phy_read,
3224 .phy_write = mv88e6165_phy_write,
08ef7f10 3225 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3226 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3227 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3228 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3229 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3230 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3231 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3232 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3233 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3234 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3235 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3236 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3237 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3238 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3239 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3240 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3241 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3242 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3243};
3244
3245static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3246 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3247 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3248 .phy_read = mv88e6165_phy_read,
3249 .phy_write = mv88e6165_phy_write,
08ef7f10 3250 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3251 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3252 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3253 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3254 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3255 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3256 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3257 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3258 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3259 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3260 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3261};
3262
3263static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3264 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3266 .phy_read = mv88e6xxx_g2_smi_phy_read,
3267 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3268 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3269 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3270 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3271 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3272 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3273 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3274 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3275 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3276 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3277 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3278 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3279 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3280 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3281 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3282 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3283 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3284 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3285 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3286 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3287};
3288
3289static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3290 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3291 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3292 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3293 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3294 .phy_read = mv88e6xxx_g2_smi_phy_read,
3295 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3296 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3297 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3298 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3299 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3300 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3301 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3302 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3303 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3304 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3305 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3306 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3307 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3308 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3309 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3310 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3311 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3312 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3313 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3314 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3315};
3316
3317static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3318 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3319 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3320 .phy_read = mv88e6xxx_g2_smi_phy_read,
3321 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3322 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3323 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3324 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3325 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3326 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3327 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3328 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3329 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3330 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3331 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3332 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3333 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3334 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3335 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3336 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3337 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3338 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3339 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3340 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3341};
3342
3343static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3344 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3345 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3346 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3347 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3348 .phy_read = mv88e6xxx_g2_smi_phy_read,
3349 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3350 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3351 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3352 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3353 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3354 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3355 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3356 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3357 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3358 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3359 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3360 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3361 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3362 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3363 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3364 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3365 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3366 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3367 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3368 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3369};
3370
3371static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3372 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3373 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3374 .phy_read = mv88e6xxx_phy_ppu_read,
3375 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3376 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3377 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3378 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3379 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3380 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
ef70b111 3381 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a605a0fe 3382 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3383 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3384 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3385 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3386 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3387 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3388 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3389 .ppu_enable = mv88e6185_g1_ppu_enable,
3390 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3391 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3392};
3393
1a3b39ec 3394static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3395 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3396 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3397 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3398 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3399 .phy_read = mv88e6xxx_g2_smi_phy_read,
3400 .phy_write = mv88e6xxx_g2_smi_phy_write,
3401 .port_set_link = mv88e6xxx_port_set_link,
3402 .port_set_duplex = mv88e6xxx_port_set_duplex,
3403 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3404 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3405 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3406 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3407 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3408 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3409 .port_pause_config = mv88e6390_port_pause_config,
79523473 3410 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3411 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3412 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3413 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3414 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3415 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3416 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3417 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3418 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3419};
3420
3421static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3422 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3423 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3424 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3425 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3426 .phy_read = mv88e6xxx_g2_smi_phy_read,
3427 .phy_write = mv88e6xxx_g2_smi_phy_write,
3428 .port_set_link = mv88e6xxx_port_set_link,
3429 .port_set_duplex = mv88e6xxx_port_set_duplex,
3430 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3431 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3432 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3433 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3434 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3435 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3436 .port_pause_config = mv88e6390_port_pause_config,
79523473 3437 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3438 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3439 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3440 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3441 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3442 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3443 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3444 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3445 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3446};
3447
3448static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3449 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3450 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3451 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3452 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3453 .phy_read = mv88e6xxx_g2_smi_phy_read,
3454 .phy_write = mv88e6xxx_g2_smi_phy_write,
3455 .port_set_link = mv88e6xxx_port_set_link,
3456 .port_set_duplex = mv88e6xxx_port_set_duplex,
3457 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3458 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3459 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3460 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3461 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3462 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3463 .port_pause_config = mv88e6390_port_pause_config,
79523473 3464 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3465 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3466 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3467 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3468 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3469 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3470 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3471 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3472 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3473};
3474
b3469dd8 3475static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3476 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3477 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3478 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3479 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3480 .phy_read = mv88e6xxx_g2_smi_phy_read,
3481 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3482 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3483 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3484 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3485 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3486 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3487 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3488 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3489 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3490 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3492 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3493 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3494 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3495 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3496 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3497 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3498 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3499 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3500 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3501};
3502
1a3b39ec 3503static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3504 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3505 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3506 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3508 .phy_read = mv88e6xxx_g2_smi_phy_read,
3509 .phy_write = mv88e6xxx_g2_smi_phy_write,
3510 .port_set_link = mv88e6xxx_port_set_link,
3511 .port_set_duplex = mv88e6xxx_port_set_duplex,
3512 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3513 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3514 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3515 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3516 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3517 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3518 .port_pause_config = mv88e6390_port_pause_config,
79523473 3519 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3520 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3521 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3522 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3523 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3524 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3525 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3526 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3527 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3528};
3529
b3469dd8 3530static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3531 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3532 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3533 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3534 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3535 .phy_read = mv88e6xxx_g2_smi_phy_read,
3536 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3537 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3538 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3539 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3540 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3542 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3543 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3544 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3545 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3546 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3547 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3548 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3549 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3550 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3551 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3552 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3553 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3554 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3555};
3556
3557static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3558 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3559 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3560 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3561 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3562 .phy_read = mv88e6xxx_g2_smi_phy_read,
3563 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3564 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3565 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3566 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3567 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3568 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3569 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3570 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3571 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3572 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3573 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3574 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3575 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3576 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3577 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3578 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3579 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3580 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3581};
3582
3583static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3584 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3585 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3586 .phy_read = mv88e6xxx_g2_smi_phy_read,
3587 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3588 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3589 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3590 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3591 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3592 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3593 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3594 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3595 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3596 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3598 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3599 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3600 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3601 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3602 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3603 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3604 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3605 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3606 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3607};
3608
3609static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3610 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3611 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3612 .phy_read = mv88e6xxx_g2_smi_phy_read,
3613 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3614 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3615 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3616 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3617 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3618 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3619 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3620 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3621 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3622 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3623 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3624 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3625 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3626 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3627 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3628 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3629 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3630 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3631 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3632 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3633};
3634
3635static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3636 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3637 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3638 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3639 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3640 .phy_read = mv88e6xxx_g2_smi_phy_read,
3641 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3642 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3643 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3644 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3645 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3646 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3647 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3648 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3649 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3650 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3651 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3652 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3653 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3654 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3655 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3656 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3657 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3658 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3659 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3660 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3661};
3662
1a3b39ec 3663static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3664 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3665 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3666 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3667 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3668 .phy_read = mv88e6xxx_g2_smi_phy_read,
3669 .phy_write = mv88e6xxx_g2_smi_phy_write,
3670 .port_set_link = mv88e6xxx_port_set_link,
3671 .port_set_duplex = mv88e6xxx_port_set_duplex,
3672 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3673 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3674 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3675 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3676 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3677 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3678 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3679 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3680 .port_pause_config = mv88e6390_port_pause_config,
79523473 3681 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3682 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3683 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3684 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3685 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3686 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3687 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3688 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3689 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3690};
3691
3692static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3693 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3694 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3695 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3696 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3697 .phy_read = mv88e6xxx_g2_smi_phy_read,
3698 .phy_write = mv88e6xxx_g2_smi_phy_write,
3699 .port_set_link = mv88e6xxx_port_set_link,
3700 .port_set_duplex = mv88e6xxx_port_set_duplex,
3701 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3702 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3703 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3704 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3705 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3706 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3707 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3708 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3709 .port_pause_config = mv88e6390_port_pause_config,
79523473 3710 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3711 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3712 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3713 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3714 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3715 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3716 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3717 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3718 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3719};
3720
3721static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3722 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3723 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3724 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3725 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3726 .phy_read = mv88e6xxx_g2_smi_phy_read,
3727 .phy_write = mv88e6xxx_g2_smi_phy_write,
3728 .port_set_link = mv88e6xxx_port_set_link,
3729 .port_set_duplex = mv88e6xxx_port_set_duplex,
3730 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3731 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3732 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3733 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3734 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3735 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3736 .port_pause_config = mv88e6390_port_pause_config,
79523473 3737 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3738 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3739 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3740 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3741 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3742 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3743 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3744 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3745 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3746};
3747
56995cbc
AL		 3748static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3749 const struct mv88e6xxx_ops *ops)
3750{
3751 if (!ops->port_set_frame_mode) {
3752 dev_err(chip->dev, "Missing port_set_frame_mode");
3753 return -EINVAL;
3754 }
3755
3756 if (!ops->port_set_egress_unknowns) {
3757 dev_err(chip->dev, "Missing port_set_egress_mode");
3758 return -EINVAL;
3759 }
3760
3761 return 0;
3762}
3763
f81ec90f
VD		 3764static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3765 [MV88E6085] = {
3766 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3767 .family = MV88E6XXX_FAMILY_6097,
3768 .name = "Marvell 88E6085",
3769 .num_databases = 4096,
3770 .num_ports = 10,
9dddd478 3771 .port_base_addr = 0x10,
a935c052 3772 .global1_addr = 0x1b,
acddbd21 3773 .age_time_coeff = 15000,
dc30c35b 3774 .g1_irqs = 8,
443d5a1b 3775 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3776 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3777 .ops = &mv88e6085_ops,
f81ec90f
VD		 3778 },
3779
3780 [MV88E6095] = {
3781 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3782 .family = MV88E6XXX_FAMILY_6095,
3783 .name = "Marvell 88E6095/88E6095F",
3784 .num_databases = 256,
3785 .num_ports = 11,
9dddd478 3786 .port_base_addr = 0x10,
a935c052 3787 .global1_addr = 0x1b,
acddbd21 3788 .age_time_coeff = 15000,
dc30c35b 3789 .g1_irqs = 8,
443d5a1b 3790 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3791 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3792 .ops = &mv88e6095_ops,
f81ec90f
VD		 3793 },
3794
7d381a02
SE		 3795 [MV88E6097] = {
3796 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3797 .family = MV88E6XXX_FAMILY_6097,
3798 .name = "Marvell 88E6097/88E6097F",
3799 .num_databases = 4096,
3800 .num_ports = 11,
3801 .port_base_addr = 0x10,
3802 .global1_addr = 0x1b,
3803 .age_time_coeff = 15000,
c534178b 3804 .g1_irqs = 8,
2bfcfcd3 3805 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3806 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3807 .ops = &mv88e6097_ops,
3808 },
3809
f81ec90f
VD		 3810 [MV88E6123] = {
3811 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3812 .family = MV88E6XXX_FAMILY_6165,
3813 .name = "Marvell 88E6123",
3814 .num_databases = 4096,
3815 .num_ports = 3,
9dddd478 3816 .port_base_addr = 0x10,
a935c052 3817 .global1_addr = 0x1b,
acddbd21 3818 .age_time_coeff = 15000,
dc30c35b 3819 .g1_irqs = 9,
443d5a1b 3820 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3821 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3822 .ops = &mv88e6123_ops,
f81ec90f
VD		 3823 },
3824
3825 [MV88E6131] = {
3826 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3827 .family = MV88E6XXX_FAMILY_6185,
3828 .name = "Marvell 88E6131",
3829 .num_databases = 256,
3830 .num_ports = 8,
9dddd478 3831 .port_base_addr = 0x10,
a935c052 3832 .global1_addr = 0x1b,
acddbd21 3833 .age_time_coeff = 15000,
dc30c35b 3834 .g1_irqs = 9,
443d5a1b 3835 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3836 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3837 .ops = &mv88e6131_ops,
f81ec90f
VD		 3838 },
3839
3840 [MV88E6161] = {
3841 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3842 .family = MV88E6XXX_FAMILY_6165,
3843 .name = "Marvell 88E6161",
3844 .num_databases = 4096,
3845 .num_ports = 6,
9dddd478 3846 .port_base_addr = 0x10,
a935c052 3847 .global1_addr = 0x1b,
acddbd21 3848 .age_time_coeff = 15000,
dc30c35b 3849 .g1_irqs = 9,
443d5a1b 3850 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3851 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3852 .ops = &mv88e6161_ops,
f81ec90f
VD		 3853 },
3854
3855 [MV88E6165] = {
3856 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3857 .family = MV88E6XXX_FAMILY_6165,
3858 .name = "Marvell 88E6165",
3859 .num_databases = 4096,
3860 .num_ports = 6,
9dddd478 3861 .port_base_addr = 0x10,
a935c052 3862 .global1_addr = 0x1b,
acddbd21 3863 .age_time_coeff = 15000,
dc30c35b 3864 .g1_irqs = 9,
443d5a1b 3865 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3866 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3867 .ops = &mv88e6165_ops,
f81ec90f
VD		 3868 },
3869
3870 [MV88E6171] = {
3871 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3872 .family = MV88E6XXX_FAMILY_6351,
3873 .name = "Marvell 88E6171",
3874 .num_databases = 4096,
3875 .num_ports = 7,
9dddd478 3876 .port_base_addr = 0x10,
a935c052 3877 .global1_addr = 0x1b,
acddbd21 3878 .age_time_coeff = 15000,
dc30c35b 3879 .g1_irqs = 9,
443d5a1b 3880 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3881 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3882 .ops = &mv88e6171_ops,
f81ec90f
VD		 3883 },
3884
3885 [MV88E6172] = {
3886 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3887 .family = MV88E6XXX_FAMILY_6352,
3888 .name = "Marvell 88E6172",
3889 .num_databases = 4096,
3890 .num_ports = 7,
9dddd478 3891 .port_base_addr = 0x10,
a935c052 3892 .global1_addr = 0x1b,
acddbd21 3893 .age_time_coeff = 15000,
dc30c35b 3894 .g1_irqs = 9,
443d5a1b 3895 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3896 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3897 .ops = &mv88e6172_ops,
f81ec90f
VD		 3898 },
3899
3900 [MV88E6175] = {
3901 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3902 .family = MV88E6XXX_FAMILY_6351,
3903 .name = "Marvell 88E6175",
3904 .num_databases = 4096,
3905 .num_ports = 7,
9dddd478 3906 .port_base_addr = 0x10,
a935c052 3907 .global1_addr = 0x1b,
acddbd21 3908 .age_time_coeff = 15000,
dc30c35b 3909 .g1_irqs = 9,
443d5a1b 3910 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3911 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3912 .ops = &mv88e6175_ops,
f81ec90f
VD		 3913 },
3914
3915 [MV88E6176] = {
3916 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3917 .family = MV88E6XXX_FAMILY_6352,
3918 .name = "Marvell 88E6176",
3919 .num_databases = 4096,
3920 .num_ports = 7,
9dddd478 3921 .port_base_addr = 0x10,
a935c052 3922 .global1_addr = 0x1b,
acddbd21 3923 .age_time_coeff = 15000,
dc30c35b 3924 .g1_irqs = 9,
443d5a1b 3925 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3926 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3927 .ops = &mv88e6176_ops,
f81ec90f
VD		 3928 },
3929
3930 [MV88E6185] = {
3931 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3932 .family = MV88E6XXX_FAMILY_6185,
3933 .name = "Marvell 88E6185",
3934 .num_databases = 256,
3935 .num_ports = 10,
9dddd478 3936 .port_base_addr = 0x10,
a935c052 3937 .global1_addr = 0x1b,
acddbd21 3938 .age_time_coeff = 15000,
dc30c35b 3939 .g1_irqs = 8,
443d5a1b 3940 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3941 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3942 .ops = &mv88e6185_ops,
f81ec90f
VD		 3943 },
3944
1a3b39ec
AL		 3945 [MV88E6190] = {
3946 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3947 .family = MV88E6XXX_FAMILY_6390,
3948 .name = "Marvell 88E6190",
3949 .num_databases = 4096,
3950 .num_ports = 11, /* 10 + Z80 */
3951 .port_base_addr = 0x0,
3952 .global1_addr = 0x1b,
443d5a1b 3953 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3954 .age_time_coeff = 15000,
3955 .g1_irqs = 9,
3956 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3957 .ops = &mv88e6190_ops,
3958 },
3959
3960 [MV88E6190X] = {
3961 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3962 .family = MV88E6XXX_FAMILY_6390,
3963 .name = "Marvell 88E6190X",
3964 .num_databases = 4096,
3965 .num_ports = 11, /* 10 + Z80 */
3966 .port_base_addr = 0x0,
3967 .global1_addr = 0x1b,
3968 .age_time_coeff = 15000,
3969 .g1_irqs = 9,
443d5a1b 3970 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3971 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3972 .ops = &mv88e6190x_ops,
3973 },
3974
3975 [MV88E6191] = {
3976 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3977 .family = MV88E6XXX_FAMILY_6390,
3978 .name = "Marvell 88E6191",
3979 .num_databases = 4096,
3980 .num_ports = 11, /* 10 + Z80 */
3981 .port_base_addr = 0x0,
3982 .global1_addr = 0x1b,
3983 .age_time_coeff = 15000,
443d5a1b
AL		 3984 .g1_irqs = 9,
3985 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3986 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3987 .ops = &mv88e6391_ops,
3988 },
3989
f81ec90f
VD		 3990 [MV88E6240] = {
3991 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3992 .family = MV88E6XXX_FAMILY_6352,
3993 .name = "Marvell 88E6240",
3994 .num_databases = 4096,
3995 .num_ports = 7,
9dddd478 3996 .port_base_addr = 0x10,
a935c052 3997 .global1_addr = 0x1b,
acddbd21 3998 .age_time_coeff = 15000,
dc30c35b 3999 .g1_irqs = 9,
443d5a1b 4000 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4001 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4002 .ops = &mv88e6240_ops,
f81ec90f
VD		 4003 },
4004
1a3b39ec
AL		 4005 [MV88E6290] = {
4006 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4007 .family = MV88E6XXX_FAMILY_6390,
4008 .name = "Marvell 88E6290",
4009 .num_databases = 4096,
4010 .num_ports = 11, /* 10 + Z80 */
4011 .port_base_addr = 0x0,
4012 .global1_addr = 0x1b,
4013 .age_time_coeff = 15000,
4014 .g1_irqs = 9,
443d5a1b 4015 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4016 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4017 .ops = &mv88e6290_ops,
4018 },
4019
f81ec90f
VD		 4020 [MV88E6320] = {
4021 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4022 .family = MV88E6XXX_FAMILY_6320,
4023 .name = "Marvell 88E6320",
4024 .num_databases = 4096,
4025 .num_ports = 7,
9dddd478 4026 .port_base_addr = 0x10,
a935c052 4027 .global1_addr = 0x1b,
acddbd21 4028 .age_time_coeff = 15000,
dc30c35b 4029 .g1_irqs = 8,
443d5a1b 4030 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4031 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4032 .ops = &mv88e6320_ops,
f81ec90f
VD		 4033 },
4034
4035 [MV88E6321] = {
4036 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4037 .family = MV88E6XXX_FAMILY_6320,
4038 .name = "Marvell 88E6321",
4039 .num_databases = 4096,
4040 .num_ports = 7,
9dddd478 4041 .port_base_addr = 0x10,
a935c052 4042 .global1_addr = 0x1b,
acddbd21 4043 .age_time_coeff = 15000,
dc30c35b 4044 .g1_irqs = 8,
443d5a1b 4045 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4046 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4047 .ops = &mv88e6321_ops,
f81ec90f
VD		 4048 },
4049
4050 [MV88E6350] = {
4051 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4052 .family = MV88E6XXX_FAMILY_6351,
4053 .name = "Marvell 88E6350",
4054 .num_databases = 4096,
4055 .num_ports = 7,
9dddd478 4056 .port_base_addr = 0x10,
a935c052 4057 .global1_addr = 0x1b,
acddbd21 4058 .age_time_coeff = 15000,
dc30c35b 4059 .g1_irqs = 9,
443d5a1b 4060 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4061 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4062 .ops = &mv88e6350_ops,
f81ec90f
VD		 4063 },
4064
4065 [MV88E6351] = {
4066 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4067 .family = MV88E6XXX_FAMILY_6351,
4068 .name = "Marvell 88E6351",
4069 .num_databases = 4096,
4070 .num_ports = 7,
9dddd478 4071 .port_base_addr = 0x10,
a935c052 4072 .global1_addr = 0x1b,
acddbd21 4073 .age_time_coeff = 15000,
dc30c35b 4074 .g1_irqs = 9,
443d5a1b 4075 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4076 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4077 .ops = &mv88e6351_ops,
f81ec90f
VD		 4078 },
4079
4080 [MV88E6352] = {
4081 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4082 .family = MV88E6XXX_FAMILY_6352,
4083 .name = "Marvell 88E6352",
4084 .num_databases = 4096,
4085 .num_ports = 7,
9dddd478 4086 .port_base_addr = 0x10,
a935c052 4087 .global1_addr = 0x1b,
acddbd21 4088 .age_time_coeff = 15000,
dc30c35b 4089 .g1_irqs = 9,
443d5a1b 4090 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4091 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4092 .ops = &mv88e6352_ops,
f81ec90f 4093 },
1a3b39ec
AL		 4094 [MV88E6390] = {
4095 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4096 .family = MV88E6XXX_FAMILY_6390,
4097 .name = "Marvell 88E6390",
4098 .num_databases = 4096,
4099 .num_ports = 11, /* 10 + Z80 */
4100 .port_base_addr = 0x0,
4101 .global1_addr = 0x1b,
4102 .age_time_coeff = 15000,
4103 .g1_irqs = 9,
443d5a1b 4104 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4105 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4106 .ops = &mv88e6390_ops,
4107 },
4108 [MV88E6390X] = {
4109 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4110 .family = MV88E6XXX_FAMILY_6390,
4111 .name = "Marvell 88E6390X",
4112 .num_databases = 4096,
4113 .num_ports = 11, /* 10 + Z80 */
4114 .port_base_addr = 0x0,
4115 .global1_addr = 0x1b,
4116 .age_time_coeff = 15000,
4117 .g1_irqs = 9,
443d5a1b 4118 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4119 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4120 .ops = &mv88e6390x_ops,
4121 },
f81ec90f
VD		 4122};
4123
5f7c0367 4124static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4125{
a439c061 4126 int i;
b9b37713 4127
5f7c0367
VD		 4128 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4129 if (mv88e6xxx_table[i].prod_num == prod_num)
4130 return &mv88e6xxx_table[i];
b9b37713 4131
b9b37713
VD		 4132 return NULL;
4133}
4134
fad09c73 4135static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4136{
4137 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4138 unsigned int prod_num, rev;
4139 u16 id;
4140 int err;
bc46a3d5 4141
8f6345b2
VD		 4142 mutex_lock(&chip->reg_lock);
4143 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4144 mutex_unlock(&chip->reg_lock);
4145 if (err)
4146 return err;
bc46a3d5
VD		 4147
4148 prod_num = (id & 0xfff0) >> 4;
4149 rev = id & 0x000f;
4150
4151 info = mv88e6xxx_lookup_info(prod_num);
4152 if (!info)
4153 return -ENODEV;
4154
caac8545 4155 /* Update the compatible info with the probed one */
fad09c73 4156 chip->info = info;
bc46a3d5 4157
ca070c10
VD		 4158 err = mv88e6xxx_g2_require(chip);
4159 if (err)
4160 return err;
4161
fad09c73
VD		 4162 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4163 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4164
4165 return 0;
4166}
4167
fad09c73 4168static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4169{
fad09c73 4170 struct mv88e6xxx_chip *chip;
469d729f 4171
fad09c73
VD		 4172 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4173 if (!chip)
469d729f
VD		 4174 return NULL;
4175
fad09c73 4176 chip->dev = dev;
469d729f 4177
fad09c73 4178 mutex_init(&chip->reg_lock);
a3c53be5 4179 INIT_LIST_HEAD(&chip->mdios);
469d729f 4180
fad09c73 4181 return chip;
469d729f
VD		 4182}
4183
e57e5e77
VD		 4184static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4185{
a199d8b6 4186 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4187 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4188}
4189
930188ce
AL		 4190static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4191{
a199d8b6 4192 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4193 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4194}
4195
fad09c73 4196static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4197 struct mii_bus *bus, int sw_addr)
4198{
914b32f6 4199 if (sw_addr == 0)
fad09c73 4200 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4201 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4202 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4203 else
4204 return -EINVAL;
4205
fad09c73
VD		 4206 chip->bus = bus;
4207 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4208
4209 return 0;
4210}
4211
7b314362
AL		 4212static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4213{
04bed143 4214 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4215
443d5a1b 4216 return chip->info->tag_protocol;
7b314362
AL		 4217}
4218
fcdce7d0
AL		 4219static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4220 struct device *host_dev, int sw_addr,
4221 void **priv)
a77d43f1 4222{
fad09c73 4223 struct mv88e6xxx_chip *chip;
a439c061 4224 struct mii_bus *bus;
b516d453 4225 int err;
a77d43f1 4226
a439c061 4227 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4228 if (!bus)
4229 return NULL;
4230
fad09c73
VD		 4231 chip = mv88e6xxx_alloc_chip(dsa_dev);
4232 if (!chip)
469d729f
VD		 4233 return NULL;
4234
caac8545 4235 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4236 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4237
fad09c73 4238 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4239 if (err)
4240 goto free;
4241
fad09c73 4242 err = mv88e6xxx_detect(chip);
bc46a3d5 4243 if (err)
469d729f 4244 goto free;
a439c061 4245
dc30c35b
AL		 4246 mutex_lock(&chip->reg_lock);
4247 err = mv88e6xxx_switch_reset(chip);
4248 mutex_unlock(&chip->reg_lock);
4249 if (err)
4250 goto free;
4251
e57e5e77
VD		 4252 mv88e6xxx_phy_init(chip);
4253
a3c53be5 4254 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4255 if (err)
469d729f 4256 goto free;
b516d453 4257
fad09c73 4258 *priv = chip;
a439c061 4259
fad09c73 4260 return chip->info->name;
469d729f 4261free:
fad09c73 4262 devm_kfree(dsa_dev, chip);
469d729f
VD		 4263
4264 return NULL;
a77d43f1
AL		 4265}
4266
7df8fbdd
VD		 4267static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4268 const struct switchdev_obj_port_mdb *mdb,
4269 struct switchdev_trans *trans)
4270{
4271 /* We don't need any dynamic resource from the kernel (yet),
4272 * so skip the prepare phase.
4273 */
4274
4275 return 0;
4276}
4277
4278static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4279 const struct switchdev_obj_port_mdb *mdb,
4280 struct switchdev_trans *trans)
4281{
04bed143 4282 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4283
4284 mutex_lock(&chip->reg_lock);
4285 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4286 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4287 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4288 mutex_unlock(&chip->reg_lock);
4289}
4290
4291static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4292 const struct switchdev_obj_port_mdb *mdb)
4293{
04bed143 4294 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4295 int err;
4296
4297 mutex_lock(&chip->reg_lock);
4298 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4299 GLOBAL_ATU_DATA_STATE_UNUSED);
4300 mutex_unlock(&chip->reg_lock);
4301
4302 return err;
4303}
4304
4305static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4306 struct switchdev_obj_port_mdb *mdb,
4307 int (*cb)(struct switchdev_obj *obj))
4308{
04bed143 4309 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4310 int err;
4311
4312 mutex_lock(&chip->reg_lock);
4313 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4314 mutex_unlock(&chip->reg_lock);
4315
4316 return err;
4317}
4318
a82f67af 4319static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4320 .probe = mv88e6xxx_drv_probe,
7b314362 4321 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4322 .setup = mv88e6xxx_setup,
4323 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4324 .adjust_link = mv88e6xxx_adjust_link,
4325 .get_strings = mv88e6xxx_get_strings,
4326 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4327 .get_sset_count = mv88e6xxx_get_sset_count,
4328 .set_eee = mv88e6xxx_set_eee,
4329 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4330 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4331 .get_eeprom = mv88e6xxx_get_eeprom,
4332 .set_eeprom = mv88e6xxx_set_eeprom,
4333 .get_regs_len = mv88e6xxx_get_regs_len,
4334 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4335 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4336 .port_bridge_join = mv88e6xxx_port_bridge_join,
4337 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4338 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4339 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4340 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4341 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4342 .port_vlan_add = mv88e6xxx_port_vlan_add,
4343 .port_vlan_del = mv88e6xxx_port_vlan_del,
4344 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4345 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4346 .port_fdb_add = mv88e6xxx_port_fdb_add,
4347 .port_fdb_del = mv88e6xxx_port_fdb_del,
4348 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4349 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4350 .port_mdb_add = mv88e6xxx_port_mdb_add,
4351 .port_mdb_del = mv88e6xxx_port_mdb_del,
4352 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4353};
4354
ab3d408d
FF		 4355static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4356 .ops = &mv88e6xxx_switch_ops,
4357};
4358
55ed0ce0 4359static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4360{
fad09c73 4361 struct device *dev = chip->dev;
b7e66a5f
VD		 4362 struct dsa_switch *ds;
4363
4364 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4365 if (!ds)
4366 return -ENOMEM;
4367
4368 ds->dev = dev;
fad09c73 4369 ds->priv = chip;
9d490b4e 4370 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4371
4372 dev_set_drvdata(dev, ds);
4373
55ed0ce0 4374 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4375}
4376
fad09c73 4377static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4378{
fad09c73 4379 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4380}
4381
57d32310 4382static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4383{
14c7b3c3 4384 struct device *dev = &mdiodev->dev;
f8cd8753 4385 struct device_node *np = dev->of_node;
caac8545 4386 const struct mv88e6xxx_info *compat_info;
fad09c73 4387 struct mv88e6xxx_chip *chip;
f8cd8753 4388 u32 eeprom_len;
52638f71 4389 int err;
14c7b3c3 4390
caac8545
VD		 4391 compat_info = of_device_get_match_data(dev);
4392 if (!compat_info)
4393 return -EINVAL;
4394
fad09c73
VD		 4395 chip = mv88e6xxx_alloc_chip(dev);
4396 if (!chip)
14c7b3c3
AL		 4397 return -ENOMEM;
4398
fad09c73 4399 chip->info = compat_info;
caac8545 4400
56995cbc
AL		 4401 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4402 if (err)
4403 return err;
4404
fad09c73 4405 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4406 if (err)
4407 return err;
14c7b3c3 4408
b4308f04
AL		 4409 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4410 if (IS_ERR(chip->reset))
4411 return PTR_ERR(chip->reset);
4412
fad09c73 4413 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4414 if (err)
4415 return err;
14c7b3c3 4416
e57e5e77
VD		 4417 mv88e6xxx_phy_init(chip);
4418
ee4dc2e7 4419 if (chip->info->ops->get_eeprom &&
f8cd8753 4420 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4421 chip->eeprom_len = eeprom_len;
f8cd8753 4422
dc30c35b
AL		 4423 mutex_lock(&chip->reg_lock);
4424 err = mv88e6xxx_switch_reset(chip);
4425 mutex_unlock(&chip->reg_lock);
4426 if (err)
4427 goto out;
4428
4429 chip->irq = of_irq_get(np, 0);
4430 if (chip->irq == -EPROBE_DEFER) {
4431 err = chip->irq;
4432 goto out;
4433 }
4434
4435 if (chip->irq > 0) {
4436 /* Has to be performed before the MDIO bus is created,
4437 * because the PHYs will link there interrupts to these
4438 * interrupt controllers
4439 */
4440 mutex_lock(&chip->reg_lock);
4441 err = mv88e6xxx_g1_irq_setup(chip);
4442 mutex_unlock(&chip->reg_lock);
4443
4444 if (err)
4445 goto out;
4446
4447 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4448 err = mv88e6xxx_g2_irq_setup(chip);
4449 if (err)
4450 goto out_g1_irq;
4451 }
4452 }
4453
a3c53be5 4454 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4455 if (err)
dc30c35b 4456 goto out_g2_irq;
b516d453 4457
55ed0ce0 4458 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4459 if (err)
4460 goto out_mdio;
83c0afae 4461
98e67308 4462 return 0;
dc30c35b
AL		 4463
4464out_mdio:
a3c53be5 4465 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4466out_g2_irq:
46712644 4467 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4468 mv88e6xxx_g2_irq_free(chip);
4469out_g1_irq:
61f7c3f8
AL		 4470 if (chip->irq > 0) {
4471 mutex_lock(&chip->reg_lock);
46712644 4472 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4473 mutex_unlock(&chip->reg_lock);
4474 }
dc30c35b
AL		 4475out:
4476 return err;
98e67308 4477}
14c7b3c3
AL		 4478
4479static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4480{
4481 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4482 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4483
930188ce 4484 mv88e6xxx_phy_destroy(chip);
fad09c73 4485 mv88e6xxx_unregister_switch(chip);
a3c53be5 4486 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4487
46712644
AL		 4488 if (chip->irq > 0) {
4489 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4490 mv88e6xxx_g2_irq_free(chip);
4491 mv88e6xxx_g1_irq_free(chip);
4492 }
14c7b3c3
AL		 4493}
4494
4495static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4496 {
4497 .compatible = "marvell,mv88e6085",
4498 .data = &mv88e6xxx_table[MV88E6085],
4499 },
1a3b39ec
AL		 4500 {
4501 .compatible = "marvell,mv88e6190",
4502 .data = &mv88e6xxx_table[MV88E6190],
4503 },
14c7b3c3
AL		 4504 { /* sentinel */ },
4505};
4506
4507MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4508
4509static struct mdio_driver mv88e6xxx_driver = {
4510 .probe = mv88e6xxx_probe,
4511 .remove = mv88e6xxx_remove,
4512 .mdiodrv.driver = {
4513 .name = "mv88e6085",
4514 .of_match_table = mv88e6xxx_of_match,
4515 },
4516};
4517
4518static int __init mv88e6xxx_init(void)
4519{
ab3d408d 4520 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4521 return mdio_driver_register(&mv88e6xxx_driver);
4522}
98e67308
BH		 4523module_init(mv88e6xxx_init);
4524
4525static void __exit mv88e6xxx_cleanup(void)
4526{
14c7b3c3 4527 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4528 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4529}
4530module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4531
4532MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4533MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4534MODULE_LICENSE("GPL");
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