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net: dsa: mv88e6xxx: rename _mv88e6xxx_wait
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
b516d453 26#include <linux/of_mdio.h>
91da11f8 27#include <linux/netdevice.h>
c8c1b39a 28#include <linux/gpio/consumer.h>
91da11f8 29#include <linux/phy.h>
c8f0b869 30#include <net/dsa.h>
1f36faf2 31#include <net/switchdev.h>
91da11f8
LB		 32#include "mv88e6xxx.h"
33
fad09c73 34static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 35{
fad09c73
VD		 36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 38 dump_stack();
39 }
40}
41
914b32f6
VD		 42/* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
44 *
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
48 *
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 52 */
914b32f6 53
fad09c73 54static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 55 int addr, int reg, u16 *val)
56{
fad09c73 57 if (!chip->smi_ops)
914b32f6
VD		 58 return -EOPNOTSUPP;
59
fad09c73 60 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 61}
62
fad09c73 63static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 *val)
74{
75 int ret;
76
fad09c73 77 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 78 if (ret < 0)
79 return ret;
80
81 *val = ret & 0xffff;
82
83 return 0;
84}
85
fad09c73 86static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 87 int addr, int reg, u16 val)
88{
89 int ret;
90
fad09c73 91 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 92 if (ret < 0)
93 return ret;
94
95 return 0;
96}
97
98static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
99 .read = mv88e6xxx_smi_single_chip_read,
100 .write = mv88e6xxx_smi_single_chip_write,
101};
102
fad09c73 103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 104{
105 int ret;
106 int i;
107
108 for (i = 0; i < 16; i++) {
fad09c73 109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 110 if (ret < 0)
111 return ret;
112
cca8b133 113 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 114 return 0;
115 }
116
117 return -ETIMEDOUT;
118}
119
fad09c73 120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 121 int addr, int reg, u16 *val)
91da11f8
LB		 122{
123 int ret;
124
3675c8d7 125 /* Wait for the bus to become free. */
fad09c73 126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 127 if (ret < 0)
128 return ret;
129
3675c8d7 130 /* Transmit the read command. */
fad09c73 131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 133 if (ret < 0)
134 return ret;
135
3675c8d7 136 /* Wait for the read command to complete. */
fad09c73 137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 138 if (ret < 0)
139 return ret;
140
3675c8d7 141 /* Read the data. */
fad09c73 142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 143 if (ret < 0)
144 return ret;
145
914b32f6 146 *val = ret & 0xffff;
91da11f8 147
914b32f6 148 return 0;
8d6d09e7
GR		 149}
150
fad09c73 151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 152 int addr, int reg, u16 val)
91da11f8
LB		 153{
154 int ret;
155
3675c8d7 156 /* Wait for the bus to become free. */
fad09c73 157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 158 if (ret < 0)
159 return ret;
160
3675c8d7 161 /* Transmit the data to write. */
fad09c73 162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 163 if (ret < 0)
164 return ret;
165
3675c8d7 166 /* Transmit the write command. */
fad09c73 167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 169 if (ret < 0)
170 return ret;
171
3675c8d7 172 /* Wait for the write command to complete. */
fad09c73 173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 174 if (ret < 0)
175 return ret;
176
177 return 0;
178}
179
914b32f6
VD		 180static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
183};
184
fad09c73 185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 186 int addr, int reg, u16 *val)
187{
188 int err;
189
fad09c73 190 assert_reg_lock(chip);
914b32f6 191
fad09c73 192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 193 if (err)
194 return err;
195
fad09c73 196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 197 addr, reg, *val);
198
199 return 0;
200}
201
fad09c73 202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
914b32f6 203 int addr, int reg, u16 val)
91da11f8 204{
914b32f6
VD		 205 int err;
206
fad09c73 207 assert_reg_lock(chip);
91da11f8 208
fad09c73 209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 210 if (err)
211 return err;
212
fad09c73 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 214 addr, reg, val);
215
914b32f6
VD		 216 return 0;
217}
218
2d79af6e
VD		 219static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
220 u16 mask)
221{
222 unsigned long timeout = jiffies + HZ / 10;
223
224 while (time_before(jiffies, timeout)) {
225 u16 val;
226 int err;
227
228 err = mv88e6xxx_read(chip, addr, reg, &val);
229 if (err)
230 return err;
231
232 if (!(val & mask))
233 return 0;
234
235 usleep_range(1000, 2000);
236 }
237
238 return -ETIMEDOUT;
239}
240
f22ab641
VD		 241/* Indirect write to single pointer-data register with an Update bit */
242static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
243 u16 update)
244{
245 u16 val;
246 int i, err;
247
248 /* Wait until the previous operation is completed */
249 for (i = 0; i < 16; ++i) {
250 err = mv88e6xxx_read(chip, addr, reg, &val);
251 if (err)
252 return err;
253
254 if (!(val & BIT(15)))
255 break;
256 }
257
258 if (i == 16)
259 return -ETIMEDOUT;
260
261 /* Set the Update bit to trigger a write operation */
262 val = BIT(15) | update;
263
264 return mv88e6xxx_write(chip, addr, reg, val);
265}
266
fad09c73 267static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
914b32f6
VD		 268{
269 u16 val;
270 int err;
271
fad09c73 272 err = mv88e6xxx_read(chip, addr, reg, &val);
914b32f6
VD		 273 if (err)
274 return err;
275
276 return val;
277}
278
fad09c73 279static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
914b32f6
VD		 280 int reg, u16 val)
281{
fad09c73 282 return mv88e6xxx_write(chip, addr, reg, val);
8d6d09e7
GR		 283}
284
fad09c73 285static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
03a4a540 286 int addr, int regnum)
91da11f8
LB		 287{
288 if (addr >= 0)
fad09c73 289 return _mv88e6xxx_reg_read(chip, addr, regnum);
91da11f8
LB		 290 return 0xffff;
291}
292
fad09c73 293static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
03a4a540 294 int addr, int regnum, u16 val)
91da11f8
LB		 295{
296 if (addr >= 0)
fad09c73 297 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
91da11f8
LB		 298 return 0;
299}
300
fad09c73 301static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
2e5f0320
LB		 302{
303 int ret;
19b2f97e 304 unsigned long timeout;
2e5f0320 305
fad09c73 306 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 307 if (ret < 0)
308 return ret;
309
fad09c73 310 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
8c9983a2 311 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 312 if (ret)
313 return ret;
2e5f0320 314
19b2f97e
BG		 315 timeout = jiffies + 1 * HZ;
316 while (time_before(jiffies, timeout)) {
fad09c73 317 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 318 if (ret < 0)
319 return ret;
320
19b2f97e 321 usleep_range(1000, 2000);
cca8b133
AL		 322 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
323 GLOBAL_STATUS_PPU_POLLING)
85686581 324 return 0;
2e5f0320
LB		 325 }
326
327 return -ETIMEDOUT;
328}
329
fad09c73 330static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 331{
48ace4ef 332 int ret, err;
19b2f97e 333 unsigned long timeout;
2e5f0320 334
fad09c73 335 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 336 if (ret < 0)
337 return ret;
338
fad09c73 339 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
762eb67b 340 ret | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 341 if (err)
342 return err;
2e5f0320 343
19b2f97e
BG		 344 timeout = jiffies + 1 * HZ;
345 while (time_before(jiffies, timeout)) {
fad09c73 346 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 347 if (ret < 0)
348 return ret;
349
19b2f97e 350 usleep_range(1000, 2000);
cca8b133
AL		 351 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
352 GLOBAL_STATUS_PPU_POLLING)
85686581 353 return 0;
2e5f0320
LB		 354 }
355
356 return -ETIMEDOUT;
357}
358
359static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
360{
fad09c73 361 struct mv88e6xxx_chip *chip;
2e5f0320 362
fad09c73 363 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 364
fad09c73 365 mutex_lock(&chip->reg_lock);
762eb67b 366
fad09c73
VD		 367 if (mutex_trylock(&chip->ppu_mutex)) {
368 if (mv88e6xxx_ppu_enable(chip) == 0)
369 chip->ppu_disabled = 0;
370 mutex_unlock(&chip->ppu_mutex);
2e5f0320 371 }
762eb67b 372
fad09c73 373 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 374}
375
376static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
377{
fad09c73 378 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 379
fad09c73 380 schedule_work(&chip->ppu_work);
2e5f0320
LB		 381}
382
fad09c73 383static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 384{
2e5f0320
LB		 385 int ret;
386
fad09c73 387 mutex_lock(&chip->ppu_mutex);
2e5f0320 388
3675c8d7 389 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 390 * we can access the PHY registers. If it was already
391 * disabled, cancel the timer that is going to re-enable
392 * it.
393 */
fad09c73
VD		 394 if (!chip->ppu_disabled) {
395 ret = mv88e6xxx_ppu_disable(chip);
85686581 396 if (ret < 0) {
fad09c73 397 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 398 return ret;
399 }
fad09c73 400 chip->ppu_disabled = 1;
2e5f0320 401 } else {
fad09c73 402 del_timer(&chip->ppu_timer);
85686581 403 ret = 0;
2e5f0320
LB		 404 }
405
406 return ret;
407}
408
fad09c73 409static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 410{
3675c8d7 411 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 412 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
413 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 414}
415
fad09c73 416static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 417{
fad09c73
VD		 418 mutex_init(&chip->ppu_mutex);
419 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
420 init_timer(&chip->ppu_timer);
421 chip->ppu_timer.data = (unsigned long)chip;
422 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 423}
424
fad09c73 425static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
03a4a540 426 int regnum)
2e5f0320
LB		 427{
428 int ret;
429
fad09c73 430 ret = mv88e6xxx_ppu_access_get(chip);
2e5f0320 431 if (ret >= 0) {
fad09c73
VD		 432 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
433 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 434 }
435
436 return ret;
437}
438
fad09c73 439static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
03a4a540 440 int regnum, u16 val)
2e5f0320
LB		 441{
442 int ret;
443
fad09c73 444 ret = mv88e6xxx_ppu_access_get(chip);
2e5f0320 445 if (ret >= 0) {
fad09c73
VD		 446 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
447 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 448 }
449
450 return ret;
451}
2e5f0320 452
fad09c73 453static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 454{
fad09c73 455 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 456}
457
fad09c73 458static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 459{
fad09c73 460 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 461}
462
fad09c73 463static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 464{
fad09c73 465 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 466}
467
fad09c73 468static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 469{
fad09c73 470 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 471}
472
fad09c73 473static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 474{
fad09c73 475 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 476}
477
fad09c73 478static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 479{
fad09c73 480 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 481}
482
fad09c73 483static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 484{
fad09c73 485 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 486}
487
fad09c73 488static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 489{
fad09c73 490 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 491}
492
fad09c73 493static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
f74df0be 494{
fad09c73 495 return chip->info->num_databases;
f74df0be
VD		 496}
497
fad09c73 498static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
b426e5f7
VD		 499{
500 /* Does the device have dedicated FID registers for ATU and VTU ops? */
fad09c73
VD		 501 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
502 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
b426e5f7
VD		 503 return true;
504
505 return false;
506}
507
dea87024
AL		 508/* We expect the switch to perform auto negotiation if there is a real
509 * phy. However, in the case of a fixed link phy, we force the port
510 * settings from the fixed link settings.
511 */
f81ec90f
VD		 512static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
513 struct phy_device *phydev)
dea87024 514{
fad09c73 515 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49052871
AL		 516 u32 reg;
517 int ret;
dea87024
AL		 518
519 if (!phy_is_pseudo_fixed_link(phydev))
520 return;
521
fad09c73 522 mutex_lock(&chip->reg_lock);
dea87024 523
fad09c73 524 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 525 if (ret < 0)
526 goto out;
527
528 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
529 PORT_PCS_CTRL_FORCE_LINK |
530 PORT_PCS_CTRL_DUPLEX_FULL |
531 PORT_PCS_CTRL_FORCE_DUPLEX |
532 PORT_PCS_CTRL_UNFORCED);
533
534 reg |= PORT_PCS_CTRL_FORCE_LINK;
535 if (phydev->link)
57d32310 536 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 537
fad09c73 538 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 539 goto out;
540
541 switch (phydev->speed) {
542 case SPEED_1000:
543 reg |= PORT_PCS_CTRL_1000;
544 break;
545 case SPEED_100:
546 reg |= PORT_PCS_CTRL_100;
547 break;
548 case SPEED_10:
549 reg |= PORT_PCS_CTRL_10;
550 break;
551 default:
552 pr_info("Unknown speed");
553 goto out;
554 }
555
556 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
557 if (phydev->duplex == DUPLEX_FULL)
558 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
559
fad09c73
VD		 560 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
561 (port >= chip->info->num_ports - 2)) {
e7e72ac0
AL		 562 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
563 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
564 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
565 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
566 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
567 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
568 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
569 }
fad09c73 570 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 571
572out:
fad09c73 573 mutex_unlock(&chip->reg_lock);
dea87024
AL		 574}
575
fad09c73 576static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 577{
578 int ret;
579 int i;
580
581 for (i = 0; i < 10; i++) {
fad09c73 582 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 583 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 584 return 0;
585 }
586
587 return -ETIMEDOUT;
588}
589
fad09c73 590static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8
LB		 591{
592 int ret;
593
fad09c73 594 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 595 port = (port + 1) << 5;
596
3675c8d7 597 /* Snapshot the hardware statistics counters for this port. */
fad09c73 598 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 599 GLOBAL_STATS_OP_CAPTURE_PORT |
600 GLOBAL_STATS_OP_HIST_RX_TX | port);
601 if (ret < 0)
602 return ret;
91da11f8 603
3675c8d7 604 /* Wait for the snapshotting to complete. */
fad09c73 605 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 606 if (ret < 0)
607 return ret;
608
609 return 0;
610}
611
fad09c73 612static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 613 int stat, u32 *val)
91da11f8
LB		 614{
615 u32 _val;
616 int ret;
617
618 *val = 0;
619
fad09c73 620 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 621 GLOBAL_STATS_OP_READ_CAPTURED |
622 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 623 if (ret < 0)
624 return;
625
fad09c73 626 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 627 if (ret < 0)
628 return;
629
fad09c73 630 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 631 if (ret < 0)
632 return;
633
634 _val = ret << 16;
635
fad09c73 636 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 637 if (ret < 0)
638 return;
639
640 *val = _val | ret;
641}
642
e413e7e1 643static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 644 { "in_good_octets", 8, 0x00, BANK0, },
645 { "in_bad_octets", 4, 0x02, BANK0, },
646 { "in_unicast", 4, 0x04, BANK0, },
647 { "in_broadcasts", 4, 0x06, BANK0, },
648 { "in_multicasts", 4, 0x07, BANK0, },
649 { "in_pause", 4, 0x16, BANK0, },
650 { "in_undersize", 4, 0x18, BANK0, },
651 { "in_fragments", 4, 0x19, BANK0, },
652 { "in_oversize", 4, 0x1a, BANK0, },
653 { "in_jabber", 4, 0x1b, BANK0, },
654 { "in_rx_error", 4, 0x1c, BANK0, },
655 { "in_fcs_error", 4, 0x1d, BANK0, },
656 { "out_octets", 8, 0x0e, BANK0, },
657 { "out_unicast", 4, 0x10, BANK0, },
658 { "out_broadcasts", 4, 0x13, BANK0, },
659 { "out_multicasts", 4, 0x12, BANK0, },
660 { "out_pause", 4, 0x15, BANK0, },
661 { "excessive", 4, 0x11, BANK0, },
662 { "collisions", 4, 0x1e, BANK0, },
663 { "deferred", 4, 0x05, BANK0, },
664 { "single", 4, 0x14, BANK0, },
665 { "multiple", 4, 0x17, BANK0, },
666 { "out_fcs_error", 4, 0x03, BANK0, },
667 { "late", 4, 0x1f, BANK0, },
668 { "hist_64bytes", 4, 0x08, BANK0, },
669 { "hist_65_127bytes", 4, 0x09, BANK0, },
670 { "hist_128_255bytes", 4, 0x0a, BANK0, },
671 { "hist_256_511bytes", 4, 0x0b, BANK0, },
672 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
673 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
674 { "sw_in_discards", 4, 0x10, PORT, },
675 { "sw_in_filtered", 2, 0x12, PORT, },
676 { "sw_out_filtered", 2, 0x13, PORT, },
677 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
679 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
680 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
682 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
683 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
684 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
685 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
686 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
687 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
688 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
689 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
690 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
691 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
692 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
693 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
694 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
695 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
696 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
697 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 703};
704
fad09c73 705static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 706 struct mv88e6xxx_hw_stat *stat)
e413e7e1 707{
f5e2ed02
AL		 708 switch (stat->type) {
709 case BANK0:
e413e7e1 710 return true;
f5e2ed02 711 case BANK1:
fad09c73 712 return mv88e6xxx_6320_family(chip);
f5e2ed02 713 case PORT:
fad09c73
VD		 714 return mv88e6xxx_6095_family(chip) ||
715 mv88e6xxx_6185_family(chip) ||
716 mv88e6xxx_6097_family(chip) ||
717 mv88e6xxx_6165_family(chip) ||
718 mv88e6xxx_6351_family(chip) ||
719 mv88e6xxx_6352_family(chip);
91da11f8 720 }
f5e2ed02 721 return false;
91da11f8
LB		 722}
723
fad09c73 724static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 725 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 726 int port)
727{
80c4627b
AL		 728 u32 low;
729 u32 high = 0;
730 int ret;
731 u64 value;
732
f5e2ed02
AL		 733 switch (s->type) {
734 case PORT:
fad09c73 735 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
80c4627b
AL		 736 if (ret < 0)
737 return UINT64_MAX;
738
739 low = ret;
740 if (s->sizeof_stat == 4) {
fad09c73 741 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
f5e2ed02 742 s->reg + 1);
80c4627b
AL		 743 if (ret < 0)
744 return UINT64_MAX;
745 high = ret;
746 }
f5e2ed02
AL		 747 break;
748 case BANK0:
749 case BANK1:
fad09c73 750 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 751 if (s->sizeof_stat == 8)
fad09c73 752 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 753 }
754 value = (((u64)high) << 16) | low;
755 return value;
756}
757
f81ec90f
VD		 758static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
759 uint8_t *data)
91da11f8 760{
fad09c73 761 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 762 struct mv88e6xxx_hw_stat *stat;
763 int i, j;
91da11f8 764
f5e2ed02
AL		 765 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
766 stat = &mv88e6xxx_hw_stats[i];
fad09c73 767 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 768 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
769 ETH_GSTRING_LEN);
770 j++;
771 }
91da11f8 772 }
e413e7e1
AL		 773}
774
f81ec90f 775static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 776{
fad09c73 777 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 778 struct mv88e6xxx_hw_stat *stat;
779 int i, j;
780
781 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
782 stat = &mv88e6xxx_hw_stats[i];
fad09c73 783 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 784 j++;
785 }
786 return j;
e413e7e1
AL		 787}
788
f81ec90f
VD		 789static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
790 uint64_t *data)
e413e7e1 791{
fad09c73 792 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 793 struct mv88e6xxx_hw_stat *stat;
794 int ret;
795 int i, j;
796
fad09c73 797 mutex_lock(&chip->reg_lock);
f5e2ed02 798
fad09c73 799 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 800 if (ret < 0) {
fad09c73 801 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 802 return;
803 }
804 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
805 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 806 if (mv88e6xxx_has_stat(chip, stat)) {
807 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 808 j++;
809 }
810 }
811
fad09c73 812 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 813}
814
f81ec90f 815static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 816{
817 return 32 * sizeof(u16);
818}
819
f81ec90f
VD		 820static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
821 struct ethtool_regs *regs, void *_p)
a1ab91f3 822{
fad09c73 823 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
a1ab91f3
GR		 824 u16 *p = _p;
825 int i;
826
827 regs->version = 0;
828
829 memset(p, 0xff, 32 * sizeof(u16));
830
fad09c73 831 mutex_lock(&chip->reg_lock);
23062513 832
a1ab91f3
GR		 833 for (i = 0; i < 32; i++) {
834 int ret;
835
fad09c73 836 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
a1ab91f3
GR		 837 if (ret >= 0)
838 p[i] = ret;
839 }
23062513 840
fad09c73 841 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 842}
843
fad09c73 844static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
f3044683 845{
2d79af6e
VD		 846 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 848}
849
fad09c73 850static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 851{
2d79af6e
VD		 852 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
853 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 854}
855
fad09c73 856static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
158bc065 857 int addr, int regnum)
f3044683
AL		 858{
859 int ret;
860
fad09c73 861 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 862 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
863 regnum);
864 if (ret < 0)
865 return ret;
f3044683 866
fad09c73 867 ret = mv88e6xxx_mdio_wait(chip);
f3044683
AL		 868 if (ret < 0)
869 return ret;
870
fad09c73 871 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
158bc065
AL		 872
873 return ret;
f3044683
AL		 874}
875
fad09c73 876static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
158bc065 877 int addr, int regnum, u16 val)
f3044683 878{
3898c148
AL		 879 int ret;
880
fad09c73 881 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
3898c148
AL		 882 if (ret < 0)
883 return ret;
f3044683 884
fad09c73 885 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 886 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
887 regnum);
888
fad09c73 889 return mv88e6xxx_mdio_wait(chip);
f3044683
AL		 890}
891
f81ec90f
VD		 892static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
893 struct ethtool_eee *e)
11b3b45d 894{
fad09c73 895 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
11b3b45d
GR		 896 int reg;
897
fad09c73 898 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 899 return -EOPNOTSUPP;
900
fad09c73 901 mutex_lock(&chip->reg_lock);
2f40c698 902
fad09c73 903 reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
11b3b45d 904 if (reg < 0)
2f40c698 905 goto out;
11b3b45d
GR		 906
907 e->eee_enabled = !!(reg & 0x0200);
908 e->tx_lpi_enabled = !!(reg & 0x0100);
909
fad09c73 910 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
11b3b45d 911 if (reg < 0)
2f40c698 912 goto out;
11b3b45d 913
cca8b133 914 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 915 reg = 0;
11b3b45d 916
2f40c698 917out:
fad09c73 918 mutex_unlock(&chip->reg_lock);
2f40c698 919 return reg;
11b3b45d
GR		 920}
921
f81ec90f
VD		 922static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
923 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 924{
fad09c73 925 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2f40c698 926 int reg;
11b3b45d
GR		 927 int ret;
928
fad09c73 929 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 930 return -EOPNOTSUPP;
931
fad09c73 932 mutex_lock(&chip->reg_lock);
11b3b45d 933
fad09c73 934 ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
2f40c698
AL		 935 if (ret < 0)
936 goto out;
937
938 reg = ret & ~0x0300;
939 if (e->eee_enabled)
940 reg |= 0x0200;
941 if (e->tx_lpi_enabled)
942 reg |= 0x0100;
943
fad09c73 944 ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
2f40c698 945out:
fad09c73 946 mutex_unlock(&chip->reg_lock);
2f40c698
AL		 947
948 return ret;
11b3b45d
GR		 949}
950
fad09c73 951static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2
GR		 952{
953 int ret;
954
fad09c73
VD		 955 if (mv88e6xxx_has_fid_reg(chip)) {
956 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
957 fid);
b426e5f7
VD		 958 if (ret < 0)
959 return ret;
fad09c73 960 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 961 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
fad09c73 962 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 963 if (ret < 0)
964 return ret;
965
fad09c73 966 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 967 (ret & 0xfff) |
968 ((fid << 8) & 0xf000));
969 if (ret < 0)
970 return ret;
971
972 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
973 cmd |= fid & 0xf;
b426e5f7
VD		 974 }
975
fad09c73 976 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 977 if (ret < 0)
978 return ret;
979
fad09c73 980 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 981}
982
fad09c73 983static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 984 struct mv88e6xxx_atu_entry *entry)
985{
986 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
987
988 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
989 unsigned int mask, shift;
990
991 if (entry->trunk) {
992 data |= GLOBAL_ATU_DATA_TRUNK;
993 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
994 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
995 } else {
996 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
997 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
998 }
999
1000 data |= (entry->portv_trunkid << shift) & mask;
1001 }
1002
fad09c73 1003 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1004}
1005
fad09c73 1006static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1007 struct mv88e6xxx_atu_entry *entry,
1008 bool static_too)
facd95b2 1009{
7fb5e755
VD		 1010 int op;
1011 int err;
facd95b2 1012
fad09c73 1013 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1014 if (err)
1015 return err;
facd95b2 1016
fad09c73 1017 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1018 if (err)
1019 return err;
1020
1021 if (entry->fid) {
7fb5e755
VD		 1022 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1023 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1024 } else {
1025 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1026 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1027 }
1028
fad09c73 1029 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1030}
1031
fad09c73 1032static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1033 u16 fid, bool static_too)
7fb5e755
VD		 1034{
1035 struct mv88e6xxx_atu_entry entry = {
1036 .fid = fid,
1037 .state = 0, /* EntryState bits must be 0 */
1038 };
70cc99d1 1039
fad09c73 1040 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1041}
1042
fad09c73 1043static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1044 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1045{
1046 struct mv88e6xxx_atu_entry entry = {
1047 .trunk = false,
1048 .fid = fid,
1049 };
1050
1051 /* EntryState bits must be 0xF */
1052 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1053
1054 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1055 entry.portv_trunkid = (to_port & 0x0f) << 4;
1056 entry.portv_trunkid |= from_port & 0x0f;
1057
fad09c73 1058 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1059}
1060
fad09c73 1061static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1062 int port, bool static_too)
9f4d55d2
VD		 1063{
1064 /* Destination port 0xF means remove the entries */
fad09c73 1065 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1066}
1067
2d9deae4
VD		 1068static const char * const mv88e6xxx_port_state_names[] = {
1069 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1070 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1071 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1072 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1073};
1074
fad09c73 1075static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1076 u8 state)
facd95b2 1077{
fad09c73 1078 struct dsa_switch *ds = chip->ds;
c3ffe6d2 1079 int reg, ret = 0;
facd95b2
GR		 1080 u8 oldstate;
1081
fad09c73 1082 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1083 if (reg < 0)
1084 return reg;
facd95b2 1085
cca8b133 1086 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1087
facd95b2
GR		 1088 if (oldstate != state) {
1089 /* Flush forwarding database if we're moving a port
1090 * from Learning or Forwarding state to Disabled or
1091 * Blocking or Listening state.
1092 */
2d9deae4 1093 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
57d32310
VD		 1094 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1095 (state == PORT_CONTROL_STATE_DISABLED ||
1096 state == PORT_CONTROL_STATE_BLOCKING)) {
fad09c73 1097 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
facd95b2 1098 if (ret)
2d9deae4 1099 return ret;
facd95b2 1100 }
2d9deae4 1101
cca8b133 1102 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
fad09c73 1103 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
cca8b133 1104 reg);
2d9deae4
VD		 1105 if (ret)
1106 return ret;
1107
c8b09808 1108 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
2d9deae4
VD		 1109 mv88e6xxx_port_state_names[state],
1110 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1111 }
1112
facd95b2
GR		 1113 return ret;
1114}
1115
fad09c73 1116static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1117{
fad09c73
VD		 1118 struct net_device *bridge = chip->ports[port].bridge_dev;
1119 const u16 mask = (1 << chip->info->num_ports) - 1;
1120 struct dsa_switch *ds = chip->ds;
b7666efe 1121 u16 output_ports = 0;
ede8098d 1122 int reg;
b7666efe
VD		 1123 int i;
1124
1125 /* allow CPU port or DSA link(s) to send frames to every port */
1126 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1127 output_ports = mask;
1128 } else {
fad09c73 1129 for (i = 0; i < chip->info->num_ports; ++i) {
b7666efe 1130 /* allow sending frames to every group member */
fad09c73 1131 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1132 output_ports |= BIT(i);
1133
1134 /* allow sending frames to CPU port and DSA link(s) */
1135 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1136 output_ports |= BIT(i);
1137 }
1138 }
1139
1140 /* prevent frames from going back out of the port they came in on */
1141 output_ports &= ~BIT(port);
facd95b2 1142
fad09c73 1143 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1144 if (reg < 0)
1145 return reg;
facd95b2 1146
ede8098d
VD		 1147 reg &= ~mask;
1148 reg |= output_ports & mask;
facd95b2 1149
fad09c73 1150 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1151}
1152
f81ec90f
VD		 1153static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1154 u8 state)
facd95b2 1155{
fad09c73 1156 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
facd95b2 1157 int stp_state;
553eb544 1158 int err;
facd95b2
GR		 1159
1160 switch (state) {
1161 case BR_STATE_DISABLED:
cca8b133 1162 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1163 break;
1164 case BR_STATE_BLOCKING:
1165 case BR_STATE_LISTENING:
cca8b133 1166 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1167 break;
1168 case BR_STATE_LEARNING:
cca8b133 1169 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1170 break;
1171 case BR_STATE_FORWARDING:
1172 default:
cca8b133 1173 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1174 break;
1175 }
1176
fad09c73
VD		 1177 mutex_lock(&chip->reg_lock);
1178 err = _mv88e6xxx_port_state(chip, port, stp_state);
1179 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1180
1181 if (err)
c8b09808
AL		 1182 netdev_err(ds->ports[port].netdev,
1183 "failed to update state to %s\n",
553eb544 1184 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1185}
1186
fad09c73 1187static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1188 u16 *new, u16 *old)
76e398a6 1189{
fad09c73 1190 struct dsa_switch *ds = chip->ds;
5da96031 1191 u16 pvid;
76e398a6
VD		 1192 int ret;
1193
fad09c73 1194 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1195 if (ret < 0)
1196 return ret;
1197
5da96031
VD		 1198 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1199
1200 if (new) {
1201 ret &= ~PORT_DEFAULT_VLAN_MASK;
1202 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1203
fad09c73 1204 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
5da96031
VD		 1205 PORT_DEFAULT_VLAN, ret);
1206 if (ret < 0)
1207 return ret;
1208
c8b09808
AL		 1209 netdev_dbg(ds->ports[port].netdev,
1210 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1211 }
1212
1213 if (old)
1214 *old = pvid;
76e398a6
VD		 1215
1216 return 0;
1217}
1218
fad09c73 1219static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1220 int port, u16 *pvid)
5da96031 1221{
fad09c73 1222 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1223}
1224
fad09c73 1225static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1226 int port, u16 pvid)
0d3b33e6 1227{
fad09c73 1228 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1229}
1230
fad09c73 1231static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1232{
2d79af6e
VD		 1233 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1234 GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1235}
1236
fad09c73 1237static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864
VD		 1238{
1239 int ret;
1240
fad09c73 1241 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1242 if (ret < 0)
1243 return ret;
1244
fad09c73 1245 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1246}
1247
fad09c73 1248static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1249{
1250 int ret;
1251
fad09c73 1252 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1253 if (ret < 0)
1254 return ret;
1255
fad09c73 1256 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1257}
1258
fad09c73 1259static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1260 struct mv88e6xxx_vtu_stu_entry *entry,
1261 unsigned int nibble_offset)
1262{
b8fee957
VD		 1263 u16 regs[3];
1264 int i;
1265 int ret;
1266
1267 for (i = 0; i < 3; ++i) {
fad09c73 1268 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1269 GLOBAL_VTU_DATA_0_3 + i);
1270 if (ret < 0)
1271 return ret;
1272
1273 regs[i] = ret;
1274 }
1275
fad09c73 1276 for (i = 0; i < chip->info->num_ports; ++i) {
b8fee957
VD		 1277 unsigned int shift = (i % 4) * 4 + nibble_offset;
1278 u16 reg = regs[i / 4];
1279
1280 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1281 }
1282
1283 return 0;
1284}
1285
fad09c73 1286static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1287 struct mv88e6xxx_vtu_stu_entry *entry)
1288{
fad09c73 1289 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1290}
1291
fad09c73 1292static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1293 struct mv88e6xxx_vtu_stu_entry *entry)
1294{
fad09c73 1295 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1296}
1297
fad09c73 1298static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1299 struct mv88e6xxx_vtu_stu_entry *entry,
1300 unsigned int nibble_offset)
1301{
7dad08d7
VD		 1302 u16 regs[3] = { 0 };
1303 int i;
1304 int ret;
1305
fad09c73 1306 for (i = 0; i < chip->info->num_ports; ++i) {
7dad08d7
VD		 1307 unsigned int shift = (i % 4) * 4 + nibble_offset;
1308 u8 data = entry->data[i];
1309
1310 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1311 }
1312
1313 for (i = 0; i < 3; ++i) {
fad09c73 1314 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
7dad08d7
VD		 1315 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1316 if (ret < 0)
1317 return ret;
1318 }
1319
1320 return 0;
1321}
1322
fad09c73 1323static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1324 struct mv88e6xxx_vtu_stu_entry *entry)
1325{
fad09c73 1326 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1327}
1328
fad09c73 1329static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1330 struct mv88e6xxx_vtu_stu_entry *entry)
1331{
fad09c73 1332 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1333}
1334
fad09c73 1335static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1336{
fad09c73 1337 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1338 vid & GLOBAL_VTU_VID_MASK);
1339}
1340
fad09c73 1341static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1342 struct mv88e6xxx_vtu_stu_entry *entry)
1343{
1344 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1345 int ret;
1346
fad09c73 1347 ret = _mv88e6xxx_vtu_wait(chip);
b8fee957
VD		 1348 if (ret < 0)
1349 return ret;
1350
fad09c73 1351 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1352 if (ret < 0)
1353 return ret;
1354
fad09c73 1355 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1356 if (ret < 0)
1357 return ret;
1358
1359 next.vid = ret & GLOBAL_VTU_VID_MASK;
1360 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1361
1362 if (next.valid) {
fad09c73 1363 ret = mv88e6xxx_vtu_data_read(chip, &next);
b8fee957
VD		 1364 if (ret < 0)
1365 return ret;
1366
fad09c73
VD		 1367 if (mv88e6xxx_has_fid_reg(chip)) {
1368 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1369 GLOBAL_VTU_FID);
1370 if (ret < 0)
1371 return ret;
1372
1373 next.fid = ret & GLOBAL_VTU_FID_MASK;
fad09c73 1374 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1375 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1376 * VTU DBNum[3:0] are located in VTU Operation 3:0
1377 */
fad09c73 1378 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
11ea809f
VD		 1379 GLOBAL_VTU_OP);
1380 if (ret < 0)
1381 return ret;
1382
1383 next.fid = (ret & 0xf00) >> 4;
1384 next.fid |= ret & 0xf;
2e7bd5ef 1385 }
b8fee957 1386
fad09c73
VD		 1387 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1388 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1389 GLOBAL_VTU_SID);
1390 if (ret < 0)
1391 return ret;
1392
1393 next.sid = ret & GLOBAL_VTU_SID_MASK;
1394 }
1395 }
1396
1397 *entry = next;
1398 return 0;
1399}
1400
f81ec90f
VD		 1401static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1402 struct switchdev_obj_port_vlan *vlan,
1403 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1404{
fad09c73 1405 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
ceff5eff
VD		 1406 struct mv88e6xxx_vtu_stu_entry next;
1407 u16 pvid;
1408 int err;
1409
fad09c73 1410 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1411 return -EOPNOTSUPP;
1412
fad09c73 1413 mutex_lock(&chip->reg_lock);
ceff5eff 1414
fad09c73 1415 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1416 if (err)
1417 goto unlock;
1418
fad09c73 1419 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1420 if (err)
1421 goto unlock;
1422
1423 do {
fad09c73 1424 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1425 if (err)
1426 break;
1427
1428 if (!next.valid)
1429 break;
1430
1431 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1432 continue;
1433
1434 /* reinit and dump this VLAN obj */
57d32310
VD		 1435 vlan->vid_begin = next.vid;
1436 vlan->vid_end = next.vid;
ceff5eff
VD		 1437 vlan->flags = 0;
1438
1439 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1440 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1441
1442 if (next.vid == pvid)
1443 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1444
1445 err = cb(&vlan->obj);
1446 if (err)
1447 break;
1448 } while (next.vid < GLOBAL_VTU_VID_MASK);
1449
1450unlock:
fad09c73 1451 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1452
1453 return err;
1454}
1455
fad09c73 1456static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1457 struct mv88e6xxx_vtu_stu_entry *entry)
1458{
11ea809f 1459 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1460 u16 reg = 0;
1461 int ret;
1462
fad09c73 1463 ret = _mv88e6xxx_vtu_wait(chip);
7dad08d7
VD		 1464 if (ret < 0)
1465 return ret;
1466
1467 if (!entry->valid)
1468 goto loadpurge;
1469
1470 /* Write port member tags */
fad09c73 1471 ret = mv88e6xxx_vtu_data_write(chip, entry);
7dad08d7
VD		 1472 if (ret < 0)
1473 return ret;
1474
fad09c73 1475 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1476 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73
VD		 1477 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1478 reg);
7dad08d7
VD		 1479 if (ret < 0)
1480 return ret;
b426e5f7 1481 }
7dad08d7 1482
fad09c73 1483 if (mv88e6xxx_has_fid_reg(chip)) {
7dad08d7 1484 reg = entry->fid & GLOBAL_VTU_FID_MASK;
fad09c73
VD		 1485 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1486 reg);
7dad08d7
VD		 1487 if (ret < 0)
1488 return ret;
fad09c73 1489 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1490 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1491 * VTU DBNum[3:0] are located in VTU Operation 3:0
1492 */
1493 op |= (entry->fid & 0xf0) << 8;
1494 op |= entry->fid & 0xf;
7dad08d7
VD		 1495 }
1496
1497 reg = GLOBAL_VTU_VID_VALID;
1498loadpurge:
1499 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
fad09c73 1500 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1501 if (ret < 0)
1502 return ret;
1503
fad09c73 1504 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1505}
1506
fad09c73 1507static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
0d3b33e6
VD		 1508 struct mv88e6xxx_vtu_stu_entry *entry)
1509{
1510 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1511 int ret;
1512
fad09c73 1513 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1514 if (ret < 0)
1515 return ret;
1516
fad09c73 1517 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1518 sid & GLOBAL_VTU_SID_MASK);
1519 if (ret < 0)
1520 return ret;
1521
fad09c73 1522 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1523 if (ret < 0)
1524 return ret;
1525
fad09c73 1526 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1527 if (ret < 0)
1528 return ret;
1529
1530 next.sid = ret & GLOBAL_VTU_SID_MASK;
1531
fad09c73 1532 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1533 if (ret < 0)
1534 return ret;
1535
1536 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1537
1538 if (next.valid) {
fad09c73 1539 ret = mv88e6xxx_stu_data_read(chip, &next);
0d3b33e6
VD		 1540 if (ret < 0)
1541 return ret;
1542 }
1543
1544 *entry = next;
1545 return 0;
1546}
1547
fad09c73 1548static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
0d3b33e6
VD		 1549 struct mv88e6xxx_vtu_stu_entry *entry)
1550{
1551 u16 reg = 0;
1552 int ret;
1553
fad09c73 1554 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1555 if (ret < 0)
1556 return ret;
1557
1558 if (!entry->valid)
1559 goto loadpurge;
1560
1561 /* Write port states */
fad09c73 1562 ret = mv88e6xxx_stu_data_write(chip, entry);
0d3b33e6
VD		 1563 if (ret < 0)
1564 return ret;
1565
1566 reg = GLOBAL_VTU_VID_VALID;
1567loadpurge:
fad09c73 1568 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1569 if (ret < 0)
1570 return ret;
1571
1572 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73 1573 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1574 if (ret < 0)
1575 return ret;
1576
fad09c73 1577 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1578}
1579
fad09c73 1580static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1581 u16 *new, u16 *old)
2db9ce1f 1582{
fad09c73 1583 struct dsa_switch *ds = chip->ds;
f74df0be 1584 u16 upper_mask;
2db9ce1f
VD		 1585 u16 fid;
1586 int ret;
1587
fad09c73 1588 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1589 upper_mask = 0xff;
fad09c73 1590 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1591 upper_mask = 0xf;
f74df0be
VD		 1592 else
1593 return -EOPNOTSUPP;
1594
2db9ce1f 1595 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
fad09c73 1596 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1597 if (ret < 0)
1598 return ret;
1599
1600 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1601
1602 if (new) {
1603 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1604 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1605
fad09c73 1606 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1607 ret);
1608 if (ret < 0)
1609 return ret;
1610 }
1611
1612 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
fad09c73 1613 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1614 if (ret < 0)
1615 return ret;
1616
f74df0be 1617 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1618
1619 if (new) {
f74df0be
VD		 1620 ret &= ~upper_mask;
1621 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1622
fad09c73 1623 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1624 ret);
1625 if (ret < 0)
1626 return ret;
1627
c8b09808
AL		 1628 netdev_dbg(ds->ports[port].netdev,
1629 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1630 }
1631
1632 if (old)
1633 *old = fid;
1634
1635 return 0;
1636}
1637
fad09c73 1638static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1639 int port, u16 *fid)
2db9ce1f 1640{
fad09c73 1641 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1642}
1643
fad09c73 1644static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1645 int port, u16 fid)
2db9ce1f 1646{
fad09c73 1647 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1648}
1649
fad09c73 1650static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1651{
1652 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1653 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1654 int i, err;
3285f9e8
VD		 1655
1656 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1657
2db9ce1f 1658 /* Set every FID bit used by the (un)bridged ports */
fad09c73
VD		 1659 for (i = 0; i < chip->info->num_ports; ++i) {
1660 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1661 if (err)
1662 return err;
1663
1664 set_bit(*fid, fid_bitmap);
1665 }
1666
3285f9e8 1667 /* Set every FID bit used by the VLAN entries */
fad09c73 1668 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1669 if (err)
1670 return err;
1671
1672 do {
fad09c73 1673 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1674 if (err)
1675 return err;
1676
1677 if (!vlan.valid)
1678 break;
1679
1680 set_bit(vlan.fid, fid_bitmap);
1681 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1682
1683 /* The reset value 0x000 is used to indicate that multiple address
1684 * databases are not needed. Return the next positive available.
1685 */
1686 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1687 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1688 return -ENOSPC;
1689
1690 /* Clear the database */
fad09c73 1691 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1692}
1693
fad09c73 1694static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09 1695 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1696{
fad09c73 1697 struct dsa_switch *ds = chip->ds;
0d3b33e6
VD		 1698 struct mv88e6xxx_vtu_stu_entry vlan = {
1699 .valid = true,
1700 .vid = vid,
1701 };
3285f9e8
VD		 1702 int i, err;
1703
fad09c73 1704 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1705 if (err)
1706 return err;
0d3b33e6 1707
3d131f07 1708 /* exclude all ports except the CPU and DSA ports */
fad09c73 1709 for (i = 0; i < chip->info->num_ports; ++i)
3d131f07
VD		 1710 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1711 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1712 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1713
fad09c73
VD		 1714 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1715 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
0d3b33e6 1716 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1717
1718 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1719 * implemented, only one STU entry is needed to cover all VTU
1720 * entries. Thus, validate the SID 0.
1721 */
1722 vlan.sid = 0;
fad09c73 1723 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1724 if (err)
1725 return err;
1726
1727 if (vstp.sid != vlan.sid || !vstp.valid) {
1728 memset(&vstp, 0, sizeof(vstp));
1729 vstp.valid = true;
1730 vstp.sid = vlan.sid;
1731
fad09c73 1732 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1733 if (err)
1734 return err;
1735 }
0d3b33e6
VD		 1736 }
1737
1738 *entry = vlan;
1739 return 0;
1740}
1741
fad09c73 1742static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09
VD		 1743 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1744{
1745 int err;
1746
1747 if (!vid)
1748 return -EINVAL;
1749
fad09c73 1750 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1751 if (err)
1752 return err;
1753
fad09c73 1754 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1755 if (err)
1756 return err;
1757
1758 if (entry->vid != vid || !entry->valid) {
1759 if (!creat)
1760 return -EOPNOTSUPP;
1761 /* -ENOENT would've been more appropriate, but switchdev expects
1762 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1763 */
1764
fad09c73 1765 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1766 }
1767
1768 return err;
1769}
1770
da9c359e
VD		 1771static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1772 u16 vid_begin, u16 vid_end)
1773{
fad09c73 1774 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1775 struct mv88e6xxx_vtu_stu_entry vlan;
1776 int i, err;
1777
1778 if (!vid_begin)
1779 return -EOPNOTSUPP;
1780
fad09c73 1781 mutex_lock(&chip->reg_lock);
da9c359e 1782
fad09c73 1783 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1784 if (err)
1785 goto unlock;
1786
1787 do {
fad09c73 1788 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1789 if (err)
1790 goto unlock;
1791
1792 if (!vlan.valid)
1793 break;
1794
1795 if (vlan.vid > vid_end)
1796 break;
1797
fad09c73 1798 for (i = 0; i < chip->info->num_ports; ++i) {
da9c359e
VD		 1799 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1800 continue;
1801
1802 if (vlan.data[i] ==
1803 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1804 continue;
1805
fad09c73
VD		 1806 if (chip->ports[i].bridge_dev ==
1807 chip->ports[port].bridge_dev)
da9c359e
VD		 1808 break; /* same bridge, check next VLAN */
1809
c8b09808 1810 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1811 "hardware VLAN %d already used by %s\n",
1812 vlan.vid,
fad09c73 1813 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1814 err = -EOPNOTSUPP;
1815 goto unlock;
1816 }
1817 } while (vlan.vid < vid_end);
1818
1819unlock:
fad09c73 1820 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1821
1822 return err;
1823}
1824
214cdb99
VD		 1825static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1826 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1827 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1828 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1829 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1830};
1831
f81ec90f
VD		 1832static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1833 bool vlan_filtering)
214cdb99 1834{
fad09c73 1835 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
214cdb99
VD		 1836 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1837 PORT_CONTROL_2_8021Q_DISABLED;
1838 int ret;
1839
fad09c73 1840 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1841 return -EOPNOTSUPP;
1842
fad09c73 1843 mutex_lock(&chip->reg_lock);
214cdb99 1844
fad09c73 1845 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 1846 if (ret < 0)
1847 goto unlock;
1848
1849 old = ret & PORT_CONTROL_2_8021Q_MASK;
1850
5220ef1e
VD		 1851 if (new != old) {
1852 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1853 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1854
fad09c73 1855 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 1856 ret);
1857 if (ret < 0)
1858 goto unlock;
1859
c8b09808 1860 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 1861 mv88e6xxx_port_8021q_mode_names[new],
1862 mv88e6xxx_port_8021q_mode_names[old]);
1863 }
214cdb99 1864
5220ef1e 1865 ret = 0;
214cdb99 1866unlock:
fad09c73 1867 mutex_unlock(&chip->reg_lock);
214cdb99
VD		 1868
1869 return ret;
1870}
1871
57d32310
VD		 1872static int
1873mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1874 const struct switchdev_obj_port_vlan *vlan,
1875 struct switchdev_trans *trans)
76e398a6 1876{
fad09c73 1877 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1878 int err;
1879
fad09c73 1880 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1881 return -EOPNOTSUPP;
1882
da9c359e
VD		 1883 /* If the requested port doesn't belong to the same bridge as the VLAN
1884 * members, do not support it (yet) and fallback to software VLAN.
1885 */
1886 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1887 vlan->vid_end);
1888 if (err)
1889 return err;
1890
76e398a6
VD		 1891 /* We don't need any dynamic resource from the kernel (yet),
1892 * so skip the prepare phase.
1893 */
1894 return 0;
1895}
1896
fad09c73 1897static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1898 u16 vid, bool untagged)
0d3b33e6 1899{
0d3b33e6
VD		 1900 struct mv88e6xxx_vtu_stu_entry vlan;
1901 int err;
1902
fad09c73 1903 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1904 if (err)
76e398a6 1905 return err;
0d3b33e6 1906
0d3b33e6
VD		 1907 vlan.data[port] = untagged ?
1908 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1909 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1910
fad09c73 1911 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1912}
1913
f81ec90f
VD		 1914static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1915 const struct switchdev_obj_port_vlan *vlan,
1916 struct switchdev_trans *trans)
76e398a6 1917{
fad09c73 1918 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 1919 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1920 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1921 u16 vid;
76e398a6 1922
fad09c73 1923 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1924 return;
1925
fad09c73 1926 mutex_lock(&chip->reg_lock);
76e398a6 1927
4d5770b3 1928 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1929 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1930 netdev_err(ds->ports[port].netdev,
1931 "failed to add VLAN %d%c\n",
4d5770b3 1932 vid, untagged ? 'u' : 't');
76e398a6 1933
fad09c73 1934 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 1935 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1936 vlan->vid_end);
0d3b33e6 1937
fad09c73 1938 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1939}
1940
fad09c73 1941static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1942 int port, u16 vid)
7dad08d7 1943{
fad09c73 1944 struct dsa_switch *ds = chip->ds;
7dad08d7 1945 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1946 int i, err;
1947
fad09c73 1948 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1949 if (err)
76e398a6 1950 return err;
7dad08d7 1951
2fb5ef09
VD		 1952 /* Tell switchdev if this VLAN is handled in software */
1953 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1954 return -EOPNOTSUPP;
7dad08d7
VD		 1955
1956 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1957
1958 /* keep the VLAN unless all ports are excluded */
f02bdffc 1959 vlan.valid = false;
fad09c73 1960 for (i = 0; i < chip->info->num_ports; ++i) {
3d131f07 1961 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1962 continue;
1963
1964 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1965 vlan.valid = true;
7dad08d7
VD		 1966 break;
1967 }
1968 }
1969
fad09c73 1970 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1971 if (err)
1972 return err;
1973
fad09c73 1974 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1975}
1976
f81ec90f
VD		 1977static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1978 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1979{
fad09c73 1980 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 1981 u16 pvid, vid;
1982 int err = 0;
1983
fad09c73 1984 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1985 return -EOPNOTSUPP;
1986
fad09c73 1987 mutex_lock(&chip->reg_lock);
76e398a6 1988
fad09c73 1989 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 1990 if (err)
1991 goto unlock;
1992
76e398a6 1993 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1994 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1995 if (err)
1996 goto unlock;
1997
1998 if (vid == pvid) {
fad09c73 1999 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 2000 if (err)
2001 goto unlock;
2002 }
2003 }
2004
7dad08d7 2005unlock:
fad09c73 2006 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2007
2008 return err;
2009}
2010
fad09c73 2011static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2012 const unsigned char *addr)
defb05b9
GR		 2013{
2014 int i, ret;
2015
2016 for (i = 0; i < 3; i++) {
cca8b133 2017 ret = _mv88e6xxx_reg_write(
fad09c73 2018 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2019 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2020 if (ret < 0)
2021 return ret;
2022 }
2023
2024 return 0;
2025}
2026
fad09c73 2027static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2028 unsigned char *addr)
defb05b9
GR		 2029{
2030 int i, ret;
2031
2032 for (i = 0; i < 3; i++) {
fad09c73 2033 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
cca8b133 2034 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2035 if (ret < 0)
2036 return ret;
2037 addr[i * 2] = ret >> 8;
2038 addr[i * 2 + 1] = ret & 0xff;
2039 }
2040
2041 return 0;
2042}
2043
fad09c73 2044static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2045 struct mv88e6xxx_atu_entry *entry)
defb05b9 2046{
6630e236
VD		 2047 int ret;
2048
fad09c73 2049 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2050 if (ret < 0)
2051 return ret;
2052
fad09c73 2053 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2054 if (ret < 0)
2055 return ret;
2056
fad09c73 2057 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2058 if (ret < 0)
87820510
VD		 2059 return ret;
2060
fad09c73 2061 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2062}
87820510 2063
fad09c73 2064static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
fd231c82
VD		 2065 const unsigned char *addr, u16 vid,
2066 u8 state)
2067{
2068 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2069 struct mv88e6xxx_vtu_stu_entry vlan;
2070 int err;
2071
2db9ce1f
VD		 2072 /* Null VLAN ID corresponds to the port private database */
2073 if (vid == 0)
fad09c73 2074 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2075 else
fad09c73 2076 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2077 if (err)
2078 return err;
fd231c82 2079
3285f9e8 2080 entry.fid = vlan.fid;
fd231c82
VD		 2081 entry.state = state;
2082 ether_addr_copy(entry.mac, addr);
2083 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2084 entry.trunk = false;
2085 entry.portv_trunkid = BIT(port);
2086 }
2087
fad09c73 2088 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2089}
2090
f81ec90f
VD		 2091static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2092 const struct switchdev_obj_port_fdb *fdb,
2093 struct switchdev_trans *trans)
146a3206
VD		 2094{
2095 /* We don't need any dynamic resource from the kernel (yet),
2096 * so skip the prepare phase.
2097 */
2098 return 0;
2099}
2100
f81ec90f
VD		 2101static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2102 const struct switchdev_obj_port_fdb *fdb,
2103 struct switchdev_trans *trans)
87820510 2104{
1f36faf2 2105 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2106 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2107 GLOBAL_ATU_DATA_STATE_UC_STATIC;
fad09c73 2108 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510 2109
fad09c73
VD		 2110 mutex_lock(&chip->reg_lock);
2111 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
c8b09808
AL		 2112 netdev_err(ds->ports[port].netdev,
2113 "failed to load MAC address\n");
fad09c73 2114 mutex_unlock(&chip->reg_lock);
87820510
VD		 2115}
2116
f81ec90f
VD		 2117static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2118 const struct switchdev_obj_port_fdb *fdb)
87820510 2119{
fad09c73 2120 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510
VD		 2121 int ret;
2122
fad09c73
VD		 2123 mutex_lock(&chip->reg_lock);
2124 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
cdf09697 2125 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2126 mutex_unlock(&chip->reg_lock);
87820510
VD		 2127
2128 return ret;
2129}
2130
fad09c73 2131static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2132 struct mv88e6xxx_atu_entry *entry)
6630e236 2133{
1d194046
VD		 2134 struct mv88e6xxx_atu_entry next = { 0 };
2135 int ret;
2136
2137 next.fid = fid;
defb05b9 2138
fad09c73 2139 ret = _mv88e6xxx_atu_wait(chip);
cdf09697
DM		 2140 if (ret < 0)
2141 return ret;
6630e236 2142
fad09c73 2143 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2144 if (ret < 0)
2145 return ret;
6630e236 2146
fad09c73 2147 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
1d194046
VD		 2148 if (ret < 0)
2149 return ret;
6630e236 2150
fad09c73 2151 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2152 if (ret < 0)
2153 return ret;
6630e236 2154
1d194046
VD		 2155 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2156 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2157 unsigned int mask, shift;
2158
2159 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2160 next.trunk = true;
2161 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2162 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2163 } else {
2164 next.trunk = false;
2165 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2166 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2167 }
2168
2169 next.portv_trunkid = (ret & mask) >> shift;
2170 }
cdf09697 2171
1d194046 2172 *entry = next;
cdf09697
DM		 2173 return 0;
2174}
2175
fad09c73 2176static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
158bc065 2177 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2178 struct switchdev_obj_port_fdb *fdb,
2179 int (*cb)(struct switchdev_obj *obj))
2180{
2181 struct mv88e6xxx_atu_entry addr = {
2182 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2183 };
2184 int err;
2185
fad09c73 2186 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2187 if (err)
2188 return err;
2189
2190 do {
fad09c73 2191 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d
VD		 2192 if (err)
2193 break;
2194
2195 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2196 break;
2197
2198 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2199 bool is_static = addr.state ==
2200 (is_multicast_ether_addr(addr.mac) ?
2201 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2202 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2203
2204 fdb->vid = vid;
2205 ether_addr_copy(fdb->addr, addr.mac);
2206 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2207
2208 err = cb(&fdb->obj);
2209 if (err)
2210 break;
2211 }
2212 } while (!is_broadcast_ether_addr(addr.mac));
2213
2214 return err;
2215}
2216
f81ec90f
VD		 2217static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2218 struct switchdev_obj_port_fdb *fdb,
2219 int (*cb)(struct switchdev_obj *obj))
f33475bd 2220{
fad09c73 2221 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f33475bd
VD		 2222 struct mv88e6xxx_vtu_stu_entry vlan = {
2223 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2224 };
2db9ce1f 2225 u16 fid;
f33475bd
VD		 2226 int err;
2227
fad09c73 2228 mutex_lock(&chip->reg_lock);
f33475bd 2229
2db9ce1f 2230 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2231 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f
VD		 2232 if (err)
2233 goto unlock;
2234
fad09c73 2235 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2236 if (err)
2237 goto unlock;
2238
74b6ba0d 2239 /* Dump VLANs' Filtering Information Databases */
fad09c73 2240 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd
VD		 2241 if (err)
2242 goto unlock;
2243
2244 do {
fad09c73 2245 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2246 if (err)
74b6ba0d 2247 break;
f33475bd
VD		 2248
2249 if (!vlan.valid)
2250 break;
2251
fad09c73
VD		 2252 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2253 port, fdb, cb);
f33475bd 2254 if (err)
74b6ba0d 2255 break;
f33475bd
VD		 2256 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2257
2258unlock:
fad09c73 2259 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2260
2261 return err;
2262}
2263
f81ec90f
VD		 2264static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2265 struct net_device *bridge)
e79a8bcb 2266{
fad09c73 2267 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1d9619d5 2268 int i, err = 0;
466dfa07 2269
fad09c73 2270 mutex_lock(&chip->reg_lock);
466dfa07 2271
b7666efe 2272 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2273 chip->ports[port].bridge_dev = bridge;
b7666efe 2274
fad09c73
VD		 2275 for (i = 0; i < chip->info->num_ports; ++i) {
2276 if (chip->ports[i].bridge_dev == bridge) {
2277 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2278 if (err)
2279 break;
2280 }
2281 }
2282
fad09c73 2283 mutex_unlock(&chip->reg_lock);
a6692754 2284
466dfa07 2285 return err;
e79a8bcb
VD		 2286}
2287
f81ec90f 2288static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2289{
fad09c73
VD		 2290 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2291 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2292 int i;
466dfa07 2293
fad09c73 2294 mutex_lock(&chip->reg_lock);
466dfa07 2295
b7666efe 2296 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2297 chip->ports[port].bridge_dev = NULL;
b7666efe 2298
fad09c73
VD		 2299 for (i = 0; i < chip->info->num_ports; ++i)
2300 if (i == port || chip->ports[i].bridge_dev == bridge)
2301 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2302 netdev_warn(ds->ports[i].netdev,
2303 "failed to remap\n");
b7666efe 2304
fad09c73 2305 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2306}
2307
fad09c73 2308static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
03a4a540 2309 int port, int page, int reg, int val)
75baacf0
PU		 2310{
2311 int ret;
2312
fad09c73 2313 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
75baacf0
PU		 2314 if (ret < 0)
2315 goto restore_page_0;
2316
fad09c73 2317 ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
75baacf0 2318restore_page_0:
fad09c73 2319 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
75baacf0
PU		 2320
2321 return ret;
2322}
2323
fad09c73 2324static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
03a4a540 2325 int port, int page, int reg)
75baacf0
PU		 2326{
2327 int ret;
2328
fad09c73 2329 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
75baacf0
PU		 2330 if (ret < 0)
2331 goto restore_page_0;
2332
fad09c73 2333 ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
75baacf0 2334restore_page_0:
fad09c73 2335 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
75baacf0
PU		 2336
2337 return ret;
2338}
2339
fad09c73 2340static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2341{
fad09c73 2342 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2343 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2344 struct gpio_desc *gpiod = chip->reset;
552238b5
VD		 2345 unsigned long timeout;
2346 int ret;
2347 int i;
2348
2349 /* Set all ports to the disabled state. */
fad09c73
VD		 2350 for (i = 0; i < chip->info->num_ports; i++) {
2351 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
552238b5
VD		 2352 if (ret < 0)
2353 return ret;
2354
fad09c73 2355 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
552238b5
VD		 2356 ret & 0xfffc);
2357 if (ret)
2358 return ret;
2359 }
2360
2361 /* Wait for transmit queues to drain. */
2362 usleep_range(2000, 4000);
2363
2364 /* If there is a gpio connected to the reset pin, toggle it */
2365 if (gpiod) {
2366 gpiod_set_value_cansleep(gpiod, 1);
2367 usleep_range(10000, 20000);
2368 gpiod_set_value_cansleep(gpiod, 0);
2369 usleep_range(10000, 20000);
2370 }
2371
2372 /* Reset the switch. Keep the PPU active if requested. The PPU
2373 * needs to be active to support indirect phy register access
2374 * through global registers 0x18 and 0x19.
2375 */
2376 if (ppu_active)
fad09c73 2377 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
552238b5 2378 else
fad09c73 2379 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
552238b5
VD		 2380 if (ret)
2381 return ret;
2382
2383 /* Wait up to one second for reset to complete. */
2384 timeout = jiffies + 1 * HZ;
2385 while (time_before(jiffies, timeout)) {
fad09c73 2386 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
552238b5
VD		 2387 if (ret < 0)
2388 return ret;
2389
2390 if ((ret & is_reset) == is_reset)
2391 break;
2392 usleep_range(1000, 2000);
2393 }
2394 if (time_after(jiffies, timeout))
2395 ret = -ETIMEDOUT;
2396 else
2397 ret = 0;
2398
2399 return ret;
2400}
2401
fad09c73 2402static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
13a7ebb3
PU		 2403{
2404 int ret;
2405
fad09c73 2406 ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
03a4a540 2407 PAGE_FIBER_SERDES, MII_BMCR);
13a7ebb3
PU		 2408 if (ret < 0)
2409 return ret;
2410
2411 if (ret & BMCR_PDOWN) {
2412 ret &= ~BMCR_PDOWN;
fad09c73 2413 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
03a4a540
AL		 2414 PAGE_FIBER_SERDES, MII_BMCR,
2415 ret);
13a7ebb3
PU		 2416 }
2417
2418 return ret;
2419}
2420
8f6345b2
VD		 2421static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2422 int reg, u16 *val)
2423{
2424 int addr = chip->info->port_base_addr + port;
2425
2426 if (port >= chip->info->num_ports)
2427 return -EINVAL;
2428
2429 return mv88e6xxx_read(chip, addr, reg, val);
2430}
2431
fad09c73 2432static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2433{
fad09c73 2434 struct dsa_switch *ds = chip->ds;
f02bdffc 2435 int ret;
54d792f2 2436 u16 reg;
d827e88a 2437
fad09c73
VD		 2438 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2439 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2440 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2441 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2442 /* MAC Forcing register: don't force link, speed,
2443 * duplex or flow control state to any particular
2444 * values on physical ports, but force the CPU port
2445 * and all DSA ports to their maximum bandwidth and
2446 * full duplex.
2447 */
fad09c73 2448 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2449 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2450 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2451 reg |= PORT_PCS_CTRL_FORCE_LINK |
2452 PORT_PCS_CTRL_LINK_UP |
2453 PORT_PCS_CTRL_DUPLEX_FULL |
2454 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2455 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2456 reg |= PORT_PCS_CTRL_100;
2457 else
2458 reg |= PORT_PCS_CTRL_1000;
2459 } else {
2460 reg |= PORT_PCS_CTRL_UNFORCED;
2461 }
2462
fad09c73 2463 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2464 PORT_PCS_CTRL, reg);
2465 if (ret)
a1a6a4d1 2466 return ret;
54d792f2
AL		 2467 }
2468
2469 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2470 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2471 * tunneling, determine priority by looking at 802.1p and IP
2472 * priority fields (IP prio has precedence), and set STP state
2473 * to Forwarding.
2474 *
2475 * If this is the CPU link, use DSA or EDSA tagging depending
2476 * on which tagging mode was configured.
2477 *
2478 * If this is a link to another switch, use DSA tagging mode.
2479 *
2480 * If this is the upstream port for this switch, enable
2481 * forwarding of unknown unicasts and multicasts.
2482 */
2483 reg = 0;
fad09c73
VD		 2484 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2485 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2486 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2487 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2488 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2489 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2490 PORT_CONTROL_STATE_FORWARDING;
2491 if (dsa_is_cpu_port(ds, port)) {
fad09c73 2492 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
54d792f2 2493 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2494 if (mv88e6xxx_6352_family(chip) ||
2495 mv88e6xxx_6351_family(chip) ||
2496 mv88e6xxx_6165_family(chip) ||
2497 mv88e6xxx_6097_family(chip) ||
2498 mv88e6xxx_6320_family(chip)) {
5377b802
AL		 2499 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2500 PORT_CONTROL_FORWARD_UNKNOWN |
c047a1f9 2501 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2502 }
2503
fad09c73
VD		 2504 if (mv88e6xxx_6352_family(chip) ||
2505 mv88e6xxx_6351_family(chip) ||
2506 mv88e6xxx_6165_family(chip) ||
2507 mv88e6xxx_6097_family(chip) ||
2508 mv88e6xxx_6095_family(chip) ||
2509 mv88e6xxx_6065_family(chip) ||
2510 mv88e6xxx_6185_family(chip) ||
2511 mv88e6xxx_6320_family(chip)) {
57d32310 2512 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
54d792f2
AL		 2513 }
2514 }
6083ce71 2515 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2516 if (mv88e6xxx_6095_family(chip) ||
2517 mv88e6xxx_6185_family(chip))
6083ce71 2518 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2519 if (mv88e6xxx_6352_family(chip) ||
2520 mv88e6xxx_6351_family(chip) ||
2521 mv88e6xxx_6165_family(chip) ||
2522 mv88e6xxx_6097_family(chip) ||
2523 mv88e6xxx_6320_family(chip)) {
54d792f2 2524 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2525 }
2526
54d792f2
AL		 2527 if (port == dsa_upstream_port(ds))
2528 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2529 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2530 }
2531 if (reg) {
fad09c73 2532 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2533 PORT_CONTROL, reg);
2534 if (ret)
a1a6a4d1 2535 return ret;
54d792f2
AL		 2536 }
2537
13a7ebb3
PU		 2538 /* If this port is connected to a SerDes, make sure the SerDes is not
2539 * powered down.
2540 */
fad09c73
VD		 2541 if (mv88e6xxx_6352_family(chip)) {
2542 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
13a7ebb3 2543 if (ret < 0)
a1a6a4d1 2544 return ret;
13a7ebb3
PU		 2545 ret &= PORT_STATUS_CMODE_MASK;
2546 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2547 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2548 (ret == PORT_STATUS_CMODE_SGMII)) {
fad09c73 2549 ret = mv88e6xxx_power_on_serdes(chip);
13a7ebb3 2550 if (ret < 0)
a1a6a4d1 2551 return ret;
13a7ebb3
PU		 2552 }
2553 }
2554
8efdda4a 2555 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2556 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2557 * untagged frames on this port, do a destination address lookup on all
2558 * received packets as usual, disable ARP mirroring and don't send a
2559 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2560 */
2561 reg = 0;
fad09c73
VD		 2562 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2563 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2564 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2565 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2566 reg = PORT_CONTROL_2_MAP_DA;
2567
fad09c73
VD		 2568 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2569 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2570 reg |= PORT_CONTROL_2_JUMBO_10240;
2571
fad09c73 2572 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2573 /* Set the upstream port this port should use */
2574 reg |= dsa_upstream_port(ds);
2575 /* enable forwarding of unknown multicast addresses to
2576 * the upstream port
2577 */
2578 if (port == dsa_upstream_port(ds))
2579 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2580 }
2581
46fbe5e5 2582 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2583
54d792f2 2584 if (reg) {
fad09c73 2585 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2586 PORT_CONTROL_2, reg);
2587 if (ret)
a1a6a4d1 2588 return ret;
54d792f2
AL		 2589 }
2590
2591 /* Port Association Vector: when learning source addresses
2592 * of packets, add the address to the address database using
2593 * a port bitmap that has only the bit for this port set and
2594 * the other bits clear.
2595 */
4c7ea3c0 2596 reg = 1 << port;
996ecb82
VD		 2597 /* Disable learning for CPU port */
2598 if (dsa_is_cpu_port(ds, port))
65fa4027 2599 reg = 0;
4c7ea3c0 2600
fad09c73
VD		 2601 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2602 reg);
54d792f2 2603 if (ret)
a1a6a4d1 2604 return ret;
54d792f2
AL		 2605
2606 /* Egress rate control 2: disable egress rate control. */
fad09c73 2607 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2608 0x0000);
2609 if (ret)
a1a6a4d1 2610 return ret;
54d792f2 2611
fad09c73
VD		 2612 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2613 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2614 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2615 /* Do not limit the period of time that this port can
2616 * be paused for by the remote end or the period of
2617 * time that this port can pause the remote end.
2618 */
fad09c73 2619 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2620 PORT_PAUSE_CTRL, 0x0000);
2621 if (ret)
a1a6a4d1 2622 return ret;
54d792f2
AL		 2623
2624 /* Port ATU control: disable limiting the number of
2625 * address database entries that this port is allowed
2626 * to use.
2627 */
fad09c73 2628 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2629 PORT_ATU_CONTROL, 0x0000);
2630 /* Priority Override: disable DA, SA and VTU priority
2631 * override.
2632 */
fad09c73 2633 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2634 PORT_PRI_OVERRIDE, 0x0000);
2635 if (ret)
a1a6a4d1 2636 return ret;
54d792f2
AL		 2637
2638 /* Port Ethertype: use the Ethertype DSA Ethertype
2639 * value.
2640 */
fad09c73 2641 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2642 PORT_ETH_TYPE, ETH_P_EDSA);
2643 if (ret)
a1a6a4d1 2644 return ret;
54d792f2
AL		 2645 /* Tag Remap: use an identity 802.1p prio -> switch
2646 * prio mapping.
2647 */
fad09c73 2648 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2649 PORT_TAG_REGMAP_0123, 0x3210);
2650 if (ret)
a1a6a4d1 2651 return ret;
54d792f2
AL		 2652
2653 /* Tag Remap 2: use an identity 802.1p prio -> switch
2654 * prio mapping.
2655 */
fad09c73 2656 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2657 PORT_TAG_REGMAP_4567, 0x7654);
2658 if (ret)
a1a6a4d1 2659 return ret;
54d792f2
AL		 2660 }
2661
fad09c73
VD		 2662 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2663 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2664 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2665 mv88e6xxx_6320_family(chip)) {
54d792f2 2666 /* Rate Control: disable ingress rate limiting. */
fad09c73 2667 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2668 PORT_RATE_CONTROL, 0x0001);
2669 if (ret)
a1a6a4d1 2670 return ret;
54d792f2
AL		 2671 }
2672
366f0a0f
GR		 2673 /* Port Control 1: disable trunking, disable sending
2674 * learning messages to this port.
d827e88a 2675 */
fad09c73
VD		 2676 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2677 0x0000);
d827e88a 2678 if (ret)
a1a6a4d1 2679 return ret;
d827e88a 2680
207afda1 2681 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2682 * database, and allow bidirectional communication between the
2683 * CPU and DSA port(s), and the other ports.
d827e88a 2684 */
fad09c73 2685 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2db9ce1f 2686 if (ret)
a1a6a4d1 2687 return ret;
2db9ce1f 2688
fad09c73 2689 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
d827e88a 2690 if (ret)
a1a6a4d1 2691 return ret;
d827e88a
GR		 2692
2693 /* Default VLAN ID and priority: don't set a default VLAN
2694 * ID, and set the default packet priority to zero.
2695 */
fad09c73 2696 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2697 0x0000);
a1a6a4d1
VD		 2698 if (ret)
2699 return ret;
dbde9e66 2700
dbde9e66
AL		 2701 return 0;
2702}
2703
3b4caa1b
VD		 2704static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2705{
2706 int err;
2707
2708 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2709 (addr[0] << 8) | addr[1]);
2710 if (err)
2711 return err;
2712
2713 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2714 (addr[2] << 8) | addr[3]);
2715 if (err)
2716 return err;
2717
2718 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2719 (addr[4] << 8) | addr[5]);
2720}
2721
acddbd21
VD		 2722static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2723 unsigned int msecs)
2724{
2725 const unsigned int coeff = chip->info->age_time_coeff;
2726 const unsigned int min = 0x01 * coeff;
2727 const unsigned int max = 0xff * coeff;
2728 u8 age_time;
2729 u16 val;
2730 int err;
2731
2732 if (msecs < min || msecs > max)
2733 return -ERANGE;
2734
2735 /* Round to nearest multiple of coeff */
2736 age_time = (msecs + coeff / 2) / coeff;
2737
2738 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2739 if (err)
2740 return err;
2741
2742 /* AgeTime is 11:4 bits */
2743 val &= ~0xff0;
2744 val |= age_time << 4;
2745
2746 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2747}
2748
2cfcd964
VD		 2749static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2750 unsigned int ageing_time)
2751{
2752 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2753 int err;
2754
2755 mutex_lock(&chip->reg_lock);
2756 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2757 mutex_unlock(&chip->reg_lock);
2758
2759 return err;
2760}
2761
9729934c 2762static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2763{
fad09c73 2764 struct dsa_switch *ds = chip->ds;
b0745e87 2765 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2766 u16 reg;
552238b5 2767 int err;
54d792f2 2768
119477bd
VD		 2769 /* Enable the PHY Polling Unit if present, don't discard any packets,
2770 * and mask all interrupt sources.
2771 */
2772 reg = 0;
fad09c73
VD		 2773 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2774 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2775 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2776
fad09c73 2777 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
119477bd
VD		 2778 if (err)
2779 return err;
2780
b0745e87
VD		 2781 /* Configure the upstream port, and configure it as the port to which
2782 * ingress and egress and ARP monitor frames are to be sent.
2783 */
2784 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2785 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2786 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
fad09c73
VD		 2787 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2788 reg);
b0745e87
VD		 2789 if (err)
2790 return err;
2791
50484ff4 2792 /* Disable remote management, and set the switch's DSA device number. */
fad09c73 2793 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
50484ff4
VD		 2794 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2795 (ds->index & 0x1f));
2796 if (err)
2797 return err;
2798
acddbd21
VD		 2799 /* Clear all the VTU and STU entries */
2800 err = _mv88e6xxx_vtu_stu_flush(chip);
2801 if (err < 0)
2802 return err;
2803
54d792f2
AL		 2804 /* Set the default address aging time to 5 minutes, and
2805 * enable address learn messages to be sent to all message
2806 * ports.
2807 */
acddbd21
VD		 2808 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2809 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2810 if (err)
08a01261 2811 return err;
54d792f2 2812
acddbd21
VD		 2813 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2814 if (err)
9729934c
VD		 2815 return err;
2816
2817 /* Clear all ATU entries */
2818 err = _mv88e6xxx_atu_flush(chip, 0, true);
2819 if (err)
2820 return err;
2821
54d792f2 2822 /* Configure the IP ToS mapping registers. */
fad09c73 2823 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2824 if (err)
08a01261 2825 return err;
fad09c73 2826 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2827 if (err)
08a01261 2828 return err;
fad09c73 2829 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2830 if (err)
08a01261 2831 return err;
fad09c73 2832 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2833 if (err)
08a01261 2834 return err;
fad09c73 2835 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2836 if (err)
08a01261 2837 return err;
fad09c73 2838 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2839 if (err)
08a01261 2840 return err;
fad09c73 2841 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2842 if (err)
08a01261 2843 return err;
fad09c73 2844 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2845 if (err)
08a01261 2846 return err;
54d792f2
AL		 2847
2848 /* Configure the IEEE 802.1p priority mapping register. */
fad09c73 2849 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2850 if (err)
08a01261 2851 return err;
54d792f2 2852
9729934c
VD		 2853 /* Clear the statistics counters for all ports */
2854 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2855 GLOBAL_STATS_OP_FLUSH_ALL);
2856 if (err)
2857 return err;
2858
2859 /* Wait for the flush to complete. */
2860 err = _mv88e6xxx_stats_wait(chip);
2861 if (err)
2862 return err;
2863
2864 return 0;
2865}
2866
f22ab641
VD		 2867static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2868 int target, int port)
2869{
2870 u16 val = (target << 8) | (port & 0xf);
2871
2872 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2873}
2874
2875static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2876{
2877 int target, port;
2878 int err;
2879
2880 /* Initialize the routing port to the 32 possible target devices */
2881 for (target = 0; target < 32; ++target) {
2882 port = 0xf;
2883
2884 if (target < DSA_MAX_SWITCHES) {
2885 port = chip->ds->rtable[target];
2886 if (port == DSA_RTABLE_NONE)
2887 port = 0xf;
2888 }
2889
2890 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2891 if (err)
2892 break;
2893 }
2894
2895 return err;
2896}
2897
5154041f
VD		 2898static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2899 bool hask, u16 mask)
2900{
2901 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2902 u16 val = (num << 12) | (mask & port_mask);
2903
2904 if (hask)
2905 val |= GLOBAL2_TRUNK_MASK_HASK;
2906
2907 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2908}
2909
2910static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2911 u16 map)
2912{
2913 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2914 u16 val = (id << 11) | (map & port_mask);
2915
2916 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2917}
2918
2919static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2920{
2921 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2922 int i, err;
2923
2924 /* Clear all eight possible Trunk Mask vectors */
2925 for (i = 0; i < 8; ++i) {
2926 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2927 if (err)
2928 return err;
2929 }
2930
2931 /* Clear all sixteen possible Trunk ID routing vectors */
2932 for (i = 0; i < 16; ++i) {
2933 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2934 if (err)
2935 return err;
2936 }
2937
2938 return 0;
2939}
2940
8ec61c7f
VD		 2941static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2942{
2943 int port, err;
2944
2945 /* Init all Ingress Rate Limit resources of all ports */
2946 for (port = 0; port < chip->info->num_ports; ++port) {
2947 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2948 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2949 GLOBAL2_IRL_CMD_OP_INIT_ALL |
2950 (port << 8));
2951 if (err)
2952 break;
2953
2954 /* Wait for the operation to complete */
2d79af6e
VD		 2955 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2956 GLOBAL2_IRL_CMD_BUSY);
8ec61c7f
VD		 2957 if (err)
2958 break;
2959 }
2960
2961 return err;
2962}
2963
3b4caa1b
VD		 2964/* Indirect write to the Switch MAC/WoL/WoF register */
2965static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2966 unsigned int pointer, u8 data)
2967{
2968 u16 val = (pointer << 8) | data;
2969
2970 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2971}
2972
2973static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2974{
2975 int i, err;
2976
2977 for (i = 0; i < 6; i++) {
2978 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2979 if (err)
2980 break;
2981 }
2982
2983 return err;
2984}
2985
9bda889f
VD		 2986static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2987 u8 data)
2988{
2989 u16 val = (pointer << 8) | (data & 0x7);
2990
2991 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2992}
2993
2994static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2995{
2996 int i, err;
2997
2998 /* Clear all sixteen possible Priority Override entries */
2999 for (i = 0; i < 16; i++) {
3000 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3001 if (err)
3002 break;
3003 }
3004
3005 return err;
3006}
3007
855b1932
VD		 3008static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3009{
2d79af6e
VD		 3010 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3011 GLOBAL2_EEPROM_CMD_BUSY |
3012 GLOBAL2_EEPROM_CMD_RUNNING);
855b1932
VD		 3013}
3014
3015static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3016{
3017 int err;
3018
3019 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3020 if (err)
3021 return err;
3022
3023 return mv88e6xxx_g2_eeprom_wait(chip);
3024}
3025
3026static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3027 u8 addr, u16 *data)
3028{
3029 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3030 int err;
3031
3032 err = mv88e6xxx_g2_eeprom_wait(chip);
3033 if (err)
3034 return err;
3035
3036 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3037 if (err)
3038 return err;
3039
3040 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3041}
3042
3043static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3044 u8 addr, u16 data)
3045{
3046 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3047 int err;
3048
3049 err = mv88e6xxx_g2_eeprom_wait(chip);
3050 if (err)
3051 return err;
3052
3053 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3054 if (err)
3055 return err;
3056
3057 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3058}
3059
9729934c
VD		 3060static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3061{
47395ed2 3062 u16 reg;
9729934c 3063 int err;
9729934c 3064
47395ed2
VD		 3065 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3066 /* Consider the frames with reserved multicast destination
3067 * addresses matching 01:80:c2:00:00:2x as MGMT.
3068 */
3069 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3070 0xffff);
3071 if (err)
3072 return err;
3073 }
3074
3075 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3076 /* Consider the frames with reserved multicast destination
3077 * addresses matching 01:80:c2:00:00:0x as MGMT.
3078 */
3079 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3080 0xffff);
3081 if (err)
3082 return err;
3083 }
54d792f2
AL		 3084
3085 /* Ignore removed tag data on doubly tagged packets, disable
3086 * flow control messages, force flow control priority to the
3087 * highest, and send all special multicast frames to the CPU
3088 * port at the highest priority.
3089 */
47395ed2
VD		 3090 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3091 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3092 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3093 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3094 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
48ace4ef 3095 if (err)
08a01261 3096 return err;
54d792f2
AL		 3097
3098 /* Program the DSA routing table. */
f22ab641
VD		 3099 err = mv88e6xxx_g2_set_device_mapping(chip);
3100 if (err)
3101 return err;
54d792f2 3102
5154041f
VD		 3103 /* Clear all trunk masks and mapping. */
3104 err = mv88e6xxx_g2_clear_trunk(chip);
3105 if (err)
3106 return err;
54d792f2 3107
8ec61c7f
VD		 3108 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3109 /* Disable ingress rate limiting by resetting all per port
3110 * ingress rate limit resources to their initial state.
3111 */
3112 err = mv88e6xxx_g2_clear_irl(chip);
3113 if (err)
3114 return err;
3115 }
3116
63ed880d
VD		 3117 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3118 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3119 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3120 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
48ace4ef 3121 if (err)
08a01261 3122 return err;
63ed880d 3123 }
54d792f2 3124
9bda889f 3125 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
54d792f2 3126 /* Clear the priority override table. */
9bda889f
VD		 3127 err = mv88e6xxx_g2_clear_pot(chip);
3128 if (err)
3129 return err;
54d792f2
AL		 3130 }
3131
9729934c 3132 return 0;
08a01261
VD		 3133}
3134
f81ec90f 3135static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3136{
fad09c73 3137 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
08a01261 3138 int err;
a1a6a4d1
VD		 3139 int i;
3140
fad09c73
VD		 3141 chip->ds = ds;
3142 ds->slave_mii_bus = chip->mdio_bus;
08a01261 3143
fad09c73 3144 mutex_lock(&chip->reg_lock);
08a01261 3145
fad09c73 3146 err = mv88e6xxx_switch_reset(chip);
08a01261
VD		 3147 if (err)
3148 goto unlock;
3149
9729934c
VD		 3150 /* Setup Switch Port Registers */
3151 for (i = 0; i < chip->info->num_ports; i++) {
3152 err = mv88e6xxx_setup_port(chip, i);
3153 if (err)
3154 goto unlock;
3155 }
3156
3157 /* Setup Switch Global 1 Registers */
3158 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 3159 if (err)
3160 goto unlock;
3161
9729934c
VD		 3162 /* Setup Switch Global 2 Registers */
3163 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3164 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 3165 if (err)
3166 goto unlock;
3167 }
08a01261 3168
6b17e864 3169unlock:
fad09c73 3170 mutex_unlock(&chip->reg_lock);
db687a56 3171
48ace4ef 3172 return err;
54d792f2
AL		 3173}
3174
3b4caa1b
VD		 3175static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3176{
3177 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3178 int err;
3179
3180 mutex_lock(&chip->reg_lock);
3181
3182 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3183 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3184 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3185 else
3186 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3187
3188 mutex_unlock(&chip->reg_lock);
3189
3190 return err;
3191}
3192
57d32310
VD		 3193static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3194 int reg)
49143585 3195{
fad09c73 3196 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49143585
AL		 3197 int ret;
3198
fad09c73
VD		 3199 mutex_lock(&chip->reg_lock);
3200 ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3201 mutex_unlock(&chip->reg_lock);
75baacf0 3202
49143585
AL		 3203 return ret;
3204}
3205
57d32310
VD		 3206static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3207 int reg, int val)
49143585 3208{
fad09c73 3209 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49143585
AL		 3210 int ret;
3211
fad09c73
VD		 3212 mutex_lock(&chip->reg_lock);
3213 ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3214 mutex_unlock(&chip->reg_lock);
75baacf0 3215
fd3a0ee4
AL		 3216 return ret;
3217}
3218
fad09c73 3219static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
fd3a0ee4 3220{
fad09c73 3221 if (port >= 0 && port < chip->info->num_ports)
fd3a0ee4
AL		 3222 return port;
3223 return -EINVAL;
3224}
3225
b516d453 3226static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
fd3a0ee4 3227{
fad09c73
VD		 3228 struct mv88e6xxx_chip *chip = bus->priv;
3229 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
fd3a0ee4
AL		 3230 int ret;
3231
3232 if (addr < 0)
158bc065 3233 return 0xffff;
fd3a0ee4 3234
fad09c73 3235 mutex_lock(&chip->reg_lock);
8c9983a2 3236
fad09c73
VD		 3237 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3238 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3239 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3240 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
8c9983a2 3241 else
fad09c73 3242 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
8c9983a2 3243
fad09c73 3244 mutex_unlock(&chip->reg_lock);
fd3a0ee4
AL		 3245 return ret;
3246}
3247
b516d453 3248static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
03a4a540 3249 u16 val)
fd3a0ee4 3250{
fad09c73
VD		 3251 struct mv88e6xxx_chip *chip = bus->priv;
3252 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
fd3a0ee4
AL		 3253 int ret;
3254
3255 if (addr < 0)
158bc065 3256 return 0xffff;
fd3a0ee4 3257
fad09c73 3258 mutex_lock(&chip->reg_lock);
8c9983a2 3259
fad09c73
VD		 3260 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3261 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3262 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3263 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
8c9983a2 3264 else
fad09c73 3265 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
8c9983a2 3266
fad09c73 3267 mutex_unlock(&chip->reg_lock);
fd3a0ee4
AL		 3268 return ret;
3269}
3270
fad09c73 3271static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 3272 struct device_node *np)
3273{
3274 static int index;
3275 struct mii_bus *bus;
3276 int err;
3277
fad09c73
VD		 3278 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3279 mv88e6xxx_ppu_state_init(chip);
b516d453
AL		 3280
3281 if (np)
fad09c73 3282 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 3283
fad09c73 3284 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 3285 if (!bus)
3286 return -ENOMEM;
3287
fad09c73 3288 bus->priv = (void *)chip;
b516d453
AL		 3289 if (np) {
3290 bus->name = np->full_name;
3291 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3292 } else {
3293 bus->name = "mv88e6xxx SMI";
3294 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3295 }
3296
3297 bus->read = mv88e6xxx_mdio_read;
3298 bus->write = mv88e6xxx_mdio_write;
fad09c73 3299 bus->parent = chip->dev;
b516d453 3300
fad09c73
VD		 3301 if (chip->mdio_np)
3302 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 3303 else
3304 err = mdiobus_register(bus);
3305 if (err) {
fad09c73 3306 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3307 goto out;
3308 }
fad09c73 3309 chip->mdio_bus = bus;
b516d453
AL		 3310
3311 return 0;
3312
3313out:
fad09c73
VD		 3314 if (chip->mdio_np)
3315 of_node_put(chip->mdio_np);
b516d453
AL		 3316
3317 return err;
3318}
3319
fad09c73 3320static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3321
3322{
fad09c73 3323 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3324
3325 mdiobus_unregister(bus);
3326
fad09c73
VD		 3327 if (chip->mdio_np)
3328 of_node_put(chip->mdio_np);
b516d453
AL		 3329}
3330
c22995c5
GR		 3331#ifdef CONFIG_NET_DSA_HWMON
3332
3333static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3334{
fad09c73 3335 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
c22995c5
GR		 3336 int ret;
3337 int val;
3338
3339 *temp = 0;
3340
fad09c73 3341 mutex_lock(&chip->reg_lock);
c22995c5 3342
fad09c73 3343 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3344 if (ret < 0)
3345 goto error;
3346
3347 /* Enable temperature sensor */
fad09c73 3348 ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
c22995c5
GR		 3349 if (ret < 0)
3350 goto error;
3351
fad09c73 3352 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
c22995c5
GR		 3353 if (ret < 0)
3354 goto error;
3355
3356 /* Wait for temperature to stabilize */
3357 usleep_range(10000, 12000);
3358
fad09c73 3359 val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
c22995c5
GR		 3360 if (val < 0) {
3361 ret = val;
3362 goto error;
3363 }
3364
3365 /* Disable temperature sensor */
fad09c73 3366 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
c22995c5
GR		 3367 if (ret < 0)
3368 goto error;
3369
3370 *temp = ((val & 0x1f) - 5) * 5;
3371
3372error:
fad09c73
VD		 3373 mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3374 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3375 return ret;
3376}
3377
3378static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3379{
fad09c73
VD		 3380 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3381 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3382 int ret;
3383
3384 *temp = 0;
3385
03a4a540 3386 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
c22995c5
GR		 3387 if (ret < 0)
3388 return ret;
3389
3390 *temp = (ret & 0xff) - 25;
3391
3392 return 0;
3393}
3394
f81ec90f 3395static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3396{
fad09c73 3397 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
158bc065 3398
fad09c73 3399 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3400 return -EOPNOTSUPP;
3401
fad09c73 3402 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3403 return mv88e63xx_get_temp(ds, temp);
3404
3405 return mv88e61xx_get_temp(ds, temp);
3406}
3407
f81ec90f 3408static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3409{
fad09c73
VD		 3410 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3411 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3412 int ret;
3413
fad09c73 3414 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3415 return -EOPNOTSUPP;
3416
3417 *temp = 0;
3418
03a4a540 3419 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3420 if (ret < 0)
3421 return ret;
3422
3423 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3424
3425 return 0;
3426}
3427
f81ec90f 3428static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3429{
fad09c73
VD		 3430 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3431 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3432 int ret;
3433
fad09c73 3434 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3435 return -EOPNOTSUPP;
3436
03a4a540 3437 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3438 if (ret < 0)
3439 return ret;
3440 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
03a4a540
AL		 3441 return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3442 (ret & 0xe0ff) | (temp << 8));
c22995c5
GR		 3443}
3444
f81ec90f 3445static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3446{
fad09c73
VD		 3447 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3448 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3449 int ret;
3450
fad09c73 3451 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3452 return -EOPNOTSUPP;
3453
3454 *alarm = false;
3455
03a4a540 3456 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3457 if (ret < 0)
3458 return ret;
3459
3460 *alarm = !!(ret & 0x40);
3461
3462 return 0;
3463}
3464#endif /* CONFIG_NET_DSA_HWMON */
3465
855b1932
VD		 3466static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3467{
3468 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3469
3470 return chip->eeprom_len;
3471}
3472
3473static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3474 struct ethtool_eeprom *eeprom, u8 *data)
3475{
3476 unsigned int offset = eeprom->offset;
3477 unsigned int len = eeprom->len;
3478 u16 val;
3479 int err;
3480
3481 eeprom->len = 0;
3482
3483 if (offset & 1) {
3484 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3485 if (err)
3486 return err;
3487
3488 *data++ = (val >> 8) & 0xff;
3489
3490 offset++;
3491 len--;
3492 eeprom->len++;
3493 }
3494
3495 while (len >= 2) {
3496 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3497 if (err)
3498 return err;
3499
3500 *data++ = val & 0xff;
3501 *data++ = (val >> 8) & 0xff;
3502
3503 offset += 2;
3504 len -= 2;
3505 eeprom->len += 2;
3506 }
3507
3508 if (len) {
3509 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3510 if (err)
3511 return err;
3512
3513 *data++ = val & 0xff;
3514
3515 offset++;
3516 len--;
3517 eeprom->len++;
3518 }
3519
3520 return 0;
3521}
3522
3523static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3524 struct ethtool_eeprom *eeprom, u8 *data)
3525{
3526 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3527 int err;
3528
3529 mutex_lock(&chip->reg_lock);
3530
3531 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3532 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3533 else
3534 err = -EOPNOTSUPP;
3535
3536 mutex_unlock(&chip->reg_lock);
3537
3538 if (err)
3539 return err;
3540
3541 eeprom->magic = 0xc3ec4951;
3542
3543 return 0;
3544}
3545
3546static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3547 struct ethtool_eeprom *eeprom, u8 *data)
3548{
3549 unsigned int offset = eeprom->offset;
3550 unsigned int len = eeprom->len;
3551 u16 val;
3552 int err;
3553
3554 /* Ensure the RO WriteEn bit is set */
3555 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3556 if (err)
3557 return err;
3558
3559 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3560 return -EROFS;
3561
3562 eeprom->len = 0;
3563
3564 if (offset & 1) {
3565 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3566 if (err)
3567 return err;
3568
3569 val = (*data++ << 8) | (val & 0xff);
3570
3571 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3572 if (err)
3573 return err;
3574
3575 offset++;
3576 len--;
3577 eeprom->len++;
3578 }
3579
3580 while (len >= 2) {
3581 val = *data++;
3582 val |= *data++ << 8;
3583
3584 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3585 if (err)
3586 return err;
3587
3588 offset += 2;
3589 len -= 2;
3590 eeprom->len += 2;
3591 }
3592
3593 if (len) {
3594 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3595 if (err)
3596 return err;
3597
3598 val = (val & 0xff00) | *data++;
3599
3600 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3601 if (err)
3602 return err;
3603
3604 offset++;
3605 len--;
3606 eeprom->len++;
3607 }
3608
3609 return 0;
3610}
3611
3612static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3613 struct ethtool_eeprom *eeprom, u8 *data)
3614{
3615 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3616 int err;
3617
3618 if (eeprom->magic != 0xc3ec4951)
3619 return -EINVAL;
3620
3621 mutex_lock(&chip->reg_lock);
3622
3623 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3624 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3625 else
3626 err = -EOPNOTSUPP;
3627
3628 mutex_unlock(&chip->reg_lock);
3629
3630 return err;
3631}
3632
f81ec90f
VD		 3633static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3634 [MV88E6085] = {
3635 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3636 .family = MV88E6XXX_FAMILY_6097,
3637 .name = "Marvell 88E6085",
3638 .num_databases = 4096,
3639 .num_ports = 10,
9dddd478 3640 .port_base_addr = 0x10,
acddbd21 3641 .age_time_coeff = 15000,
f81ec90f
VD		 3642 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3643 },
3644
3645 [MV88E6095] = {
3646 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3647 .family = MV88E6XXX_FAMILY_6095,
3648 .name = "Marvell 88E6095/88E6095F",
3649 .num_databases = 256,
3650 .num_ports = 11,
9dddd478 3651 .port_base_addr = 0x10,
acddbd21 3652 .age_time_coeff = 15000,
f81ec90f
VD		 3653 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3654 },
3655
3656 [MV88E6123] = {
3657 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3658 .family = MV88E6XXX_FAMILY_6165,
3659 .name = "Marvell 88E6123",
3660 .num_databases = 4096,
3661 .num_ports = 3,
9dddd478 3662 .port_base_addr = 0x10,
acddbd21 3663 .age_time_coeff = 15000,
f81ec90f
VD		 3664 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3665 },
3666
3667 [MV88E6131] = {
3668 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3669 .family = MV88E6XXX_FAMILY_6185,
3670 .name = "Marvell 88E6131",
3671 .num_databases = 256,
3672 .num_ports = 8,
9dddd478 3673 .port_base_addr = 0x10,
acddbd21 3674 .age_time_coeff = 15000,
f81ec90f
VD		 3675 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3676 },
3677
3678 [MV88E6161] = {
3679 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3680 .family = MV88E6XXX_FAMILY_6165,
3681 .name = "Marvell 88E6161",
3682 .num_databases = 4096,
3683 .num_ports = 6,
9dddd478 3684 .port_base_addr = 0x10,
acddbd21 3685 .age_time_coeff = 15000,
f81ec90f
VD		 3686 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3687 },
3688
3689 [MV88E6165] = {
3690 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3691 .family = MV88E6XXX_FAMILY_6165,
3692 .name = "Marvell 88E6165",
3693 .num_databases = 4096,
3694 .num_ports = 6,
9dddd478 3695 .port_base_addr = 0x10,
acddbd21 3696 .age_time_coeff = 15000,
f81ec90f
VD		 3697 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3698 },
3699
3700 [MV88E6171] = {
3701 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3702 .family = MV88E6XXX_FAMILY_6351,
3703 .name = "Marvell 88E6171",
3704 .num_databases = 4096,
3705 .num_ports = 7,
9dddd478 3706 .port_base_addr = 0x10,
acddbd21 3707 .age_time_coeff = 15000,
f81ec90f
VD		 3708 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3709 },
3710
3711 [MV88E6172] = {
3712 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3713 .family = MV88E6XXX_FAMILY_6352,
3714 .name = "Marvell 88E6172",
3715 .num_databases = 4096,
3716 .num_ports = 7,
9dddd478 3717 .port_base_addr = 0x10,
acddbd21 3718 .age_time_coeff = 15000,
f81ec90f
VD		 3719 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3720 },
3721
3722 [MV88E6175] = {
3723 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3724 .family = MV88E6XXX_FAMILY_6351,
3725 .name = "Marvell 88E6175",
3726 .num_databases = 4096,
3727 .num_ports = 7,
9dddd478 3728 .port_base_addr = 0x10,
acddbd21 3729 .age_time_coeff = 15000,
f81ec90f
VD		 3730 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3731 },
3732
3733 [MV88E6176] = {
3734 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3735 .family = MV88E6XXX_FAMILY_6352,
3736 .name = "Marvell 88E6176",
3737 .num_databases = 4096,
3738 .num_ports = 7,
9dddd478 3739 .port_base_addr = 0x10,
acddbd21 3740 .age_time_coeff = 15000,
f81ec90f
VD		 3741 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3742 },
3743
3744 [MV88E6185] = {
3745 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3746 .family = MV88E6XXX_FAMILY_6185,
3747 .name = "Marvell 88E6185",
3748 .num_databases = 256,
3749 .num_ports = 10,
9dddd478 3750 .port_base_addr = 0x10,
acddbd21 3751 .age_time_coeff = 15000,
f81ec90f
VD		 3752 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3753 },
3754
3755 [MV88E6240] = {
3756 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3757 .family = MV88E6XXX_FAMILY_6352,
3758 .name = "Marvell 88E6240",
3759 .num_databases = 4096,
3760 .num_ports = 7,
9dddd478 3761 .port_base_addr = 0x10,
acddbd21 3762 .age_time_coeff = 15000,
f81ec90f
VD		 3763 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3764 },
3765
3766 [MV88E6320] = {
3767 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3768 .family = MV88E6XXX_FAMILY_6320,
3769 .name = "Marvell 88E6320",
3770 .num_databases = 4096,
3771 .num_ports = 7,
9dddd478 3772 .port_base_addr = 0x10,
acddbd21 3773 .age_time_coeff = 15000,
f81ec90f
VD		 3774 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3775 },
3776
3777 [MV88E6321] = {
3778 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3779 .family = MV88E6XXX_FAMILY_6320,
3780 .name = "Marvell 88E6321",
3781 .num_databases = 4096,
3782 .num_ports = 7,
9dddd478 3783 .port_base_addr = 0x10,
acddbd21 3784 .age_time_coeff = 15000,
f81ec90f
VD		 3785 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3786 },
3787
3788 [MV88E6350] = {
3789 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3790 .family = MV88E6XXX_FAMILY_6351,
3791 .name = "Marvell 88E6350",
3792 .num_databases = 4096,
3793 .num_ports = 7,
9dddd478 3794 .port_base_addr = 0x10,
acddbd21 3795 .age_time_coeff = 15000,
f81ec90f
VD		 3796 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3797 },
3798
3799 [MV88E6351] = {
3800 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3801 .family = MV88E6XXX_FAMILY_6351,
3802 .name = "Marvell 88E6351",
3803 .num_databases = 4096,
3804 .num_ports = 7,
9dddd478 3805 .port_base_addr = 0x10,
acddbd21 3806 .age_time_coeff = 15000,
f81ec90f
VD		 3807 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3808 },
3809
3810 [MV88E6352] = {
3811 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3812 .family = MV88E6XXX_FAMILY_6352,
3813 .name = "Marvell 88E6352",
3814 .num_databases = 4096,
3815 .num_ports = 7,
9dddd478 3816 .port_base_addr = 0x10,
acddbd21 3817 .age_time_coeff = 15000,
f81ec90f
VD		 3818 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3819 },
3820};
3821
5f7c0367 3822static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3823{
a439c061 3824 int i;
b9b37713 3825
5f7c0367
VD		 3826 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3827 if (mv88e6xxx_table[i].prod_num == prod_num)
3828 return &mv88e6xxx_table[i];
b9b37713 3829
b9b37713
VD		 3830 return NULL;
3831}
3832
fad09c73 3833static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3834{
3835 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3836 unsigned int prod_num, rev;
3837 u16 id;
3838 int err;
bc46a3d5 3839
8f6345b2
VD		 3840 mutex_lock(&chip->reg_lock);
3841 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3842 mutex_unlock(&chip->reg_lock);
3843 if (err)
3844 return err;
bc46a3d5
VD		 3845
3846 prod_num = (id & 0xfff0) >> 4;
3847 rev = id & 0x000f;
3848
3849 info = mv88e6xxx_lookup_info(prod_num);
3850 if (!info)
3851 return -ENODEV;
3852
caac8545 3853 /* Update the compatible info with the probed one */
fad09c73 3854 chip->info = info;
bc46a3d5 3855
fad09c73
VD		 3856 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3857 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3858
3859 return 0;
3860}
3861
fad09c73 3862static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3863{
fad09c73 3864 struct mv88e6xxx_chip *chip;
469d729f 3865
fad09c73
VD		 3866 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3867 if (!chip)
469d729f
VD		 3868 return NULL;
3869
fad09c73 3870 chip->dev = dev;
469d729f 3871
fad09c73 3872 mutex_init(&chip->reg_lock);
469d729f 3873
fad09c73 3874 return chip;
469d729f
VD		 3875}
3876
fad09c73 3877static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3878 struct mii_bus *bus, int sw_addr)
3879{
3880 /* ADDR[0] pin is unavailable externally and considered zero */
3881 if (sw_addr & 0x1)
3882 return -EINVAL;
3883
914b32f6 3884 if (sw_addr == 0)
fad09c73
VD		 3885 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3886 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3887 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3888 else
3889 return -EINVAL;
3890
fad09c73
VD		 3891 chip->bus = bus;
3892 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3893
3894 return 0;
3895}
3896
fcdce7d0
AL		 3897static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3898 struct device *host_dev, int sw_addr,
3899 void **priv)
a77d43f1 3900{
fad09c73 3901 struct mv88e6xxx_chip *chip;
a439c061 3902 struct mii_bus *bus;
b516d453 3903 int err;
a77d43f1 3904
a439c061 3905 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3906 if (!bus)
3907 return NULL;
3908
fad09c73
VD		 3909 chip = mv88e6xxx_alloc_chip(dsa_dev);
3910 if (!chip)
469d729f
VD		 3911 return NULL;
3912
caac8545 3913 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3914 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3915
fad09c73 3916 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3917 if (err)
3918 goto free;
3919
fad09c73 3920 err = mv88e6xxx_detect(chip);
bc46a3d5 3921 if (err)
469d729f 3922 goto free;
a439c061 3923
fad09c73 3924 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3925 if (err)
469d729f 3926 goto free;
b516d453 3927
fad09c73 3928 *priv = chip;
a439c061 3929
fad09c73 3930 return chip->info->name;
469d729f 3931free:
fad09c73 3932 devm_kfree(dsa_dev, chip);
469d729f
VD		 3933
3934 return NULL;
a77d43f1
AL		 3935}
3936
57d32310 3937static struct dsa_switch_driver mv88e6xxx_switch_driver = {
f81ec90f 3938 .tag_protocol = DSA_TAG_PROTO_EDSA,
fcdce7d0 3939 .probe = mv88e6xxx_drv_probe,
f81ec90f
VD		 3940 .setup = mv88e6xxx_setup,
3941 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3942 .adjust_link = mv88e6xxx_adjust_link,
3943 .get_strings = mv88e6xxx_get_strings,
3944 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3945 .get_sset_count = mv88e6xxx_get_sset_count,
3946 .set_eee = mv88e6xxx_set_eee,
3947 .get_eee = mv88e6xxx_get_eee,
3948#ifdef CONFIG_NET_DSA_HWMON
3949 .get_temp = mv88e6xxx_get_temp,
3950 .get_temp_limit = mv88e6xxx_get_temp_limit,
3951 .set_temp_limit = mv88e6xxx_set_temp_limit,
3952 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3953#endif
f8cd8753 3954 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3955 .get_eeprom = mv88e6xxx_get_eeprom,
3956 .set_eeprom = mv88e6xxx_set_eeprom,
3957 .get_regs_len = mv88e6xxx_get_regs_len,
3958 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3959 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3960 .port_bridge_join = mv88e6xxx_port_bridge_join,
3961 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3962 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3963 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3964 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3965 .port_vlan_add = mv88e6xxx_port_vlan_add,
3966 .port_vlan_del = mv88e6xxx_port_vlan_del,
3967 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3968 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3969 .port_fdb_add = mv88e6xxx_port_fdb_add,
3970 .port_fdb_del = mv88e6xxx_port_fdb_del,
3971 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3972};
3973
fad09c73 3974static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3975 struct device_node *np)
3976{
fad09c73 3977 struct device *dev = chip->dev;
b7e66a5f
VD		 3978 struct dsa_switch *ds;
3979
3980 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3981 if (!ds)
3982 return -ENOMEM;
3983
3984 ds->dev = dev;
fad09c73 3985 ds->priv = chip;
b7e66a5f
VD		 3986 ds->drv = &mv88e6xxx_switch_driver;
3987
3988 dev_set_drvdata(dev, ds);
3989
3990 return dsa_register_switch(ds, np);
3991}
3992
fad09c73 3993static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3994{
fad09c73 3995 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3996}
3997
57d32310 3998static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3999{
14c7b3c3 4000 struct device *dev = &mdiodev->dev;
f8cd8753 4001 struct device_node *np = dev->of_node;
caac8545 4002 const struct mv88e6xxx_info *compat_info;
fad09c73 4003 struct mv88e6xxx_chip *chip;
f8cd8753 4004 u32 eeprom_len;
52638f71 4005 int err;
14c7b3c3 4006
caac8545
VD		 4007 compat_info = of_device_get_match_data(dev);
4008 if (!compat_info)
4009 return -EINVAL;
4010
fad09c73
VD		 4011 chip = mv88e6xxx_alloc_chip(dev);
4012 if (!chip)
14c7b3c3
AL		 4013 return -ENOMEM;
4014
fad09c73 4015 chip->info = compat_info;
caac8545 4016
fad09c73 4017 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4018 if (err)
4019 return err;
14c7b3c3 4020
fad09c73 4021 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4022 if (err)
4023 return err;
14c7b3c3 4024
fad09c73
VD		 4025 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4026 if (IS_ERR(chip->reset))
4027 return PTR_ERR(chip->reset);
52638f71 4028
855b1932 4029 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
f8cd8753 4030 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4031 chip->eeprom_len = eeprom_len;
f8cd8753 4032
fad09c73 4033 err = mv88e6xxx_mdio_register(chip, np);
b516d453
AL		 4034 if (err)
4035 return err;
4036
fad09c73 4037 err = mv88e6xxx_register_switch(chip, np);
83c0afae 4038 if (err) {
fad09c73 4039 mv88e6xxx_mdio_unregister(chip);
83c0afae
AL		 4040 return err;
4041 }
4042
98e67308
BH		 4043 return 0;
4044}
14c7b3c3
AL		 4045
4046static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4047{
4048 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
fad09c73 4049 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
14c7b3c3 4050
fad09c73
VD		 4051 mv88e6xxx_unregister_switch(chip);
4052 mv88e6xxx_mdio_unregister(chip);
14c7b3c3
AL		 4053}
4054
4055static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4056 {
4057 .compatible = "marvell,mv88e6085",
4058 .data = &mv88e6xxx_table[MV88E6085],
4059 },
14c7b3c3
AL		 4060 { /* sentinel */ },
4061};
4062
4063MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4064
4065static struct mdio_driver mv88e6xxx_driver = {
4066 .probe = mv88e6xxx_probe,
4067 .remove = mv88e6xxx_remove,
4068 .mdiodrv.driver = {
4069 .name = "mv88e6085",
4070 .of_match_table = mv88e6xxx_of_match,
4071 },
4072};
4073
4074static int __init mv88e6xxx_init(void)
4075{
4076 register_switch_driver(&mv88e6xxx_switch_driver);
4077 return mdio_driver_register(&mv88e6xxx_driver);
4078}
98e67308
BH		 4079module_init(mv88e6xxx_init);
4080
4081static void __exit mv88e6xxx_cleanup(void)
4082{
14c7b3c3 4083 mdio_driver_unregister(&mv88e6xxx_driver);
f81ec90f 4084 unregister_switch_driver(&mv88e6xxx_switch_driver);
98e67308
BH		 4085}
4086module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4087
4088MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4089MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4090MODULE_LICENSE("GPL");
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