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net: dsa: support switchdev ageing time attr
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
b516d453 26#include <linux/of_mdio.h>
91da11f8 27#include <linux/netdevice.h>
c8c1b39a 28#include <linux/gpio/consumer.h>
91da11f8 29#include <linux/phy.h>
c8f0b869 30#include <net/dsa.h>
1f36faf2 31#include <net/switchdev.h>
91da11f8
LB		 32#include "mv88e6xxx.h"
33
fad09c73 34static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 35{
fad09c73
VD		 36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 38 dump_stack();
39 }
40}
41
914b32f6
VD		 42/* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
44 *
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
48 *
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 52 */
914b32f6 53
fad09c73 54static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 55 int addr, int reg, u16 *val)
56{
fad09c73 57 if (!chip->smi_ops)
914b32f6
VD		 58 return -EOPNOTSUPP;
59
fad09c73 60 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 61}
62
fad09c73 63static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 *val)
74{
75 int ret;
76
fad09c73 77 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 78 if (ret < 0)
79 return ret;
80
81 *val = ret & 0xffff;
82
83 return 0;
84}
85
fad09c73 86static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 87 int addr, int reg, u16 val)
88{
89 int ret;
90
fad09c73 91 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 92 if (ret < 0)
93 return ret;
94
95 return 0;
96}
97
98static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
99 .read = mv88e6xxx_smi_single_chip_read,
100 .write = mv88e6xxx_smi_single_chip_write,
101};
102
fad09c73 103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 104{
105 int ret;
106 int i;
107
108 for (i = 0; i < 16; i++) {
fad09c73 109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 110 if (ret < 0)
111 return ret;
112
cca8b133 113 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 114 return 0;
115 }
116
117 return -ETIMEDOUT;
118}
119
fad09c73 120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 121 int addr, int reg, u16 *val)
91da11f8
LB		 122{
123 int ret;
124
3675c8d7 125 /* Wait for the bus to become free. */
fad09c73 126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 127 if (ret < 0)
128 return ret;
129
3675c8d7 130 /* Transmit the read command. */
fad09c73 131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 133 if (ret < 0)
134 return ret;
135
3675c8d7 136 /* Wait for the read command to complete. */
fad09c73 137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 138 if (ret < 0)
139 return ret;
140
3675c8d7 141 /* Read the data. */
fad09c73 142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 143 if (ret < 0)
144 return ret;
145
914b32f6 146 *val = ret & 0xffff;
91da11f8 147
914b32f6 148 return 0;
8d6d09e7
GR		 149}
150
fad09c73 151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 152 int addr, int reg, u16 val)
91da11f8
LB		 153{
154 int ret;
155
3675c8d7 156 /* Wait for the bus to become free. */
fad09c73 157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 158 if (ret < 0)
159 return ret;
160
3675c8d7 161 /* Transmit the data to write. */
fad09c73 162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 163 if (ret < 0)
164 return ret;
165
3675c8d7 166 /* Transmit the write command. */
fad09c73 167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 169 if (ret < 0)
170 return ret;
171
3675c8d7 172 /* Wait for the write command to complete. */
fad09c73 173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 174 if (ret < 0)
175 return ret;
176
177 return 0;
178}
179
914b32f6
VD		 180static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
183};
184
fad09c73 185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 186 int addr, int reg, u16 *val)
187{
188 int err;
189
fad09c73 190 assert_reg_lock(chip);
914b32f6 191
fad09c73 192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 193 if (err)
194 return err;
195
fad09c73 196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 197 addr, reg, *val);
198
199 return 0;
200}
201
fad09c73 202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
914b32f6 203 int addr, int reg, u16 val)
91da11f8 204{
914b32f6
VD		 205 int err;
206
fad09c73 207 assert_reg_lock(chip);
91da11f8 208
fad09c73 209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 210 if (err)
211 return err;
212
fad09c73 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 214 addr, reg, val);
215
914b32f6
VD		 216 return 0;
217}
218
f22ab641
VD		 219/* Indirect write to single pointer-data register with an Update bit */
220static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
221 u16 update)
222{
223 u16 val;
224 int i, err;
225
226 /* Wait until the previous operation is completed */
227 for (i = 0; i < 16; ++i) {
228 err = mv88e6xxx_read(chip, addr, reg, &val);
229 if (err)
230 return err;
231
232 if (!(val & BIT(15)))
233 break;
234 }
235
236 if (i == 16)
237 return -ETIMEDOUT;
238
239 /* Set the Update bit to trigger a write operation */
240 val = BIT(15) | update;
241
242 return mv88e6xxx_write(chip, addr, reg, val);
243}
244
fad09c73 245static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
914b32f6
VD		 246{
247 u16 val;
248 int err;
249
fad09c73 250 err = mv88e6xxx_read(chip, addr, reg, &val);
914b32f6
VD		 251 if (err)
252 return err;
253
254 return val;
255}
256
fad09c73 257static int mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
914b32f6
VD		 258{
259 int ret;
260
fad09c73
VD		 261 mutex_lock(&chip->reg_lock);
262 ret = _mv88e6xxx_reg_read(chip, addr, reg);
263 mutex_unlock(&chip->reg_lock);
914b32f6
VD		 264
265 return ret;
266}
267
fad09c73 268static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
914b32f6
VD		 269 int reg, u16 val)
270{
fad09c73 271 return mv88e6xxx_write(chip, addr, reg, val);
8d6d09e7
GR		 272}
273
fad09c73 274static int mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
57d32310 275 int reg, u16 val)
8d6d09e7 276{
8d6d09e7
GR		 277 int ret;
278
fad09c73
VD		 279 mutex_lock(&chip->reg_lock);
280 ret = _mv88e6xxx_reg_write(chip, addr, reg, val);
281 mutex_unlock(&chip->reg_lock);
91da11f8
LB		 282
283 return ret;
284}
285
fad09c73 286static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
03a4a540 287 int addr, int regnum)
91da11f8
LB		 288{
289 if (addr >= 0)
fad09c73 290 return _mv88e6xxx_reg_read(chip, addr, regnum);
91da11f8
LB		 291 return 0xffff;
292}
293
fad09c73 294static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
03a4a540 295 int addr, int regnum, u16 val)
91da11f8
LB		 296{
297 if (addr >= 0)
fad09c73 298 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
91da11f8
LB		 299 return 0;
300}
301
fad09c73 302static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
2e5f0320
LB		 303{
304 int ret;
19b2f97e 305 unsigned long timeout;
2e5f0320 306
fad09c73 307 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 308 if (ret < 0)
309 return ret;
310
fad09c73 311 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
8c9983a2 312 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 313 if (ret)
314 return ret;
2e5f0320 315
19b2f97e
BG		 316 timeout = jiffies + 1 * HZ;
317 while (time_before(jiffies, timeout)) {
fad09c73 318 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 319 if (ret < 0)
320 return ret;
321
19b2f97e 322 usleep_range(1000, 2000);
cca8b133
AL		 323 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
324 GLOBAL_STATUS_PPU_POLLING)
85686581 325 return 0;
2e5f0320
LB		 326 }
327
328 return -ETIMEDOUT;
329}
330
fad09c73 331static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 332{
48ace4ef 333 int ret, err;
19b2f97e 334 unsigned long timeout;
2e5f0320 335
fad09c73 336 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 337 if (ret < 0)
338 return ret;
339
fad09c73 340 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
762eb67b 341 ret | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 342 if (err)
343 return err;
2e5f0320 344
19b2f97e
BG		 345 timeout = jiffies + 1 * HZ;
346 while (time_before(jiffies, timeout)) {
fad09c73 347 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 348 if (ret < 0)
349 return ret;
350
19b2f97e 351 usleep_range(1000, 2000);
cca8b133
AL		 352 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
353 GLOBAL_STATUS_PPU_POLLING)
85686581 354 return 0;
2e5f0320
LB		 355 }
356
357 return -ETIMEDOUT;
358}
359
360static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
361{
fad09c73 362 struct mv88e6xxx_chip *chip;
2e5f0320 363
fad09c73 364 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 365
fad09c73 366 mutex_lock(&chip->reg_lock);
762eb67b 367
fad09c73
VD		 368 if (mutex_trylock(&chip->ppu_mutex)) {
369 if (mv88e6xxx_ppu_enable(chip) == 0)
370 chip->ppu_disabled = 0;
371 mutex_unlock(&chip->ppu_mutex);
2e5f0320 372 }
762eb67b 373
fad09c73 374 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 375}
376
377static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
378{
fad09c73 379 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 380
fad09c73 381 schedule_work(&chip->ppu_work);
2e5f0320
LB		 382}
383
fad09c73 384static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 385{
2e5f0320
LB		 386 int ret;
387
fad09c73 388 mutex_lock(&chip->ppu_mutex);
2e5f0320 389
3675c8d7 390 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 391 * we can access the PHY registers. If it was already
392 * disabled, cancel the timer that is going to re-enable
393 * it.
394 */
fad09c73
VD		 395 if (!chip->ppu_disabled) {
396 ret = mv88e6xxx_ppu_disable(chip);
85686581 397 if (ret < 0) {
fad09c73 398 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 399 return ret;
400 }
fad09c73 401 chip->ppu_disabled = 1;
2e5f0320 402 } else {
fad09c73 403 del_timer(&chip->ppu_timer);
85686581 404 ret = 0;
2e5f0320
LB		 405 }
406
407 return ret;
408}
409
fad09c73 410static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 411{
3675c8d7 412 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 413 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
414 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 415}
416
fad09c73 417static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 418{
fad09c73
VD		 419 mutex_init(&chip->ppu_mutex);
420 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
421 init_timer(&chip->ppu_timer);
422 chip->ppu_timer.data = (unsigned long)chip;
423 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 424}
425
fad09c73 426static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
03a4a540 427 int regnum)
2e5f0320
LB		 428{
429 int ret;
430
fad09c73 431 ret = mv88e6xxx_ppu_access_get(chip);
2e5f0320 432 if (ret >= 0) {
fad09c73
VD		 433 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
434 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 435 }
436
437 return ret;
438}
439
fad09c73 440static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
03a4a540 441 int regnum, u16 val)
2e5f0320
LB		 442{
443 int ret;
444
fad09c73 445 ret = mv88e6xxx_ppu_access_get(chip);
2e5f0320 446 if (ret >= 0) {
fad09c73
VD		 447 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
448 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 449 }
450
451 return ret;
452}
2e5f0320 453
fad09c73 454static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 455{
fad09c73 456 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 457}
458
fad09c73 459static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 460{
fad09c73 461 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 462}
463
fad09c73 464static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 465{
fad09c73 466 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 467}
468
fad09c73 469static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 470{
fad09c73 471 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 472}
473
fad09c73 474static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 475{
fad09c73 476 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 477}
478
fad09c73 479static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 480{
fad09c73 481 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 482}
483
fad09c73 484static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 485{
fad09c73 486 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 487}
488
fad09c73 489static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 490{
fad09c73 491 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 492}
493
fad09c73 494static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
f74df0be 495{
fad09c73 496 return chip->info->num_databases;
f74df0be
VD		 497}
498
fad09c73 499static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
b426e5f7
VD		 500{
501 /* Does the device have dedicated FID registers for ATU and VTU ops? */
fad09c73
VD		 502 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
503 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
b426e5f7
VD		 504 return true;
505
506 return false;
507}
508
dea87024
AL		 509/* We expect the switch to perform auto negotiation if there is a real
510 * phy. However, in the case of a fixed link phy, we force the port
511 * settings from the fixed link settings.
512 */
f81ec90f
VD		 513static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
514 struct phy_device *phydev)
dea87024 515{
fad09c73 516 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49052871
AL		 517 u32 reg;
518 int ret;
dea87024
AL		 519
520 if (!phy_is_pseudo_fixed_link(phydev))
521 return;
522
fad09c73 523 mutex_lock(&chip->reg_lock);
dea87024 524
fad09c73 525 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 526 if (ret < 0)
527 goto out;
528
529 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
530 PORT_PCS_CTRL_FORCE_LINK |
531 PORT_PCS_CTRL_DUPLEX_FULL |
532 PORT_PCS_CTRL_FORCE_DUPLEX |
533 PORT_PCS_CTRL_UNFORCED);
534
535 reg |= PORT_PCS_CTRL_FORCE_LINK;
536 if (phydev->link)
57d32310 537 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 538
fad09c73 539 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 540 goto out;
541
542 switch (phydev->speed) {
543 case SPEED_1000:
544 reg |= PORT_PCS_CTRL_1000;
545 break;
546 case SPEED_100:
547 reg |= PORT_PCS_CTRL_100;
548 break;
549 case SPEED_10:
550 reg |= PORT_PCS_CTRL_10;
551 break;
552 default:
553 pr_info("Unknown speed");
554 goto out;
555 }
556
557 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
558 if (phydev->duplex == DUPLEX_FULL)
559 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
560
fad09c73
VD		 561 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
562 (port >= chip->info->num_ports - 2)) {
e7e72ac0
AL		 563 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
564 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
565 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
566 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
567 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
568 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
569 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
570 }
fad09c73 571 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 572
573out:
fad09c73 574 mutex_unlock(&chip->reg_lock);
dea87024
AL		 575}
576
fad09c73 577static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 578{
579 int ret;
580 int i;
581
582 for (i = 0; i < 10; i++) {
fad09c73 583 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 584 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 585 return 0;
586 }
587
588 return -ETIMEDOUT;
589}
590
fad09c73 591static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8
LB		 592{
593 int ret;
594
fad09c73 595 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 596 port = (port + 1) << 5;
597
3675c8d7 598 /* Snapshot the hardware statistics counters for this port. */
fad09c73 599 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 600 GLOBAL_STATS_OP_CAPTURE_PORT |
601 GLOBAL_STATS_OP_HIST_RX_TX | port);
602 if (ret < 0)
603 return ret;
91da11f8 604
3675c8d7 605 /* Wait for the snapshotting to complete. */
fad09c73 606 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 607 if (ret < 0)
608 return ret;
609
610 return 0;
611}
612
fad09c73 613static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 614 int stat, u32 *val)
91da11f8
LB		 615{
616 u32 _val;
617 int ret;
618
619 *val = 0;
620
fad09c73 621 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 622 GLOBAL_STATS_OP_READ_CAPTURED |
623 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 624 if (ret < 0)
625 return;
626
fad09c73 627 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 628 if (ret < 0)
629 return;
630
fad09c73 631 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 632 if (ret < 0)
633 return;
634
635 _val = ret << 16;
636
fad09c73 637 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 638 if (ret < 0)
639 return;
640
641 *val = _val | ret;
642}
643
e413e7e1 644static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 645 { "in_good_octets", 8, 0x00, BANK0, },
646 { "in_bad_octets", 4, 0x02, BANK0, },
647 { "in_unicast", 4, 0x04, BANK0, },
648 { "in_broadcasts", 4, 0x06, BANK0, },
649 { "in_multicasts", 4, 0x07, BANK0, },
650 { "in_pause", 4, 0x16, BANK0, },
651 { "in_undersize", 4, 0x18, BANK0, },
652 { "in_fragments", 4, 0x19, BANK0, },
653 { "in_oversize", 4, 0x1a, BANK0, },
654 { "in_jabber", 4, 0x1b, BANK0, },
655 { "in_rx_error", 4, 0x1c, BANK0, },
656 { "in_fcs_error", 4, 0x1d, BANK0, },
657 { "out_octets", 8, 0x0e, BANK0, },
658 { "out_unicast", 4, 0x10, BANK0, },
659 { "out_broadcasts", 4, 0x13, BANK0, },
660 { "out_multicasts", 4, 0x12, BANK0, },
661 { "out_pause", 4, 0x15, BANK0, },
662 { "excessive", 4, 0x11, BANK0, },
663 { "collisions", 4, 0x1e, BANK0, },
664 { "deferred", 4, 0x05, BANK0, },
665 { "single", 4, 0x14, BANK0, },
666 { "multiple", 4, 0x17, BANK0, },
667 { "out_fcs_error", 4, 0x03, BANK0, },
668 { "late", 4, 0x1f, BANK0, },
669 { "hist_64bytes", 4, 0x08, BANK0, },
670 { "hist_65_127bytes", 4, 0x09, BANK0, },
671 { "hist_128_255bytes", 4, 0x0a, BANK0, },
672 { "hist_256_511bytes", 4, 0x0b, BANK0, },
673 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
674 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
675 { "sw_in_discards", 4, 0x10, PORT, },
676 { "sw_in_filtered", 2, 0x12, PORT, },
677 { "sw_out_filtered", 2, 0x13, PORT, },
678 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
679 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
680 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
682 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
683 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
684 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
685 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
686 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
687 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
688 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
689 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
690 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
691 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
692 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
693 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
694 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
695 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
696 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
697 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
703 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 704};
705
fad09c73 706static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 707 struct mv88e6xxx_hw_stat *stat)
e413e7e1 708{
f5e2ed02
AL		 709 switch (stat->type) {
710 case BANK0:
e413e7e1 711 return true;
f5e2ed02 712 case BANK1:
fad09c73 713 return mv88e6xxx_6320_family(chip);
f5e2ed02 714 case PORT:
fad09c73
VD		 715 return mv88e6xxx_6095_family(chip) ||
716 mv88e6xxx_6185_family(chip) ||
717 mv88e6xxx_6097_family(chip) ||
718 mv88e6xxx_6165_family(chip) ||
719 mv88e6xxx_6351_family(chip) ||
720 mv88e6xxx_6352_family(chip);
91da11f8 721 }
f5e2ed02 722 return false;
91da11f8
LB		 723}
724
fad09c73 725static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 726 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 727 int port)
728{
80c4627b
AL		 729 u32 low;
730 u32 high = 0;
731 int ret;
732 u64 value;
733
f5e2ed02
AL		 734 switch (s->type) {
735 case PORT:
fad09c73 736 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
80c4627b
AL		 737 if (ret < 0)
738 return UINT64_MAX;
739
740 low = ret;
741 if (s->sizeof_stat == 4) {
fad09c73 742 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
f5e2ed02 743 s->reg + 1);
80c4627b
AL		 744 if (ret < 0)
745 return UINT64_MAX;
746 high = ret;
747 }
f5e2ed02
AL		 748 break;
749 case BANK0:
750 case BANK1:
fad09c73 751 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 752 if (s->sizeof_stat == 8)
fad09c73 753 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 754 }
755 value = (((u64)high) << 16) | low;
756 return value;
757}
758
f81ec90f
VD		 759static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
760 uint8_t *data)
91da11f8 761{
fad09c73 762 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 763 struct mv88e6xxx_hw_stat *stat;
764 int i, j;
91da11f8 765
f5e2ed02
AL		 766 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
767 stat = &mv88e6xxx_hw_stats[i];
fad09c73 768 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 769 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
770 ETH_GSTRING_LEN);
771 j++;
772 }
91da11f8 773 }
e413e7e1
AL		 774}
775
f81ec90f 776static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 777{
fad09c73 778 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 779 struct mv88e6xxx_hw_stat *stat;
780 int i, j;
781
782 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
783 stat = &mv88e6xxx_hw_stats[i];
fad09c73 784 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 785 j++;
786 }
787 return j;
e413e7e1
AL		 788}
789
f81ec90f
VD		 790static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
791 uint64_t *data)
e413e7e1 792{
fad09c73 793 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 794 struct mv88e6xxx_hw_stat *stat;
795 int ret;
796 int i, j;
797
fad09c73 798 mutex_lock(&chip->reg_lock);
f5e2ed02 799
fad09c73 800 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 801 if (ret < 0) {
fad09c73 802 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 803 return;
804 }
805 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
806 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 807 if (mv88e6xxx_has_stat(chip, stat)) {
808 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 809 j++;
810 }
811 }
812
fad09c73 813 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 814}
815
f81ec90f 816static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 817{
818 return 32 * sizeof(u16);
819}
820
f81ec90f
VD		 821static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
822 struct ethtool_regs *regs, void *_p)
a1ab91f3 823{
fad09c73 824 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
a1ab91f3
GR		 825 u16 *p = _p;
826 int i;
827
828 regs->version = 0;
829
830 memset(p, 0xff, 32 * sizeof(u16));
831
fad09c73 832 mutex_lock(&chip->reg_lock);
23062513 833
a1ab91f3
GR		 834 for (i = 0; i < 32; i++) {
835 int ret;
836
fad09c73 837 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
a1ab91f3
GR		 838 if (ret >= 0)
839 p[i] = ret;
840 }
23062513 841
fad09c73 842 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 843}
844
fad09c73 845static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
3898c148 846 u16 mask)
f3044683
AL		 847{
848 unsigned long timeout = jiffies + HZ / 10;
849
850 while (time_before(jiffies, timeout)) {
851 int ret;
852
fad09c73 853 ret = _mv88e6xxx_reg_read(chip, reg, offset);
3898c148
AL		 854 if (ret < 0)
855 return ret;
f3044683
AL		 856 if (!(ret & mask))
857 return 0;
858
859 usleep_range(1000, 2000);
860 }
861 return -ETIMEDOUT;
862}
863
fad09c73 864static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg,
158bc065 865 int offset, u16 mask)
3898c148 866{
3898c148
AL		 867 int ret;
868
fad09c73
VD		 869 mutex_lock(&chip->reg_lock);
870 ret = _mv88e6xxx_wait(chip, reg, offset, mask);
871 mutex_unlock(&chip->reg_lock);
3898c148
AL		 872
873 return ret;
874}
875
fad09c73 876static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
f3044683 877{
fad09c73 878 return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148 879 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 880}
881
d24645be 882static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
f3044683 883{
fad09c73 884 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
158bc065 885
fad09c73 886 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 887 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 888}
889
d24645be 890static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
f3044683 891{
fad09c73 892 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
158bc065 893
fad09c73 894 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 895 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 896}
897
d24645be
VD		 898static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
899{
fad09c73 900 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
d24645be
VD		 901 int ret;
902
fad09c73 903 mutex_lock(&chip->eeprom_mutex);
d24645be 904
fad09c73 905 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
d24645be
VD		 906 GLOBAL2_EEPROM_OP_READ |
907 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
908 if (ret < 0)
909 goto error;
910
911 ret = mv88e6xxx_eeprom_busy_wait(ds);
912 if (ret < 0)
913 goto error;
914
fad09c73 915 ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
d24645be 916error:
fad09c73 917 mutex_unlock(&chip->eeprom_mutex);
d24645be
VD		 918 return ret;
919}
920
f8cd8753
AL		 921static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
922{
fad09c73 923 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f8cd8753 924
fad09c73
VD		 925 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
926 return chip->eeprom_len;
f8cd8753
AL		 927
928 return 0;
929}
930
f81ec90f
VD		 931static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
932 struct ethtool_eeprom *eeprom, u8 *data)
d24645be 933{
fad09c73 934 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
d24645be
VD		 935 int offset;
936 int len;
937 int ret;
938
fad09c73 939 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
d24645be
VD		 940 return -EOPNOTSUPP;
941
942 offset = eeprom->offset;
943 len = eeprom->len;
944 eeprom->len = 0;
945
946 eeprom->magic = 0xc3ec4951;
947
948 ret = mv88e6xxx_eeprom_load_wait(ds);
949 if (ret < 0)
950 return ret;
951
952 if (offset & 1) {
953 int word;
954
955 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
956 if (word < 0)
957 return word;
958
959 *data++ = (word >> 8) & 0xff;
960
961 offset++;
962 len--;
963 eeprom->len++;
964 }
965
966 while (len >= 2) {
967 int word;
968
969 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
970 if (word < 0)
971 return word;
972
973 *data++ = word & 0xff;
974 *data++ = (word >> 8) & 0xff;
975
976 offset += 2;
977 len -= 2;
978 eeprom->len += 2;
979 }
980
981 if (len) {
982 int word;
983
984 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
985 if (word < 0)
986 return word;
987
988 *data++ = word & 0xff;
989
990 offset++;
991 len--;
992 eeprom->len++;
993 }
994
995 return 0;
996}
997
998static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
999{
fad09c73 1000 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
d24645be
VD		 1001 int ret;
1002
fad09c73 1003 ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
d24645be
VD		 1004 if (ret < 0)
1005 return ret;
1006
1007 if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
1008 return -EROFS;
1009
1010 return 0;
1011}
1012
1013static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
1014 u16 data)
1015{
fad09c73 1016 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
d24645be
VD		 1017 int ret;
1018
fad09c73 1019 mutex_lock(&chip->eeprom_mutex);
d24645be 1020
fad09c73 1021 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
d24645be
VD		 1022 if (ret < 0)
1023 goto error;
1024
fad09c73 1025 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
d24645be
VD		 1026 GLOBAL2_EEPROM_OP_WRITE |
1027 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
1028 if (ret < 0)
1029 goto error;
1030
1031 ret = mv88e6xxx_eeprom_busy_wait(ds);
1032error:
fad09c73 1033 mutex_unlock(&chip->eeprom_mutex);
d24645be
VD		 1034 return ret;
1035}
1036
f81ec90f
VD		 1037static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
1038 struct ethtool_eeprom *eeprom, u8 *data)
d24645be 1039{
fad09c73 1040 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
d24645be
VD		 1041 int offset;
1042 int ret;
1043 int len;
1044
fad09c73 1045 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
d24645be
VD		 1046 return -EOPNOTSUPP;
1047
1048 if (eeprom->magic != 0xc3ec4951)
1049 return -EINVAL;
1050
1051 ret = mv88e6xxx_eeprom_is_readonly(ds);
1052 if (ret)
1053 return ret;
1054
1055 offset = eeprom->offset;
1056 len = eeprom->len;
1057 eeprom->len = 0;
1058
1059 ret = mv88e6xxx_eeprom_load_wait(ds);
1060 if (ret < 0)
1061 return ret;
1062
1063 if (offset & 1) {
1064 int word;
1065
1066 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1067 if (word < 0)
1068 return word;
1069
1070 word = (*data++ << 8) | (word & 0xff);
1071
1072 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1073 if (ret < 0)
1074 return ret;
1075
1076 offset++;
1077 len--;
1078 eeprom->len++;
1079 }
1080
1081 while (len >= 2) {
1082 int word;
1083
1084 word = *data++;
1085 word |= *data++ << 8;
1086
1087 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1088 if (ret < 0)
1089 return ret;
1090
1091 offset += 2;
1092 len -= 2;
1093 eeprom->len += 2;
1094 }
1095
1096 if (len) {
1097 int word;
1098
1099 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1100 if (word < 0)
1101 return word;
1102
1103 word = (word & 0xff00) | *data++;
1104
1105 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1106 if (ret < 0)
1107 return ret;
1108
1109 offset++;
1110 len--;
1111 eeprom->len++;
1112 }
1113
1114 return 0;
1115}
1116
fad09c73 1117static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1118{
fad09c73 1119 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
cca8b133 1120 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1121}
1122
fad09c73 1123static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
158bc065 1124 int addr, int regnum)
f3044683
AL		 1125{
1126 int ret;
1127
fad09c73 1128 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1129 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1130 regnum);
1131 if (ret < 0)
1132 return ret;
f3044683 1133
fad09c73 1134 ret = mv88e6xxx_mdio_wait(chip);
f3044683
AL		 1135 if (ret < 0)
1136 return ret;
1137
fad09c73 1138 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
158bc065
AL		 1139
1140 return ret;
f3044683
AL		 1141}
1142
fad09c73 1143static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
158bc065 1144 int addr, int regnum, u16 val)
f3044683 1145{
3898c148
AL		 1146 int ret;
1147
fad09c73 1148 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
3898c148
AL		 1149 if (ret < 0)
1150 return ret;
f3044683 1151
fad09c73 1152 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1153 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1154 regnum);
1155
fad09c73 1156 return mv88e6xxx_mdio_wait(chip);
f3044683
AL		 1157}
1158
f81ec90f
VD		 1159static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1160 struct ethtool_eee *e)
11b3b45d 1161{
fad09c73 1162 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
11b3b45d
GR		 1163 int reg;
1164
fad09c73 1165 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1166 return -EOPNOTSUPP;
1167
fad09c73 1168 mutex_lock(&chip->reg_lock);
2f40c698 1169
fad09c73 1170 reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
11b3b45d 1171 if (reg < 0)
2f40c698 1172 goto out;
11b3b45d
GR		 1173
1174 e->eee_enabled = !!(reg & 0x0200);
1175 e->tx_lpi_enabled = !!(reg & 0x0100);
1176
fad09c73 1177 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
11b3b45d 1178 if (reg < 0)
2f40c698 1179 goto out;
11b3b45d 1180
cca8b133 1181 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1182 reg = 0;
11b3b45d 1183
2f40c698 1184out:
fad09c73 1185 mutex_unlock(&chip->reg_lock);
2f40c698 1186 return reg;
11b3b45d
GR		 1187}
1188
f81ec90f
VD		 1189static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1190 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1191{
fad09c73 1192 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2f40c698 1193 int reg;
11b3b45d
GR		 1194 int ret;
1195
fad09c73 1196 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1197 return -EOPNOTSUPP;
1198
fad09c73 1199 mutex_lock(&chip->reg_lock);
11b3b45d 1200
fad09c73 1201 ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
2f40c698
AL		 1202 if (ret < 0)
1203 goto out;
1204
1205 reg = ret & ~0x0300;
1206 if (e->eee_enabled)
1207 reg |= 0x0200;
1208 if (e->tx_lpi_enabled)
1209 reg |= 0x0100;
1210
fad09c73 1211 ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
2f40c698 1212out:
fad09c73 1213 mutex_unlock(&chip->reg_lock);
2f40c698
AL		 1214
1215 return ret;
11b3b45d
GR		 1216}
1217
fad09c73 1218static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2
GR		 1219{
1220 int ret;
1221
fad09c73
VD		 1222 if (mv88e6xxx_has_fid_reg(chip)) {
1223 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
1224 fid);
b426e5f7
VD		 1225 if (ret < 0)
1226 return ret;
fad09c73 1227 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1228 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
fad09c73 1229 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 1230 if (ret < 0)
1231 return ret;
1232
fad09c73 1233 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 1234 (ret & 0xfff) |
1235 ((fid << 8) & 0xf000));
1236 if (ret < 0)
1237 return ret;
1238
1239 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1240 cmd |= fid & 0xf;
b426e5f7
VD		 1241 }
1242
fad09c73 1243 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1244 if (ret < 0)
1245 return ret;
1246
fad09c73 1247 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1248}
1249
fad09c73 1250static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1251 struct mv88e6xxx_atu_entry *entry)
1252{
1253 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1254
1255 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1256 unsigned int mask, shift;
1257
1258 if (entry->trunk) {
1259 data |= GLOBAL_ATU_DATA_TRUNK;
1260 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1261 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1262 } else {
1263 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1264 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1265 }
1266
1267 data |= (entry->portv_trunkid << shift) & mask;
1268 }
1269
fad09c73 1270 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1271}
1272
fad09c73 1273static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1274 struct mv88e6xxx_atu_entry *entry,
1275 bool static_too)
facd95b2 1276{
7fb5e755
VD		 1277 int op;
1278 int err;
facd95b2 1279
fad09c73 1280 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1281 if (err)
1282 return err;
facd95b2 1283
fad09c73 1284 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1285 if (err)
1286 return err;
1287
1288 if (entry->fid) {
7fb5e755
VD		 1289 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1290 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1291 } else {
1292 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1293 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1294 }
1295
fad09c73 1296 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1297}
1298
fad09c73 1299static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1300 u16 fid, bool static_too)
7fb5e755
VD		 1301{
1302 struct mv88e6xxx_atu_entry entry = {
1303 .fid = fid,
1304 .state = 0, /* EntryState bits must be 0 */
1305 };
70cc99d1 1306
fad09c73 1307 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1308}
1309
fad09c73 1310static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1311 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1312{
1313 struct mv88e6xxx_atu_entry entry = {
1314 .trunk = false,
1315 .fid = fid,
1316 };
1317
1318 /* EntryState bits must be 0xF */
1319 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1320
1321 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1322 entry.portv_trunkid = (to_port & 0x0f) << 4;
1323 entry.portv_trunkid |= from_port & 0x0f;
1324
fad09c73 1325 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1326}
1327
fad09c73 1328static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1329 int port, bool static_too)
9f4d55d2
VD		 1330{
1331 /* Destination port 0xF means remove the entries */
fad09c73 1332 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1333}
1334
2d9deae4
VD		 1335static const char * const mv88e6xxx_port_state_names[] = {
1336 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1337 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1338 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1339 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1340};
1341
fad09c73 1342static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1343 u8 state)
facd95b2 1344{
fad09c73 1345 struct dsa_switch *ds = chip->ds;
c3ffe6d2 1346 int reg, ret = 0;
facd95b2
GR		 1347 u8 oldstate;
1348
fad09c73 1349 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1350 if (reg < 0)
1351 return reg;
facd95b2 1352
cca8b133 1353 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1354
facd95b2
GR		 1355 if (oldstate != state) {
1356 /* Flush forwarding database if we're moving a port
1357 * from Learning or Forwarding state to Disabled or
1358 * Blocking or Listening state.
1359 */
2d9deae4 1360 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
57d32310
VD		 1361 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1362 (state == PORT_CONTROL_STATE_DISABLED ||
1363 state == PORT_CONTROL_STATE_BLOCKING)) {
fad09c73 1364 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
facd95b2 1365 if (ret)
2d9deae4 1366 return ret;
facd95b2 1367 }
2d9deae4 1368
cca8b133 1369 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
fad09c73 1370 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
cca8b133 1371 reg);
2d9deae4
VD		 1372 if (ret)
1373 return ret;
1374
c8b09808 1375 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
2d9deae4
VD		 1376 mv88e6xxx_port_state_names[state],
1377 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1378 }
1379
facd95b2
GR		 1380 return ret;
1381}
1382
fad09c73 1383static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1384{
fad09c73
VD		 1385 struct net_device *bridge = chip->ports[port].bridge_dev;
1386 const u16 mask = (1 << chip->info->num_ports) - 1;
1387 struct dsa_switch *ds = chip->ds;
b7666efe 1388 u16 output_ports = 0;
ede8098d 1389 int reg;
b7666efe
VD		 1390 int i;
1391
1392 /* allow CPU port or DSA link(s) to send frames to every port */
1393 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1394 output_ports = mask;
1395 } else {
fad09c73 1396 for (i = 0; i < chip->info->num_ports; ++i) {
b7666efe 1397 /* allow sending frames to every group member */
fad09c73 1398 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1399 output_ports |= BIT(i);
1400
1401 /* allow sending frames to CPU port and DSA link(s) */
1402 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1403 output_ports |= BIT(i);
1404 }
1405 }
1406
1407 /* prevent frames from going back out of the port they came in on */
1408 output_ports &= ~BIT(port);
facd95b2 1409
fad09c73 1410 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1411 if (reg < 0)
1412 return reg;
facd95b2 1413
ede8098d
VD		 1414 reg &= ~mask;
1415 reg |= output_ports & mask;
facd95b2 1416
fad09c73 1417 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1418}
1419
f81ec90f
VD		 1420static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1421 u8 state)
facd95b2 1422{
fad09c73 1423 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
facd95b2 1424 int stp_state;
553eb544 1425 int err;
facd95b2
GR		 1426
1427 switch (state) {
1428 case BR_STATE_DISABLED:
cca8b133 1429 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1430 break;
1431 case BR_STATE_BLOCKING:
1432 case BR_STATE_LISTENING:
cca8b133 1433 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1434 break;
1435 case BR_STATE_LEARNING:
cca8b133 1436 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1437 break;
1438 case BR_STATE_FORWARDING:
1439 default:
cca8b133 1440 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1441 break;
1442 }
1443
fad09c73
VD		 1444 mutex_lock(&chip->reg_lock);
1445 err = _mv88e6xxx_port_state(chip, port, stp_state);
1446 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1447
1448 if (err)
c8b09808
AL		 1449 netdev_err(ds->ports[port].netdev,
1450 "failed to update state to %s\n",
553eb544 1451 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1452}
1453
fad09c73 1454static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1455 u16 *new, u16 *old)
76e398a6 1456{
fad09c73 1457 struct dsa_switch *ds = chip->ds;
5da96031 1458 u16 pvid;
76e398a6
VD		 1459 int ret;
1460
fad09c73 1461 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1462 if (ret < 0)
1463 return ret;
1464
5da96031
VD		 1465 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1466
1467 if (new) {
1468 ret &= ~PORT_DEFAULT_VLAN_MASK;
1469 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1470
fad09c73 1471 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
5da96031
VD		 1472 PORT_DEFAULT_VLAN, ret);
1473 if (ret < 0)
1474 return ret;
1475
c8b09808
AL		 1476 netdev_dbg(ds->ports[port].netdev,
1477 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1478 }
1479
1480 if (old)
1481 *old = pvid;
76e398a6
VD		 1482
1483 return 0;
1484}
1485
fad09c73 1486static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1487 int port, u16 *pvid)
5da96031 1488{
fad09c73 1489 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1490}
1491
fad09c73 1492static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1493 int port, u16 pvid)
0d3b33e6 1494{
fad09c73 1495 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1496}
1497
fad09c73 1498static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1499{
fad09c73 1500 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
6b17e864
VD		 1501 GLOBAL_VTU_OP_BUSY);
1502}
1503
fad09c73 1504static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864
VD		 1505{
1506 int ret;
1507
fad09c73 1508 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1509 if (ret < 0)
1510 return ret;
1511
fad09c73 1512 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1513}
1514
fad09c73 1515static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1516{
1517 int ret;
1518
fad09c73 1519 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1520 if (ret < 0)
1521 return ret;
1522
fad09c73 1523 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1524}
1525
fad09c73 1526static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1527 struct mv88e6xxx_vtu_stu_entry *entry,
1528 unsigned int nibble_offset)
1529{
b8fee957
VD		 1530 u16 regs[3];
1531 int i;
1532 int ret;
1533
1534 for (i = 0; i < 3; ++i) {
fad09c73 1535 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1536 GLOBAL_VTU_DATA_0_3 + i);
1537 if (ret < 0)
1538 return ret;
1539
1540 regs[i] = ret;
1541 }
1542
fad09c73 1543 for (i = 0; i < chip->info->num_ports; ++i) {
b8fee957
VD		 1544 unsigned int shift = (i % 4) * 4 + nibble_offset;
1545 u16 reg = regs[i / 4];
1546
1547 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1548 }
1549
1550 return 0;
1551}
1552
fad09c73 1553static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1554 struct mv88e6xxx_vtu_stu_entry *entry)
1555{
fad09c73 1556 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1557}
1558
fad09c73 1559static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1560 struct mv88e6xxx_vtu_stu_entry *entry)
1561{
fad09c73 1562 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1563}
1564
fad09c73 1565static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1566 struct mv88e6xxx_vtu_stu_entry *entry,
1567 unsigned int nibble_offset)
1568{
7dad08d7
VD		 1569 u16 regs[3] = { 0 };
1570 int i;
1571 int ret;
1572
fad09c73 1573 for (i = 0; i < chip->info->num_ports; ++i) {
7dad08d7
VD		 1574 unsigned int shift = (i % 4) * 4 + nibble_offset;
1575 u8 data = entry->data[i];
1576
1577 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1578 }
1579
1580 for (i = 0; i < 3; ++i) {
fad09c73 1581 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
7dad08d7
VD		 1582 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1583 if (ret < 0)
1584 return ret;
1585 }
1586
1587 return 0;
1588}
1589
fad09c73 1590static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1591 struct mv88e6xxx_vtu_stu_entry *entry)
1592{
fad09c73 1593 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1594}
1595
fad09c73 1596static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1597 struct mv88e6xxx_vtu_stu_entry *entry)
1598{
fad09c73 1599 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1600}
1601
fad09c73 1602static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1603{
fad09c73 1604 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1605 vid & GLOBAL_VTU_VID_MASK);
1606}
1607
fad09c73 1608static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1609 struct mv88e6xxx_vtu_stu_entry *entry)
1610{
1611 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1612 int ret;
1613
fad09c73 1614 ret = _mv88e6xxx_vtu_wait(chip);
b8fee957
VD		 1615 if (ret < 0)
1616 return ret;
1617
fad09c73 1618 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1619 if (ret < 0)
1620 return ret;
1621
fad09c73 1622 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1623 if (ret < 0)
1624 return ret;
1625
1626 next.vid = ret & GLOBAL_VTU_VID_MASK;
1627 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1628
1629 if (next.valid) {
fad09c73 1630 ret = mv88e6xxx_vtu_data_read(chip, &next);
b8fee957
VD		 1631 if (ret < 0)
1632 return ret;
1633
fad09c73
VD		 1634 if (mv88e6xxx_has_fid_reg(chip)) {
1635 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1636 GLOBAL_VTU_FID);
1637 if (ret < 0)
1638 return ret;
1639
1640 next.fid = ret & GLOBAL_VTU_FID_MASK;
fad09c73 1641 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1642 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1643 * VTU DBNum[3:0] are located in VTU Operation 3:0
1644 */
fad09c73 1645 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
11ea809f
VD		 1646 GLOBAL_VTU_OP);
1647 if (ret < 0)
1648 return ret;
1649
1650 next.fid = (ret & 0xf00) >> 4;
1651 next.fid |= ret & 0xf;
2e7bd5ef 1652 }
b8fee957 1653
fad09c73
VD		 1654 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1655 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1656 GLOBAL_VTU_SID);
1657 if (ret < 0)
1658 return ret;
1659
1660 next.sid = ret & GLOBAL_VTU_SID_MASK;
1661 }
1662 }
1663
1664 *entry = next;
1665 return 0;
1666}
1667
f81ec90f
VD		 1668static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1669 struct switchdev_obj_port_vlan *vlan,
1670 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1671{
fad09c73 1672 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
ceff5eff
VD		 1673 struct mv88e6xxx_vtu_stu_entry next;
1674 u16 pvid;
1675 int err;
1676
fad09c73 1677 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1678 return -EOPNOTSUPP;
1679
fad09c73 1680 mutex_lock(&chip->reg_lock);
ceff5eff 1681
fad09c73 1682 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1683 if (err)
1684 goto unlock;
1685
fad09c73 1686 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1687 if (err)
1688 goto unlock;
1689
1690 do {
fad09c73 1691 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1692 if (err)
1693 break;
1694
1695 if (!next.valid)
1696 break;
1697
1698 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1699 continue;
1700
1701 /* reinit and dump this VLAN obj */
57d32310
VD		 1702 vlan->vid_begin = next.vid;
1703 vlan->vid_end = next.vid;
ceff5eff
VD		 1704 vlan->flags = 0;
1705
1706 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1707 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1708
1709 if (next.vid == pvid)
1710 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1711
1712 err = cb(&vlan->obj);
1713 if (err)
1714 break;
1715 } while (next.vid < GLOBAL_VTU_VID_MASK);
1716
1717unlock:
fad09c73 1718 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1719
1720 return err;
1721}
1722
fad09c73 1723static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1724 struct mv88e6xxx_vtu_stu_entry *entry)
1725{
11ea809f 1726 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1727 u16 reg = 0;
1728 int ret;
1729
fad09c73 1730 ret = _mv88e6xxx_vtu_wait(chip);
7dad08d7
VD		 1731 if (ret < 0)
1732 return ret;
1733
1734 if (!entry->valid)
1735 goto loadpurge;
1736
1737 /* Write port member tags */
fad09c73 1738 ret = mv88e6xxx_vtu_data_write(chip, entry);
7dad08d7
VD		 1739 if (ret < 0)
1740 return ret;
1741
fad09c73 1742 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1743 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73
VD		 1744 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1745 reg);
7dad08d7
VD		 1746 if (ret < 0)
1747 return ret;
b426e5f7 1748 }
7dad08d7 1749
fad09c73 1750 if (mv88e6xxx_has_fid_reg(chip)) {
7dad08d7 1751 reg = entry->fid & GLOBAL_VTU_FID_MASK;
fad09c73
VD		 1752 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1753 reg);
7dad08d7
VD		 1754 if (ret < 0)
1755 return ret;
fad09c73 1756 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1757 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1758 * VTU DBNum[3:0] are located in VTU Operation 3:0
1759 */
1760 op |= (entry->fid & 0xf0) << 8;
1761 op |= entry->fid & 0xf;
7dad08d7
VD		 1762 }
1763
1764 reg = GLOBAL_VTU_VID_VALID;
1765loadpurge:
1766 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
fad09c73 1767 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1768 if (ret < 0)
1769 return ret;
1770
fad09c73 1771 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1772}
1773
fad09c73 1774static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
0d3b33e6
VD		 1775 struct mv88e6xxx_vtu_stu_entry *entry)
1776{
1777 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1778 int ret;
1779
fad09c73 1780 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1781 if (ret < 0)
1782 return ret;
1783
fad09c73 1784 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1785 sid & GLOBAL_VTU_SID_MASK);
1786 if (ret < 0)
1787 return ret;
1788
fad09c73 1789 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1790 if (ret < 0)
1791 return ret;
1792
fad09c73 1793 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1794 if (ret < 0)
1795 return ret;
1796
1797 next.sid = ret & GLOBAL_VTU_SID_MASK;
1798
fad09c73 1799 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1800 if (ret < 0)
1801 return ret;
1802
1803 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1804
1805 if (next.valid) {
fad09c73 1806 ret = mv88e6xxx_stu_data_read(chip, &next);
0d3b33e6
VD		 1807 if (ret < 0)
1808 return ret;
1809 }
1810
1811 *entry = next;
1812 return 0;
1813}
1814
fad09c73 1815static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
0d3b33e6
VD		 1816 struct mv88e6xxx_vtu_stu_entry *entry)
1817{
1818 u16 reg = 0;
1819 int ret;
1820
fad09c73 1821 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1822 if (ret < 0)
1823 return ret;
1824
1825 if (!entry->valid)
1826 goto loadpurge;
1827
1828 /* Write port states */
fad09c73 1829 ret = mv88e6xxx_stu_data_write(chip, entry);
0d3b33e6
VD		 1830 if (ret < 0)
1831 return ret;
1832
1833 reg = GLOBAL_VTU_VID_VALID;
1834loadpurge:
fad09c73 1835 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1836 if (ret < 0)
1837 return ret;
1838
1839 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73 1840 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1841 if (ret < 0)
1842 return ret;
1843
fad09c73 1844 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1845}
1846
fad09c73 1847static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1848 u16 *new, u16 *old)
2db9ce1f 1849{
fad09c73 1850 struct dsa_switch *ds = chip->ds;
f74df0be 1851 u16 upper_mask;
2db9ce1f
VD		 1852 u16 fid;
1853 int ret;
1854
fad09c73 1855 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1856 upper_mask = 0xff;
fad09c73 1857 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1858 upper_mask = 0xf;
f74df0be
VD		 1859 else
1860 return -EOPNOTSUPP;
1861
2db9ce1f 1862 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
fad09c73 1863 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1864 if (ret < 0)
1865 return ret;
1866
1867 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1868
1869 if (new) {
1870 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1871 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1872
fad09c73 1873 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1874 ret);
1875 if (ret < 0)
1876 return ret;
1877 }
1878
1879 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
fad09c73 1880 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1881 if (ret < 0)
1882 return ret;
1883
f74df0be 1884 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1885
1886 if (new) {
f74df0be
VD		 1887 ret &= ~upper_mask;
1888 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1889
fad09c73 1890 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1891 ret);
1892 if (ret < 0)
1893 return ret;
1894
c8b09808
AL		 1895 netdev_dbg(ds->ports[port].netdev,
1896 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1897 }
1898
1899 if (old)
1900 *old = fid;
1901
1902 return 0;
1903}
1904
fad09c73 1905static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1906 int port, u16 *fid)
2db9ce1f 1907{
fad09c73 1908 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1909}
1910
fad09c73 1911static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1912 int port, u16 fid)
2db9ce1f 1913{
fad09c73 1914 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1915}
1916
fad09c73 1917static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1918{
1919 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1920 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1921 int i, err;
3285f9e8
VD		 1922
1923 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1924
2db9ce1f 1925 /* Set every FID bit used by the (un)bridged ports */
fad09c73
VD		 1926 for (i = 0; i < chip->info->num_ports; ++i) {
1927 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1928 if (err)
1929 return err;
1930
1931 set_bit(*fid, fid_bitmap);
1932 }
1933
3285f9e8 1934 /* Set every FID bit used by the VLAN entries */
fad09c73 1935 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1936 if (err)
1937 return err;
1938
1939 do {
fad09c73 1940 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1941 if (err)
1942 return err;
1943
1944 if (!vlan.valid)
1945 break;
1946
1947 set_bit(vlan.fid, fid_bitmap);
1948 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1949
1950 /* The reset value 0x000 is used to indicate that multiple address
1951 * databases are not needed. Return the next positive available.
1952 */
1953 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1954 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1955 return -ENOSPC;
1956
1957 /* Clear the database */
fad09c73 1958 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1959}
1960
fad09c73 1961static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09 1962 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1963{
fad09c73 1964 struct dsa_switch *ds = chip->ds;
0d3b33e6
VD		 1965 struct mv88e6xxx_vtu_stu_entry vlan = {
1966 .valid = true,
1967 .vid = vid,
1968 };
3285f9e8
VD		 1969 int i, err;
1970
fad09c73 1971 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1972 if (err)
1973 return err;
0d3b33e6 1974
3d131f07 1975 /* exclude all ports except the CPU and DSA ports */
fad09c73 1976 for (i = 0; i < chip->info->num_ports; ++i)
3d131f07
VD		 1977 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1978 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1979 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1980
fad09c73
VD		 1981 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1982 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
0d3b33e6 1983 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1984
1985 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1986 * implemented, only one STU entry is needed to cover all VTU
1987 * entries. Thus, validate the SID 0.
1988 */
1989 vlan.sid = 0;
fad09c73 1990 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1991 if (err)
1992 return err;
1993
1994 if (vstp.sid != vlan.sid || !vstp.valid) {
1995 memset(&vstp, 0, sizeof(vstp));
1996 vstp.valid = true;
1997 vstp.sid = vlan.sid;
1998
fad09c73 1999 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 2000 if (err)
2001 return err;
2002 }
0d3b33e6
VD		 2003 }
2004
2005 *entry = vlan;
2006 return 0;
2007}
2008
fad09c73 2009static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09
VD		 2010 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
2011{
2012 int err;
2013
2014 if (!vid)
2015 return -EINVAL;
2016
fad09c73 2017 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 2018 if (err)
2019 return err;
2020
fad09c73 2021 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 2022 if (err)
2023 return err;
2024
2025 if (entry->vid != vid || !entry->valid) {
2026 if (!creat)
2027 return -EOPNOTSUPP;
2028 /* -ENOENT would've been more appropriate, but switchdev expects
2029 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
2030 */
2031
fad09c73 2032 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 2033 }
2034
2035 return err;
2036}
2037
da9c359e
VD		 2038static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2039 u16 vid_begin, u16 vid_end)
2040{
fad09c73 2041 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 2042 struct mv88e6xxx_vtu_stu_entry vlan;
2043 int i, err;
2044
2045 if (!vid_begin)
2046 return -EOPNOTSUPP;
2047
fad09c73 2048 mutex_lock(&chip->reg_lock);
da9c359e 2049
fad09c73 2050 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 2051 if (err)
2052 goto unlock;
2053
2054 do {
fad09c73 2055 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 2056 if (err)
2057 goto unlock;
2058
2059 if (!vlan.valid)
2060 break;
2061
2062 if (vlan.vid > vid_end)
2063 break;
2064
fad09c73 2065 for (i = 0; i < chip->info->num_ports; ++i) {
da9c359e
VD		 2066 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2067 continue;
2068
2069 if (vlan.data[i] ==
2070 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2071 continue;
2072
fad09c73
VD		 2073 if (chip->ports[i].bridge_dev ==
2074 chip->ports[port].bridge_dev)
da9c359e
VD		 2075 break; /* same bridge, check next VLAN */
2076
c8b09808 2077 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 2078 "hardware VLAN %d already used by %s\n",
2079 vlan.vid,
fad09c73 2080 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 2081 err = -EOPNOTSUPP;
2082 goto unlock;
2083 }
2084 } while (vlan.vid < vid_end);
2085
2086unlock:
fad09c73 2087 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 2088
2089 return err;
2090}
2091
214cdb99
VD		 2092static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2093 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2094 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2095 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2096 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2097};
2098
f81ec90f
VD		 2099static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2100 bool vlan_filtering)
214cdb99 2101{
fad09c73 2102 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
214cdb99
VD		 2103 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2104 PORT_CONTROL_2_8021Q_DISABLED;
2105 int ret;
2106
fad09c73 2107 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2108 return -EOPNOTSUPP;
2109
fad09c73 2110 mutex_lock(&chip->reg_lock);
214cdb99 2111
fad09c73 2112 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 2113 if (ret < 0)
2114 goto unlock;
2115
2116 old = ret & PORT_CONTROL_2_8021Q_MASK;
2117
5220ef1e
VD		 2118 if (new != old) {
2119 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2120 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 2121
fad09c73 2122 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 2123 ret);
2124 if (ret < 0)
2125 goto unlock;
2126
c8b09808 2127 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 2128 mv88e6xxx_port_8021q_mode_names[new],
2129 mv88e6xxx_port_8021q_mode_names[old]);
2130 }
214cdb99 2131
5220ef1e 2132 ret = 0;
214cdb99 2133unlock:
fad09c73 2134 mutex_unlock(&chip->reg_lock);
214cdb99
VD		 2135
2136 return ret;
2137}
2138
57d32310
VD		 2139static int
2140mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2141 const struct switchdev_obj_port_vlan *vlan,
2142 struct switchdev_trans *trans)
76e398a6 2143{
fad09c73 2144 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 2145 int err;
2146
fad09c73 2147 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2148 return -EOPNOTSUPP;
2149
da9c359e
VD		 2150 /* If the requested port doesn't belong to the same bridge as the VLAN
2151 * members, do not support it (yet) and fallback to software VLAN.
2152 */
2153 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2154 vlan->vid_end);
2155 if (err)
2156 return err;
2157
76e398a6
VD		 2158 /* We don't need any dynamic resource from the kernel (yet),
2159 * so skip the prepare phase.
2160 */
2161 return 0;
2162}
2163
fad09c73 2164static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 2165 u16 vid, bool untagged)
0d3b33e6 2166{
0d3b33e6
VD		 2167 struct mv88e6xxx_vtu_stu_entry vlan;
2168 int err;
2169
fad09c73 2170 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 2171 if (err)
76e398a6 2172 return err;
0d3b33e6 2173
0d3b33e6
VD		 2174 vlan.data[port] = untagged ?
2175 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2176 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2177
fad09c73 2178 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2179}
2180
f81ec90f
VD		 2181static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2182 const struct switchdev_obj_port_vlan *vlan,
2183 struct switchdev_trans *trans)
76e398a6 2184{
fad09c73 2185 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 2186 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2187 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2188 u16 vid;
76e398a6 2189
fad09c73 2190 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2191 return;
2192
fad09c73 2193 mutex_lock(&chip->reg_lock);
76e398a6 2194
4d5770b3 2195 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 2196 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 2197 netdev_err(ds->ports[port].netdev,
2198 "failed to add VLAN %d%c\n",
4d5770b3 2199 vid, untagged ? 'u' : 't');
76e398a6 2200
fad09c73 2201 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 2202 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 2203 vlan->vid_end);
0d3b33e6 2204
fad09c73 2205 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 2206}
2207
fad09c73 2208static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 2209 int port, u16 vid)
7dad08d7 2210{
fad09c73 2211 struct dsa_switch *ds = chip->ds;
7dad08d7 2212 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 2213 int i, err;
2214
fad09c73 2215 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 2216 if (err)
76e398a6 2217 return err;
7dad08d7 2218
2fb5ef09
VD		 2219 /* Tell switchdev if this VLAN is handled in software */
2220 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2221 return -EOPNOTSUPP;
7dad08d7
VD		 2222
2223 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2224
2225 /* keep the VLAN unless all ports are excluded */
f02bdffc 2226 vlan.valid = false;
fad09c73 2227 for (i = 0; i < chip->info->num_ports; ++i) {
3d131f07 2228 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 2229 continue;
2230
2231 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2232 vlan.valid = true;
7dad08d7
VD		 2233 break;
2234 }
2235 }
2236
fad09c73 2237 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2238 if (err)
2239 return err;
2240
fad09c73 2241 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 2242}
2243
f81ec90f
VD		 2244static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2245 const struct switchdev_obj_port_vlan *vlan)
76e398a6 2246{
fad09c73 2247 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 2248 u16 pvid, vid;
2249 int err = 0;
2250
fad09c73 2251 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2252 return -EOPNOTSUPP;
2253
fad09c73 2254 mutex_lock(&chip->reg_lock);
76e398a6 2255
fad09c73 2256 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 2257 if (err)
2258 goto unlock;
2259
76e398a6 2260 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 2261 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 2262 if (err)
2263 goto unlock;
2264
2265 if (vid == pvid) {
fad09c73 2266 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 2267 if (err)
2268 goto unlock;
2269 }
2270 }
2271
7dad08d7 2272unlock:
fad09c73 2273 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2274
2275 return err;
2276}
2277
fad09c73 2278static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2279 const unsigned char *addr)
defb05b9
GR		 2280{
2281 int i, ret;
2282
2283 for (i = 0; i < 3; i++) {
cca8b133 2284 ret = _mv88e6xxx_reg_write(
fad09c73 2285 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2286 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2287 if (ret < 0)
2288 return ret;
2289 }
2290
2291 return 0;
2292}
2293
fad09c73 2294static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2295 unsigned char *addr)
defb05b9
GR		 2296{
2297 int i, ret;
2298
2299 for (i = 0; i < 3; i++) {
fad09c73 2300 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
cca8b133 2301 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2302 if (ret < 0)
2303 return ret;
2304 addr[i * 2] = ret >> 8;
2305 addr[i * 2 + 1] = ret & 0xff;
2306 }
2307
2308 return 0;
2309}
2310
fad09c73 2311static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2312 struct mv88e6xxx_atu_entry *entry)
defb05b9 2313{
6630e236
VD		 2314 int ret;
2315
fad09c73 2316 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2317 if (ret < 0)
2318 return ret;
2319
fad09c73 2320 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2321 if (ret < 0)
2322 return ret;
2323
fad09c73 2324 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2325 if (ret < 0)
87820510
VD		 2326 return ret;
2327
fad09c73 2328 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2329}
87820510 2330
fad09c73 2331static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
fd231c82
VD		 2332 const unsigned char *addr, u16 vid,
2333 u8 state)
2334{
2335 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2336 struct mv88e6xxx_vtu_stu_entry vlan;
2337 int err;
2338
2db9ce1f
VD		 2339 /* Null VLAN ID corresponds to the port private database */
2340 if (vid == 0)
fad09c73 2341 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2342 else
fad09c73 2343 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2344 if (err)
2345 return err;
fd231c82 2346
3285f9e8 2347 entry.fid = vlan.fid;
fd231c82
VD		 2348 entry.state = state;
2349 ether_addr_copy(entry.mac, addr);
2350 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2351 entry.trunk = false;
2352 entry.portv_trunkid = BIT(port);
2353 }
2354
fad09c73 2355 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2356}
2357
f81ec90f
VD		 2358static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2359 const struct switchdev_obj_port_fdb *fdb,
2360 struct switchdev_trans *trans)
146a3206
VD		 2361{
2362 /* We don't need any dynamic resource from the kernel (yet),
2363 * so skip the prepare phase.
2364 */
2365 return 0;
2366}
2367
f81ec90f
VD		 2368static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2369 const struct switchdev_obj_port_fdb *fdb,
2370 struct switchdev_trans *trans)
87820510 2371{
1f36faf2 2372 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2373 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2374 GLOBAL_ATU_DATA_STATE_UC_STATIC;
fad09c73 2375 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510 2376
fad09c73
VD		 2377 mutex_lock(&chip->reg_lock);
2378 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
c8b09808
AL		 2379 netdev_err(ds->ports[port].netdev,
2380 "failed to load MAC address\n");
fad09c73 2381 mutex_unlock(&chip->reg_lock);
87820510
VD		 2382}
2383
f81ec90f
VD		 2384static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2385 const struct switchdev_obj_port_fdb *fdb)
87820510 2386{
fad09c73 2387 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510
VD		 2388 int ret;
2389
fad09c73
VD		 2390 mutex_lock(&chip->reg_lock);
2391 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
cdf09697 2392 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2393 mutex_unlock(&chip->reg_lock);
87820510
VD		 2394
2395 return ret;
2396}
2397
fad09c73 2398static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2399 struct mv88e6xxx_atu_entry *entry)
6630e236 2400{
1d194046
VD		 2401 struct mv88e6xxx_atu_entry next = { 0 };
2402 int ret;
2403
2404 next.fid = fid;
defb05b9 2405
fad09c73 2406 ret = _mv88e6xxx_atu_wait(chip);
cdf09697
DM		 2407 if (ret < 0)
2408 return ret;
6630e236 2409
fad09c73 2410 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2411 if (ret < 0)
2412 return ret;
6630e236 2413
fad09c73 2414 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
1d194046
VD		 2415 if (ret < 0)
2416 return ret;
6630e236 2417
fad09c73 2418 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2419 if (ret < 0)
2420 return ret;
6630e236 2421
1d194046
VD		 2422 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2423 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2424 unsigned int mask, shift;
2425
2426 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2427 next.trunk = true;
2428 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2429 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2430 } else {
2431 next.trunk = false;
2432 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2433 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2434 }
2435
2436 next.portv_trunkid = (ret & mask) >> shift;
2437 }
cdf09697 2438
1d194046 2439 *entry = next;
cdf09697
DM		 2440 return 0;
2441}
2442
fad09c73 2443static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
158bc065 2444 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2445 struct switchdev_obj_port_fdb *fdb,
2446 int (*cb)(struct switchdev_obj *obj))
2447{
2448 struct mv88e6xxx_atu_entry addr = {
2449 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2450 };
2451 int err;
2452
fad09c73 2453 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2454 if (err)
2455 return err;
2456
2457 do {
fad09c73 2458 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d
VD		 2459 if (err)
2460 break;
2461
2462 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2463 break;
2464
2465 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2466 bool is_static = addr.state ==
2467 (is_multicast_ether_addr(addr.mac) ?
2468 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2469 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2470
2471 fdb->vid = vid;
2472 ether_addr_copy(fdb->addr, addr.mac);
2473 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2474
2475 err = cb(&fdb->obj);
2476 if (err)
2477 break;
2478 }
2479 } while (!is_broadcast_ether_addr(addr.mac));
2480
2481 return err;
2482}
2483
f81ec90f
VD		 2484static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2485 struct switchdev_obj_port_fdb *fdb,
2486 int (*cb)(struct switchdev_obj *obj))
f33475bd 2487{
fad09c73 2488 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f33475bd
VD		 2489 struct mv88e6xxx_vtu_stu_entry vlan = {
2490 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2491 };
2db9ce1f 2492 u16 fid;
f33475bd
VD		 2493 int err;
2494
fad09c73 2495 mutex_lock(&chip->reg_lock);
f33475bd 2496
2db9ce1f 2497 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2498 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f
VD		 2499 if (err)
2500 goto unlock;
2501
fad09c73 2502 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2503 if (err)
2504 goto unlock;
2505
74b6ba0d 2506 /* Dump VLANs' Filtering Information Databases */
fad09c73 2507 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd
VD		 2508 if (err)
2509 goto unlock;
2510
2511 do {
fad09c73 2512 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2513 if (err)
74b6ba0d 2514 break;
f33475bd
VD		 2515
2516 if (!vlan.valid)
2517 break;
2518
fad09c73
VD		 2519 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2520 port, fdb, cb);
f33475bd 2521 if (err)
74b6ba0d 2522 break;
f33475bd
VD		 2523 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2524
2525unlock:
fad09c73 2526 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2527
2528 return err;
2529}
2530
f81ec90f
VD		 2531static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2532 struct net_device *bridge)
e79a8bcb 2533{
fad09c73 2534 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1d9619d5 2535 int i, err = 0;
466dfa07 2536
fad09c73 2537 mutex_lock(&chip->reg_lock);
466dfa07 2538
b7666efe 2539 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2540 chip->ports[port].bridge_dev = bridge;
b7666efe 2541
fad09c73
VD		 2542 for (i = 0; i < chip->info->num_ports; ++i) {
2543 if (chip->ports[i].bridge_dev == bridge) {
2544 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2545 if (err)
2546 break;
2547 }
2548 }
2549
fad09c73 2550 mutex_unlock(&chip->reg_lock);
a6692754 2551
466dfa07 2552 return err;
e79a8bcb
VD		 2553}
2554
f81ec90f 2555static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2556{
fad09c73
VD		 2557 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2558 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2559 int i;
466dfa07 2560
fad09c73 2561 mutex_lock(&chip->reg_lock);
466dfa07 2562
b7666efe 2563 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2564 chip->ports[port].bridge_dev = NULL;
b7666efe 2565
fad09c73
VD		 2566 for (i = 0; i < chip->info->num_ports; ++i)
2567 if (i == port || chip->ports[i].bridge_dev == bridge)
2568 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2569 netdev_warn(ds->ports[i].netdev,
2570 "failed to remap\n");
b7666efe 2571
fad09c73 2572 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2573}
2574
fad09c73 2575static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
03a4a540 2576 int port, int page, int reg, int val)
75baacf0
PU		 2577{
2578 int ret;
2579
fad09c73 2580 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
75baacf0
PU		 2581 if (ret < 0)
2582 goto restore_page_0;
2583
fad09c73 2584 ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
75baacf0 2585restore_page_0:
fad09c73 2586 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
75baacf0
PU		 2587
2588 return ret;
2589}
2590
fad09c73 2591static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
03a4a540 2592 int port, int page, int reg)
75baacf0
PU		 2593{
2594 int ret;
2595
fad09c73 2596 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
75baacf0
PU		 2597 if (ret < 0)
2598 goto restore_page_0;
2599
fad09c73 2600 ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
75baacf0 2601restore_page_0:
fad09c73 2602 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
75baacf0
PU		 2603
2604 return ret;
2605}
2606
fad09c73 2607static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2608{
fad09c73 2609 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2610 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2611 struct gpio_desc *gpiod = chip->reset;
552238b5
VD		 2612 unsigned long timeout;
2613 int ret;
2614 int i;
2615
2616 /* Set all ports to the disabled state. */
fad09c73
VD		 2617 for (i = 0; i < chip->info->num_ports; i++) {
2618 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
552238b5
VD		 2619 if (ret < 0)
2620 return ret;
2621
fad09c73 2622 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
552238b5
VD		 2623 ret & 0xfffc);
2624 if (ret)
2625 return ret;
2626 }
2627
2628 /* Wait for transmit queues to drain. */
2629 usleep_range(2000, 4000);
2630
2631 /* If there is a gpio connected to the reset pin, toggle it */
2632 if (gpiod) {
2633 gpiod_set_value_cansleep(gpiod, 1);
2634 usleep_range(10000, 20000);
2635 gpiod_set_value_cansleep(gpiod, 0);
2636 usleep_range(10000, 20000);
2637 }
2638
2639 /* Reset the switch. Keep the PPU active if requested. The PPU
2640 * needs to be active to support indirect phy register access
2641 * through global registers 0x18 and 0x19.
2642 */
2643 if (ppu_active)
fad09c73 2644 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
552238b5 2645 else
fad09c73 2646 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
552238b5
VD		 2647 if (ret)
2648 return ret;
2649
2650 /* Wait up to one second for reset to complete. */
2651 timeout = jiffies + 1 * HZ;
2652 while (time_before(jiffies, timeout)) {
fad09c73 2653 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
552238b5
VD		 2654 if (ret < 0)
2655 return ret;
2656
2657 if ((ret & is_reset) == is_reset)
2658 break;
2659 usleep_range(1000, 2000);
2660 }
2661 if (time_after(jiffies, timeout))
2662 ret = -ETIMEDOUT;
2663 else
2664 ret = 0;
2665
2666 return ret;
2667}
2668
fad09c73 2669static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
13a7ebb3
PU		 2670{
2671 int ret;
2672
fad09c73 2673 ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
03a4a540 2674 PAGE_FIBER_SERDES, MII_BMCR);
13a7ebb3
PU		 2675 if (ret < 0)
2676 return ret;
2677
2678 if (ret & BMCR_PDOWN) {
2679 ret &= ~BMCR_PDOWN;
fad09c73 2680 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
03a4a540
AL		 2681 PAGE_FIBER_SERDES, MII_BMCR,
2682 ret);
13a7ebb3
PU		 2683 }
2684
2685 return ret;
2686}
2687
fad09c73 2688static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2689{
fad09c73 2690 struct dsa_switch *ds = chip->ds;
f02bdffc 2691 int ret;
54d792f2 2692 u16 reg;
d827e88a 2693
fad09c73
VD		 2694 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2695 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2696 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2697 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2698 /* MAC Forcing register: don't force link, speed,
2699 * duplex or flow control state to any particular
2700 * values on physical ports, but force the CPU port
2701 * and all DSA ports to their maximum bandwidth and
2702 * full duplex.
2703 */
fad09c73 2704 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2705 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2706 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2707 reg |= PORT_PCS_CTRL_FORCE_LINK |
2708 PORT_PCS_CTRL_LINK_UP |
2709 PORT_PCS_CTRL_DUPLEX_FULL |
2710 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2711 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2712 reg |= PORT_PCS_CTRL_100;
2713 else
2714 reg |= PORT_PCS_CTRL_1000;
2715 } else {
2716 reg |= PORT_PCS_CTRL_UNFORCED;
2717 }
2718
fad09c73 2719 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2720 PORT_PCS_CTRL, reg);
2721 if (ret)
a1a6a4d1 2722 return ret;
54d792f2
AL		 2723 }
2724
2725 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2726 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2727 * tunneling, determine priority by looking at 802.1p and IP
2728 * priority fields (IP prio has precedence), and set STP state
2729 * to Forwarding.
2730 *
2731 * If this is the CPU link, use DSA or EDSA tagging depending
2732 * on which tagging mode was configured.
2733 *
2734 * If this is a link to another switch, use DSA tagging mode.
2735 *
2736 * If this is the upstream port for this switch, enable
2737 * forwarding of unknown unicasts and multicasts.
2738 */
2739 reg = 0;
fad09c73
VD		 2740 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2741 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2742 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2743 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2744 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2745 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2746 PORT_CONTROL_STATE_FORWARDING;
2747 if (dsa_is_cpu_port(ds, port)) {
fad09c73 2748 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
54d792f2 2749 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2750 if (mv88e6xxx_6352_family(chip) ||
2751 mv88e6xxx_6351_family(chip) ||
2752 mv88e6xxx_6165_family(chip) ||
2753 mv88e6xxx_6097_family(chip) ||
2754 mv88e6xxx_6320_family(chip)) {
5377b802
AL		 2755 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2756 PORT_CONTROL_FORWARD_UNKNOWN |
c047a1f9 2757 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2758 }
2759
fad09c73
VD		 2760 if (mv88e6xxx_6352_family(chip) ||
2761 mv88e6xxx_6351_family(chip) ||
2762 mv88e6xxx_6165_family(chip) ||
2763 mv88e6xxx_6097_family(chip) ||
2764 mv88e6xxx_6095_family(chip) ||
2765 mv88e6xxx_6065_family(chip) ||
2766 mv88e6xxx_6185_family(chip) ||
2767 mv88e6xxx_6320_family(chip)) {
57d32310 2768 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
54d792f2
AL		 2769 }
2770 }
6083ce71 2771 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2772 if (mv88e6xxx_6095_family(chip) ||
2773 mv88e6xxx_6185_family(chip))
6083ce71 2774 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2775 if (mv88e6xxx_6352_family(chip) ||
2776 mv88e6xxx_6351_family(chip) ||
2777 mv88e6xxx_6165_family(chip) ||
2778 mv88e6xxx_6097_family(chip) ||
2779 mv88e6xxx_6320_family(chip)) {
54d792f2 2780 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2781 }
2782
54d792f2
AL		 2783 if (port == dsa_upstream_port(ds))
2784 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2785 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2786 }
2787 if (reg) {
fad09c73 2788 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2789 PORT_CONTROL, reg);
2790 if (ret)
a1a6a4d1 2791 return ret;
54d792f2
AL		 2792 }
2793
13a7ebb3
PU		 2794 /* If this port is connected to a SerDes, make sure the SerDes is not
2795 * powered down.
2796 */
fad09c73
VD		 2797 if (mv88e6xxx_6352_family(chip)) {
2798 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
13a7ebb3 2799 if (ret < 0)
a1a6a4d1 2800 return ret;
13a7ebb3
PU		 2801 ret &= PORT_STATUS_CMODE_MASK;
2802 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2803 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2804 (ret == PORT_STATUS_CMODE_SGMII)) {
fad09c73 2805 ret = mv88e6xxx_power_on_serdes(chip);
13a7ebb3 2806 if (ret < 0)
a1a6a4d1 2807 return ret;
13a7ebb3
PU		 2808 }
2809 }
2810
8efdda4a 2811 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2812 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2813 * untagged frames on this port, do a destination address lookup on all
2814 * received packets as usual, disable ARP mirroring and don't send a
2815 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2816 */
2817 reg = 0;
fad09c73
VD		 2818 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2819 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2820 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2821 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2822 reg = PORT_CONTROL_2_MAP_DA;
2823
fad09c73
VD		 2824 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2825 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2826 reg |= PORT_CONTROL_2_JUMBO_10240;
2827
fad09c73 2828 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2829 /* Set the upstream port this port should use */
2830 reg |= dsa_upstream_port(ds);
2831 /* enable forwarding of unknown multicast addresses to
2832 * the upstream port
2833 */
2834 if (port == dsa_upstream_port(ds))
2835 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2836 }
2837
46fbe5e5 2838 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2839
54d792f2 2840 if (reg) {
fad09c73 2841 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2842 PORT_CONTROL_2, reg);
2843 if (ret)
a1a6a4d1 2844 return ret;
54d792f2
AL		 2845 }
2846
2847 /* Port Association Vector: when learning source addresses
2848 * of packets, add the address to the address database using
2849 * a port bitmap that has only the bit for this port set and
2850 * the other bits clear.
2851 */
4c7ea3c0 2852 reg = 1 << port;
996ecb82
VD		 2853 /* Disable learning for CPU port */
2854 if (dsa_is_cpu_port(ds, port))
65fa4027 2855 reg = 0;
4c7ea3c0 2856
fad09c73
VD		 2857 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2858 reg);
54d792f2 2859 if (ret)
a1a6a4d1 2860 return ret;
54d792f2
AL		 2861
2862 /* Egress rate control 2: disable egress rate control. */
fad09c73 2863 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2864 0x0000);
2865 if (ret)
a1a6a4d1 2866 return ret;
54d792f2 2867
fad09c73
VD		 2868 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2869 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2870 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2871 /* Do not limit the period of time that this port can
2872 * be paused for by the remote end or the period of
2873 * time that this port can pause the remote end.
2874 */
fad09c73 2875 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2876 PORT_PAUSE_CTRL, 0x0000);
2877 if (ret)
a1a6a4d1 2878 return ret;
54d792f2
AL		 2879
2880 /* Port ATU control: disable limiting the number of
2881 * address database entries that this port is allowed
2882 * to use.
2883 */
fad09c73 2884 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2885 PORT_ATU_CONTROL, 0x0000);
2886 /* Priority Override: disable DA, SA and VTU priority
2887 * override.
2888 */
fad09c73 2889 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2890 PORT_PRI_OVERRIDE, 0x0000);
2891 if (ret)
a1a6a4d1 2892 return ret;
54d792f2
AL		 2893
2894 /* Port Ethertype: use the Ethertype DSA Ethertype
2895 * value.
2896 */
fad09c73 2897 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2898 PORT_ETH_TYPE, ETH_P_EDSA);
2899 if (ret)
a1a6a4d1 2900 return ret;
54d792f2
AL		 2901 /* Tag Remap: use an identity 802.1p prio -> switch
2902 * prio mapping.
2903 */
fad09c73 2904 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2905 PORT_TAG_REGMAP_0123, 0x3210);
2906 if (ret)
a1a6a4d1 2907 return ret;
54d792f2
AL		 2908
2909 /* Tag Remap 2: use an identity 802.1p prio -> switch
2910 * prio mapping.
2911 */
fad09c73 2912 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2913 PORT_TAG_REGMAP_4567, 0x7654);
2914 if (ret)
a1a6a4d1 2915 return ret;
54d792f2
AL		 2916 }
2917
fad09c73
VD		 2918 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2919 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2920 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2921 mv88e6xxx_6320_family(chip)) {
54d792f2 2922 /* Rate Control: disable ingress rate limiting. */
fad09c73 2923 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2924 PORT_RATE_CONTROL, 0x0001);
2925 if (ret)
a1a6a4d1 2926 return ret;
54d792f2
AL		 2927 }
2928
366f0a0f
GR		 2929 /* Port Control 1: disable trunking, disable sending
2930 * learning messages to this port.
d827e88a 2931 */
fad09c73
VD		 2932 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2933 0x0000);
d827e88a 2934 if (ret)
a1a6a4d1 2935 return ret;
d827e88a 2936
207afda1 2937 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2938 * database, and allow bidirectional communication between the
2939 * CPU and DSA port(s), and the other ports.
d827e88a 2940 */
fad09c73 2941 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2db9ce1f 2942 if (ret)
a1a6a4d1 2943 return ret;
2db9ce1f 2944
fad09c73 2945 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
d827e88a 2946 if (ret)
a1a6a4d1 2947 return ret;
d827e88a
GR		 2948
2949 /* Default VLAN ID and priority: don't set a default VLAN
2950 * ID, and set the default packet priority to zero.
2951 */
fad09c73 2952 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2953 0x0000);
a1a6a4d1
VD		 2954 if (ret)
2955 return ret;
dbde9e66 2956
dbde9e66
AL		 2957 return 0;
2958}
2959
3b4caa1b
VD		 2960static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2961{
2962 int err;
2963
2964 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2965 (addr[0] << 8) | addr[1]);
2966 if (err)
2967 return err;
2968
2969 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2970 (addr[2] << 8) | addr[3]);
2971 if (err)
2972 return err;
2973
2974 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2975 (addr[4] << 8) | addr[5]);
2976}
2977
9729934c 2978static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2979{
fad09c73 2980 struct dsa_switch *ds = chip->ds;
b0745e87 2981 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2982 u16 reg;
552238b5 2983 int err;
54d792f2 2984
119477bd
VD		 2985 /* Enable the PHY Polling Unit if present, don't discard any packets,
2986 * and mask all interrupt sources.
2987 */
2988 reg = 0;
fad09c73
VD		 2989 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2990 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2991 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2992
fad09c73 2993 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
119477bd
VD		 2994 if (err)
2995 return err;
2996
b0745e87
VD		 2997 /* Configure the upstream port, and configure it as the port to which
2998 * ingress and egress and ARP monitor frames are to be sent.
2999 */
3000 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
3001 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
3002 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
fad09c73
VD		 3003 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
3004 reg);
b0745e87
VD		 3005 if (err)
3006 return err;
3007
50484ff4 3008 /* Disable remote management, and set the switch's DSA device number. */
fad09c73 3009 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
50484ff4
VD		 3010 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
3011 (ds->index & 0x1f));
3012 if (err)
3013 return err;
3014
54d792f2
AL		 3015 /* Set the default address aging time to 5 minutes, and
3016 * enable address learn messages to be sent to all message
3017 * ports.
3018 */
fad09c73 3019 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
48ace4ef
AL		 3020 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
3021 if (err)
08a01261 3022 return err;
54d792f2 3023
9729934c
VD		 3024 /* Clear all the VTU and STU entries */
3025 err = _mv88e6xxx_vtu_stu_flush(chip);
3026 if (err < 0)
3027 return err;
3028
3029 /* Clear all ATU entries */
3030 err = _mv88e6xxx_atu_flush(chip, 0, true);
3031 if (err)
3032 return err;
3033
54d792f2 3034 /* Configure the IP ToS mapping registers. */
fad09c73 3035 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 3036 if (err)
08a01261 3037 return err;
fad09c73 3038 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 3039 if (err)
08a01261 3040 return err;
fad09c73 3041 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 3042 if (err)
08a01261 3043 return err;
fad09c73 3044 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 3045 if (err)
08a01261 3046 return err;
fad09c73 3047 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 3048 if (err)
08a01261 3049 return err;
fad09c73 3050 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 3051 if (err)
08a01261 3052 return err;
fad09c73 3053 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 3054 if (err)
08a01261 3055 return err;
fad09c73 3056 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 3057 if (err)
08a01261 3058 return err;
54d792f2
AL		 3059
3060 /* Configure the IEEE 802.1p priority mapping register. */
fad09c73 3061 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 3062 if (err)
08a01261 3063 return err;
54d792f2 3064
9729934c
VD		 3065 /* Clear the statistics counters for all ports */
3066 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
3067 GLOBAL_STATS_OP_FLUSH_ALL);
3068 if (err)
3069 return err;
3070
3071 /* Wait for the flush to complete. */
3072 err = _mv88e6xxx_stats_wait(chip);
3073 if (err)
3074 return err;
3075
3076 return 0;
3077}
3078
f22ab641
VD		 3079static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
3080 int target, int port)
3081{
3082 u16 val = (target << 8) | (port & 0xf);
3083
3084 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
3085}
3086
3087static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
3088{
3089 int target, port;
3090 int err;
3091
3092 /* Initialize the routing port to the 32 possible target devices */
3093 for (target = 0; target < 32; ++target) {
3094 port = 0xf;
3095
3096 if (target < DSA_MAX_SWITCHES) {
3097 port = chip->ds->rtable[target];
3098 if (port == DSA_RTABLE_NONE)
3099 port = 0xf;
3100 }
3101
3102 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
3103 if (err)
3104 break;
3105 }
3106
3107 return err;
3108}
3109
5154041f
VD		 3110static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
3111 bool hask, u16 mask)
3112{
3113 const u16 port_mask = BIT(chip->info->num_ports) - 1;
3114 u16 val = (num << 12) | (mask & port_mask);
3115
3116 if (hask)
3117 val |= GLOBAL2_TRUNK_MASK_HASK;
3118
3119 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
3120}
3121
3122static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
3123 u16 map)
3124{
3125 const u16 port_mask = BIT(chip->info->num_ports) - 1;
3126 u16 val = (id << 11) | (map & port_mask);
3127
3128 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
3129}
3130
3131static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
3132{
3133 const u16 port_mask = BIT(chip->info->num_ports) - 1;
3134 int i, err;
3135
3136 /* Clear all eight possible Trunk Mask vectors */
3137 for (i = 0; i < 8; ++i) {
3138 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
3139 if (err)
3140 return err;
3141 }
3142
3143 /* Clear all sixteen possible Trunk ID routing vectors */
3144 for (i = 0; i < 16; ++i) {
3145 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
3146 if (err)
3147 return err;
3148 }
3149
3150 return 0;
3151}
3152
8ec61c7f
VD		 3153static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
3154{
3155 int port, err;
3156
3157 /* Init all Ingress Rate Limit resources of all ports */
3158 for (port = 0; port < chip->info->num_ports; ++port) {
3159 /* XXX newer chips (like 88E6390) have different 2-bit ops */
3160 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
3161 GLOBAL2_IRL_CMD_OP_INIT_ALL |
3162 (port << 8));
3163 if (err)
3164 break;
3165
3166 /* Wait for the operation to complete */
3167 err = _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
3168 GLOBAL2_IRL_CMD_BUSY);
3169 if (err)
3170 break;
3171 }
3172
3173 return err;
3174}
3175
3b4caa1b
VD		 3176/* Indirect write to the Switch MAC/WoL/WoF register */
3177static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
3178 unsigned int pointer, u8 data)
3179{
3180 u16 val = (pointer << 8) | data;
3181
3182 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
3183}
3184
3185static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3186{
3187 int i, err;
3188
3189 for (i = 0; i < 6; i++) {
3190 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
3191 if (err)
3192 break;
3193 }
3194
3195 return err;
3196}
3197
9bda889f
VD		 3198static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
3199 u8 data)
3200{
3201 u16 val = (pointer << 8) | (data & 0x7);
3202
3203 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
3204}
3205
3206static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
3207{
3208 int i, err;
3209
3210 /* Clear all sixteen possible Priority Override entries */
3211 for (i = 0; i < 16; i++) {
3212 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3213 if (err)
3214 break;
3215 }
3216
3217 return err;
3218}
3219
9729934c
VD		 3220static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3221{
47395ed2 3222 u16 reg;
9729934c 3223 int err;
9729934c 3224
47395ed2
VD		 3225 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3226 /* Consider the frames with reserved multicast destination
3227 * addresses matching 01:80:c2:00:00:2x as MGMT.
3228 */
3229 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3230 0xffff);
3231 if (err)
3232 return err;
3233 }
3234
3235 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3236 /* Consider the frames with reserved multicast destination
3237 * addresses matching 01:80:c2:00:00:0x as MGMT.
3238 */
3239 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3240 0xffff);
3241 if (err)
3242 return err;
3243 }
54d792f2
AL		 3244
3245 /* Ignore removed tag data on doubly tagged packets, disable
3246 * flow control messages, force flow control priority to the
3247 * highest, and send all special multicast frames to the CPU
3248 * port at the highest priority.
3249 */
47395ed2
VD		 3250 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3251 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3252 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3253 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3254 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
48ace4ef 3255 if (err)
08a01261 3256 return err;
54d792f2
AL		 3257
3258 /* Program the DSA routing table. */
f22ab641
VD		 3259 err = mv88e6xxx_g2_set_device_mapping(chip);
3260 if (err)
3261 return err;
54d792f2 3262
5154041f
VD		 3263 /* Clear all trunk masks and mapping. */
3264 err = mv88e6xxx_g2_clear_trunk(chip);
3265 if (err)
3266 return err;
54d792f2 3267
8ec61c7f
VD		 3268 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3269 /* Disable ingress rate limiting by resetting all per port
3270 * ingress rate limit resources to their initial state.
3271 */
3272 err = mv88e6xxx_g2_clear_irl(chip);
3273 if (err)
3274 return err;
3275 }
3276
63ed880d
VD		 3277 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3278 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3279 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3280 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
48ace4ef 3281 if (err)
08a01261 3282 return err;
63ed880d 3283 }
54d792f2 3284
9bda889f 3285 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
54d792f2 3286 /* Clear the priority override table. */
9bda889f
VD		 3287 err = mv88e6xxx_g2_clear_pot(chip);
3288 if (err)
3289 return err;
54d792f2
AL		 3290 }
3291
9729934c 3292 return 0;
08a01261
VD		 3293}
3294
f81ec90f 3295static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3296{
fad09c73 3297 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
08a01261 3298 int err;
a1a6a4d1
VD		 3299 int i;
3300
fad09c73
VD		 3301 chip->ds = ds;
3302 ds->slave_mii_bus = chip->mdio_bus;
08a01261 3303
fad09c73
VD		 3304 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
3305 mutex_init(&chip->eeprom_mutex);
08a01261 3306
fad09c73 3307 mutex_lock(&chip->reg_lock);
08a01261 3308
fad09c73 3309 err = mv88e6xxx_switch_reset(chip);
08a01261
VD		 3310 if (err)
3311 goto unlock;
3312
9729934c
VD		 3313 /* Setup Switch Port Registers */
3314 for (i = 0; i < chip->info->num_ports; i++) {
3315 err = mv88e6xxx_setup_port(chip, i);
3316 if (err)
3317 goto unlock;
3318 }
3319
3320 /* Setup Switch Global 1 Registers */
3321 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 3322 if (err)
3323 goto unlock;
3324
9729934c
VD		 3325 /* Setup Switch Global 2 Registers */
3326 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3327 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 3328 if (err)
3329 goto unlock;
3330 }
08a01261 3331
6b17e864 3332unlock:
fad09c73 3333 mutex_unlock(&chip->reg_lock);
db687a56 3334
48ace4ef 3335 return err;
54d792f2
AL		 3336}
3337
3b4caa1b
VD		 3338static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3339{
3340 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3341 int err;
3342
3343 mutex_lock(&chip->reg_lock);
3344
3345 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3346 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3347 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3348 else
3349 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3350
3351 mutex_unlock(&chip->reg_lock);
3352
3353 return err;
3354}
3355
57d32310
VD		 3356static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3357 int reg)
49143585 3358{
fad09c73 3359 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49143585
AL		 3360 int ret;
3361
fad09c73
VD		 3362 mutex_lock(&chip->reg_lock);
3363 ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3364 mutex_unlock(&chip->reg_lock);
75baacf0 3365
49143585
AL		 3366 return ret;
3367}
3368
57d32310
VD		 3369static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3370 int reg, int val)
49143585 3371{
fad09c73 3372 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49143585
AL		 3373 int ret;
3374
fad09c73
VD		 3375 mutex_lock(&chip->reg_lock);
3376 ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3377 mutex_unlock(&chip->reg_lock);
75baacf0 3378
fd3a0ee4
AL		 3379 return ret;
3380}
3381
fad09c73 3382static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
fd3a0ee4 3383{
fad09c73 3384 if (port >= 0 && port < chip->info->num_ports)
fd3a0ee4
AL		 3385 return port;
3386 return -EINVAL;
3387}
3388
b516d453 3389static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
fd3a0ee4 3390{
fad09c73
VD		 3391 struct mv88e6xxx_chip *chip = bus->priv;
3392 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
fd3a0ee4
AL		 3393 int ret;
3394
3395 if (addr < 0)
158bc065 3396 return 0xffff;
fd3a0ee4 3397
fad09c73 3398 mutex_lock(&chip->reg_lock);
8c9983a2 3399
fad09c73
VD		 3400 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3401 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3402 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3403 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
8c9983a2 3404 else
fad09c73 3405 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
8c9983a2 3406
fad09c73 3407 mutex_unlock(&chip->reg_lock);
fd3a0ee4
AL		 3408 return ret;
3409}
3410
b516d453 3411static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
03a4a540 3412 u16 val)
fd3a0ee4 3413{
fad09c73
VD		 3414 struct mv88e6xxx_chip *chip = bus->priv;
3415 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
fd3a0ee4
AL		 3416 int ret;
3417
3418 if (addr < 0)
158bc065 3419 return 0xffff;
fd3a0ee4 3420
fad09c73 3421 mutex_lock(&chip->reg_lock);
8c9983a2 3422
fad09c73
VD		 3423 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3424 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3425 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3426 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
8c9983a2 3427 else
fad09c73 3428 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
8c9983a2 3429
fad09c73 3430 mutex_unlock(&chip->reg_lock);
fd3a0ee4
AL		 3431 return ret;
3432}
3433
fad09c73 3434static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 3435 struct device_node *np)
3436{
3437 static int index;
3438 struct mii_bus *bus;
3439 int err;
3440
fad09c73
VD		 3441 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3442 mv88e6xxx_ppu_state_init(chip);
b516d453
AL		 3443
3444 if (np)
fad09c73 3445 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 3446
fad09c73 3447 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 3448 if (!bus)
3449 return -ENOMEM;
3450
fad09c73 3451 bus->priv = (void *)chip;
b516d453
AL		 3452 if (np) {
3453 bus->name = np->full_name;
3454 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3455 } else {
3456 bus->name = "mv88e6xxx SMI";
3457 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3458 }
3459
3460 bus->read = mv88e6xxx_mdio_read;
3461 bus->write = mv88e6xxx_mdio_write;
fad09c73 3462 bus->parent = chip->dev;
b516d453 3463
fad09c73
VD		 3464 if (chip->mdio_np)
3465 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 3466 else
3467 err = mdiobus_register(bus);
3468 if (err) {
fad09c73 3469 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3470 goto out;
3471 }
fad09c73 3472 chip->mdio_bus = bus;
b516d453
AL		 3473
3474 return 0;
3475
3476out:
fad09c73
VD		 3477 if (chip->mdio_np)
3478 of_node_put(chip->mdio_np);
b516d453
AL		 3479
3480 return err;
3481}
3482
fad09c73 3483static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3484
3485{
fad09c73 3486 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3487
3488 mdiobus_unregister(bus);
3489
fad09c73
VD		 3490 if (chip->mdio_np)
3491 of_node_put(chip->mdio_np);
b516d453
AL		 3492}
3493
c22995c5
GR		 3494#ifdef CONFIG_NET_DSA_HWMON
3495
3496static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3497{
fad09c73 3498 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
c22995c5
GR		 3499 int ret;
3500 int val;
3501
3502 *temp = 0;
3503
fad09c73 3504 mutex_lock(&chip->reg_lock);
c22995c5 3505
fad09c73 3506 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3507 if (ret < 0)
3508 goto error;
3509
3510 /* Enable temperature sensor */
fad09c73 3511 ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
c22995c5
GR		 3512 if (ret < 0)
3513 goto error;
3514
fad09c73 3515 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
c22995c5
GR		 3516 if (ret < 0)
3517 goto error;
3518
3519 /* Wait for temperature to stabilize */
3520 usleep_range(10000, 12000);
3521
fad09c73 3522 val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
c22995c5
GR		 3523 if (val < 0) {
3524 ret = val;
3525 goto error;
3526 }
3527
3528 /* Disable temperature sensor */
fad09c73 3529 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
c22995c5
GR		 3530 if (ret < 0)
3531 goto error;
3532
3533 *temp = ((val & 0x1f) - 5) * 5;
3534
3535error:
fad09c73
VD		 3536 mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3537 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3538 return ret;
3539}
3540
3541static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3542{
fad09c73
VD		 3543 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3544 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3545 int ret;
3546
3547 *temp = 0;
3548
03a4a540 3549 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
c22995c5
GR		 3550 if (ret < 0)
3551 return ret;
3552
3553 *temp = (ret & 0xff) - 25;
3554
3555 return 0;
3556}
3557
f81ec90f 3558static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3559{
fad09c73 3560 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
158bc065 3561
fad09c73 3562 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3563 return -EOPNOTSUPP;
3564
fad09c73 3565 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3566 return mv88e63xx_get_temp(ds, temp);
3567
3568 return mv88e61xx_get_temp(ds, temp);
3569}
3570
f81ec90f 3571static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3572{
fad09c73
VD		 3573 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3574 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3575 int ret;
3576
fad09c73 3577 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3578 return -EOPNOTSUPP;
3579
3580 *temp = 0;
3581
03a4a540 3582 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3583 if (ret < 0)
3584 return ret;
3585
3586 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3587
3588 return 0;
3589}
3590
f81ec90f 3591static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3592{
fad09c73
VD		 3593 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3594 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3595 int ret;
3596
fad09c73 3597 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3598 return -EOPNOTSUPP;
3599
03a4a540 3600 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3601 if (ret < 0)
3602 return ret;
3603 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
03a4a540
AL		 3604 return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3605 (ret & 0xe0ff) | (temp << 8));
c22995c5
GR		 3606}
3607
f81ec90f 3608static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3609{
fad09c73
VD		 3610 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3611 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3612 int ret;
3613
fad09c73 3614 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3615 return -EOPNOTSUPP;
3616
3617 *alarm = false;
3618
03a4a540 3619 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3620 if (ret < 0)
3621 return ret;
3622
3623 *alarm = !!(ret & 0x40);
3624
3625 return 0;
3626}
3627#endif /* CONFIG_NET_DSA_HWMON */
3628
f81ec90f
VD		 3629static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3630 [MV88E6085] = {
3631 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3632 .family = MV88E6XXX_FAMILY_6097,
3633 .name = "Marvell 88E6085",
3634 .num_databases = 4096,
3635 .num_ports = 10,
9dddd478 3636 .port_base_addr = 0x10,
f81ec90f
VD		 3637 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3638 },
3639
3640 [MV88E6095] = {
3641 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3642 .family = MV88E6XXX_FAMILY_6095,
3643 .name = "Marvell 88E6095/88E6095F",
3644 .num_databases = 256,
3645 .num_ports = 11,
9dddd478 3646 .port_base_addr = 0x10,
f81ec90f
VD		 3647 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3648 },
3649
3650 [MV88E6123] = {
3651 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3652 .family = MV88E6XXX_FAMILY_6165,
3653 .name = "Marvell 88E6123",
3654 .num_databases = 4096,
3655 .num_ports = 3,
9dddd478 3656 .port_base_addr = 0x10,
f81ec90f
VD		 3657 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3658 },
3659
3660 [MV88E6131] = {
3661 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3662 .family = MV88E6XXX_FAMILY_6185,
3663 .name = "Marvell 88E6131",
3664 .num_databases = 256,
3665 .num_ports = 8,
9dddd478 3666 .port_base_addr = 0x10,
f81ec90f
VD		 3667 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3668 },
3669
3670 [MV88E6161] = {
3671 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3672 .family = MV88E6XXX_FAMILY_6165,
3673 .name = "Marvell 88E6161",
3674 .num_databases = 4096,
3675 .num_ports = 6,
9dddd478 3676 .port_base_addr = 0x10,
f81ec90f
VD		 3677 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3678 },
3679
3680 [MV88E6165] = {
3681 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3682 .family = MV88E6XXX_FAMILY_6165,
3683 .name = "Marvell 88E6165",
3684 .num_databases = 4096,
3685 .num_ports = 6,
9dddd478 3686 .port_base_addr = 0x10,
f81ec90f
VD		 3687 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3688 },
3689
3690 [MV88E6171] = {
3691 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3692 .family = MV88E6XXX_FAMILY_6351,
3693 .name = "Marvell 88E6171",
3694 .num_databases = 4096,
3695 .num_ports = 7,
9dddd478 3696 .port_base_addr = 0x10,
f81ec90f
VD		 3697 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3698 },
3699
3700 [MV88E6172] = {
3701 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3702 .family = MV88E6XXX_FAMILY_6352,
3703 .name = "Marvell 88E6172",
3704 .num_databases = 4096,
3705 .num_ports = 7,
9dddd478 3706 .port_base_addr = 0x10,
f81ec90f
VD		 3707 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3708 },
3709
3710 [MV88E6175] = {
3711 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3712 .family = MV88E6XXX_FAMILY_6351,
3713 .name = "Marvell 88E6175",
3714 .num_databases = 4096,
3715 .num_ports = 7,
9dddd478 3716 .port_base_addr = 0x10,
f81ec90f
VD		 3717 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3718 },
3719
3720 [MV88E6176] = {
3721 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3722 .family = MV88E6XXX_FAMILY_6352,
3723 .name = "Marvell 88E6176",
3724 .num_databases = 4096,
3725 .num_ports = 7,
9dddd478 3726 .port_base_addr = 0x10,
f81ec90f
VD		 3727 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3728 },
3729
3730 [MV88E6185] = {
3731 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3732 .family = MV88E6XXX_FAMILY_6185,
3733 .name = "Marvell 88E6185",
3734 .num_databases = 256,
3735 .num_ports = 10,
9dddd478 3736 .port_base_addr = 0x10,
f81ec90f
VD		 3737 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3738 },
3739
3740 [MV88E6240] = {
3741 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3742 .family = MV88E6XXX_FAMILY_6352,
3743 .name = "Marvell 88E6240",
3744 .num_databases = 4096,
3745 .num_ports = 7,
9dddd478 3746 .port_base_addr = 0x10,
f81ec90f
VD		 3747 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3748 },
3749
3750 [MV88E6320] = {
3751 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3752 .family = MV88E6XXX_FAMILY_6320,
3753 .name = "Marvell 88E6320",
3754 .num_databases = 4096,
3755 .num_ports = 7,
9dddd478 3756 .port_base_addr = 0x10,
f81ec90f
VD		 3757 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3758 },
3759
3760 [MV88E6321] = {
3761 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3762 .family = MV88E6XXX_FAMILY_6320,
3763 .name = "Marvell 88E6321",
3764 .num_databases = 4096,
3765 .num_ports = 7,
9dddd478 3766 .port_base_addr = 0x10,
f81ec90f
VD		 3767 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3768 },
3769
3770 [MV88E6350] = {
3771 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3772 .family = MV88E6XXX_FAMILY_6351,
3773 .name = "Marvell 88E6350",
3774 .num_databases = 4096,
3775 .num_ports = 7,
9dddd478 3776 .port_base_addr = 0x10,
f81ec90f
VD		 3777 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3778 },
3779
3780 [MV88E6351] = {
3781 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3782 .family = MV88E6XXX_FAMILY_6351,
3783 .name = "Marvell 88E6351",
3784 .num_databases = 4096,
3785 .num_ports = 7,
9dddd478 3786 .port_base_addr = 0x10,
f81ec90f
VD		 3787 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3788 },
3789
3790 [MV88E6352] = {
3791 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3792 .family = MV88E6XXX_FAMILY_6352,
3793 .name = "Marvell 88E6352",
3794 .num_databases = 4096,
3795 .num_ports = 7,
9dddd478 3796 .port_base_addr = 0x10,
f81ec90f
VD		 3797 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3798 },
3799};
3800
5f7c0367 3801static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3802{
a439c061 3803 int i;
b9b37713 3804
5f7c0367
VD		 3805 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3806 if (mv88e6xxx_table[i].prod_num == prod_num)
3807 return &mv88e6xxx_table[i];
b9b37713 3808
b9b37713
VD		 3809 return NULL;
3810}
3811
fad09c73 3812static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3813{
3814 const struct mv88e6xxx_info *info;
3815 int id, prod_num, rev;
3816
fad09c73
VD		 3817 id = mv88e6xxx_reg_read(chip, chip->info->port_base_addr,
3818 PORT_SWITCH_ID);
bc46a3d5
VD		 3819 if (id < 0)
3820 return id;
3821
3822 prod_num = (id & 0xfff0) >> 4;
3823 rev = id & 0x000f;
3824
3825 info = mv88e6xxx_lookup_info(prod_num);
3826 if (!info)
3827 return -ENODEV;
3828
caac8545 3829 /* Update the compatible info with the probed one */
fad09c73 3830 chip->info = info;
bc46a3d5 3831
fad09c73
VD		 3832 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3833 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3834
3835 return 0;
3836}
3837
fad09c73 3838static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3839{
fad09c73 3840 struct mv88e6xxx_chip *chip;
469d729f 3841
fad09c73
VD		 3842 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3843 if (!chip)
469d729f
VD		 3844 return NULL;
3845
fad09c73 3846 chip->dev = dev;
469d729f 3847
fad09c73 3848 mutex_init(&chip->reg_lock);
469d729f 3849
fad09c73 3850 return chip;
469d729f
VD		 3851}
3852
fad09c73 3853static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3854 struct mii_bus *bus, int sw_addr)
3855{
3856 /* ADDR[0] pin is unavailable externally and considered zero */
3857 if (sw_addr & 0x1)
3858 return -EINVAL;
3859
914b32f6 3860 if (sw_addr == 0)
fad09c73
VD		 3861 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3862 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3863 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3864 else
3865 return -EINVAL;
3866
fad09c73
VD		 3867 chip->bus = bus;
3868 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3869
3870 return 0;
3871}
3872
fcdce7d0
AL		 3873static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3874 struct device *host_dev, int sw_addr,
3875 void **priv)
a77d43f1 3876{
fad09c73 3877 struct mv88e6xxx_chip *chip;
a439c061 3878 struct mii_bus *bus;
b516d453 3879 int err;
a77d43f1 3880
a439c061 3881 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3882 if (!bus)
3883 return NULL;
3884
fad09c73
VD		 3885 chip = mv88e6xxx_alloc_chip(dsa_dev);
3886 if (!chip)
469d729f
VD		 3887 return NULL;
3888
caac8545 3889 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3890 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3891
fad09c73 3892 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3893 if (err)
3894 goto free;
3895
fad09c73 3896 err = mv88e6xxx_detect(chip);
bc46a3d5 3897 if (err)
469d729f 3898 goto free;
a439c061 3899
fad09c73 3900 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3901 if (err)
469d729f 3902 goto free;
b516d453 3903
fad09c73 3904 *priv = chip;
a439c061 3905
fad09c73 3906 return chip->info->name;
469d729f 3907free:
fad09c73 3908 devm_kfree(dsa_dev, chip);
469d729f
VD		 3909
3910 return NULL;
a77d43f1
AL		 3911}
3912
57d32310 3913static struct dsa_switch_driver mv88e6xxx_switch_driver = {
f81ec90f 3914 .tag_protocol = DSA_TAG_PROTO_EDSA,
fcdce7d0 3915 .probe = mv88e6xxx_drv_probe,
f81ec90f
VD		 3916 .setup = mv88e6xxx_setup,
3917 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3918 .adjust_link = mv88e6xxx_adjust_link,
3919 .get_strings = mv88e6xxx_get_strings,
3920 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3921 .get_sset_count = mv88e6xxx_get_sset_count,
3922 .set_eee = mv88e6xxx_set_eee,
3923 .get_eee = mv88e6xxx_get_eee,
3924#ifdef CONFIG_NET_DSA_HWMON
3925 .get_temp = mv88e6xxx_get_temp,
3926 .get_temp_limit = mv88e6xxx_get_temp_limit,
3927 .set_temp_limit = mv88e6xxx_set_temp_limit,
3928 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3929#endif
f8cd8753 3930 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3931 .get_eeprom = mv88e6xxx_get_eeprom,
3932 .set_eeprom = mv88e6xxx_set_eeprom,
3933 .get_regs_len = mv88e6xxx_get_regs_len,
3934 .get_regs = mv88e6xxx_get_regs,
3935 .port_bridge_join = mv88e6xxx_port_bridge_join,
3936 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3937 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3938 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3939 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3940 .port_vlan_add = mv88e6xxx_port_vlan_add,
3941 .port_vlan_del = mv88e6xxx_port_vlan_del,
3942 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3943 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3944 .port_fdb_add = mv88e6xxx_port_fdb_add,
3945 .port_fdb_del = mv88e6xxx_port_fdb_del,
3946 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3947};
3948
fad09c73 3949static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3950 struct device_node *np)
3951{
fad09c73 3952 struct device *dev = chip->dev;
b7e66a5f
VD		 3953 struct dsa_switch *ds;
3954
3955 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3956 if (!ds)
3957 return -ENOMEM;
3958
3959 ds->dev = dev;
fad09c73 3960 ds->priv = chip;
b7e66a5f
VD		 3961 ds->drv = &mv88e6xxx_switch_driver;
3962
3963 dev_set_drvdata(dev, ds);
3964
3965 return dsa_register_switch(ds, np);
3966}
3967
fad09c73 3968static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3969{
fad09c73 3970 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3971}
3972
57d32310 3973static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3974{
14c7b3c3 3975 struct device *dev = &mdiodev->dev;
f8cd8753 3976 struct device_node *np = dev->of_node;
caac8545 3977 const struct mv88e6xxx_info *compat_info;
fad09c73 3978 struct mv88e6xxx_chip *chip;
f8cd8753 3979 u32 eeprom_len;
52638f71 3980 int err;
14c7b3c3 3981
caac8545
VD		 3982 compat_info = of_device_get_match_data(dev);
3983 if (!compat_info)
3984 return -EINVAL;
3985
fad09c73
VD		 3986 chip = mv88e6xxx_alloc_chip(dev);
3987 if (!chip)
14c7b3c3
AL		 3988 return -ENOMEM;
3989
fad09c73 3990 chip->info = compat_info;
caac8545 3991
fad09c73 3992 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3993 if (err)
3994 return err;
14c7b3c3 3995
fad09c73 3996 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3997 if (err)
3998 return err;
14c7b3c3 3999
fad09c73
VD		 4000 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4001 if (IS_ERR(chip->reset))
4002 return PTR_ERR(chip->reset);
52638f71 4003
fad09c73 4004 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM) &&
f8cd8753 4005 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4006 chip->eeprom_len = eeprom_len;
f8cd8753 4007
fad09c73 4008 err = mv88e6xxx_mdio_register(chip, np);
b516d453
AL		 4009 if (err)
4010 return err;
4011
fad09c73 4012 err = mv88e6xxx_register_switch(chip, np);
83c0afae 4013 if (err) {
fad09c73 4014 mv88e6xxx_mdio_unregister(chip);
83c0afae
AL		 4015 return err;
4016 }
4017
98e67308
BH		 4018 return 0;
4019}
14c7b3c3
AL		 4020
4021static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4022{
4023 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
fad09c73 4024 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
14c7b3c3 4025
fad09c73
VD		 4026 mv88e6xxx_unregister_switch(chip);
4027 mv88e6xxx_mdio_unregister(chip);
14c7b3c3
AL		 4028}
4029
4030static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4031 {
4032 .compatible = "marvell,mv88e6085",
4033 .data = &mv88e6xxx_table[MV88E6085],
4034 },
14c7b3c3
AL		 4035 { /* sentinel */ },
4036};
4037
4038MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4039
4040static struct mdio_driver mv88e6xxx_driver = {
4041 .probe = mv88e6xxx_probe,
4042 .remove = mv88e6xxx_remove,
4043 .mdiodrv.driver = {
4044 .name = "mv88e6085",
4045 .of_match_table = mv88e6xxx_of_match,
4046 },
4047};
4048
4049static int __init mv88e6xxx_init(void)
4050{
4051 register_switch_driver(&mv88e6xxx_switch_driver);
4052 return mdio_driver_register(&mv88e6xxx_driver);
4053}
98e67308
BH		 4054module_init(mv88e6xxx_init);
4055
4056static void __exit mv88e6xxx_cleanup(void)
4057{
14c7b3c3 4058 mdio_driver_unregister(&mv88e6xxx_driver);
f81ec90f 4059 unregister_switch_driver(&mv88e6xxx_switch_driver);
98e67308
BH		 4060}
4061module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4062
4063MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4064MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4065MODULE_LICENSE("GPL");
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