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net: dsa: mv88e6xxx: add helper to disable ports
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
e57e5e77
VD		 225static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227{
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
b3469dd8 230 if (!chip->info->ops->phy_read)
e57e5e77
VD		 231 return -EOPNOTSUPP;
232
b3469dd8 233 return chip->info->ops->phy_read(chip, addr, reg, val);
e57e5e77
VD		 234}
235
236static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
b3469dd8 241 if (!chip->info->ops->phy_write)
e57e5e77
VD		 242 return -EOPNOTSUPP;
243
b3469dd8 244 return chip->info->ops->phy_write(chip, addr, reg, val);
e57e5e77
VD		 245}
246
09cb7dfd
VD		 247static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248{
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253}
254
255static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256{
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265}
266
267static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269{
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283}
284
285static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287{
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301}
302
303static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304{
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
309static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310{
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313}
314
dc30c35b
AL		 315static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316{
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321}
322
323static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324{
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329}
330
331static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332{
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356}
357
358static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359{
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363}
364
365static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366{
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383out:
384 mutex_unlock(&chip->reg_lock);
385}
386
387static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393};
394
395static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398{
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406}
407
408static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411};
412
413static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414{
415 int irq, virq;
3460a577
AL		 416 u16 mask;
417
418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
419 mask |= GENMASK(chip->g1_irq.nirqs, 0);
420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
421
422 free_irq(chip->irq, chip);
dc30c35b 423
5edef2f2 424 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 425 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 426 irq_dispose_mapping(virq);
427 }
428
a3db3d3a 429 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 430}
431
432static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
433{
3dd0ef05
AL		 434 int err, irq, virq;
435 u16 reg, mask;
dc30c35b
AL		 436
437 chip->g1_irq.nirqs = chip->info->g1_irqs;
438 chip->g1_irq.domain = irq_domain_add_simple(
439 NULL, chip->g1_irq.nirqs, 0,
440 &mv88e6xxx_g1_irq_domain_ops, chip);
441 if (!chip->g1_irq.domain)
442 return -ENOMEM;
443
444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
445 irq_create_mapping(chip->g1_irq.domain, irq);
446
447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
448 chip->g1_irq.masked = ~0;
449
3dd0ef05 450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 451 if (err)
3dd0ef05 452 goto out_mapping;
dc30c35b 453
3dd0ef05 454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 455
3dd0ef05 456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 457 if (err)
3dd0ef05 458 goto out_disable;
dc30c35b
AL		 459
460 /* Reading the interrupt status clears (most of) them */
461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
462 if (err)
3dd0ef05 463 goto out_disable;
dc30c35b
AL		 464
465 err = request_threaded_irq(chip->irq, NULL,
466 mv88e6xxx_g1_irq_thread_fn,
467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
468 dev_name(chip->dev), chip);
469 if (err)
3dd0ef05 470 goto out_disable;
dc30c35b
AL		 471
472 return 0;
473
3dd0ef05
AL		 474out_disable:
475 mask |= GENMASK(chip->g1_irq.nirqs, 0);
476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
477
478out_mapping:
479 for (irq = 0; irq < 16; irq++) {
480 virq = irq_find_mapping(chip->g1_irq.domain, irq);
481 irq_dispose_mapping(virq);
482 }
483
484 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 485
486 return err;
487}
488
ec561276 489int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 490{
6441e669 491 int i;
2d79af6e 492
6441e669 493 for (i = 0; i < 16; i++) {
2d79af6e
VD		 494 u16 val;
495 int err;
496
497 err = mv88e6xxx_read(chip, addr, reg, &val);
498 if (err)
499 return err;
500
501 if (!(val & mask))
502 return 0;
503
504 usleep_range(1000, 2000);
505 }
506
30853553 507 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 508 return -ETIMEDOUT;
509}
510
f22ab641 511/* Indirect write to single pointer-data register with an Update bit */
ec561276 512int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 513{
514 u16 val;
0f02b4f7 515 int err;
f22ab641
VD		 516
517 /* Wait until the previous operation is completed */
0f02b4f7
AL		 518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
519 if (err)
520 return err;
f22ab641
VD		 521
522 /* Set the Update bit to trigger a write operation */
523 val = BIT(15) | update;
524
525 return mv88e6xxx_write(chip, addr, reg, val);
526}
527
a935c052 528static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6
VD		 529{
530 u16 val;
a935c052 531 int i, err;
914b32f6 532
a935c052 533 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
914b32f6
VD		 534 if (err)
535 return err;
536
a935c052
VD		 537 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
538 val & ~GLOBAL_CONTROL_PPU_ENABLE);
539 if (err)
540 return err;
2e5f0320 541
6441e669 542 for (i = 0; i < 16; i++) {
a935c052
VD		 543 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
544 if (err)
545 return err;
48ace4ef 546
19b2f97e 547 usleep_range(1000, 2000);
a935c052 548 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
85686581 549 return 0;
2e5f0320
LB		 550 }
551
552 return -ETIMEDOUT;
553}
554
fad09c73 555static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 556{
a935c052
VD		 557 u16 val;
558 int i, err;
2e5f0320 559
a935c052
VD		 560 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
561 if (err)
562 return err;
48ace4ef 563
a935c052
VD		 564 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
565 val | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 566 if (err)
567 return err;
2e5f0320 568
6441e669 569 for (i = 0; i < 16; i++) {
a935c052
VD		 570 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
571 if (err)
572 return err;
48ace4ef 573
19b2f97e 574 usleep_range(1000, 2000);
a935c052 575 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
85686581 576 return 0;
2e5f0320
LB		 577 }
578
579 return -ETIMEDOUT;
580}
581
582static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
583{
fad09c73 584 struct mv88e6xxx_chip *chip;
2e5f0320 585
fad09c73 586 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 587
fad09c73 588 mutex_lock(&chip->reg_lock);
762eb67b 589
fad09c73
VD		 590 if (mutex_trylock(&chip->ppu_mutex)) {
591 if (mv88e6xxx_ppu_enable(chip) == 0)
592 chip->ppu_disabled = 0;
593 mutex_unlock(&chip->ppu_mutex);
2e5f0320 594 }
762eb67b 595
fad09c73 596 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 597}
598
599static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
600{
fad09c73 601 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 602
fad09c73 603 schedule_work(&chip->ppu_work);
2e5f0320
LB		 604}
605
fad09c73 606static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 607{
2e5f0320
LB		 608 int ret;
609
fad09c73 610 mutex_lock(&chip->ppu_mutex);
2e5f0320 611
3675c8d7 612 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 613 * we can access the PHY registers. If it was already
614 * disabled, cancel the timer that is going to re-enable
615 * it.
616 */
fad09c73
VD		 617 if (!chip->ppu_disabled) {
618 ret = mv88e6xxx_ppu_disable(chip);
85686581 619 if (ret < 0) {
fad09c73 620 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 621 return ret;
622 }
fad09c73 623 chip->ppu_disabled = 1;
2e5f0320 624 } else {
fad09c73 625 del_timer(&chip->ppu_timer);
85686581 626 ret = 0;
2e5f0320
LB		 627 }
628
629 return ret;
630}
631
fad09c73 632static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 633{
3675c8d7 634 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 635 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
636 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 637}
638
fad09c73 639static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 640{
fad09c73
VD		 641 mutex_init(&chip->ppu_mutex);
642 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 643 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
644 (unsigned long)chip);
2e5f0320
LB		 645}
646
930188ce
AL		 647static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
648{
649 del_timer_sync(&chip->ppu_timer);
650}
651
e57e5e77
VD		 652static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
653 int reg, u16 *val)
2e5f0320 654{
e57e5e77 655 int err;
2e5f0320 656
e57e5e77
VD		 657 err = mv88e6xxx_ppu_access_get(chip);
658 if (!err) {
659 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 660 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 661 }
662
e57e5e77 663 return err;
2e5f0320
LB		 664}
665
e57e5e77
VD		 666static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
667 int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 693}
694
fad09c73 695static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 696{
fad09c73 697 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 698}
699
fad09c73 700static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 703}
704
fad09c73 705static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 708}
709
fad09c73 710static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 711{
fad09c73 712 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 713}
714
d78343d2
VD		 715static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
716 int link, int speed, int duplex,
717 phy_interface_t mode)
718{
719 int err;
720
721 if (!chip->info->ops->port_set_link)
722 return 0;
723
724 /* Port's MAC control must not be changed unless the link is down */
725 err = chip->info->ops->port_set_link(chip, port, 0);
726 if (err)
727 return err;
728
729 if (chip->info->ops->port_set_speed) {
730 err = chip->info->ops->port_set_speed(chip, port, speed);
731 if (err && err != -EOPNOTSUPP)
732 goto restore_link;
733 }
734
735 if (chip->info->ops->port_set_duplex) {
736 err = chip->info->ops->port_set_duplex(chip, port, duplex);
737 if (err && err != -EOPNOTSUPP)
738 goto restore_link;
739 }
740
741 if (chip->info->ops->port_set_rgmii_delay) {
742 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
743 if (err && err != -EOPNOTSUPP)
744 goto restore_link;
745 }
746
747 err = 0;
748restore_link:
749 if (chip->info->ops->port_set_link(chip, port, link))
750 netdev_err(chip->ds->ports[port].netdev,
751 "failed to restore MAC's link\n");
752
753 return err;
754}
755
dea87024
AL		 756/* We expect the switch to perform auto negotiation if there is a real
757 * phy. However, in the case of a fixed link phy, we force the port
758 * settings from the fixed link settings.
759 */
f81ec90f
VD		 760static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
761 struct phy_device *phydev)
dea87024 762{
04bed143 763 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 764 int err;
dea87024
AL		 765
766 if (!phy_is_pseudo_fixed_link(phydev))
767 return;
768
fad09c73 769 mutex_lock(&chip->reg_lock);
d78343d2
VD		 770 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
771 phydev->duplex, phydev->interface);
fad09c73 772 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 773
774 if (err && err != -EOPNOTSUPP)
775 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 776}
777
a605a0fe 778static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 779{
a605a0fe
AL		 780 if (!chip->info->ops->stats_snapshot)
781 return -EOPNOTSUPP;
91da11f8 782
a605a0fe 783 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 784}
785
e413e7e1 786static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 787 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
788 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
789 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
790 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
791 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
792 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
793 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
794 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
795 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
796 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
797 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
798 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
799 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
800 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
801 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
802 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
803 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
804 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
805 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
806 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
807 { "single", 4, 0x14, STATS_TYPE_BANK0, },
808 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
809 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
810 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
811 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
812 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
813 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
814 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
815 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
816 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
817 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
818 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
819 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
820 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
821 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
822 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
823 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
824 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
826 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
828 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
829 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
830 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
831 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
832 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
833 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
834 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
835 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
836 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
837 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
838 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
839 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
840 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
841 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
842 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
843 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
844 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
845 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 846};
847
fad09c73 848static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 849 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 850 int port, u16 bank1_select,
851 u16 histogram)
80c4627b 852{
80c4627b
AL		 853 u32 low;
854 u32 high = 0;
dfafe449 855 u16 reg = 0;
0e7b9925 856 int err;
80c4627b
AL		 857 u64 value;
858
f5e2ed02 859 switch (s->type) {
dfafe449 860 case STATS_TYPE_PORT:
0e7b9925
AL		 861 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
862 if (err)
80c4627b
AL		 863 return UINT64_MAX;
864
0e7b9925 865 low = reg;
80c4627b 866 if (s->sizeof_stat == 4) {
0e7b9925
AL		 867 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
868 if (err)
80c4627b 869 return UINT64_MAX;
0e7b9925 870 high = reg;
80c4627b 871 }
f5e2ed02 872 break;
dfafe449 873 case STATS_TYPE_BANK1:
e0d8b615 874 reg = bank1_select;
dfafe449
AL		 875 /* fall through */
876 case STATS_TYPE_BANK0:
e0d8b615 877 reg |= s->reg | histogram;
7f9ef3af 878 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 879 if (s->sizeof_stat == 8)
7f9ef3af 880 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 881 }
882 value = (((u64)high) << 16) | low;
883 return value;
884}
885
dfafe449
AL		 886static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
887 uint8_t *data, int types)
91da11f8 888{
f5e2ed02
AL		 889 struct mv88e6xxx_hw_stat *stat;
890 int i, j;
91da11f8 891
f5e2ed02
AL		 892 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
893 stat = &mv88e6xxx_hw_stats[i];
dfafe449 894 if (stat->type & types) {
f5e2ed02
AL		 895 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
896 ETH_GSTRING_LEN);
897 j++;
898 }
91da11f8 899 }
e413e7e1
AL		 900}
901
dfafe449
AL		 902static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
903 uint8_t *data)
904{
905 mv88e6xxx_stats_get_strings(chip, data,
906 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
907}
908
909static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
910 uint8_t *data)
911{
912 mv88e6xxx_stats_get_strings(chip, data,
913 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
914}
915
916static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
917 uint8_t *data)
e413e7e1 918{
04bed143 919 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 920
921 if (chip->info->ops->stats_get_strings)
922 chip->info->ops->stats_get_strings(chip, data);
923}
924
925static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
926 int types)
927{
f5e2ed02
AL		 928 struct mv88e6xxx_hw_stat *stat;
929 int i, j;
930
931 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
932 stat = &mv88e6xxx_hw_stats[i];
dfafe449 933 if (stat->type & types)
f5e2ed02
AL		 934 j++;
935 }
936 return j;
e413e7e1
AL		 937}
938
dfafe449
AL		 939static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
940{
941 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
942 STATS_TYPE_PORT);
943}
944
945static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
946{
947 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
948 STATS_TYPE_BANK1);
949}
950
951static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
952{
953 struct mv88e6xxx_chip *chip = ds->priv;
954
955 if (chip->info->ops->stats_get_sset_count)
956 return chip->info->ops->stats_get_sset_count(chip);
957
958 return 0;
959}
960
052f947f 961static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 962 uint64_t *data, int types,
963 u16 bank1_select, u16 histogram)
052f947f
AL		 964{
965 struct mv88e6xxx_hw_stat *stat;
966 int i, j;
967
968 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
969 stat = &mv88e6xxx_hw_stats[i];
970 if (stat->type & types) {
e0d8b615
AL		 971 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
972 bank1_select,
973 histogram);
052f947f
AL		 974 j++;
975 }
976 }
977}
978
979static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
980 uint64_t *data)
981{
982 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 983 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
984 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 985}
986
987static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
988 uint64_t *data)
989{
990 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 991 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
992 GLOBAL_STATS_OP_BANK_1_BIT_9,
993 GLOBAL_STATS_OP_HIST_RX_TX);
994}
995
996static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
997 uint64_t *data)
998{
999 return mv88e6xxx_stats_get_stats(chip, port, data,
1000 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1001 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1002}
1003
1004static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1005 uint64_t *data)
1006{
1007 if (chip->info->ops->stats_get_stats)
1008 chip->info->ops->stats_get_stats(chip, port, data);
1009}
1010
f81ec90f
VD		 1011static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1012 uint64_t *data)
e413e7e1 1013{
04bed143 1014 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1015 int ret;
f5e2ed02 1016
fad09c73 1017 mutex_lock(&chip->reg_lock);
f5e2ed02 1018
a605a0fe 1019 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1020 if (ret < 0) {
fad09c73 1021 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1022 return;
1023 }
052f947f
AL		 1024
1025 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1026
fad09c73 1027 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1028}
1029
de227387
AL		 1030static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1031{
1032 if (chip->info->ops->stats_set_histogram)
1033 return chip->info->ops->stats_set_histogram(chip);
1034
1035 return 0;
1036}
1037
f81ec90f 1038static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1039{
1040 return 32 * sizeof(u16);
1041}
1042
f81ec90f
VD		 1043static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1044 struct ethtool_regs *regs, void *_p)
a1ab91f3 1045{
04bed143 1046 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1047 int err;
1048 u16 reg;
a1ab91f3
GR		 1049 u16 *p = _p;
1050 int i;
1051
1052 regs->version = 0;
1053
1054 memset(p, 0xff, 32 * sizeof(u16));
1055
fad09c73 1056 mutex_lock(&chip->reg_lock);
23062513 1057
a1ab91f3 1058 for (i = 0; i < 32; i++) {
a1ab91f3 1059
0e7b9925
AL		 1060 err = mv88e6xxx_port_read(chip, port, i, &reg);
1061 if (!err)
1062 p[i] = reg;
a1ab91f3 1063 }
23062513 1064
fad09c73 1065 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1066}
1067
fad09c73 1068static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1069{
a935c052 1070 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1071}
1072
f81ec90f
VD		 1073static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1074 struct ethtool_eee *e)
11b3b45d 1075{
04bed143 1076 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1077 u16 reg;
1078 int err;
11b3b45d 1079
fad09c73 1080 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1081 return -EOPNOTSUPP;
1082
fad09c73 1083 mutex_lock(&chip->reg_lock);
2f40c698 1084
9c93829c
VD		 1085 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1086 if (err)
2f40c698 1087 goto out;
11b3b45d
GR		 1088
1089 e->eee_enabled = !!(reg & 0x0200);
1090 e->tx_lpi_enabled = !!(reg & 0x0100);
1091
0e7b9925 1092 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1093 if (err)
2f40c698 1094 goto out;
11b3b45d 1095
cca8b133 1096 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1097out:
fad09c73 1098 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1099
1100 return err;
11b3b45d
GR		 1101}
1102
f81ec90f
VD		 1103static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1104 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1105{
04bed143 1106 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1107 u16 reg;
1108 int err;
11b3b45d 1109
fad09c73 1110 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1111 return -EOPNOTSUPP;
1112
fad09c73 1113 mutex_lock(&chip->reg_lock);
11b3b45d 1114
9c93829c
VD		 1115 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1116 if (err)
2f40c698
AL		 1117 goto out;
1118
9c93829c 1119 reg &= ~0x0300;
2f40c698
AL		 1120 if (e->eee_enabled)
1121 reg |= 0x0200;
1122 if (e->tx_lpi_enabled)
1123 reg |= 0x0100;
1124
9c93829c 1125 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1126out:
fad09c73 1127 mutex_unlock(&chip->reg_lock);
2f40c698 1128
9c93829c 1129 return err;
11b3b45d
GR		 1130}
1131
fad09c73 1132static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1133{
a935c052
VD		 1134 u16 val;
1135 int err;
facd95b2 1136
6dc10bbc 1137 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1138 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1139 if (err)
1140 return err;
fad09c73 1141 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1142 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1143 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1144 if (err)
1145 return err;
11ea809f 1146
a935c052
VD		 1147 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1148 (val & 0xfff) | ((fid << 8) & 0xf000));
1149 if (err)
1150 return err;
11ea809f
VD		 1151
1152 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1153 cmd |= fid & 0xf;
b426e5f7
VD		 1154 }
1155
a935c052
VD		 1156 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1157 if (err)
1158 return err;
facd95b2 1159
fad09c73 1160 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1161}
1162
fad09c73 1163static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1164 struct mv88e6xxx_atu_entry *entry)
1165{
1166 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1167
1168 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1169 unsigned int mask, shift;
1170
1171 if (entry->trunk) {
1172 data |= GLOBAL_ATU_DATA_TRUNK;
1173 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1174 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1175 } else {
1176 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1177 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1178 }
1179
1180 data |= (entry->portv_trunkid << shift) & mask;
1181 }
1182
a935c052 1183 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1184}
1185
fad09c73 1186static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1187 struct mv88e6xxx_atu_entry *entry,
1188 bool static_too)
facd95b2 1189{
7fb5e755
VD		 1190 int op;
1191 int err;
facd95b2 1192
fad09c73 1193 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1194 if (err)
1195 return err;
facd95b2 1196
fad09c73 1197 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1198 if (err)
1199 return err;
1200
1201 if (entry->fid) {
7fb5e755
VD		 1202 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1203 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1204 } else {
1205 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1206 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1207 }
1208
fad09c73 1209 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1210}
1211
fad09c73 1212static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1213 u16 fid, bool static_too)
7fb5e755
VD		 1214{
1215 struct mv88e6xxx_atu_entry entry = {
1216 .fid = fid,
1217 .state = 0, /* EntryState bits must be 0 */
1218 };
70cc99d1 1219
fad09c73 1220 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1221}
1222
fad09c73 1223static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1224 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1225{
1226 struct mv88e6xxx_atu_entry entry = {
1227 .trunk = false,
1228 .fid = fid,
1229 };
1230
1231 /* EntryState bits must be 0xF */
1232 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1233
1234 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1235 entry.portv_trunkid = (to_port & 0x0f) << 4;
1236 entry.portv_trunkid |= from_port & 0x0f;
1237
fad09c73 1238 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1239}
1240
fad09c73 1241static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1242 int port, bool static_too)
9f4d55d2
VD		 1243{
1244 /* Destination port 0xF means remove the entries */
fad09c73 1245 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1246}
1247
fad09c73 1248static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1249{
fad09c73 1250 struct net_device *bridge = chip->ports[port].bridge_dev;
fad09c73 1251 struct dsa_switch *ds = chip->ds;
b7666efe 1252 u16 output_ports = 0;
b7666efe
VD		 1253 int i;
1254
1255 /* allow CPU port or DSA link(s) to send frames to every port */
1256 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1257 output_ports = ~0;
b7666efe 1258 } else {
370b4ffb 1259 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1260 /* allow sending frames to every group member */
fad09c73 1261 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1262 output_ports |= BIT(i);
1263
1264 /* allow sending frames to CPU port and DSA link(s) */
1265 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1266 output_ports |= BIT(i);
1267 }
1268 }
1269
1270 /* prevent frames from going back out of the port they came in on */
1271 output_ports &= ~BIT(port);
facd95b2 1272
5a7921f4 1273 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1274}
1275
f81ec90f
VD		 1276static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1277 u8 state)
facd95b2 1278{
04bed143 1279 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1280 int stp_state;
553eb544 1281 int err;
facd95b2
GR		 1282
1283 switch (state) {
1284 case BR_STATE_DISABLED:
cca8b133 1285 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1286 break;
1287 case BR_STATE_BLOCKING:
1288 case BR_STATE_LISTENING:
cca8b133 1289 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1290 break;
1291 case BR_STATE_LEARNING:
cca8b133 1292 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1293 break;
1294 case BR_STATE_FORWARDING:
1295 default:
cca8b133 1296 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1297 break;
1298 }
1299
fad09c73 1300 mutex_lock(&chip->reg_lock);
e28def33 1301 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1302 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1303
1304 if (err)
e28def33 1305 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1306}
1307
749efcb8
VD		 1308static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1309{
1310 struct mv88e6xxx_chip *chip = ds->priv;
1311 int err;
1312
1313 mutex_lock(&chip->reg_lock);
1314 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1315 mutex_unlock(&chip->reg_lock);
1316
1317 if (err)
1318 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1319}
1320
fad09c73 1321static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1322{
a935c052 1323 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1324}
1325
fad09c73 1326static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1327{
a935c052 1328 int err;
6b17e864 1329
a935c052
VD		 1330 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1331 if (err)
1332 return err;
6b17e864 1333
fad09c73 1334 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1335}
1336
fad09c73 1337static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1338{
1339 int ret;
1340
fad09c73 1341 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1342 if (ret < 0)
1343 return ret;
1344
fad09c73 1345 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1346}
1347
fad09c73 1348static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1349 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1350 unsigned int nibble_offset)
1351{
b8fee957 1352 u16 regs[3];
a935c052 1353 int i, err;
b8fee957
VD		 1354
1355 for (i = 0; i < 3; ++i) {
a935c052 1356 u16 *reg = &regs[i];
b8fee957 1357
a935c052
VD		 1358 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1359 if (err)
1360 return err;
b8fee957
VD		 1361 }
1362
370b4ffb 1363 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1364 unsigned int shift = (i % 4) * 4 + nibble_offset;
1365 u16 reg = regs[i / 4];
1366
1367 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1368 }
1369
1370 return 0;
1371}
1372
fad09c73 1373static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1374 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1375{
fad09c73 1376 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1377}
1378
fad09c73 1379static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1380 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1381{
fad09c73 1382 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1383}
1384
fad09c73 1385static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1386 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1387 unsigned int nibble_offset)
1388{
7dad08d7 1389 u16 regs[3] = { 0 };
a935c052 1390 int i, err;
7dad08d7 1391
370b4ffb 1392 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1393 unsigned int shift = (i % 4) * 4 + nibble_offset;
1394 u8 data = entry->data[i];
1395
1396 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1397 }
1398
1399 for (i = 0; i < 3; ++i) {
a935c052
VD		 1400 u16 reg = regs[i];
1401
1402 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1403 if (err)
1404 return err;
7dad08d7
VD		 1405 }
1406
1407 return 0;
1408}
1409
fad09c73 1410static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1411 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1412{
fad09c73 1413 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1414}
1415
fad09c73 1416static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1417 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1418{
fad09c73 1419 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1420}
1421
fad09c73 1422static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1423{
a935c052
VD		 1424 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1425 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1426}
1427
fad09c73 1428static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1429 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1430{
b4e47c0f 1431 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1432 u16 val;
1433 int err;
b8fee957 1434
a935c052
VD		 1435 err = _mv88e6xxx_vtu_wait(chip);
1436 if (err)
1437 return err;
b8fee957 1438
a935c052
VD		 1439 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1440 if (err)
1441 return err;
b8fee957 1442
a935c052
VD		 1443 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1444 if (err)
1445 return err;
b8fee957 1446
a935c052
VD		 1447 next.vid = val & GLOBAL_VTU_VID_MASK;
1448 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1449
1450 if (next.valid) {
a935c052
VD		 1451 err = mv88e6xxx_vtu_data_read(chip, &next);
1452 if (err)
1453 return err;
b8fee957 1454
6dc10bbc 1455 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1456 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1457 if (err)
1458 return err;
b8fee957 1459
a935c052 1460 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1461 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1462 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1463 * VTU DBNum[3:0] are located in VTU Operation 3:0
1464 */
a935c052
VD		 1465 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1466 if (err)
1467 return err;
11ea809f 1468
a935c052
VD		 1469 next.fid = (val & 0xf00) >> 4;
1470 next.fid |= val & 0xf;
2e7bd5ef 1471 }
b8fee957 1472
fad09c73 1473 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1474 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1475 if (err)
1476 return err;
b8fee957 1477
a935c052 1478 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1479 }
1480 }
1481
1482 *entry = next;
1483 return 0;
1484}
1485
f81ec90f
VD		 1486static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1487 struct switchdev_obj_port_vlan *vlan,
1488 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1489{
04bed143 1490 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1491 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1492 u16 pvid;
1493 int err;
1494
fad09c73 1495 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1496 return -EOPNOTSUPP;
1497
fad09c73 1498 mutex_lock(&chip->reg_lock);
ceff5eff 1499
77064f37 1500 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1501 if (err)
1502 goto unlock;
1503
fad09c73 1504 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1505 if (err)
1506 goto unlock;
1507
1508 do {
fad09c73 1509 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1510 if (err)
1511 break;
1512
1513 if (!next.valid)
1514 break;
1515
1516 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1517 continue;
1518
1519 /* reinit and dump this VLAN obj */
57d32310
VD		 1520 vlan->vid_begin = next.vid;
1521 vlan->vid_end = next.vid;
ceff5eff
VD		 1522 vlan->flags = 0;
1523
1524 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1525 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1526
1527 if (next.vid == pvid)
1528 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1529
1530 err = cb(&vlan->obj);
1531 if (err)
1532 break;
1533 } while (next.vid < GLOBAL_VTU_VID_MASK);
1534
1535unlock:
fad09c73 1536 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1537
1538 return err;
1539}
1540
fad09c73 1541static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1542 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1543{
11ea809f 1544 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1545 u16 reg = 0;
a935c052 1546 int err;
7dad08d7 1547
a935c052
VD		 1548 err = _mv88e6xxx_vtu_wait(chip);
1549 if (err)
1550 return err;
7dad08d7
VD		 1551
1552 if (!entry->valid)
1553 goto loadpurge;
1554
1555 /* Write port member tags */
a935c052
VD		 1556 err = mv88e6xxx_vtu_data_write(chip, entry);
1557 if (err)
1558 return err;
7dad08d7 1559
fad09c73 1560 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1561 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1562 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1563 if (err)
1564 return err;
b426e5f7 1565 }
7dad08d7 1566
6dc10bbc 1567 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1568 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1569 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1570 if (err)
1571 return err;
fad09c73 1572 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1573 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1574 * VTU DBNum[3:0] are located in VTU Operation 3:0
1575 */
1576 op |= (entry->fid & 0xf0) << 8;
1577 op |= entry->fid & 0xf;
7dad08d7
VD		 1578 }
1579
1580 reg = GLOBAL_VTU_VID_VALID;
1581loadpurge:
1582 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1583 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1584 if (err)
1585 return err;
7dad08d7 1586
fad09c73 1587 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1588}
1589
fad09c73 1590static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1591 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1592{
b4e47c0f 1593 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1594 u16 val;
1595 int err;
0d3b33e6 1596
a935c052
VD		 1597 err = _mv88e6xxx_vtu_wait(chip);
1598 if (err)
1599 return err;
0d3b33e6 1600
a935c052
VD		 1601 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1602 sid & GLOBAL_VTU_SID_MASK);
1603 if (err)
1604 return err;
0d3b33e6 1605
a935c052
VD		 1606 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1607 if (err)
1608 return err;
0d3b33e6 1609
a935c052
VD		 1610 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1611 if (err)
1612 return err;
0d3b33e6 1613
a935c052 1614 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1615
a935c052
VD		 1616 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1617 if (err)
1618 return err;
0d3b33e6 1619
a935c052 1620 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1621
1622 if (next.valid) {
a935c052
VD		 1623 err = mv88e6xxx_stu_data_read(chip, &next);
1624 if (err)
1625 return err;
0d3b33e6
VD		 1626 }
1627
1628 *entry = next;
1629 return 0;
1630}
1631
fad09c73 1632static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1633 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1634{
1635 u16 reg = 0;
a935c052 1636 int err;
0d3b33e6 1637
a935c052
VD		 1638 err = _mv88e6xxx_vtu_wait(chip);
1639 if (err)
1640 return err;
0d3b33e6
VD		 1641
1642 if (!entry->valid)
1643 goto loadpurge;
1644
1645 /* Write port states */
a935c052
VD		 1646 err = mv88e6xxx_stu_data_write(chip, entry);
1647 if (err)
1648 return err;
0d3b33e6
VD		 1649
1650 reg = GLOBAL_VTU_VID_VALID;
1651loadpurge:
a935c052
VD		 1652 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1653 if (err)
1654 return err;
0d3b33e6
VD		 1655
1656 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1657 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1658 if (err)
1659 return err;
0d3b33e6 1660
fad09c73 1661 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1662}
1663
fad09c73 1664static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1665{
1666 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1667 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1668 int i, err;
3285f9e8
VD		 1669
1670 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1671
2db9ce1f 1672 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1673 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1674 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1675 if (err)
1676 return err;
1677
1678 set_bit(*fid, fid_bitmap);
1679 }
1680
3285f9e8 1681 /* Set every FID bit used by the VLAN entries */
fad09c73 1682 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1683 if (err)
1684 return err;
1685
1686 do {
fad09c73 1687 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1688 if (err)
1689 return err;
1690
1691 if (!vlan.valid)
1692 break;
1693
1694 set_bit(vlan.fid, fid_bitmap);
1695 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1696
1697 /* The reset value 0x000 is used to indicate that multiple address
1698 * databases are not needed. Return the next positive available.
1699 */
1700 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1701 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1702 return -ENOSPC;
1703
1704 /* Clear the database */
fad09c73 1705 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1706}
1707
fad09c73 1708static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1709 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1710{
fad09c73 1711 struct dsa_switch *ds = chip->ds;
b4e47c0f 1712 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1713 .valid = true,
1714 .vid = vid,
1715 };
3285f9e8
VD		 1716 int i, err;
1717
fad09c73 1718 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1719 if (err)
1720 return err;
0d3b33e6 1721
3d131f07 1722 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1723 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1724 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1725 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1726 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1727
fad09c73
VD		 1728 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1729 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1730 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1731
1732 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1733 * implemented, only one STU entry is needed to cover all VTU
1734 * entries. Thus, validate the SID 0.
1735 */
1736 vlan.sid = 0;
fad09c73 1737 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1738 if (err)
1739 return err;
1740
1741 if (vstp.sid != vlan.sid || !vstp.valid) {
1742 memset(&vstp, 0, sizeof(vstp));
1743 vstp.valid = true;
1744 vstp.sid = vlan.sid;
1745
fad09c73 1746 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1747 if (err)
1748 return err;
1749 }
0d3b33e6
VD		 1750 }
1751
1752 *entry = vlan;
1753 return 0;
1754}
1755
fad09c73 1756static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1757 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1758{
1759 int err;
1760
1761 if (!vid)
1762 return -EINVAL;
1763
fad09c73 1764 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1765 if (err)
1766 return err;
1767
fad09c73 1768 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1769 if (err)
1770 return err;
1771
1772 if (entry->vid != vid || !entry->valid) {
1773 if (!creat)
1774 return -EOPNOTSUPP;
1775 /* -ENOENT would've been more appropriate, but switchdev expects
1776 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1777 */
1778
fad09c73 1779 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1780 }
1781
1782 return err;
1783}
1784
da9c359e
VD		 1785static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1786 u16 vid_begin, u16 vid_end)
1787{
04bed143 1788 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1789 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1790 int i, err;
1791
1792 if (!vid_begin)
1793 return -EOPNOTSUPP;
1794
fad09c73 1795 mutex_lock(&chip->reg_lock);
da9c359e 1796
fad09c73 1797 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1798 if (err)
1799 goto unlock;
1800
1801 do {
fad09c73 1802 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1803 if (err)
1804 goto unlock;
1805
1806 if (!vlan.valid)
1807 break;
1808
1809 if (vlan.vid > vid_end)
1810 break;
1811
370b4ffb 1812 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1813 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1814 continue;
1815
1816 if (vlan.data[i] ==
1817 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1818 continue;
1819
fad09c73
VD		 1820 if (chip->ports[i].bridge_dev ==
1821 chip->ports[port].bridge_dev)
da9c359e
VD		 1822 break; /* same bridge, check next VLAN */
1823
c8b09808 1824 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1825 "hardware VLAN %d already used by %s\n",
1826 vlan.vid,
fad09c73 1827 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1828 err = -EOPNOTSUPP;
1829 goto unlock;
1830 }
1831 } while (vlan.vid < vid_end);
1832
1833unlock:
fad09c73 1834 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1835
1836 return err;
1837}
1838
f81ec90f
VD		 1839static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1840 bool vlan_filtering)
214cdb99 1841{
04bed143 1842 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1843 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1844 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1845 int err;
214cdb99 1846
fad09c73 1847 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1848 return -EOPNOTSUPP;
1849
fad09c73 1850 mutex_lock(&chip->reg_lock);
385a0995 1851 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1852 mutex_unlock(&chip->reg_lock);
214cdb99 1853
0e7b9925 1854 return err;
214cdb99
VD		 1855}
1856
57d32310
VD		 1857static int
1858mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1859 const struct switchdev_obj_port_vlan *vlan,
1860 struct switchdev_trans *trans)
76e398a6 1861{
04bed143 1862 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1863 int err;
1864
fad09c73 1865 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1866 return -EOPNOTSUPP;
1867
da9c359e
VD		 1868 /* If the requested port doesn't belong to the same bridge as the VLAN
1869 * members, do not support it (yet) and fallback to software VLAN.
1870 */
1871 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1872 vlan->vid_end);
1873 if (err)
1874 return err;
1875
76e398a6
VD		 1876 /* We don't need any dynamic resource from the kernel (yet),
1877 * so skip the prepare phase.
1878 */
1879 return 0;
1880}
1881
fad09c73 1882static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1883 u16 vid, bool untagged)
0d3b33e6 1884{
b4e47c0f 1885 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1886 int err;
1887
fad09c73 1888 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1889 if (err)
76e398a6 1890 return err;
0d3b33e6 1891
0d3b33e6
VD		 1892 vlan.data[port] = untagged ?
1893 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1894 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1895
fad09c73 1896 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1897}
1898
f81ec90f
VD		 1899static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1900 const struct switchdev_obj_port_vlan *vlan,
1901 struct switchdev_trans *trans)
76e398a6 1902{
04bed143 1903 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1904 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1905 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1906 u16 vid;
76e398a6 1907
fad09c73 1908 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1909 return;
1910
fad09c73 1911 mutex_lock(&chip->reg_lock);
76e398a6 1912
4d5770b3 1913 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1914 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1915 netdev_err(ds->ports[port].netdev,
1916 "failed to add VLAN %d%c\n",
4d5770b3 1917 vid, untagged ? 'u' : 't');
76e398a6 1918
77064f37 1919 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1920 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1921 vlan->vid_end);
0d3b33e6 1922
fad09c73 1923 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1924}
1925
fad09c73 1926static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1927 int port, u16 vid)
7dad08d7 1928{
fad09c73 1929 struct dsa_switch *ds = chip->ds;
b4e47c0f 1930 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1931 int i, err;
1932
fad09c73 1933 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1934 if (err)
76e398a6 1935 return err;
7dad08d7 1936
2fb5ef09
VD		 1937 /* Tell switchdev if this VLAN is handled in software */
1938 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1939 return -EOPNOTSUPP;
7dad08d7
VD		 1940
1941 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1942
1943 /* keep the VLAN unless all ports are excluded */
f02bdffc 1944 vlan.valid = false;
370b4ffb 1945 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1946 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1947 continue;
1948
1949 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1950 vlan.valid = true;
7dad08d7
VD		 1951 break;
1952 }
1953 }
1954
fad09c73 1955 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1956 if (err)
1957 return err;
1958
fad09c73 1959 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1960}
1961
f81ec90f
VD		 1962static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1963 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1964{
04bed143 1965 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1966 u16 pvid, vid;
1967 int err = 0;
1968
fad09c73 1969 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1970 return -EOPNOTSUPP;
1971
fad09c73 1972 mutex_lock(&chip->reg_lock);
76e398a6 1973
77064f37 1974 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1975 if (err)
1976 goto unlock;
1977
76e398a6 1978 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1979 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1980 if (err)
1981 goto unlock;
1982
1983 if (vid == pvid) {
77064f37 1984 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1985 if (err)
1986 goto unlock;
1987 }
1988 }
1989
7dad08d7 1990unlock:
fad09c73 1991 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1992
1993 return err;
1994}
1995
fad09c73 1996static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 1997 const unsigned char *addr)
defb05b9 1998{
a935c052 1999 int i, err;
defb05b9
GR		 2000
2001 for (i = 0; i < 3; i++) {
a935c052
VD		 2002 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2003 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2004 if (err)
2005 return err;
defb05b9
GR		 2006 }
2007
2008 return 0;
2009}
2010
fad09c73 2011static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2012 unsigned char *addr)
defb05b9 2013{
a935c052
VD		 2014 u16 val;
2015 int i, err;
defb05b9
GR		 2016
2017 for (i = 0; i < 3; i++) {
a935c052
VD		 2018 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2019 if (err)
2020 return err;
2021
2022 addr[i * 2] = val >> 8;
2023 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2024 }
2025
2026 return 0;
2027}
2028
fad09c73 2029static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2030 struct mv88e6xxx_atu_entry *entry)
defb05b9 2031{
6630e236
VD		 2032 int ret;
2033
fad09c73 2034 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2035 if (ret < 0)
2036 return ret;
2037
fad09c73 2038 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2039 if (ret < 0)
2040 return ret;
2041
fad09c73 2042 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2043 if (ret < 0)
87820510
VD		 2044 return ret;
2045
fad09c73 2046 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2047}
87820510 2048
88472939
VD		 2049static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2050 struct mv88e6xxx_atu_entry *entry);
2051
2052static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2053 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2054{
2055 struct mv88e6xxx_atu_entry next;
2056 int err;
2057
2058 eth_broadcast_addr(next.mac);
2059
2060 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2061 if (err)
2062 return err;
2063
2064 do {
2065 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2066 if (err)
2067 return err;
2068
2069 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2070 break;
2071
2072 if (ether_addr_equal(next.mac, addr)) {
2073 *entry = next;
2074 return 0;
2075 }
2076 } while (!is_broadcast_ether_addr(next.mac));
2077
2078 memset(entry, 0, sizeof(*entry));
2079 entry->fid = fid;
2080 ether_addr_copy(entry->mac, addr);
2081
2082 return 0;
2083}
2084
83dabd1f
VD		 2085static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2086 const unsigned char *addr, u16 vid,
2087 u8 state)
fd231c82 2088{
b4e47c0f 2089 struct mv88e6xxx_vtu_entry vlan;
88472939 2090 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2091 int err;
2092
2db9ce1f
VD		 2093 /* Null VLAN ID corresponds to the port private database */
2094 if (vid == 0)
b4e48c50 2095 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2096 else
fad09c73 2097 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2098 if (err)
2099 return err;
fd231c82 2100
88472939
VD		 2101 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2102 if (err)
2103 return err;
2104
2105 /* Purge the ATU entry only if no port is using it anymore */
2106 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2107 entry.portv_trunkid &= ~BIT(port);
2108 if (!entry.portv_trunkid)
2109 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2110 } else {
2111 entry.portv_trunkid |= BIT(port);
2112 entry.state = state;
fd231c82
VD		 2113 }
2114
fad09c73 2115 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2116}
2117
f81ec90f
VD		 2118static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2119 const struct switchdev_obj_port_fdb *fdb,
2120 struct switchdev_trans *trans)
146a3206
VD		 2121{
2122 /* We don't need any dynamic resource from the kernel (yet),
2123 * so skip the prepare phase.
2124 */
2125 return 0;
2126}
2127
f81ec90f
VD		 2128static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2129 const struct switchdev_obj_port_fdb *fdb,
2130 struct switchdev_trans *trans)
87820510 2131{
04bed143 2132 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2133
fad09c73 2134 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2135 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2136 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2137 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2138 mutex_unlock(&chip->reg_lock);
87820510
VD		 2139}
2140
f81ec90f
VD		 2141static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2142 const struct switchdev_obj_port_fdb *fdb)
87820510 2143{
04bed143 2144 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2145 int err;
87820510 2146
fad09c73 2147 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2148 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2149 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2150 mutex_unlock(&chip->reg_lock);
87820510 2151
83dabd1f 2152 return err;
87820510
VD		 2153}
2154
fad09c73 2155static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2156 struct mv88e6xxx_atu_entry *entry)
6630e236 2157{
1d194046 2158 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2159 u16 val;
2160 int err;
1d194046
VD		 2161
2162 next.fid = fid;
defb05b9 2163
a935c052
VD		 2164 err = _mv88e6xxx_atu_wait(chip);
2165 if (err)
2166 return err;
6630e236 2167
a935c052
VD		 2168 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2169 if (err)
2170 return err;
6630e236 2171
a935c052
VD		 2172 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2173 if (err)
2174 return err;
6630e236 2175
a935c052
VD		 2176 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2177 if (err)
2178 return err;
6630e236 2179
a935c052 2180 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2181 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2182 unsigned int mask, shift;
2183
a935c052 2184 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2185 next.trunk = true;
2186 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2187 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2188 } else {
2189 next.trunk = false;
2190 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2191 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2192 }
2193
a935c052 2194 next.portv_trunkid = (val & mask) >> shift;
1d194046 2195 }
cdf09697 2196
1d194046 2197 *entry = next;
cdf09697
DM		 2198 return 0;
2199}
2200
83dabd1f
VD		 2201static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2202 u16 fid, u16 vid, int port,
2203 struct switchdev_obj *obj,
2204 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2205{
2206 struct mv88e6xxx_atu_entry addr = {
2207 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2208 };
2209 int err;
2210
fad09c73 2211 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2212 if (err)
2213 return err;
2214
2215 do {
fad09c73 2216 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2217 if (err)
83dabd1f 2218 return err;
74b6ba0d
VD		 2219
2220 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2221 break;
2222
83dabd1f
VD		 2223 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2224 continue;
2225
2226 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2227 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2228
83dabd1f
VD		 2229 if (!is_unicast_ether_addr(addr.mac))
2230 continue;
2231
2232 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2233 fdb->vid = vid;
2234 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2235 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2236 fdb->ndm_state = NUD_NOARP;
2237 else
2238 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2239 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2240 struct switchdev_obj_port_mdb *mdb;
2241
2242 if (!is_multicast_ether_addr(addr.mac))
2243 continue;
2244
2245 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2246 mdb->vid = vid;
2247 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2248 } else {
2249 return -EOPNOTSUPP;
74b6ba0d 2250 }
83dabd1f
VD		 2251
2252 err = cb(obj);
2253 if (err)
2254 return err;
74b6ba0d
VD		 2255 } while (!is_broadcast_ether_addr(addr.mac));
2256
2257 return err;
2258}
2259
83dabd1f
VD		 2260static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2261 struct switchdev_obj *obj,
2262 int (*cb)(struct switchdev_obj *obj))
f33475bd 2263{
b4e47c0f 2264 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2265 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2266 };
2db9ce1f 2267 u16 fid;
f33475bd
VD		 2268 int err;
2269
2db9ce1f 2270 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2271 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2272 if (err)
83dabd1f 2273 return err;
2db9ce1f 2274
83dabd1f 2275 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2276 if (err)
83dabd1f 2277 return err;
2db9ce1f 2278
74b6ba0d 2279 /* Dump VLANs' Filtering Information Databases */
fad09c73 2280 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2281 if (err)
83dabd1f 2282 return err;
f33475bd
VD		 2283
2284 do {
fad09c73 2285 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2286 if (err)
83dabd1f 2287 return err;
f33475bd
VD		 2288
2289 if (!vlan.valid)
2290 break;
2291
83dabd1f
VD		 2292 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2293 obj, cb);
f33475bd 2294 if (err)
83dabd1f 2295 return err;
f33475bd
VD		 2296 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2297
83dabd1f
VD		 2298 return err;
2299}
2300
2301static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2302 struct switchdev_obj_port_fdb *fdb,
2303 int (*cb)(struct switchdev_obj *obj))
2304{
04bed143 2305 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2306 int err;
2307
2308 mutex_lock(&chip->reg_lock);
2309 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2310 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2311
2312 return err;
2313}
2314
f81ec90f
VD		 2315static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2316 struct net_device *bridge)
e79a8bcb 2317{
04bed143 2318 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2319 int i, err = 0;
466dfa07 2320
fad09c73 2321 mutex_lock(&chip->reg_lock);
466dfa07 2322
b7666efe 2323 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2324 chip->ports[port].bridge_dev = bridge;
b7666efe 2325
370b4ffb 2326 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2327 if (chip->ports[i].bridge_dev == bridge) {
2328 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2329 if (err)
2330 break;
2331 }
2332 }
2333
fad09c73 2334 mutex_unlock(&chip->reg_lock);
a6692754 2335
466dfa07 2336 return err;
e79a8bcb
VD		 2337}
2338
f81ec90f 2339static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2340{
04bed143 2341 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2342 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2343 int i;
466dfa07 2344
fad09c73 2345 mutex_lock(&chip->reg_lock);
466dfa07 2346
b7666efe 2347 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2348 chip->ports[port].bridge_dev = NULL;
b7666efe 2349
370b4ffb 2350 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2351 if (i == port || chip->ports[i].bridge_dev == bridge)
2352 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2353 netdev_warn(ds->ports[i].netdev,
2354 "failed to remap\n");
b7666efe 2355
fad09c73 2356 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2357}
2358
4ac4b5a6 2359static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2360{
4ac4b5a6 2361 int i, err;
552238b5 2362
4ac4b5a6 2363 /* Set all ports to the Disabled state */
370b4ffb 2364 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2365 err = mv88e6xxx_port_set_state(chip, i,
2366 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2367 if (err)
2368 return err;
552238b5
VD		 2369 }
2370
4ac4b5a6
VD		 2371 /* Wait for transmit queues to drain,
2372 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2373 */
552238b5
VD		 2374 usleep_range(2000, 4000);
2375
4ac4b5a6
VD		 2376 return 0;
2377}
2378
2379static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2380{
2381 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2382 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2383 struct gpio_desc *gpiod = chip->reset;
2384 unsigned long timeout;
2385 u16 reg;
2386 int err;
2387
2388 err = mv88e6xxx_disable_ports(chip);
2389 if (err)
2390 return err;
2391
552238b5
VD		 2392 /* If there is a gpio connected to the reset pin, toggle it */
2393 if (gpiod) {
2394 gpiod_set_value_cansleep(gpiod, 1);
2395 usleep_range(10000, 20000);
2396 gpiod_set_value_cansleep(gpiod, 0);
2397 usleep_range(10000, 20000);
2398 }
2399
2400 /* Reset the switch. Keep the PPU active if requested. The PPU
2401 * needs to be active to support indirect phy register access
2402 * through global registers 0x18 and 0x19.
2403 */
2404 if (ppu_active)
a935c052 2405 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
552238b5 2406 else
a935c052 2407 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
0e7b9925
AL		 2408 if (err)
2409 return err;
552238b5
VD		 2410
2411 /* Wait up to one second for reset to complete. */
2412 timeout = jiffies + 1 * HZ;
2413 while (time_before(jiffies, timeout)) {
a935c052
VD		 2414 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2415 if (err)
2416 return err;
552238b5 2417
a935c052 2418 if ((reg & is_reset) == is_reset)
552238b5
VD		 2419 break;
2420 usleep_range(1000, 2000);
2421 }
2422 if (time_after(jiffies, timeout))
0e7b9925 2423 err = -ETIMEDOUT;
552238b5 2424 else
0e7b9925 2425 err = 0;
552238b5 2426
0e7b9925 2427 return err;
552238b5
VD		 2428}
2429
09cb7dfd 2430static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2431{
09cb7dfd
VD		 2432 u16 val;
2433 int err;
13a7ebb3 2434
09cb7dfd
VD		 2435 /* Clear Power Down bit */
2436 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2437 if (err)
2438 return err;
13a7ebb3 2439
09cb7dfd
VD		 2440 if (val & BMCR_PDOWN) {
2441 val &= ~BMCR_PDOWN;
2442 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2443 }
2444
09cb7dfd 2445 return err;
13a7ebb3
PU		 2446}
2447
56995cbc
AL		 2448static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2449 int upstream_port)
2450{
2451 int err;
2452
2453 err = chip->info->ops->port_set_frame_mode(
2454 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2455 if (err)
2456 return err;
2457
2458 return chip->info->ops->port_set_egress_unknowns(
2459 chip, port, port == upstream_port);
2460}
2461
2462static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2463{
2464 int err;
2465
2466 switch (chip->info->tag_protocol) {
2467 case DSA_TAG_PROTO_EDSA:
2468 err = chip->info->ops->port_set_frame_mode(
2469 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2470 if (err)
2471 return err;
2472
2473 err = mv88e6xxx_port_set_egress_mode(
2474 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2475 if (err)
2476 return err;
2477
2478 if (chip->info->ops->port_set_ether_type)
2479 err = chip->info->ops->port_set_ether_type(
2480 chip, port, ETH_P_EDSA);
2481 break;
2482
2483 case DSA_TAG_PROTO_DSA:
2484 err = chip->info->ops->port_set_frame_mode(
2485 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2486 if (err)
2487 return err;
2488
2489 err = mv88e6xxx_port_set_egress_mode(
2490 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2491 break;
2492 default:
2493 err = -EINVAL;
2494 }
2495
2496 if (err)
2497 return err;
2498
2499 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2500}
2501
2502static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2503{
2504 int err;
2505
2506 err = chip->info->ops->port_set_frame_mode(
2507 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2508 if (err)
2509 return err;
2510
2511 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2512}
2513
fad09c73 2514static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2515{
fad09c73 2516 struct dsa_switch *ds = chip->ds;
0e7b9925 2517 int err;
54d792f2 2518 u16 reg;
d827e88a 2519
d78343d2
VD		 2520 /* MAC Forcing register: don't force link, speed, duplex or flow control
2521 * state to any particular values on physical ports, but force the CPU
2522 * port and all DSA ports to their maximum bandwidth and full duplex.
2523 */
2524 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2525 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2526 SPEED_MAX, DUPLEX_FULL,
2527 PHY_INTERFACE_MODE_NA);
2528 else
2529 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2530 SPEED_UNFORCED, DUPLEX_UNFORCED,
2531 PHY_INTERFACE_MODE_NA);
2532 if (err)
2533 return err;
54d792f2
AL		 2534
2535 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2536 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2537 * tunneling, determine priority by looking at 802.1p and IP
2538 * priority fields (IP prio has precedence), and set STP state
2539 * to Forwarding.
2540 *
2541 * If this is the CPU link, use DSA or EDSA tagging depending
2542 * on which tagging mode was configured.
2543 *
2544 * If this is a link to another switch, use DSA tagging mode.
2545 *
2546 * If this is the upstream port for this switch, enable
2547 * forwarding of unknown unicasts and multicasts.
2548 */
56995cbc 2549 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2550 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2551 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2552 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2553 if (err)
2554 return err;
6083ce71 2555
56995cbc
AL		 2556 if (dsa_is_cpu_port(ds, port)) {
2557 err = mv88e6xxx_setup_port_cpu(chip, port);
2558 } else if (dsa_is_dsa_port(ds, port)) {
2559 err = mv88e6xxx_setup_port_dsa(chip, port,
2560 dsa_upstream_port(ds));
2561 } else {
2562 err = mv88e6xxx_setup_port_normal(chip, port);
54d792f2 2563 }
56995cbc
AL		 2564 if (err)
2565 return err;
54d792f2 2566
13a7ebb3
PU		 2567 /* If this port is connected to a SerDes, make sure the SerDes is not
2568 * powered down.
2569 */
09cb7dfd 2570 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2571 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2572 if (err)
2573 return err;
2574 reg &= PORT_STATUS_CMODE_MASK;
2575 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2576 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2577 (reg == PORT_STATUS_CMODE_SGMII)) {
2578 err = mv88e6xxx_serdes_power_on(chip);
2579 if (err < 0)
2580 return err;
13a7ebb3
PU		 2581 }
2582 }
2583
8efdda4a 2584 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2585 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2586 * untagged frames on this port, do a destination address lookup on all
2587 * received packets as usual, disable ARP mirroring and don't send a
2588 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2589 */
2590 reg = 0;
fad09c73
VD		 2591 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2592 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2593 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2594 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2595 reg = PORT_CONTROL_2_MAP_DA;
2596
fad09c73 2597 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2598 /* Set the upstream port this port should use */
2599 reg |= dsa_upstream_port(ds);
2600 /* enable forwarding of unknown multicast addresses to
2601 * the upstream port
2602 */
2603 if (port == dsa_upstream_port(ds))
2604 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2605 }
2606
46fbe5e5 2607 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2608
54d792f2 2609 if (reg) {
0e7b9925
AL		 2610 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2611 if (err)
2612 return err;
54d792f2
AL		 2613 }
2614
5f436666
AL		 2615 if (chip->info->ops->port_jumbo_config) {
2616 err = chip->info->ops->port_jumbo_config(chip, port);
2617 if (err)
2618 return err;
2619 }
2620
54d792f2
AL		 2621 /* Port Association Vector: when learning source addresses
2622 * of packets, add the address to the address database using
2623 * a port bitmap that has only the bit for this port set and
2624 * the other bits clear.
2625 */
4c7ea3c0 2626 reg = 1 << port;
996ecb82
VD		 2627 /* Disable learning for CPU port */
2628 if (dsa_is_cpu_port(ds, port))
65fa4027 2629 reg = 0;
4c7ea3c0 2630
0e7b9925
AL		 2631 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2632 if (err)
2633 return err;
54d792f2
AL		 2634
2635 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2636 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2637 if (err)
2638 return err;
54d792f2 2639
b35d322a
AL		 2640 if (chip->info->ops->port_pause_config) {
2641 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2642 if (err)
2643 return err;
b35d322a 2644 }
54d792f2 2645
b35d322a
AL		 2646 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2647 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2648 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2649 /* Port ATU control: disable limiting the number of
2650 * address database entries that this port is allowed
2651 * to use.
2652 */
0e7b9925
AL		 2653 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2654 0x0000);
54d792f2
AL		 2655 /* Priority Override: disable DA, SA and VTU priority
2656 * override.
2657 */
0e7b9925
AL		 2658 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2659 0x0000);
2660 if (err)
2661 return err;
ef0a7318 2662 }
2bbb33be 2663
ef0a7318
AL		 2664 if (chip->info->ops->port_tag_remap) {
2665 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2666 if (err)
2667 return err;
54d792f2
AL		 2668 }
2669
ef70b111
AL		 2670 if (chip->info->ops->port_egress_rate_limiting) {
2671 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2672 if (err)
2673 return err;
54d792f2
AL		 2674 }
2675
366f0a0f
GR		 2676 /* Port Control 1: disable trunking, disable sending
2677 * learning messages to this port.
d827e88a 2678 */
0e7b9925
AL		 2679 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2680 if (err)
2681 return err;
d827e88a 2682
207afda1 2683 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2684 * database, and allow bidirectional communication between the
2685 * CPU and DSA port(s), and the other ports.
d827e88a 2686 */
b4e48c50 2687 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2688 if (err)
2689 return err;
2db9ce1f 2690
0e7b9925
AL		 2691 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2692 if (err)
2693 return err;
d827e88a
GR		 2694
2695 /* Default VLAN ID and priority: don't set a default VLAN
2696 * ID, and set the default packet priority to zero.
2697 */
0e7b9925 2698 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2699}
2700
aa0938c6 2701static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2702{
2703 int err;
2704
a935c052 2705 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2706 if (err)
2707 return err;
2708
a935c052 2709 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2710 if (err)
2711 return err;
2712
a935c052
VD		 2713 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2714 if (err)
2715 return err;
2716
2717 return 0;
3b4caa1b
VD		 2718}
2719
acddbd21
VD		 2720static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2721 unsigned int msecs)
2722{
2723 const unsigned int coeff = chip->info->age_time_coeff;
2724 const unsigned int min = 0x01 * coeff;
2725 const unsigned int max = 0xff * coeff;
2726 u8 age_time;
2727 u16 val;
2728 int err;
2729
2730 if (msecs < min || msecs > max)
2731 return -ERANGE;
2732
2733 /* Round to nearest multiple of coeff */
2734 age_time = (msecs + coeff / 2) / coeff;
2735
a935c052 2736 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2737 if (err)
2738 return err;
2739
2740 /* AgeTime is 11:4 bits */
2741 val &= ~0xff0;
2742 val |= age_time << 4;
2743
a935c052 2744 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2745}
2746
2cfcd964
VD		 2747static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2748 unsigned int ageing_time)
2749{
04bed143 2750 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2751 int err;
2752
2753 mutex_lock(&chip->reg_lock);
2754 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2755 mutex_unlock(&chip->reg_lock);
2756
2757 return err;
2758}
2759
9729934c 2760static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2761{
fad09c73 2762 struct dsa_switch *ds = chip->ds;
b0745e87 2763 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2764 u16 reg;
552238b5 2765 int err;
54d792f2 2766
119477bd
VD		 2767 /* Enable the PHY Polling Unit if present, don't discard any packets,
2768 * and mask all interrupt sources.
2769 */
dc30c35b
AL		 2770 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2771 if (err < 0)
2772 return err;
2773
2774 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
fad09c73
VD		 2775 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2776 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2777 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2778
a935c052 2779 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
119477bd
VD		 2780 if (err)
2781 return err;
2782
33641994
AL		 2783 if (chip->info->ops->g1_set_cpu_port) {
2784 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2785 if (err)
2786 return err;
2787 }
2788
2789 if (chip->info->ops->g1_set_egress_port) {
2790 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2791 if (err)
2792 return err;
2793 }
b0745e87 2794
50484ff4 2795 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2796 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2797 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2798 (ds->index & 0x1f));
50484ff4
VD		 2799 if (err)
2800 return err;
2801
acddbd21
VD		 2802 /* Clear all the VTU and STU entries */
2803 err = _mv88e6xxx_vtu_stu_flush(chip);
2804 if (err < 0)
2805 return err;
2806
54d792f2
AL		 2807 /* Set the default address aging time to 5 minutes, and
2808 * enable address learn messages to be sent to all message
2809 * ports.
2810 */
a935c052
VD		 2811 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2812 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2813 if (err)
08a01261 2814 return err;
54d792f2 2815
acddbd21
VD		 2816 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2817 if (err)
9729934c
VD		 2818 return err;
2819
2820 /* Clear all ATU entries */
2821 err = _mv88e6xxx_atu_flush(chip, 0, true);
2822 if (err)
2823 return err;
2824
54d792f2 2825 /* Configure the IP ToS mapping registers. */
a935c052 2826 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2827 if (err)
08a01261 2828 return err;
a935c052 2829 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2830 if (err)
08a01261 2831 return err;
a935c052 2832 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2833 if (err)
08a01261 2834 return err;
a935c052 2835 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2836 if (err)
08a01261 2837 return err;
a935c052 2838 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2839 if (err)
08a01261 2840 return err;
a935c052 2841 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2842 if (err)
08a01261 2843 return err;
a935c052 2844 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2845 if (err)
08a01261 2846 return err;
a935c052 2847 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2848 if (err)
08a01261 2849 return err;
54d792f2
AL		 2850
2851 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2852 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2853 if (err)
08a01261 2854 return err;
54d792f2 2855
de227387
AL		 2856 /* Initialize the statistics unit */
2857 err = mv88e6xxx_stats_set_histogram(chip);
2858 if (err)
2859 return err;
2860
9729934c 2861 /* Clear the statistics counters for all ports */
a935c052
VD		 2862 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2863 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2864 if (err)
2865 return err;
2866
2867 /* Wait for the flush to complete. */
7f9ef3af 2868 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2869 if (err)
2870 return err;
2871
2872 return 0;
2873}
2874
f81ec90f 2875static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2876{
04bed143 2877 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2878 int err;
a1a6a4d1
VD		 2879 int i;
2880
fad09c73
VD		 2881 chip->ds = ds;
2882 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2883
fad09c73 2884 mutex_lock(&chip->reg_lock);
08a01261 2885
9729934c 2886 /* Setup Switch Port Registers */
370b4ffb 2887 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2888 err = mv88e6xxx_setup_port(chip, i);
2889 if (err)
2890 goto unlock;
2891 }
2892
2893 /* Setup Switch Global 1 Registers */
2894 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2895 if (err)
2896 goto unlock;
2897
9729934c
VD		 2898 /* Setup Switch Global 2 Registers */
2899 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2900 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2901 if (err)
2902 goto unlock;
2903 }
08a01261 2904
6e55f698
AL		 2905 /* Some generations have the configuration of sending reserved
2906 * management frames to the CPU in global2, others in
2907 * global1. Hence it does not fit the two setup functions
2908 * above.
2909 */
2910 if (chip->info->ops->mgmt_rsvd2cpu) {
2911 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2912 if (err)
2913 goto unlock;
2914 }
2915
6b17e864 2916unlock:
fad09c73 2917 mutex_unlock(&chip->reg_lock);
db687a56 2918
48ace4ef 2919 return err;
54d792f2
AL		 2920}
2921
3b4caa1b
VD		 2922static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2923{
04bed143 2924 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2925 int err;
2926
b073d4e2
VD		 2927 if (!chip->info->ops->set_switch_mac)
2928 return -EOPNOTSUPP;
3b4caa1b 2929
b073d4e2
VD		 2930 mutex_lock(&chip->reg_lock);
2931 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2932 mutex_unlock(&chip->reg_lock);
2933
2934 return err;
2935}
2936
e57e5e77 2937static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2938{
fad09c73 2939 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2940 u16 val;
2941 int err;
fd3a0ee4 2942
370b4ffb 2943 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2944 return 0xffff;
fd3a0ee4 2945
fad09c73 2946 mutex_lock(&chip->reg_lock);
e57e5e77 2947 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2948 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2949
2950 return err ? err : val;
fd3a0ee4
AL		 2951}
2952
e57e5e77 2953static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2954{
fad09c73 2955 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2956 int err;
fd3a0ee4 2957
370b4ffb 2958 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2959 return 0xffff;
fd3a0ee4 2960
fad09c73 2961 mutex_lock(&chip->reg_lock);
e57e5e77 2962 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2963 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2964
2965 return err;
fd3a0ee4
AL		 2966}
2967
fad09c73 2968static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2969 struct device_node *np)
2970{
2971 static int index;
2972 struct mii_bus *bus;
2973 int err;
2974
b516d453 2975 if (np)
fad09c73 2976 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2977
fad09c73 2978 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2979 if (!bus)
2980 return -ENOMEM;
2981
fad09c73 2982 bus->priv = (void *)chip;
b516d453
AL		 2983 if (np) {
2984 bus->name = np->full_name;
2985 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2986 } else {
2987 bus->name = "mv88e6xxx SMI";
2988 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2989 }
2990
2991 bus->read = mv88e6xxx_mdio_read;
2992 bus->write = mv88e6xxx_mdio_write;
fad09c73 2993 bus->parent = chip->dev;
b516d453 2994
fad09c73
VD		 2995 if (chip->mdio_np)
2996 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2997 else
2998 err = mdiobus_register(bus);
2999 if (err) {
fad09c73 3000 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3001 goto out;
3002 }
fad09c73 3003 chip->mdio_bus = bus;
b516d453
AL		 3004
3005 return 0;
3006
3007out:
fad09c73
VD		 3008 if (chip->mdio_np)
3009 of_node_put(chip->mdio_np);
b516d453
AL		 3010
3011 return err;
3012}
3013
fad09c73 3014static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3015
3016{
fad09c73 3017 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3018
3019 mdiobus_unregister(bus);
3020
fad09c73
VD		 3021 if (chip->mdio_np)
3022 of_node_put(chip->mdio_np);
b516d453
AL		 3023}
3024
c22995c5
GR		 3025#ifdef CONFIG_NET_DSA_HWMON
3026
3027static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3028{
04bed143 3029 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 3030 u16 val;
c22995c5 3031 int ret;
c22995c5
GR		 3032
3033 *temp = 0;
3034
fad09c73 3035 mutex_lock(&chip->reg_lock);
c22995c5 3036
9c93829c 3037 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3038 if (ret < 0)
3039 goto error;
3040
3041 /* Enable temperature sensor */
9c93829c 3042 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3043 if (ret < 0)
3044 goto error;
3045
9c93829c 3046 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3047 if (ret < 0)
3048 goto error;
3049
3050 /* Wait for temperature to stabilize */
3051 usleep_range(10000, 12000);
3052
9c93829c
VD		 3053 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3054 if (ret < 0)
c22995c5 3055 goto error;
c22995c5
GR		 3056
3057 /* Disable temperature sensor */
9c93829c 3058 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3059 if (ret < 0)
3060 goto error;
3061
3062 *temp = ((val & 0x1f) - 5) * 5;
3063
3064error:
9c93829c 3065 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3066 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3067 return ret;
3068}
3069
3070static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3071{
04bed143 3072 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3073 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3074 u16 val;
c22995c5
GR		 3075 int ret;
3076
3077 *temp = 0;
3078
9c93829c
VD		 3079 mutex_lock(&chip->reg_lock);
3080 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3081 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3082 if (ret < 0)
3083 return ret;
3084
9c93829c 3085 *temp = (val & 0xff) - 25;
c22995c5
GR		 3086
3087 return 0;
3088}
3089
f81ec90f 3090static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3091{
04bed143 3092 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3093
fad09c73 3094 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3095 return -EOPNOTSUPP;
3096
fad09c73 3097 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3098 return mv88e63xx_get_temp(ds, temp);
3099
3100 return mv88e61xx_get_temp(ds, temp);
3101}
3102
f81ec90f 3103static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3104{
04bed143 3105 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3106 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3107 u16 val;
c22995c5
GR		 3108 int ret;
3109
fad09c73 3110 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3111 return -EOPNOTSUPP;
3112
3113 *temp = 0;
3114
9c93829c
VD		 3115 mutex_lock(&chip->reg_lock);
3116 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3117 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3118 if (ret < 0)
3119 return ret;
3120
9c93829c 3121 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3122
3123 return 0;
3124}
3125
f81ec90f 3126static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3127{
04bed143 3128 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3129 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3130 u16 val;
3131 int err;
c22995c5 3132
fad09c73 3133 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3134 return -EOPNOTSUPP;
3135
9c93829c
VD		 3136 mutex_lock(&chip->reg_lock);
3137 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3138 if (err)
3139 goto unlock;
c22995c5 3140 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3141 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3142 (val & 0xe0ff) | (temp << 8));
3143unlock:
3144 mutex_unlock(&chip->reg_lock);
3145
3146 return err;
c22995c5
GR		 3147}
3148
f81ec90f 3149static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3150{
04bed143 3151 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3152 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3153 u16 val;
c22995c5
GR		 3154 int ret;
3155
fad09c73 3156 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3157 return -EOPNOTSUPP;
3158
3159 *alarm = false;
3160
9c93829c
VD		 3161 mutex_lock(&chip->reg_lock);
3162 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3163 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3164 if (ret < 0)
3165 return ret;
3166
9c93829c 3167 *alarm = !!(val & 0x40);
c22995c5
GR		 3168
3169 return 0;
3170}
3171#endif /* CONFIG_NET_DSA_HWMON */
3172
855b1932
VD		 3173static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3174{
04bed143 3175 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3176
3177 return chip->eeprom_len;
3178}
3179
855b1932
VD		 3180static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3181 struct ethtool_eeprom *eeprom, u8 *data)
3182{
04bed143 3183 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3184 int err;
3185
ee4dc2e7
VD		 3186 if (!chip->info->ops->get_eeprom)
3187 return -EOPNOTSUPP;
855b1932 3188
ee4dc2e7
VD		 3189 mutex_lock(&chip->reg_lock);
3190 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3191 mutex_unlock(&chip->reg_lock);
3192
3193 if (err)
3194 return err;
3195
3196 eeprom->magic = 0xc3ec4951;
3197
3198 return 0;
3199}
3200
855b1932
VD		 3201static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3202 struct ethtool_eeprom *eeprom, u8 *data)
3203{
04bed143 3204 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3205 int err;
3206
ee4dc2e7
VD		 3207 if (!chip->info->ops->set_eeprom)
3208 return -EOPNOTSUPP;
3209
855b1932
VD		 3210 if (eeprom->magic != 0xc3ec4951)
3211 return -EINVAL;
3212
3213 mutex_lock(&chip->reg_lock);
ee4dc2e7 3214 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3215 mutex_unlock(&chip->reg_lock);
3216
3217 return err;
3218}
3219
b3469dd8 3220static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3221 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3222 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3223 .phy_read = mv88e6xxx_phy_ppu_read,
3224 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3225 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3226 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3227 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3228 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3229 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3230 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3231 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3232 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3233 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3234 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3235 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3236 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3237 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3238 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3239 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3240 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3241};
3242
3243static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3244 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3245 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3246 .phy_read = mv88e6xxx_phy_ppu_read,
3247 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3248 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3249 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3250 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3251 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3252 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3253 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3254 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3255 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3256 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 3257 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3258};
3259
7d381a02 3260static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3261 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 3262 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3263 .phy_read = mv88e6xxx_g2_smi_phy_read,
3264 .phy_write = mv88e6xxx_g2_smi_phy_write,
3265 .port_set_link = mv88e6xxx_port_set_link,
3266 .port_set_duplex = mv88e6xxx_port_set_duplex,
3267 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3268 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3269 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3270 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3271 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3272 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3273 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 3274 .port_pause_config = mv88e6097_port_pause_config,
7d381a02
SE		 3275 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3276 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3277 .stats_get_strings = mv88e6095_stats_get_strings,
3278 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3279 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3280 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3281 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
7d381a02
SE		 3282};
3283
b3469dd8 3284static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3285 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3286 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3287 .phy_read = mv88e6xxx_read,
3288 .phy_write = mv88e6xxx_write,
08ef7f10 3289 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3290 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3291 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3292 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3293 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3294 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3295 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3296 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3297 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3298 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3299 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3300 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3301};
3302
3303static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3304 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3305 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3306 .phy_read = mv88e6xxx_phy_ppu_read,
3307 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3308 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3309 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3310 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3311 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3312 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3313 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3314 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3315 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3316 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3317 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3318 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3319 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3320 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3321 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3322 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3323 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3324 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3325};
3326
3327static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3328 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3329 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3330 .phy_read = mv88e6xxx_read,
3331 .phy_write = mv88e6xxx_write,
08ef7f10 3332 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3333 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3334 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3335 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3336 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3337 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3338 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3339 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3340 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3341 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3342 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3343 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3344 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3345 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3346 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3347 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3348 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3349};
3350
3351static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3352 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3353 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3354 .phy_read = mv88e6xxx_read,
3355 .phy_write = mv88e6xxx_write,
08ef7f10 3356 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3357 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3358 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3359 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3360 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3361 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3362 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3363 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3364 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3365 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3366};
3367
3368static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3369 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3370 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3371 .phy_read = mv88e6xxx_g2_smi_phy_read,
3372 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3373 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3374 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3375 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3376 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3377 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3378 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3379 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3380 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3381 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3383 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3384 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3385 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3386 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3387 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3388 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3389 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3390 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3391};
3392
3393static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3394 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3395 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3396 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3397 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3398 .phy_read = mv88e6xxx_g2_smi_phy_read,
3399 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3400 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3401 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3402 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3403 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3404 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3405 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3406 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3407 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3408 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3409 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3410 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3411 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3412 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3413 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3414 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3415 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3416 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3417 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3418};
3419
3420static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3421 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3423 .phy_read = mv88e6xxx_g2_smi_phy_read,
3424 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3425 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3426 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3427 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3428 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3429 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3430 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3431 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3432 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3433 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3434 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3435 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3436 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3437 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3438 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3439 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3440 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3441 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3442 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3443};
3444
3445static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3446 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3447 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3448 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3449 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3450 .phy_read = mv88e6xxx_g2_smi_phy_read,
3451 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3452 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3453 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3454 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3455 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3456 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3457 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3458 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3459 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3460 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3461 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3462 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3463 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3464 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3465 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3466 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3467 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3468 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3469 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3470};
3471
3472static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3473 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3474 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3475 .phy_read = mv88e6xxx_phy_ppu_read,
3476 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3477 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3478 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3479 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3480 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3481 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
ef70b111 3482 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a605a0fe 3483 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3484 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3485 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3486 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3487 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3488 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3489 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3490};
3491
1a3b39ec 3492static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3493 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3494 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3495 .phy_read = mv88e6xxx_g2_smi_phy_read,
3496 .phy_write = mv88e6xxx_g2_smi_phy_write,
3497 .port_set_link = mv88e6xxx_port_set_link,
3498 .port_set_duplex = mv88e6xxx_port_set_duplex,
3499 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3500 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3501 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3502 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3503 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3504 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3505 .port_pause_config = mv88e6390_port_pause_config,
79523473 3506 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3507 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3508 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3509 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3510 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3511 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3512 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3513 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
1a3b39ec
AL		 3514};
3515
3516static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3517 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3518 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3519 .phy_read = mv88e6xxx_g2_smi_phy_read,
3520 .phy_write = mv88e6xxx_g2_smi_phy_write,
3521 .port_set_link = mv88e6xxx_port_set_link,
3522 .port_set_duplex = mv88e6xxx_port_set_duplex,
3523 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3524 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3525 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3526 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3527 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3528 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3529 .port_pause_config = mv88e6390_port_pause_config,
79523473 3530 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3531 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3532 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3533 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3534 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3535 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3536 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3537 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
1a3b39ec
AL		 3538};
3539
3540static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3541 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3542 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3543 .phy_read = mv88e6xxx_g2_smi_phy_read,
3544 .phy_write = mv88e6xxx_g2_smi_phy_write,
3545 .port_set_link = mv88e6xxx_port_set_link,
3546 .port_set_duplex = mv88e6xxx_port_set_duplex,
3547 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3548 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3549 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3550 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3551 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3552 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3553 .port_pause_config = mv88e6390_port_pause_config,
79523473 3554 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3555 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3556 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3557 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3558 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3559 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3560 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3561 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
1a3b39ec
AL		 3562};
3563
b3469dd8 3564static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3565 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3566 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3567 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3568 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3569 .phy_read = mv88e6xxx_g2_smi_phy_read,
3570 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3571 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3572 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3573 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3574 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3575 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3576 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3577 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3578 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3579 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3580 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3581 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3582 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3583 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3584 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3585 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3586 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3587 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3588 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3589};
3590
1a3b39ec 3591static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3592 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3593 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3594 .phy_read = mv88e6xxx_g2_smi_phy_read,
3595 .phy_write = mv88e6xxx_g2_smi_phy_write,
3596 .port_set_link = mv88e6xxx_port_set_link,
3597 .port_set_duplex = mv88e6xxx_port_set_duplex,
3598 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3599 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3600 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3601 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3602 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3603 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3604 .port_pause_config = mv88e6390_port_pause_config,
79523473 3605 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3606 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3607 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3608 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3609 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3610 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3611 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3612 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
1a3b39ec
AL		 3613};
3614
b3469dd8 3615static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3616 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3617 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3618 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3619 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3620 .phy_read = mv88e6xxx_g2_smi_phy_read,
3621 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3622 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3623 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3624 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3625 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3626 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3627 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3628 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3629 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3630 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3631 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3632 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3633 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3634 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3635 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3636 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3637 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3638 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3639};
3640
3641static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3642 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3643 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3644 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3645 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3646 .phy_read = mv88e6xxx_g2_smi_phy_read,
3647 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3648 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3649 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3650 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3651 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3652 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3653 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3654 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3655 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3656 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3657 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3658 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3659 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3660 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3661 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3662 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3663 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
b3469dd8
VD		 3664};
3665
3666static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3667 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3668 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3669 .phy_read = mv88e6xxx_g2_smi_phy_read,
3670 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3671 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3672 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3673 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3674 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3675 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3676 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3677 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3678 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3679 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3680 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3681 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3682 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3683 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3684 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3685 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3686 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3687 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3688 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3689};
3690
3691static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3692 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3693 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3694 .phy_read = mv88e6xxx_g2_smi_phy_read,
3695 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3696 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3697 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3698 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3699 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3700 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3701 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3702 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3703 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3704 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3705 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3706 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3707 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3708 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3709 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3710 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3711 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3712 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3713 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3714};
3715
3716static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3717 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3718 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3719 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3720 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3721 .phy_read = mv88e6xxx_g2_smi_phy_read,
3722 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3723 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3724 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3725 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3726 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3727 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3728 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3729 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3730 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3731 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3732 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3733 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3734 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3735 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3736 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3737 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3738 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3739 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3740 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
b3469dd8
VD		 3741};
3742
1a3b39ec 3743static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3744 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3745 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3746 .phy_read = mv88e6xxx_g2_smi_phy_read,
3747 .phy_write = mv88e6xxx_g2_smi_phy_write,
3748 .port_set_link = mv88e6xxx_port_set_link,
3749 .port_set_duplex = mv88e6xxx_port_set_duplex,
3750 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3751 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3752 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3753 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3754 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3755 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3756 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3757 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3758 .port_pause_config = mv88e6390_port_pause_config,
79523473 3759 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3760 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3761 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3762 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3763 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3764 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3765 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3766 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
1a3b39ec
AL		 3767};
3768
3769static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3770 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3771 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3772 .phy_read = mv88e6xxx_g2_smi_phy_read,
3773 .phy_write = mv88e6xxx_g2_smi_phy_write,
3774 .port_set_link = mv88e6xxx_port_set_link,
3775 .port_set_duplex = mv88e6xxx_port_set_duplex,
3776 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3777 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3778 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3779 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3780 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3781 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3782 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3783 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3784 .port_pause_config = mv88e6390_port_pause_config,
79523473 3785 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3786 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3787 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3788 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3789 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3790 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3791 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3792 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
1a3b39ec
AL		 3793};
3794
3795static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3796 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3797 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3798 .phy_read = mv88e6xxx_g2_smi_phy_read,
3799 .phy_write = mv88e6xxx_g2_smi_phy_write,
3800 .port_set_link = mv88e6xxx_port_set_link,
3801 .port_set_duplex = mv88e6xxx_port_set_duplex,
3802 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3803 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3804 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3805 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3806 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3807 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3808 .port_pause_config = mv88e6390_port_pause_config,
79523473 3809 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3810 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3811 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3812 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3813 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3814 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3815 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
6e55f698 3816 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
1a3b39ec
AL		 3817};
3818
56995cbc
AL		 3819static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3820 const struct mv88e6xxx_ops *ops)
3821{
3822 if (!ops->port_set_frame_mode) {
3823 dev_err(chip->dev, "Missing port_set_frame_mode");
3824 return -EINVAL;
3825 }
3826
3827 if (!ops->port_set_egress_unknowns) {
3828 dev_err(chip->dev, "Missing port_set_egress_mode");
3829 return -EINVAL;
3830 }
3831
3832 return 0;
3833}
3834
f81ec90f
VD		 3835static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3836 [MV88E6085] = {
3837 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3838 .family = MV88E6XXX_FAMILY_6097,
3839 .name = "Marvell 88E6085",
3840 .num_databases = 4096,
3841 .num_ports = 10,
9dddd478 3842 .port_base_addr = 0x10,
a935c052 3843 .global1_addr = 0x1b,
acddbd21 3844 .age_time_coeff = 15000,
dc30c35b 3845 .g1_irqs = 8,
443d5a1b 3846 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3847 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3848 .ops = &mv88e6085_ops,
f81ec90f
VD		 3849 },
3850
3851 [MV88E6095] = {
3852 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3853 .family = MV88E6XXX_FAMILY_6095,
3854 .name = "Marvell 88E6095/88E6095F",
3855 .num_databases = 256,
3856 .num_ports = 11,
9dddd478 3857 .port_base_addr = 0x10,
a935c052 3858 .global1_addr = 0x1b,
acddbd21 3859 .age_time_coeff = 15000,
dc30c35b 3860 .g1_irqs = 8,
443d5a1b 3861 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3862 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3863 .ops = &mv88e6095_ops,
f81ec90f
VD		 3864 },
3865
7d381a02
SE		 3866 [MV88E6097] = {
3867 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3868 .family = MV88E6XXX_FAMILY_6097,
3869 .name = "Marvell 88E6097/88E6097F",
3870 .num_databases = 4096,
3871 .num_ports = 11,
3872 .port_base_addr = 0x10,
3873 .global1_addr = 0x1b,
3874 .age_time_coeff = 15000,
c534178b 3875 .g1_irqs = 8,
2bfcfcd3 3876 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3877 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3878 .ops = &mv88e6097_ops,
3879 },
3880
f81ec90f
VD		 3881 [MV88E6123] = {
3882 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3883 .family = MV88E6XXX_FAMILY_6165,
3884 .name = "Marvell 88E6123",
3885 .num_databases = 4096,
3886 .num_ports = 3,
9dddd478 3887 .port_base_addr = 0x10,
a935c052 3888 .global1_addr = 0x1b,
acddbd21 3889 .age_time_coeff = 15000,
dc30c35b 3890 .g1_irqs = 9,
443d5a1b 3891 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3892 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3893 .ops = &mv88e6123_ops,
f81ec90f
VD		 3894 },
3895
3896 [MV88E6131] = {
3897 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3898 .family = MV88E6XXX_FAMILY_6185,
3899 .name = "Marvell 88E6131",
3900 .num_databases = 256,
3901 .num_ports = 8,
9dddd478 3902 .port_base_addr = 0x10,
a935c052 3903 .global1_addr = 0x1b,
acddbd21 3904 .age_time_coeff = 15000,
dc30c35b 3905 .g1_irqs = 9,
443d5a1b 3906 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3907 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3908 .ops = &mv88e6131_ops,
f81ec90f
VD		 3909 },
3910
3911 [MV88E6161] = {
3912 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3913 .family = MV88E6XXX_FAMILY_6165,
3914 .name = "Marvell 88E6161",
3915 .num_databases = 4096,
3916 .num_ports = 6,
9dddd478 3917 .port_base_addr = 0x10,
a935c052 3918 .global1_addr = 0x1b,
acddbd21 3919 .age_time_coeff = 15000,
dc30c35b 3920 .g1_irqs = 9,
443d5a1b 3921 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3922 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3923 .ops = &mv88e6161_ops,
f81ec90f
VD		 3924 },
3925
3926 [MV88E6165] = {
3927 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3928 .family = MV88E6XXX_FAMILY_6165,
3929 .name = "Marvell 88E6165",
3930 .num_databases = 4096,
3931 .num_ports = 6,
9dddd478 3932 .port_base_addr = 0x10,
a935c052 3933 .global1_addr = 0x1b,
acddbd21 3934 .age_time_coeff = 15000,
dc30c35b 3935 .g1_irqs = 9,
443d5a1b 3936 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3937 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3938 .ops = &mv88e6165_ops,
f81ec90f
VD		 3939 },
3940
3941 [MV88E6171] = {
3942 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3943 .family = MV88E6XXX_FAMILY_6351,
3944 .name = "Marvell 88E6171",
3945 .num_databases = 4096,
3946 .num_ports = 7,
9dddd478 3947 .port_base_addr = 0x10,
a935c052 3948 .global1_addr = 0x1b,
acddbd21 3949 .age_time_coeff = 15000,
dc30c35b 3950 .g1_irqs = 9,
443d5a1b 3951 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3952 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3953 .ops = &mv88e6171_ops,
f81ec90f
VD		 3954 },
3955
3956 [MV88E6172] = {
3957 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3958 .family = MV88E6XXX_FAMILY_6352,
3959 .name = "Marvell 88E6172",
3960 .num_databases = 4096,
3961 .num_ports = 7,
9dddd478 3962 .port_base_addr = 0x10,
a935c052 3963 .global1_addr = 0x1b,
acddbd21 3964 .age_time_coeff = 15000,
dc30c35b 3965 .g1_irqs = 9,
443d5a1b 3966 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3967 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3968 .ops = &mv88e6172_ops,
f81ec90f
VD		 3969 },
3970
3971 [MV88E6175] = {
3972 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3973 .family = MV88E6XXX_FAMILY_6351,
3974 .name = "Marvell 88E6175",
3975 .num_databases = 4096,
3976 .num_ports = 7,
9dddd478 3977 .port_base_addr = 0x10,
a935c052 3978 .global1_addr = 0x1b,
acddbd21 3979 .age_time_coeff = 15000,
dc30c35b 3980 .g1_irqs = 9,
443d5a1b 3981 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3982 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3983 .ops = &mv88e6175_ops,
f81ec90f
VD		 3984 },
3985
3986 [MV88E6176] = {
3987 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3988 .family = MV88E6XXX_FAMILY_6352,
3989 .name = "Marvell 88E6176",
3990 .num_databases = 4096,
3991 .num_ports = 7,
9dddd478 3992 .port_base_addr = 0x10,
a935c052 3993 .global1_addr = 0x1b,
acddbd21 3994 .age_time_coeff = 15000,
dc30c35b 3995 .g1_irqs = 9,
443d5a1b 3996 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3997 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3998 .ops = &mv88e6176_ops,
f81ec90f
VD		 3999 },
4000
4001 [MV88E6185] = {
4002 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
4003 .family = MV88E6XXX_FAMILY_6185,
4004 .name = "Marvell 88E6185",
4005 .num_databases = 256,
4006 .num_ports = 10,
9dddd478 4007 .port_base_addr = 0x10,
a935c052 4008 .global1_addr = 0x1b,
acddbd21 4009 .age_time_coeff = 15000,
dc30c35b 4010 .g1_irqs = 8,
443d5a1b 4011 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4012 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 4013 .ops = &mv88e6185_ops,
f81ec90f
VD		 4014 },
4015
1a3b39ec
AL		 4016 [MV88E6190] = {
4017 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
4018 .family = MV88E6XXX_FAMILY_6390,
4019 .name = "Marvell 88E6190",
4020 .num_databases = 4096,
4021 .num_ports = 11, /* 10 + Z80 */
4022 .port_base_addr = 0x0,
4023 .global1_addr = 0x1b,
443d5a1b 4024 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4025 .age_time_coeff = 15000,
4026 .g1_irqs = 9,
4027 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4028 .ops = &mv88e6190_ops,
4029 },
4030
4031 [MV88E6190X] = {
4032 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
4033 .family = MV88E6XXX_FAMILY_6390,
4034 .name = "Marvell 88E6190X",
4035 .num_databases = 4096,
4036 .num_ports = 11, /* 10 + Z80 */
4037 .port_base_addr = 0x0,
4038 .global1_addr = 0x1b,
4039 .age_time_coeff = 15000,
4040 .g1_irqs = 9,
443d5a1b 4041 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4042 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4043 .ops = &mv88e6190x_ops,
4044 },
4045
4046 [MV88E6191] = {
4047 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
4048 .family = MV88E6XXX_FAMILY_6390,
4049 .name = "Marvell 88E6191",
4050 .num_databases = 4096,
4051 .num_ports = 11, /* 10 + Z80 */
4052 .port_base_addr = 0x0,
4053 .global1_addr = 0x1b,
4054 .age_time_coeff = 15000,
443d5a1b
AL		 4055 .g1_irqs = 9,
4056 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4057 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4058 .ops = &mv88e6391_ops,
4059 },
4060
f81ec90f
VD		 4061 [MV88E6240] = {
4062 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
4063 .family = MV88E6XXX_FAMILY_6352,
4064 .name = "Marvell 88E6240",
4065 .num_databases = 4096,
4066 .num_ports = 7,
9dddd478 4067 .port_base_addr = 0x10,
a935c052 4068 .global1_addr = 0x1b,
acddbd21 4069 .age_time_coeff = 15000,
dc30c35b 4070 .g1_irqs = 9,
443d5a1b 4071 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4072 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4073 .ops = &mv88e6240_ops,
f81ec90f
VD		 4074 },
4075
1a3b39ec
AL		 4076 [MV88E6290] = {
4077 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4078 .family = MV88E6XXX_FAMILY_6390,
4079 .name = "Marvell 88E6290",
4080 .num_databases = 4096,
4081 .num_ports = 11, /* 10 + Z80 */
4082 .port_base_addr = 0x0,
4083 .global1_addr = 0x1b,
4084 .age_time_coeff = 15000,
4085 .g1_irqs = 9,
443d5a1b 4086 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4087 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4088 .ops = &mv88e6290_ops,
4089 },
4090
f81ec90f
VD		 4091 [MV88E6320] = {
4092 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4093 .family = MV88E6XXX_FAMILY_6320,
4094 .name = "Marvell 88E6320",
4095 .num_databases = 4096,
4096 .num_ports = 7,
9dddd478 4097 .port_base_addr = 0x10,
a935c052 4098 .global1_addr = 0x1b,
acddbd21 4099 .age_time_coeff = 15000,
dc30c35b 4100 .g1_irqs = 8,
443d5a1b 4101 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4102 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4103 .ops = &mv88e6320_ops,
f81ec90f
VD		 4104 },
4105
4106 [MV88E6321] = {
4107 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4108 .family = MV88E6XXX_FAMILY_6320,
4109 .name = "Marvell 88E6321",
4110 .num_databases = 4096,
4111 .num_ports = 7,
9dddd478 4112 .port_base_addr = 0x10,
a935c052 4113 .global1_addr = 0x1b,
acddbd21 4114 .age_time_coeff = 15000,
dc30c35b 4115 .g1_irqs = 8,
443d5a1b 4116 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4117 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4118 .ops = &mv88e6321_ops,
f81ec90f
VD		 4119 },
4120
4121 [MV88E6350] = {
4122 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4123 .family = MV88E6XXX_FAMILY_6351,
4124 .name = "Marvell 88E6350",
4125 .num_databases = 4096,
4126 .num_ports = 7,
9dddd478 4127 .port_base_addr = 0x10,
a935c052 4128 .global1_addr = 0x1b,
acddbd21 4129 .age_time_coeff = 15000,
dc30c35b 4130 .g1_irqs = 9,
443d5a1b 4131 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4132 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4133 .ops = &mv88e6350_ops,
f81ec90f
VD		 4134 },
4135
4136 [MV88E6351] = {
4137 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4138 .family = MV88E6XXX_FAMILY_6351,
4139 .name = "Marvell 88E6351",
4140 .num_databases = 4096,
4141 .num_ports = 7,
9dddd478 4142 .port_base_addr = 0x10,
a935c052 4143 .global1_addr = 0x1b,
acddbd21 4144 .age_time_coeff = 15000,
dc30c35b 4145 .g1_irqs = 9,
443d5a1b 4146 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4147 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4148 .ops = &mv88e6351_ops,
f81ec90f
VD		 4149 },
4150
4151 [MV88E6352] = {
4152 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4153 .family = MV88E6XXX_FAMILY_6352,
4154 .name = "Marvell 88E6352",
4155 .num_databases = 4096,
4156 .num_ports = 7,
9dddd478 4157 .port_base_addr = 0x10,
a935c052 4158 .global1_addr = 0x1b,
acddbd21 4159 .age_time_coeff = 15000,
dc30c35b 4160 .g1_irqs = 9,
443d5a1b 4161 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4162 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4163 .ops = &mv88e6352_ops,
f81ec90f 4164 },
1a3b39ec
AL		 4165 [MV88E6390] = {
4166 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4167 .family = MV88E6XXX_FAMILY_6390,
4168 .name = "Marvell 88E6390",
4169 .num_databases = 4096,
4170 .num_ports = 11, /* 10 + Z80 */
4171 .port_base_addr = 0x0,
4172 .global1_addr = 0x1b,
4173 .age_time_coeff = 15000,
4174 .g1_irqs = 9,
443d5a1b 4175 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4176 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4177 .ops = &mv88e6390_ops,
4178 },
4179 [MV88E6390X] = {
4180 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4181 .family = MV88E6XXX_FAMILY_6390,
4182 .name = "Marvell 88E6390X",
4183 .num_databases = 4096,
4184 .num_ports = 11, /* 10 + Z80 */
4185 .port_base_addr = 0x0,
4186 .global1_addr = 0x1b,
4187 .age_time_coeff = 15000,
4188 .g1_irqs = 9,
443d5a1b 4189 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4190 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4191 .ops = &mv88e6390x_ops,
4192 },
f81ec90f
VD		 4193};
4194
5f7c0367 4195static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4196{
a439c061 4197 int i;
b9b37713 4198
5f7c0367
VD		 4199 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4200 if (mv88e6xxx_table[i].prod_num == prod_num)
4201 return &mv88e6xxx_table[i];
b9b37713 4202
b9b37713
VD		 4203 return NULL;
4204}
4205
fad09c73 4206static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4207{
4208 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4209 unsigned int prod_num, rev;
4210 u16 id;
4211 int err;
bc46a3d5 4212
8f6345b2
VD		 4213 mutex_lock(&chip->reg_lock);
4214 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4215 mutex_unlock(&chip->reg_lock);
4216 if (err)
4217 return err;
bc46a3d5
VD		 4218
4219 prod_num = (id & 0xfff0) >> 4;
4220 rev = id & 0x000f;
4221
4222 info = mv88e6xxx_lookup_info(prod_num);
4223 if (!info)
4224 return -ENODEV;
4225
caac8545 4226 /* Update the compatible info with the probed one */
fad09c73 4227 chip->info = info;
bc46a3d5 4228
ca070c10
VD		 4229 err = mv88e6xxx_g2_require(chip);
4230 if (err)
4231 return err;
4232
fad09c73
VD		 4233 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4234 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4235
4236 return 0;
4237}
4238
fad09c73 4239static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4240{
fad09c73 4241 struct mv88e6xxx_chip *chip;
469d729f 4242
fad09c73
VD		 4243 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4244 if (!chip)
469d729f
VD		 4245 return NULL;
4246
fad09c73 4247 chip->dev = dev;
469d729f 4248
fad09c73 4249 mutex_init(&chip->reg_lock);
469d729f 4250
fad09c73 4251 return chip;
469d729f
VD		 4252}
4253
e57e5e77
VD		 4254static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4255{
b3469dd8 4256 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
e57e5e77 4257 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4258}
4259
930188ce
AL		 4260static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4261{
b3469dd8 4262 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
930188ce 4263 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4264}
4265
fad09c73 4266static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4267 struct mii_bus *bus, int sw_addr)
4268{
4269 /* ADDR[0] pin is unavailable externally and considered zero */
4270 if (sw_addr & 0x1)
4271 return -EINVAL;
4272
914b32f6 4273 if (sw_addr == 0)
fad09c73 4274 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4275 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4276 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4277 else
4278 return -EINVAL;
4279
fad09c73
VD		 4280 chip->bus = bus;
4281 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4282
4283 return 0;
4284}
4285
7b314362
AL		 4286static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4287{
04bed143 4288 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4289
443d5a1b 4290 return chip->info->tag_protocol;
7b314362
AL		 4291}
4292
fcdce7d0
AL		 4293static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4294 struct device *host_dev, int sw_addr,
4295 void **priv)
a77d43f1 4296{
fad09c73 4297 struct mv88e6xxx_chip *chip;
a439c061 4298 struct mii_bus *bus;
b516d453 4299 int err;
a77d43f1 4300
a439c061 4301 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4302 if (!bus)
4303 return NULL;
4304
fad09c73
VD		 4305 chip = mv88e6xxx_alloc_chip(dsa_dev);
4306 if (!chip)
469d729f
VD		 4307 return NULL;
4308
caac8545 4309 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4310 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4311
fad09c73 4312 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4313 if (err)
4314 goto free;
4315
fad09c73 4316 err = mv88e6xxx_detect(chip);
bc46a3d5 4317 if (err)
469d729f 4318 goto free;
a439c061 4319
dc30c35b
AL		 4320 mutex_lock(&chip->reg_lock);
4321 err = mv88e6xxx_switch_reset(chip);
4322 mutex_unlock(&chip->reg_lock);
4323 if (err)
4324 goto free;
4325
e57e5e77
VD		 4326 mv88e6xxx_phy_init(chip);
4327
fad09c73 4328 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 4329 if (err)
469d729f 4330 goto free;
b516d453 4331
fad09c73 4332 *priv = chip;
a439c061 4333
fad09c73 4334 return chip->info->name;
469d729f 4335free:
fad09c73 4336 devm_kfree(dsa_dev, chip);
469d729f
VD		 4337
4338 return NULL;
a77d43f1
AL		 4339}
4340
7df8fbdd
VD		 4341static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4342 const struct switchdev_obj_port_mdb *mdb,
4343 struct switchdev_trans *trans)
4344{
4345 /* We don't need any dynamic resource from the kernel (yet),
4346 * so skip the prepare phase.
4347 */
4348
4349 return 0;
4350}
4351
4352static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4353 const struct switchdev_obj_port_mdb *mdb,
4354 struct switchdev_trans *trans)
4355{
04bed143 4356 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4357
4358 mutex_lock(&chip->reg_lock);
4359 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4360 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4361 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4362 mutex_unlock(&chip->reg_lock);
4363}
4364
4365static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4366 const struct switchdev_obj_port_mdb *mdb)
4367{
04bed143 4368 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4369 int err;
4370
4371 mutex_lock(&chip->reg_lock);
4372 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4373 GLOBAL_ATU_DATA_STATE_UNUSED);
4374 mutex_unlock(&chip->reg_lock);
4375
4376 return err;
4377}
4378
4379static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4380 struct switchdev_obj_port_mdb *mdb,
4381 int (*cb)(struct switchdev_obj *obj))
4382{
04bed143 4383 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4384 int err;
4385
4386 mutex_lock(&chip->reg_lock);
4387 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4388 mutex_unlock(&chip->reg_lock);
4389
4390 return err;
4391}
4392
9d490b4e 4393static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4394 .probe = mv88e6xxx_drv_probe,
7b314362 4395 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4396 .setup = mv88e6xxx_setup,
4397 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4398 .adjust_link = mv88e6xxx_adjust_link,
4399 .get_strings = mv88e6xxx_get_strings,
4400 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4401 .get_sset_count = mv88e6xxx_get_sset_count,
4402 .set_eee = mv88e6xxx_set_eee,
4403 .get_eee = mv88e6xxx_get_eee,
4404#ifdef CONFIG_NET_DSA_HWMON
4405 .get_temp = mv88e6xxx_get_temp,
4406 .get_temp_limit = mv88e6xxx_get_temp_limit,
4407 .set_temp_limit = mv88e6xxx_set_temp_limit,
4408 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
4409#endif
f8cd8753 4410 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4411 .get_eeprom = mv88e6xxx_get_eeprom,
4412 .set_eeprom = mv88e6xxx_set_eeprom,
4413 .get_regs_len = mv88e6xxx_get_regs_len,
4414 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4415 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4416 .port_bridge_join = mv88e6xxx_port_bridge_join,
4417 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4418 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4419 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4420 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4421 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4422 .port_vlan_add = mv88e6xxx_port_vlan_add,
4423 .port_vlan_del = mv88e6xxx_port_vlan_del,
4424 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4425 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4426 .port_fdb_add = mv88e6xxx_port_fdb_add,
4427 .port_fdb_del = mv88e6xxx_port_fdb_del,
4428 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4429 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4430 .port_mdb_add = mv88e6xxx_port_mdb_add,
4431 .port_mdb_del = mv88e6xxx_port_mdb_del,
4432 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4433};
4434
fad09c73 4435static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 4436 struct device_node *np)
4437{
fad09c73 4438 struct device *dev = chip->dev;
b7e66a5f
VD		 4439 struct dsa_switch *ds;
4440
4441 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4442 if (!ds)
4443 return -ENOMEM;
4444
4445 ds->dev = dev;
fad09c73 4446 ds->priv = chip;
9d490b4e 4447 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4448
4449 dev_set_drvdata(dev, ds);
4450
4451 return dsa_register_switch(ds, np);
4452}
4453
fad09c73 4454static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4455{
fad09c73 4456 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4457}
4458
57d32310 4459static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4460{
14c7b3c3 4461 struct device *dev = &mdiodev->dev;
f8cd8753 4462 struct device_node *np = dev->of_node;
caac8545 4463 const struct mv88e6xxx_info *compat_info;
fad09c73 4464 struct mv88e6xxx_chip *chip;
f8cd8753 4465 u32 eeprom_len;
52638f71 4466 int err;
14c7b3c3 4467
caac8545
VD		 4468 compat_info = of_device_get_match_data(dev);
4469 if (!compat_info)
4470 return -EINVAL;
4471
fad09c73
VD		 4472 chip = mv88e6xxx_alloc_chip(dev);
4473 if (!chip)
14c7b3c3
AL		 4474 return -ENOMEM;
4475
fad09c73 4476 chip->info = compat_info;
caac8545 4477
56995cbc
AL		 4478 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4479 if (err)
4480 return err;
4481
fad09c73 4482 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4483 if (err)
4484 return err;
14c7b3c3 4485
b4308f04
AL		 4486 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4487 if (IS_ERR(chip->reset))
4488 return PTR_ERR(chip->reset);
4489
fad09c73 4490 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4491 if (err)
4492 return err;
14c7b3c3 4493
e57e5e77
VD		 4494 mv88e6xxx_phy_init(chip);
4495
ee4dc2e7 4496 if (chip->info->ops->get_eeprom &&
f8cd8753 4497 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4498 chip->eeprom_len = eeprom_len;
f8cd8753 4499
dc30c35b
AL		 4500 mutex_lock(&chip->reg_lock);
4501 err = mv88e6xxx_switch_reset(chip);
4502 mutex_unlock(&chip->reg_lock);
4503 if (err)
4504 goto out;
4505
4506 chip->irq = of_irq_get(np, 0);
4507 if (chip->irq == -EPROBE_DEFER) {
4508 err = chip->irq;
4509 goto out;
4510 }
4511
4512 if (chip->irq > 0) {
4513 /* Has to be performed before the MDIO bus is created,
4514 * because the PHYs will link there interrupts to these
4515 * interrupt controllers
4516 */
4517 mutex_lock(&chip->reg_lock);
4518 err = mv88e6xxx_g1_irq_setup(chip);
4519 mutex_unlock(&chip->reg_lock);
4520
4521 if (err)
4522 goto out;
4523
4524 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4525 err = mv88e6xxx_g2_irq_setup(chip);
4526 if (err)
4527 goto out_g1_irq;
4528 }
4529 }
4530
fad09c73 4531 err = mv88e6xxx_mdio_register(chip, np);
b516d453 4532 if (err)
dc30c35b 4533 goto out_g2_irq;
b516d453 4534
fad09c73 4535 err = mv88e6xxx_register_switch(chip, np);
dc30c35b
AL		 4536 if (err)
4537 goto out_mdio;
83c0afae 4538
98e67308 4539 return 0;
dc30c35b
AL		 4540
4541out_mdio:
4542 mv88e6xxx_mdio_unregister(chip);
4543out_g2_irq:
46712644 4544 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4545 mv88e6xxx_g2_irq_free(chip);
4546out_g1_irq:
61f7c3f8
AL		 4547 if (chip->irq > 0) {
4548 mutex_lock(&chip->reg_lock);
46712644 4549 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4550 mutex_unlock(&chip->reg_lock);
4551 }
dc30c35b
AL		 4552out:
4553 return err;
98e67308 4554}
14c7b3c3
AL		 4555
4556static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4557{
4558 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4559 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4560
930188ce 4561 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 4562 mv88e6xxx_unregister_switch(chip);
4563 mv88e6xxx_mdio_unregister(chip);
dc30c35b 4564
46712644
AL		 4565 if (chip->irq > 0) {
4566 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4567 mv88e6xxx_g2_irq_free(chip);
4568 mv88e6xxx_g1_irq_free(chip);
4569 }
14c7b3c3
AL		 4570}
4571
4572static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4573 {
4574 .compatible = "marvell,mv88e6085",
4575 .data = &mv88e6xxx_table[MV88E6085],
4576 },
1a3b39ec
AL		 4577 {
4578 .compatible = "marvell,mv88e6190",
4579 .data = &mv88e6xxx_table[MV88E6190],
4580 },
14c7b3c3
AL		 4581 { /* sentinel */ },
4582};
4583
4584MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4585
4586static struct mdio_driver mv88e6xxx_driver = {
4587 .probe = mv88e6xxx_probe,
4588 .remove = mv88e6xxx_remove,
4589 .mdiodrv.driver = {
4590 .name = "mv88e6085",
4591 .of_match_table = mv88e6xxx_of_match,
4592 },
4593};
4594
4595static int __init mv88e6xxx_init(void)
4596{
9d490b4e 4597 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 4598 return mdio_driver_register(&mv88e6xxx_driver);
4599}
98e67308
BH		 4600module_init(mv88e6xxx_init);
4601
4602static void __exit mv88e6xxx_cleanup(void)
4603{
14c7b3c3 4604 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 4605 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 4606}
4607module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4608
4609MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4610MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4611MODULE_LICENSE("GPL");
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