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[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
e57e5e77
VD		 225static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227{
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
b3469dd8 230 if (!chip->info->ops->phy_read)
e57e5e77
VD		 231 return -EOPNOTSUPP;
232
b3469dd8 233 return chip->info->ops->phy_read(chip, addr, reg, val);
e57e5e77
VD		 234}
235
236static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
b3469dd8 241 if (!chip->info->ops->phy_write)
e57e5e77
VD		 242 return -EOPNOTSUPP;
243
b3469dd8 244 return chip->info->ops->phy_write(chip, addr, reg, val);
e57e5e77
VD		 245}
246
09cb7dfd
VD		 247static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248{
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253}
254
255static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256{
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265}
266
267static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269{
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283}
284
285static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287{
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301}
302
303static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304{
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
309static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310{
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313}
314
dc30c35b
AL		 315static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316{
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321}
322
323static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324{
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329}
330
331static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332{
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356}
357
358static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359{
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363}
364
365static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366{
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383out:
384 mutex_unlock(&chip->reg_lock);
385}
386
387static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393};
394
395static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398{
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406}
407
408static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411};
412
413static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414{
415 int irq, virq;
3460a577
AL		 416 u16 mask;
417
418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
419 mask |= GENMASK(chip->g1_irq.nirqs, 0);
420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
421
422 free_irq(chip->irq, chip);
dc30c35b
AL		 423
424 for (irq = 0; irq < 16; irq++) {
a3db3d3a 425 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 426 irq_dispose_mapping(virq);
427 }
428
a3db3d3a 429 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 430}
431
432static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
433{
3dd0ef05
AL		 434 int err, irq, virq;
435 u16 reg, mask;
dc30c35b
AL		 436
437 chip->g1_irq.nirqs = chip->info->g1_irqs;
438 chip->g1_irq.domain = irq_domain_add_simple(
439 NULL, chip->g1_irq.nirqs, 0,
440 &mv88e6xxx_g1_irq_domain_ops, chip);
441 if (!chip->g1_irq.domain)
442 return -ENOMEM;
443
444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
445 irq_create_mapping(chip->g1_irq.domain, irq);
446
447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
448 chip->g1_irq.masked = ~0;
449
3dd0ef05 450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 451 if (err)
3dd0ef05 452 goto out_mapping;
dc30c35b 453
3dd0ef05 454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 455
3dd0ef05 456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 457 if (err)
3dd0ef05 458 goto out_disable;
dc30c35b
AL		 459
460 /* Reading the interrupt status clears (most of) them */
461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
462 if (err)
3dd0ef05 463 goto out_disable;
dc30c35b
AL		 464
465 err = request_threaded_irq(chip->irq, NULL,
466 mv88e6xxx_g1_irq_thread_fn,
467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
468 dev_name(chip->dev), chip);
469 if (err)
3dd0ef05 470 goto out_disable;
dc30c35b
AL		 471
472 return 0;
473
3dd0ef05
AL		 474out_disable:
475 mask |= GENMASK(chip->g1_irq.nirqs, 0);
476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
477
478out_mapping:
479 for (irq = 0; irq < 16; irq++) {
480 virq = irq_find_mapping(chip->g1_irq.domain, irq);
481 irq_dispose_mapping(virq);
482 }
483
484 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 485
486 return err;
487}
488
ec561276 489int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 490{
6441e669 491 int i;
2d79af6e 492
6441e669 493 for (i = 0; i < 16; i++) {
2d79af6e
VD		 494 u16 val;
495 int err;
496
497 err = mv88e6xxx_read(chip, addr, reg, &val);
498 if (err)
499 return err;
500
501 if (!(val & mask))
502 return 0;
503
504 usleep_range(1000, 2000);
505 }
506
30853553 507 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 508 return -ETIMEDOUT;
509}
510
f22ab641 511/* Indirect write to single pointer-data register with an Update bit */
ec561276 512int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 513{
514 u16 val;
0f02b4f7 515 int err;
f22ab641
VD		 516
517 /* Wait until the previous operation is completed */
0f02b4f7
AL		 518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
519 if (err)
520 return err;
f22ab641
VD		 521
522 /* Set the Update bit to trigger a write operation */
523 val = BIT(15) | update;
524
525 return mv88e6xxx_write(chip, addr, reg, val);
526}
527
a935c052 528static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6
VD		 529{
530 u16 val;
a935c052 531 int i, err;
914b32f6 532
a935c052 533 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
914b32f6
VD		 534 if (err)
535 return err;
536
a935c052
VD		 537 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
538 val & ~GLOBAL_CONTROL_PPU_ENABLE);
539 if (err)
540 return err;
2e5f0320 541
6441e669 542 for (i = 0; i < 16; i++) {
a935c052
VD		 543 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
544 if (err)
545 return err;
48ace4ef 546
19b2f97e 547 usleep_range(1000, 2000);
a935c052 548 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
85686581 549 return 0;
2e5f0320
LB		 550 }
551
552 return -ETIMEDOUT;
553}
554
fad09c73 555static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 556{
a935c052
VD		 557 u16 val;
558 int i, err;
2e5f0320 559
a935c052
VD		 560 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
561 if (err)
562 return err;
48ace4ef 563
a935c052
VD		 564 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
565 val | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 566 if (err)
567 return err;
2e5f0320 568
6441e669 569 for (i = 0; i < 16; i++) {
a935c052
VD		 570 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
571 if (err)
572 return err;
48ace4ef 573
19b2f97e 574 usleep_range(1000, 2000);
a935c052 575 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
85686581 576 return 0;
2e5f0320
LB		 577 }
578
579 return -ETIMEDOUT;
580}
581
582static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
583{
fad09c73 584 struct mv88e6xxx_chip *chip;
2e5f0320 585
fad09c73 586 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 587
fad09c73 588 mutex_lock(&chip->reg_lock);
762eb67b 589
fad09c73
VD		 590 if (mutex_trylock(&chip->ppu_mutex)) {
591 if (mv88e6xxx_ppu_enable(chip) == 0)
592 chip->ppu_disabled = 0;
593 mutex_unlock(&chip->ppu_mutex);
2e5f0320 594 }
762eb67b 595
fad09c73 596 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 597}
598
599static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
600{
fad09c73 601 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 602
fad09c73 603 schedule_work(&chip->ppu_work);
2e5f0320
LB		 604}
605
fad09c73 606static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 607{
2e5f0320
LB		 608 int ret;
609
fad09c73 610 mutex_lock(&chip->ppu_mutex);
2e5f0320 611
3675c8d7 612 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 613 * we can access the PHY registers. If it was already
614 * disabled, cancel the timer that is going to re-enable
615 * it.
616 */
fad09c73
VD		 617 if (!chip->ppu_disabled) {
618 ret = mv88e6xxx_ppu_disable(chip);
85686581 619 if (ret < 0) {
fad09c73 620 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 621 return ret;
622 }
fad09c73 623 chip->ppu_disabled = 1;
2e5f0320 624 } else {
fad09c73 625 del_timer(&chip->ppu_timer);
85686581 626 ret = 0;
2e5f0320
LB		 627 }
628
629 return ret;
630}
631
fad09c73 632static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 633{
3675c8d7 634 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 635 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
636 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 637}
638
fad09c73 639static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 640{
fad09c73
VD		 641 mutex_init(&chip->ppu_mutex);
642 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 643 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
644 (unsigned long)chip);
2e5f0320
LB		 645}
646
930188ce
AL		 647static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
648{
649 del_timer_sync(&chip->ppu_timer);
650}
651
e57e5e77
VD		 652static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
653 int reg, u16 *val)
2e5f0320 654{
e57e5e77 655 int err;
2e5f0320 656
e57e5e77
VD		 657 err = mv88e6xxx_ppu_access_get(chip);
658 if (!err) {
659 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 660 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 661 }
662
e57e5e77 663 return err;
2e5f0320
LB		 664}
665
e57e5e77
VD		 666static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
667 int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 693}
694
fad09c73 695static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 696{
fad09c73 697 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 698}
699
fad09c73 700static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 703}
704
fad09c73 705static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 708}
709
fad09c73 710static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 711{
fad09c73 712 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 713}
714
fad09c73 715static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 716{
fad09c73 717 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 718}
719
d78343d2
VD		 720static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
721 int link, int speed, int duplex,
722 phy_interface_t mode)
723{
724 int err;
725
726 if (!chip->info->ops->port_set_link)
727 return 0;
728
729 /* Port's MAC control must not be changed unless the link is down */
730 err = chip->info->ops->port_set_link(chip, port, 0);
731 if (err)
732 return err;
733
734 if (chip->info->ops->port_set_speed) {
735 err = chip->info->ops->port_set_speed(chip, port, speed);
736 if (err && err != -EOPNOTSUPP)
737 goto restore_link;
738 }
739
740 if (chip->info->ops->port_set_duplex) {
741 err = chip->info->ops->port_set_duplex(chip, port, duplex);
742 if (err && err != -EOPNOTSUPP)
743 goto restore_link;
744 }
745
746 if (chip->info->ops->port_set_rgmii_delay) {
747 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
748 if (err && err != -EOPNOTSUPP)
749 goto restore_link;
750 }
751
752 err = 0;
753restore_link:
754 if (chip->info->ops->port_set_link(chip, port, link))
755 netdev_err(chip->ds->ports[port].netdev,
756 "failed to restore MAC's link\n");
757
758 return err;
759}
760
dea87024
AL		 761/* We expect the switch to perform auto negotiation if there is a real
762 * phy. However, in the case of a fixed link phy, we force the port
763 * settings from the fixed link settings.
764 */
f81ec90f
VD		 765static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
766 struct phy_device *phydev)
dea87024 767{
04bed143 768 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 769 int err;
dea87024
AL		 770
771 if (!phy_is_pseudo_fixed_link(phydev))
772 return;
773
fad09c73 774 mutex_lock(&chip->reg_lock);
d78343d2
VD		 775 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
776 phydev->duplex, phydev->interface);
fad09c73 777 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 778
779 if (err && err != -EOPNOTSUPP)
780 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 781}
782
fad09c73 783static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8 784{
a935c052
VD		 785 u16 val;
786 int i, err;
91da11f8
LB		 787
788 for (i = 0; i < 10; i++) {
a935c052 789 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
096eea0f
AL		 790 if (err)
791 return err;
792
a935c052 793 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 794 return 0;
795 }
796
797 return -ETIMEDOUT;
798}
799
a605a0fe 800static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 801{
a605a0fe
AL		 802 if (!chip->info->ops->stats_snapshot)
803 return -EOPNOTSUPP;
91da11f8 804
a605a0fe 805 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 806}
807
fad09c73 808static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 809 int stat, u32 *val)
91da11f8 810{
a935c052
VD		 811 u32 value;
812 u16 reg;
813 int err;
91da11f8
LB		 814
815 *val = 0;
816
a935c052
VD		 817 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
818 GLOBAL_STATS_OP_READ_CAPTURED |
819 GLOBAL_STATS_OP_HIST_RX_TX | stat);
820 if (err)
91da11f8
LB		 821 return;
822
a935c052
VD		 823 err = _mv88e6xxx_stats_wait(chip);
824 if (err)
91da11f8
LB		 825 return;
826
a935c052
VD		 827 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
828 if (err)
91da11f8
LB		 829 return;
830
a935c052 831 value = reg << 16;
91da11f8 832
a935c052
VD		 833 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
834 if (err)
91da11f8
LB		 835 return;
836
a935c052 837 *val = value | reg;
91da11f8
LB		 838}
839
e413e7e1 840static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 841 { "in_good_octets", 8, 0x00, BANK0, },
842 { "in_bad_octets", 4, 0x02, BANK0, },
843 { "in_unicast", 4, 0x04, BANK0, },
844 { "in_broadcasts", 4, 0x06, BANK0, },
845 { "in_multicasts", 4, 0x07, BANK0, },
846 { "in_pause", 4, 0x16, BANK0, },
847 { "in_undersize", 4, 0x18, BANK0, },
848 { "in_fragments", 4, 0x19, BANK0, },
849 { "in_oversize", 4, 0x1a, BANK0, },
850 { "in_jabber", 4, 0x1b, BANK0, },
851 { "in_rx_error", 4, 0x1c, BANK0, },
852 { "in_fcs_error", 4, 0x1d, BANK0, },
853 { "out_octets", 8, 0x0e, BANK0, },
854 { "out_unicast", 4, 0x10, BANK0, },
855 { "out_broadcasts", 4, 0x13, BANK0, },
856 { "out_multicasts", 4, 0x12, BANK0, },
857 { "out_pause", 4, 0x15, BANK0, },
858 { "excessive", 4, 0x11, BANK0, },
859 { "collisions", 4, 0x1e, BANK0, },
860 { "deferred", 4, 0x05, BANK0, },
861 { "single", 4, 0x14, BANK0, },
862 { "multiple", 4, 0x17, BANK0, },
863 { "out_fcs_error", 4, 0x03, BANK0, },
864 { "late", 4, 0x1f, BANK0, },
865 { "hist_64bytes", 4, 0x08, BANK0, },
866 { "hist_65_127bytes", 4, 0x09, BANK0, },
867 { "hist_128_255bytes", 4, 0x0a, BANK0, },
868 { "hist_256_511bytes", 4, 0x0b, BANK0, },
869 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
870 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
871 { "sw_in_discards", 4, 0x10, PORT, },
872 { "sw_in_filtered", 2, 0x12, PORT, },
873 { "sw_out_filtered", 2, 0x13, PORT, },
874 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
875 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
876 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
877 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
878 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
879 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
880 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
881 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
882 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
883 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
884 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
885 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
886 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
887 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
888 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
889 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
890 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
891 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
892 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
893 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
894 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
895 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
896 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
897 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
898 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
899 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 900};
901
fad09c73 902static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 903 struct mv88e6xxx_hw_stat *stat)
e413e7e1 904{
f5e2ed02
AL		 905 switch (stat->type) {
906 case BANK0:
e413e7e1 907 return true;
f5e2ed02 908 case BANK1:
fad09c73 909 return mv88e6xxx_6320_family(chip);
f5e2ed02 910 case PORT:
fad09c73
VD		 911 return mv88e6xxx_6095_family(chip) ||
912 mv88e6xxx_6185_family(chip) ||
913 mv88e6xxx_6097_family(chip) ||
914 mv88e6xxx_6165_family(chip) ||
915 mv88e6xxx_6351_family(chip) ||
916 mv88e6xxx_6352_family(chip);
91da11f8 917 }
f5e2ed02 918 return false;
91da11f8
LB		 919}
920
fad09c73 921static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 922 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 923 int port)
924{
80c4627b
AL		 925 u32 low;
926 u32 high = 0;
0e7b9925
AL		 927 int err;
928 u16 reg;
80c4627b
AL		 929 u64 value;
930
f5e2ed02
AL		 931 switch (s->type) {
932 case PORT:
0e7b9925
AL		 933 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
934 if (err)
80c4627b
AL		 935 return UINT64_MAX;
936
0e7b9925 937 low = reg;
80c4627b 938 if (s->sizeof_stat == 4) {
0e7b9925
AL		 939 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
940 if (err)
80c4627b 941 return UINT64_MAX;
0e7b9925 942 high = reg;
80c4627b 943 }
f5e2ed02
AL		 944 break;
945 case BANK0:
946 case BANK1:
fad09c73 947 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 948 if (s->sizeof_stat == 8)
fad09c73 949 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 950 }
951 value = (((u64)high) << 16) | low;
952 return value;
953}
954
f81ec90f
VD		 955static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
956 uint8_t *data)
91da11f8 957{
04bed143 958 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 959 struct mv88e6xxx_hw_stat *stat;
960 int i, j;
91da11f8 961
f5e2ed02
AL		 962 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
963 stat = &mv88e6xxx_hw_stats[i];
fad09c73 964 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 965 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
966 ETH_GSTRING_LEN);
967 j++;
968 }
91da11f8 969 }
e413e7e1
AL		 970}
971
f81ec90f 972static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 973{
04bed143 974 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 975 struct mv88e6xxx_hw_stat *stat;
976 int i, j;
977
978 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
979 stat = &mv88e6xxx_hw_stats[i];
fad09c73 980 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 981 j++;
982 }
983 return j;
e413e7e1
AL		 984}
985
f81ec90f
VD		 986static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
987 uint64_t *data)
e413e7e1 988{
04bed143 989 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 990 struct mv88e6xxx_hw_stat *stat;
991 int ret;
992 int i, j;
993
fad09c73 994 mutex_lock(&chip->reg_lock);
f5e2ed02 995
a605a0fe 996 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 997 if (ret < 0) {
fad09c73 998 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 999 return;
1000 }
1001 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1002 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 1003 if (mv88e6xxx_has_stat(chip, stat)) {
1004 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 1005 j++;
1006 }
1007 }
1008
fad09c73 1009 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1010}
1011
f81ec90f 1012static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1013{
1014 return 32 * sizeof(u16);
1015}
1016
f81ec90f
VD		 1017static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1018 struct ethtool_regs *regs, void *_p)
a1ab91f3 1019{
04bed143 1020 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1021 int err;
1022 u16 reg;
a1ab91f3
GR		 1023 u16 *p = _p;
1024 int i;
1025
1026 regs->version = 0;
1027
1028 memset(p, 0xff, 32 * sizeof(u16));
1029
fad09c73 1030 mutex_lock(&chip->reg_lock);
23062513 1031
a1ab91f3 1032 for (i = 0; i < 32; i++) {
a1ab91f3 1033
0e7b9925
AL		 1034 err = mv88e6xxx_port_read(chip, port, i, &reg);
1035 if (!err)
1036 p[i] = reg;
a1ab91f3 1037 }
23062513 1038
fad09c73 1039 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1040}
1041
fad09c73 1042static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1043{
a935c052 1044 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1045}
1046
f81ec90f
VD		 1047static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1048 struct ethtool_eee *e)
11b3b45d 1049{
04bed143 1050 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1051 u16 reg;
1052 int err;
11b3b45d 1053
fad09c73 1054 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1055 return -EOPNOTSUPP;
1056
fad09c73 1057 mutex_lock(&chip->reg_lock);
2f40c698 1058
9c93829c
VD		 1059 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1060 if (err)
2f40c698 1061 goto out;
11b3b45d
GR		 1062
1063 e->eee_enabled = !!(reg & 0x0200);
1064 e->tx_lpi_enabled = !!(reg & 0x0100);
1065
0e7b9925 1066 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1067 if (err)
2f40c698 1068 goto out;
11b3b45d 1069
cca8b133 1070 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1071out:
fad09c73 1072 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1073
1074 return err;
11b3b45d
GR		 1075}
1076
f81ec90f
VD		 1077static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1078 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1079{
04bed143 1080 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1081 u16 reg;
1082 int err;
11b3b45d 1083
fad09c73 1084 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1085 return -EOPNOTSUPP;
1086
fad09c73 1087 mutex_lock(&chip->reg_lock);
11b3b45d 1088
9c93829c
VD		 1089 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1090 if (err)
2f40c698
AL		 1091 goto out;
1092
9c93829c 1093 reg &= ~0x0300;
2f40c698
AL		 1094 if (e->eee_enabled)
1095 reg |= 0x0200;
1096 if (e->tx_lpi_enabled)
1097 reg |= 0x0100;
1098
9c93829c 1099 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1100out:
fad09c73 1101 mutex_unlock(&chip->reg_lock);
2f40c698 1102
9c93829c 1103 return err;
11b3b45d
GR		 1104}
1105
fad09c73 1106static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1107{
a935c052
VD		 1108 u16 val;
1109 int err;
facd95b2 1110
6dc10bbc 1111 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1112 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1113 if (err)
1114 return err;
fad09c73 1115 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1116 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1117 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1118 if (err)
1119 return err;
11ea809f 1120
a935c052
VD		 1121 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1122 (val & 0xfff) | ((fid << 8) & 0xf000));
1123 if (err)
1124 return err;
11ea809f
VD		 1125
1126 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1127 cmd |= fid & 0xf;
b426e5f7
VD		 1128 }
1129
a935c052
VD		 1130 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1131 if (err)
1132 return err;
facd95b2 1133
fad09c73 1134 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1135}
1136
fad09c73 1137static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1138 struct mv88e6xxx_atu_entry *entry)
1139{
1140 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1141
1142 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1143 unsigned int mask, shift;
1144
1145 if (entry->trunk) {
1146 data |= GLOBAL_ATU_DATA_TRUNK;
1147 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1148 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1149 } else {
1150 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1151 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1152 }
1153
1154 data |= (entry->portv_trunkid << shift) & mask;
1155 }
1156
a935c052 1157 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1158}
1159
fad09c73 1160static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1161 struct mv88e6xxx_atu_entry *entry,
1162 bool static_too)
facd95b2 1163{
7fb5e755
VD		 1164 int op;
1165 int err;
facd95b2 1166
fad09c73 1167 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1168 if (err)
1169 return err;
facd95b2 1170
fad09c73 1171 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1172 if (err)
1173 return err;
1174
1175 if (entry->fid) {
7fb5e755
VD		 1176 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1177 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1178 } else {
1179 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1180 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1181 }
1182
fad09c73 1183 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1184}
1185
fad09c73 1186static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1187 u16 fid, bool static_too)
7fb5e755
VD		 1188{
1189 struct mv88e6xxx_atu_entry entry = {
1190 .fid = fid,
1191 .state = 0, /* EntryState bits must be 0 */
1192 };
70cc99d1 1193
fad09c73 1194 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1195}
1196
fad09c73 1197static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1198 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1199{
1200 struct mv88e6xxx_atu_entry entry = {
1201 .trunk = false,
1202 .fid = fid,
1203 };
1204
1205 /* EntryState bits must be 0xF */
1206 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1207
1208 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1209 entry.portv_trunkid = (to_port & 0x0f) << 4;
1210 entry.portv_trunkid |= from_port & 0x0f;
1211
fad09c73 1212 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1213}
1214
fad09c73 1215static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1216 int port, bool static_too)
9f4d55d2
VD		 1217{
1218 /* Destination port 0xF means remove the entries */
fad09c73 1219 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1220}
1221
fad09c73 1222static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1223{
fad09c73 1224 struct net_device *bridge = chip->ports[port].bridge_dev;
fad09c73 1225 struct dsa_switch *ds = chip->ds;
b7666efe 1226 u16 output_ports = 0;
b7666efe
VD		 1227 int i;
1228
1229 /* allow CPU port or DSA link(s) to send frames to every port */
1230 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1231 output_ports = ~0;
b7666efe 1232 } else {
370b4ffb 1233 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1234 /* allow sending frames to every group member */
fad09c73 1235 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1236 output_ports |= BIT(i);
1237
1238 /* allow sending frames to CPU port and DSA link(s) */
1239 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1240 output_ports |= BIT(i);
1241 }
1242 }
1243
1244 /* prevent frames from going back out of the port they came in on */
1245 output_ports &= ~BIT(port);
facd95b2 1246
5a7921f4 1247 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1248}
1249
f81ec90f
VD		 1250static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1251 u8 state)
facd95b2 1252{
04bed143 1253 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1254 int stp_state;
553eb544 1255 int err;
facd95b2
GR		 1256
1257 switch (state) {
1258 case BR_STATE_DISABLED:
cca8b133 1259 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1260 break;
1261 case BR_STATE_BLOCKING:
1262 case BR_STATE_LISTENING:
cca8b133 1263 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1264 break;
1265 case BR_STATE_LEARNING:
cca8b133 1266 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1267 break;
1268 case BR_STATE_FORWARDING:
1269 default:
cca8b133 1270 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1271 break;
1272 }
1273
fad09c73 1274 mutex_lock(&chip->reg_lock);
e28def33 1275 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1276 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1277
1278 if (err)
e28def33 1279 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1280}
1281
749efcb8
VD		 1282static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1283{
1284 struct mv88e6xxx_chip *chip = ds->priv;
1285 int err;
1286
1287 mutex_lock(&chip->reg_lock);
1288 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1289 mutex_unlock(&chip->reg_lock);
1290
1291 if (err)
1292 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1293}
1294
fad09c73 1295static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1296{
a935c052 1297 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1298}
1299
fad09c73 1300static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1301{
a935c052 1302 int err;
6b17e864 1303
a935c052
VD		 1304 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1305 if (err)
1306 return err;
6b17e864 1307
fad09c73 1308 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1309}
1310
fad09c73 1311static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1312{
1313 int ret;
1314
fad09c73 1315 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1316 if (ret < 0)
1317 return ret;
1318
fad09c73 1319 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1320}
1321
fad09c73 1322static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1323 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1324 unsigned int nibble_offset)
1325{
b8fee957 1326 u16 regs[3];
a935c052 1327 int i, err;
b8fee957
VD		 1328
1329 for (i = 0; i < 3; ++i) {
a935c052 1330 u16 *reg = &regs[i];
b8fee957 1331
a935c052
VD		 1332 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1333 if (err)
1334 return err;
b8fee957
VD		 1335 }
1336
370b4ffb 1337 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1338 unsigned int shift = (i % 4) * 4 + nibble_offset;
1339 u16 reg = regs[i / 4];
1340
1341 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1342 }
1343
1344 return 0;
1345}
1346
fad09c73 1347static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1348 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1349{
fad09c73 1350 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1351}
1352
fad09c73 1353static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1354 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1355{
fad09c73 1356 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1357}
1358
fad09c73 1359static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1360 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1361 unsigned int nibble_offset)
1362{
7dad08d7 1363 u16 regs[3] = { 0 };
a935c052 1364 int i, err;
7dad08d7 1365
370b4ffb 1366 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1367 unsigned int shift = (i % 4) * 4 + nibble_offset;
1368 u8 data = entry->data[i];
1369
1370 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1371 }
1372
1373 for (i = 0; i < 3; ++i) {
a935c052
VD		 1374 u16 reg = regs[i];
1375
1376 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1377 if (err)
1378 return err;
7dad08d7
VD		 1379 }
1380
1381 return 0;
1382}
1383
fad09c73 1384static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1385 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1386{
fad09c73 1387 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1388}
1389
fad09c73 1390static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1391 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1392{
fad09c73 1393 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1394}
1395
fad09c73 1396static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1397{
a935c052
VD		 1398 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1399 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1400}
1401
fad09c73 1402static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1403 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1404{
b4e47c0f 1405 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1406 u16 val;
1407 int err;
b8fee957 1408
a935c052
VD		 1409 err = _mv88e6xxx_vtu_wait(chip);
1410 if (err)
1411 return err;
b8fee957 1412
a935c052
VD		 1413 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1414 if (err)
1415 return err;
b8fee957 1416
a935c052
VD		 1417 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1418 if (err)
1419 return err;
b8fee957 1420
a935c052
VD		 1421 next.vid = val & GLOBAL_VTU_VID_MASK;
1422 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1423
1424 if (next.valid) {
a935c052
VD		 1425 err = mv88e6xxx_vtu_data_read(chip, &next);
1426 if (err)
1427 return err;
b8fee957 1428
6dc10bbc 1429 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1430 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1431 if (err)
1432 return err;
b8fee957 1433
a935c052 1434 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1435 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1436 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1437 * VTU DBNum[3:0] are located in VTU Operation 3:0
1438 */
a935c052
VD		 1439 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1440 if (err)
1441 return err;
11ea809f 1442
a935c052
VD		 1443 next.fid = (val & 0xf00) >> 4;
1444 next.fid |= val & 0xf;
2e7bd5ef 1445 }
b8fee957 1446
fad09c73 1447 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1448 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1449 if (err)
1450 return err;
b8fee957 1451
a935c052 1452 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1453 }
1454 }
1455
1456 *entry = next;
1457 return 0;
1458}
1459
f81ec90f
VD		 1460static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1461 struct switchdev_obj_port_vlan *vlan,
1462 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1463{
04bed143 1464 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1465 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1466 u16 pvid;
1467 int err;
1468
fad09c73 1469 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1470 return -EOPNOTSUPP;
1471
fad09c73 1472 mutex_lock(&chip->reg_lock);
ceff5eff 1473
77064f37 1474 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1475 if (err)
1476 goto unlock;
1477
fad09c73 1478 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1479 if (err)
1480 goto unlock;
1481
1482 do {
fad09c73 1483 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1484 if (err)
1485 break;
1486
1487 if (!next.valid)
1488 break;
1489
1490 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1491 continue;
1492
1493 /* reinit and dump this VLAN obj */
57d32310
VD		 1494 vlan->vid_begin = next.vid;
1495 vlan->vid_end = next.vid;
ceff5eff
VD		 1496 vlan->flags = 0;
1497
1498 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1499 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1500
1501 if (next.vid == pvid)
1502 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1503
1504 err = cb(&vlan->obj);
1505 if (err)
1506 break;
1507 } while (next.vid < GLOBAL_VTU_VID_MASK);
1508
1509unlock:
fad09c73 1510 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1511
1512 return err;
1513}
1514
fad09c73 1515static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1516 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1517{
11ea809f 1518 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1519 u16 reg = 0;
a935c052 1520 int err;
7dad08d7 1521
a935c052
VD		 1522 err = _mv88e6xxx_vtu_wait(chip);
1523 if (err)
1524 return err;
7dad08d7
VD		 1525
1526 if (!entry->valid)
1527 goto loadpurge;
1528
1529 /* Write port member tags */
a935c052
VD		 1530 err = mv88e6xxx_vtu_data_write(chip, entry);
1531 if (err)
1532 return err;
7dad08d7 1533
fad09c73 1534 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1535 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1536 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1537 if (err)
1538 return err;
b426e5f7 1539 }
7dad08d7 1540
6dc10bbc 1541 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1542 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1543 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1544 if (err)
1545 return err;
fad09c73 1546 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1547 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1548 * VTU DBNum[3:0] are located in VTU Operation 3:0
1549 */
1550 op |= (entry->fid & 0xf0) << 8;
1551 op |= entry->fid & 0xf;
7dad08d7
VD		 1552 }
1553
1554 reg = GLOBAL_VTU_VID_VALID;
1555loadpurge:
1556 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1557 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1558 if (err)
1559 return err;
7dad08d7 1560
fad09c73 1561 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1562}
1563
fad09c73 1564static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1565 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1566{
b4e47c0f 1567 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1568 u16 val;
1569 int err;
0d3b33e6 1570
a935c052
VD		 1571 err = _mv88e6xxx_vtu_wait(chip);
1572 if (err)
1573 return err;
0d3b33e6 1574
a935c052
VD		 1575 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1576 sid & GLOBAL_VTU_SID_MASK);
1577 if (err)
1578 return err;
0d3b33e6 1579
a935c052
VD		 1580 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1581 if (err)
1582 return err;
0d3b33e6 1583
a935c052
VD		 1584 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1585 if (err)
1586 return err;
0d3b33e6 1587
a935c052 1588 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1589
a935c052
VD		 1590 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1591 if (err)
1592 return err;
0d3b33e6 1593
a935c052 1594 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1595
1596 if (next.valid) {
a935c052
VD		 1597 err = mv88e6xxx_stu_data_read(chip, &next);
1598 if (err)
1599 return err;
0d3b33e6
VD		 1600 }
1601
1602 *entry = next;
1603 return 0;
1604}
1605
fad09c73 1606static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1607 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1608{
1609 u16 reg = 0;
a935c052 1610 int err;
0d3b33e6 1611
a935c052
VD		 1612 err = _mv88e6xxx_vtu_wait(chip);
1613 if (err)
1614 return err;
0d3b33e6
VD		 1615
1616 if (!entry->valid)
1617 goto loadpurge;
1618
1619 /* Write port states */
a935c052
VD		 1620 err = mv88e6xxx_stu_data_write(chip, entry);
1621 if (err)
1622 return err;
0d3b33e6
VD		 1623
1624 reg = GLOBAL_VTU_VID_VALID;
1625loadpurge:
a935c052
VD		 1626 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1627 if (err)
1628 return err;
0d3b33e6
VD		 1629
1630 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1631 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1632 if (err)
1633 return err;
0d3b33e6 1634
fad09c73 1635 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1636}
1637
fad09c73 1638static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1639{
1640 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1641 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1642 int i, err;
3285f9e8
VD		 1643
1644 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1645
2db9ce1f 1646 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1647 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1648 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1649 if (err)
1650 return err;
1651
1652 set_bit(*fid, fid_bitmap);
1653 }
1654
3285f9e8 1655 /* Set every FID bit used by the VLAN entries */
fad09c73 1656 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1657 if (err)
1658 return err;
1659
1660 do {
fad09c73 1661 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1662 if (err)
1663 return err;
1664
1665 if (!vlan.valid)
1666 break;
1667
1668 set_bit(vlan.fid, fid_bitmap);
1669 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1670
1671 /* The reset value 0x000 is used to indicate that multiple address
1672 * databases are not needed. Return the next positive available.
1673 */
1674 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1675 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1676 return -ENOSPC;
1677
1678 /* Clear the database */
fad09c73 1679 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1680}
1681
fad09c73 1682static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1683 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1684{
fad09c73 1685 struct dsa_switch *ds = chip->ds;
b4e47c0f 1686 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1687 .valid = true,
1688 .vid = vid,
1689 };
3285f9e8
VD		 1690 int i, err;
1691
fad09c73 1692 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1693 if (err)
1694 return err;
0d3b33e6 1695
3d131f07 1696 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1697 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1698 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1699 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1700 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1701
fad09c73
VD		 1702 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1703 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1704 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1705
1706 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1707 * implemented, only one STU entry is needed to cover all VTU
1708 * entries. Thus, validate the SID 0.
1709 */
1710 vlan.sid = 0;
fad09c73 1711 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1712 if (err)
1713 return err;
1714
1715 if (vstp.sid != vlan.sid || !vstp.valid) {
1716 memset(&vstp, 0, sizeof(vstp));
1717 vstp.valid = true;
1718 vstp.sid = vlan.sid;
1719
fad09c73 1720 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1721 if (err)
1722 return err;
1723 }
0d3b33e6
VD		 1724 }
1725
1726 *entry = vlan;
1727 return 0;
1728}
1729
fad09c73 1730static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1731 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1732{
1733 int err;
1734
1735 if (!vid)
1736 return -EINVAL;
1737
fad09c73 1738 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1739 if (err)
1740 return err;
1741
fad09c73 1742 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1743 if (err)
1744 return err;
1745
1746 if (entry->vid != vid || !entry->valid) {
1747 if (!creat)
1748 return -EOPNOTSUPP;
1749 /* -ENOENT would've been more appropriate, but switchdev expects
1750 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1751 */
1752
fad09c73 1753 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1754 }
1755
1756 return err;
1757}
1758
da9c359e
VD		 1759static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1760 u16 vid_begin, u16 vid_end)
1761{
04bed143 1762 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1763 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1764 int i, err;
1765
1766 if (!vid_begin)
1767 return -EOPNOTSUPP;
1768
fad09c73 1769 mutex_lock(&chip->reg_lock);
da9c359e 1770
fad09c73 1771 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1772 if (err)
1773 goto unlock;
1774
1775 do {
fad09c73 1776 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1777 if (err)
1778 goto unlock;
1779
1780 if (!vlan.valid)
1781 break;
1782
1783 if (vlan.vid > vid_end)
1784 break;
1785
370b4ffb 1786 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1787 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1788 continue;
1789
1790 if (vlan.data[i] ==
1791 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1792 continue;
1793
fad09c73
VD		 1794 if (chip->ports[i].bridge_dev ==
1795 chip->ports[port].bridge_dev)
da9c359e
VD		 1796 break; /* same bridge, check next VLAN */
1797
c8b09808 1798 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1799 "hardware VLAN %d already used by %s\n",
1800 vlan.vid,
fad09c73 1801 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1802 err = -EOPNOTSUPP;
1803 goto unlock;
1804 }
1805 } while (vlan.vid < vid_end);
1806
1807unlock:
fad09c73 1808 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1809
1810 return err;
1811}
1812
f81ec90f
VD		 1813static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1814 bool vlan_filtering)
214cdb99 1815{
04bed143 1816 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1817 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1818 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1819 int err;
214cdb99 1820
fad09c73 1821 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1822 return -EOPNOTSUPP;
1823
fad09c73 1824 mutex_lock(&chip->reg_lock);
385a0995 1825 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1826 mutex_unlock(&chip->reg_lock);
214cdb99 1827
0e7b9925 1828 return err;
214cdb99
VD		 1829}
1830
57d32310
VD		 1831static int
1832mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1833 const struct switchdev_obj_port_vlan *vlan,
1834 struct switchdev_trans *trans)
76e398a6 1835{
04bed143 1836 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1837 int err;
1838
fad09c73 1839 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1840 return -EOPNOTSUPP;
1841
da9c359e
VD		 1842 /* If the requested port doesn't belong to the same bridge as the VLAN
1843 * members, do not support it (yet) and fallback to software VLAN.
1844 */
1845 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1846 vlan->vid_end);
1847 if (err)
1848 return err;
1849
76e398a6
VD		 1850 /* We don't need any dynamic resource from the kernel (yet),
1851 * so skip the prepare phase.
1852 */
1853 return 0;
1854}
1855
fad09c73 1856static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1857 u16 vid, bool untagged)
0d3b33e6 1858{
b4e47c0f 1859 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1860 int err;
1861
fad09c73 1862 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1863 if (err)
76e398a6 1864 return err;
0d3b33e6 1865
0d3b33e6
VD		 1866 vlan.data[port] = untagged ?
1867 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1868 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1869
fad09c73 1870 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1871}
1872
f81ec90f
VD		 1873static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1874 const struct switchdev_obj_port_vlan *vlan,
1875 struct switchdev_trans *trans)
76e398a6 1876{
04bed143 1877 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1878 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1879 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1880 u16 vid;
76e398a6 1881
fad09c73 1882 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1883 return;
1884
fad09c73 1885 mutex_lock(&chip->reg_lock);
76e398a6 1886
4d5770b3 1887 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1888 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1889 netdev_err(ds->ports[port].netdev,
1890 "failed to add VLAN %d%c\n",
4d5770b3 1891 vid, untagged ? 'u' : 't');
76e398a6 1892
77064f37 1893 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1894 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1895 vlan->vid_end);
0d3b33e6 1896
fad09c73 1897 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1898}
1899
fad09c73 1900static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1901 int port, u16 vid)
7dad08d7 1902{
fad09c73 1903 struct dsa_switch *ds = chip->ds;
b4e47c0f 1904 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1905 int i, err;
1906
fad09c73 1907 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1908 if (err)
76e398a6 1909 return err;
7dad08d7 1910
2fb5ef09
VD		 1911 /* Tell switchdev if this VLAN is handled in software */
1912 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1913 return -EOPNOTSUPP;
7dad08d7
VD		 1914
1915 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1916
1917 /* keep the VLAN unless all ports are excluded */
f02bdffc 1918 vlan.valid = false;
370b4ffb 1919 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1920 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1921 continue;
1922
1923 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1924 vlan.valid = true;
7dad08d7
VD		 1925 break;
1926 }
1927 }
1928
fad09c73 1929 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1930 if (err)
1931 return err;
1932
fad09c73 1933 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1934}
1935
f81ec90f
VD		 1936static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1937 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1938{
04bed143 1939 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1940 u16 pvid, vid;
1941 int err = 0;
1942
fad09c73 1943 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1944 return -EOPNOTSUPP;
1945
fad09c73 1946 mutex_lock(&chip->reg_lock);
76e398a6 1947
77064f37 1948 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1949 if (err)
1950 goto unlock;
1951
76e398a6 1952 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1953 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1954 if (err)
1955 goto unlock;
1956
1957 if (vid == pvid) {
77064f37 1958 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1959 if (err)
1960 goto unlock;
1961 }
1962 }
1963
7dad08d7 1964unlock:
fad09c73 1965 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1966
1967 return err;
1968}
1969
fad09c73 1970static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 1971 const unsigned char *addr)
defb05b9 1972{
a935c052 1973 int i, err;
defb05b9
GR		 1974
1975 for (i = 0; i < 3; i++) {
a935c052
VD		 1976 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
1977 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1978 if (err)
1979 return err;
defb05b9
GR		 1980 }
1981
1982 return 0;
1983}
1984
fad09c73 1985static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 1986 unsigned char *addr)
defb05b9 1987{
a935c052
VD		 1988 u16 val;
1989 int i, err;
defb05b9
GR		 1990
1991 for (i = 0; i < 3; i++) {
a935c052
VD		 1992 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
1993 if (err)
1994 return err;
1995
1996 addr[i * 2] = val >> 8;
1997 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 1998 }
1999
2000 return 0;
2001}
2002
fad09c73 2003static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2004 struct mv88e6xxx_atu_entry *entry)
defb05b9 2005{
6630e236
VD		 2006 int ret;
2007
fad09c73 2008 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2009 if (ret < 0)
2010 return ret;
2011
fad09c73 2012 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2013 if (ret < 0)
2014 return ret;
2015
fad09c73 2016 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2017 if (ret < 0)
87820510
VD		 2018 return ret;
2019
fad09c73 2020 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2021}
87820510 2022
88472939
VD		 2023static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2024 struct mv88e6xxx_atu_entry *entry);
2025
2026static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2027 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2028{
2029 struct mv88e6xxx_atu_entry next;
2030 int err;
2031
2032 eth_broadcast_addr(next.mac);
2033
2034 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2035 if (err)
2036 return err;
2037
2038 do {
2039 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2040 if (err)
2041 return err;
2042
2043 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2044 break;
2045
2046 if (ether_addr_equal(next.mac, addr)) {
2047 *entry = next;
2048 return 0;
2049 }
2050 } while (!is_broadcast_ether_addr(next.mac));
2051
2052 memset(entry, 0, sizeof(*entry));
2053 entry->fid = fid;
2054 ether_addr_copy(entry->mac, addr);
2055
2056 return 0;
2057}
2058
83dabd1f
VD		 2059static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2060 const unsigned char *addr, u16 vid,
2061 u8 state)
fd231c82 2062{
b4e47c0f 2063 struct mv88e6xxx_vtu_entry vlan;
88472939 2064 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2065 int err;
2066
2db9ce1f
VD		 2067 /* Null VLAN ID corresponds to the port private database */
2068 if (vid == 0)
b4e48c50 2069 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2070 else
fad09c73 2071 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2072 if (err)
2073 return err;
fd231c82 2074
88472939
VD		 2075 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2076 if (err)
2077 return err;
2078
2079 /* Purge the ATU entry only if no port is using it anymore */
2080 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2081 entry.portv_trunkid &= ~BIT(port);
2082 if (!entry.portv_trunkid)
2083 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2084 } else {
2085 entry.portv_trunkid |= BIT(port);
2086 entry.state = state;
fd231c82
VD		 2087 }
2088
fad09c73 2089 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2090}
2091
f81ec90f
VD		 2092static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2093 const struct switchdev_obj_port_fdb *fdb,
2094 struct switchdev_trans *trans)
146a3206
VD		 2095{
2096 /* We don't need any dynamic resource from the kernel (yet),
2097 * so skip the prepare phase.
2098 */
2099 return 0;
2100}
2101
f81ec90f
VD		 2102static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2103 const struct switchdev_obj_port_fdb *fdb,
2104 struct switchdev_trans *trans)
87820510 2105{
04bed143 2106 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2107
fad09c73 2108 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2109 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2110 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2111 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2112 mutex_unlock(&chip->reg_lock);
87820510
VD		 2113}
2114
f81ec90f
VD		 2115static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2116 const struct switchdev_obj_port_fdb *fdb)
87820510 2117{
04bed143 2118 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2119 int err;
87820510 2120
fad09c73 2121 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2122 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2123 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2124 mutex_unlock(&chip->reg_lock);
87820510 2125
83dabd1f 2126 return err;
87820510
VD		 2127}
2128
fad09c73 2129static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2130 struct mv88e6xxx_atu_entry *entry)
6630e236 2131{
1d194046 2132 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2133 u16 val;
2134 int err;
1d194046
VD		 2135
2136 next.fid = fid;
defb05b9 2137
a935c052
VD		 2138 err = _mv88e6xxx_atu_wait(chip);
2139 if (err)
2140 return err;
6630e236 2141
a935c052
VD		 2142 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2143 if (err)
2144 return err;
6630e236 2145
a935c052
VD		 2146 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2147 if (err)
2148 return err;
6630e236 2149
a935c052
VD		 2150 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2151 if (err)
2152 return err;
6630e236 2153
a935c052 2154 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2155 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2156 unsigned int mask, shift;
2157
a935c052 2158 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2159 next.trunk = true;
2160 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2161 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2162 } else {
2163 next.trunk = false;
2164 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2165 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2166 }
2167
a935c052 2168 next.portv_trunkid = (val & mask) >> shift;
1d194046 2169 }
cdf09697 2170
1d194046 2171 *entry = next;
cdf09697
DM		 2172 return 0;
2173}
2174
83dabd1f
VD		 2175static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2176 u16 fid, u16 vid, int port,
2177 struct switchdev_obj *obj,
2178 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2179{
2180 struct mv88e6xxx_atu_entry addr = {
2181 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2182 };
2183 int err;
2184
fad09c73 2185 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2186 if (err)
2187 return err;
2188
2189 do {
fad09c73 2190 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2191 if (err)
83dabd1f 2192 return err;
74b6ba0d
VD		 2193
2194 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2195 break;
2196
83dabd1f
VD		 2197 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2198 continue;
2199
2200 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2201 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2202
83dabd1f
VD		 2203 if (!is_unicast_ether_addr(addr.mac))
2204 continue;
2205
2206 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2207 fdb->vid = vid;
2208 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2209 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2210 fdb->ndm_state = NUD_NOARP;
2211 else
2212 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2213 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2214 struct switchdev_obj_port_mdb *mdb;
2215
2216 if (!is_multicast_ether_addr(addr.mac))
2217 continue;
2218
2219 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2220 mdb->vid = vid;
2221 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2222 } else {
2223 return -EOPNOTSUPP;
74b6ba0d 2224 }
83dabd1f
VD		 2225
2226 err = cb(obj);
2227 if (err)
2228 return err;
74b6ba0d
VD		 2229 } while (!is_broadcast_ether_addr(addr.mac));
2230
2231 return err;
2232}
2233
83dabd1f
VD		 2234static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2235 struct switchdev_obj *obj,
2236 int (*cb)(struct switchdev_obj *obj))
f33475bd 2237{
b4e47c0f 2238 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2239 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2240 };
2db9ce1f 2241 u16 fid;
f33475bd
VD		 2242 int err;
2243
2db9ce1f 2244 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2245 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2246 if (err)
83dabd1f 2247 return err;
2db9ce1f 2248
83dabd1f 2249 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2250 if (err)
83dabd1f 2251 return err;
2db9ce1f 2252
74b6ba0d 2253 /* Dump VLANs' Filtering Information Databases */
fad09c73 2254 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2255 if (err)
83dabd1f 2256 return err;
f33475bd
VD		 2257
2258 do {
fad09c73 2259 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2260 if (err)
83dabd1f 2261 return err;
f33475bd
VD		 2262
2263 if (!vlan.valid)
2264 break;
2265
83dabd1f
VD		 2266 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2267 obj, cb);
f33475bd 2268 if (err)
83dabd1f 2269 return err;
f33475bd
VD		 2270 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2271
83dabd1f
VD		 2272 return err;
2273}
2274
2275static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2276 struct switchdev_obj_port_fdb *fdb,
2277 int (*cb)(struct switchdev_obj *obj))
2278{
04bed143 2279 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2280 int err;
2281
2282 mutex_lock(&chip->reg_lock);
2283 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2284 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2285
2286 return err;
2287}
2288
f81ec90f
VD		 2289static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2290 struct net_device *bridge)
e79a8bcb 2291{
04bed143 2292 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2293 int i, err = 0;
466dfa07 2294
fad09c73 2295 mutex_lock(&chip->reg_lock);
466dfa07 2296
b7666efe 2297 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2298 chip->ports[port].bridge_dev = bridge;
b7666efe 2299
370b4ffb 2300 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2301 if (chip->ports[i].bridge_dev == bridge) {
2302 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2303 if (err)
2304 break;
2305 }
2306 }
2307
fad09c73 2308 mutex_unlock(&chip->reg_lock);
a6692754 2309
466dfa07 2310 return err;
e79a8bcb
VD		 2311}
2312
f81ec90f 2313static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2314{
04bed143 2315 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2316 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2317 int i;
466dfa07 2318
fad09c73 2319 mutex_lock(&chip->reg_lock);
466dfa07 2320
b7666efe 2321 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2322 chip->ports[port].bridge_dev = NULL;
b7666efe 2323
370b4ffb 2324 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2325 if (i == port || chip->ports[i].bridge_dev == bridge)
2326 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2327 netdev_warn(ds->ports[i].netdev,
2328 "failed to remap\n");
b7666efe 2329
fad09c73 2330 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2331}
2332
fad09c73 2333static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2334{
fad09c73 2335 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2336 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2337 struct gpio_desc *gpiod = chip->reset;
552238b5 2338 unsigned long timeout;
0e7b9925 2339 u16 reg;
a935c052 2340 int err;
552238b5
VD		 2341 int i;
2342
2343 /* Set all ports to the disabled state. */
370b4ffb 2344 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2345 err = mv88e6xxx_port_set_state(chip, i,
2346 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2347 if (err)
2348 return err;
552238b5
VD		 2349 }
2350
2351 /* Wait for transmit queues to drain. */
2352 usleep_range(2000, 4000);
2353
2354 /* If there is a gpio connected to the reset pin, toggle it */
2355 if (gpiod) {
2356 gpiod_set_value_cansleep(gpiod, 1);
2357 usleep_range(10000, 20000);
2358 gpiod_set_value_cansleep(gpiod, 0);
2359 usleep_range(10000, 20000);
2360 }
2361
2362 /* Reset the switch. Keep the PPU active if requested. The PPU
2363 * needs to be active to support indirect phy register access
2364 * through global registers 0x18 and 0x19.
2365 */
2366 if (ppu_active)
a935c052 2367 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
552238b5 2368 else
a935c052 2369 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
0e7b9925
AL		 2370 if (err)
2371 return err;
552238b5
VD		 2372
2373 /* Wait up to one second for reset to complete. */
2374 timeout = jiffies + 1 * HZ;
2375 while (time_before(jiffies, timeout)) {
a935c052
VD		 2376 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2377 if (err)
2378 return err;
552238b5 2379
a935c052 2380 if ((reg & is_reset) == is_reset)
552238b5
VD		 2381 break;
2382 usleep_range(1000, 2000);
2383 }
2384 if (time_after(jiffies, timeout))
0e7b9925 2385 err = -ETIMEDOUT;
552238b5 2386 else
0e7b9925 2387 err = 0;
552238b5 2388
0e7b9925 2389 return err;
552238b5
VD		 2390}
2391
09cb7dfd 2392static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2393{
09cb7dfd
VD		 2394 u16 val;
2395 int err;
13a7ebb3 2396
09cb7dfd
VD		 2397 /* Clear Power Down bit */
2398 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2399 if (err)
2400 return err;
13a7ebb3 2401
09cb7dfd
VD		 2402 if (val & BMCR_PDOWN) {
2403 val &= ~BMCR_PDOWN;
2404 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2405 }
2406
09cb7dfd 2407 return err;
13a7ebb3
PU		 2408}
2409
fad09c73 2410static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2411{
fad09c73 2412 struct dsa_switch *ds = chip->ds;
0e7b9925 2413 int err;
54d792f2 2414 u16 reg;
d827e88a 2415
d78343d2
VD		 2416 /* MAC Forcing register: don't force link, speed, duplex or flow control
2417 * state to any particular values on physical ports, but force the CPU
2418 * port and all DSA ports to their maximum bandwidth and full duplex.
2419 */
2420 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2421 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2422 SPEED_MAX, DUPLEX_FULL,
2423 PHY_INTERFACE_MODE_NA);
2424 else
2425 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2426 SPEED_UNFORCED, DUPLEX_UNFORCED,
2427 PHY_INTERFACE_MODE_NA);
2428 if (err)
2429 return err;
54d792f2
AL		 2430
2431 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2432 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2433 * tunneling, determine priority by looking at 802.1p and IP
2434 * priority fields (IP prio has precedence), and set STP state
2435 * to Forwarding.
2436 *
2437 * If this is the CPU link, use DSA or EDSA tagging depending
2438 * on which tagging mode was configured.
2439 *
2440 * If this is a link to another switch, use DSA tagging mode.
2441 *
2442 * If this is the upstream port for this switch, enable
2443 * forwarding of unknown unicasts and multicasts.
2444 */
2445 reg = 0;
fad09c73
VD		 2446 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2447 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2448 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2449 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2450 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2451 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2452 PORT_CONTROL_STATE_FORWARDING;
2453 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2454 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2455 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2456 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2457 else
2458 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2459 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2460 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2461 }
6083ce71 2462 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2463 if (mv88e6xxx_6095_family(chip) ||
2464 mv88e6xxx_6185_family(chip))
6083ce71 2465 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2466 if (mv88e6xxx_6352_family(chip) ||
2467 mv88e6xxx_6351_family(chip) ||
2468 mv88e6xxx_6165_family(chip) ||
2469 mv88e6xxx_6097_family(chip) ||
2470 mv88e6xxx_6320_family(chip)) {
54d792f2 2471 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2472 }
2473
54d792f2
AL		 2474 if (port == dsa_upstream_port(ds))
2475 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2476 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2477 }
2478 if (reg) {
0e7b9925
AL		 2479 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2480 if (err)
2481 return err;
54d792f2
AL		 2482 }
2483
13a7ebb3
PU		 2484 /* If this port is connected to a SerDes, make sure the SerDes is not
2485 * powered down.
2486 */
09cb7dfd 2487 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2488 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2489 if (err)
2490 return err;
2491 reg &= PORT_STATUS_CMODE_MASK;
2492 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2493 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2494 (reg == PORT_STATUS_CMODE_SGMII)) {
2495 err = mv88e6xxx_serdes_power_on(chip);
2496 if (err < 0)
2497 return err;
13a7ebb3
PU		 2498 }
2499 }
2500
8efdda4a 2501 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2502 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2503 * untagged frames on this port, do a destination address lookup on all
2504 * received packets as usual, disable ARP mirroring and don't send a
2505 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2506 */
2507 reg = 0;
fad09c73
VD		 2508 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2509 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2510 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2511 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2512 reg = PORT_CONTROL_2_MAP_DA;
2513
fad09c73
VD		 2514 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2515 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2516 reg |= PORT_CONTROL_2_JUMBO_10240;
2517
fad09c73 2518 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2519 /* Set the upstream port this port should use */
2520 reg |= dsa_upstream_port(ds);
2521 /* enable forwarding of unknown multicast addresses to
2522 * the upstream port
2523 */
2524 if (port == dsa_upstream_port(ds))
2525 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2526 }
2527
46fbe5e5 2528 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2529
54d792f2 2530 if (reg) {
0e7b9925
AL		 2531 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2532 if (err)
2533 return err;
54d792f2
AL		 2534 }
2535
2536 /* Port Association Vector: when learning source addresses
2537 * of packets, add the address to the address database using
2538 * a port bitmap that has only the bit for this port set and
2539 * the other bits clear.
2540 */
4c7ea3c0 2541 reg = 1 << port;
996ecb82
VD		 2542 /* Disable learning for CPU port */
2543 if (dsa_is_cpu_port(ds, port))
65fa4027 2544 reg = 0;
4c7ea3c0 2545
0e7b9925
AL		 2546 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2547 if (err)
2548 return err;
54d792f2
AL		 2549
2550 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2551 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2552 if (err)
2553 return err;
54d792f2 2554
fad09c73
VD		 2555 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2556 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2557 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2558 /* Do not limit the period of time that this port can
2559 * be paused for by the remote end or the period of
2560 * time that this port can pause the remote end.
2561 */
0e7b9925
AL		 2562 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2563 if (err)
2564 return err;
54d792f2
AL		 2565
2566 /* Port ATU control: disable limiting the number of
2567 * address database entries that this port is allowed
2568 * to use.
2569 */
0e7b9925
AL		 2570 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2571 0x0000);
54d792f2
AL		 2572 /* Priority Override: disable DA, SA and VTU priority
2573 * override.
2574 */
0e7b9925
AL		 2575 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2576 0x0000);
2577 if (err)
2578 return err;
54d792f2
AL		 2579
2580 /* Port Ethertype: use the Ethertype DSA Ethertype
2581 * value.
2582 */
2bbb33be 2583 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
0e7b9925
AL		 2584 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2585 ETH_P_EDSA);
2586 if (err)
2587 return err;
2bbb33be
AL		 2588 }
2589
54d792f2
AL		 2590 /* Tag Remap: use an identity 802.1p prio -> switch
2591 * prio mapping.
2592 */
0e7b9925
AL		 2593 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2594 0x3210);
2595 if (err)
2596 return err;
54d792f2
AL		 2597
2598 /* Tag Remap 2: use an identity 802.1p prio -> switch
2599 * prio mapping.
2600 */
0e7b9925
AL		 2601 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2602 0x7654);
2603 if (err)
2604 return err;
54d792f2
AL		 2605 }
2606
1bc261fa 2607 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2608 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2609 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2610 mv88e6xxx_6320_family(chip)) {
0e7b9925
AL		 2611 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2612 0x0001);
2613 if (err)
2614 return err;
1bc261fa 2615 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
0e7b9925
AL		 2616 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2617 0x0000);
2618 if (err)
2619 return err;
54d792f2
AL		 2620 }
2621
366f0a0f
GR		 2622 /* Port Control 1: disable trunking, disable sending
2623 * learning messages to this port.
d827e88a 2624 */
0e7b9925
AL		 2625 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2626 if (err)
2627 return err;
d827e88a 2628
207afda1 2629 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2630 * database, and allow bidirectional communication between the
2631 * CPU and DSA port(s), and the other ports.
d827e88a 2632 */
b4e48c50 2633 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2634 if (err)
2635 return err;
2db9ce1f 2636
0e7b9925
AL		 2637 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2638 if (err)
2639 return err;
d827e88a
GR		 2640
2641 /* Default VLAN ID and priority: don't set a default VLAN
2642 * ID, and set the default packet priority to zero.
2643 */
0e7b9925 2644 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2645}
2646
aa0938c6 2647static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2648{
2649 int err;
2650
a935c052 2651 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2652 if (err)
2653 return err;
2654
a935c052 2655 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2656 if (err)
2657 return err;
2658
a935c052
VD		 2659 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2660 if (err)
2661 return err;
2662
2663 return 0;
3b4caa1b
VD		 2664}
2665
acddbd21
VD		 2666static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2667 unsigned int msecs)
2668{
2669 const unsigned int coeff = chip->info->age_time_coeff;
2670 const unsigned int min = 0x01 * coeff;
2671 const unsigned int max = 0xff * coeff;
2672 u8 age_time;
2673 u16 val;
2674 int err;
2675
2676 if (msecs < min || msecs > max)
2677 return -ERANGE;
2678
2679 /* Round to nearest multiple of coeff */
2680 age_time = (msecs + coeff / 2) / coeff;
2681
a935c052 2682 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2683 if (err)
2684 return err;
2685
2686 /* AgeTime is 11:4 bits */
2687 val &= ~0xff0;
2688 val |= age_time << 4;
2689
a935c052 2690 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2691}
2692
2cfcd964
VD		 2693static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2694 unsigned int ageing_time)
2695{
04bed143 2696 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2697 int err;
2698
2699 mutex_lock(&chip->reg_lock);
2700 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2701 mutex_unlock(&chip->reg_lock);
2702
2703 return err;
2704}
2705
9729934c 2706static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2707{
fad09c73 2708 struct dsa_switch *ds = chip->ds;
b0745e87 2709 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2710 u16 reg;
552238b5 2711 int err;
54d792f2 2712
119477bd
VD		 2713 /* Enable the PHY Polling Unit if present, don't discard any packets,
2714 * and mask all interrupt sources.
2715 */
dc30c35b
AL		 2716 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2717 if (err < 0)
2718 return err;
2719
2720 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
fad09c73
VD		 2721 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2722 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2723 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2724
a935c052 2725 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
119477bd
VD		 2726 if (err)
2727 return err;
2728
b0745e87
VD		 2729 /* Configure the upstream port, and configure it as the port to which
2730 * ingress and egress and ARP monitor frames are to be sent.
2731 */
2732 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2733 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2734 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
a935c052 2735 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
b0745e87
VD		 2736 if (err)
2737 return err;
2738
50484ff4 2739 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2740 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2741 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2742 (ds->index & 0x1f));
50484ff4
VD		 2743 if (err)
2744 return err;
2745
acddbd21
VD		 2746 /* Clear all the VTU and STU entries */
2747 err = _mv88e6xxx_vtu_stu_flush(chip);
2748 if (err < 0)
2749 return err;
2750
54d792f2
AL		 2751 /* Set the default address aging time to 5 minutes, and
2752 * enable address learn messages to be sent to all message
2753 * ports.
2754 */
a935c052
VD		 2755 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2756 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2757 if (err)
08a01261 2758 return err;
54d792f2 2759
acddbd21
VD		 2760 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2761 if (err)
9729934c
VD		 2762 return err;
2763
2764 /* Clear all ATU entries */
2765 err = _mv88e6xxx_atu_flush(chip, 0, true);
2766 if (err)
2767 return err;
2768
54d792f2 2769 /* Configure the IP ToS mapping registers. */
a935c052 2770 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2771 if (err)
08a01261 2772 return err;
a935c052 2773 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2774 if (err)
08a01261 2775 return err;
a935c052 2776 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2777 if (err)
08a01261 2778 return err;
a935c052 2779 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2780 if (err)
08a01261 2781 return err;
a935c052 2782 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2783 if (err)
08a01261 2784 return err;
a935c052 2785 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2786 if (err)
08a01261 2787 return err;
a935c052 2788 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2789 if (err)
08a01261 2790 return err;
a935c052 2791 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2792 if (err)
08a01261 2793 return err;
54d792f2
AL		 2794
2795 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2796 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2797 if (err)
08a01261 2798 return err;
54d792f2 2799
9729934c 2800 /* Clear the statistics counters for all ports */
a935c052
VD		 2801 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2802 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2803 if (err)
2804 return err;
2805
2806 /* Wait for the flush to complete. */
2807 err = _mv88e6xxx_stats_wait(chip);
2808 if (err)
2809 return err;
2810
2811 return 0;
2812}
2813
f81ec90f 2814static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2815{
04bed143 2816 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2817 int err;
a1a6a4d1
VD		 2818 int i;
2819
fad09c73
VD		 2820 chip->ds = ds;
2821 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2822
fad09c73 2823 mutex_lock(&chip->reg_lock);
08a01261 2824
9729934c 2825 /* Setup Switch Port Registers */
370b4ffb 2826 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2827 err = mv88e6xxx_setup_port(chip, i);
2828 if (err)
2829 goto unlock;
2830 }
2831
2832 /* Setup Switch Global 1 Registers */
2833 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2834 if (err)
2835 goto unlock;
2836
9729934c
VD		 2837 /* Setup Switch Global 2 Registers */
2838 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2839 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2840 if (err)
2841 goto unlock;
2842 }
08a01261 2843
6b17e864 2844unlock:
fad09c73 2845 mutex_unlock(&chip->reg_lock);
db687a56 2846
48ace4ef 2847 return err;
54d792f2
AL		 2848}
2849
3b4caa1b
VD		 2850static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2851{
04bed143 2852 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2853 int err;
2854
b073d4e2
VD		 2855 if (!chip->info->ops->set_switch_mac)
2856 return -EOPNOTSUPP;
3b4caa1b 2857
b073d4e2
VD		 2858 mutex_lock(&chip->reg_lock);
2859 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2860 mutex_unlock(&chip->reg_lock);
2861
2862 return err;
2863}
2864
e57e5e77 2865static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2866{
fad09c73 2867 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2868 u16 val;
2869 int err;
fd3a0ee4 2870
370b4ffb 2871 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2872 return 0xffff;
fd3a0ee4 2873
fad09c73 2874 mutex_lock(&chip->reg_lock);
e57e5e77 2875 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2876 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2877
2878 return err ? err : val;
fd3a0ee4
AL		 2879}
2880
e57e5e77 2881static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2882{
fad09c73 2883 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2884 int err;
fd3a0ee4 2885
370b4ffb 2886 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2887 return 0xffff;
fd3a0ee4 2888
fad09c73 2889 mutex_lock(&chip->reg_lock);
e57e5e77 2890 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2891 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2892
2893 return err;
fd3a0ee4
AL		 2894}
2895
fad09c73 2896static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2897 struct device_node *np)
2898{
2899 static int index;
2900 struct mii_bus *bus;
2901 int err;
2902
b516d453 2903 if (np)
fad09c73 2904 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2905
fad09c73 2906 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2907 if (!bus)
2908 return -ENOMEM;
2909
fad09c73 2910 bus->priv = (void *)chip;
b516d453
AL		 2911 if (np) {
2912 bus->name = np->full_name;
2913 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2914 } else {
2915 bus->name = "mv88e6xxx SMI";
2916 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2917 }
2918
2919 bus->read = mv88e6xxx_mdio_read;
2920 bus->write = mv88e6xxx_mdio_write;
fad09c73 2921 bus->parent = chip->dev;
b516d453 2922
fad09c73
VD		 2923 if (chip->mdio_np)
2924 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2925 else
2926 err = mdiobus_register(bus);
2927 if (err) {
fad09c73 2928 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 2929 goto out;
2930 }
fad09c73 2931 chip->mdio_bus = bus;
b516d453
AL		 2932
2933 return 0;
2934
2935out:
fad09c73
VD		 2936 if (chip->mdio_np)
2937 of_node_put(chip->mdio_np);
b516d453
AL		 2938
2939 return err;
2940}
2941
fad09c73 2942static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2943
2944{
fad09c73 2945 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 2946
2947 mdiobus_unregister(bus);
2948
fad09c73
VD		 2949 if (chip->mdio_np)
2950 of_node_put(chip->mdio_np);
b516d453
AL		 2951}
2952
c22995c5
GR		 2953#ifdef CONFIG_NET_DSA_HWMON
2954
2955static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2956{
04bed143 2957 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 2958 u16 val;
c22995c5 2959 int ret;
c22995c5
GR		 2960
2961 *temp = 0;
2962
fad09c73 2963 mutex_lock(&chip->reg_lock);
c22995c5 2964
9c93829c 2965 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 2966 if (ret < 0)
2967 goto error;
2968
2969 /* Enable temperature sensor */
9c93829c 2970 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 2971 if (ret < 0)
2972 goto error;
2973
9c93829c 2974 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 2975 if (ret < 0)
2976 goto error;
2977
2978 /* Wait for temperature to stabilize */
2979 usleep_range(10000, 12000);
2980
9c93829c
VD		 2981 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
2982 if (ret < 0)
c22995c5 2983 goto error;
c22995c5
GR		 2984
2985 /* Disable temperature sensor */
9c93829c 2986 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 2987 if (ret < 0)
2988 goto error;
2989
2990 *temp = ((val & 0x1f) - 5) * 5;
2991
2992error:
9c93829c 2993 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 2994 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 2995 return ret;
2996}
2997
2998static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2999{
04bed143 3000 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3001 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3002 u16 val;
c22995c5
GR		 3003 int ret;
3004
3005 *temp = 0;
3006
9c93829c
VD		 3007 mutex_lock(&chip->reg_lock);
3008 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3009 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3010 if (ret < 0)
3011 return ret;
3012
9c93829c 3013 *temp = (val & 0xff) - 25;
c22995c5
GR		 3014
3015 return 0;
3016}
3017
f81ec90f 3018static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3019{
04bed143 3020 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3021
fad09c73 3022 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3023 return -EOPNOTSUPP;
3024
fad09c73 3025 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3026 return mv88e63xx_get_temp(ds, temp);
3027
3028 return mv88e61xx_get_temp(ds, temp);
3029}
3030
f81ec90f 3031static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3032{
04bed143 3033 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3034 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3035 u16 val;
c22995c5
GR		 3036 int ret;
3037
fad09c73 3038 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3039 return -EOPNOTSUPP;
3040
3041 *temp = 0;
3042
9c93829c
VD		 3043 mutex_lock(&chip->reg_lock);
3044 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3045 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3046 if (ret < 0)
3047 return ret;
3048
9c93829c 3049 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3050
3051 return 0;
3052}
3053
f81ec90f 3054static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3055{
04bed143 3056 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3057 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3058 u16 val;
3059 int err;
c22995c5 3060
fad09c73 3061 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3062 return -EOPNOTSUPP;
3063
9c93829c
VD		 3064 mutex_lock(&chip->reg_lock);
3065 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3066 if (err)
3067 goto unlock;
c22995c5 3068 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3069 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3070 (val & 0xe0ff) | (temp << 8));
3071unlock:
3072 mutex_unlock(&chip->reg_lock);
3073
3074 return err;
c22995c5
GR		 3075}
3076
f81ec90f 3077static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3078{
04bed143 3079 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3080 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3081 u16 val;
c22995c5
GR		 3082 int ret;
3083
fad09c73 3084 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3085 return -EOPNOTSUPP;
3086
3087 *alarm = false;
3088
9c93829c
VD		 3089 mutex_lock(&chip->reg_lock);
3090 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3091 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3092 if (ret < 0)
3093 return ret;
3094
9c93829c 3095 *alarm = !!(val & 0x40);
c22995c5
GR		 3096
3097 return 0;
3098}
3099#endif /* CONFIG_NET_DSA_HWMON */
3100
855b1932
VD		 3101static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3102{
04bed143 3103 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3104
3105 return chip->eeprom_len;
3106}
3107
855b1932
VD		 3108static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3109 struct ethtool_eeprom *eeprom, u8 *data)
3110{
04bed143 3111 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3112 int err;
3113
ee4dc2e7
VD		 3114 if (!chip->info->ops->get_eeprom)
3115 return -EOPNOTSUPP;
855b1932 3116
ee4dc2e7
VD		 3117 mutex_lock(&chip->reg_lock);
3118 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3119 mutex_unlock(&chip->reg_lock);
3120
3121 if (err)
3122 return err;
3123
3124 eeprom->magic = 0xc3ec4951;
3125
3126 return 0;
3127}
3128
855b1932
VD		 3129static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3130 struct ethtool_eeprom *eeprom, u8 *data)
3131{
04bed143 3132 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3133 int err;
3134
ee4dc2e7
VD		 3135 if (!chip->info->ops->set_eeprom)
3136 return -EOPNOTSUPP;
3137
855b1932
VD		 3138 if (eeprom->magic != 0xc3ec4951)
3139 return -EINVAL;
3140
3141 mutex_lock(&chip->reg_lock);
ee4dc2e7 3142 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3143 mutex_unlock(&chip->reg_lock);
3144
3145 return err;
3146}
3147
b3469dd8 3148static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3149 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3150 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3151 .phy_read = mv88e6xxx_phy_ppu_read,
3152 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3153 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3154 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3155 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3156 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
b3469dd8
VD		 3157};
3158
3159static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3160 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3161 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3162 .phy_read = mv88e6xxx_phy_ppu_read,
3163 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3164 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3165 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3166 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3167 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
b3469dd8
VD		 3168};
3169
3170static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3171 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3172 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3173 .phy_read = mv88e6xxx_read,
3174 .phy_write = mv88e6xxx_write,
08ef7f10 3175 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3176 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3177 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3178 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
b3469dd8
VD		 3179};
3180
3181static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3182 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3183 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3184 .phy_read = mv88e6xxx_phy_ppu_read,
3185 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3186 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3187 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3188 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3189 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
b3469dd8
VD		 3190};
3191
3192static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3193 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3194 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3195 .phy_read = mv88e6xxx_read,
3196 .phy_write = mv88e6xxx_write,
08ef7f10 3197 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3198 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3199 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3200 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
b3469dd8
VD		 3201};
3202
3203static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3204 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3205 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3206 .phy_read = mv88e6xxx_read,
3207 .phy_write = mv88e6xxx_write,
08ef7f10 3208 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3209 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3210 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3211 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
b3469dd8
VD		 3212};
3213
3214static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3215 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3216 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3217 .phy_read = mv88e6xxx_g2_smi_phy_read,
3218 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3219 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3220 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3221 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3222 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3223 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3224};
3225
3226static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3227 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3228 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3229 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3230 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3231 .phy_read = mv88e6xxx_g2_smi_phy_read,
3232 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3233 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3234 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3235 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3236 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3237 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3238};
3239
3240static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3241 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3243 .phy_read = mv88e6xxx_g2_smi_phy_read,
3244 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3245 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3246 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3247 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3248 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3249 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3250};
3251
3252static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3253 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3254 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3255 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3256 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3257 .phy_read = mv88e6xxx_g2_smi_phy_read,
3258 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3259 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3260 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3261 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3262 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3263 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3264};
3265
3266static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3267 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3268 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3269 .phy_read = mv88e6xxx_phy_ppu_read,
3270 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3271 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3272 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3273 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3274 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
b3469dd8
VD		 3275};
3276
1a3b39ec 3277static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3278 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3279 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3280 .phy_read = mv88e6xxx_g2_smi_phy_read,
3281 .phy_write = mv88e6xxx_g2_smi_phy_write,
3282 .port_set_link = mv88e6xxx_port_set_link,
3283 .port_set_duplex = mv88e6xxx_port_set_duplex,
3284 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3285 .port_set_speed = mv88e6390_port_set_speed,
3286};
3287
3288static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3289 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3290 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3291 .phy_read = mv88e6xxx_g2_smi_phy_read,
3292 .phy_write = mv88e6xxx_g2_smi_phy_write,
3293 .port_set_link = mv88e6xxx_port_set_link,
3294 .port_set_duplex = mv88e6xxx_port_set_duplex,
3295 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3296 .port_set_speed = mv88e6390x_port_set_speed,
3297};
3298
3299static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3300 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3302 .phy_read = mv88e6xxx_g2_smi_phy_read,
3303 .phy_write = mv88e6xxx_g2_smi_phy_write,
3304 .port_set_link = mv88e6xxx_port_set_link,
3305 .port_set_duplex = mv88e6xxx_port_set_duplex,
3306 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3307 .port_set_speed = mv88e6390_port_set_speed,
3308};
3309
b3469dd8 3310static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3311 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3312 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3313 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3314 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3315 .phy_read = mv88e6xxx_g2_smi_phy_read,
3316 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3317 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3318 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3319 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3320 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3321 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3322};
3323
1a3b39ec 3324static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3325 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3326 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3327 .phy_read = mv88e6xxx_g2_smi_phy_read,
3328 .phy_write = mv88e6xxx_g2_smi_phy_write,
3329 .port_set_link = mv88e6xxx_port_set_link,
3330 .port_set_duplex = mv88e6xxx_port_set_duplex,
3331 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3332 .port_set_speed = mv88e6390_port_set_speed,
3333};
3334
b3469dd8 3335static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3336 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3337 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3338 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3339 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3340 .phy_read = mv88e6xxx_g2_smi_phy_read,
3341 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3342 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3343 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3344 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3345 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3346};
3347
3348static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3349 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3350 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3351 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3352 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3353 .phy_read = mv88e6xxx_g2_smi_phy_read,
3354 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3355 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3356 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3357 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3358 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3359};
3360
3361static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3362 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3363 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3364 .phy_read = mv88e6xxx_g2_smi_phy_read,
3365 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3366 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3367 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3368 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3369 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3370 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3371};
3372
3373static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3374 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3375 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3376 .phy_read = mv88e6xxx_g2_smi_phy_read,
3377 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3378 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3379 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3380 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3381 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3382 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3383};
3384
3385static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3386 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3387 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3388 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3389 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3390 .phy_read = mv88e6xxx_g2_smi_phy_read,
3391 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3392 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3393 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3394 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3395 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3396 .stats_snapshot = mv88e6320_g1_stats_snapshot,
b3469dd8
VD		 3397};
3398
1a3b39ec 3399static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3400 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3401 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3402 .phy_read = mv88e6xxx_g2_smi_phy_read,
3403 .phy_write = mv88e6xxx_g2_smi_phy_write,
3404 .port_set_link = mv88e6xxx_port_set_link,
3405 .port_set_duplex = mv88e6xxx_port_set_duplex,
3406 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3407 .port_set_speed = mv88e6390_port_set_speed,
3408};
3409
3410static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3411 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3412 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3413 .phy_read = mv88e6xxx_g2_smi_phy_read,
3414 .phy_write = mv88e6xxx_g2_smi_phy_write,
3415 .port_set_link = mv88e6xxx_port_set_link,
3416 .port_set_duplex = mv88e6xxx_port_set_duplex,
3417 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3418 .port_set_speed = mv88e6390x_port_set_speed,
3419};
3420
3421static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3422 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3423 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3424 .phy_read = mv88e6xxx_g2_smi_phy_read,
3425 .phy_write = mv88e6xxx_g2_smi_phy_write,
3426 .port_set_link = mv88e6xxx_port_set_link,
3427 .port_set_duplex = mv88e6xxx_port_set_duplex,
3428 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3429 .port_set_speed = mv88e6390_port_set_speed,
3430};
3431
f81ec90f
VD		 3432static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3433 [MV88E6085] = {
3434 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3435 .family = MV88E6XXX_FAMILY_6097,
3436 .name = "Marvell 88E6085",
3437 .num_databases = 4096,
3438 .num_ports = 10,
9dddd478 3439 .port_base_addr = 0x10,
a935c052 3440 .global1_addr = 0x1b,
acddbd21 3441 .age_time_coeff = 15000,
dc30c35b 3442 .g1_irqs = 8,
f81ec90f 3443 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3444 .ops = &mv88e6085_ops,
f81ec90f
VD		 3445 },
3446
3447 [MV88E6095] = {
3448 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3449 .family = MV88E6XXX_FAMILY_6095,
3450 .name = "Marvell 88E6095/88E6095F",
3451 .num_databases = 256,
3452 .num_ports = 11,
9dddd478 3453 .port_base_addr = 0x10,
a935c052 3454 .global1_addr = 0x1b,
acddbd21 3455 .age_time_coeff = 15000,
dc30c35b 3456 .g1_irqs = 8,
f81ec90f 3457 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3458 .ops = &mv88e6095_ops,
f81ec90f
VD		 3459 },
3460
3461 [MV88E6123] = {
3462 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3463 .family = MV88E6XXX_FAMILY_6165,
3464 .name = "Marvell 88E6123",
3465 .num_databases = 4096,
3466 .num_ports = 3,
9dddd478 3467 .port_base_addr = 0x10,
a935c052 3468 .global1_addr = 0x1b,
acddbd21 3469 .age_time_coeff = 15000,
dc30c35b 3470 .g1_irqs = 9,
f81ec90f 3471 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3472 .ops = &mv88e6123_ops,
f81ec90f
VD		 3473 },
3474
3475 [MV88E6131] = {
3476 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3477 .family = MV88E6XXX_FAMILY_6185,
3478 .name = "Marvell 88E6131",
3479 .num_databases = 256,
3480 .num_ports = 8,
9dddd478 3481 .port_base_addr = 0x10,
a935c052 3482 .global1_addr = 0x1b,
acddbd21 3483 .age_time_coeff = 15000,
dc30c35b 3484 .g1_irqs = 9,
f81ec90f 3485 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3486 .ops = &mv88e6131_ops,
f81ec90f
VD		 3487 },
3488
3489 [MV88E6161] = {
3490 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3491 .family = MV88E6XXX_FAMILY_6165,
3492 .name = "Marvell 88E6161",
3493 .num_databases = 4096,
3494 .num_ports = 6,
9dddd478 3495 .port_base_addr = 0x10,
a935c052 3496 .global1_addr = 0x1b,
acddbd21 3497 .age_time_coeff = 15000,
dc30c35b 3498 .g1_irqs = 9,
f81ec90f 3499 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3500 .ops = &mv88e6161_ops,
f81ec90f
VD		 3501 },
3502
3503 [MV88E6165] = {
3504 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3505 .family = MV88E6XXX_FAMILY_6165,
3506 .name = "Marvell 88E6165",
3507 .num_databases = 4096,
3508 .num_ports = 6,
9dddd478 3509 .port_base_addr = 0x10,
a935c052 3510 .global1_addr = 0x1b,
acddbd21 3511 .age_time_coeff = 15000,
dc30c35b 3512 .g1_irqs = 9,
f81ec90f 3513 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3514 .ops = &mv88e6165_ops,
f81ec90f
VD		 3515 },
3516
3517 [MV88E6171] = {
3518 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3519 .family = MV88E6XXX_FAMILY_6351,
3520 .name = "Marvell 88E6171",
3521 .num_databases = 4096,
3522 .num_ports = 7,
9dddd478 3523 .port_base_addr = 0x10,
a935c052 3524 .global1_addr = 0x1b,
acddbd21 3525 .age_time_coeff = 15000,
dc30c35b 3526 .g1_irqs = 9,
f81ec90f 3527 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3528 .ops = &mv88e6171_ops,
f81ec90f
VD		 3529 },
3530
3531 [MV88E6172] = {
3532 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3533 .family = MV88E6XXX_FAMILY_6352,
3534 .name = "Marvell 88E6172",
3535 .num_databases = 4096,
3536 .num_ports = 7,
9dddd478 3537 .port_base_addr = 0x10,
a935c052 3538 .global1_addr = 0x1b,
acddbd21 3539 .age_time_coeff = 15000,
dc30c35b 3540 .g1_irqs = 9,
f81ec90f 3541 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3542 .ops = &mv88e6172_ops,
f81ec90f
VD		 3543 },
3544
3545 [MV88E6175] = {
3546 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3547 .family = MV88E6XXX_FAMILY_6351,
3548 .name = "Marvell 88E6175",
3549 .num_databases = 4096,
3550 .num_ports = 7,
9dddd478 3551 .port_base_addr = 0x10,
a935c052 3552 .global1_addr = 0x1b,
acddbd21 3553 .age_time_coeff = 15000,
dc30c35b 3554 .g1_irqs = 9,
f81ec90f 3555 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3556 .ops = &mv88e6175_ops,
f81ec90f
VD		 3557 },
3558
3559 [MV88E6176] = {
3560 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3561 .family = MV88E6XXX_FAMILY_6352,
3562 .name = "Marvell 88E6176",
3563 .num_databases = 4096,
3564 .num_ports = 7,
9dddd478 3565 .port_base_addr = 0x10,
a935c052 3566 .global1_addr = 0x1b,
acddbd21 3567 .age_time_coeff = 15000,
dc30c35b 3568 .g1_irqs = 9,
f81ec90f 3569 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3570 .ops = &mv88e6176_ops,
f81ec90f
VD		 3571 },
3572
3573 [MV88E6185] = {
3574 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3575 .family = MV88E6XXX_FAMILY_6185,
3576 .name = "Marvell 88E6185",
3577 .num_databases = 256,
3578 .num_ports = 10,
9dddd478 3579 .port_base_addr = 0x10,
a935c052 3580 .global1_addr = 0x1b,
acddbd21 3581 .age_time_coeff = 15000,
dc30c35b 3582 .g1_irqs = 8,
f81ec90f 3583 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3584 .ops = &mv88e6185_ops,
f81ec90f
VD		 3585 },
3586
1a3b39ec
AL		 3587 [MV88E6190] = {
3588 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3589 .family = MV88E6XXX_FAMILY_6390,
3590 .name = "Marvell 88E6190",
3591 .num_databases = 4096,
3592 .num_ports = 11, /* 10 + Z80 */
3593 .port_base_addr = 0x0,
3594 .global1_addr = 0x1b,
3595 .age_time_coeff = 15000,
3596 .g1_irqs = 9,
3597 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3598 .ops = &mv88e6190_ops,
3599 },
3600
3601 [MV88E6190X] = {
3602 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3603 .family = MV88E6XXX_FAMILY_6390,
3604 .name = "Marvell 88E6190X",
3605 .num_databases = 4096,
3606 .num_ports = 11, /* 10 + Z80 */
3607 .port_base_addr = 0x0,
3608 .global1_addr = 0x1b,
3609 .age_time_coeff = 15000,
3610 .g1_irqs = 9,
3611 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3612 .ops = &mv88e6190x_ops,
3613 },
3614
3615 [MV88E6191] = {
3616 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3617 .family = MV88E6XXX_FAMILY_6390,
3618 .name = "Marvell 88E6191",
3619 .num_databases = 4096,
3620 .num_ports = 11, /* 10 + Z80 */
3621 .port_base_addr = 0x0,
3622 .global1_addr = 0x1b,
3623 .age_time_coeff = 15000,
3624 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3625 .ops = &mv88e6391_ops,
3626 },
3627
f81ec90f
VD		 3628 [MV88E6240] = {
3629 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3630 .family = MV88E6XXX_FAMILY_6352,
3631 .name = "Marvell 88E6240",
3632 .num_databases = 4096,
3633 .num_ports = 7,
9dddd478 3634 .port_base_addr = 0x10,
a935c052 3635 .global1_addr = 0x1b,
acddbd21 3636 .age_time_coeff = 15000,
dc30c35b 3637 .g1_irqs = 9,
f81ec90f 3638 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3639 .ops = &mv88e6240_ops,
f81ec90f
VD		 3640 },
3641
1a3b39ec
AL		 3642 [MV88E6290] = {
3643 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3644 .family = MV88E6XXX_FAMILY_6390,
3645 .name = "Marvell 88E6290",
3646 .num_databases = 4096,
3647 .num_ports = 11, /* 10 + Z80 */
3648 .port_base_addr = 0x0,
3649 .global1_addr = 0x1b,
3650 .age_time_coeff = 15000,
3651 .g1_irqs = 9,
3652 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3653 .ops = &mv88e6290_ops,
3654 },
3655
f81ec90f
VD		 3656 [MV88E6320] = {
3657 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3658 .family = MV88E6XXX_FAMILY_6320,
3659 .name = "Marvell 88E6320",
3660 .num_databases = 4096,
3661 .num_ports = 7,
9dddd478 3662 .port_base_addr = 0x10,
a935c052 3663 .global1_addr = 0x1b,
acddbd21 3664 .age_time_coeff = 15000,
dc30c35b 3665 .g1_irqs = 8,
f81ec90f 3666 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3667 .ops = &mv88e6320_ops,
f81ec90f
VD		 3668 },
3669
3670 [MV88E6321] = {
3671 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3672 .family = MV88E6XXX_FAMILY_6320,
3673 .name = "Marvell 88E6321",
3674 .num_databases = 4096,
3675 .num_ports = 7,
9dddd478 3676 .port_base_addr = 0x10,
a935c052 3677 .global1_addr = 0x1b,
acddbd21 3678 .age_time_coeff = 15000,
dc30c35b 3679 .g1_irqs = 8,
f81ec90f 3680 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3681 .ops = &mv88e6321_ops,
f81ec90f
VD		 3682 },
3683
3684 [MV88E6350] = {
3685 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3686 .family = MV88E6XXX_FAMILY_6351,
3687 .name = "Marvell 88E6350",
3688 .num_databases = 4096,
3689 .num_ports = 7,
9dddd478 3690 .port_base_addr = 0x10,
a935c052 3691 .global1_addr = 0x1b,
acddbd21 3692 .age_time_coeff = 15000,
dc30c35b 3693 .g1_irqs = 9,
f81ec90f 3694 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3695 .ops = &mv88e6350_ops,
f81ec90f
VD		 3696 },
3697
3698 [MV88E6351] = {
3699 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3700 .family = MV88E6XXX_FAMILY_6351,
3701 .name = "Marvell 88E6351",
3702 .num_databases = 4096,
3703 .num_ports = 7,
9dddd478 3704 .port_base_addr = 0x10,
a935c052 3705 .global1_addr = 0x1b,
acddbd21 3706 .age_time_coeff = 15000,
dc30c35b 3707 .g1_irqs = 9,
f81ec90f 3708 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3709 .ops = &mv88e6351_ops,
f81ec90f
VD		 3710 },
3711
3712 [MV88E6352] = {
3713 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3714 .family = MV88E6XXX_FAMILY_6352,
3715 .name = "Marvell 88E6352",
3716 .num_databases = 4096,
3717 .num_ports = 7,
9dddd478 3718 .port_base_addr = 0x10,
a935c052 3719 .global1_addr = 0x1b,
acddbd21 3720 .age_time_coeff = 15000,
dc30c35b 3721 .g1_irqs = 9,
f81ec90f 3722 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3723 .ops = &mv88e6352_ops,
f81ec90f 3724 },
1a3b39ec
AL		 3725 [MV88E6390] = {
3726 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3727 .family = MV88E6XXX_FAMILY_6390,
3728 .name = "Marvell 88E6390",
3729 .num_databases = 4096,
3730 .num_ports = 11, /* 10 + Z80 */
3731 .port_base_addr = 0x0,
3732 .global1_addr = 0x1b,
3733 .age_time_coeff = 15000,
3734 .g1_irqs = 9,
3735 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3736 .ops = &mv88e6390_ops,
3737 },
3738 [MV88E6390X] = {
3739 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3740 .family = MV88E6XXX_FAMILY_6390,
3741 .name = "Marvell 88E6390X",
3742 .num_databases = 4096,
3743 .num_ports = 11, /* 10 + Z80 */
3744 .port_base_addr = 0x0,
3745 .global1_addr = 0x1b,
3746 .age_time_coeff = 15000,
3747 .g1_irqs = 9,
3748 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3749 .ops = &mv88e6390x_ops,
3750 },
f81ec90f
VD		 3751};
3752
5f7c0367 3753static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3754{
a439c061 3755 int i;
b9b37713 3756
5f7c0367
VD		 3757 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3758 if (mv88e6xxx_table[i].prod_num == prod_num)
3759 return &mv88e6xxx_table[i];
b9b37713 3760
b9b37713
VD		 3761 return NULL;
3762}
3763
fad09c73 3764static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3765{
3766 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3767 unsigned int prod_num, rev;
3768 u16 id;
3769 int err;
bc46a3d5 3770
8f6345b2
VD		 3771 mutex_lock(&chip->reg_lock);
3772 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3773 mutex_unlock(&chip->reg_lock);
3774 if (err)
3775 return err;
bc46a3d5
VD		 3776
3777 prod_num = (id & 0xfff0) >> 4;
3778 rev = id & 0x000f;
3779
3780 info = mv88e6xxx_lookup_info(prod_num);
3781 if (!info)
3782 return -ENODEV;
3783
caac8545 3784 /* Update the compatible info with the probed one */
fad09c73 3785 chip->info = info;
bc46a3d5 3786
ca070c10
VD		 3787 err = mv88e6xxx_g2_require(chip);
3788 if (err)
3789 return err;
3790
fad09c73
VD		 3791 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3792 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3793
3794 return 0;
3795}
3796
fad09c73 3797static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3798{
fad09c73 3799 struct mv88e6xxx_chip *chip;
469d729f 3800
fad09c73
VD		 3801 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3802 if (!chip)
469d729f
VD		 3803 return NULL;
3804
fad09c73 3805 chip->dev = dev;
469d729f 3806
fad09c73 3807 mutex_init(&chip->reg_lock);
469d729f 3808
fad09c73 3809 return chip;
469d729f
VD		 3810}
3811
e57e5e77
VD		 3812static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3813{
b3469dd8 3814 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
e57e5e77 3815 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 3816}
3817
930188ce
AL		 3818static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3819{
b3469dd8 3820 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
930188ce 3821 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 3822}
3823
fad09c73 3824static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3825 struct mii_bus *bus, int sw_addr)
3826{
3827 /* ADDR[0] pin is unavailable externally and considered zero */
3828 if (sw_addr & 0x1)
3829 return -EINVAL;
3830
914b32f6 3831 if (sw_addr == 0)
fad09c73 3832 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3833 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3834 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3835 else
3836 return -EINVAL;
3837
fad09c73
VD		 3838 chip->bus = bus;
3839 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3840
3841 return 0;
3842}
3843
7b314362
AL		 3844static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3845{
04bed143 3846 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be
AL		 3847
3848 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3849 return DSA_TAG_PROTO_EDSA;
3850
3851 return DSA_TAG_PROTO_DSA;
7b314362
AL		 3852}
3853
fcdce7d0
AL		 3854static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3855 struct device *host_dev, int sw_addr,
3856 void **priv)
a77d43f1 3857{
fad09c73 3858 struct mv88e6xxx_chip *chip;
a439c061 3859 struct mii_bus *bus;
b516d453 3860 int err;
a77d43f1 3861
a439c061 3862 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3863 if (!bus)
3864 return NULL;
3865
fad09c73
VD		 3866 chip = mv88e6xxx_alloc_chip(dsa_dev);
3867 if (!chip)
469d729f
VD		 3868 return NULL;
3869
caac8545 3870 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3871 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3872
fad09c73 3873 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3874 if (err)
3875 goto free;
3876
fad09c73 3877 err = mv88e6xxx_detect(chip);
bc46a3d5 3878 if (err)
469d729f 3879 goto free;
a439c061 3880
dc30c35b
AL		 3881 mutex_lock(&chip->reg_lock);
3882 err = mv88e6xxx_switch_reset(chip);
3883 mutex_unlock(&chip->reg_lock);
3884 if (err)
3885 goto free;
3886
e57e5e77
VD		 3887 mv88e6xxx_phy_init(chip);
3888
fad09c73 3889 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3890 if (err)
469d729f 3891 goto free;
b516d453 3892
fad09c73 3893 *priv = chip;
a439c061 3894
fad09c73 3895 return chip->info->name;
469d729f 3896free:
fad09c73 3897 devm_kfree(dsa_dev, chip);
469d729f
VD		 3898
3899 return NULL;
a77d43f1
AL		 3900}
3901
7df8fbdd
VD		 3902static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3903 const struct switchdev_obj_port_mdb *mdb,
3904 struct switchdev_trans *trans)
3905{
3906 /* We don't need any dynamic resource from the kernel (yet),
3907 * so skip the prepare phase.
3908 */
3909
3910 return 0;
3911}
3912
3913static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3914 const struct switchdev_obj_port_mdb *mdb,
3915 struct switchdev_trans *trans)
3916{
04bed143 3917 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3918
3919 mutex_lock(&chip->reg_lock);
3920 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3921 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3922 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3923 mutex_unlock(&chip->reg_lock);
3924}
3925
3926static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3927 const struct switchdev_obj_port_mdb *mdb)
3928{
04bed143 3929 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3930 int err;
3931
3932 mutex_lock(&chip->reg_lock);
3933 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3934 GLOBAL_ATU_DATA_STATE_UNUSED);
3935 mutex_unlock(&chip->reg_lock);
3936
3937 return err;
3938}
3939
3940static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3941 struct switchdev_obj_port_mdb *mdb,
3942 int (*cb)(struct switchdev_obj *obj))
3943{
04bed143 3944 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3945 int err;
3946
3947 mutex_lock(&chip->reg_lock);
3948 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3949 mutex_unlock(&chip->reg_lock);
3950
3951 return err;
3952}
3953
9d490b4e 3954static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3955 .probe = mv88e6xxx_drv_probe,
7b314362 3956 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3957 .setup = mv88e6xxx_setup,
3958 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3959 .adjust_link = mv88e6xxx_adjust_link,
3960 .get_strings = mv88e6xxx_get_strings,
3961 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3962 .get_sset_count = mv88e6xxx_get_sset_count,
3963 .set_eee = mv88e6xxx_set_eee,
3964 .get_eee = mv88e6xxx_get_eee,
3965#ifdef CONFIG_NET_DSA_HWMON
3966 .get_temp = mv88e6xxx_get_temp,
3967 .get_temp_limit = mv88e6xxx_get_temp_limit,
3968 .set_temp_limit = mv88e6xxx_set_temp_limit,
3969 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3970#endif
f8cd8753 3971 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3972 .get_eeprom = mv88e6xxx_get_eeprom,
3973 .set_eeprom = mv88e6xxx_set_eeprom,
3974 .get_regs_len = mv88e6xxx_get_regs_len,
3975 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3976 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3977 .port_bridge_join = mv88e6xxx_port_bridge_join,
3978 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3979 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3980 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3981 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3982 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3983 .port_vlan_add = mv88e6xxx_port_vlan_add,
3984 .port_vlan_del = mv88e6xxx_port_vlan_del,
3985 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3986 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3987 .port_fdb_add = mv88e6xxx_port_fdb_add,
3988 .port_fdb_del = mv88e6xxx_port_fdb_del,
3989 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3990 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3991 .port_mdb_add = mv88e6xxx_port_mdb_add,
3992 .port_mdb_del = mv88e6xxx_port_mdb_del,
3993 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 3994};
3995
fad09c73 3996static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3997 struct device_node *np)
3998{
fad09c73 3999 struct device *dev = chip->dev;
b7e66a5f
VD		 4000 struct dsa_switch *ds;
4001
4002 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4003 if (!ds)
4004 return -ENOMEM;
4005
4006 ds->dev = dev;
fad09c73 4007 ds->priv = chip;
9d490b4e 4008 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4009
4010 dev_set_drvdata(dev, ds);
4011
4012 return dsa_register_switch(ds, np);
4013}
4014
fad09c73 4015static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4016{
fad09c73 4017 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4018}
4019
57d32310 4020static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4021{
14c7b3c3 4022 struct device *dev = &mdiodev->dev;
f8cd8753 4023 struct device_node *np = dev->of_node;
caac8545 4024 const struct mv88e6xxx_info *compat_info;
fad09c73 4025 struct mv88e6xxx_chip *chip;
f8cd8753 4026 u32 eeprom_len;
52638f71 4027 int err;
14c7b3c3 4028
caac8545
VD		 4029 compat_info = of_device_get_match_data(dev);
4030 if (!compat_info)
4031 return -EINVAL;
4032
fad09c73
VD		 4033 chip = mv88e6xxx_alloc_chip(dev);
4034 if (!chip)
14c7b3c3
AL		 4035 return -ENOMEM;
4036
fad09c73 4037 chip->info = compat_info;
caac8545 4038
fad09c73 4039 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4040 if (err)
4041 return err;
14c7b3c3 4042
b4308f04
AL		 4043 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4044 if (IS_ERR(chip->reset))
4045 return PTR_ERR(chip->reset);
4046
fad09c73 4047 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4048 if (err)
4049 return err;
14c7b3c3 4050
e57e5e77
VD		 4051 mv88e6xxx_phy_init(chip);
4052
ee4dc2e7 4053 if (chip->info->ops->get_eeprom &&
f8cd8753 4054 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4055 chip->eeprom_len = eeprom_len;
f8cd8753 4056
dc30c35b
AL		 4057 mutex_lock(&chip->reg_lock);
4058 err = mv88e6xxx_switch_reset(chip);
4059 mutex_unlock(&chip->reg_lock);
4060 if (err)
4061 goto out;
4062
4063 chip->irq = of_irq_get(np, 0);
4064 if (chip->irq == -EPROBE_DEFER) {
4065 err = chip->irq;
4066 goto out;
4067 }
4068
4069 if (chip->irq > 0) {
4070 /* Has to be performed before the MDIO bus is created,
4071 * because the PHYs will link there interrupts to these
4072 * interrupt controllers
4073 */
4074 mutex_lock(&chip->reg_lock);
4075 err = mv88e6xxx_g1_irq_setup(chip);
4076 mutex_unlock(&chip->reg_lock);
4077
4078 if (err)
4079 goto out;
4080
4081 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4082 err = mv88e6xxx_g2_irq_setup(chip);
4083 if (err)
4084 goto out_g1_irq;
4085 }
4086 }
4087
fad09c73 4088 err = mv88e6xxx_mdio_register(chip, np);
b516d453 4089 if (err)
dc30c35b 4090 goto out_g2_irq;
b516d453 4091
fad09c73 4092 err = mv88e6xxx_register_switch(chip, np);
dc30c35b
AL		 4093 if (err)
4094 goto out_mdio;
83c0afae 4095
98e67308 4096 return 0;
dc30c35b
AL		 4097
4098out_mdio:
4099 mv88e6xxx_mdio_unregister(chip);
4100out_g2_irq:
46712644 4101 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4102 mv88e6xxx_g2_irq_free(chip);
4103out_g1_irq:
61f7c3f8
AL		 4104 if (chip->irq > 0) {
4105 mutex_lock(&chip->reg_lock);
46712644 4106 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4107 mutex_unlock(&chip->reg_lock);
4108 }
dc30c35b
AL		 4109out:
4110 return err;
98e67308 4111}
14c7b3c3
AL		 4112
4113static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4114{
4115 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4116 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4117
930188ce 4118 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 4119 mv88e6xxx_unregister_switch(chip);
4120 mv88e6xxx_mdio_unregister(chip);
dc30c35b 4121
46712644
AL		 4122 if (chip->irq > 0) {
4123 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4124 mv88e6xxx_g2_irq_free(chip);
4125 mv88e6xxx_g1_irq_free(chip);
4126 }
14c7b3c3
AL		 4127}
4128
4129static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4130 {
4131 .compatible = "marvell,mv88e6085",
4132 .data = &mv88e6xxx_table[MV88E6085],
4133 },
1a3b39ec
AL		 4134 {
4135 .compatible = "marvell,mv88e6190",
4136 .data = &mv88e6xxx_table[MV88E6190],
4137 },
14c7b3c3
AL		 4138 { /* sentinel */ },
4139};
4140
4141MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4142
4143static struct mdio_driver mv88e6xxx_driver = {
4144 .probe = mv88e6xxx_probe,
4145 .remove = mv88e6xxx_remove,
4146 .mdiodrv.driver = {
4147 .name = "mv88e6085",
4148 .of_match_table = mv88e6xxx_of_match,
4149 },
4150};
4151
4152static int __init mv88e6xxx_init(void)
4153{
9d490b4e 4154 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 4155 return mdio_driver_register(&mv88e6xxx_driver);
4156}
98e67308
BH		 4157module_init(mv88e6xxx_init);
4158
4159static void __exit mv88e6xxx_cleanup(void)
4160{
14c7b3c3 4161 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 4162 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 4163}
4164module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4165
4166MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4167MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4168MODULE_LICENSE("GPL");
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