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[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
e57e5e77
VD		 225static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227{
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
b3469dd8 230 if (!chip->info->ops->phy_read)
e57e5e77
VD		 231 return -EOPNOTSUPP;
232
b3469dd8 233 return chip->info->ops->phy_read(chip, addr, reg, val);
e57e5e77
VD		 234}
235
236static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
b3469dd8 241 if (!chip->info->ops->phy_write)
e57e5e77
VD		 242 return -EOPNOTSUPP;
243
b3469dd8 244 return chip->info->ops->phy_write(chip, addr, reg, val);
e57e5e77
VD		 245}
246
09cb7dfd
VD		 247static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248{
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253}
254
255static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256{
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265}
266
267static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269{
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283}
284
285static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287{
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301}
302
303static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304{
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
309static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310{
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313}
314
dc30c35b
AL		 315static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316{
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321}
322
323static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324{
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329}
330
331static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332{
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356}
357
358static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359{
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363}
364
365static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366{
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383out:
384 mutex_unlock(&chip->reg_lock);
385}
386
387static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393};
394
395static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398{
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406}
407
408static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411};
412
413static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414{
415 int irq, virq;
3460a577
AL		 416 u16 mask;
417
418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
419 mask |= GENMASK(chip->g1_irq.nirqs, 0);
420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
421
422 free_irq(chip->irq, chip);
dc30c35b
AL		 423
424 for (irq = 0; irq < 16; irq++) {
a3db3d3a 425 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 426 irq_dispose_mapping(virq);
427 }
428
a3db3d3a 429 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 430}
431
432static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
433{
3dd0ef05
AL		 434 int err, irq, virq;
435 u16 reg, mask;
dc30c35b
AL		 436
437 chip->g1_irq.nirqs = chip->info->g1_irqs;
438 chip->g1_irq.domain = irq_domain_add_simple(
439 NULL, chip->g1_irq.nirqs, 0,
440 &mv88e6xxx_g1_irq_domain_ops, chip);
441 if (!chip->g1_irq.domain)
442 return -ENOMEM;
443
444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
445 irq_create_mapping(chip->g1_irq.domain, irq);
446
447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
448 chip->g1_irq.masked = ~0;
449
3dd0ef05 450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 451 if (err)
3dd0ef05 452 goto out_mapping;
dc30c35b 453
3dd0ef05 454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 455
3dd0ef05 456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 457 if (err)
3dd0ef05 458 goto out_disable;
dc30c35b
AL		 459
460 /* Reading the interrupt status clears (most of) them */
461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
462 if (err)
3dd0ef05 463 goto out_disable;
dc30c35b
AL		 464
465 err = request_threaded_irq(chip->irq, NULL,
466 mv88e6xxx_g1_irq_thread_fn,
467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
468 dev_name(chip->dev), chip);
469 if (err)
3dd0ef05 470 goto out_disable;
dc30c35b
AL		 471
472 return 0;
473
3dd0ef05
AL		 474out_disable:
475 mask |= GENMASK(chip->g1_irq.nirqs, 0);
476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
477
478out_mapping:
479 for (irq = 0; irq < 16; irq++) {
480 virq = irq_find_mapping(chip->g1_irq.domain, irq);
481 irq_dispose_mapping(virq);
482 }
483
484 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 485
486 return err;
487}
488
ec561276 489int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 490{
6441e669 491 int i;
2d79af6e 492
6441e669 493 for (i = 0; i < 16; i++) {
2d79af6e
VD		 494 u16 val;
495 int err;
496
497 err = mv88e6xxx_read(chip, addr, reg, &val);
498 if (err)
499 return err;
500
501 if (!(val & mask))
502 return 0;
503
504 usleep_range(1000, 2000);
505 }
506
30853553 507 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 508 return -ETIMEDOUT;
509}
510
f22ab641 511/* Indirect write to single pointer-data register with an Update bit */
ec561276 512int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 513{
514 u16 val;
0f02b4f7 515 int err;
f22ab641
VD		 516
517 /* Wait until the previous operation is completed */
0f02b4f7
AL		 518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
519 if (err)
520 return err;
f22ab641
VD		 521
522 /* Set the Update bit to trigger a write operation */
523 val = BIT(15) | update;
524
525 return mv88e6xxx_write(chip, addr, reg, val);
526}
527
a935c052 528static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6
VD		 529{
530 u16 val;
a935c052 531 int i, err;
914b32f6 532
a935c052 533 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
914b32f6
VD		 534 if (err)
535 return err;
536
a935c052
VD		 537 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
538 val & ~GLOBAL_CONTROL_PPU_ENABLE);
539 if (err)
540 return err;
2e5f0320 541
6441e669 542 for (i = 0; i < 16; i++) {
a935c052
VD		 543 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
544 if (err)
545 return err;
48ace4ef 546
19b2f97e 547 usleep_range(1000, 2000);
a935c052 548 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
85686581 549 return 0;
2e5f0320
LB		 550 }
551
552 return -ETIMEDOUT;
553}
554
fad09c73 555static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 556{
a935c052
VD		 557 u16 val;
558 int i, err;
2e5f0320 559
a935c052
VD		 560 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
561 if (err)
562 return err;
48ace4ef 563
a935c052
VD		 564 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
565 val | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 566 if (err)
567 return err;
2e5f0320 568
6441e669 569 for (i = 0; i < 16; i++) {
a935c052
VD		 570 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
571 if (err)
572 return err;
48ace4ef 573
19b2f97e 574 usleep_range(1000, 2000);
a935c052 575 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
85686581 576 return 0;
2e5f0320
LB		 577 }
578
579 return -ETIMEDOUT;
580}
581
582static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
583{
fad09c73 584 struct mv88e6xxx_chip *chip;
2e5f0320 585
fad09c73 586 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 587
fad09c73 588 mutex_lock(&chip->reg_lock);
762eb67b 589
fad09c73
VD		 590 if (mutex_trylock(&chip->ppu_mutex)) {
591 if (mv88e6xxx_ppu_enable(chip) == 0)
592 chip->ppu_disabled = 0;
593 mutex_unlock(&chip->ppu_mutex);
2e5f0320 594 }
762eb67b 595
fad09c73 596 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 597}
598
599static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
600{
fad09c73 601 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 602
fad09c73 603 schedule_work(&chip->ppu_work);
2e5f0320
LB		 604}
605
fad09c73 606static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 607{
2e5f0320
LB		 608 int ret;
609
fad09c73 610 mutex_lock(&chip->ppu_mutex);
2e5f0320 611
3675c8d7 612 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 613 * we can access the PHY registers. If it was already
614 * disabled, cancel the timer that is going to re-enable
615 * it.
616 */
fad09c73
VD		 617 if (!chip->ppu_disabled) {
618 ret = mv88e6xxx_ppu_disable(chip);
85686581 619 if (ret < 0) {
fad09c73 620 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 621 return ret;
622 }
fad09c73 623 chip->ppu_disabled = 1;
2e5f0320 624 } else {
fad09c73 625 del_timer(&chip->ppu_timer);
85686581 626 ret = 0;
2e5f0320
LB		 627 }
628
629 return ret;
630}
631
fad09c73 632static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 633{
3675c8d7 634 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 635 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
636 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 637}
638
fad09c73 639static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 640{
fad09c73
VD		 641 mutex_init(&chip->ppu_mutex);
642 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 643 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
644 (unsigned long)chip);
2e5f0320
LB		 645}
646
930188ce
AL		 647static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
648{
649 del_timer_sync(&chip->ppu_timer);
650}
651
e57e5e77
VD		 652static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
653 int reg, u16 *val)
2e5f0320 654{
e57e5e77 655 int err;
2e5f0320 656
e57e5e77
VD		 657 err = mv88e6xxx_ppu_access_get(chip);
658 if (!err) {
659 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 660 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 661 }
662
e57e5e77 663 return err;
2e5f0320
LB		 664}
665
e57e5e77
VD		 666static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
667 int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 693}
694
fad09c73 695static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 696{
fad09c73 697 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 698}
699
fad09c73 700static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 703}
704
fad09c73 705static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 708}
709
fad09c73 710static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 711{
fad09c73 712 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 713}
714
fad09c73 715static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 716{
fad09c73 717 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 718}
719
d78343d2
VD		 720static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
721 int link, int speed, int duplex,
722 phy_interface_t mode)
723{
724 int err;
725
726 if (!chip->info->ops->port_set_link)
727 return 0;
728
729 /* Port's MAC control must not be changed unless the link is down */
730 err = chip->info->ops->port_set_link(chip, port, 0);
731 if (err)
732 return err;
733
734 if (chip->info->ops->port_set_speed) {
735 err = chip->info->ops->port_set_speed(chip, port, speed);
736 if (err && err != -EOPNOTSUPP)
737 goto restore_link;
738 }
739
740 if (chip->info->ops->port_set_duplex) {
741 err = chip->info->ops->port_set_duplex(chip, port, duplex);
742 if (err && err != -EOPNOTSUPP)
743 goto restore_link;
744 }
745
746 if (chip->info->ops->port_set_rgmii_delay) {
747 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
748 if (err && err != -EOPNOTSUPP)
749 goto restore_link;
750 }
751
752 err = 0;
753restore_link:
754 if (chip->info->ops->port_set_link(chip, port, link))
755 netdev_err(chip->ds->ports[port].netdev,
756 "failed to restore MAC's link\n");
757
758 return err;
759}
760
dea87024
AL		 761/* We expect the switch to perform auto negotiation if there is a real
762 * phy. However, in the case of a fixed link phy, we force the port
763 * settings from the fixed link settings.
764 */
f81ec90f
VD		 765static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
766 struct phy_device *phydev)
dea87024 767{
04bed143 768 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 769 int err;
dea87024
AL		 770
771 if (!phy_is_pseudo_fixed_link(phydev))
772 return;
773
fad09c73 774 mutex_lock(&chip->reg_lock);
d78343d2
VD		 775 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
776 phydev->duplex, phydev->interface);
fad09c73 777 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 778
779 if (err && err != -EOPNOTSUPP)
780 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 781}
782
a605a0fe 783static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 784{
a605a0fe
AL		 785 if (!chip->info->ops->stats_snapshot)
786 return -EOPNOTSUPP;
91da11f8 787
a605a0fe 788 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 789}
790
e413e7e1 791static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 792 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
793 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
794 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
795 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
796 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
797 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
798 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
799 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
800 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
801 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
802 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
803 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
804 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
805 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
806 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
807 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
808 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
809 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
810 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
811 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
812 { "single", 4, 0x14, STATS_TYPE_BANK0, },
813 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
814 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
815 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
816 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
817 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
818 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
819 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
820 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
821 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
822 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
823 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
824 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
825 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
826 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
827 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
828 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
829 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
830 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
831 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
832 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
833 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
834 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
835 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
836 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
837 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
838 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
839 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
840 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
841 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
842 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
843 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
844 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
845 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
846 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
847 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
848 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
849 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
850 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 851};
852
fad09c73 853static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 854 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 855 int port, u16 bank1_select,
856 u16 histogram)
80c4627b 857{
80c4627b
AL		 858 u32 low;
859 u32 high = 0;
dfafe449 860 u16 reg = 0;
0e7b9925 861 int err;
80c4627b
AL		 862 u64 value;
863
f5e2ed02 864 switch (s->type) {
dfafe449 865 case STATS_TYPE_PORT:
0e7b9925
AL		 866 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
867 if (err)
80c4627b
AL		 868 return UINT64_MAX;
869
0e7b9925 870 low = reg;
80c4627b 871 if (s->sizeof_stat == 4) {
0e7b9925
AL		 872 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
873 if (err)
80c4627b 874 return UINT64_MAX;
0e7b9925 875 high = reg;
80c4627b 876 }
f5e2ed02 877 break;
dfafe449 878 case STATS_TYPE_BANK1:
e0d8b615 879 reg = bank1_select;
dfafe449
AL		 880 /* fall through */
881 case STATS_TYPE_BANK0:
e0d8b615 882 reg |= s->reg | histogram;
7f9ef3af 883 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 884 if (s->sizeof_stat == 8)
7f9ef3af 885 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 886 }
887 value = (((u64)high) << 16) | low;
888 return value;
889}
890
dfafe449
AL		 891static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
892 uint8_t *data, int types)
91da11f8 893{
f5e2ed02
AL		 894 struct mv88e6xxx_hw_stat *stat;
895 int i, j;
91da11f8 896
f5e2ed02
AL		 897 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
898 stat = &mv88e6xxx_hw_stats[i];
dfafe449 899 if (stat->type & types) {
f5e2ed02
AL		 900 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
901 ETH_GSTRING_LEN);
902 j++;
903 }
91da11f8 904 }
e413e7e1
AL		 905}
906
dfafe449
AL		 907static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
908 uint8_t *data)
909{
910 mv88e6xxx_stats_get_strings(chip, data,
911 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
912}
913
914static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
915 uint8_t *data)
916{
917 mv88e6xxx_stats_get_strings(chip, data,
918 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
919}
920
921static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
922 uint8_t *data)
e413e7e1 923{
04bed143 924 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 925
926 if (chip->info->ops->stats_get_strings)
927 chip->info->ops->stats_get_strings(chip, data);
928}
929
930static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
931 int types)
932{
f5e2ed02
AL		 933 struct mv88e6xxx_hw_stat *stat;
934 int i, j;
935
936 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
937 stat = &mv88e6xxx_hw_stats[i];
dfafe449 938 if (stat->type & types)
f5e2ed02
AL		 939 j++;
940 }
941 return j;
e413e7e1
AL		 942}
943
dfafe449
AL		 944static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
945{
946 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
947 STATS_TYPE_PORT);
948}
949
950static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
951{
952 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
953 STATS_TYPE_BANK1);
954}
955
956static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
957{
958 struct mv88e6xxx_chip *chip = ds->priv;
959
960 if (chip->info->ops->stats_get_sset_count)
961 return chip->info->ops->stats_get_sset_count(chip);
962
963 return 0;
964}
965
052f947f 966static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 967 uint64_t *data, int types,
968 u16 bank1_select, u16 histogram)
052f947f
AL		 969{
970 struct mv88e6xxx_hw_stat *stat;
971 int i, j;
972
973 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
974 stat = &mv88e6xxx_hw_stats[i];
975 if (stat->type & types) {
e0d8b615
AL		 976 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
977 bank1_select,
978 histogram);
052f947f
AL		 979 j++;
980 }
981 }
982}
983
984static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
985 uint64_t *data)
986{
987 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 988 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
989 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 990}
991
992static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
993 uint64_t *data)
994{
995 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
997 GLOBAL_STATS_OP_BANK_1_BIT_9,
998 GLOBAL_STATS_OP_HIST_RX_TX);
999}
1000
1001static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1002 uint64_t *data)
1003{
1004 return mv88e6xxx_stats_get_stats(chip, port, data,
1005 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1006 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1007}
1008
1009static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1010 uint64_t *data)
1011{
1012 if (chip->info->ops->stats_get_stats)
1013 chip->info->ops->stats_get_stats(chip, port, data);
1014}
1015
f81ec90f
VD		 1016static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1017 uint64_t *data)
e413e7e1 1018{
04bed143 1019 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1020 int ret;
f5e2ed02 1021
fad09c73 1022 mutex_lock(&chip->reg_lock);
f5e2ed02 1023
a605a0fe 1024 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1025 if (ret < 0) {
fad09c73 1026 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1027 return;
1028 }
052f947f
AL		 1029
1030 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1031
fad09c73 1032 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1033}
1034
de227387
AL		 1035static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1036{
1037 if (chip->info->ops->stats_set_histogram)
1038 return chip->info->ops->stats_set_histogram(chip);
1039
1040 return 0;
1041}
1042
f81ec90f 1043static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1044{
1045 return 32 * sizeof(u16);
1046}
1047
f81ec90f
VD		 1048static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1049 struct ethtool_regs *regs, void *_p)
a1ab91f3 1050{
04bed143 1051 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1052 int err;
1053 u16 reg;
a1ab91f3
GR		 1054 u16 *p = _p;
1055 int i;
1056
1057 regs->version = 0;
1058
1059 memset(p, 0xff, 32 * sizeof(u16));
1060
fad09c73 1061 mutex_lock(&chip->reg_lock);
23062513 1062
a1ab91f3 1063 for (i = 0; i < 32; i++) {
a1ab91f3 1064
0e7b9925
AL		 1065 err = mv88e6xxx_port_read(chip, port, i, &reg);
1066 if (!err)
1067 p[i] = reg;
a1ab91f3 1068 }
23062513 1069
fad09c73 1070 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1071}
1072
fad09c73 1073static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1074{
a935c052 1075 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1076}
1077
f81ec90f
VD		 1078static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1079 struct ethtool_eee *e)
11b3b45d 1080{
04bed143 1081 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1082 u16 reg;
1083 int err;
11b3b45d 1084
fad09c73 1085 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1086 return -EOPNOTSUPP;
1087
fad09c73 1088 mutex_lock(&chip->reg_lock);
2f40c698 1089
9c93829c
VD		 1090 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1091 if (err)
2f40c698 1092 goto out;
11b3b45d
GR		 1093
1094 e->eee_enabled = !!(reg & 0x0200);
1095 e->tx_lpi_enabled = !!(reg & 0x0100);
1096
0e7b9925 1097 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1098 if (err)
2f40c698 1099 goto out;
11b3b45d 1100
cca8b133 1101 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1102out:
fad09c73 1103 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1104
1105 return err;
11b3b45d
GR		 1106}
1107
f81ec90f
VD		 1108static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1109 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1110{
04bed143 1111 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1112 u16 reg;
1113 int err;
11b3b45d 1114
fad09c73 1115 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1116 return -EOPNOTSUPP;
1117
fad09c73 1118 mutex_lock(&chip->reg_lock);
11b3b45d 1119
9c93829c
VD		 1120 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1121 if (err)
2f40c698
AL		 1122 goto out;
1123
9c93829c 1124 reg &= ~0x0300;
2f40c698
AL		 1125 if (e->eee_enabled)
1126 reg |= 0x0200;
1127 if (e->tx_lpi_enabled)
1128 reg |= 0x0100;
1129
9c93829c 1130 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1131out:
fad09c73 1132 mutex_unlock(&chip->reg_lock);
2f40c698 1133
9c93829c 1134 return err;
11b3b45d
GR		 1135}
1136
fad09c73 1137static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1138{
a935c052
VD		 1139 u16 val;
1140 int err;
facd95b2 1141
6dc10bbc 1142 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1143 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1144 if (err)
1145 return err;
fad09c73 1146 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1147 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1148 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1149 if (err)
1150 return err;
11ea809f 1151
a935c052
VD		 1152 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1153 (val & 0xfff) | ((fid << 8) & 0xf000));
1154 if (err)
1155 return err;
11ea809f
VD		 1156
1157 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1158 cmd |= fid & 0xf;
b426e5f7
VD		 1159 }
1160
a935c052
VD		 1161 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1162 if (err)
1163 return err;
facd95b2 1164
fad09c73 1165 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1166}
1167
fad09c73 1168static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1169 struct mv88e6xxx_atu_entry *entry)
1170{
1171 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1172
1173 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1174 unsigned int mask, shift;
1175
1176 if (entry->trunk) {
1177 data |= GLOBAL_ATU_DATA_TRUNK;
1178 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1179 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1180 } else {
1181 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1182 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1183 }
1184
1185 data |= (entry->portv_trunkid << shift) & mask;
1186 }
1187
a935c052 1188 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1189}
1190
fad09c73 1191static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1192 struct mv88e6xxx_atu_entry *entry,
1193 bool static_too)
facd95b2 1194{
7fb5e755
VD		 1195 int op;
1196 int err;
facd95b2 1197
fad09c73 1198 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1199 if (err)
1200 return err;
facd95b2 1201
fad09c73 1202 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1203 if (err)
1204 return err;
1205
1206 if (entry->fid) {
7fb5e755
VD		 1207 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1208 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1209 } else {
1210 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1211 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1212 }
1213
fad09c73 1214 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1215}
1216
fad09c73 1217static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1218 u16 fid, bool static_too)
7fb5e755
VD		 1219{
1220 struct mv88e6xxx_atu_entry entry = {
1221 .fid = fid,
1222 .state = 0, /* EntryState bits must be 0 */
1223 };
70cc99d1 1224
fad09c73 1225 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1226}
1227
fad09c73 1228static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1229 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1230{
1231 struct mv88e6xxx_atu_entry entry = {
1232 .trunk = false,
1233 .fid = fid,
1234 };
1235
1236 /* EntryState bits must be 0xF */
1237 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1238
1239 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1240 entry.portv_trunkid = (to_port & 0x0f) << 4;
1241 entry.portv_trunkid |= from_port & 0x0f;
1242
fad09c73 1243 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1244}
1245
fad09c73 1246static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1247 int port, bool static_too)
9f4d55d2
VD		 1248{
1249 /* Destination port 0xF means remove the entries */
fad09c73 1250 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1251}
1252
fad09c73 1253static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1254{
fad09c73 1255 struct net_device *bridge = chip->ports[port].bridge_dev;
fad09c73 1256 struct dsa_switch *ds = chip->ds;
b7666efe 1257 u16 output_ports = 0;
b7666efe
VD		 1258 int i;
1259
1260 /* allow CPU port or DSA link(s) to send frames to every port */
1261 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1262 output_ports = ~0;
b7666efe 1263 } else {
370b4ffb 1264 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1265 /* allow sending frames to every group member */
fad09c73 1266 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1267 output_ports |= BIT(i);
1268
1269 /* allow sending frames to CPU port and DSA link(s) */
1270 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1271 output_ports |= BIT(i);
1272 }
1273 }
1274
1275 /* prevent frames from going back out of the port they came in on */
1276 output_ports &= ~BIT(port);
facd95b2 1277
5a7921f4 1278 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1279}
1280
f81ec90f
VD		 1281static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1282 u8 state)
facd95b2 1283{
04bed143 1284 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1285 int stp_state;
553eb544 1286 int err;
facd95b2
GR		 1287
1288 switch (state) {
1289 case BR_STATE_DISABLED:
cca8b133 1290 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1291 break;
1292 case BR_STATE_BLOCKING:
1293 case BR_STATE_LISTENING:
cca8b133 1294 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1295 break;
1296 case BR_STATE_LEARNING:
cca8b133 1297 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1298 break;
1299 case BR_STATE_FORWARDING:
1300 default:
cca8b133 1301 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1302 break;
1303 }
1304
fad09c73 1305 mutex_lock(&chip->reg_lock);
e28def33 1306 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1307 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1308
1309 if (err)
e28def33 1310 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1311}
1312
749efcb8
VD		 1313static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1314{
1315 struct mv88e6xxx_chip *chip = ds->priv;
1316 int err;
1317
1318 mutex_lock(&chip->reg_lock);
1319 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1320 mutex_unlock(&chip->reg_lock);
1321
1322 if (err)
1323 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1324}
1325
fad09c73 1326static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1327{
a935c052 1328 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1329}
1330
fad09c73 1331static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1332{
a935c052 1333 int err;
6b17e864 1334
a935c052
VD		 1335 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1336 if (err)
1337 return err;
6b17e864 1338
fad09c73 1339 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1340}
1341
fad09c73 1342static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1343{
1344 int ret;
1345
fad09c73 1346 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1347 if (ret < 0)
1348 return ret;
1349
fad09c73 1350 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1351}
1352
fad09c73 1353static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1354 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1355 unsigned int nibble_offset)
1356{
b8fee957 1357 u16 regs[3];
a935c052 1358 int i, err;
b8fee957
VD		 1359
1360 for (i = 0; i < 3; ++i) {
a935c052 1361 u16 *reg = &regs[i];
b8fee957 1362
a935c052
VD		 1363 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1364 if (err)
1365 return err;
b8fee957
VD		 1366 }
1367
370b4ffb 1368 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1369 unsigned int shift = (i % 4) * 4 + nibble_offset;
1370 u16 reg = regs[i / 4];
1371
1372 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1373 }
1374
1375 return 0;
1376}
1377
fad09c73 1378static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1379 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1380{
fad09c73 1381 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1382}
1383
fad09c73 1384static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1385 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1386{
fad09c73 1387 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1388}
1389
fad09c73 1390static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1391 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1392 unsigned int nibble_offset)
1393{
7dad08d7 1394 u16 regs[3] = { 0 };
a935c052 1395 int i, err;
7dad08d7 1396
370b4ffb 1397 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1398 unsigned int shift = (i % 4) * 4 + nibble_offset;
1399 u8 data = entry->data[i];
1400
1401 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1402 }
1403
1404 for (i = 0; i < 3; ++i) {
a935c052
VD		 1405 u16 reg = regs[i];
1406
1407 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1408 if (err)
1409 return err;
7dad08d7
VD		 1410 }
1411
1412 return 0;
1413}
1414
fad09c73 1415static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1416 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1417{
fad09c73 1418 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1419}
1420
fad09c73 1421static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1422 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1423{
fad09c73 1424 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1425}
1426
fad09c73 1427static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1428{
a935c052
VD		 1429 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1430 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1431}
1432
fad09c73 1433static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1434 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1435{
b4e47c0f 1436 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1437 u16 val;
1438 int err;
b8fee957 1439
a935c052
VD		 1440 err = _mv88e6xxx_vtu_wait(chip);
1441 if (err)
1442 return err;
b8fee957 1443
a935c052
VD		 1444 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1445 if (err)
1446 return err;
b8fee957 1447
a935c052
VD		 1448 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1449 if (err)
1450 return err;
b8fee957 1451
a935c052
VD		 1452 next.vid = val & GLOBAL_VTU_VID_MASK;
1453 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1454
1455 if (next.valid) {
a935c052
VD		 1456 err = mv88e6xxx_vtu_data_read(chip, &next);
1457 if (err)
1458 return err;
b8fee957 1459
6dc10bbc 1460 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1461 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1462 if (err)
1463 return err;
b8fee957 1464
a935c052 1465 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1466 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1467 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1468 * VTU DBNum[3:0] are located in VTU Operation 3:0
1469 */
a935c052
VD		 1470 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1471 if (err)
1472 return err;
11ea809f 1473
a935c052
VD		 1474 next.fid = (val & 0xf00) >> 4;
1475 next.fid |= val & 0xf;
2e7bd5ef 1476 }
b8fee957 1477
fad09c73 1478 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1479 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1480 if (err)
1481 return err;
b8fee957 1482
a935c052 1483 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1484 }
1485 }
1486
1487 *entry = next;
1488 return 0;
1489}
1490
f81ec90f
VD		 1491static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1492 struct switchdev_obj_port_vlan *vlan,
1493 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1494{
04bed143 1495 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1496 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1497 u16 pvid;
1498 int err;
1499
fad09c73 1500 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1501 return -EOPNOTSUPP;
1502
fad09c73 1503 mutex_lock(&chip->reg_lock);
ceff5eff 1504
77064f37 1505 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1506 if (err)
1507 goto unlock;
1508
fad09c73 1509 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1510 if (err)
1511 goto unlock;
1512
1513 do {
fad09c73 1514 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1515 if (err)
1516 break;
1517
1518 if (!next.valid)
1519 break;
1520
1521 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1522 continue;
1523
1524 /* reinit and dump this VLAN obj */
57d32310
VD		 1525 vlan->vid_begin = next.vid;
1526 vlan->vid_end = next.vid;
ceff5eff
VD		 1527 vlan->flags = 0;
1528
1529 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1530 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1531
1532 if (next.vid == pvid)
1533 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1534
1535 err = cb(&vlan->obj);
1536 if (err)
1537 break;
1538 } while (next.vid < GLOBAL_VTU_VID_MASK);
1539
1540unlock:
fad09c73 1541 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1542
1543 return err;
1544}
1545
fad09c73 1546static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1547 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1548{
11ea809f 1549 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1550 u16 reg = 0;
a935c052 1551 int err;
7dad08d7 1552
a935c052
VD		 1553 err = _mv88e6xxx_vtu_wait(chip);
1554 if (err)
1555 return err;
7dad08d7
VD		 1556
1557 if (!entry->valid)
1558 goto loadpurge;
1559
1560 /* Write port member tags */
a935c052
VD		 1561 err = mv88e6xxx_vtu_data_write(chip, entry);
1562 if (err)
1563 return err;
7dad08d7 1564
fad09c73 1565 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1566 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1567 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1568 if (err)
1569 return err;
b426e5f7 1570 }
7dad08d7 1571
6dc10bbc 1572 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1573 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1574 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1575 if (err)
1576 return err;
fad09c73 1577 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1578 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1579 * VTU DBNum[3:0] are located in VTU Operation 3:0
1580 */
1581 op |= (entry->fid & 0xf0) << 8;
1582 op |= entry->fid & 0xf;
7dad08d7
VD		 1583 }
1584
1585 reg = GLOBAL_VTU_VID_VALID;
1586loadpurge:
1587 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1588 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1589 if (err)
1590 return err;
7dad08d7 1591
fad09c73 1592 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1593}
1594
fad09c73 1595static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1596 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1597{
b4e47c0f 1598 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1599 u16 val;
1600 int err;
0d3b33e6 1601
a935c052
VD		 1602 err = _mv88e6xxx_vtu_wait(chip);
1603 if (err)
1604 return err;
0d3b33e6 1605
a935c052
VD		 1606 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1607 sid & GLOBAL_VTU_SID_MASK);
1608 if (err)
1609 return err;
0d3b33e6 1610
a935c052
VD		 1611 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1612 if (err)
1613 return err;
0d3b33e6 1614
a935c052
VD		 1615 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1616 if (err)
1617 return err;
0d3b33e6 1618
a935c052 1619 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1620
a935c052
VD		 1621 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1622 if (err)
1623 return err;
0d3b33e6 1624
a935c052 1625 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1626
1627 if (next.valid) {
a935c052
VD		 1628 err = mv88e6xxx_stu_data_read(chip, &next);
1629 if (err)
1630 return err;
0d3b33e6
VD		 1631 }
1632
1633 *entry = next;
1634 return 0;
1635}
1636
fad09c73 1637static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1638 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1639{
1640 u16 reg = 0;
a935c052 1641 int err;
0d3b33e6 1642
a935c052
VD		 1643 err = _mv88e6xxx_vtu_wait(chip);
1644 if (err)
1645 return err;
0d3b33e6
VD		 1646
1647 if (!entry->valid)
1648 goto loadpurge;
1649
1650 /* Write port states */
a935c052
VD		 1651 err = mv88e6xxx_stu_data_write(chip, entry);
1652 if (err)
1653 return err;
0d3b33e6
VD		 1654
1655 reg = GLOBAL_VTU_VID_VALID;
1656loadpurge:
a935c052
VD		 1657 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1658 if (err)
1659 return err;
0d3b33e6
VD		 1660
1661 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1662 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1663 if (err)
1664 return err;
0d3b33e6 1665
fad09c73 1666 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1667}
1668
fad09c73 1669static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1670{
1671 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1672 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1673 int i, err;
3285f9e8
VD		 1674
1675 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1676
2db9ce1f 1677 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1678 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1679 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1680 if (err)
1681 return err;
1682
1683 set_bit(*fid, fid_bitmap);
1684 }
1685
3285f9e8 1686 /* Set every FID bit used by the VLAN entries */
fad09c73 1687 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1688 if (err)
1689 return err;
1690
1691 do {
fad09c73 1692 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1693 if (err)
1694 return err;
1695
1696 if (!vlan.valid)
1697 break;
1698
1699 set_bit(vlan.fid, fid_bitmap);
1700 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1701
1702 /* The reset value 0x000 is used to indicate that multiple address
1703 * databases are not needed. Return the next positive available.
1704 */
1705 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1706 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1707 return -ENOSPC;
1708
1709 /* Clear the database */
fad09c73 1710 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1711}
1712
fad09c73 1713static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1714 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1715{
fad09c73 1716 struct dsa_switch *ds = chip->ds;
b4e47c0f 1717 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1718 .valid = true,
1719 .vid = vid,
1720 };
3285f9e8
VD		 1721 int i, err;
1722
fad09c73 1723 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1724 if (err)
1725 return err;
0d3b33e6 1726
3d131f07 1727 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1728 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1729 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1730 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1731 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1732
fad09c73
VD		 1733 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1734 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1735 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1736
1737 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1738 * implemented, only one STU entry is needed to cover all VTU
1739 * entries. Thus, validate the SID 0.
1740 */
1741 vlan.sid = 0;
fad09c73 1742 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1743 if (err)
1744 return err;
1745
1746 if (vstp.sid != vlan.sid || !vstp.valid) {
1747 memset(&vstp, 0, sizeof(vstp));
1748 vstp.valid = true;
1749 vstp.sid = vlan.sid;
1750
fad09c73 1751 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1752 if (err)
1753 return err;
1754 }
0d3b33e6
VD		 1755 }
1756
1757 *entry = vlan;
1758 return 0;
1759}
1760
fad09c73 1761static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1762 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1763{
1764 int err;
1765
1766 if (!vid)
1767 return -EINVAL;
1768
fad09c73 1769 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1770 if (err)
1771 return err;
1772
fad09c73 1773 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1774 if (err)
1775 return err;
1776
1777 if (entry->vid != vid || !entry->valid) {
1778 if (!creat)
1779 return -EOPNOTSUPP;
1780 /* -ENOENT would've been more appropriate, but switchdev expects
1781 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1782 */
1783
fad09c73 1784 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1785 }
1786
1787 return err;
1788}
1789
da9c359e
VD		 1790static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1791 u16 vid_begin, u16 vid_end)
1792{
04bed143 1793 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1794 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1795 int i, err;
1796
1797 if (!vid_begin)
1798 return -EOPNOTSUPP;
1799
fad09c73 1800 mutex_lock(&chip->reg_lock);
da9c359e 1801
fad09c73 1802 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1803 if (err)
1804 goto unlock;
1805
1806 do {
fad09c73 1807 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1808 if (err)
1809 goto unlock;
1810
1811 if (!vlan.valid)
1812 break;
1813
1814 if (vlan.vid > vid_end)
1815 break;
1816
370b4ffb 1817 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1818 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1819 continue;
1820
1821 if (vlan.data[i] ==
1822 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1823 continue;
1824
fad09c73
VD		 1825 if (chip->ports[i].bridge_dev ==
1826 chip->ports[port].bridge_dev)
da9c359e
VD		 1827 break; /* same bridge, check next VLAN */
1828
c8b09808 1829 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1830 "hardware VLAN %d already used by %s\n",
1831 vlan.vid,
fad09c73 1832 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1833 err = -EOPNOTSUPP;
1834 goto unlock;
1835 }
1836 } while (vlan.vid < vid_end);
1837
1838unlock:
fad09c73 1839 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1840
1841 return err;
1842}
1843
f81ec90f
VD		 1844static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1845 bool vlan_filtering)
214cdb99 1846{
04bed143 1847 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1848 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1849 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1850 int err;
214cdb99 1851
fad09c73 1852 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1853 return -EOPNOTSUPP;
1854
fad09c73 1855 mutex_lock(&chip->reg_lock);
385a0995 1856 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1857 mutex_unlock(&chip->reg_lock);
214cdb99 1858
0e7b9925 1859 return err;
214cdb99
VD		 1860}
1861
57d32310
VD		 1862static int
1863mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1864 const struct switchdev_obj_port_vlan *vlan,
1865 struct switchdev_trans *trans)
76e398a6 1866{
04bed143 1867 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1868 int err;
1869
fad09c73 1870 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1871 return -EOPNOTSUPP;
1872
da9c359e
VD		 1873 /* If the requested port doesn't belong to the same bridge as the VLAN
1874 * members, do not support it (yet) and fallback to software VLAN.
1875 */
1876 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1877 vlan->vid_end);
1878 if (err)
1879 return err;
1880
76e398a6
VD		 1881 /* We don't need any dynamic resource from the kernel (yet),
1882 * so skip the prepare phase.
1883 */
1884 return 0;
1885}
1886
fad09c73 1887static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1888 u16 vid, bool untagged)
0d3b33e6 1889{
b4e47c0f 1890 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1891 int err;
1892
fad09c73 1893 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1894 if (err)
76e398a6 1895 return err;
0d3b33e6 1896
0d3b33e6
VD		 1897 vlan.data[port] = untagged ?
1898 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1899 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1900
fad09c73 1901 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1902}
1903
f81ec90f
VD		 1904static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1905 const struct switchdev_obj_port_vlan *vlan,
1906 struct switchdev_trans *trans)
76e398a6 1907{
04bed143 1908 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1909 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1910 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1911 u16 vid;
76e398a6 1912
fad09c73 1913 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1914 return;
1915
fad09c73 1916 mutex_lock(&chip->reg_lock);
76e398a6 1917
4d5770b3 1918 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1919 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1920 netdev_err(ds->ports[port].netdev,
1921 "failed to add VLAN %d%c\n",
4d5770b3 1922 vid, untagged ? 'u' : 't');
76e398a6 1923
77064f37 1924 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1925 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1926 vlan->vid_end);
0d3b33e6 1927
fad09c73 1928 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1929}
1930
fad09c73 1931static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1932 int port, u16 vid)
7dad08d7 1933{
fad09c73 1934 struct dsa_switch *ds = chip->ds;
b4e47c0f 1935 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1936 int i, err;
1937
fad09c73 1938 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1939 if (err)
76e398a6 1940 return err;
7dad08d7 1941
2fb5ef09
VD		 1942 /* Tell switchdev if this VLAN is handled in software */
1943 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1944 return -EOPNOTSUPP;
7dad08d7
VD		 1945
1946 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1947
1948 /* keep the VLAN unless all ports are excluded */
f02bdffc 1949 vlan.valid = false;
370b4ffb 1950 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1951 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1952 continue;
1953
1954 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1955 vlan.valid = true;
7dad08d7
VD		 1956 break;
1957 }
1958 }
1959
fad09c73 1960 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1961 if (err)
1962 return err;
1963
fad09c73 1964 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1965}
1966
f81ec90f
VD		 1967static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1968 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1969{
04bed143 1970 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1971 u16 pvid, vid;
1972 int err = 0;
1973
fad09c73 1974 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1975 return -EOPNOTSUPP;
1976
fad09c73 1977 mutex_lock(&chip->reg_lock);
76e398a6 1978
77064f37 1979 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1980 if (err)
1981 goto unlock;
1982
76e398a6 1983 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1984 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1985 if (err)
1986 goto unlock;
1987
1988 if (vid == pvid) {
77064f37 1989 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1990 if (err)
1991 goto unlock;
1992 }
1993 }
1994
7dad08d7 1995unlock:
fad09c73 1996 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1997
1998 return err;
1999}
2000
fad09c73 2001static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2002 const unsigned char *addr)
defb05b9 2003{
a935c052 2004 int i, err;
defb05b9
GR		 2005
2006 for (i = 0; i < 3; i++) {
a935c052
VD		 2007 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2008 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2009 if (err)
2010 return err;
defb05b9
GR		 2011 }
2012
2013 return 0;
2014}
2015
fad09c73 2016static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2017 unsigned char *addr)
defb05b9 2018{
a935c052
VD		 2019 u16 val;
2020 int i, err;
defb05b9
GR		 2021
2022 for (i = 0; i < 3; i++) {
a935c052
VD		 2023 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2024 if (err)
2025 return err;
2026
2027 addr[i * 2] = val >> 8;
2028 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2029 }
2030
2031 return 0;
2032}
2033
fad09c73 2034static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2035 struct mv88e6xxx_atu_entry *entry)
defb05b9 2036{
6630e236
VD		 2037 int ret;
2038
fad09c73 2039 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2040 if (ret < 0)
2041 return ret;
2042
fad09c73 2043 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2044 if (ret < 0)
2045 return ret;
2046
fad09c73 2047 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2048 if (ret < 0)
87820510
VD		 2049 return ret;
2050
fad09c73 2051 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2052}
87820510 2053
88472939
VD		 2054static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2055 struct mv88e6xxx_atu_entry *entry);
2056
2057static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2058 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2059{
2060 struct mv88e6xxx_atu_entry next;
2061 int err;
2062
2063 eth_broadcast_addr(next.mac);
2064
2065 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2066 if (err)
2067 return err;
2068
2069 do {
2070 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2071 if (err)
2072 return err;
2073
2074 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2075 break;
2076
2077 if (ether_addr_equal(next.mac, addr)) {
2078 *entry = next;
2079 return 0;
2080 }
2081 } while (!is_broadcast_ether_addr(next.mac));
2082
2083 memset(entry, 0, sizeof(*entry));
2084 entry->fid = fid;
2085 ether_addr_copy(entry->mac, addr);
2086
2087 return 0;
2088}
2089
83dabd1f
VD		 2090static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2091 const unsigned char *addr, u16 vid,
2092 u8 state)
fd231c82 2093{
b4e47c0f 2094 struct mv88e6xxx_vtu_entry vlan;
88472939 2095 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2096 int err;
2097
2db9ce1f
VD		 2098 /* Null VLAN ID corresponds to the port private database */
2099 if (vid == 0)
b4e48c50 2100 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2101 else
fad09c73 2102 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2103 if (err)
2104 return err;
fd231c82 2105
88472939
VD		 2106 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2107 if (err)
2108 return err;
2109
2110 /* Purge the ATU entry only if no port is using it anymore */
2111 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2112 entry.portv_trunkid &= ~BIT(port);
2113 if (!entry.portv_trunkid)
2114 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2115 } else {
2116 entry.portv_trunkid |= BIT(port);
2117 entry.state = state;
fd231c82
VD		 2118 }
2119
fad09c73 2120 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2121}
2122
f81ec90f
VD		 2123static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2124 const struct switchdev_obj_port_fdb *fdb,
2125 struct switchdev_trans *trans)
146a3206
VD		 2126{
2127 /* We don't need any dynamic resource from the kernel (yet),
2128 * so skip the prepare phase.
2129 */
2130 return 0;
2131}
2132
f81ec90f
VD		 2133static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2134 const struct switchdev_obj_port_fdb *fdb,
2135 struct switchdev_trans *trans)
87820510 2136{
04bed143 2137 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2138
fad09c73 2139 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2140 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2141 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2142 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2143 mutex_unlock(&chip->reg_lock);
87820510
VD		 2144}
2145
f81ec90f
VD		 2146static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2147 const struct switchdev_obj_port_fdb *fdb)
87820510 2148{
04bed143 2149 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2150 int err;
87820510 2151
fad09c73 2152 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2153 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2154 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2155 mutex_unlock(&chip->reg_lock);
87820510 2156
83dabd1f 2157 return err;
87820510
VD		 2158}
2159
fad09c73 2160static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2161 struct mv88e6xxx_atu_entry *entry)
6630e236 2162{
1d194046 2163 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2164 u16 val;
2165 int err;
1d194046
VD		 2166
2167 next.fid = fid;
defb05b9 2168
a935c052
VD		 2169 err = _mv88e6xxx_atu_wait(chip);
2170 if (err)
2171 return err;
6630e236 2172
a935c052
VD		 2173 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2174 if (err)
2175 return err;
6630e236 2176
a935c052
VD		 2177 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2178 if (err)
2179 return err;
6630e236 2180
a935c052
VD		 2181 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2182 if (err)
2183 return err;
6630e236 2184
a935c052 2185 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2186 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2187 unsigned int mask, shift;
2188
a935c052 2189 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2190 next.trunk = true;
2191 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2192 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2193 } else {
2194 next.trunk = false;
2195 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2196 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2197 }
2198
a935c052 2199 next.portv_trunkid = (val & mask) >> shift;
1d194046 2200 }
cdf09697 2201
1d194046 2202 *entry = next;
cdf09697
DM		 2203 return 0;
2204}
2205
83dabd1f
VD		 2206static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2207 u16 fid, u16 vid, int port,
2208 struct switchdev_obj *obj,
2209 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2210{
2211 struct mv88e6xxx_atu_entry addr = {
2212 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2213 };
2214 int err;
2215
fad09c73 2216 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2217 if (err)
2218 return err;
2219
2220 do {
fad09c73 2221 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2222 if (err)
83dabd1f 2223 return err;
74b6ba0d
VD		 2224
2225 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2226 break;
2227
83dabd1f
VD		 2228 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2229 continue;
2230
2231 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2232 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2233
83dabd1f
VD		 2234 if (!is_unicast_ether_addr(addr.mac))
2235 continue;
2236
2237 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2238 fdb->vid = vid;
2239 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2240 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2241 fdb->ndm_state = NUD_NOARP;
2242 else
2243 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2244 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2245 struct switchdev_obj_port_mdb *mdb;
2246
2247 if (!is_multicast_ether_addr(addr.mac))
2248 continue;
2249
2250 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2251 mdb->vid = vid;
2252 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2253 } else {
2254 return -EOPNOTSUPP;
74b6ba0d 2255 }
83dabd1f
VD		 2256
2257 err = cb(obj);
2258 if (err)
2259 return err;
74b6ba0d
VD		 2260 } while (!is_broadcast_ether_addr(addr.mac));
2261
2262 return err;
2263}
2264
83dabd1f
VD		 2265static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2266 struct switchdev_obj *obj,
2267 int (*cb)(struct switchdev_obj *obj))
f33475bd 2268{
b4e47c0f 2269 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2270 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2271 };
2db9ce1f 2272 u16 fid;
f33475bd
VD		 2273 int err;
2274
2db9ce1f 2275 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2276 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2277 if (err)
83dabd1f 2278 return err;
2db9ce1f 2279
83dabd1f 2280 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2281 if (err)
83dabd1f 2282 return err;
2db9ce1f 2283
74b6ba0d 2284 /* Dump VLANs' Filtering Information Databases */
fad09c73 2285 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2286 if (err)
83dabd1f 2287 return err;
f33475bd
VD		 2288
2289 do {
fad09c73 2290 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2291 if (err)
83dabd1f 2292 return err;
f33475bd
VD		 2293
2294 if (!vlan.valid)
2295 break;
2296
83dabd1f
VD		 2297 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2298 obj, cb);
f33475bd 2299 if (err)
83dabd1f 2300 return err;
f33475bd
VD		 2301 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2302
83dabd1f
VD		 2303 return err;
2304}
2305
2306static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2307 struct switchdev_obj_port_fdb *fdb,
2308 int (*cb)(struct switchdev_obj *obj))
2309{
04bed143 2310 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2311 int err;
2312
2313 mutex_lock(&chip->reg_lock);
2314 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2315 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2316
2317 return err;
2318}
2319
f81ec90f
VD		 2320static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2321 struct net_device *bridge)
e79a8bcb 2322{
04bed143 2323 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2324 int i, err = 0;
466dfa07 2325
fad09c73 2326 mutex_lock(&chip->reg_lock);
466dfa07 2327
b7666efe 2328 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2329 chip->ports[port].bridge_dev = bridge;
b7666efe 2330
370b4ffb 2331 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2332 if (chip->ports[i].bridge_dev == bridge) {
2333 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2334 if (err)
2335 break;
2336 }
2337 }
2338
fad09c73 2339 mutex_unlock(&chip->reg_lock);
a6692754 2340
466dfa07 2341 return err;
e79a8bcb
VD		 2342}
2343
f81ec90f 2344static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2345{
04bed143 2346 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2347 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2348 int i;
466dfa07 2349
fad09c73 2350 mutex_lock(&chip->reg_lock);
466dfa07 2351
b7666efe 2352 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2353 chip->ports[port].bridge_dev = NULL;
b7666efe 2354
370b4ffb 2355 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2356 if (i == port || chip->ports[i].bridge_dev == bridge)
2357 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2358 netdev_warn(ds->ports[i].netdev,
2359 "failed to remap\n");
b7666efe 2360
fad09c73 2361 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2362}
2363
fad09c73 2364static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2365{
fad09c73 2366 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2367 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2368 struct gpio_desc *gpiod = chip->reset;
552238b5 2369 unsigned long timeout;
0e7b9925 2370 u16 reg;
a935c052 2371 int err;
552238b5
VD		 2372 int i;
2373
2374 /* Set all ports to the disabled state. */
370b4ffb 2375 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2376 err = mv88e6xxx_port_set_state(chip, i,
2377 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2378 if (err)
2379 return err;
552238b5
VD		 2380 }
2381
2382 /* Wait for transmit queues to drain. */
2383 usleep_range(2000, 4000);
2384
2385 /* If there is a gpio connected to the reset pin, toggle it */
2386 if (gpiod) {
2387 gpiod_set_value_cansleep(gpiod, 1);
2388 usleep_range(10000, 20000);
2389 gpiod_set_value_cansleep(gpiod, 0);
2390 usleep_range(10000, 20000);
2391 }
2392
2393 /* Reset the switch. Keep the PPU active if requested. The PPU
2394 * needs to be active to support indirect phy register access
2395 * through global registers 0x18 and 0x19.
2396 */
2397 if (ppu_active)
a935c052 2398 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
552238b5 2399 else
a935c052 2400 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
0e7b9925
AL		 2401 if (err)
2402 return err;
552238b5
VD		 2403
2404 /* Wait up to one second for reset to complete. */
2405 timeout = jiffies + 1 * HZ;
2406 while (time_before(jiffies, timeout)) {
a935c052
VD		 2407 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2408 if (err)
2409 return err;
552238b5 2410
a935c052 2411 if ((reg & is_reset) == is_reset)
552238b5
VD		 2412 break;
2413 usleep_range(1000, 2000);
2414 }
2415 if (time_after(jiffies, timeout))
0e7b9925 2416 err = -ETIMEDOUT;
552238b5 2417 else
0e7b9925 2418 err = 0;
552238b5 2419
0e7b9925 2420 return err;
552238b5
VD		 2421}
2422
09cb7dfd 2423static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2424{
09cb7dfd
VD		 2425 u16 val;
2426 int err;
13a7ebb3 2427
09cb7dfd
VD		 2428 /* Clear Power Down bit */
2429 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2430 if (err)
2431 return err;
13a7ebb3 2432
09cb7dfd
VD		 2433 if (val & BMCR_PDOWN) {
2434 val &= ~BMCR_PDOWN;
2435 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2436 }
2437
09cb7dfd 2438 return err;
13a7ebb3
PU		 2439}
2440
fad09c73 2441static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2442{
fad09c73 2443 struct dsa_switch *ds = chip->ds;
0e7b9925 2444 int err;
54d792f2 2445 u16 reg;
d827e88a 2446
d78343d2
VD		 2447 /* MAC Forcing register: don't force link, speed, duplex or flow control
2448 * state to any particular values on physical ports, but force the CPU
2449 * port and all DSA ports to their maximum bandwidth and full duplex.
2450 */
2451 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2452 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2453 SPEED_MAX, DUPLEX_FULL,
2454 PHY_INTERFACE_MODE_NA);
2455 else
2456 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2457 SPEED_UNFORCED, DUPLEX_UNFORCED,
2458 PHY_INTERFACE_MODE_NA);
2459 if (err)
2460 return err;
54d792f2
AL		 2461
2462 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2463 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2464 * tunneling, determine priority by looking at 802.1p and IP
2465 * priority fields (IP prio has precedence), and set STP state
2466 * to Forwarding.
2467 *
2468 * If this is the CPU link, use DSA or EDSA tagging depending
2469 * on which tagging mode was configured.
2470 *
2471 * If this is a link to another switch, use DSA tagging mode.
2472 *
2473 * If this is the upstream port for this switch, enable
2474 * forwarding of unknown unicasts and multicasts.
2475 */
2476 reg = 0;
fad09c73
VD		 2477 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2478 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2479 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2480 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2481 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2482 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2483 PORT_CONTROL_STATE_FORWARDING;
2484 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2485 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2486 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2487 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2488 else
2489 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2490 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2491 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2492 }
6083ce71 2493 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2494 if (mv88e6xxx_6095_family(chip) ||
2495 mv88e6xxx_6185_family(chip))
6083ce71 2496 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2497 if (mv88e6xxx_6352_family(chip) ||
2498 mv88e6xxx_6351_family(chip) ||
2499 mv88e6xxx_6165_family(chip) ||
2500 mv88e6xxx_6097_family(chip) ||
2501 mv88e6xxx_6320_family(chip)) {
54d792f2 2502 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2503 }
2504
54d792f2
AL		 2505 if (port == dsa_upstream_port(ds))
2506 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2507 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2508 }
2509 if (reg) {
0e7b9925
AL		 2510 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2511 if (err)
2512 return err;
54d792f2
AL		 2513 }
2514
13a7ebb3
PU		 2515 /* If this port is connected to a SerDes, make sure the SerDes is not
2516 * powered down.
2517 */
09cb7dfd 2518 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2519 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2520 if (err)
2521 return err;
2522 reg &= PORT_STATUS_CMODE_MASK;
2523 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2524 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2525 (reg == PORT_STATUS_CMODE_SGMII)) {
2526 err = mv88e6xxx_serdes_power_on(chip);
2527 if (err < 0)
2528 return err;
13a7ebb3
PU		 2529 }
2530 }
2531
8efdda4a 2532 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2533 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2534 * untagged frames on this port, do a destination address lookup on all
2535 * received packets as usual, disable ARP mirroring and don't send a
2536 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2537 */
2538 reg = 0;
fad09c73
VD		 2539 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2540 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2541 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2542 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2543 reg = PORT_CONTROL_2_MAP_DA;
2544
fad09c73
VD		 2545 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2546 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2547 reg |= PORT_CONTROL_2_JUMBO_10240;
2548
fad09c73 2549 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2550 /* Set the upstream port this port should use */
2551 reg |= dsa_upstream_port(ds);
2552 /* enable forwarding of unknown multicast addresses to
2553 * the upstream port
2554 */
2555 if (port == dsa_upstream_port(ds))
2556 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2557 }
2558
46fbe5e5 2559 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2560
54d792f2 2561 if (reg) {
0e7b9925
AL		 2562 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2563 if (err)
2564 return err;
54d792f2
AL		 2565 }
2566
2567 /* Port Association Vector: when learning source addresses
2568 * of packets, add the address to the address database using
2569 * a port bitmap that has only the bit for this port set and
2570 * the other bits clear.
2571 */
4c7ea3c0 2572 reg = 1 << port;
996ecb82
VD		 2573 /* Disable learning for CPU port */
2574 if (dsa_is_cpu_port(ds, port))
65fa4027 2575 reg = 0;
4c7ea3c0 2576
0e7b9925
AL		 2577 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2578 if (err)
2579 return err;
54d792f2
AL		 2580
2581 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2582 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2583 if (err)
2584 return err;
54d792f2 2585
fad09c73
VD		 2586 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2587 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2588 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2589 /* Do not limit the period of time that this port can
2590 * be paused for by the remote end or the period of
2591 * time that this port can pause the remote end.
2592 */
0e7b9925
AL		 2593 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2594 if (err)
2595 return err;
54d792f2
AL		 2596
2597 /* Port ATU control: disable limiting the number of
2598 * address database entries that this port is allowed
2599 * to use.
2600 */
0e7b9925
AL		 2601 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2602 0x0000);
54d792f2
AL		 2603 /* Priority Override: disable DA, SA and VTU priority
2604 * override.
2605 */
0e7b9925
AL		 2606 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2607 0x0000);
2608 if (err)
2609 return err;
54d792f2
AL		 2610
2611 /* Port Ethertype: use the Ethertype DSA Ethertype
2612 * value.
2613 */
2bbb33be 2614 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
0e7b9925
AL		 2615 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2616 ETH_P_EDSA);
2617 if (err)
2618 return err;
2bbb33be
AL		 2619 }
2620
54d792f2
AL		 2621 /* Tag Remap: use an identity 802.1p prio -> switch
2622 * prio mapping.
2623 */
0e7b9925
AL		 2624 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2625 0x3210);
2626 if (err)
2627 return err;
54d792f2
AL		 2628
2629 /* Tag Remap 2: use an identity 802.1p prio -> switch
2630 * prio mapping.
2631 */
0e7b9925
AL		 2632 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2633 0x7654);
2634 if (err)
2635 return err;
54d792f2
AL		 2636 }
2637
1bc261fa 2638 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2639 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2640 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2641 mv88e6xxx_6320_family(chip)) {
0e7b9925
AL		 2642 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2643 0x0001);
2644 if (err)
2645 return err;
1bc261fa 2646 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
0e7b9925
AL		 2647 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2648 0x0000);
2649 if (err)
2650 return err;
54d792f2
AL		 2651 }
2652
366f0a0f
GR		 2653 /* Port Control 1: disable trunking, disable sending
2654 * learning messages to this port.
d827e88a 2655 */
0e7b9925
AL		 2656 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2657 if (err)
2658 return err;
d827e88a 2659
207afda1 2660 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2661 * database, and allow bidirectional communication between the
2662 * CPU and DSA port(s), and the other ports.
d827e88a 2663 */
b4e48c50 2664 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2665 if (err)
2666 return err;
2db9ce1f 2667
0e7b9925
AL		 2668 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2669 if (err)
2670 return err;
d827e88a
GR		 2671
2672 /* Default VLAN ID and priority: don't set a default VLAN
2673 * ID, and set the default packet priority to zero.
2674 */
0e7b9925 2675 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2676}
2677
aa0938c6 2678static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2679{
2680 int err;
2681
a935c052 2682 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2683 if (err)
2684 return err;
2685
a935c052 2686 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2687 if (err)
2688 return err;
2689
a935c052
VD		 2690 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2691 if (err)
2692 return err;
2693
2694 return 0;
3b4caa1b
VD		 2695}
2696
acddbd21
VD		 2697static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2698 unsigned int msecs)
2699{
2700 const unsigned int coeff = chip->info->age_time_coeff;
2701 const unsigned int min = 0x01 * coeff;
2702 const unsigned int max = 0xff * coeff;
2703 u8 age_time;
2704 u16 val;
2705 int err;
2706
2707 if (msecs < min || msecs > max)
2708 return -ERANGE;
2709
2710 /* Round to nearest multiple of coeff */
2711 age_time = (msecs + coeff / 2) / coeff;
2712
a935c052 2713 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2714 if (err)
2715 return err;
2716
2717 /* AgeTime is 11:4 bits */
2718 val &= ~0xff0;
2719 val |= age_time << 4;
2720
a935c052 2721 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2722}
2723
2cfcd964
VD		 2724static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2725 unsigned int ageing_time)
2726{
04bed143 2727 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2728 int err;
2729
2730 mutex_lock(&chip->reg_lock);
2731 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2732 mutex_unlock(&chip->reg_lock);
2733
2734 return err;
2735}
2736
9729934c 2737static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2738{
fad09c73 2739 struct dsa_switch *ds = chip->ds;
b0745e87 2740 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2741 u16 reg;
552238b5 2742 int err;
54d792f2 2743
119477bd
VD		 2744 /* Enable the PHY Polling Unit if present, don't discard any packets,
2745 * and mask all interrupt sources.
2746 */
dc30c35b
AL		 2747 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2748 if (err < 0)
2749 return err;
2750
2751 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
fad09c73
VD		 2752 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2753 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2754 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2755
a935c052 2756 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
119477bd
VD		 2757 if (err)
2758 return err;
2759
b0745e87
VD		 2760 /* Configure the upstream port, and configure it as the port to which
2761 * ingress and egress and ARP monitor frames are to be sent.
2762 */
2763 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2764 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2765 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
a935c052 2766 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
b0745e87
VD		 2767 if (err)
2768 return err;
2769
50484ff4 2770 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2771 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2772 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2773 (ds->index & 0x1f));
50484ff4
VD		 2774 if (err)
2775 return err;
2776
acddbd21
VD		 2777 /* Clear all the VTU and STU entries */
2778 err = _mv88e6xxx_vtu_stu_flush(chip);
2779 if (err < 0)
2780 return err;
2781
54d792f2
AL		 2782 /* Set the default address aging time to 5 minutes, and
2783 * enable address learn messages to be sent to all message
2784 * ports.
2785 */
a935c052
VD		 2786 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2787 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2788 if (err)
08a01261 2789 return err;
54d792f2 2790
acddbd21
VD		 2791 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2792 if (err)
9729934c
VD		 2793 return err;
2794
2795 /* Clear all ATU entries */
2796 err = _mv88e6xxx_atu_flush(chip, 0, true);
2797 if (err)
2798 return err;
2799
54d792f2 2800 /* Configure the IP ToS mapping registers. */
a935c052 2801 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2802 if (err)
08a01261 2803 return err;
a935c052 2804 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2805 if (err)
08a01261 2806 return err;
a935c052 2807 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2808 if (err)
08a01261 2809 return err;
a935c052 2810 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2811 if (err)
08a01261 2812 return err;
a935c052 2813 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2814 if (err)
08a01261 2815 return err;
a935c052 2816 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2817 if (err)
08a01261 2818 return err;
a935c052 2819 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2820 if (err)
08a01261 2821 return err;
a935c052 2822 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2823 if (err)
08a01261 2824 return err;
54d792f2
AL		 2825
2826 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2827 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2828 if (err)
08a01261 2829 return err;
54d792f2 2830
de227387
AL		 2831 /* Initialize the statistics unit */
2832 err = mv88e6xxx_stats_set_histogram(chip);
2833 if (err)
2834 return err;
2835
9729934c 2836 /* Clear the statistics counters for all ports */
a935c052
VD		 2837 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2838 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2839 if (err)
2840 return err;
2841
2842 /* Wait for the flush to complete. */
7f9ef3af 2843 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2844 if (err)
2845 return err;
2846
2847 return 0;
2848}
2849
f81ec90f 2850static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2851{
04bed143 2852 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2853 int err;
a1a6a4d1
VD		 2854 int i;
2855
fad09c73
VD		 2856 chip->ds = ds;
2857 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2858
fad09c73 2859 mutex_lock(&chip->reg_lock);
08a01261 2860
9729934c 2861 /* Setup Switch Port Registers */
370b4ffb 2862 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2863 err = mv88e6xxx_setup_port(chip, i);
2864 if (err)
2865 goto unlock;
2866 }
2867
2868 /* Setup Switch Global 1 Registers */
2869 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2870 if (err)
2871 goto unlock;
2872
9729934c
VD		 2873 /* Setup Switch Global 2 Registers */
2874 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2875 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2876 if (err)
2877 goto unlock;
2878 }
08a01261 2879
6b17e864 2880unlock:
fad09c73 2881 mutex_unlock(&chip->reg_lock);
db687a56 2882
48ace4ef 2883 return err;
54d792f2
AL		 2884}
2885
3b4caa1b
VD		 2886static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2887{
04bed143 2888 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2889 int err;
2890
b073d4e2
VD		 2891 if (!chip->info->ops->set_switch_mac)
2892 return -EOPNOTSUPP;
3b4caa1b 2893
b073d4e2
VD		 2894 mutex_lock(&chip->reg_lock);
2895 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2896 mutex_unlock(&chip->reg_lock);
2897
2898 return err;
2899}
2900
e57e5e77 2901static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2902{
fad09c73 2903 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2904 u16 val;
2905 int err;
fd3a0ee4 2906
370b4ffb 2907 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2908 return 0xffff;
fd3a0ee4 2909
fad09c73 2910 mutex_lock(&chip->reg_lock);
e57e5e77 2911 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2912 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2913
2914 return err ? err : val;
fd3a0ee4
AL		 2915}
2916
e57e5e77 2917static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2918{
fad09c73 2919 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2920 int err;
fd3a0ee4 2921
370b4ffb 2922 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2923 return 0xffff;
fd3a0ee4 2924
fad09c73 2925 mutex_lock(&chip->reg_lock);
e57e5e77 2926 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2927 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2928
2929 return err;
fd3a0ee4
AL		 2930}
2931
fad09c73 2932static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2933 struct device_node *np)
2934{
2935 static int index;
2936 struct mii_bus *bus;
2937 int err;
2938
b516d453 2939 if (np)
fad09c73 2940 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2941
fad09c73 2942 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2943 if (!bus)
2944 return -ENOMEM;
2945
fad09c73 2946 bus->priv = (void *)chip;
b516d453
AL		 2947 if (np) {
2948 bus->name = np->full_name;
2949 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2950 } else {
2951 bus->name = "mv88e6xxx SMI";
2952 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2953 }
2954
2955 bus->read = mv88e6xxx_mdio_read;
2956 bus->write = mv88e6xxx_mdio_write;
fad09c73 2957 bus->parent = chip->dev;
b516d453 2958
fad09c73
VD		 2959 if (chip->mdio_np)
2960 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2961 else
2962 err = mdiobus_register(bus);
2963 if (err) {
fad09c73 2964 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 2965 goto out;
2966 }
fad09c73 2967 chip->mdio_bus = bus;
b516d453
AL		 2968
2969 return 0;
2970
2971out:
fad09c73
VD		 2972 if (chip->mdio_np)
2973 of_node_put(chip->mdio_np);
b516d453
AL		 2974
2975 return err;
2976}
2977
fad09c73 2978static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2979
2980{
fad09c73 2981 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 2982
2983 mdiobus_unregister(bus);
2984
fad09c73
VD		 2985 if (chip->mdio_np)
2986 of_node_put(chip->mdio_np);
b516d453
AL		 2987}
2988
c22995c5
GR		 2989#ifdef CONFIG_NET_DSA_HWMON
2990
2991static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2992{
04bed143 2993 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 2994 u16 val;
c22995c5 2995 int ret;
c22995c5
GR		 2996
2997 *temp = 0;
2998
fad09c73 2999 mutex_lock(&chip->reg_lock);
c22995c5 3000
9c93829c 3001 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3002 if (ret < 0)
3003 goto error;
3004
3005 /* Enable temperature sensor */
9c93829c 3006 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3007 if (ret < 0)
3008 goto error;
3009
9c93829c 3010 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3011 if (ret < 0)
3012 goto error;
3013
3014 /* Wait for temperature to stabilize */
3015 usleep_range(10000, 12000);
3016
9c93829c
VD		 3017 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3018 if (ret < 0)
c22995c5 3019 goto error;
c22995c5
GR		 3020
3021 /* Disable temperature sensor */
9c93829c 3022 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3023 if (ret < 0)
3024 goto error;
3025
3026 *temp = ((val & 0x1f) - 5) * 5;
3027
3028error:
9c93829c 3029 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3030 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3031 return ret;
3032}
3033
3034static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3035{
04bed143 3036 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3037 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3038 u16 val;
c22995c5
GR		 3039 int ret;
3040
3041 *temp = 0;
3042
9c93829c
VD		 3043 mutex_lock(&chip->reg_lock);
3044 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3045 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3046 if (ret < 0)
3047 return ret;
3048
9c93829c 3049 *temp = (val & 0xff) - 25;
c22995c5
GR		 3050
3051 return 0;
3052}
3053
f81ec90f 3054static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3055{
04bed143 3056 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3057
fad09c73 3058 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3059 return -EOPNOTSUPP;
3060
fad09c73 3061 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3062 return mv88e63xx_get_temp(ds, temp);
3063
3064 return mv88e61xx_get_temp(ds, temp);
3065}
3066
f81ec90f 3067static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3068{
04bed143 3069 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3070 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3071 u16 val;
c22995c5
GR		 3072 int ret;
3073
fad09c73 3074 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3075 return -EOPNOTSUPP;
3076
3077 *temp = 0;
3078
9c93829c
VD		 3079 mutex_lock(&chip->reg_lock);
3080 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3081 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3082 if (ret < 0)
3083 return ret;
3084
9c93829c 3085 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3086
3087 return 0;
3088}
3089
f81ec90f 3090static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3091{
04bed143 3092 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3093 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3094 u16 val;
3095 int err;
c22995c5 3096
fad09c73 3097 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3098 return -EOPNOTSUPP;
3099
9c93829c
VD		 3100 mutex_lock(&chip->reg_lock);
3101 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3102 if (err)
3103 goto unlock;
c22995c5 3104 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3105 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3106 (val & 0xe0ff) | (temp << 8));
3107unlock:
3108 mutex_unlock(&chip->reg_lock);
3109
3110 return err;
c22995c5
GR		 3111}
3112
f81ec90f 3113static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3114{
04bed143 3115 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3116 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3117 u16 val;
c22995c5
GR		 3118 int ret;
3119
fad09c73 3120 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3121 return -EOPNOTSUPP;
3122
3123 *alarm = false;
3124
9c93829c
VD		 3125 mutex_lock(&chip->reg_lock);
3126 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3127 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3128 if (ret < 0)
3129 return ret;
3130
9c93829c 3131 *alarm = !!(val & 0x40);
c22995c5
GR		 3132
3133 return 0;
3134}
3135#endif /* CONFIG_NET_DSA_HWMON */
3136
855b1932
VD		 3137static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3138{
04bed143 3139 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3140
3141 return chip->eeprom_len;
3142}
3143
855b1932
VD		 3144static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3145 struct ethtool_eeprom *eeprom, u8 *data)
3146{
04bed143 3147 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3148 int err;
3149
ee4dc2e7
VD		 3150 if (!chip->info->ops->get_eeprom)
3151 return -EOPNOTSUPP;
855b1932 3152
ee4dc2e7
VD		 3153 mutex_lock(&chip->reg_lock);
3154 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3155 mutex_unlock(&chip->reg_lock);
3156
3157 if (err)
3158 return err;
3159
3160 eeprom->magic = 0xc3ec4951;
3161
3162 return 0;
3163}
3164
855b1932
VD		 3165static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3166 struct ethtool_eeprom *eeprom, u8 *data)
3167{
04bed143 3168 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3169 int err;
3170
ee4dc2e7
VD		 3171 if (!chip->info->ops->set_eeprom)
3172 return -EOPNOTSUPP;
3173
855b1932
VD		 3174 if (eeprom->magic != 0xc3ec4951)
3175 return -EINVAL;
3176
3177 mutex_lock(&chip->reg_lock);
ee4dc2e7 3178 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3179 mutex_unlock(&chip->reg_lock);
3180
3181 return err;
3182}
3183
b3469dd8 3184static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3185 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3186 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3187 .phy_read = mv88e6xxx_phy_ppu_read,
3188 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3189 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3190 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3191 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3192 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3193 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3194 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3195 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3196};
3197
3198static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3199 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3200 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3201 .phy_read = mv88e6xxx_phy_ppu_read,
3202 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3203 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3204 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3205 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3206 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3207 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3208 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3209 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3210};
3211
7d381a02
SE		 3212static const struct mv88e6xxx_ops mv88e6097_ops = {
3213 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3214 .phy_read = mv88e6xxx_g2_smi_phy_read,
3215 .phy_write = mv88e6xxx_g2_smi_phy_write,
3216 .port_set_link = mv88e6xxx_port_set_link,
3217 .port_set_duplex = mv88e6xxx_port_set_duplex,
3218 .port_set_speed = mv88e6185_port_set_speed,
3219 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3220 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3221 .stats_get_strings = mv88e6095_stats_get_strings,
3222 .stats_get_stats = mv88e6095_stats_get_stats,
3223};
3224
b3469dd8 3225static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3226 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3227 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3228 .phy_read = mv88e6xxx_read,
3229 .phy_write = mv88e6xxx_write,
08ef7f10 3230 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3231 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3232 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3234 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3235 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3236 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3237};
3238
3239static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3240 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3241 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3242 .phy_read = mv88e6xxx_phy_ppu_read,
3243 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3244 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3245 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3246 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3247 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3248 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3249 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3250 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3251};
3252
3253static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3254 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3255 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3256 .phy_read = mv88e6xxx_read,
3257 .phy_write = mv88e6xxx_write,
08ef7f10 3258 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3259 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3260 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3261 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3262 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3263 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3264 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3265};
3266
3267static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3268 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3269 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3270 .phy_read = mv88e6xxx_read,
3271 .phy_write = mv88e6xxx_write,
08ef7f10 3272 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3273 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3274 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3275 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3276 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3277 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3278 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3279};
3280
3281static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3282 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3283 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3284 .phy_read = mv88e6xxx_g2_smi_phy_read,
3285 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3286 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3287 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3288 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3289 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3290 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3291 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3292 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3293 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3294};
3295
3296static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3297 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3298 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3299 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3301 .phy_read = mv88e6xxx_g2_smi_phy_read,
3302 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3303 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3304 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3305 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3306 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3307 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3308 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3309 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3310 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3311};
3312
3313static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3314 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3315 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3316 .phy_read = mv88e6xxx_g2_smi_phy_read,
3317 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3318 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3319 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3320 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3321 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3322 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3323 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3324 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3325 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3326};
3327
3328static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3329 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3330 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3331 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3332 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3333 .phy_read = mv88e6xxx_g2_smi_phy_read,
3334 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3335 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3336 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3337 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3338 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3339 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3340 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3341 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3342 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3343};
3344
3345static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3346 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3347 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3348 .phy_read = mv88e6xxx_phy_ppu_read,
3349 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3350 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3351 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3352 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3353 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3354 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3355 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3356 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3357};
3358
1a3b39ec 3359static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3360 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3361 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3362 .phy_read = mv88e6xxx_g2_smi_phy_read,
3363 .phy_write = mv88e6xxx_g2_smi_phy_write,
3364 .port_set_link = mv88e6xxx_port_set_link,
3365 .port_set_duplex = mv88e6xxx_port_set_duplex,
3366 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3367 .port_set_speed = mv88e6390_port_set_speed,
79523473 3368 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3369 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3370 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3371 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3372 .stats_get_stats = mv88e6390_stats_get_stats,
1a3b39ec
AL		 3373};
3374
3375static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3376 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3377 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3378 .phy_read = mv88e6xxx_g2_smi_phy_read,
3379 .phy_write = mv88e6xxx_g2_smi_phy_write,
3380 .port_set_link = mv88e6xxx_port_set_link,
3381 .port_set_duplex = mv88e6xxx_port_set_duplex,
3382 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3383 .port_set_speed = mv88e6390x_port_set_speed,
79523473 3384 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3385 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3386 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3387 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3388 .stats_get_stats = mv88e6390_stats_get_stats,
1a3b39ec
AL		 3389};
3390
3391static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3392 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3393 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3394 .phy_read = mv88e6xxx_g2_smi_phy_read,
3395 .phy_write = mv88e6xxx_g2_smi_phy_write,
3396 .port_set_link = mv88e6xxx_port_set_link,
3397 .port_set_duplex = mv88e6xxx_port_set_duplex,
3398 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3399 .port_set_speed = mv88e6390_port_set_speed,
79523473 3400 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3401 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3402 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3403 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3404 .stats_get_stats = mv88e6390_stats_get_stats,
1a3b39ec
AL		 3405};
3406
b3469dd8 3407static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3408 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3409 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3410 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3411 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3412 .phy_read = mv88e6xxx_g2_smi_phy_read,
3413 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3414 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3415 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3416 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3417 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3418 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3419 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3420 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3421 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3422};
3423
1a3b39ec 3424static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3425 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3426 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3427 .phy_read = mv88e6xxx_g2_smi_phy_read,
3428 .phy_write = mv88e6xxx_g2_smi_phy_write,
3429 .port_set_link = mv88e6xxx_port_set_link,
3430 .port_set_duplex = mv88e6xxx_port_set_duplex,
3431 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3432 .port_set_speed = mv88e6390_port_set_speed,
79523473 3433 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3434 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3435 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3436 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3437 .stats_get_stats = mv88e6390_stats_get_stats,
1a3b39ec
AL		 3438};
3439
b3469dd8 3440static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3441 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3442 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3443 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3444 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3445 .phy_read = mv88e6xxx_g2_smi_phy_read,
3446 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3447 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3448 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3449 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3450 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3451 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3452 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3453 .stats_get_stats = mv88e6320_stats_get_stats,
b3469dd8
VD		 3454};
3455
3456static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3457 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3458 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3459 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3460 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3461 .phy_read = mv88e6xxx_g2_smi_phy_read,
3462 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3463 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3464 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3465 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3466 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3467 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3468 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3469 .stats_get_stats = mv88e6320_stats_get_stats,
b3469dd8
VD		 3470};
3471
3472static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3473 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3475 .phy_read = mv88e6xxx_g2_smi_phy_read,
3476 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3477 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3478 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3479 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3480 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3481 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3482 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3483 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3484 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3485};
3486
3487static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3488 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3489 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3490 .phy_read = mv88e6xxx_g2_smi_phy_read,
3491 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3492 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3493 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3494 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3495 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3496 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3497 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3498 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3499 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3500};
3501
3502static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3503 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3504 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3505 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3506 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3507 .phy_read = mv88e6xxx_g2_smi_phy_read,
3508 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3509 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3510 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3511 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3512 .port_set_speed = mv88e6352_port_set_speed,
a605a0fe 3513 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3514 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3515 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3516 .stats_get_stats = mv88e6095_stats_get_stats,
b3469dd8
VD		 3517};
3518
1a3b39ec 3519static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3520 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3522 .phy_read = mv88e6xxx_g2_smi_phy_read,
3523 .phy_write = mv88e6xxx_g2_smi_phy_write,
3524 .port_set_link = mv88e6xxx_port_set_link,
3525 .port_set_duplex = mv88e6xxx_port_set_duplex,
3526 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3527 .port_set_speed = mv88e6390_port_set_speed,
79523473 3528 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3529 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3530 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3531 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3532 .stats_get_stats = mv88e6390_stats_get_stats,
1a3b39ec
AL		 3533};
3534
3535static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3536 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3537 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3538 .phy_read = mv88e6xxx_g2_smi_phy_read,
3539 .phy_write = mv88e6xxx_g2_smi_phy_write,
3540 .port_set_link = mv88e6xxx_port_set_link,
3541 .port_set_duplex = mv88e6xxx_port_set_duplex,
3542 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3543 .port_set_speed = mv88e6390x_port_set_speed,
79523473 3544 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3545 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3546 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3547 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3548 .stats_get_stats = mv88e6390_stats_get_stats,
1a3b39ec
AL		 3549};
3550
3551static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3552 /* MV88E6XXX_FAMILY_6390 */
1a3b39ec
AL		 3553 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3554 .phy_read = mv88e6xxx_g2_smi_phy_read,
3555 .phy_write = mv88e6xxx_g2_smi_phy_write,
3556 .port_set_link = mv88e6xxx_port_set_link,
3557 .port_set_duplex = mv88e6xxx_port_set_duplex,
3558 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3559 .port_set_speed = mv88e6390_port_set_speed,
79523473 3560 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3561 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3562 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3563 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3564 .stats_get_stats = mv88e6390_stats_get_stats,
1a3b39ec
AL		 3565};
3566
f81ec90f
VD		 3567static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3568 [MV88E6085] = {
3569 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3570 .family = MV88E6XXX_FAMILY_6097,
3571 .name = "Marvell 88E6085",
3572 .num_databases = 4096,
3573 .num_ports = 10,
9dddd478 3574 .port_base_addr = 0x10,
a935c052 3575 .global1_addr = 0x1b,
acddbd21 3576 .age_time_coeff = 15000,
dc30c35b 3577 .g1_irqs = 8,
f81ec90f 3578 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3579 .ops = &mv88e6085_ops,
f81ec90f
VD		 3580 },
3581
3582 [MV88E6095] = {
3583 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3584 .family = MV88E6XXX_FAMILY_6095,
3585 .name = "Marvell 88E6095/88E6095F",
3586 .num_databases = 256,
3587 .num_ports = 11,
9dddd478 3588 .port_base_addr = 0x10,
a935c052 3589 .global1_addr = 0x1b,
acddbd21 3590 .age_time_coeff = 15000,
dc30c35b 3591 .g1_irqs = 8,
f81ec90f 3592 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3593 .ops = &mv88e6095_ops,
f81ec90f
VD		 3594 },
3595
7d381a02
SE		 3596 [MV88E6097] = {
3597 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3598 .family = MV88E6XXX_FAMILY_6097,
3599 .name = "Marvell 88E6097/88E6097F",
3600 .num_databases = 4096,
3601 .num_ports = 11,
3602 .port_base_addr = 0x10,
3603 .global1_addr = 0x1b,
3604 .age_time_coeff = 15000,
3605 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3606 .ops = &mv88e6097_ops,
3607 },
3608
f81ec90f
VD		 3609 [MV88E6123] = {
3610 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3611 .family = MV88E6XXX_FAMILY_6165,
3612 .name = "Marvell 88E6123",
3613 .num_databases = 4096,
3614 .num_ports = 3,
9dddd478 3615 .port_base_addr = 0x10,
a935c052 3616 .global1_addr = 0x1b,
acddbd21 3617 .age_time_coeff = 15000,
dc30c35b 3618 .g1_irqs = 9,
f81ec90f 3619 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3620 .ops = &mv88e6123_ops,
f81ec90f
VD		 3621 },
3622
3623 [MV88E6131] = {
3624 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3625 .family = MV88E6XXX_FAMILY_6185,
3626 .name = "Marvell 88E6131",
3627 .num_databases = 256,
3628 .num_ports = 8,
9dddd478 3629 .port_base_addr = 0x10,
a935c052 3630 .global1_addr = 0x1b,
acddbd21 3631 .age_time_coeff = 15000,
dc30c35b 3632 .g1_irqs = 9,
f81ec90f 3633 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3634 .ops = &mv88e6131_ops,
f81ec90f
VD		 3635 },
3636
3637 [MV88E6161] = {
3638 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3639 .family = MV88E6XXX_FAMILY_6165,
3640 .name = "Marvell 88E6161",
3641 .num_databases = 4096,
3642 .num_ports = 6,
9dddd478 3643 .port_base_addr = 0x10,
a935c052 3644 .global1_addr = 0x1b,
acddbd21 3645 .age_time_coeff = 15000,
dc30c35b 3646 .g1_irqs = 9,
f81ec90f 3647 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3648 .ops = &mv88e6161_ops,
f81ec90f
VD		 3649 },
3650
3651 [MV88E6165] = {
3652 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3653 .family = MV88E6XXX_FAMILY_6165,
3654 .name = "Marvell 88E6165",
3655 .num_databases = 4096,
3656 .num_ports = 6,
9dddd478 3657 .port_base_addr = 0x10,
a935c052 3658 .global1_addr = 0x1b,
acddbd21 3659 .age_time_coeff = 15000,
dc30c35b 3660 .g1_irqs = 9,
f81ec90f 3661 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3662 .ops = &mv88e6165_ops,
f81ec90f
VD		 3663 },
3664
3665 [MV88E6171] = {
3666 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3667 .family = MV88E6XXX_FAMILY_6351,
3668 .name = "Marvell 88E6171",
3669 .num_databases = 4096,
3670 .num_ports = 7,
9dddd478 3671 .port_base_addr = 0x10,
a935c052 3672 .global1_addr = 0x1b,
acddbd21 3673 .age_time_coeff = 15000,
dc30c35b 3674 .g1_irqs = 9,
f81ec90f 3675 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3676 .ops = &mv88e6171_ops,
f81ec90f
VD		 3677 },
3678
3679 [MV88E6172] = {
3680 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3681 .family = MV88E6XXX_FAMILY_6352,
3682 .name = "Marvell 88E6172",
3683 .num_databases = 4096,
3684 .num_ports = 7,
9dddd478 3685 .port_base_addr = 0x10,
a935c052 3686 .global1_addr = 0x1b,
acddbd21 3687 .age_time_coeff = 15000,
dc30c35b 3688 .g1_irqs = 9,
f81ec90f 3689 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3690 .ops = &mv88e6172_ops,
f81ec90f
VD		 3691 },
3692
3693 [MV88E6175] = {
3694 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3695 .family = MV88E6XXX_FAMILY_6351,
3696 .name = "Marvell 88E6175",
3697 .num_databases = 4096,
3698 .num_ports = 7,
9dddd478 3699 .port_base_addr = 0x10,
a935c052 3700 .global1_addr = 0x1b,
acddbd21 3701 .age_time_coeff = 15000,
dc30c35b 3702 .g1_irqs = 9,
f81ec90f 3703 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3704 .ops = &mv88e6175_ops,
f81ec90f
VD		 3705 },
3706
3707 [MV88E6176] = {
3708 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3709 .family = MV88E6XXX_FAMILY_6352,
3710 .name = "Marvell 88E6176",
3711 .num_databases = 4096,
3712 .num_ports = 7,
9dddd478 3713 .port_base_addr = 0x10,
a935c052 3714 .global1_addr = 0x1b,
acddbd21 3715 .age_time_coeff = 15000,
dc30c35b 3716 .g1_irqs = 9,
f81ec90f 3717 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3718 .ops = &mv88e6176_ops,
f81ec90f
VD		 3719 },
3720
3721 [MV88E6185] = {
3722 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3723 .family = MV88E6XXX_FAMILY_6185,
3724 .name = "Marvell 88E6185",
3725 .num_databases = 256,
3726 .num_ports = 10,
9dddd478 3727 .port_base_addr = 0x10,
a935c052 3728 .global1_addr = 0x1b,
acddbd21 3729 .age_time_coeff = 15000,
dc30c35b 3730 .g1_irqs = 8,
f81ec90f 3731 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3732 .ops = &mv88e6185_ops,
f81ec90f
VD		 3733 },
3734
1a3b39ec
AL		 3735 [MV88E6190] = {
3736 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3737 .family = MV88E6XXX_FAMILY_6390,
3738 .name = "Marvell 88E6190",
3739 .num_databases = 4096,
3740 .num_ports = 11, /* 10 + Z80 */
3741 .port_base_addr = 0x0,
3742 .global1_addr = 0x1b,
3743 .age_time_coeff = 15000,
3744 .g1_irqs = 9,
3745 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3746 .ops = &mv88e6190_ops,
3747 },
3748
3749 [MV88E6190X] = {
3750 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3751 .family = MV88E6XXX_FAMILY_6390,
3752 .name = "Marvell 88E6190X",
3753 .num_databases = 4096,
3754 .num_ports = 11, /* 10 + Z80 */
3755 .port_base_addr = 0x0,
3756 .global1_addr = 0x1b,
3757 .age_time_coeff = 15000,
3758 .g1_irqs = 9,
3759 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3760 .ops = &mv88e6190x_ops,
3761 },
3762
3763 [MV88E6191] = {
3764 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3765 .family = MV88E6XXX_FAMILY_6390,
3766 .name = "Marvell 88E6191",
3767 .num_databases = 4096,
3768 .num_ports = 11, /* 10 + Z80 */
3769 .port_base_addr = 0x0,
3770 .global1_addr = 0x1b,
3771 .age_time_coeff = 15000,
3772 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3773 .ops = &mv88e6391_ops,
3774 },
3775
f81ec90f
VD		 3776 [MV88E6240] = {
3777 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3778 .family = MV88E6XXX_FAMILY_6352,
3779 .name = "Marvell 88E6240",
3780 .num_databases = 4096,
3781 .num_ports = 7,
9dddd478 3782 .port_base_addr = 0x10,
a935c052 3783 .global1_addr = 0x1b,
acddbd21 3784 .age_time_coeff = 15000,
dc30c35b 3785 .g1_irqs = 9,
f81ec90f 3786 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3787 .ops = &mv88e6240_ops,
f81ec90f
VD		 3788 },
3789
1a3b39ec
AL		 3790 [MV88E6290] = {
3791 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3792 .family = MV88E6XXX_FAMILY_6390,
3793 .name = "Marvell 88E6290",
3794 .num_databases = 4096,
3795 .num_ports = 11, /* 10 + Z80 */
3796 .port_base_addr = 0x0,
3797 .global1_addr = 0x1b,
3798 .age_time_coeff = 15000,
3799 .g1_irqs = 9,
3800 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3801 .ops = &mv88e6290_ops,
3802 },
3803
f81ec90f
VD		 3804 [MV88E6320] = {
3805 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3806 .family = MV88E6XXX_FAMILY_6320,
3807 .name = "Marvell 88E6320",
3808 .num_databases = 4096,
3809 .num_ports = 7,
9dddd478 3810 .port_base_addr = 0x10,
a935c052 3811 .global1_addr = 0x1b,
acddbd21 3812 .age_time_coeff = 15000,
dc30c35b 3813 .g1_irqs = 8,
f81ec90f 3814 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3815 .ops = &mv88e6320_ops,
f81ec90f
VD		 3816 },
3817
3818 [MV88E6321] = {
3819 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3820 .family = MV88E6XXX_FAMILY_6320,
3821 .name = "Marvell 88E6321",
3822 .num_databases = 4096,
3823 .num_ports = 7,
9dddd478 3824 .port_base_addr = 0x10,
a935c052 3825 .global1_addr = 0x1b,
acddbd21 3826 .age_time_coeff = 15000,
dc30c35b 3827 .g1_irqs = 8,
f81ec90f 3828 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3829 .ops = &mv88e6321_ops,
f81ec90f
VD		 3830 },
3831
3832 [MV88E6350] = {
3833 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3834 .family = MV88E6XXX_FAMILY_6351,
3835 .name = "Marvell 88E6350",
3836 .num_databases = 4096,
3837 .num_ports = 7,
9dddd478 3838 .port_base_addr = 0x10,
a935c052 3839 .global1_addr = 0x1b,
acddbd21 3840 .age_time_coeff = 15000,
dc30c35b 3841 .g1_irqs = 9,
f81ec90f 3842 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3843 .ops = &mv88e6350_ops,
f81ec90f
VD		 3844 },
3845
3846 [MV88E6351] = {
3847 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3848 .family = MV88E6XXX_FAMILY_6351,
3849 .name = "Marvell 88E6351",
3850 .num_databases = 4096,
3851 .num_ports = 7,
9dddd478 3852 .port_base_addr = 0x10,
a935c052 3853 .global1_addr = 0x1b,
acddbd21 3854 .age_time_coeff = 15000,
dc30c35b 3855 .g1_irqs = 9,
f81ec90f 3856 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3857 .ops = &mv88e6351_ops,
f81ec90f
VD		 3858 },
3859
3860 [MV88E6352] = {
3861 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3862 .family = MV88E6XXX_FAMILY_6352,
3863 .name = "Marvell 88E6352",
3864 .num_databases = 4096,
3865 .num_ports = 7,
9dddd478 3866 .port_base_addr = 0x10,
a935c052 3867 .global1_addr = 0x1b,
acddbd21 3868 .age_time_coeff = 15000,
dc30c35b 3869 .g1_irqs = 9,
f81ec90f 3870 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3871 .ops = &mv88e6352_ops,
f81ec90f 3872 },
1a3b39ec
AL		 3873 [MV88E6390] = {
3874 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3875 .family = MV88E6XXX_FAMILY_6390,
3876 .name = "Marvell 88E6390",
3877 .num_databases = 4096,
3878 .num_ports = 11, /* 10 + Z80 */
3879 .port_base_addr = 0x0,
3880 .global1_addr = 0x1b,
3881 .age_time_coeff = 15000,
3882 .g1_irqs = 9,
3883 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3884 .ops = &mv88e6390_ops,
3885 },
3886 [MV88E6390X] = {
3887 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3888 .family = MV88E6XXX_FAMILY_6390,
3889 .name = "Marvell 88E6390X",
3890 .num_databases = 4096,
3891 .num_ports = 11, /* 10 + Z80 */
3892 .port_base_addr = 0x0,
3893 .global1_addr = 0x1b,
3894 .age_time_coeff = 15000,
3895 .g1_irqs = 9,
3896 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3897 .ops = &mv88e6390x_ops,
3898 },
f81ec90f
VD		 3899};
3900
5f7c0367 3901static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3902{
a439c061 3903 int i;
b9b37713 3904
5f7c0367
VD		 3905 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3906 if (mv88e6xxx_table[i].prod_num == prod_num)
3907 return &mv88e6xxx_table[i];
b9b37713 3908
b9b37713
VD		 3909 return NULL;
3910}
3911
fad09c73 3912static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3913{
3914 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3915 unsigned int prod_num, rev;
3916 u16 id;
3917 int err;
bc46a3d5 3918
8f6345b2
VD		 3919 mutex_lock(&chip->reg_lock);
3920 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3921 mutex_unlock(&chip->reg_lock);
3922 if (err)
3923 return err;
bc46a3d5
VD		 3924
3925 prod_num = (id & 0xfff0) >> 4;
3926 rev = id & 0x000f;
3927
3928 info = mv88e6xxx_lookup_info(prod_num);
3929 if (!info)
3930 return -ENODEV;
3931
caac8545 3932 /* Update the compatible info with the probed one */
fad09c73 3933 chip->info = info;
bc46a3d5 3934
ca070c10
VD		 3935 err = mv88e6xxx_g2_require(chip);
3936 if (err)
3937 return err;
3938
fad09c73
VD		 3939 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3940 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3941
3942 return 0;
3943}
3944
fad09c73 3945static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3946{
fad09c73 3947 struct mv88e6xxx_chip *chip;
469d729f 3948
fad09c73
VD		 3949 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3950 if (!chip)
469d729f
VD		 3951 return NULL;
3952
fad09c73 3953 chip->dev = dev;
469d729f 3954
fad09c73 3955 mutex_init(&chip->reg_lock);
469d729f 3956
fad09c73 3957 return chip;
469d729f
VD		 3958}
3959
e57e5e77
VD		 3960static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3961{
b3469dd8 3962 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
e57e5e77 3963 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 3964}
3965
930188ce
AL		 3966static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3967{
b3469dd8 3968 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
930188ce 3969 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 3970}
3971
fad09c73 3972static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3973 struct mii_bus *bus, int sw_addr)
3974{
3975 /* ADDR[0] pin is unavailable externally and considered zero */
3976 if (sw_addr & 0x1)
3977 return -EINVAL;
3978
914b32f6 3979 if (sw_addr == 0)
fad09c73 3980 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3981 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3982 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3983 else
3984 return -EINVAL;
3985
fad09c73
VD		 3986 chip->bus = bus;
3987 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3988
3989 return 0;
3990}
3991
7b314362
AL		 3992static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3993{
04bed143 3994 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be
AL		 3995
3996 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3997 return DSA_TAG_PROTO_EDSA;
3998
3999 return DSA_TAG_PROTO_DSA;
7b314362
AL		 4000}
4001
fcdce7d0
AL		 4002static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4003 struct device *host_dev, int sw_addr,
4004 void **priv)
a77d43f1 4005{
fad09c73 4006 struct mv88e6xxx_chip *chip;
a439c061 4007 struct mii_bus *bus;
b516d453 4008 int err;
a77d43f1 4009
a439c061 4010 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4011 if (!bus)
4012 return NULL;
4013
fad09c73
VD		 4014 chip = mv88e6xxx_alloc_chip(dsa_dev);
4015 if (!chip)
469d729f
VD		 4016 return NULL;
4017
caac8545 4018 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4019 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4020
fad09c73 4021 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4022 if (err)
4023 goto free;
4024
fad09c73 4025 err = mv88e6xxx_detect(chip);
bc46a3d5 4026 if (err)
469d729f 4027 goto free;
a439c061 4028
dc30c35b
AL		 4029 mutex_lock(&chip->reg_lock);
4030 err = mv88e6xxx_switch_reset(chip);
4031 mutex_unlock(&chip->reg_lock);
4032 if (err)
4033 goto free;
4034
e57e5e77
VD		 4035 mv88e6xxx_phy_init(chip);
4036
fad09c73 4037 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 4038 if (err)
469d729f 4039 goto free;
b516d453 4040
fad09c73 4041 *priv = chip;
a439c061 4042
fad09c73 4043 return chip->info->name;
469d729f 4044free:
fad09c73 4045 devm_kfree(dsa_dev, chip);
469d729f
VD		 4046
4047 return NULL;
a77d43f1
AL		 4048}
4049
7df8fbdd
VD		 4050static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4051 const struct switchdev_obj_port_mdb *mdb,
4052 struct switchdev_trans *trans)
4053{
4054 /* We don't need any dynamic resource from the kernel (yet),
4055 * so skip the prepare phase.
4056 */
4057
4058 return 0;
4059}
4060
4061static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4062 const struct switchdev_obj_port_mdb *mdb,
4063 struct switchdev_trans *trans)
4064{
04bed143 4065 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4066
4067 mutex_lock(&chip->reg_lock);
4068 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4069 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4070 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4071 mutex_unlock(&chip->reg_lock);
4072}
4073
4074static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4075 const struct switchdev_obj_port_mdb *mdb)
4076{
04bed143 4077 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4078 int err;
4079
4080 mutex_lock(&chip->reg_lock);
4081 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4082 GLOBAL_ATU_DATA_STATE_UNUSED);
4083 mutex_unlock(&chip->reg_lock);
4084
4085 return err;
4086}
4087
4088static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4089 struct switchdev_obj_port_mdb *mdb,
4090 int (*cb)(struct switchdev_obj *obj))
4091{
04bed143 4092 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4093 int err;
4094
4095 mutex_lock(&chip->reg_lock);
4096 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4097 mutex_unlock(&chip->reg_lock);
4098
4099 return err;
4100}
4101
9d490b4e 4102static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4103 .probe = mv88e6xxx_drv_probe,
7b314362 4104 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4105 .setup = mv88e6xxx_setup,
4106 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4107 .adjust_link = mv88e6xxx_adjust_link,
4108 .get_strings = mv88e6xxx_get_strings,
4109 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4110 .get_sset_count = mv88e6xxx_get_sset_count,
4111 .set_eee = mv88e6xxx_set_eee,
4112 .get_eee = mv88e6xxx_get_eee,
4113#ifdef CONFIG_NET_DSA_HWMON
4114 .get_temp = mv88e6xxx_get_temp,
4115 .get_temp_limit = mv88e6xxx_get_temp_limit,
4116 .set_temp_limit = mv88e6xxx_set_temp_limit,
4117 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
4118#endif
f8cd8753 4119 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4120 .get_eeprom = mv88e6xxx_get_eeprom,
4121 .set_eeprom = mv88e6xxx_set_eeprom,
4122 .get_regs_len = mv88e6xxx_get_regs_len,
4123 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4124 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4125 .port_bridge_join = mv88e6xxx_port_bridge_join,
4126 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4127 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4128 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4129 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4130 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4131 .port_vlan_add = mv88e6xxx_port_vlan_add,
4132 .port_vlan_del = mv88e6xxx_port_vlan_del,
4133 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4134 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4135 .port_fdb_add = mv88e6xxx_port_fdb_add,
4136 .port_fdb_del = mv88e6xxx_port_fdb_del,
4137 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4138 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4139 .port_mdb_add = mv88e6xxx_port_mdb_add,
4140 .port_mdb_del = mv88e6xxx_port_mdb_del,
4141 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4142};
4143
fad09c73 4144static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 4145 struct device_node *np)
4146{
fad09c73 4147 struct device *dev = chip->dev;
b7e66a5f
VD		 4148 struct dsa_switch *ds;
4149
4150 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4151 if (!ds)
4152 return -ENOMEM;
4153
4154 ds->dev = dev;
fad09c73 4155 ds->priv = chip;
9d490b4e 4156 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4157
4158 dev_set_drvdata(dev, ds);
4159
4160 return dsa_register_switch(ds, np);
4161}
4162
fad09c73 4163static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4164{
fad09c73 4165 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4166}
4167
57d32310 4168static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4169{
14c7b3c3 4170 struct device *dev = &mdiodev->dev;
f8cd8753 4171 struct device_node *np = dev->of_node;
caac8545 4172 const struct mv88e6xxx_info *compat_info;
fad09c73 4173 struct mv88e6xxx_chip *chip;
f8cd8753 4174 u32 eeprom_len;
52638f71 4175 int err;
14c7b3c3 4176
caac8545
VD		 4177 compat_info = of_device_get_match_data(dev);
4178 if (!compat_info)
4179 return -EINVAL;
4180
fad09c73
VD		 4181 chip = mv88e6xxx_alloc_chip(dev);
4182 if (!chip)
14c7b3c3
AL		 4183 return -ENOMEM;
4184
fad09c73 4185 chip->info = compat_info;
caac8545 4186
fad09c73 4187 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4188 if (err)
4189 return err;
14c7b3c3 4190
b4308f04
AL		 4191 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4192 if (IS_ERR(chip->reset))
4193 return PTR_ERR(chip->reset);
4194
fad09c73 4195 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4196 if (err)
4197 return err;
14c7b3c3 4198
e57e5e77
VD		 4199 mv88e6xxx_phy_init(chip);
4200
ee4dc2e7 4201 if (chip->info->ops->get_eeprom &&
f8cd8753 4202 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4203 chip->eeprom_len = eeprom_len;
f8cd8753 4204
dc30c35b
AL		 4205 mutex_lock(&chip->reg_lock);
4206 err = mv88e6xxx_switch_reset(chip);
4207 mutex_unlock(&chip->reg_lock);
4208 if (err)
4209 goto out;
4210
4211 chip->irq = of_irq_get(np, 0);
4212 if (chip->irq == -EPROBE_DEFER) {
4213 err = chip->irq;
4214 goto out;
4215 }
4216
4217 if (chip->irq > 0) {
4218 /* Has to be performed before the MDIO bus is created,
4219 * because the PHYs will link there interrupts to these
4220 * interrupt controllers
4221 */
4222 mutex_lock(&chip->reg_lock);
4223 err = mv88e6xxx_g1_irq_setup(chip);
4224 mutex_unlock(&chip->reg_lock);
4225
4226 if (err)
4227 goto out;
4228
4229 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4230 err = mv88e6xxx_g2_irq_setup(chip);
4231 if (err)
4232 goto out_g1_irq;
4233 }
4234 }
4235
fad09c73 4236 err = mv88e6xxx_mdio_register(chip, np);
b516d453 4237 if (err)
dc30c35b 4238 goto out_g2_irq;
b516d453 4239
fad09c73 4240 err = mv88e6xxx_register_switch(chip, np);
dc30c35b
AL		 4241 if (err)
4242 goto out_mdio;
83c0afae 4243
98e67308 4244 return 0;
dc30c35b
AL		 4245
4246out_mdio:
4247 mv88e6xxx_mdio_unregister(chip);
4248out_g2_irq:
46712644 4249 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4250 mv88e6xxx_g2_irq_free(chip);
4251out_g1_irq:
61f7c3f8
AL		 4252 if (chip->irq > 0) {
4253 mutex_lock(&chip->reg_lock);
46712644 4254 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4255 mutex_unlock(&chip->reg_lock);
4256 }
dc30c35b
AL		 4257out:
4258 return err;
98e67308 4259}
14c7b3c3
AL		 4260
4261static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4262{
4263 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4264 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4265
930188ce 4266 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 4267 mv88e6xxx_unregister_switch(chip);
4268 mv88e6xxx_mdio_unregister(chip);
dc30c35b 4269
46712644
AL		 4270 if (chip->irq > 0) {
4271 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4272 mv88e6xxx_g2_irq_free(chip);
4273 mv88e6xxx_g1_irq_free(chip);
4274 }
14c7b3c3
AL		 4275}
4276
4277static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4278 {
4279 .compatible = "marvell,mv88e6085",
4280 .data = &mv88e6xxx_table[MV88E6085],
4281 },
1a3b39ec
AL		 4282 {
4283 .compatible = "marvell,mv88e6190",
4284 .data = &mv88e6xxx_table[MV88E6190],
4285 },
14c7b3c3
AL		 4286 { /* sentinel */ },
4287};
4288
4289MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4290
4291static struct mdio_driver mv88e6xxx_driver = {
4292 .probe = mv88e6xxx_probe,
4293 .remove = mv88e6xxx_remove,
4294 .mdiodrv.driver = {
4295 .name = "mv88e6085",
4296 .of_match_table = mv88e6xxx_of_match,
4297 },
4298};
4299
4300static int __init mv88e6xxx_init(void)
4301{
9d490b4e 4302 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 4303 return mdio_driver_register(&mv88e6xxx_driver);
4304}
98e67308
BH		 4305module_init(mv88e6xxx_init);
4306
4307static void __exit mv88e6xxx_cleanup(void)
4308{
14c7b3c3 4309 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 4310 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 4311}
4312module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4313
4314MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4315MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4316MODULE_LICENSE("GPL");
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