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[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
4333d619
VD		 11 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
12 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
13 *
91da11f8
LB		 14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 */
19
19b2f97e 20#include <linux/delay.h>
defb05b9 21#include <linux/etherdevice.h>
dea87024 22#include <linux/ethtool.h>
facd95b2 23#include <linux/if_bridge.h>
dc30c35b
AL		 24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/irqdomain.h>
19b2f97e 27#include <linux/jiffies.h>
91da11f8 28#include <linux/list.h>
14c7b3c3 29#include <linux/mdio.h>
2bbba277 30#include <linux/module.h>
caac8545 31#include <linux/of_device.h>
dc30c35b 32#include <linux/of_irq.h>
b516d453 33#include <linux/of_mdio.h>
91da11f8 34#include <linux/netdevice.h>
c8c1b39a 35#include <linux/gpio/consumer.h>
91da11f8 36#include <linux/phy.h>
c8f0b869 37#include <net/dsa.h>
1f36faf2 38#include <net/switchdev.h>
ec561276 39
91da11f8 40#include "mv88e6xxx.h"
a935c052 41#include "global1.h"
ec561276 42#include "global2.h"
18abed21 43#include "port.h"
91da11f8 44
fad09c73 45static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 46{
fad09c73
VD		 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 49 dump_stack();
50 }
51}
52
914b32f6
VD		 53/* The switch ADDR[4:1] configuration pins define the chip SMI device address
54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
55 *
56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
57 * is the only device connected to the SMI master. In this mode it responds to
58 * all 32 possible SMI addresses, and thus maps directly the internal devices.
59 *
60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
61 * multiple devices to share the SMI interface. In this mode it responds to only
62 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 63 */
914b32f6 64
fad09c73 65static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 66 int addr, int reg, u16 *val)
67{
fad09c73 68 if (!chip->smi_ops)
914b32f6
VD		 69 return -EOPNOTSUPP;
70
fad09c73 71 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 72}
73
fad09c73 74static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 75 int addr, int reg, u16 val)
76{
fad09c73 77 if (!chip->smi_ops)
914b32f6
VD		 78 return -EOPNOTSUPP;
79
fad09c73 80 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 81}
82
fad09c73 83static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 84 int addr, int reg, u16 *val)
85{
86 int ret;
87
fad09c73 88 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 89 if (ret < 0)
90 return ret;
91
92 *val = ret & 0xffff;
93
94 return 0;
95}
96
fad09c73 97static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 98 int addr, int reg, u16 val)
99{
100 int ret;
101
fad09c73 102 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 103 if (ret < 0)
104 return ret;
105
106 return 0;
107}
108
c08026ab 109static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 110 .read = mv88e6xxx_smi_single_chip_read,
111 .write = mv88e6xxx_smi_single_chip_write,
112};
113
fad09c73 114static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 115{
116 int ret;
117 int i;
118
119 for (i = 0; i < 16; i++) {
fad09c73 120 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 121 if (ret < 0)
122 return ret;
123
cca8b133 124 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 125 return 0;
126 }
127
128 return -ETIMEDOUT;
129}
130
fad09c73 131static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 132 int addr, int reg, u16 *val)
91da11f8
LB		 133{
134 int ret;
135
3675c8d7 136 /* Wait for the bus to become free. */
fad09c73 137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 138 if (ret < 0)
139 return ret;
140
3675c8d7 141 /* Transmit the read command. */
fad09c73 142 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 143 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 144 if (ret < 0)
145 return ret;
146
3675c8d7 147 /* Wait for the read command to complete. */
fad09c73 148 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 149 if (ret < 0)
150 return ret;
151
3675c8d7 152 /* Read the data. */
fad09c73 153 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 154 if (ret < 0)
155 return ret;
156
914b32f6 157 *val = ret & 0xffff;
91da11f8 158
914b32f6 159 return 0;
8d6d09e7
GR		 160}
161
fad09c73 162static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 163 int addr, int reg, u16 val)
91da11f8
LB		 164{
165 int ret;
166
3675c8d7 167 /* Wait for the bus to become free. */
fad09c73 168 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 169 if (ret < 0)
170 return ret;
171
3675c8d7 172 /* Transmit the data to write. */
fad09c73 173 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 174 if (ret < 0)
175 return ret;
176
3675c8d7 177 /* Transmit the write command. */
fad09c73 178 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 179 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 180 if (ret < 0)
181 return ret;
182
3675c8d7 183 /* Wait for the write command to complete. */
fad09c73 184 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 185 if (ret < 0)
186 return ret;
187
188 return 0;
189}
190
c08026ab 191static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 192 .read = mv88e6xxx_smi_multi_chip_read,
193 .write = mv88e6xxx_smi_multi_chip_write,
194};
195
ec561276 196int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 197{
198 int err;
199
fad09c73 200 assert_reg_lock(chip);
914b32f6 201
fad09c73 202 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 203 if (err)
204 return err;
205
fad09c73 206 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 207 addr, reg, *val);
208
209 return 0;
210}
211
ec561276 212int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 213{
914b32f6
VD		 214 int err;
215
fad09c73 216 assert_reg_lock(chip);
91da11f8 217
fad09c73 218 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 219 if (err)
220 return err;
221
fad09c73 222 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 223 addr, reg, val);
224
914b32f6
VD		 225 return 0;
226}
227
ee26a228
AL		 228static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
229 struct mii_bus *bus,
230 int addr, int reg, u16 *val)
efb3e74d
AL		 231{
232 return mv88e6xxx_read(chip, addr, reg, val);
233}
234
ee26a228
AL		 235static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
236 struct mii_bus *bus,
237 int addr, int reg, u16 val)
efb3e74d
AL		 238{
239 return mv88e6xxx_write(chip, addr, reg, val);
240}
241
a3c53be5
AL		 242static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
243{
244 struct mv88e6xxx_mdio_bus *mdio_bus;
245
246 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
247 list);
248 if (!mdio_bus)
249 return NULL;
250
251 return mdio_bus->bus;
252}
253
e57e5e77
VD		 254static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
255 int reg, u16 *val)
256{
257 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 258 struct mii_bus *bus;
e57e5e77 259
a3c53be5
AL		 260 bus = mv88e6xxx_default_mdio_bus(chip);
261 if (!bus)
e57e5e77
VD		 262 return -EOPNOTSUPP;
263
a3c53be5 264 if (!chip->info->ops->phy_read)
ee26a228
AL		 265 return -EOPNOTSUPP;
266
267 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 268}
269
270static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
271 int reg, u16 val)
272{
273 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 274 struct mii_bus *bus;
e57e5e77 275
a3c53be5
AL		 276 bus = mv88e6xxx_default_mdio_bus(chip);
277 if (!bus)
e57e5e77
VD		 278 return -EOPNOTSUPP;
279
a3c53be5 280 if (!chip->info->ops->phy_write)
ee26a228
AL		 281 return -EOPNOTSUPP;
282
283 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 284}
285
09cb7dfd
VD		 286static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
287{
288 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
289 return -EOPNOTSUPP;
290
291 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
292}
293
294static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
295{
296 int err;
297
298 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
299 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
300 if (unlikely(err)) {
301 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
302 phy, err);
303 }
304}
305
306static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
307 u8 page, int reg, u16 *val)
308{
309 int err;
310
311 /* There is no paging for registers 22 */
312 if (reg == PHY_PAGE)
313 return -EINVAL;
314
315 err = mv88e6xxx_phy_page_get(chip, phy, page);
316 if (!err) {
317 err = mv88e6xxx_phy_read(chip, phy, reg, val);
318 mv88e6xxx_phy_page_put(chip, phy);
319 }
320
321 return err;
322}
323
324static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
325 u8 page, int reg, u16 val)
326{
327 int err;
328
329 /* There is no paging for registers 22 */
330 if (reg == PHY_PAGE)
331 return -EINVAL;
332
333 err = mv88e6xxx_phy_page_get(chip, phy, page);
334 if (!err) {
335 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
336 mv88e6xxx_phy_page_put(chip, phy);
337 }
338
339 return err;
340}
341
342static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
343{
344 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
345 reg, val);
346}
347
348static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
349{
350 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
351 reg, val);
352}
353
dc30c35b
AL		 354static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
355{
356 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
357 unsigned int n = d->hwirq;
358
359 chip->g1_irq.masked |= (1 << n);
360}
361
362static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
363{
364 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
365 unsigned int n = d->hwirq;
366
367 chip->g1_irq.masked &= ~(1 << n);
368}
369
370static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
371{
372 struct mv88e6xxx_chip *chip = dev_id;
373 unsigned int nhandled = 0;
374 unsigned int sub_irq;
375 unsigned int n;
376 u16 reg;
377 int err;
378
379 mutex_lock(&chip->reg_lock);
380 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
381 mutex_unlock(&chip->reg_lock);
382
383 if (err)
384 goto out;
385
386 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
387 if (reg & (1 << n)) {
388 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
389 handle_nested_irq(sub_irq);
390 ++nhandled;
391 }
392 }
393out:
394 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
395}
396
397static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
398{
399 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
400
401 mutex_lock(&chip->reg_lock);
402}
403
404static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
405{
406 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
407 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
408 u16 reg;
409 int err;
410
411 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
412 if (err)
413 goto out;
414
415 reg &= ~mask;
416 reg |= (~chip->g1_irq.masked & mask);
417
418 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
419 if (err)
420 goto out;
421
422out:
423 mutex_unlock(&chip->reg_lock);
424}
425
426static struct irq_chip mv88e6xxx_g1_irq_chip = {
427 .name = "mv88e6xxx-g1",
428 .irq_mask = mv88e6xxx_g1_irq_mask,
429 .irq_unmask = mv88e6xxx_g1_irq_unmask,
430 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
431 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
432};
433
434static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
435 unsigned int irq,
436 irq_hw_number_t hwirq)
437{
438 struct mv88e6xxx_chip *chip = d->host_data;
439
440 irq_set_chip_data(irq, d->host_data);
441 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
442 irq_set_noprobe(irq);
443
444 return 0;
445}
446
447static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
448 .map = mv88e6xxx_g1_irq_domain_map,
449 .xlate = irq_domain_xlate_twocell,
450};
451
452static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
453{
454 int irq, virq;
3460a577
AL		 455 u16 mask;
456
457 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
458 mask |= GENMASK(chip->g1_irq.nirqs, 0);
459 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
460
461 free_irq(chip->irq, chip);
dc30c35b 462
5edef2f2 463 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 464 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 465 irq_dispose_mapping(virq);
466 }
467
a3db3d3a 468 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 469}
470
471static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
472{
3dd0ef05
AL		 473 int err, irq, virq;
474 u16 reg, mask;
dc30c35b
AL		 475
476 chip->g1_irq.nirqs = chip->info->g1_irqs;
477 chip->g1_irq.domain = irq_domain_add_simple(
478 NULL, chip->g1_irq.nirqs, 0,
479 &mv88e6xxx_g1_irq_domain_ops, chip);
480 if (!chip->g1_irq.domain)
481 return -ENOMEM;
482
483 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
484 irq_create_mapping(chip->g1_irq.domain, irq);
485
486 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
487 chip->g1_irq.masked = ~0;
488
3dd0ef05 489 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 490 if (err)
3dd0ef05 491 goto out_mapping;
dc30c35b 492
3dd0ef05 493 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 494
3dd0ef05 495 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 496 if (err)
3dd0ef05 497 goto out_disable;
dc30c35b
AL		 498
499 /* Reading the interrupt status clears (most of) them */
500 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
501 if (err)
3dd0ef05 502 goto out_disable;
dc30c35b
AL		 503
504 err = request_threaded_irq(chip->irq, NULL,
505 mv88e6xxx_g1_irq_thread_fn,
506 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
507 dev_name(chip->dev), chip);
508 if (err)
3dd0ef05 509 goto out_disable;
dc30c35b
AL		 510
511 return 0;
512
3dd0ef05
AL		 513out_disable:
514 mask |= GENMASK(chip->g1_irq.nirqs, 0);
515 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
516
517out_mapping:
518 for (irq = 0; irq < 16; irq++) {
519 virq = irq_find_mapping(chip->g1_irq.domain, irq);
520 irq_dispose_mapping(virq);
521 }
522
523 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 524
525 return err;
526}
527
ec561276 528int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 529{
6441e669 530 int i;
2d79af6e 531
6441e669 532 for (i = 0; i < 16; i++) {
2d79af6e
VD		 533 u16 val;
534 int err;
535
536 err = mv88e6xxx_read(chip, addr, reg, &val);
537 if (err)
538 return err;
539
540 if (!(val & mask))
541 return 0;
542
543 usleep_range(1000, 2000);
544 }
545
30853553 546 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 547 return -ETIMEDOUT;
548}
549
f22ab641 550/* Indirect write to single pointer-data register with an Update bit */
ec561276 551int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 552{
553 u16 val;
0f02b4f7 554 int err;
f22ab641
VD		 555
556 /* Wait until the previous operation is completed */
0f02b4f7
AL		 557 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
558 if (err)
559 return err;
f22ab641
VD		 560
561 /* Set the Update bit to trigger a write operation */
562 val = BIT(15) | update;
563
564 return mv88e6xxx_write(chip, addr, reg, val);
565}
566
a935c052 567static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 568{
a199d8b6
VD		 569 if (!chip->info->ops->ppu_disable)
570 return 0;
2e5f0320 571
a199d8b6 572 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 573}
574
fad09c73 575static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 576{
a199d8b6
VD		 577 if (!chip->info->ops->ppu_enable)
578 return 0;
2e5f0320 579
a199d8b6 580 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 581}
582
583static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
584{
fad09c73 585 struct mv88e6xxx_chip *chip;
2e5f0320 586
fad09c73 587 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 588
fad09c73 589 mutex_lock(&chip->reg_lock);
762eb67b 590
fad09c73
VD		 591 if (mutex_trylock(&chip->ppu_mutex)) {
592 if (mv88e6xxx_ppu_enable(chip) == 0)
593 chip->ppu_disabled = 0;
594 mutex_unlock(&chip->ppu_mutex);
2e5f0320 595 }
762eb67b 596
fad09c73 597 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 598}
599
600static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
601{
fad09c73 602 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 603
fad09c73 604 schedule_work(&chip->ppu_work);
2e5f0320
LB		 605}
606
fad09c73 607static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 608{
2e5f0320
LB		 609 int ret;
610
fad09c73 611 mutex_lock(&chip->ppu_mutex);
2e5f0320 612
3675c8d7 613 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 614 * we can access the PHY registers. If it was already
615 * disabled, cancel the timer that is going to re-enable
616 * it.
617 */
fad09c73
VD		 618 if (!chip->ppu_disabled) {
619 ret = mv88e6xxx_ppu_disable(chip);
85686581 620 if (ret < 0) {
fad09c73 621 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 622 return ret;
623 }
fad09c73 624 chip->ppu_disabled = 1;
2e5f0320 625 } else {
fad09c73 626 del_timer(&chip->ppu_timer);
85686581 627 ret = 0;
2e5f0320
LB		 628 }
629
630 return ret;
631}
632
fad09c73 633static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 634{
3675c8d7 635 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 636 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
637 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 638}
639
fad09c73 640static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 641{
fad09c73
VD		 642 mutex_init(&chip->ppu_mutex);
643 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 644 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
645 (unsigned long)chip);
2e5f0320
LB		 646}
647
930188ce
AL		 648static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
649{
650 del_timer_sync(&chip->ppu_timer);
651}
652
ee26a228
AL		 653static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
654 struct mii_bus *bus,
655 int addr, int reg, u16 *val)
2e5f0320 656{
e57e5e77 657 int err;
2e5f0320 658
e57e5e77
VD		 659 err = mv88e6xxx_ppu_access_get(chip);
660 if (!err) {
661 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 662 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 663 }
664
e57e5e77 665 return err;
2e5f0320
LB		 666}
667
ee26a228
AL		 668static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
669 struct mii_bus *bus,
670 int addr, int reg, u16 val)
2e5f0320 671{
e57e5e77 672 int err;
2e5f0320 673
e57e5e77
VD		 674 err = mv88e6xxx_ppu_access_get(chip);
675 if (!err) {
676 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 677 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 678 }
679
e57e5e77 680 return err;
2e5f0320 681}
2e5f0320 682
fad09c73 683static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 684{
fad09c73 685 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 686}
687
fad09c73 688static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 689{
fad09c73 690 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 691}
692
a75961d0
GC		 693static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
694{
695 return chip->info->family == MV88E6XXX_FAMILY_6341;
696}
697
fad09c73 698static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 699{
fad09c73 700 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 701}
702
fad09c73 703static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 704{
fad09c73 705 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 706}
707
d78343d2
VD		 708static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
709 int link, int speed, int duplex,
710 phy_interface_t mode)
711{
712 int err;
713
714 if (!chip->info->ops->port_set_link)
715 return 0;
716
717 /* Port's MAC control must not be changed unless the link is down */
718 err = chip->info->ops->port_set_link(chip, port, 0);
719 if (err)
720 return err;
721
722 if (chip->info->ops->port_set_speed) {
723 err = chip->info->ops->port_set_speed(chip, port, speed);
724 if (err && err != -EOPNOTSUPP)
725 goto restore_link;
726 }
727
728 if (chip->info->ops->port_set_duplex) {
729 err = chip->info->ops->port_set_duplex(chip, port, duplex);
730 if (err && err != -EOPNOTSUPP)
731 goto restore_link;
732 }
733
734 if (chip->info->ops->port_set_rgmii_delay) {
735 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
736 if (err && err != -EOPNOTSUPP)
737 goto restore_link;
738 }
739
f39908d3
AL		 740 if (chip->info->ops->port_set_cmode) {
741 err = chip->info->ops->port_set_cmode(chip, port, mode);
742 if (err && err != -EOPNOTSUPP)
743 goto restore_link;
744 }
745
d78343d2
VD		 746 err = 0;
747restore_link:
748 if (chip->info->ops->port_set_link(chip, port, link))
749 netdev_err(chip->ds->ports[port].netdev,
750 "failed to restore MAC's link\n");
751
752 return err;
753}
754
dea87024
AL		 755/* We expect the switch to perform auto negotiation if there is a real
756 * phy. However, in the case of a fixed link phy, we force the port
757 * settings from the fixed link settings.
758 */
f81ec90f
VD		 759static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
760 struct phy_device *phydev)
dea87024 761{
04bed143 762 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 763 int err;
dea87024
AL		 764
765 if (!phy_is_pseudo_fixed_link(phydev))
766 return;
767
fad09c73 768 mutex_lock(&chip->reg_lock);
d78343d2
VD		 769 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
770 phydev->duplex, phydev->interface);
fad09c73 771 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 772
773 if (err && err != -EOPNOTSUPP)
774 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 775}
776
a605a0fe 777static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 778{
a605a0fe
AL		 779 if (!chip->info->ops->stats_snapshot)
780 return -EOPNOTSUPP;
91da11f8 781
a605a0fe 782 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 783}
784
e413e7e1 785static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 786 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
787 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
788 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
789 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
790 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
791 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
792 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
793 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
794 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
795 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
796 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
797 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
798 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
799 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
800 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
801 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
802 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
803 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
804 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
805 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
806 { "single", 4, 0x14, STATS_TYPE_BANK0, },
807 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
808 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
809 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
810 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
811 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
812 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
813 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
814 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
815 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
816 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
817 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
818 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
819 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
820 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
821 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
822 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
823 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
824 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
825 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
826 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
827 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
828 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
829 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
830 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
831 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
832 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
833 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
834 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
835 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
836 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
837 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
838 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
839 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
840 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
841 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
842 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
843 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
844 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 845};
846
fad09c73 847static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 848 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 849 int port, u16 bank1_select,
850 u16 histogram)
80c4627b 851{
80c4627b
AL		 852 u32 low;
853 u32 high = 0;
dfafe449 854 u16 reg = 0;
0e7b9925 855 int err;
80c4627b
AL		 856 u64 value;
857
f5e2ed02 858 switch (s->type) {
dfafe449 859 case STATS_TYPE_PORT:
0e7b9925
AL		 860 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
861 if (err)
80c4627b
AL		 862 return UINT64_MAX;
863
0e7b9925 864 low = reg;
80c4627b 865 if (s->sizeof_stat == 4) {
0e7b9925
AL		 866 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
867 if (err)
80c4627b 868 return UINT64_MAX;
0e7b9925 869 high = reg;
80c4627b 870 }
f5e2ed02 871 break;
dfafe449 872 case STATS_TYPE_BANK1:
e0d8b615 873 reg = bank1_select;
dfafe449
AL		 874 /* fall through */
875 case STATS_TYPE_BANK0:
e0d8b615 876 reg |= s->reg | histogram;
7f9ef3af 877 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 878 if (s->sizeof_stat == 8)
7f9ef3af 879 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 880 }
881 value = (((u64)high) << 16) | low;
882 return value;
883}
884
dfafe449
AL		 885static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
886 uint8_t *data, int types)
91da11f8 887{
f5e2ed02
AL		 888 struct mv88e6xxx_hw_stat *stat;
889 int i, j;
91da11f8 890
f5e2ed02
AL		 891 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
892 stat = &mv88e6xxx_hw_stats[i];
dfafe449 893 if (stat->type & types) {
f5e2ed02
AL		 894 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
895 ETH_GSTRING_LEN);
896 j++;
897 }
91da11f8 898 }
e413e7e1
AL		 899}
900
dfafe449
AL		 901static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
902 uint8_t *data)
903{
904 mv88e6xxx_stats_get_strings(chip, data,
905 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
906}
907
908static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
909 uint8_t *data)
910{
911 mv88e6xxx_stats_get_strings(chip, data,
912 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
913}
914
915static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
916 uint8_t *data)
e413e7e1 917{
04bed143 918 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 919
920 if (chip->info->ops->stats_get_strings)
921 chip->info->ops->stats_get_strings(chip, data);
922}
923
924static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
925 int types)
926{
f5e2ed02
AL		 927 struct mv88e6xxx_hw_stat *stat;
928 int i, j;
929
930 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
931 stat = &mv88e6xxx_hw_stats[i];
dfafe449 932 if (stat->type & types)
f5e2ed02
AL		 933 j++;
934 }
935 return j;
e413e7e1
AL		 936}
937
dfafe449
AL		 938static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
939{
940 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
941 STATS_TYPE_PORT);
942}
943
944static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
945{
946 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
947 STATS_TYPE_BANK1);
948}
949
950static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
951{
952 struct mv88e6xxx_chip *chip = ds->priv;
953
954 if (chip->info->ops->stats_get_sset_count)
955 return chip->info->ops->stats_get_sset_count(chip);
956
957 return 0;
958}
959
052f947f 960static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 961 uint64_t *data, int types,
962 u16 bank1_select, u16 histogram)
052f947f
AL		 963{
964 struct mv88e6xxx_hw_stat *stat;
965 int i, j;
966
967 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
968 stat = &mv88e6xxx_hw_stats[i];
969 if (stat->type & types) {
e0d8b615
AL		 970 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
971 bank1_select,
972 histogram);
052f947f
AL		 973 j++;
974 }
975 }
976}
977
978static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
979 uint64_t *data)
980{
981 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 982 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
983 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 984}
985
986static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
987 uint64_t *data)
988{
989 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 990 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
991 GLOBAL_STATS_OP_BANK_1_BIT_9,
992 GLOBAL_STATS_OP_HIST_RX_TX);
993}
994
995static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
996 uint64_t *data)
997{
998 return mv88e6xxx_stats_get_stats(chip, port, data,
999 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1000 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1001}
1002
1003static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1004 uint64_t *data)
1005{
1006 if (chip->info->ops->stats_get_stats)
1007 chip->info->ops->stats_get_stats(chip, port, data);
1008}
1009
f81ec90f
VD		 1010static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1011 uint64_t *data)
e413e7e1 1012{
04bed143 1013 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1014 int ret;
f5e2ed02 1015
fad09c73 1016 mutex_lock(&chip->reg_lock);
f5e2ed02 1017
a605a0fe 1018 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1019 if (ret < 0) {
fad09c73 1020 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1021 return;
1022 }
052f947f
AL		 1023
1024 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1025
fad09c73 1026 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1027}
1028
de227387
AL		 1029static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1030{
1031 if (chip->info->ops->stats_set_histogram)
1032 return chip->info->ops->stats_set_histogram(chip);
1033
1034 return 0;
1035}
1036
f81ec90f 1037static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1038{
1039 return 32 * sizeof(u16);
1040}
1041
f81ec90f
VD		 1042static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1043 struct ethtool_regs *regs, void *_p)
a1ab91f3 1044{
04bed143 1045 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1046 int err;
1047 u16 reg;
a1ab91f3
GR		 1048 u16 *p = _p;
1049 int i;
1050
1051 regs->version = 0;
1052
1053 memset(p, 0xff, 32 * sizeof(u16));
1054
fad09c73 1055 mutex_lock(&chip->reg_lock);
23062513 1056
a1ab91f3 1057 for (i = 0; i < 32; i++) {
a1ab91f3 1058
0e7b9925
AL		 1059 err = mv88e6xxx_port_read(chip, port, i, &reg);
1060 if (!err)
1061 p[i] = reg;
a1ab91f3 1062 }
23062513 1063
fad09c73 1064 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1065}
1066
f81ec90f
VD		 1067static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1068 struct ethtool_eee *e)
11b3b45d 1069{
04bed143 1070 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1071 u16 reg;
1072 int err;
11b3b45d 1073
fad09c73 1074 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1075 return -EOPNOTSUPP;
1076
fad09c73 1077 mutex_lock(&chip->reg_lock);
2f40c698 1078
9c93829c
VD		 1079 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1080 if (err)
2f40c698 1081 goto out;
11b3b45d
GR		 1082
1083 e->eee_enabled = !!(reg & 0x0200);
1084 e->tx_lpi_enabled = !!(reg & 0x0100);
1085
0e7b9925 1086 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1087 if (err)
2f40c698 1088 goto out;
11b3b45d 1089
cca8b133 1090 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1091out:
fad09c73 1092 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1093
1094 return err;
11b3b45d
GR		 1095}
1096
f81ec90f
VD		 1097static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1098 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1099{
04bed143 1100 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1101 u16 reg;
1102 int err;
11b3b45d 1103
fad09c73 1104 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1105 return -EOPNOTSUPP;
1106
fad09c73 1107 mutex_lock(&chip->reg_lock);
11b3b45d 1108
9c93829c
VD		 1109 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1110 if (err)
2f40c698
AL		 1111 goto out;
1112
9c93829c 1113 reg &= ~0x0300;
2f40c698
AL		 1114 if (e->eee_enabled)
1115 reg |= 0x0200;
1116 if (e->tx_lpi_enabled)
1117 reg |= 0x0100;
1118
9c93829c 1119 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1120out:
fad09c73 1121 mutex_unlock(&chip->reg_lock);
2f40c698 1122
9c93829c 1123 return err;
11b3b45d
GR		 1124}
1125
fad09c73 1126static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1127{
fad09c73 1128 struct dsa_switch *ds = chip->ds;
fae8a25e 1129 struct net_device *bridge = ds->ports[port].bridge_dev;
b7666efe 1130 u16 output_ports = 0;
b7666efe
VD		 1131 int i;
1132
1133 /* allow CPU port or DSA link(s) to send frames to every port */
1134 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1135 output_ports = ~0;
b7666efe 1136 } else {
370b4ffb 1137 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1138 /* allow sending frames to every group member */
fae8a25e 1139 if (bridge && ds->ports[i].bridge_dev == bridge)
b7666efe
VD		 1140 output_ports |= BIT(i);
1141
1142 /* allow sending frames to CPU port and DSA link(s) */
1143 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1144 output_ports |= BIT(i);
1145 }
1146 }
1147
1148 /* prevent frames from going back out of the port they came in on */
1149 output_ports &= ~BIT(port);
facd95b2 1150
5a7921f4 1151 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1152}
1153
f81ec90f
VD		 1154static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1155 u8 state)
facd95b2 1156{
04bed143 1157 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1158 int stp_state;
553eb544 1159 int err;
facd95b2
GR		 1160
1161 switch (state) {
1162 case BR_STATE_DISABLED:
cca8b133 1163 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1164 break;
1165 case BR_STATE_BLOCKING:
1166 case BR_STATE_LISTENING:
cca8b133 1167 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1168 break;
1169 case BR_STATE_LEARNING:
cca8b133 1170 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1171 break;
1172 case BR_STATE_FORWARDING:
1173 default:
cca8b133 1174 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1175 break;
1176 }
1177
fad09c73 1178 mutex_lock(&chip->reg_lock);
e28def33 1179 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1180 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1181
1182 if (err)
e28def33 1183 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1184}
1185
a2ac29d2
VD		 1186static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1187{
c3a7d4ad
VD		 1188 int err;
1189
daefc943
VD		 1190 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1191 if (err)
1192 return err;
1193
c3a7d4ad
VD		 1194 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1195 if (err)
1196 return err;
1197
a2ac29d2
VD		 1198 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1199}
1200
749efcb8
VD		 1201static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1202{
1203 struct mv88e6xxx_chip *chip = ds->priv;
1204 int err;
1205
1206 mutex_lock(&chip->reg_lock);
e606ca36 1207 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1208 mutex_unlock(&chip->reg_lock);
1209
1210 if (err)
1211 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1212}
1213
fad09c73 1214static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1215{
a935c052 1216 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1217}
1218
fad09c73 1219static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1220{
a935c052 1221 int err;
6b17e864 1222
a935c052
VD		 1223 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1224 if (err)
1225 return err;
6b17e864 1226
fad09c73 1227 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1228}
1229
fad09c73 1230static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1231{
1232 int ret;
1233
fad09c73 1234 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1235 if (ret < 0)
1236 return ret;
1237
fad09c73 1238 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1239}
1240
fad09c73 1241static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1242 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1243 unsigned int nibble_offset)
1244{
b8fee957 1245 u16 regs[3];
a935c052 1246 int i, err;
b8fee957
VD		 1247
1248 for (i = 0; i < 3; ++i) {
a935c052 1249 u16 *reg = &regs[i];
b8fee957 1250
a935c052
VD		 1251 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1252 if (err)
1253 return err;
b8fee957
VD		 1254 }
1255
370b4ffb 1256 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1257 unsigned int shift = (i % 4) * 4 + nibble_offset;
1258 u16 reg = regs[i / 4];
1259
1260 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1261 }
1262
1263 return 0;
1264}
1265
fad09c73 1266static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1267 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1268{
fad09c73 1269 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1270}
1271
fad09c73 1272static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1273 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1274{
fad09c73 1275 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1276}
1277
fad09c73 1278static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1279 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1280 unsigned int nibble_offset)
1281{
7dad08d7 1282 u16 regs[3] = { 0 };
a935c052 1283 int i, err;
7dad08d7 1284
370b4ffb 1285 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1286 unsigned int shift = (i % 4) * 4 + nibble_offset;
1287 u8 data = entry->data[i];
1288
1289 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1290 }
1291
1292 for (i = 0; i < 3; ++i) {
a935c052
VD		 1293 u16 reg = regs[i];
1294
1295 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1296 if (err)
1297 return err;
7dad08d7
VD		 1298 }
1299
1300 return 0;
1301}
1302
fad09c73 1303static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1304 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1305{
fad09c73 1306 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1307}
1308
fad09c73 1309static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1310 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1311{
fad09c73 1312 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1313}
1314
fad09c73 1315static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1316{
a935c052
VD		 1317 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1318 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1319}
1320
fad09c73 1321static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1322 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1323{
b4e47c0f 1324 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1325 u16 val;
1326 int err;
b8fee957 1327
a935c052
VD		 1328 err = _mv88e6xxx_vtu_wait(chip);
1329 if (err)
1330 return err;
b8fee957 1331
a935c052
VD		 1332 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1333 if (err)
1334 return err;
b8fee957 1335
a935c052
VD		 1336 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1337 if (err)
1338 return err;
b8fee957 1339
a935c052
VD		 1340 next.vid = val & GLOBAL_VTU_VID_MASK;
1341 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1342
1343 if (next.valid) {
a935c052
VD		 1344 err = mv88e6xxx_vtu_data_read(chip, &next);
1345 if (err)
1346 return err;
b8fee957 1347
6dc10bbc 1348 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1349 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1350 if (err)
1351 return err;
b8fee957 1352
a935c052 1353 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1354 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1355 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1356 * VTU DBNum[3:0] are located in VTU Operation 3:0
1357 */
a935c052
VD		 1358 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1359 if (err)
1360 return err;
11ea809f 1361
a935c052
VD		 1362 next.fid = (val & 0xf00) >> 4;
1363 next.fid |= val & 0xf;
2e7bd5ef 1364 }
b8fee957 1365
fad09c73 1366 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1367 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1368 if (err)
1369 return err;
b8fee957 1370
a935c052 1371 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1372 }
1373 }
1374
1375 *entry = next;
1376 return 0;
1377}
1378
f81ec90f
VD		 1379static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1380 struct switchdev_obj_port_vlan *vlan,
1381 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1382{
04bed143 1383 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1384 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1385 u16 pvid;
1386 int err;
1387
fad09c73 1388 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1389 return -EOPNOTSUPP;
1390
fad09c73 1391 mutex_lock(&chip->reg_lock);
ceff5eff 1392
77064f37 1393 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1394 if (err)
1395 goto unlock;
1396
fad09c73 1397 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1398 if (err)
1399 goto unlock;
1400
1401 do {
fad09c73 1402 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1403 if (err)
1404 break;
1405
1406 if (!next.valid)
1407 break;
1408
1409 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1410 continue;
1411
1412 /* reinit and dump this VLAN obj */
57d32310
VD		 1413 vlan->vid_begin = next.vid;
1414 vlan->vid_end = next.vid;
ceff5eff
VD		 1415 vlan->flags = 0;
1416
1417 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1418 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1419
1420 if (next.vid == pvid)
1421 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1422
1423 err = cb(&vlan->obj);
1424 if (err)
1425 break;
1426 } while (next.vid < GLOBAL_VTU_VID_MASK);
1427
1428unlock:
fad09c73 1429 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1430
1431 return err;
1432}
1433
fad09c73 1434static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1435 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1436{
11ea809f 1437 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1438 u16 reg = 0;
a935c052 1439 int err;
7dad08d7 1440
a935c052
VD		 1441 err = _mv88e6xxx_vtu_wait(chip);
1442 if (err)
1443 return err;
7dad08d7
VD		 1444
1445 if (!entry->valid)
1446 goto loadpurge;
1447
1448 /* Write port member tags */
a935c052
VD		 1449 err = mv88e6xxx_vtu_data_write(chip, entry);
1450 if (err)
1451 return err;
7dad08d7 1452
fad09c73 1453 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1454 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1455 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1456 if (err)
1457 return err;
b426e5f7 1458 }
7dad08d7 1459
6dc10bbc 1460 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1461 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1462 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1463 if (err)
1464 return err;
fad09c73 1465 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1466 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1467 * VTU DBNum[3:0] are located in VTU Operation 3:0
1468 */
1469 op |= (entry->fid & 0xf0) << 8;
1470 op |= entry->fid & 0xf;
7dad08d7
VD		 1471 }
1472
1473 reg = GLOBAL_VTU_VID_VALID;
1474loadpurge:
1475 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1476 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1477 if (err)
1478 return err;
7dad08d7 1479
fad09c73 1480 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1481}
1482
fad09c73 1483static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1484 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1485{
b4e47c0f 1486 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1487 u16 val;
1488 int err;
0d3b33e6 1489
a935c052
VD		 1490 err = _mv88e6xxx_vtu_wait(chip);
1491 if (err)
1492 return err;
0d3b33e6 1493
a935c052
VD		 1494 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1495 sid & GLOBAL_VTU_SID_MASK);
1496 if (err)
1497 return err;
0d3b33e6 1498
a935c052
VD		 1499 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1500 if (err)
1501 return err;
0d3b33e6 1502
a935c052
VD		 1503 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1504 if (err)
1505 return err;
0d3b33e6 1506
a935c052 1507 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1508
a935c052
VD		 1509 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1510 if (err)
1511 return err;
0d3b33e6 1512
a935c052 1513 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1514
1515 if (next.valid) {
a935c052
VD		 1516 err = mv88e6xxx_stu_data_read(chip, &next);
1517 if (err)
1518 return err;
0d3b33e6
VD		 1519 }
1520
1521 *entry = next;
1522 return 0;
1523}
1524
fad09c73 1525static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1526 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1527{
1528 u16 reg = 0;
a935c052 1529 int err;
0d3b33e6 1530
a935c052
VD		 1531 err = _mv88e6xxx_vtu_wait(chip);
1532 if (err)
1533 return err;
0d3b33e6
VD		 1534
1535 if (!entry->valid)
1536 goto loadpurge;
1537
1538 /* Write port states */
a935c052
VD		 1539 err = mv88e6xxx_stu_data_write(chip, entry);
1540 if (err)
1541 return err;
0d3b33e6
VD		 1542
1543 reg = GLOBAL_VTU_VID_VALID;
1544loadpurge:
a935c052
VD		 1545 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1546 if (err)
1547 return err;
0d3b33e6
VD		 1548
1549 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1550 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1551 if (err)
1552 return err;
0d3b33e6 1553
fad09c73 1554 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1555}
1556
d7f435f9 1557static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1558{
1559 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1560 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1561 int i, err;
3285f9e8
VD		 1562
1563 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1564
2db9ce1f 1565 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1566 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1567 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1568 if (err)
1569 return err;
1570
1571 set_bit(*fid, fid_bitmap);
1572 }
1573
3285f9e8 1574 /* Set every FID bit used by the VLAN entries */
fad09c73 1575 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1576 if (err)
1577 return err;
1578
1579 do {
fad09c73 1580 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1581 if (err)
1582 return err;
1583
1584 if (!vlan.valid)
1585 break;
1586
1587 set_bit(vlan.fid, fid_bitmap);
1588 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1589
1590 /* The reset value 0x000 is used to indicate that multiple address
1591 * databases are not needed. Return the next positive available.
1592 */
1593 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1594 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1595 return -ENOSPC;
1596
1597 /* Clear the database */
daefc943 1598 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1599}
1600
fad09c73 1601static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1602 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1603{
fad09c73 1604 struct dsa_switch *ds = chip->ds;
b4e47c0f 1605 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1606 .valid = true,
1607 .vid = vid,
1608 };
3285f9e8
VD		 1609 int i, err;
1610
d7f435f9 1611 err = mv88e6xxx_atu_new(chip, &vlan.fid);
3285f9e8
VD		 1612 if (err)
1613 return err;
0d3b33e6 1614
3d131f07 1615 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1616 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1617 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1618 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1619 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1620
fad09c73 1621 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
a75961d0
GC		 1622 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1623 mv88e6xxx_6341_family(chip)) {
b4e47c0f 1624 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1625
1626 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1627 * implemented, only one STU entry is needed to cover all VTU
1628 * entries. Thus, validate the SID 0.
1629 */
1630 vlan.sid = 0;
fad09c73 1631 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1632 if (err)
1633 return err;
1634
1635 if (vstp.sid != vlan.sid || !vstp.valid) {
1636 memset(&vstp, 0, sizeof(vstp));
1637 vstp.valid = true;
1638 vstp.sid = vlan.sid;
1639
fad09c73 1640 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1641 if (err)
1642 return err;
1643 }
0d3b33e6
VD		 1644 }
1645
1646 *entry = vlan;
1647 return 0;
1648}
1649
fad09c73 1650static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1651 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1652{
1653 int err;
1654
1655 if (!vid)
1656 return -EINVAL;
1657
fad09c73 1658 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1659 if (err)
1660 return err;
1661
fad09c73 1662 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1663 if (err)
1664 return err;
1665
1666 if (entry->vid != vid || !entry->valid) {
1667 if (!creat)
1668 return -EOPNOTSUPP;
1669 /* -ENOENT would've been more appropriate, but switchdev expects
1670 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1671 */
1672
fad09c73 1673 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1674 }
1675
1676 return err;
1677}
1678
da9c359e
VD		 1679static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1680 u16 vid_begin, u16 vid_end)
1681{
04bed143 1682 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1683 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1684 int i, err;
1685
1686 if (!vid_begin)
1687 return -EOPNOTSUPP;
1688
fad09c73 1689 mutex_lock(&chip->reg_lock);
da9c359e 1690
fad09c73 1691 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1692 if (err)
1693 goto unlock;
1694
1695 do {
fad09c73 1696 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1697 if (err)
1698 goto unlock;
1699
1700 if (!vlan.valid)
1701 break;
1702
1703 if (vlan.vid > vid_end)
1704 break;
1705
370b4ffb 1706 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1707 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1708 continue;
1709
66e2809d
AL		 1710 if (!ds->ports[port].netdev)
1711 continue;
1712
da9c359e
VD		 1713 if (vlan.data[i] ==
1714 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1715 continue;
1716
fae8a25e
VD		 1717 if (ds->ports[i].bridge_dev ==
1718 ds->ports[port].bridge_dev)
da9c359e
VD		 1719 break; /* same bridge, check next VLAN */
1720
fae8a25e 1721 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1722 continue;
1723
c8b09808 1724 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1725 "hardware VLAN %d already used by %s\n",
1726 vlan.vid,
fae8a25e 1727 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1728 err = -EOPNOTSUPP;
1729 goto unlock;
1730 }
1731 } while (vlan.vid < vid_end);
1732
1733unlock:
fad09c73 1734 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1735
1736 return err;
1737}
1738
f81ec90f
VD		 1739static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1740 bool vlan_filtering)
214cdb99 1741{
04bed143 1742 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1743 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1744 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1745 int err;
214cdb99 1746
fad09c73 1747 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1748 return -EOPNOTSUPP;
1749
fad09c73 1750 mutex_lock(&chip->reg_lock);
385a0995 1751 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1752 mutex_unlock(&chip->reg_lock);
214cdb99 1753
0e7b9925 1754 return err;
214cdb99
VD		 1755}
1756
57d32310
VD		 1757static int
1758mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1759 const struct switchdev_obj_port_vlan *vlan,
1760 struct switchdev_trans *trans)
76e398a6 1761{
04bed143 1762 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1763 int err;
1764
fad09c73 1765 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1766 return -EOPNOTSUPP;
1767
da9c359e
VD		 1768 /* If the requested port doesn't belong to the same bridge as the VLAN
1769 * members, do not support it (yet) and fallback to software VLAN.
1770 */
1771 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1772 vlan->vid_end);
1773 if (err)
1774 return err;
1775
76e398a6
VD		 1776 /* We don't need any dynamic resource from the kernel (yet),
1777 * so skip the prepare phase.
1778 */
1779 return 0;
1780}
1781
fad09c73 1782static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1783 u16 vid, bool untagged)
0d3b33e6 1784{
b4e47c0f 1785 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1786 int err;
1787
fad09c73 1788 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1789 if (err)
76e398a6 1790 return err;
0d3b33e6 1791
0d3b33e6
VD		 1792 vlan.data[port] = untagged ?
1793 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1794 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1795
fad09c73 1796 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1797}
1798
f81ec90f
VD		 1799static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1800 const struct switchdev_obj_port_vlan *vlan,
1801 struct switchdev_trans *trans)
76e398a6 1802{
04bed143 1803 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1804 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1805 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1806 u16 vid;
76e398a6 1807
fad09c73 1808 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1809 return;
1810
fad09c73 1811 mutex_lock(&chip->reg_lock);
76e398a6 1812
4d5770b3 1813 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1814 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1815 netdev_err(ds->ports[port].netdev,
1816 "failed to add VLAN %d%c\n",
4d5770b3 1817 vid, untagged ? 'u' : 't');
76e398a6 1818
77064f37 1819 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1820 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1821 vlan->vid_end);
0d3b33e6 1822
fad09c73 1823 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1824}
1825
fad09c73 1826static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1827 int port, u16 vid)
7dad08d7 1828{
fad09c73 1829 struct dsa_switch *ds = chip->ds;
b4e47c0f 1830 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1831 int i, err;
1832
fad09c73 1833 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1834 if (err)
76e398a6 1835 return err;
7dad08d7 1836
2fb5ef09
VD		 1837 /* Tell switchdev if this VLAN is handled in software */
1838 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1839 return -EOPNOTSUPP;
7dad08d7
VD		 1840
1841 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1842
1843 /* keep the VLAN unless all ports are excluded */
f02bdffc 1844 vlan.valid = false;
370b4ffb 1845 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1846 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1847 continue;
1848
1849 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1850 vlan.valid = true;
7dad08d7
VD		 1851 break;
1852 }
1853 }
1854
fad09c73 1855 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1856 if (err)
1857 return err;
1858
e606ca36 1859 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1860}
1861
f81ec90f
VD		 1862static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1863 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1864{
04bed143 1865 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1866 u16 pvid, vid;
1867 int err = 0;
1868
fad09c73 1869 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1870 return -EOPNOTSUPP;
1871
fad09c73 1872 mutex_lock(&chip->reg_lock);
76e398a6 1873
77064f37 1874 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1875 if (err)
1876 goto unlock;
1877
76e398a6 1878 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1879 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1880 if (err)
1881 goto unlock;
1882
1883 if (vid == pvid) {
77064f37 1884 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1885 if (err)
1886 goto unlock;
1887 }
1888 }
1889
7dad08d7 1890unlock:
fad09c73 1891 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1892
1893 return err;
1894}
1895
83dabd1f
VD		 1896static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1897 const unsigned char *addr, u16 vid,
1898 u8 state)
fd231c82 1899{
b4e47c0f 1900 struct mv88e6xxx_vtu_entry vlan;
88472939 1901 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1902 int err;
1903
2db9ce1f
VD		 1904 /* Null VLAN ID corresponds to the port private database */
1905 if (vid == 0)
b4e48c50 1906 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1907 else
fad09c73 1908 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1909 if (err)
1910 return err;
fd231c82 1911
dabc1a96
VD		 1912 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1913 ether_addr_copy(entry.mac, addr);
1914 eth_addr_dec(entry.mac);
1915
1916 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1917 if (err)
1918 return err;
1919
dabc1a96
VD		 1920 /* Initialize a fresh ATU entry if it isn't found */
1921 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1922 !ether_addr_equal(entry.mac, addr)) {
1923 memset(&entry, 0, sizeof(entry));
1924 ether_addr_copy(entry.mac, addr);
1925 }
1926
88472939
VD		 1927 /* Purge the ATU entry only if no port is using it anymore */
1928 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1929 entry.portvec &= ~BIT(port);
1930 if (!entry.portvec)
88472939
VD		 1931 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1932 } else {
01bd96c8 1933 entry.portvec |= BIT(port);
88472939 1934 entry.state = state;
fd231c82
VD		 1935 }
1936
9c13c026 1937 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1938}
1939
f81ec90f
VD		 1940static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1941 const struct switchdev_obj_port_fdb *fdb,
1942 struct switchdev_trans *trans)
146a3206
VD		 1943{
1944 /* We don't need any dynamic resource from the kernel (yet),
1945 * so skip the prepare phase.
1946 */
1947 return 0;
1948}
1949
f81ec90f
VD		 1950static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1951 const struct switchdev_obj_port_fdb *fdb,
1952 struct switchdev_trans *trans)
87820510 1953{
04bed143 1954 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1955
fad09c73 1956 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1957 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1958 GLOBAL_ATU_DATA_STATE_UC_STATIC))
1959 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 1960 mutex_unlock(&chip->reg_lock);
87820510
VD		 1961}
1962
f81ec90f
VD		 1963static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1964 const struct switchdev_obj_port_fdb *fdb)
87820510 1965{
04bed143 1966 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1967 int err;
87820510 1968
fad09c73 1969 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1970 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1971 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 1972 mutex_unlock(&chip->reg_lock);
87820510 1973
83dabd1f 1974 return err;
87820510
VD		 1975}
1976
83dabd1f
VD		 1977static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1978 u16 fid, u16 vid, int port,
1979 struct switchdev_obj *obj,
1980 int (*cb)(struct switchdev_obj *obj))
74b6ba0d 1981{
dabc1a96 1982 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 1983 int err;
1984
dabc1a96
VD		 1985 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1986 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1987
1988 do {
dabc1a96 1989 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1990 if (err)
83dabd1f 1991 return err;
74b6ba0d
VD		 1992
1993 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1994 break;
1995
01bd96c8 1996 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1997 continue;
1998
1999 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2000 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2001
83dabd1f
VD		 2002 if (!is_unicast_ether_addr(addr.mac))
2003 continue;
2004
2005 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2006 fdb->vid = vid;
2007 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2008 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2009 fdb->ndm_state = NUD_NOARP;
2010 else
2011 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2012 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2013 struct switchdev_obj_port_mdb *mdb;
2014
2015 if (!is_multicast_ether_addr(addr.mac))
2016 continue;
2017
2018 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2019 mdb->vid = vid;
2020 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2021 } else {
2022 return -EOPNOTSUPP;
74b6ba0d 2023 }
83dabd1f
VD		 2024
2025 err = cb(obj);
2026 if (err)
2027 return err;
74b6ba0d
VD		 2028 } while (!is_broadcast_ether_addr(addr.mac));
2029
2030 return err;
2031}
2032
83dabd1f
VD		 2033static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2034 struct switchdev_obj *obj,
2035 int (*cb)(struct switchdev_obj *obj))
f33475bd 2036{
b4e47c0f 2037 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2038 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2039 };
2db9ce1f 2040 u16 fid;
f33475bd
VD		 2041 int err;
2042
2db9ce1f 2043 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2044 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2045 if (err)
83dabd1f 2046 return err;
2db9ce1f 2047
83dabd1f 2048 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2049 if (err)
83dabd1f 2050 return err;
2db9ce1f 2051
74b6ba0d 2052 /* Dump VLANs' Filtering Information Databases */
fad09c73 2053 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2054 if (err)
83dabd1f 2055 return err;
f33475bd
VD		 2056
2057 do {
fad09c73 2058 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2059 if (err)
83dabd1f 2060 return err;
f33475bd
VD		 2061
2062 if (!vlan.valid)
2063 break;
2064
83dabd1f
VD		 2065 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2066 obj, cb);
f33475bd 2067 if (err)
83dabd1f 2068 return err;
f33475bd
VD		 2069 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2070
83dabd1f
VD		 2071 return err;
2072}
2073
2074static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2075 struct switchdev_obj_port_fdb *fdb,
2076 int (*cb)(struct switchdev_obj *obj))
2077{
04bed143 2078 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2079 int err;
2080
2081 mutex_lock(&chip->reg_lock);
2082 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2083 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2084
2085 return err;
2086}
2087
f81ec90f 2088static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
fae8a25e 2089 struct net_device *br)
e79a8bcb 2090{
04bed143 2091 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2092 int i, err = 0;
466dfa07 2093
fad09c73 2094 mutex_lock(&chip->reg_lock);
466dfa07 2095
fae8a25e 2096 /* Remap each port's VLANTable */
370b4ffb 2097 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fae8a25e 2098 if (ds->ports[i].bridge_dev == br) {
fad09c73 2099 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2100 if (err)
2101 break;
2102 }
2103 }
2104
fad09c73 2105 mutex_unlock(&chip->reg_lock);
a6692754 2106
466dfa07 2107 return err;
e79a8bcb
VD		 2108}
2109
f123f2fb
VD		 2110static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2111 struct net_device *br)
66d9cd0f 2112{
04bed143 2113 struct mv88e6xxx_chip *chip = ds->priv;
16bfa702 2114 int i;
466dfa07 2115
fad09c73 2116 mutex_lock(&chip->reg_lock);
466dfa07 2117
fae8a25e 2118 /* Remap each port's VLANTable */
370b4ffb 2119 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fae8a25e 2120 if (i == port || ds->ports[i].bridge_dev == br)
fad09c73 2121 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2122 netdev_warn(ds->ports[i].netdev,
2123 "failed to remap\n");
b7666efe 2124
fad09c73 2125 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2126}
2127
17e708ba
VD		 2128static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2129{
2130 if (chip->info->ops->reset)
2131 return chip->info->ops->reset(chip);
2132
2133 return 0;
2134}
2135
309eca6d
VD		 2136static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2137{
2138 struct gpio_desc *gpiod = chip->reset;
2139
2140 /* If there is a GPIO connected to the reset pin, toggle it */
2141 if (gpiod) {
2142 gpiod_set_value_cansleep(gpiod, 1);
2143 usleep_range(10000, 20000);
2144 gpiod_set_value_cansleep(gpiod, 0);
2145 usleep_range(10000, 20000);
2146 }
2147}
2148
4ac4b5a6 2149static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2150{
4ac4b5a6 2151 int i, err;
552238b5 2152
4ac4b5a6 2153 /* Set all ports to the Disabled state */
370b4ffb 2154 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2155 err = mv88e6xxx_port_set_state(chip, i,
2156 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2157 if (err)
2158 return err;
552238b5
VD		 2159 }
2160
4ac4b5a6
VD		 2161 /* Wait for transmit queues to drain,
2162 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2163 */
552238b5
VD		 2164 usleep_range(2000, 4000);
2165
4ac4b5a6
VD		 2166 return 0;
2167}
2168
2169static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2170{
4ac4b5a6
VD		 2171 int err;
2172
2173 err = mv88e6xxx_disable_ports(chip);
2174 if (err)
2175 return err;
2176
309eca6d 2177 mv88e6xxx_hardware_reset(chip);
552238b5 2178
17e708ba 2179 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2180}
2181
09cb7dfd 2182static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2183{
09cb7dfd
VD		 2184 u16 val;
2185 int err;
13a7ebb3 2186
09cb7dfd
VD		 2187 /* Clear Power Down bit */
2188 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2189 if (err)
2190 return err;
13a7ebb3 2191
09cb7dfd
VD		 2192 if (val & BMCR_PDOWN) {
2193 val &= ~BMCR_PDOWN;
2194 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2195 }
2196
09cb7dfd 2197 return err;
13a7ebb3
PU		 2198}
2199
4314557c
VD		 2200static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2201 enum mv88e6xxx_frame_mode frame, u16 egress,
2202 u16 etype)
56995cbc
AL		 2203{
2204 int err;
2205
4314557c
VD		 2206 if (!chip->info->ops->port_set_frame_mode)
2207 return -EOPNOTSUPP;
2208
2209 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 2210 if (err)
2211 return err;
2212
4314557c
VD		 2213 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2214 if (err)
2215 return err;
2216
2217 if (chip->info->ops->port_set_ether_type)
2218 return chip->info->ops->port_set_ether_type(chip, port, etype);
2219
2220 return 0;
56995cbc
AL		 2221}
2222
4314557c 2223static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 2224{
4314557c
VD		 2225 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2226 PORT_CONTROL_EGRESS_UNMODIFIED,
2227 PORT_ETH_TYPE_DEFAULT);
2228}
56995cbc 2229
4314557c
VD		 2230static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2231{
2232 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2233 PORT_CONTROL_EGRESS_UNMODIFIED,
2234 PORT_ETH_TYPE_DEFAULT);
2235}
56995cbc 2236
4314557c
VD		 2237static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2238{
2239 return mv88e6xxx_set_port_mode(chip, port,
2240 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2241 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2242}
56995cbc 2243
4314557c
VD		 2244static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2245{
2246 if (dsa_is_dsa_port(chip->ds, port))
2247 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2248
4314557c
VD		 2249 if (dsa_is_normal_port(chip->ds, port))
2250 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 2251
4314557c
VD		 2252 /* Setup CPU port mode depending on its supported tag format */
2253 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2254 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2255
4314557c
VD		 2256 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2257 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 2258
4314557c 2259 return -EINVAL;
56995cbc
AL		 2260}
2261
601aeed3 2262static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 2263{
601aeed3 2264 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 2265
601aeed3 2266 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 2267}
56995cbc 2268
601aeed3 2269static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 2270{
601aeed3 2271 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 2272
601aeed3
VD		 2273 /* Upstream ports flood frames with unknown unicast or multicast DA */
2274 if (chip->info->ops->port_set_egress_floods)
2275 return chip->info->ops->port_set_egress_floods(chip, port,
2276 flood, flood);
ea698f4f 2277
601aeed3 2278 return 0;
ea698f4f
VD		 2279}
2280
fad09c73 2281static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2282{
fad09c73 2283 struct dsa_switch *ds = chip->ds;
0e7b9925 2284 int err;
54d792f2 2285 u16 reg;
d827e88a 2286
d78343d2
VD		 2287 /* MAC Forcing register: don't force link, speed, duplex or flow control
2288 * state to any particular values on physical ports, but force the CPU
2289 * port and all DSA ports to their maximum bandwidth and full duplex.
2290 */
2291 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2292 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2293 SPEED_MAX, DUPLEX_FULL,
2294 PHY_INTERFACE_MODE_NA);
2295 else
2296 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2297 SPEED_UNFORCED, DUPLEX_UNFORCED,
2298 PHY_INTERFACE_MODE_NA);
2299 if (err)
2300 return err;
54d792f2
AL		 2301
2302 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2303 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2304 * tunneling, determine priority by looking at 802.1p and IP
2305 * priority fields (IP prio has precedence), and set STP state
2306 * to Forwarding.
2307 *
2308 * If this is the CPU link, use DSA or EDSA tagging depending
2309 * on which tagging mode was configured.
2310 *
2311 * If this is a link to another switch, use DSA tagging mode.
2312 *
2313 * If this is the upstream port for this switch, enable
2314 * forwarding of unknown unicasts and multicasts.
2315 */
56995cbc 2316 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2317 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2318 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2319 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2320 if (err)
2321 return err;
6083ce71 2322
601aeed3 2323 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 2324 if (err)
2325 return err;
54d792f2 2326
601aeed3 2327 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 2328 if (err)
2329 return err;
2330
13a7ebb3
PU		 2331 /* If this port is connected to a SerDes, make sure the SerDes is not
2332 * powered down.
2333 */
09cb7dfd 2334 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2335 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2336 if (err)
2337 return err;
2338 reg &= PORT_STATUS_CMODE_MASK;
2339 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2340 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2341 (reg == PORT_STATUS_CMODE_SGMII)) {
2342 err = mv88e6xxx_serdes_power_on(chip);
2343 if (err < 0)
2344 return err;
13a7ebb3
PU		 2345 }
2346 }
2347
8efdda4a 2348 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2349 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2350 * untagged frames on this port, do a destination address lookup on all
2351 * received packets as usual, disable ARP mirroring and don't send a
2352 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2353 */
a23b2961
AL		 2354 err = mv88e6xxx_port_set_map_da(chip, port);
2355 if (err)
2356 return err;
8efdda4a 2357
a23b2961
AL		 2358 reg = 0;
2359 if (chip->info->ops->port_set_upstream_port) {
2360 err = chip->info->ops->port_set_upstream_port(
2361 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 2362 if (err)
2363 return err;
54d792f2
AL		 2364 }
2365
a23b2961
AL		 2366 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2367 PORT_CONTROL_2_8021Q_DISABLED);
2368 if (err)
2369 return err;
2370
5f436666
AL		 2371 if (chip->info->ops->port_jumbo_config) {
2372 err = chip->info->ops->port_jumbo_config(chip, port);
2373 if (err)
2374 return err;
2375 }
2376
54d792f2
AL		 2377 /* Port Association Vector: when learning source addresses
2378 * of packets, add the address to the address database using
2379 * a port bitmap that has only the bit for this port set and
2380 * the other bits clear.
2381 */
4c7ea3c0 2382 reg = 1 << port;
996ecb82
VD		 2383 /* Disable learning for CPU port */
2384 if (dsa_is_cpu_port(ds, port))
65fa4027 2385 reg = 0;
4c7ea3c0 2386
0e7b9925
AL		 2387 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2388 if (err)
2389 return err;
54d792f2
AL		 2390
2391 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2392 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2393 if (err)
2394 return err;
54d792f2 2395
b35d322a
AL		 2396 if (chip->info->ops->port_pause_config) {
2397 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2398 if (err)
2399 return err;
b35d322a 2400 }
54d792f2 2401
c8c94891
VD		 2402 if (chip->info->ops->port_disable_learn_limit) {
2403 err = chip->info->ops->port_disable_learn_limit(chip, port);
2404 if (err)
2405 return err;
2406 }
2407
9dbfb4e1
VD		 2408 if (chip->info->ops->port_disable_pri_override) {
2409 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 2410 if (err)
2411 return err;
ef0a7318 2412 }
2bbb33be 2413
ef0a7318
AL		 2414 if (chip->info->ops->port_tag_remap) {
2415 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2416 if (err)
2417 return err;
54d792f2
AL		 2418 }
2419
ef70b111
AL		 2420 if (chip->info->ops->port_egress_rate_limiting) {
2421 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2422 if (err)
2423 return err;
54d792f2
AL		 2424 }
2425
ea698f4f 2426 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 2427 if (err)
2428 return err;
d827e88a 2429
207afda1 2430 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2431 * database, and allow bidirectional communication between the
2432 * CPU and DSA port(s), and the other ports.
d827e88a 2433 */
b4e48c50 2434 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2435 if (err)
2436 return err;
2db9ce1f 2437
0e7b9925
AL		 2438 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2439 if (err)
2440 return err;
d827e88a
GR		 2441
2442 /* Default VLAN ID and priority: don't set a default VLAN
2443 * ID, and set the default packet priority to zero.
2444 */
0e7b9925 2445 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2446}
2447
aa0938c6 2448static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2449{
2450 int err;
2451
a935c052 2452 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2453 if (err)
2454 return err;
2455
a935c052 2456 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2457 if (err)
2458 return err;
2459
a935c052
VD		 2460 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2461 if (err)
2462 return err;
2463
2464 return 0;
3b4caa1b
VD		 2465}
2466
2cfcd964
VD		 2467static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2468 unsigned int ageing_time)
2469{
04bed143 2470 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2471 int err;
2472
2473 mutex_lock(&chip->reg_lock);
720c6343 2474 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2475 mutex_unlock(&chip->reg_lock);
2476
2477 return err;
2478}
2479
9729934c 2480static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2481{
fad09c73 2482 struct dsa_switch *ds = chip->ds;
b0745e87 2483 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2484 int err;
54d792f2 2485
119477bd
VD		 2486 /* Enable the PHY Polling Unit if present, don't discard any packets,
2487 * and mask all interrupt sources.
2488 */
a199d8b6 2489 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2490 if (err)
2491 return err;
2492
33641994
AL		 2493 if (chip->info->ops->g1_set_cpu_port) {
2494 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2495 if (err)
2496 return err;
2497 }
2498
2499 if (chip->info->ops->g1_set_egress_port) {
2500 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2501 if (err)
2502 return err;
2503 }
b0745e87 2504
50484ff4 2505 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2506 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2507 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2508 (ds->index & 0x1f));
50484ff4
VD		 2509 if (err)
2510 return err;
2511
acddbd21
VD		 2512 /* Clear all the VTU and STU entries */
2513 err = _mv88e6xxx_vtu_stu_flush(chip);
2514 if (err < 0)
2515 return err;
2516
54d792f2 2517 /* Configure the IP ToS mapping registers. */
a935c052 2518 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2519 if (err)
08a01261 2520 return err;
a935c052 2521 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2522 if (err)
08a01261 2523 return err;
a935c052 2524 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2525 if (err)
08a01261 2526 return err;
a935c052 2527 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2528 if (err)
08a01261 2529 return err;
a935c052 2530 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2531 if (err)
08a01261 2532 return err;
a935c052 2533 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2534 if (err)
08a01261 2535 return err;
a935c052 2536 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2537 if (err)
08a01261 2538 return err;
a935c052 2539 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2540 if (err)
08a01261 2541 return err;
54d792f2
AL		 2542
2543 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2544 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2545 if (err)
08a01261 2546 return err;
54d792f2 2547
de227387
AL		 2548 /* Initialize the statistics unit */
2549 err = mv88e6xxx_stats_set_histogram(chip);
2550 if (err)
2551 return err;
2552
9729934c 2553 /* Clear the statistics counters for all ports */
a935c052
VD		 2554 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2555 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2556 if (err)
2557 return err;
2558
2559 /* Wait for the flush to complete. */
7f9ef3af 2560 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2561 if (err)
2562 return err;
2563
2564 return 0;
2565}
2566
f81ec90f 2567static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2568{
04bed143 2569 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2570 int err;
a1a6a4d1
VD		 2571 int i;
2572
fad09c73 2573 chip->ds = ds;
a3c53be5 2574 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2575
fad09c73 2576 mutex_lock(&chip->reg_lock);
08a01261 2577
9729934c 2578 /* Setup Switch Port Registers */
370b4ffb 2579 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2580 err = mv88e6xxx_setup_port(chip, i);
2581 if (err)
2582 goto unlock;
2583 }
2584
2585 /* Setup Switch Global 1 Registers */
2586 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2587 if (err)
2588 goto unlock;
2589
9729934c
VD		 2590 /* Setup Switch Global 2 Registers */
2591 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2592 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2593 if (err)
2594 goto unlock;
2595 }
08a01261 2596
a2ac29d2
VD		 2597 err = mv88e6xxx_atu_setup(chip);
2598 if (err)
2599 goto unlock;
2600
6e55f698
AL		 2601 /* Some generations have the configuration of sending reserved
2602 * management frames to the CPU in global2, others in
2603 * global1. Hence it does not fit the two setup functions
2604 * above.
2605 */
2606 if (chip->info->ops->mgmt_rsvd2cpu) {
2607 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2608 if (err)
2609 goto unlock;
2610 }
2611
6b17e864 2612unlock:
fad09c73 2613 mutex_unlock(&chip->reg_lock);
db687a56 2614
48ace4ef 2615 return err;
54d792f2
AL		 2616}
2617
3b4caa1b
VD		 2618static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2619{
04bed143 2620 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2621 int err;
2622
b073d4e2
VD		 2623 if (!chip->info->ops->set_switch_mac)
2624 return -EOPNOTSUPP;
3b4caa1b 2625
b073d4e2
VD		 2626 mutex_lock(&chip->reg_lock);
2627 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2628 mutex_unlock(&chip->reg_lock);
2629
2630 return err;
2631}
2632
e57e5e77 2633static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2634{
0dd12d54
AL		 2635 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2636 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2637 u16 val;
2638 int err;
fd3a0ee4 2639
ee26a228
AL		 2640 if (!chip->info->ops->phy_read)
2641 return -EOPNOTSUPP;
2642
fad09c73 2643 mutex_lock(&chip->reg_lock);
ee26a228 2644 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2645 mutex_unlock(&chip->reg_lock);
e57e5e77 2646
da9f3301
AL		 2647 if (reg == MII_PHYSID2) {
2648 /* Some internal PHYS don't have a model number. Use
2649 * the mv88e6390 family model number instead.
2650 */
2651 if (!(val & 0x3f0))
2652 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2653 }
2654
e57e5e77 2655 return err ? err : val;
fd3a0ee4
AL		 2656}
2657
e57e5e77 2658static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2659{
0dd12d54
AL		 2660 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2661 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2662 int err;
fd3a0ee4 2663
ee26a228
AL		 2664 if (!chip->info->ops->phy_write)
2665 return -EOPNOTSUPP;
2666
fad09c73 2667 mutex_lock(&chip->reg_lock);
ee26a228 2668 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2669 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2670
2671 return err;
fd3a0ee4
AL		 2672}
2673
fad09c73 2674static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2675 struct device_node *np,
2676 bool external)
b516d453
AL		 2677{
2678 static int index;
0dd12d54 2679 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2680 struct mii_bus *bus;
2681 int err;
2682
0dd12d54 2683 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2684 if (!bus)
2685 return -ENOMEM;
2686
0dd12d54 2687 mdio_bus = bus->priv;
a3c53be5 2688 mdio_bus->bus = bus;
0dd12d54 2689 mdio_bus->chip = chip;
a3c53be5
AL		 2690 INIT_LIST_HEAD(&mdio_bus->list);
2691 mdio_bus->external = external;
0dd12d54 2692
b516d453
AL		 2693 if (np) {
2694 bus->name = np->full_name;
2695 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2696 } else {
2697 bus->name = "mv88e6xxx SMI";
2698 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2699 }
2700
2701 bus->read = mv88e6xxx_mdio_read;
2702 bus->write = mv88e6xxx_mdio_write;
fad09c73 2703 bus->parent = chip->dev;
b516d453 2704
a3c53be5
AL		 2705 if (np)
2706 err = of_mdiobus_register(bus, np);
b516d453
AL		 2707 else
2708 err = mdiobus_register(bus);
2709 if (err) {
fad09c73 2710 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2711 return err;
b516d453 2712 }
a3c53be5
AL		 2713
2714 if (external)
2715 list_add_tail(&mdio_bus->list, &chip->mdios);
2716 else
2717 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2718
2719 return 0;
a3c53be5 2720}
b516d453 2721
a3c53be5
AL		 2722static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2723 { .compatible = "marvell,mv88e6xxx-mdio-external",
2724 .data = (void *)true },
2725 { },
2726};
b516d453 2727
a3c53be5
AL		 2728static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2729 struct device_node *np)
2730{
2731 const struct of_device_id *match;
2732 struct device_node *child;
2733 int err;
2734
2735 /* Always register one mdio bus for the internal/default mdio
2736 * bus. This maybe represented in the device tree, but is
2737 * optional.
2738 */
2739 child = of_get_child_by_name(np, "mdio");
2740 err = mv88e6xxx_mdio_register(chip, child, false);
2741 if (err)
2742 return err;
2743
2744 /* Walk the device tree, and see if there are any other nodes
2745 * which say they are compatible with the external mdio
2746 * bus.
2747 */
2748 for_each_available_child_of_node(np, child) {
2749 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2750 if (match) {
2751 err = mv88e6xxx_mdio_register(chip, child, true);
2752 if (err)
2753 return err;
2754 }
2755 }
2756
2757 return 0;
b516d453
AL		 2758}
2759
a3c53be5 2760static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2761
2762{
a3c53be5
AL		 2763 struct mv88e6xxx_mdio_bus *mdio_bus;
2764 struct mii_bus *bus;
b516d453 2765
a3c53be5
AL		 2766 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2767 bus = mdio_bus->bus;
b516d453 2768
a3c53be5
AL		 2769 mdiobus_unregister(bus);
2770 }
b516d453
AL		 2771}
2772
855b1932
VD		 2773static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2774{
04bed143 2775 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2776
2777 return chip->eeprom_len;
2778}
2779
855b1932
VD		 2780static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2781 struct ethtool_eeprom *eeprom, u8 *data)
2782{
04bed143 2783 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2784 int err;
2785
ee4dc2e7
VD		 2786 if (!chip->info->ops->get_eeprom)
2787 return -EOPNOTSUPP;
855b1932 2788
ee4dc2e7
VD		 2789 mutex_lock(&chip->reg_lock);
2790 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2791 mutex_unlock(&chip->reg_lock);
2792
2793 if (err)
2794 return err;
2795
2796 eeprom->magic = 0xc3ec4951;
2797
2798 return 0;
2799}
2800
855b1932
VD		 2801static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2802 struct ethtool_eeprom *eeprom, u8 *data)
2803{
04bed143 2804 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2805 int err;
2806
ee4dc2e7
VD		 2807 if (!chip->info->ops->set_eeprom)
2808 return -EOPNOTSUPP;
2809
855b1932
VD		 2810 if (eeprom->magic != 0xc3ec4951)
2811 return -EINVAL;
2812
2813 mutex_lock(&chip->reg_lock);
ee4dc2e7 2814 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2815 mutex_unlock(&chip->reg_lock);
2816
2817 return err;
2818}
2819
b3469dd8 2820static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2821 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 2822 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2823 .phy_read = mv88e6xxx_phy_ppu_read,
2824 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2825 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2826 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2827 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2828 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2829 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2830 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2831 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2832 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2833 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2834 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2835 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2836 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2837 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2838 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2839 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2840 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2841 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2842 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2843 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2844 .ppu_enable = mv88e6185_g1_ppu_enable,
2845 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2846 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2847};
2848
2849static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2850 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2851 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2852 .phy_read = mv88e6xxx_phy_ppu_read,
2853 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2854 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2855 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2856 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2857 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2858 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2859 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2860 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2861 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2862 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2863 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 2864 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2865 .ppu_enable = mv88e6185_g1_ppu_enable,
2866 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2867 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2868};
2869
7d381a02 2870static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2871 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 2872 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2873 .phy_read = mv88e6xxx_g2_smi_phy_read,
2874 .phy_write = mv88e6xxx_g2_smi_phy_write,
2875 .port_set_link = mv88e6xxx_port_set_link,
2876 .port_set_duplex = mv88e6xxx_port_set_duplex,
2877 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2878 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2879 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2880 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2881 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 2882 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2883 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 2884 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2885 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2886 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2887 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2888 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2889 .stats_get_strings = mv88e6095_stats_get_strings,
2890 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2891 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2892 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2893 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2894 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2895 .reset = mv88e6352_g1_reset,
7d381a02
SE		 2896};
2897
b3469dd8 2898static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2899 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2900 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2901 .phy_read = mv88e6165_phy_read,
2902 .phy_write = mv88e6165_phy_write,
08ef7f10 2903 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2904 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2905 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2906 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2907 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2908 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2909 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2910 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2911 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2912 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2913 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2914 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2915 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2916 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2917 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2918 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 2919};
2920
2921static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2922 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2923 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2924 .phy_read = mv88e6xxx_phy_ppu_read,
2925 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2926 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2927 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2928 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2929 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2930 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2931 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2932 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2933 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
5f436666 2934 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2935 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2936 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 2937 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2938 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2939 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2940 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2941 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2942 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2943 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2944 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2945 .ppu_enable = mv88e6185_g1_ppu_enable,
2946 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2947 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2948};
2949
990e27b0
VD		 2950static const struct mv88e6xxx_ops mv88e6141_ops = {
2951 /* MV88E6XXX_FAMILY_6341 */
2952 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2953 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2954 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2955 .phy_read = mv88e6xxx_g2_smi_phy_read,
2956 .phy_write = mv88e6xxx_g2_smi_phy_write,
2957 .port_set_link = mv88e6xxx_port_set_link,
2958 .port_set_duplex = mv88e6xxx_port_set_duplex,
2959 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2960 .port_set_speed = mv88e6390_port_set_speed,
2961 .port_tag_remap = mv88e6095_port_tag_remap,
2962 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2963 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2964 .port_set_ether_type = mv88e6351_port_set_ether_type,
2965 .port_jumbo_config = mv88e6165_port_jumbo_config,
2966 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2967 .port_pause_config = mv88e6097_port_pause_config,
2968 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2969 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2970 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2971 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2972 .stats_get_strings = mv88e6320_stats_get_strings,
2973 .stats_get_stats = mv88e6390_stats_get_stats,
2974 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
2975 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
2976 .watchdog_ops = &mv88e6390_watchdog_ops,
2977 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2978 .reset = mv88e6352_g1_reset,
2979};
2980
b3469dd8 2981static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2982 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2983 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2984 .phy_read = mv88e6165_phy_read,
2985 .phy_write = mv88e6165_phy_write,
08ef7f10 2986 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2987 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2988 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2989 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2990 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2991 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2992 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 2993 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2994 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2995 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2996 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2997 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2998 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2999 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3000 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3001 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3002 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3003 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3004 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3005 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3006 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3007};
3008
3009static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3010 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3011 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3012 .phy_read = mv88e6165_phy_read,
3013 .phy_write = mv88e6165_phy_write,
08ef7f10 3014 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3015 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3016 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 3017 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3018 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3019 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3020 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3021 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3022 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3023 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3024 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3025 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3026 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3027 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3028};
3029
3030static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3031 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3032 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3033 .phy_read = mv88e6xxx_g2_smi_phy_read,
3034 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3035 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3036 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3037 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3038 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3039 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3040 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3041 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3042 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3043 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3044 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3045 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3046 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3047 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3048 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3049 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3050 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3051 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3052 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3053 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3054 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3055 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3056 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3057};
3058
3059static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3060 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3061 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3062 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3063 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3064 .phy_read = mv88e6xxx_g2_smi_phy_read,
3065 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3066 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3067 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3068 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3069 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3070 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3071 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3072 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3073 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3074 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3075 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3076 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3077 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3078 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3079 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3080 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3081 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3082 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3083 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3084 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3085 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3086 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3087 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3088};
3089
3090static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3091 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3092 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3093 .phy_read = mv88e6xxx_g2_smi_phy_read,
3094 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3095 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3096 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3097 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3098 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3099 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3100 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3101 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3102 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3103 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3104 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3105 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3106 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3107 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3108 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3109 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3110 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3111 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3112 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3113 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3114 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3115 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3116 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3117};
3118
3119static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3120 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3121 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3122 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3123 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3124 .phy_read = mv88e6xxx_g2_smi_phy_read,
3125 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3126 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3127 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3128 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3129 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3130 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3131 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3132 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3133 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3134 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3135 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3136 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3137 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3138 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3139 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3140 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3141 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3142 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3143 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3144 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3145 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3146 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3147 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3148};
3149
3150static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3151 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3152 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3153 .phy_read = mv88e6xxx_phy_ppu_read,
3154 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3155 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3156 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3157 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3158 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 3159 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 3160 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 3161 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3162 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3163 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3164 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3165 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3166 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3167 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3168 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3169 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3170 .ppu_enable = mv88e6185_g1_ppu_enable,
3171 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3172 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3173};
3174
1a3b39ec 3175static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3176 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3177 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3178 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3179 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3180 .phy_read = mv88e6xxx_g2_smi_phy_read,
3181 .phy_write = mv88e6xxx_g2_smi_phy_write,
3182 .port_set_link = mv88e6xxx_port_set_link,
3183 .port_set_duplex = mv88e6xxx_port_set_duplex,
3184 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3185 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3186 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3187 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3188 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3189 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3190 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3191 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3192 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3193 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3194 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3195 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3196 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3197 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3198 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3199 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3200 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3201 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3202 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3203};
3204
3205static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3206 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3207 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3208 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3209 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3210 .phy_read = mv88e6xxx_g2_smi_phy_read,
3211 .phy_write = mv88e6xxx_g2_smi_phy_write,
3212 .port_set_link = mv88e6xxx_port_set_link,
3213 .port_set_duplex = mv88e6xxx_port_set_duplex,
3214 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3215 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3216 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3217 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3218 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3219 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3220 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3221 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3222 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3223 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3224 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3225 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3226 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3227 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3228 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3229 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3230 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3231 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3232 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3233};
3234
3235static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3236 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3237 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3238 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3239 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3240 .phy_read = mv88e6xxx_g2_smi_phy_read,
3241 .phy_write = mv88e6xxx_g2_smi_phy_write,
3242 .port_set_link = mv88e6xxx_port_set_link,
3243 .port_set_duplex = mv88e6xxx_port_set_duplex,
3244 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3245 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3246 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3247 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3248 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3249 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3250 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3251 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3252 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3253 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3254 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3255 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3256 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3257 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3258 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3259 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3260 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3261 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3262 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3263};
3264
b3469dd8 3265static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3266 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3267 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3268 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3269 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3270 .phy_read = mv88e6xxx_g2_smi_phy_read,
3271 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3272 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3273 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3274 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3275 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3276 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3277 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3278 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3279 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3280 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3281 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3282 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3283 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3284 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3285 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3286 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3287 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3288 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3289 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3290 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3291 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3292 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3293 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3294};
3295
1a3b39ec 3296static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3297 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3298 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3299 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3301 .phy_read = mv88e6xxx_g2_smi_phy_read,
3302 .phy_write = mv88e6xxx_g2_smi_phy_write,
3303 .port_set_link = mv88e6xxx_port_set_link,
3304 .port_set_duplex = mv88e6xxx_port_set_duplex,
3305 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3306 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3307 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3308 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3309 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3310 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3311 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3312 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3313 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3314 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3315 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3316 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3317 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3318 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3319 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3320 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3321 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3322 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3323 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3324 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3325};
3326
b3469dd8 3327static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3328 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3329 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3330 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3331 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3332 .phy_read = mv88e6xxx_g2_smi_phy_read,
3333 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3334 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3335 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3336 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3337 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3338 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3339 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3340 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3341 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3342 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3343 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3344 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3345 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3346 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3347 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3348 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3349 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3350 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3351 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3352 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3353 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3354};
3355
3356static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3357 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3358 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3359 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3360 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3361 .phy_read = mv88e6xxx_g2_smi_phy_read,
3362 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3363 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3364 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3365 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3366 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3367 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3368 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3369 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3370 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3371 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3372 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3373 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3374 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3375 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3376 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3377 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3378 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3379 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3380 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3381 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3382};
3383
16e329ae
VD		 3384static const struct mv88e6xxx_ops mv88e6341_ops = {
3385 /* MV88E6XXX_FAMILY_6341 */
3386 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3387 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3388 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3389 .phy_read = mv88e6xxx_g2_smi_phy_read,
3390 .phy_write = mv88e6xxx_g2_smi_phy_write,
3391 .port_set_link = mv88e6xxx_port_set_link,
3392 .port_set_duplex = mv88e6xxx_port_set_duplex,
3393 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3394 .port_set_speed = mv88e6390_port_set_speed,
3395 .port_tag_remap = mv88e6095_port_tag_remap,
3396 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3397 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3398 .port_set_ether_type = mv88e6351_port_set_ether_type,
3399 .port_jumbo_config = mv88e6165_port_jumbo_config,
3400 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3401 .port_pause_config = mv88e6097_port_pause_config,
3402 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3403 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3404 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3405 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3406 .stats_get_strings = mv88e6320_stats_get_strings,
3407 .stats_get_stats = mv88e6390_stats_get_stats,
3408 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3409 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3410 .watchdog_ops = &mv88e6390_watchdog_ops,
3411 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3412 .reset = mv88e6352_g1_reset,
3413};
3414
b3469dd8 3415static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3416 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3417 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3418 .phy_read = mv88e6xxx_g2_smi_phy_read,
3419 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3420 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3421 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3422 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3423 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3424 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3425 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3426 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3427 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3428 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3429 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3430 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3431 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3432 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3433 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3434 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3435 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3436 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3437 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3438 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3439 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3440 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3441 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3442};
3443
3444static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3445 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3446 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3447 .phy_read = mv88e6xxx_g2_smi_phy_read,
3448 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3449 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3450 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3451 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3452 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3453 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3454 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3455 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3456 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3457 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3459 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3462 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3463 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3464 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3465 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3466 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3467 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3468 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3469 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3470 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3471};
3472
3473static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3474 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3475 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3476 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3477 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3478 .phy_read = mv88e6xxx_g2_smi_phy_read,
3479 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3480 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3481 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3482 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3483 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3484 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3485 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3486 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3487 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3488 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3489 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3490 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3491 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3492 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3493 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3494 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3495 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3496 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3497 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3498 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3499 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3500 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3501 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3502};
3503
1a3b39ec 3504static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3505 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3506 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3507 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3508 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3509 .phy_read = mv88e6xxx_g2_smi_phy_read,
3510 .phy_write = mv88e6xxx_g2_smi_phy_write,
3511 .port_set_link = mv88e6xxx_port_set_link,
3512 .port_set_duplex = mv88e6xxx_port_set_duplex,
3513 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3514 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3515 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3516 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3517 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3518 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3519 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3520 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3521 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3522 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3523 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3524 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3525 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3526 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3527 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3528 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3529 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3530 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3531 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3532 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3533 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3534 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3535};
3536
3537static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3538 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3539 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3540 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3541 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3542 .phy_read = mv88e6xxx_g2_smi_phy_read,
3543 .phy_write = mv88e6xxx_g2_smi_phy_write,
3544 .port_set_link = mv88e6xxx_port_set_link,
3545 .port_set_duplex = mv88e6xxx_port_set_duplex,
3546 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3547 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3548 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3549 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3550 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3551 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3552 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3553 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3554 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3555 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3556 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3557 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3558 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3559 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3560 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3561 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3562 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3563 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3564 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3565 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3566 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3567};
3568
f81ec90f
VD		 3569static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3570 [MV88E6085] = {
3571 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3572 .family = MV88E6XXX_FAMILY_6097,
3573 .name = "Marvell 88E6085",
3574 .num_databases = 4096,
3575 .num_ports = 10,
9dddd478 3576 .port_base_addr = 0x10,
a935c052 3577 .global1_addr = 0x1b,
acddbd21 3578 .age_time_coeff = 15000,
dc30c35b 3579 .g1_irqs = 8,
e606ca36 3580 .atu_move_port_mask = 0xf,
443d5a1b 3581 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3582 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3583 .ops = &mv88e6085_ops,
f81ec90f
VD		 3584 },
3585
3586 [MV88E6095] = {
3587 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3588 .family = MV88E6XXX_FAMILY_6095,
3589 .name = "Marvell 88E6095/88E6095F",
3590 .num_databases = 256,
3591 .num_ports = 11,
9dddd478 3592 .port_base_addr = 0x10,
a935c052 3593 .global1_addr = 0x1b,
acddbd21 3594 .age_time_coeff = 15000,
dc30c35b 3595 .g1_irqs = 8,
e606ca36 3596 .atu_move_port_mask = 0xf,
443d5a1b 3597 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3598 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3599 .ops = &mv88e6095_ops,
f81ec90f
VD		 3600 },
3601
7d381a02
SE		 3602 [MV88E6097] = {
3603 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3604 .family = MV88E6XXX_FAMILY_6097,
3605 .name = "Marvell 88E6097/88E6097F",
3606 .num_databases = 4096,
3607 .num_ports = 11,
3608 .port_base_addr = 0x10,
3609 .global1_addr = 0x1b,
3610 .age_time_coeff = 15000,
c534178b 3611 .g1_irqs = 8,
e606ca36 3612 .atu_move_port_mask = 0xf,
2bfcfcd3 3613 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3614 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3615 .ops = &mv88e6097_ops,
3616 },
3617
f81ec90f
VD		 3618 [MV88E6123] = {
3619 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3620 .family = MV88E6XXX_FAMILY_6165,
3621 .name = "Marvell 88E6123",
3622 .num_databases = 4096,
3623 .num_ports = 3,
9dddd478 3624 .port_base_addr = 0x10,
a935c052 3625 .global1_addr = 0x1b,
acddbd21 3626 .age_time_coeff = 15000,
dc30c35b 3627 .g1_irqs = 9,
e606ca36 3628 .atu_move_port_mask = 0xf,
443d5a1b 3629 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3630 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3631 .ops = &mv88e6123_ops,
f81ec90f
VD		 3632 },
3633
3634 [MV88E6131] = {
3635 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3636 .family = MV88E6XXX_FAMILY_6185,
3637 .name = "Marvell 88E6131",
3638 .num_databases = 256,
3639 .num_ports = 8,
9dddd478 3640 .port_base_addr = 0x10,
a935c052 3641 .global1_addr = 0x1b,
acddbd21 3642 .age_time_coeff = 15000,
dc30c35b 3643 .g1_irqs = 9,
e606ca36 3644 .atu_move_port_mask = 0xf,
443d5a1b 3645 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3646 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3647 .ops = &mv88e6131_ops,
f81ec90f
VD		 3648 },
3649
990e27b0
VD		 3650 [MV88E6141] = {
3651 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3652 .family = MV88E6XXX_FAMILY_6341,
3653 .name = "Marvell 88E6341",
3654 .num_databases = 4096,
3655 .num_ports = 6,
3656 .port_base_addr = 0x10,
3657 .global1_addr = 0x1b,
3658 .age_time_coeff = 3750,
3659 .atu_move_port_mask = 0x1f,
3660 .tag_protocol = DSA_TAG_PROTO_EDSA,
3661 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3662 .ops = &mv88e6141_ops,
3663 },
3664
f81ec90f
VD		 3665 [MV88E6161] = {
3666 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3667 .family = MV88E6XXX_FAMILY_6165,
3668 .name = "Marvell 88E6161",
3669 .num_databases = 4096,
3670 .num_ports = 6,
9dddd478 3671 .port_base_addr = 0x10,
a935c052 3672 .global1_addr = 0x1b,
acddbd21 3673 .age_time_coeff = 15000,
dc30c35b 3674 .g1_irqs = 9,
e606ca36 3675 .atu_move_port_mask = 0xf,
443d5a1b 3676 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3677 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3678 .ops = &mv88e6161_ops,
f81ec90f
VD		 3679 },
3680
3681 [MV88E6165] = {
3682 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3683 .family = MV88E6XXX_FAMILY_6165,
3684 .name = "Marvell 88E6165",
3685 .num_databases = 4096,
3686 .num_ports = 6,
9dddd478 3687 .port_base_addr = 0x10,
a935c052 3688 .global1_addr = 0x1b,
acddbd21 3689 .age_time_coeff = 15000,
dc30c35b 3690 .g1_irqs = 9,
e606ca36 3691 .atu_move_port_mask = 0xf,
443d5a1b 3692 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3693 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3694 .ops = &mv88e6165_ops,
f81ec90f
VD		 3695 },
3696
3697 [MV88E6171] = {
3698 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3699 .family = MV88E6XXX_FAMILY_6351,
3700 .name = "Marvell 88E6171",
3701 .num_databases = 4096,
3702 .num_ports = 7,
9dddd478 3703 .port_base_addr = 0x10,
a935c052 3704 .global1_addr = 0x1b,
acddbd21 3705 .age_time_coeff = 15000,
dc30c35b 3706 .g1_irqs = 9,
e606ca36 3707 .atu_move_port_mask = 0xf,
443d5a1b 3708 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3709 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3710 .ops = &mv88e6171_ops,
f81ec90f
VD		 3711 },
3712
3713 [MV88E6172] = {
3714 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3715 .family = MV88E6XXX_FAMILY_6352,
3716 .name = "Marvell 88E6172",
3717 .num_databases = 4096,
3718 .num_ports = 7,
9dddd478 3719 .port_base_addr = 0x10,
a935c052 3720 .global1_addr = 0x1b,
acddbd21 3721 .age_time_coeff = 15000,
dc30c35b 3722 .g1_irqs = 9,
e606ca36 3723 .atu_move_port_mask = 0xf,
443d5a1b 3724 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3725 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3726 .ops = &mv88e6172_ops,
f81ec90f
VD		 3727 },
3728
3729 [MV88E6175] = {
3730 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3731 .family = MV88E6XXX_FAMILY_6351,
3732 .name = "Marvell 88E6175",
3733 .num_databases = 4096,
3734 .num_ports = 7,
9dddd478 3735 .port_base_addr = 0x10,
a935c052 3736 .global1_addr = 0x1b,
acddbd21 3737 .age_time_coeff = 15000,
dc30c35b 3738 .g1_irqs = 9,
e606ca36 3739 .atu_move_port_mask = 0xf,
443d5a1b 3740 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3741 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3742 .ops = &mv88e6175_ops,
f81ec90f
VD		 3743 },
3744
3745 [MV88E6176] = {
3746 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3747 .family = MV88E6XXX_FAMILY_6352,
3748 .name = "Marvell 88E6176",
3749 .num_databases = 4096,
3750 .num_ports = 7,
9dddd478 3751 .port_base_addr = 0x10,
a935c052 3752 .global1_addr = 0x1b,
acddbd21 3753 .age_time_coeff = 15000,
dc30c35b 3754 .g1_irqs = 9,
e606ca36 3755 .atu_move_port_mask = 0xf,
443d5a1b 3756 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3757 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3758 .ops = &mv88e6176_ops,
f81ec90f
VD		 3759 },
3760
3761 [MV88E6185] = {
3762 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3763 .family = MV88E6XXX_FAMILY_6185,
3764 .name = "Marvell 88E6185",
3765 .num_databases = 256,
3766 .num_ports = 10,
9dddd478 3767 .port_base_addr = 0x10,
a935c052 3768 .global1_addr = 0x1b,
acddbd21 3769 .age_time_coeff = 15000,
dc30c35b 3770 .g1_irqs = 8,
e606ca36 3771 .atu_move_port_mask = 0xf,
443d5a1b 3772 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3773 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3774 .ops = &mv88e6185_ops,
f81ec90f
VD		 3775 },
3776
1a3b39ec
AL		 3777 [MV88E6190] = {
3778 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3779 .family = MV88E6XXX_FAMILY_6390,
3780 .name = "Marvell 88E6190",
3781 .num_databases = 4096,
3782 .num_ports = 11, /* 10 + Z80 */
3783 .port_base_addr = 0x0,
3784 .global1_addr = 0x1b,
443d5a1b 3785 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3786 .age_time_coeff = 3750,
1a3b39ec 3787 .g1_irqs = 9,
e606ca36 3788 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3789 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3790 .ops = &mv88e6190_ops,
3791 },
3792
3793 [MV88E6190X] = {
3794 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3795 .family = MV88E6XXX_FAMILY_6390,
3796 .name = "Marvell 88E6190X",
3797 .num_databases = 4096,
3798 .num_ports = 11, /* 10 + Z80 */
3799 .port_base_addr = 0x0,
3800 .global1_addr = 0x1b,
b91e055c 3801 .age_time_coeff = 3750,
1a3b39ec 3802 .g1_irqs = 9,
e606ca36 3803 .atu_move_port_mask = 0x1f,
443d5a1b 3804 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3805 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3806 .ops = &mv88e6190x_ops,
3807 },
3808
3809 [MV88E6191] = {
3810 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3811 .family = MV88E6XXX_FAMILY_6390,
3812 .name = "Marvell 88E6191",
3813 .num_databases = 4096,
3814 .num_ports = 11, /* 10 + Z80 */
3815 .port_base_addr = 0x0,
3816 .global1_addr = 0x1b,
b91e055c 3817 .age_time_coeff = 3750,
443d5a1b 3818 .g1_irqs = 9,
e606ca36 3819 .atu_move_port_mask = 0x1f,
443d5a1b 3820 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec 3821 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
2cf4cefb 3822 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3823 },
3824
f81ec90f
VD		 3825 [MV88E6240] = {
3826 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3827 .family = MV88E6XXX_FAMILY_6352,
3828 .name = "Marvell 88E6240",
3829 .num_databases = 4096,
3830 .num_ports = 7,
9dddd478 3831 .port_base_addr = 0x10,
a935c052 3832 .global1_addr = 0x1b,
acddbd21 3833 .age_time_coeff = 15000,
dc30c35b 3834 .g1_irqs = 9,
e606ca36 3835 .atu_move_port_mask = 0xf,
443d5a1b 3836 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3837 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3838 .ops = &mv88e6240_ops,
f81ec90f
VD		 3839 },
3840
1a3b39ec
AL		 3841 [MV88E6290] = {
3842 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3843 .family = MV88E6XXX_FAMILY_6390,
3844 .name = "Marvell 88E6290",
3845 .num_databases = 4096,
3846 .num_ports = 11, /* 10 + Z80 */
3847 .port_base_addr = 0x0,
3848 .global1_addr = 0x1b,
b91e055c 3849 .age_time_coeff = 3750,
1a3b39ec 3850 .g1_irqs = 9,
e606ca36 3851 .atu_move_port_mask = 0x1f,
443d5a1b 3852 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3853 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3854 .ops = &mv88e6290_ops,
3855 },
3856
f81ec90f
VD		 3857 [MV88E6320] = {
3858 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3859 .family = MV88E6XXX_FAMILY_6320,
3860 .name = "Marvell 88E6320",
3861 .num_databases = 4096,
3862 .num_ports = 7,
9dddd478 3863 .port_base_addr = 0x10,
a935c052 3864 .global1_addr = 0x1b,
acddbd21 3865 .age_time_coeff = 15000,
dc30c35b 3866 .g1_irqs = 8,
e606ca36 3867 .atu_move_port_mask = 0xf,
443d5a1b 3868 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3869 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3870 .ops = &mv88e6320_ops,
f81ec90f
VD		 3871 },
3872
3873 [MV88E6321] = {
3874 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3875 .family = MV88E6XXX_FAMILY_6320,
3876 .name = "Marvell 88E6321",
3877 .num_databases = 4096,
3878 .num_ports = 7,
9dddd478 3879 .port_base_addr = 0x10,
a935c052 3880 .global1_addr = 0x1b,
acddbd21 3881 .age_time_coeff = 15000,
dc30c35b 3882 .g1_irqs = 8,
e606ca36 3883 .atu_move_port_mask = 0xf,
443d5a1b 3884 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3885 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3886 .ops = &mv88e6321_ops,
f81ec90f
VD		 3887 },
3888
a75961d0
GC		 3889 [MV88E6341] = {
3890 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
3891 .family = MV88E6XXX_FAMILY_6341,
3892 .name = "Marvell 88E6341",
3893 .num_databases = 4096,
3894 .num_ports = 6,
3895 .port_base_addr = 0x10,
3896 .global1_addr = 0x1b,
3897 .age_time_coeff = 3750,
e606ca36 3898 .atu_move_port_mask = 0x1f,
a75961d0
GC		 3899 .tag_protocol = DSA_TAG_PROTO_EDSA,
3900 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3901 .ops = &mv88e6341_ops,
3902 },
3903
f81ec90f
VD		 3904 [MV88E6350] = {
3905 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3906 .family = MV88E6XXX_FAMILY_6351,
3907 .name = "Marvell 88E6350",
3908 .num_databases = 4096,
3909 .num_ports = 7,
9dddd478 3910 .port_base_addr = 0x10,
a935c052 3911 .global1_addr = 0x1b,
acddbd21 3912 .age_time_coeff = 15000,
dc30c35b 3913 .g1_irqs = 9,
e606ca36 3914 .atu_move_port_mask = 0xf,
443d5a1b 3915 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3916 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3917 .ops = &mv88e6350_ops,
f81ec90f
VD		 3918 },
3919
3920 [MV88E6351] = {
3921 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3922 .family = MV88E6XXX_FAMILY_6351,
3923 .name = "Marvell 88E6351",
3924 .num_databases = 4096,
3925 .num_ports = 7,
9dddd478 3926 .port_base_addr = 0x10,
a935c052 3927 .global1_addr = 0x1b,
acddbd21 3928 .age_time_coeff = 15000,
dc30c35b 3929 .g1_irqs = 9,
e606ca36 3930 .atu_move_port_mask = 0xf,
443d5a1b 3931 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3932 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3933 .ops = &mv88e6351_ops,
f81ec90f
VD		 3934 },
3935
3936 [MV88E6352] = {
3937 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3938 .family = MV88E6XXX_FAMILY_6352,
3939 .name = "Marvell 88E6352",
3940 .num_databases = 4096,
3941 .num_ports = 7,
9dddd478 3942 .port_base_addr = 0x10,
a935c052 3943 .global1_addr = 0x1b,
acddbd21 3944 .age_time_coeff = 15000,
dc30c35b 3945 .g1_irqs = 9,
e606ca36 3946 .atu_move_port_mask = 0xf,
443d5a1b 3947 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3948 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3949 .ops = &mv88e6352_ops,
f81ec90f 3950 },
1a3b39ec
AL		 3951 [MV88E6390] = {
3952 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3953 .family = MV88E6XXX_FAMILY_6390,
3954 .name = "Marvell 88E6390",
3955 .num_databases = 4096,
3956 .num_ports = 11, /* 10 + Z80 */
3957 .port_base_addr = 0x0,
3958 .global1_addr = 0x1b,
b91e055c 3959 .age_time_coeff = 3750,
1a3b39ec 3960 .g1_irqs = 9,
e606ca36 3961 .atu_move_port_mask = 0x1f,
443d5a1b 3962 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3963 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3964 .ops = &mv88e6390_ops,
3965 },
3966 [MV88E6390X] = {
3967 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3968 .family = MV88E6XXX_FAMILY_6390,
3969 .name = "Marvell 88E6390X",
3970 .num_databases = 4096,
3971 .num_ports = 11, /* 10 + Z80 */
3972 .port_base_addr = 0x0,
3973 .global1_addr = 0x1b,
b91e055c 3974 .age_time_coeff = 3750,
1a3b39ec 3975 .g1_irqs = 9,
e606ca36 3976 .atu_move_port_mask = 0x1f,
443d5a1b 3977 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3978 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3979 .ops = &mv88e6390x_ops,
3980 },
f81ec90f
VD		 3981};
3982
5f7c0367 3983static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3984{
a439c061 3985 int i;
b9b37713 3986
5f7c0367
VD		 3987 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3988 if (mv88e6xxx_table[i].prod_num == prod_num)
3989 return &mv88e6xxx_table[i];
b9b37713 3990
b9b37713
VD		 3991 return NULL;
3992}
3993
fad09c73 3994static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3995{
3996 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3997 unsigned int prod_num, rev;
3998 u16 id;
3999 int err;
bc46a3d5 4000
8f6345b2
VD		 4001 mutex_lock(&chip->reg_lock);
4002 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4003 mutex_unlock(&chip->reg_lock);
4004 if (err)
4005 return err;
bc46a3d5
VD		 4006
4007 prod_num = (id & 0xfff0) >> 4;
4008 rev = id & 0x000f;
4009
4010 info = mv88e6xxx_lookup_info(prod_num);
4011 if (!info)
4012 return -ENODEV;
4013
caac8545 4014 /* Update the compatible info with the probed one */
fad09c73 4015 chip->info = info;
bc46a3d5 4016
ca070c10
VD		 4017 err = mv88e6xxx_g2_require(chip);
4018 if (err)
4019 return err;
4020
fad09c73
VD		 4021 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4022 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4023
4024 return 0;
4025}
4026
fad09c73 4027static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4028{
fad09c73 4029 struct mv88e6xxx_chip *chip;
469d729f 4030
fad09c73
VD		 4031 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4032 if (!chip)
469d729f
VD		 4033 return NULL;
4034
fad09c73 4035 chip->dev = dev;
469d729f 4036
fad09c73 4037 mutex_init(&chip->reg_lock);
a3c53be5 4038 INIT_LIST_HEAD(&chip->mdios);
469d729f 4039
fad09c73 4040 return chip;
469d729f
VD		 4041}
4042
e57e5e77
VD		 4043static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4044{
a199d8b6 4045 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4046 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4047}
4048
930188ce
AL		 4049static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4050{
a199d8b6 4051 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4052 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4053}
4054
fad09c73 4055static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4056 struct mii_bus *bus, int sw_addr)
4057{
914b32f6 4058 if (sw_addr == 0)
fad09c73 4059 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4060 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4061 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4062 else
4063 return -EINVAL;
4064
fad09c73
VD		 4065 chip->bus = bus;
4066 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4067
4068 return 0;
4069}
4070
7b314362
AL		 4071static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4072{
04bed143 4073 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4074
443d5a1b 4075 return chip->info->tag_protocol;
7b314362
AL		 4076}
4077
fcdce7d0
AL		 4078static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4079 struct device *host_dev, int sw_addr,
4080 void **priv)
a77d43f1 4081{
fad09c73 4082 struct mv88e6xxx_chip *chip;
a439c061 4083 struct mii_bus *bus;
b516d453 4084 int err;
a77d43f1 4085
a439c061 4086 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4087 if (!bus)
4088 return NULL;
4089
fad09c73
VD		 4090 chip = mv88e6xxx_alloc_chip(dsa_dev);
4091 if (!chip)
469d729f
VD		 4092 return NULL;
4093
caac8545 4094 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4095 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4096
fad09c73 4097 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4098 if (err)
4099 goto free;
4100
fad09c73 4101 err = mv88e6xxx_detect(chip);
bc46a3d5 4102 if (err)
469d729f 4103 goto free;
a439c061 4104
dc30c35b
AL		 4105 mutex_lock(&chip->reg_lock);
4106 err = mv88e6xxx_switch_reset(chip);
4107 mutex_unlock(&chip->reg_lock);
4108 if (err)
4109 goto free;
4110
e57e5e77
VD		 4111 mv88e6xxx_phy_init(chip);
4112
a3c53be5 4113 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4114 if (err)
469d729f 4115 goto free;
b516d453 4116
fad09c73 4117 *priv = chip;
a439c061 4118
fad09c73 4119 return chip->info->name;
469d729f 4120free:
fad09c73 4121 devm_kfree(dsa_dev, chip);
469d729f
VD		 4122
4123 return NULL;
a77d43f1
AL		 4124}
4125
7df8fbdd
VD		 4126static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4127 const struct switchdev_obj_port_mdb *mdb,
4128 struct switchdev_trans *trans)
4129{
4130 /* We don't need any dynamic resource from the kernel (yet),
4131 * so skip the prepare phase.
4132 */
4133
4134 return 0;
4135}
4136
4137static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4138 const struct switchdev_obj_port_mdb *mdb,
4139 struct switchdev_trans *trans)
4140{
04bed143 4141 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4142
4143 mutex_lock(&chip->reg_lock);
4144 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4145 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4146 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4147 mutex_unlock(&chip->reg_lock);
4148}
4149
4150static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4151 const struct switchdev_obj_port_mdb *mdb)
4152{
04bed143 4153 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4154 int err;
4155
4156 mutex_lock(&chip->reg_lock);
4157 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4158 GLOBAL_ATU_DATA_STATE_UNUSED);
4159 mutex_unlock(&chip->reg_lock);
4160
4161 return err;
4162}
4163
4164static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4165 struct switchdev_obj_port_mdb *mdb,
4166 int (*cb)(struct switchdev_obj *obj))
4167{
04bed143 4168 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4169 int err;
4170
4171 mutex_lock(&chip->reg_lock);
4172 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4173 mutex_unlock(&chip->reg_lock);
4174
4175 return err;
4176}
4177
a82f67af 4178static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4179 .probe = mv88e6xxx_drv_probe,
7b314362 4180 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4181 .setup = mv88e6xxx_setup,
4182 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4183 .adjust_link = mv88e6xxx_adjust_link,
4184 .get_strings = mv88e6xxx_get_strings,
4185 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4186 .get_sset_count = mv88e6xxx_get_sset_count,
4187 .set_eee = mv88e6xxx_set_eee,
4188 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4189 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4190 .get_eeprom = mv88e6xxx_get_eeprom,
4191 .set_eeprom = mv88e6xxx_set_eeprom,
4192 .get_regs_len = mv88e6xxx_get_regs_len,
4193 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4194 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4195 .port_bridge_join = mv88e6xxx_port_bridge_join,
4196 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4197 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4198 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4199 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4200 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4201 .port_vlan_add = mv88e6xxx_port_vlan_add,
4202 .port_vlan_del = mv88e6xxx_port_vlan_del,
4203 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4204 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4205 .port_fdb_add = mv88e6xxx_port_fdb_add,
4206 .port_fdb_del = mv88e6xxx_port_fdb_del,
4207 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4208 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4209 .port_mdb_add = mv88e6xxx_port_mdb_add,
4210 .port_mdb_del = mv88e6xxx_port_mdb_del,
4211 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4212};
4213
ab3d408d
FF		 4214static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4215 .ops = &mv88e6xxx_switch_ops,
4216};
4217
55ed0ce0 4218static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4219{
fad09c73 4220 struct device *dev = chip->dev;
b7e66a5f
VD		 4221 struct dsa_switch *ds;
4222
a0c02161 4223 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
b7e66a5f
VD		 4224 if (!ds)
4225 return -ENOMEM;
4226
fad09c73 4227 ds->priv = chip;
9d490b4e 4228 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 4229 ds->ageing_time_min = chip->info->age_time_coeff;
4230 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 4231
4232 dev_set_drvdata(dev, ds);
4233
55ed0ce0 4234 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4235}
4236
fad09c73 4237static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4238{
fad09c73 4239 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4240}
4241
57d32310 4242static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4243{
14c7b3c3 4244 struct device *dev = &mdiodev->dev;
f8cd8753 4245 struct device_node *np = dev->of_node;
caac8545 4246 const struct mv88e6xxx_info *compat_info;
fad09c73 4247 struct mv88e6xxx_chip *chip;
f8cd8753 4248 u32 eeprom_len;
52638f71 4249 int err;
14c7b3c3 4250
caac8545
VD		 4251 compat_info = of_device_get_match_data(dev);
4252 if (!compat_info)
4253 return -EINVAL;
4254
fad09c73
VD		 4255 chip = mv88e6xxx_alloc_chip(dev);
4256 if (!chip)
14c7b3c3
AL		 4257 return -ENOMEM;
4258
fad09c73 4259 chip->info = compat_info;
caac8545 4260
fad09c73 4261 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4262 if (err)
4263 return err;
14c7b3c3 4264
b4308f04
AL		 4265 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4266 if (IS_ERR(chip->reset))
4267 return PTR_ERR(chip->reset);
4268
fad09c73 4269 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4270 if (err)
4271 return err;
14c7b3c3 4272
e57e5e77
VD		 4273 mv88e6xxx_phy_init(chip);
4274
ee4dc2e7 4275 if (chip->info->ops->get_eeprom &&
f8cd8753 4276 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4277 chip->eeprom_len = eeprom_len;
f8cd8753 4278
dc30c35b
AL		 4279 mutex_lock(&chip->reg_lock);
4280 err = mv88e6xxx_switch_reset(chip);
4281 mutex_unlock(&chip->reg_lock);
4282 if (err)
4283 goto out;
4284
4285 chip->irq = of_irq_get(np, 0);
4286 if (chip->irq == -EPROBE_DEFER) {
4287 err = chip->irq;
4288 goto out;
4289 }
4290
4291 if (chip->irq > 0) {
4292 /* Has to be performed before the MDIO bus is created,
4293 * because the PHYs will link there interrupts to these
4294 * interrupt controllers
4295 */
4296 mutex_lock(&chip->reg_lock);
4297 err = mv88e6xxx_g1_irq_setup(chip);
4298 mutex_unlock(&chip->reg_lock);
4299
4300 if (err)
4301 goto out;
4302
4303 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4304 err = mv88e6xxx_g2_irq_setup(chip);
4305 if (err)
4306 goto out_g1_irq;
4307 }
4308 }
4309
a3c53be5 4310 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4311 if (err)
dc30c35b 4312 goto out_g2_irq;
b516d453 4313
55ed0ce0 4314 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4315 if (err)
4316 goto out_mdio;
83c0afae 4317
98e67308 4318 return 0;
dc30c35b
AL		 4319
4320out_mdio:
a3c53be5 4321 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4322out_g2_irq:
46712644 4323 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4324 mv88e6xxx_g2_irq_free(chip);
4325out_g1_irq:
61f7c3f8
AL		 4326 if (chip->irq > 0) {
4327 mutex_lock(&chip->reg_lock);
46712644 4328 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4329 mutex_unlock(&chip->reg_lock);
4330 }
dc30c35b
AL		 4331out:
4332 return err;
98e67308 4333}
14c7b3c3
AL		 4334
4335static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4336{
4337 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4338 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4339
930188ce 4340 mv88e6xxx_phy_destroy(chip);
fad09c73 4341 mv88e6xxx_unregister_switch(chip);
a3c53be5 4342 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4343
46712644
AL		 4344 if (chip->irq > 0) {
4345 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4346 mv88e6xxx_g2_irq_free(chip);
4347 mv88e6xxx_g1_irq_free(chip);
4348 }
14c7b3c3
AL		 4349}
4350
4351static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4352 {
4353 .compatible = "marvell,mv88e6085",
4354 .data = &mv88e6xxx_table[MV88E6085],
4355 },
1a3b39ec
AL		 4356 {
4357 .compatible = "marvell,mv88e6190",
4358 .data = &mv88e6xxx_table[MV88E6190],
4359 },
14c7b3c3
AL		 4360 { /* sentinel */ },
4361};
4362
4363MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4364
4365static struct mdio_driver mv88e6xxx_driver = {
4366 .probe = mv88e6xxx_probe,
4367 .remove = mv88e6xxx_remove,
4368 .mdiodrv.driver = {
4369 .name = "mv88e6085",
4370 .of_match_table = mv88e6xxx_of_match,
4371 },
4372};
4373
4374static int __init mv88e6xxx_init(void)
4375{
ab3d408d 4376 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4377 return mdio_driver_register(&mv88e6xxx_driver);
4378}
98e67308
BH		 4379module_init(mv88e6xxx_init);
4380
4381static void __exit mv88e6xxx_cleanup(void)
4382{
14c7b3c3 4383 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4384 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4385}
4386module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4387
4388MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4389MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4390MODULE_LICENSE("GPL");
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