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net: dsa: mv88e6xxx: Release lock while requesting IRQ
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
ec561276 35
4d5f2ba7 36#include "chip.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
6d91782f 41#include "serdes.h"
91da11f8 42
fad09c73 43static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 44{
fad09c73
VD		 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 47 dump_stack();
48 }
49}
50
914b32f6
VD		 51/* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 *
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 *
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 61 */
914b32f6 62
fad09c73 63static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 *val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 val)
74{
fad09c73 75 if (!chip->smi_ops)
914b32f6
VD		 76 return -EOPNOTSUPP;
77
fad09c73 78 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 79}
80
fad09c73 81static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 82 int addr, int reg, u16 *val)
83{
84 int ret;
85
fad09c73 86 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 87 if (ret < 0)
88 return ret;
89
90 *val = ret & 0xffff;
91
92 return 0;
93}
94
fad09c73 95static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 96 int addr, int reg, u16 val)
97{
98 int ret;
99
fad09c73 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 101 if (ret < 0)
102 return ret;
103
104 return 0;
105}
106
c08026ab 107static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
110};
111
fad09c73 112static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 113{
114 int ret;
115 int i;
116
117 for (i = 0; i < 16; i++) {
fad09c73 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 119 if (ret < 0)
120 return ret;
121
cca8b133 122 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 123 return 0;
124 }
125
126 return -ETIMEDOUT;
127}
128
fad09c73 129static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 130 int addr, int reg, u16 *val)
91da11f8
LB		 131{
132 int ret;
133
3675c8d7 134 /* Wait for the bus to become free. */
fad09c73 135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the read command. */
fad09c73 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the read command to complete. */
fad09c73 146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 147 if (ret < 0)
148 return ret;
149
3675c8d7 150 /* Read the data. */
fad09c73 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 152 if (ret < 0)
153 return ret;
154
914b32f6 155 *val = ret & 0xffff;
91da11f8 156
914b32f6 157 return 0;
8d6d09e7
GR		 158}
159
fad09c73 160static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 161 int addr, int reg, u16 val)
91da11f8
LB		 162{
163 int ret;
164
3675c8d7 165 /* Wait for the bus to become free. */
fad09c73 166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 167 if (ret < 0)
168 return ret;
169
3675c8d7 170 /* Transmit the data to write. */
fad09c73 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Transmit the write command. */
fad09c73 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 178 if (ret < 0)
179 return ret;
180
3675c8d7 181 /* Wait for the write command to complete. */
fad09c73 182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 183 if (ret < 0)
184 return ret;
185
186 return 0;
187}
188
c08026ab 189static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
192};
193
ec561276 194int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 195{
196 int err;
197
fad09c73 198 assert_reg_lock(chip);
914b32f6 199
fad09c73 200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 201 if (err)
202 return err;
203
fad09c73 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 205 addr, reg, *val);
206
207 return 0;
208}
209
ec561276 210int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 211{
914b32f6
VD		 212 int err;
213
fad09c73 214 assert_reg_lock(chip);
91da11f8 215
fad09c73 216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 217 if (err)
218 return err;
219
fad09c73 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 221 addr, reg, val);
222
914b32f6
VD		 223 return 0;
224}
225
10fa5bfc 226struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 227{
228 struct mv88e6xxx_mdio_bus *mdio_bus;
229
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
231 list);
232 if (!mdio_bus)
233 return NULL;
234
235 return mdio_bus->bus;
236}
237
dc30c35b
AL		 238static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
239{
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
242
243 chip->g1_irq.masked |= (1 << n);
244}
245
246static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
247{
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
250
251 chip->g1_irq.masked &= ~(1 << n);
252}
253
254static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
255{
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
259 unsigned int n;
260 u16 reg;
f0b95e6b 261 u16 ctl1;
dc30c35b
AL		 262 int err;
263
264 mutex_lock(&chip->reg_lock);
82466921 265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b
AL		 266 mutex_unlock(&chip->reg_lock);
267
268 if (err)
269 goto out;
270
f0b95e6b
JDA		 271 do {
272 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
273 if (reg & (1 << n)) {
274 sub_irq = irq_find_mapping(chip->g1_irq.domain,
275 n);
276 handle_nested_irq(sub_irq);
277 ++nhandled;
278 }
dc30c35b 279 }
f0b95e6b
JDA		 280
281 mutex_lock(&chip->reg_lock);
282 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
283 if (err)
284 goto unlock;
285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
286unlock:
287 mutex_unlock(&chip->reg_lock);
288 if (err)
289 goto out;
290 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
291 } while (reg & ctl1);
292
dc30c35b
AL		 293out:
294 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
295}
296
297static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
298{
299 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
300
301 mutex_lock(&chip->reg_lock);
302}
303
304static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
305{
306 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
307 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
308 u16 reg;
309 int err;
310
d77f4321 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 312 if (err)
313 goto out;
314
315 reg &= ~mask;
316 reg |= (~chip->g1_irq.masked & mask);
317
d77f4321 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 319 if (err)
320 goto out;
321
322out:
323 mutex_unlock(&chip->reg_lock);
324}
325
6eb15e21 326static const struct irq_chip mv88e6xxx_g1_irq_chip = {
dc30c35b
AL		 327 .name = "mv88e6xxx-g1",
328 .irq_mask = mv88e6xxx_g1_irq_mask,
329 .irq_unmask = mv88e6xxx_g1_irq_unmask,
330 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
331 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
332};
333
334static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
335 unsigned int irq,
336 irq_hw_number_t hwirq)
337{
338 struct mv88e6xxx_chip *chip = d->host_data;
339
340 irq_set_chip_data(irq, d->host_data);
341 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
342 irq_set_noprobe(irq);
343
344 return 0;
345}
346
347static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
348 .map = mv88e6xxx_g1_irq_domain_map,
349 .xlate = irq_domain_xlate_twocell,
350};
351
352static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
353{
354 int irq, virq;
3460a577
AL		 355 u16 mask;
356
d77f4321 357 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3d5fdba1 358 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 359 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577
AL		 360
361 free_irq(chip->irq, chip);
dc30c35b 362
5edef2f2 363 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 364 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 365 irq_dispose_mapping(virq);
366 }
367
a3db3d3a 368 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 369}
370
371static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
372{
3dd0ef05
AL		 373 int err, irq, virq;
374 u16 reg, mask;
dc30c35b
AL		 375
376 chip->g1_irq.nirqs = chip->info->g1_irqs;
377 chip->g1_irq.domain = irq_domain_add_simple(
378 NULL, chip->g1_irq.nirqs, 0,
379 &mv88e6xxx_g1_irq_domain_ops, chip);
380 if (!chip->g1_irq.domain)
381 return -ENOMEM;
382
383 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
384 irq_create_mapping(chip->g1_irq.domain, irq);
385
386 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
387 chip->g1_irq.masked = ~0;
388
d77f4321 389 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 390 if (err)
3dd0ef05 391 goto out_mapping;
dc30c35b 392
3dd0ef05 393 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 394
d77f4321 395 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 396 if (err)
3dd0ef05 397 goto out_disable;
dc30c35b
AL		 398
399 /* Reading the interrupt status clears (most of) them */
82466921 400 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 401 if (err)
3dd0ef05 402 goto out_disable;
dc30c35b 403
812be1a6 404 mutex_unlock(&chip->reg_lock);
dc30c35b
AL		 405 err = request_threaded_irq(chip->irq, NULL,
406 mv88e6xxx_g1_irq_thread_fn,
407 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
408 dev_name(chip->dev), chip);
812be1a6 409 mutex_lock(&chip->reg_lock);
dc30c35b 410 if (err)
3dd0ef05 411 goto out_disable;
dc30c35b
AL		 412
413 return 0;
414
3dd0ef05 415out_disable:
3d5fdba1 416 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 417 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 418
419out_mapping:
420 for (irq = 0; irq < 16; irq++) {
421 virq = irq_find_mapping(chip->g1_irq.domain, irq);
422 irq_dispose_mapping(virq);
423 }
424
425 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 426
427 return err;
428}
429
ec561276 430int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 431{
6441e669 432 int i;
2d79af6e 433
6441e669 434 for (i = 0; i < 16; i++) {
2d79af6e
VD		 435 u16 val;
436 int err;
437
438 err = mv88e6xxx_read(chip, addr, reg, &val);
439 if (err)
440 return err;
441
442 if (!(val & mask))
443 return 0;
444
445 usleep_range(1000, 2000);
446 }
447
30853553 448 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 449 return -ETIMEDOUT;
450}
451
f22ab641 452/* Indirect write to single pointer-data register with an Update bit */
ec561276 453int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 454{
455 u16 val;
0f02b4f7 456 int err;
f22ab641
VD		 457
458 /* Wait until the previous operation is completed */
0f02b4f7
AL		 459 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
460 if (err)
461 return err;
f22ab641
VD		 462
463 /* Set the Update bit to trigger a write operation */
464 val = BIT(15) | update;
465
466 return mv88e6xxx_write(chip, addr, reg, val);
467}
468
d78343d2
VD		 469static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
470 int link, int speed, int duplex,
471 phy_interface_t mode)
472{
473 int err;
474
475 if (!chip->info->ops->port_set_link)
476 return 0;
477
478 /* Port's MAC control must not be changed unless the link is down */
479 err = chip->info->ops->port_set_link(chip, port, 0);
480 if (err)
481 return err;
482
483 if (chip->info->ops->port_set_speed) {
484 err = chip->info->ops->port_set_speed(chip, port, speed);
485 if (err && err != -EOPNOTSUPP)
486 goto restore_link;
487 }
488
489 if (chip->info->ops->port_set_duplex) {
490 err = chip->info->ops->port_set_duplex(chip, port, duplex);
491 if (err && err != -EOPNOTSUPP)
492 goto restore_link;
493 }
494
495 if (chip->info->ops->port_set_rgmii_delay) {
496 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
497 if (err && err != -EOPNOTSUPP)
498 goto restore_link;
499 }
500
f39908d3
AL		 501 if (chip->info->ops->port_set_cmode) {
502 err = chip->info->ops->port_set_cmode(chip, port, mode);
503 if (err && err != -EOPNOTSUPP)
504 goto restore_link;
505 }
506
d78343d2
VD		 507 err = 0;
508restore_link:
509 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 510 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 511
512 return err;
513}
514
dea87024
AL		 515/* We expect the switch to perform auto negotiation if there is a real
516 * phy. However, in the case of a fixed link phy, we force the port
517 * settings from the fixed link settings.
518 */
f81ec90f
VD		 519static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
520 struct phy_device *phydev)
dea87024 521{
04bed143 522 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 523 int err;
dea87024
AL		 524
525 if (!phy_is_pseudo_fixed_link(phydev))
526 return;
527
fad09c73 528 mutex_lock(&chip->reg_lock);
d78343d2
VD		 529 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
530 phydev->duplex, phydev->interface);
fad09c73 531 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 532
533 if (err && err != -EOPNOTSUPP)
774439e5 534 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
dea87024
AL		 535}
536
a605a0fe 537static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 538{
a605a0fe
AL		 539 if (!chip->info->ops->stats_snapshot)
540 return -EOPNOTSUPP;
91da11f8 541
a605a0fe 542 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 543}
544
e413e7e1 545static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 546 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
547 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
548 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
549 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
550 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
551 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
552 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
553 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
554 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
555 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
556 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
557 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
558 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
559 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
560 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
561 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
562 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
563 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
564 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
565 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
566 { "single", 4, 0x14, STATS_TYPE_BANK0, },
567 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
568 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
569 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
570 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
571 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
572 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
573 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
574 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
575 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
576 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
577 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
578 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
579 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
580 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
581 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
582 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
583 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
584 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
585 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
586 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
587 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
588 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
589 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
590 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
591 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
592 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
593 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
594 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
595 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
596 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
597 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
598 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
599 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
600 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
601 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
602 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
603 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
604 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 605};
606
fad09c73 607static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 608 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 609 int port, u16 bank1_select,
610 u16 histogram)
80c4627b 611{
80c4627b
AL		 612 u32 low;
613 u32 high = 0;
dfafe449 614 u16 reg = 0;
0e7b9925 615 int err;
80c4627b
AL		 616 u64 value;
617
f5e2ed02 618 switch (s->type) {
dfafe449 619 case STATS_TYPE_PORT:
0e7b9925
AL		 620 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
621 if (err)
80c4627b
AL		 622 return UINT64_MAX;
623
0e7b9925 624 low = reg;
80c4627b 625 if (s->sizeof_stat == 4) {
0e7b9925
AL		 626 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
627 if (err)
80c4627b 628 return UINT64_MAX;
8f30c5d8 629 low |= ((u32)reg) << 16;
80c4627b 630 }
f5e2ed02 631 break;
dfafe449 632 case STATS_TYPE_BANK1:
e0d8b615 633 reg = bank1_select;
dfafe449
AL		 634 /* fall through */
635 case STATS_TYPE_BANK0:
e0d8b615 636 reg |= s->reg | histogram;
7f9ef3af 637 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 638 if (s->sizeof_stat == 8)
7f9ef3af 639 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 640 break;
641 default:
642 return UINT64_MAX;
80c4627b 643 }
04527c1b 644 value = (((u64)high) << 32) | low;
80c4627b
AL		 645 return value;
646}
647
dfafe449
AL		 648static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
649 uint8_t *data, int types)
91da11f8 650{
f5e2ed02
AL		 651 struct mv88e6xxx_hw_stat *stat;
652 int i, j;
91da11f8 653
f5e2ed02
AL		 654 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
655 stat = &mv88e6xxx_hw_stats[i];
dfafe449 656 if (stat->type & types) {
f5e2ed02
AL		 657 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
658 ETH_GSTRING_LEN);
659 j++;
660 }
91da11f8 661 }
e413e7e1
AL		 662}
663
dfafe449
AL		 664static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
665 uint8_t *data)
666{
667 mv88e6xxx_stats_get_strings(chip, data,
668 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
669}
670
671static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
672 uint8_t *data)
673{
674 mv88e6xxx_stats_get_strings(chip, data,
675 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
676}
677
678static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
679 uint8_t *data)
e413e7e1 680{
04bed143 681 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 682
683 if (chip->info->ops->stats_get_strings)
684 chip->info->ops->stats_get_strings(chip, data);
685}
686
687static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
688 int types)
689{
f5e2ed02
AL		 690 struct mv88e6xxx_hw_stat *stat;
691 int i, j;
692
693 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
694 stat = &mv88e6xxx_hw_stats[i];
dfafe449 695 if (stat->type & types)
f5e2ed02
AL		 696 j++;
697 }
698 return j;
e413e7e1
AL		 699}
700
dfafe449
AL		 701static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
702{
703 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
704 STATS_TYPE_PORT);
705}
706
707static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
708{
709 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
710 STATS_TYPE_BANK1);
711}
712
713static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
714{
715 struct mv88e6xxx_chip *chip = ds->priv;
716
717 if (chip->info->ops->stats_get_sset_count)
718 return chip->info->ops->stats_get_sset_count(chip);
719
720 return 0;
721}
722
052f947f 723static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 724 uint64_t *data, int types,
725 u16 bank1_select, u16 histogram)
052f947f
AL		 726{
727 struct mv88e6xxx_hw_stat *stat;
728 int i, j;
729
730 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
731 stat = &mv88e6xxx_hw_stats[i];
732 if (stat->type & types) {
e0d8b615
AL		 733 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
734 bank1_select,
735 histogram);
052f947f
AL		 736 j++;
737 }
738 }
739}
740
741static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
742 uint64_t *data)
743{
744 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 745 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 746 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 747}
748
749static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
750 uint64_t *data)
751{
752 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 753 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 754 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
755 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 756}
757
758static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
759 uint64_t *data)
760{
761 return mv88e6xxx_stats_get_stats(chip, port, data,
762 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 763 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
764 0);
052f947f
AL		 765}
766
767static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
768 uint64_t *data)
769{
770 if (chip->info->ops->stats_get_stats)
771 chip->info->ops->stats_get_stats(chip, port, data);
772}
773
f81ec90f
VD		 774static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
775 uint64_t *data)
e413e7e1 776{
04bed143 777 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 778 int ret;
f5e2ed02 779
fad09c73 780 mutex_lock(&chip->reg_lock);
f5e2ed02 781
a605a0fe 782 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 783 if (ret < 0) {
fad09c73 784 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 785 return;
786 }
052f947f
AL		 787
788 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 789
fad09c73 790 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 791}
792
de227387
AL		 793static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
794{
795 if (chip->info->ops->stats_set_histogram)
796 return chip->info->ops->stats_set_histogram(chip);
797
798 return 0;
799}
800
f81ec90f 801static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 802{
803 return 32 * sizeof(u16);
804}
805
f81ec90f
VD		 806static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
807 struct ethtool_regs *regs, void *_p)
a1ab91f3 808{
04bed143 809 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 810 int err;
811 u16 reg;
a1ab91f3
GR		 812 u16 *p = _p;
813 int i;
814
815 regs->version = 0;
816
817 memset(p, 0xff, 32 * sizeof(u16));
818
fad09c73 819 mutex_lock(&chip->reg_lock);
23062513 820
a1ab91f3 821 for (i = 0; i < 32; i++) {
a1ab91f3 822
0e7b9925
AL		 823 err = mv88e6xxx_port_read(chip, port, i, &reg);
824 if (!err)
825 p[i] = reg;
a1ab91f3 826 }
23062513 827
fad09c73 828 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 829}
830
08f50061
VD		 831static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
832 struct ethtool_eee *e)
68b8f60c 833{
5480db69
VD		 834 /* Nothing to do on the port's MAC */
835 return 0;
11b3b45d
GR		 836}
837
08f50061
VD		 838static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
839 struct ethtool_eee *e)
11b3b45d 840{
5480db69
VD		 841 /* Nothing to do on the port's MAC */
842 return 0;
11b3b45d
GR		 843}
844
e5887a2a 845static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 846{
e5887a2a
VD		 847 struct dsa_switch *ds = NULL;
848 struct net_device *br;
849 u16 pvlan;
b7666efe
VD		 850 int i;
851
e5887a2a
VD		 852 if (dev < DSA_MAX_SWITCHES)
853 ds = chip->ds->dst->ds[dev];
854
855 /* Prevent frames from unknown switch or port */
856 if (!ds || port >= ds->num_ports)
857 return 0;
858
859 /* Frames from DSA links and CPU ports can egress any local port */
860 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
861 return mv88e6xxx_port_mask(chip);
862
863 br = ds->ports[port].bridge_dev;
864 pvlan = 0;
865
866 /* Frames from user ports can egress any local DSA links and CPU ports,
867 * as well as any local member of their bridge group.
868 */
869 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
870 if (dsa_is_cpu_port(chip->ds, i) ||
871 dsa_is_dsa_port(chip->ds, i) ||
c8652c83 872 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
e5887a2a
VD		 873 pvlan |= BIT(i);
874
875 return pvlan;
876}
877
240ea3ef 878static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 879{
880 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 881
882 /* prevent frames from going back out of the port they came in on */
883 output_ports &= ~BIT(port);
facd95b2 884
5a7921f4 885 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 886}
887
f81ec90f
VD		 888static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
889 u8 state)
facd95b2 890{
04bed143 891 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 892 int err;
facd95b2 893
fad09c73 894 mutex_lock(&chip->reg_lock);
f894c29c 895 err = mv88e6xxx_port_set_state(chip, port, state);
fad09c73 896 mutex_unlock(&chip->reg_lock);
553eb544
VD		 897
898 if (err)
774439e5 899 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 900}
901
9e907d73
VD		 902static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
903{
904 if (chip->info->ops->pot_clear)
905 return chip->info->ops->pot_clear(chip);
906
907 return 0;
908}
909
51c901a7
VD		 910static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
911{
912 if (chip->info->ops->mgmt_rsvd2cpu)
913 return chip->info->ops->mgmt_rsvd2cpu(chip);
914
915 return 0;
916}
917
a2ac29d2
VD		 918static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
919{
c3a7d4ad
VD		 920 int err;
921
daefc943
VD		 922 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
923 if (err)
924 return err;
925
c3a7d4ad
VD		 926 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
927 if (err)
928 return err;
929
a2ac29d2
VD		 930 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
931}
932
cd8da8bb
VD		 933static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
934{
935 int port;
936 int err;
937
938 if (!chip->info->ops->irl_init_all)
939 return 0;
940
941 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
942 /* Disable ingress rate limiting by resetting all per port
943 * ingress rate limit resources to their initial state.
944 */
945 err = chip->info->ops->irl_init_all(chip, port);
946 if (err)
947 return err;
948 }
949
950 return 0;
951}
952
04a69a17
VD		 953static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
954{
955 if (chip->info->ops->set_switch_mac) {
956 u8 addr[ETH_ALEN];
957
958 eth_random_addr(addr);
959
960 return chip->info->ops->set_switch_mac(chip, addr);
961 }
962
963 return 0;
964}
965
17a1594e
VD		 966static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
967{
968 u16 pvlan = 0;
969
970 if (!mv88e6xxx_has_pvt(chip))
971 return -EOPNOTSUPP;
972
973 /* Skip the local source device, which uses in-chip port VLAN */
974 if (dev != chip->ds->index)
aec5ac88 975 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 976
977 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
978}
979
81228996
VD		 980static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
981{
17a1594e
VD		 982 int dev, port;
983 int err;
984
81228996
VD		 985 if (!mv88e6xxx_has_pvt(chip))
986 return 0;
987
988 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
989 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
990 */
17a1594e
VD		 991 err = mv88e6xxx_g2_misc_4_bit_port(chip);
992 if (err)
993 return err;
994
995 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
996 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
997 err = mv88e6xxx_pvt_map(chip, dev, port);
998 if (err)
999 return err;
1000 }
1001 }
1002
1003 return 0;
81228996
VD		 1004}
1005
749efcb8
VD		 1006static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1007{
1008 struct mv88e6xxx_chip *chip = ds->priv;
1009 int err;
1010
1011 mutex_lock(&chip->reg_lock);
e606ca36 1012 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1013 mutex_unlock(&chip->reg_lock);
1014
1015 if (err)
774439e5 1016 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 1017}
1018
b486d7c9
VD		 1019static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1020{
1021 if (!chip->info->max_vid)
1022 return 0;
1023
1024 return mv88e6xxx_g1_vtu_flush(chip);
1025}
1026
f1394b78
VD		 1027static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1028 struct mv88e6xxx_vtu_entry *entry)
1029{
1030 if (!chip->info->ops->vtu_getnext)
1031 return -EOPNOTSUPP;
1032
1033 return chip->info->ops->vtu_getnext(chip, entry);
1034}
1035
0ad5daf6
VD		 1036static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1037 struct mv88e6xxx_vtu_entry *entry)
1038{
1039 if (!chip->info->ops->vtu_loadpurge)
1040 return -EOPNOTSUPP;
1041
1042 return chip->info->ops->vtu_loadpurge(chip, entry);
1043}
1044
d7f435f9 1045static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1046{
1047 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
3afb4bde
VD		 1048 struct mv88e6xxx_vtu_entry vlan = {
1049 .vid = chip->info->max_vid,
1050 };
2db9ce1f 1051 int i, err;
3285f9e8
VD		 1052
1053 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1054
2db9ce1f 1055 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1056 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1057 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1058 if (err)
1059 return err;
1060
1061 set_bit(*fid, fid_bitmap);
1062 }
1063
3285f9e8 1064 /* Set every FID bit used by the VLAN entries */
3285f9e8 1065 do {
f1394b78 1066 err = mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1067 if (err)
1068 return err;
1069
1070 if (!vlan.valid)
1071 break;
1072
1073 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1074 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1075
1076 /* The reset value 0x000 is used to indicate that multiple address
1077 * databases are not needed. Return the next positive available.
1078 */
1079 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1080 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1081 return -ENOSPC;
1082
1083 /* Clear the database */
daefc943 1084 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1085}
1086
567aa59a
VD		 1087static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1088 struct mv88e6xxx_vtu_entry *entry, bool new)
2fb5ef09
VD		 1089{
1090 int err;
1091
1092 if (!vid)
af7f46b6 1093 return -EOPNOTSUPP;
2fb5ef09 1094
3afb4bde
VD		 1095 entry->vid = vid - 1;
1096 entry->valid = false;
2fb5ef09 1097
f1394b78 1098 err = mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1099 if (err)
1100 return err;
1101
567aa59a
VD		 1102 if (entry->vid == vid && entry->valid)
1103 return 0;
2fb5ef09 1104
567aa59a
VD		 1105 if (new) {
1106 int i;
1107
1108 /* Initialize a fresh VLAN entry */
1109 memset(entry, 0, sizeof(*entry));
1110 entry->valid = true;
1111 entry->vid = vid;
1112
553a768d 1113 /* Exclude all ports */
567aa59a 1114 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
553a768d 1115 entry->member[i] =
7ec60d6e 1116 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
567aa59a
VD		 1117
1118 return mv88e6xxx_atu_new(chip, &entry->fid);
2fb5ef09
VD		 1119 }
1120
567aa59a
VD		 1121 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1122 return -EOPNOTSUPP;
2fb5ef09
VD		 1123}
1124
da9c359e
VD		 1125static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1126 u16 vid_begin, u16 vid_end)
1127{
04bed143 1128 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1129 struct mv88e6xxx_vtu_entry vlan = {
1130 .vid = vid_begin - 1,
1131 };
da9c359e
VD		 1132 int i, err;
1133
db06ae41
AL		 1134 /* DSA and CPU ports have to be members of multiple vlans */
1135 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1136 return 0;
1137
da9c359e
VD		 1138 if (!vid_begin)
1139 return -EOPNOTSUPP;
1140
fad09c73 1141 mutex_lock(&chip->reg_lock);
da9c359e 1142
da9c359e 1143 do {
f1394b78 1144 err = mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1145 if (err)
1146 goto unlock;
1147
1148 if (!vlan.valid)
1149 break;
1150
1151 if (vlan.vid > vid_end)
1152 break;
1153
370b4ffb 1154 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1155 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1156 continue;
1157
cd886469 1158 if (!ds->ports[i].slave)
66e2809d
AL		 1159 continue;
1160
bd00e053 1161 if (vlan.member[i] ==
7ec60d6e 1162 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
da9c359e
VD		 1163 continue;
1164
c8652c83 1165 if (dsa_to_port(ds, i)->bridge_dev ==
fae8a25e 1166 ds->ports[port].bridge_dev)
da9c359e
VD		 1167 break; /* same bridge, check next VLAN */
1168
c8652c83 1169 if (!dsa_to_port(ds, i)->bridge_dev)
66e2809d
AL		 1170 continue;
1171
743fcc28
AL		 1172 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1173 port, vlan.vid, i,
c8652c83 1174 netdev_name(dsa_to_port(ds, i)->bridge_dev));
da9c359e
VD		 1175 err = -EOPNOTSUPP;
1176 goto unlock;
1177 }
1178 } while (vlan.vid < vid_end);
1179
1180unlock:
fad09c73 1181 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1182
1183 return err;
1184}
1185
f81ec90f
VD		 1186static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1187 bool vlan_filtering)
214cdb99 1188{
04bed143 1189 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1190 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1191 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1192 int err;
214cdb99 1193
3cf3c846 1194 if (!chip->info->max_vid)
54d77b5b
VD		 1195 return -EOPNOTSUPP;
1196
fad09c73 1197 mutex_lock(&chip->reg_lock);
385a0995 1198 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1199 mutex_unlock(&chip->reg_lock);
214cdb99 1200
0e7b9925 1201 return err;
214cdb99
VD		 1202}
1203
57d32310
VD		 1204static int
1205mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1206 const struct switchdev_obj_port_vlan *vlan,
1207 struct switchdev_trans *trans)
76e398a6 1208{
04bed143 1209 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1210 int err;
1211
3cf3c846 1212 if (!chip->info->max_vid)
54d77b5b
VD		 1213 return -EOPNOTSUPP;
1214
da9c359e
VD		 1215 /* If the requested port doesn't belong to the same bridge as the VLAN
1216 * members, do not support it (yet) and fallback to software VLAN.
1217 */
1218 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1219 vlan->vid_end);
1220 if (err)
1221 return err;
1222
76e398a6
VD		 1223 /* We don't need any dynamic resource from the kernel (yet),
1224 * so skip the prepare phase.
1225 */
1226 return 0;
1227}
1228
a4c93ae1
AL		 1229static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1230 const unsigned char *addr, u16 vid,
1231 u8 state)
1232{
1233 struct mv88e6xxx_vtu_entry vlan;
1234 struct mv88e6xxx_atu_entry entry;
1235 int err;
1236
1237 /* Null VLAN ID corresponds to the port private database */
1238 if (vid == 0)
1239 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1240 else
1241 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1242 if (err)
1243 return err;
1244
1245 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1246 ether_addr_copy(entry.mac, addr);
1247 eth_addr_dec(entry.mac);
1248
1249 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1250 if (err)
1251 return err;
1252
1253 /* Initialize a fresh ATU entry if it isn't found */
1254 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1255 !ether_addr_equal(entry.mac, addr)) {
1256 memset(&entry, 0, sizeof(entry));
1257 ether_addr_copy(entry.mac, addr);
1258 }
1259
1260 /* Purge the ATU entry only if no port is using it anymore */
1261 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1262 entry.portvec &= ~BIT(port);
1263 if (!entry.portvec)
1264 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1265 } else {
1266 entry.portvec |= BIT(port);
1267 entry.state = state;
1268 }
1269
1270 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1271}
1272
87fa886e
AL		 1273static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1274 u16 vid)
1275{
1276 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1277 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1278
1279 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1280}
1281
1282static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1283{
1284 int port;
1285 int err;
1286
1287 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1288 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1289 if (err)
1290 return err;
1291 }
1292
1293 return 0;
1294}
1295
fad09c73 1296static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
c91498e1 1297 u16 vid, u8 member)
0d3b33e6 1298{
b4e47c0f 1299 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1300 int err;
1301
567aa59a 1302 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1303 if (err)
76e398a6 1304 return err;
0d3b33e6 1305
c91498e1 1306 vlan.member[port] = member;
0d3b33e6 1307
87fa886e
AL		 1308 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1309 if (err)
1310 return err;
1311
1312 return mv88e6xxx_broadcast_setup(chip, vid);
76e398a6
VD		 1313}
1314
f81ec90f
VD		 1315static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1316 const struct switchdev_obj_port_vlan *vlan,
1317 struct switchdev_trans *trans)
76e398a6 1318{
04bed143 1319 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1320 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1321 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
c91498e1 1322 u8 member;
76e398a6 1323 u16 vid;
76e398a6 1324
3cf3c846 1325 if (!chip->info->max_vid)
54d77b5b
VD		 1326 return;
1327
c91498e1 1328 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 1329 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 1330 else if (untagged)
7ec60d6e 1331 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 1332 else
7ec60d6e 1333 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 1334
fad09c73 1335 mutex_lock(&chip->reg_lock);
76e398a6 1336
4d5770b3 1337 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
c91498e1 1338 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
774439e5
VD		 1339 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1340 vid, untagged ? 'u' : 't');
76e398a6 1341
77064f37 1342 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
774439e5
VD		 1343 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1344 vlan->vid_end);
0d3b33e6 1345
fad09c73 1346 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1347}
1348
fad09c73 1349static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1350 int port, u16 vid)
7dad08d7 1351{
b4e47c0f 1352 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1353 int i, err;
1354
567aa59a 1355 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1356 if (err)
76e398a6 1357 return err;
7dad08d7 1358
2fb5ef09 1359 /* Tell switchdev if this VLAN is handled in software */
7ec60d6e 1360 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1361 return -EOPNOTSUPP;
7dad08d7 1362
7ec60d6e 1363 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1364
1365 /* keep the VLAN unless all ports are excluded */
f02bdffc 1366 vlan.valid = false;
370b4ffb 1367 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 1368 if (vlan.member[i] !=
1369 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1370 vlan.valid = true;
7dad08d7
VD		 1371 break;
1372 }
1373 }
1374
0ad5daf6 1375 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1376 if (err)
1377 return err;
1378
e606ca36 1379 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1380}
1381
f81ec90f
VD		 1382static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1383 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1384{
04bed143 1385 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1386 u16 pvid, vid;
1387 int err = 0;
1388
3cf3c846 1389 if (!chip->info->max_vid)
54d77b5b
VD		 1390 return -EOPNOTSUPP;
1391
fad09c73 1392 mutex_lock(&chip->reg_lock);
76e398a6 1393
77064f37 1394 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1395 if (err)
1396 goto unlock;
1397
76e398a6 1398 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1399 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1400 if (err)
1401 goto unlock;
1402
1403 if (vid == pvid) {
77064f37 1404 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1405 if (err)
1406 goto unlock;
1407 }
1408 }
1409
7dad08d7 1410unlock:
fad09c73 1411 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1412
1413 return err;
1414}
1415
1b6dd556
AS		 1416static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1417 const unsigned char *addr, u16 vid)
87820510 1418{
04bed143 1419 struct mv88e6xxx_chip *chip = ds->priv;
1b6dd556 1420 int err;
87820510 1421
fad09c73 1422 mutex_lock(&chip->reg_lock);
1b6dd556
AS		 1423 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1424 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
fad09c73 1425 mutex_unlock(&chip->reg_lock);
1b6dd556
AS		 1426
1427 return err;
87820510
VD		 1428}
1429
f81ec90f 1430static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1431 const unsigned char *addr, u16 vid)
87820510 1432{
04bed143 1433 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1434 int err;
87820510 1435
fad09c73 1436 mutex_lock(&chip->reg_lock);
6c2c1dcb 1437 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
27c0e600 1438 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
fad09c73 1439 mutex_unlock(&chip->reg_lock);
87820510 1440
83dabd1f 1441 return err;
87820510
VD		 1442}
1443
83dabd1f
VD		 1444static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1445 u16 fid, u16 vid, int port,
2bedde1a 1446 dsa_fdb_dump_cb_t *cb, void *data)
74b6ba0d 1447{
dabc1a96 1448 struct mv88e6xxx_atu_entry addr;
2bedde1a 1449 bool is_static;
74b6ba0d
VD		 1450 int err;
1451
27c0e600 1452 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96 1453 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1454
1455 do {
dabc1a96 1456 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1457 if (err)
83dabd1f 1458 return err;
74b6ba0d 1459
27c0e600 1460 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
74b6ba0d
VD		 1461 break;
1462
01bd96c8 1463 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1464 continue;
1465
2bedde1a
AS		 1466 if (!is_unicast_ether_addr(addr.mac))
1467 continue;
83dabd1f 1468
2bedde1a
AS		 1469 is_static = (addr.state ==
1470 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1471 err = cb(addr.mac, vid, is_static, data);
83dabd1f
VD		 1472 if (err)
1473 return err;
74b6ba0d
VD		 1474 } while (!is_broadcast_ether_addr(addr.mac));
1475
1476 return err;
1477}
1478
83dabd1f 1479static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2bedde1a 1480 dsa_fdb_dump_cb_t *cb, void *data)
f33475bd 1481{
b4e47c0f 1482 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 1483 .vid = chip->info->max_vid,
f33475bd 1484 };
2db9ce1f 1485 u16 fid;
f33475bd
VD		 1486 int err;
1487
2db9ce1f 1488 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 1489 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 1490 if (err)
83dabd1f 1491 return err;
2db9ce1f 1492
2bedde1a 1493 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2db9ce1f 1494 if (err)
83dabd1f 1495 return err;
2db9ce1f 1496
74b6ba0d 1497 /* Dump VLANs' Filtering Information Databases */
f33475bd 1498 do {
f1394b78 1499 err = mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 1500 if (err)
83dabd1f 1501 return err;
f33475bd
VD		 1502
1503 if (!vlan.valid)
1504 break;
1505
83dabd1f 1506 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2bedde1a 1507 cb, data);
f33475bd 1508 if (err)
83dabd1f 1509 return err;
3cf3c846 1510 } while (vlan.vid < chip->info->max_vid);
f33475bd 1511
83dabd1f
VD		 1512 return err;
1513}
1514
1515static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1516 dsa_fdb_dump_cb_t *cb, void *data)
83dabd1f 1517{
04bed143 1518 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 1519 int err;
1520
1521 mutex_lock(&chip->reg_lock);
2bedde1a 1522 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
fad09c73 1523 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 1524
1525 return err;
1526}
1527
240ea3ef
VD		 1528static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1529 struct net_device *br)
e79a8bcb 1530{
e96a6e02 1531 struct dsa_switch *ds;
240ea3ef 1532 int port;
e96a6e02 1533 int dev;
240ea3ef 1534 int err;
466dfa07 1535
240ea3ef
VD		 1536 /* Remap the Port VLAN of each local bridge group member */
1537 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1538 if (chip->ds->ports[port].bridge_dev == br) {
1539 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 1540 if (err)
240ea3ef 1541 return err;
b7666efe
VD		 1542 }
1543 }
1544
e96a6e02
VD		 1545 if (!mv88e6xxx_has_pvt(chip))
1546 return 0;
1547
1548 /* Remap the Port VLAN of each cross-chip bridge group member */
1549 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1550 ds = chip->ds->dst->ds[dev];
1551 if (!ds)
1552 break;
1553
1554 for (port = 0; port < ds->num_ports; ++port) {
1555 if (ds->ports[port].bridge_dev == br) {
1556 err = mv88e6xxx_pvt_map(chip, dev, port);
1557 if (err)
1558 return err;
1559 }
1560 }
1561 }
1562
240ea3ef
VD		 1563 return 0;
1564}
1565
1566static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1567 struct net_device *br)
1568{
1569 struct mv88e6xxx_chip *chip = ds->priv;
1570 int err;
1571
1572 mutex_lock(&chip->reg_lock);
1573 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 1574 mutex_unlock(&chip->reg_lock);
a6692754 1575
466dfa07 1576 return err;
e79a8bcb
VD		 1577}
1578
f123f2fb
VD		 1579static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1580 struct net_device *br)
66d9cd0f 1581{
04bed143 1582 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 1583
fad09c73 1584 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 1585 if (mv88e6xxx_bridge_map(chip, br) ||
1586 mv88e6xxx_port_vlan_map(chip, port))
1587 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 1588 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 1589}
1590
aec5ac88
VD		 1591static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1592 int port, struct net_device *br)
1593{
1594 struct mv88e6xxx_chip *chip = ds->priv;
1595 int err;
1596
1597 if (!mv88e6xxx_has_pvt(chip))
1598 return 0;
1599
1600 mutex_lock(&chip->reg_lock);
1601 err = mv88e6xxx_pvt_map(chip, dev, port);
1602 mutex_unlock(&chip->reg_lock);
1603
1604 return err;
1605}
1606
1607static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1608 int port, struct net_device *br)
1609{
1610 struct mv88e6xxx_chip *chip = ds->priv;
1611
1612 if (!mv88e6xxx_has_pvt(chip))
1613 return;
1614
1615 mutex_lock(&chip->reg_lock);
1616 if (mv88e6xxx_pvt_map(chip, dev, port))
1617 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1618 mutex_unlock(&chip->reg_lock);
1619}
1620
17e708ba
VD		 1621static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1622{
1623 if (chip->info->ops->reset)
1624 return chip->info->ops->reset(chip);
1625
1626 return 0;
1627}
1628
309eca6d
VD		 1629static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1630{
1631 struct gpio_desc *gpiod = chip->reset;
1632
1633 /* If there is a GPIO connected to the reset pin, toggle it */
1634 if (gpiod) {
1635 gpiod_set_value_cansleep(gpiod, 1);
1636 usleep_range(10000, 20000);
1637 gpiod_set_value_cansleep(gpiod, 0);
1638 usleep_range(10000, 20000);
1639 }
1640}
1641
4ac4b5a6 1642static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 1643{
4ac4b5a6 1644 int i, err;
552238b5 1645
4ac4b5a6 1646 /* Set all ports to the Disabled state */
370b4ffb 1647 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 1648 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 1649 if (err)
1650 return err;
552238b5
VD		 1651 }
1652
4ac4b5a6
VD		 1653 /* Wait for transmit queues to drain,
1654 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1655 */
552238b5
VD		 1656 usleep_range(2000, 4000);
1657
4ac4b5a6
VD		 1658 return 0;
1659}
1660
1661static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1662{
4ac4b5a6
VD		 1663 int err;
1664
1665 err = mv88e6xxx_disable_ports(chip);
1666 if (err)
1667 return err;
1668
309eca6d 1669 mv88e6xxx_hardware_reset(chip);
552238b5 1670
17e708ba 1671 return mv88e6xxx_software_reset(chip);
552238b5
VD		 1672}
1673
4314557c 1674static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 1675 enum mv88e6xxx_frame_mode frame,
1676 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 1677{
1678 int err;
1679
4314557c
VD		 1680 if (!chip->info->ops->port_set_frame_mode)
1681 return -EOPNOTSUPP;
1682
1683 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 1684 if (err)
1685 return err;
1686
4314557c
VD		 1687 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1688 if (err)
1689 return err;
1690
1691 if (chip->info->ops->port_set_ether_type)
1692 return chip->info->ops->port_set_ether_type(chip, port, etype);
1693
1694 return 0;
56995cbc
AL		 1695}
1696
4314557c 1697static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 1698{
4314557c 1699 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 1700 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1701 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1702}
56995cbc 1703
4314557c
VD		 1704static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1705{
1706 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 1707 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1708 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1709}
56995cbc 1710
4314557c
VD		 1711static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1712{
1713 return mv88e6xxx_set_port_mode(chip, port,
1714 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 1715 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1716 ETH_P_EDSA);
4314557c 1717}
56995cbc 1718
4314557c
VD		 1719static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1720{
1721 if (dsa_is_dsa_port(chip->ds, port))
1722 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1723
2b3e9891 1724 if (dsa_is_user_port(chip->ds, port))
4314557c 1725 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 1726
4314557c
VD		 1727 /* Setup CPU port mode depending on its supported tag format */
1728 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1729 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1730
4314557c
VD		 1731 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1732 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 1733
4314557c 1734 return -EINVAL;
56995cbc
AL		 1735}
1736
601aeed3 1737static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 1738{
601aeed3 1739 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 1740
601aeed3 1741 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 1742}
56995cbc 1743
601aeed3 1744static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 1745{
601aeed3 1746 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 1747
601aeed3
VD		 1748 /* Upstream ports flood frames with unknown unicast or multicast DA */
1749 if (chip->info->ops->port_set_egress_floods)
1750 return chip->info->ops->port_set_egress_floods(chip, port,
1751 flood, flood);
ea698f4f 1752
601aeed3 1753 return 0;
ea698f4f
VD		 1754}
1755
6d91782f
AL		 1756static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1757 bool on)
1758{
523a8904
VD		 1759 if (chip->info->ops->serdes_power)
1760 return chip->info->ops->serdes_power(chip, port, on);
04aca993 1761
523a8904 1762 return 0;
6d91782f
AL		 1763}
1764
fad09c73 1765static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 1766{
fad09c73 1767 struct dsa_switch *ds = chip->ds;
0e7b9925 1768 int err;
54d792f2 1769 u16 reg;
d827e88a 1770
d78343d2
VD		 1771 /* MAC Forcing register: don't force link, speed, duplex or flow control
1772 * state to any particular values on physical ports, but force the CPU
1773 * port and all DSA ports to their maximum bandwidth and full duplex.
1774 */
1775 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1776 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1777 SPEED_MAX, DUPLEX_FULL,
1778 PHY_INTERFACE_MODE_NA);
1779 else
1780 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1781 SPEED_UNFORCED, DUPLEX_UNFORCED,
1782 PHY_INTERFACE_MODE_NA);
1783 if (err)
1784 return err;
54d792f2
AL		 1785
1786 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1787 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1788 * tunneling, determine priority by looking at 802.1p and IP
1789 * priority fields (IP prio has precedence), and set STP state
1790 * to Forwarding.
1791 *
1792 * If this is the CPU link, use DSA or EDSA tagging depending
1793 * on which tagging mode was configured.
1794 *
1795 * If this is a link to another switch, use DSA tagging mode.
1796 *
1797 * If this is the upstream port for this switch, enable
1798 * forwarding of unknown unicasts and multicasts.
1799 */
a89b433b
VD		 1800 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1801 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1802 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1803 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 1804 if (err)
1805 return err;
6083ce71 1806
601aeed3 1807 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 1808 if (err)
1809 return err;
54d792f2 1810
601aeed3 1811 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 1812 if (err)
1813 return err;
1814
04aca993
AL		 1815 /* Enable the SERDES interface for DSA and CPU ports. Normal
1816 * ports SERDES are enabled when the port is enabled, thus
1817 * saving a bit of power.
13a7ebb3 1818 */
04aca993
AL		 1819 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1820 err = mv88e6xxx_serdes_power(chip, port, true);
1821 if (err)
1822 return err;
1823 }
13a7ebb3 1824
8efdda4a 1825 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 1826 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 1827 * untagged frames on this port, do a destination address lookup on all
1828 * received packets as usual, disable ARP mirroring and don't send a
1829 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 1830 */
a23b2961
AL		 1831 err = mv88e6xxx_port_set_map_da(chip, port);
1832 if (err)
1833 return err;
8efdda4a 1834
a23b2961
AL		 1835 reg = 0;
1836 if (chip->info->ops->port_set_upstream_port) {
1837 err = chip->info->ops->port_set_upstream_port(
1838 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 1839 if (err)
1840 return err;
54d792f2
AL		 1841 }
1842
a23b2961 1843 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 1844 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 1845 if (err)
1846 return err;
1847
cd782656
VD		 1848 if (chip->info->ops->port_set_jumbo_size) {
1849 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 1850 if (err)
1851 return err;
1852 }
1853
54d792f2
AL		 1854 /* Port Association Vector: when learning source addresses
1855 * of packets, add the address to the address database using
1856 * a port bitmap that has only the bit for this port set and
1857 * the other bits clear.
1858 */
4c7ea3c0 1859 reg = 1 << port;
996ecb82
VD		 1860 /* Disable learning for CPU port */
1861 if (dsa_is_cpu_port(ds, port))
65fa4027 1862 reg = 0;
4c7ea3c0 1863
2a4614e4
VD		 1864 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1865 reg);
0e7b9925
AL		 1866 if (err)
1867 return err;
54d792f2
AL		 1868
1869 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 1870 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1871 0x0000);
0e7b9925
AL		 1872 if (err)
1873 return err;
54d792f2 1874
0898432c
VD		 1875 if (chip->info->ops->port_pause_limit) {
1876 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 1877 if (err)
1878 return err;
b35d322a 1879 }
54d792f2 1880
c8c94891
VD		 1881 if (chip->info->ops->port_disable_learn_limit) {
1882 err = chip->info->ops->port_disable_learn_limit(chip, port);
1883 if (err)
1884 return err;
1885 }
1886
9dbfb4e1
VD		 1887 if (chip->info->ops->port_disable_pri_override) {
1888 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 1889 if (err)
1890 return err;
ef0a7318 1891 }
2bbb33be 1892
ef0a7318
AL		 1893 if (chip->info->ops->port_tag_remap) {
1894 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 1895 if (err)
1896 return err;
54d792f2
AL		 1897 }
1898
ef70b111
AL		 1899 if (chip->info->ops->port_egress_rate_limiting) {
1900 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 1901 if (err)
1902 return err;
54d792f2
AL		 1903 }
1904
ea698f4f 1905 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 1906 if (err)
1907 return err;
d827e88a 1908
207afda1 1909 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 1910 * database, and allow bidirectional communication between the
1911 * CPU and DSA port(s), and the other ports.
d827e88a 1912 */
b4e48c50 1913 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 1914 if (err)
1915 return err;
2db9ce1f 1916
240ea3ef 1917 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 1918 if (err)
1919 return err;
d827e88a
GR		 1920
1921 /* Default VLAN ID and priority: don't set a default VLAN
1922 * ID, and set the default packet priority to zero.
1923 */
b7929fb3 1924 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 1925}
1926
04aca993
AL		 1927static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1928 struct phy_device *phydev)
1929{
1930 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 1931 int err;
04aca993
AL		 1932
1933 mutex_lock(&chip->reg_lock);
523a8904 1934 err = mv88e6xxx_serdes_power(chip, port, true);
04aca993
AL		 1935 mutex_unlock(&chip->reg_lock);
1936
1937 return err;
1938}
1939
1940static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1941 struct phy_device *phydev)
1942{
1943 struct mv88e6xxx_chip *chip = ds->priv;
1944
1945 mutex_lock(&chip->reg_lock);
523a8904
VD		 1946 if (mv88e6xxx_serdes_power(chip, port, false))
1947 dev_err(chip->dev, "failed to power off SERDES\n");
04aca993
AL		 1948 mutex_unlock(&chip->reg_lock);
1949}
1950
2cfcd964
VD		 1951static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
1952 unsigned int ageing_time)
1953{
04bed143 1954 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 1955 int err;
1956
1957 mutex_lock(&chip->reg_lock);
720c6343 1958 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 1959 mutex_unlock(&chip->reg_lock);
1960
1961 return err;
1962}
1963
9729934c 1964static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 1965{
fad09c73 1966 struct dsa_switch *ds = chip->ds;
b0745e87 1967 u32 upstream_port = dsa_upstream_port(ds);
552238b5 1968 int err;
54d792f2 1969
fa8d1179
VD		 1970 if (chip->info->ops->set_cpu_port) {
1971 err = chip->info->ops->set_cpu_port(chip, upstream_port);
33641994
AL		 1972 if (err)
1973 return err;
1974 }
1975
fa8d1179
VD		 1976 if (chip->info->ops->set_egress_port) {
1977 err = chip->info->ops->set_egress_port(chip, upstream_port);
33641994
AL		 1978 if (err)
1979 return err;
1980 }
b0745e87 1981
50484ff4 1982 /* Disable remote management, and set the switch's DSA device number. */
d77f4321
VD		 1983 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
1984 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
a935c052 1985 (ds->index & 0x1f));
50484ff4
VD		 1986 if (err)
1987 return err;
1988
54d792f2 1989 /* Configure the IP ToS mapping registers. */
ccba8f3a 1990 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
48ace4ef 1991 if (err)
08a01261 1992 return err;
ccba8f3a 1993 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
48ace4ef 1994 if (err)
08a01261 1995 return err;
ccba8f3a 1996 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
48ace4ef 1997 if (err)
08a01261 1998 return err;
ccba8f3a 1999 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
48ace4ef 2000 if (err)
08a01261 2001 return err;
ccba8f3a 2002 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
48ace4ef 2003 if (err)
08a01261 2004 return err;
ccba8f3a 2005 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
48ace4ef 2006 if (err)
08a01261 2007 return err;
ccba8f3a 2008 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
48ace4ef 2009 if (err)
08a01261 2010 return err;
ccba8f3a 2011 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
48ace4ef 2012 if (err)
08a01261 2013 return err;
54d792f2
AL		 2014
2015 /* Configure the IEEE 802.1p priority mapping register. */
ccba8f3a 2016 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
48ace4ef 2017 if (err)
08a01261 2018 return err;
54d792f2 2019
de227387
AL		 2020 /* Initialize the statistics unit */
2021 err = mv88e6xxx_stats_set_histogram(chip);
2022 if (err)
2023 return err;
2024
40cff8fc 2025 return mv88e6xxx_g1_stats_clear(chip);
9729934c
VD		 2026}
2027
f843abe0
AL		 2028/* The mv88e6390 has some hidden registers used for debug and
2029 * development. The errata also makes use of them.
2030 */
2031static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2032 int reg, u16 val)
2033{
2034 u16 ctrl;
2035 int err;
2036
2037 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2038 PORT_RESERVED_1A, val);
2039 if (err)
2040 return err;
2041
2042 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2043 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2044 reg;
2045
2046 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2047 PORT_RESERVED_1A, ctrl);
2048}
2049
2050static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2051{
2052 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2053 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2054}
2055
2056
2057static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2058 int reg, u16 *val)
2059{
2060 u16 ctrl;
2061 int err;
2062
2063 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2064 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2065 reg;
2066
2067 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2068 PORT_RESERVED_1A, ctrl);
2069 if (err)
2070 return err;
2071
2072 err = mv88e6390_hidden_wait(chip);
2073 if (err)
2074 return err;
2075
2076 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2077 PORT_RESERVED_1A, val);
2078}
2079
2080/* Check if the errata has already been applied. */
2081static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2082{
2083 int port;
2084 int err;
2085 u16 val;
2086
2087 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2088 err = mv88e6390_hidden_read(chip, port, 0, &val);
2089 if (err) {
2090 dev_err(chip->dev,
2091 "Error reading hidden register: %d\n", err);
2092 return false;
2093 }
2094 if (val != 0x01c0)
2095 return false;
2096 }
2097
2098 return true;
2099}
2100
2101/* The 6390 copper ports have an errata which require poking magic
2102 * values into undocumented hidden registers and then performing a
2103 * software reset.
2104 */
2105static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2106{
2107 int port;
2108 int err;
2109
2110 if (mv88e6390_setup_errata_applied(chip))
2111 return 0;
2112
2113 /* Set the ports into blocking mode */
2114 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2115 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2116 if (err)
2117 return err;
2118 }
2119
2120 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2121 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2122 if (err)
2123 return err;
2124 }
2125
2126 return mv88e6xxx_software_reset(chip);
2127}
2128
f81ec90f 2129static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2130{
04bed143 2131 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2132 int err;
a1a6a4d1
VD		 2133 int i;
2134
fad09c73 2135 chip->ds = ds;
a3c53be5 2136 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2137
fad09c73 2138 mutex_lock(&chip->reg_lock);
08a01261 2139
f843abe0
AL		 2140 if (chip->info->ops->setup_errata) {
2141 err = chip->info->ops->setup_errata(chip);
2142 if (err)
2143 goto unlock;
2144 }
2145
9729934c 2146 /* Setup Switch Port Registers */
370b4ffb 2147 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
91dee144
VD		 2148 if (dsa_is_unused_port(ds, i))
2149 continue;
2150
9729934c
VD		 2151 err = mv88e6xxx_setup_port(chip, i);
2152 if (err)
2153 goto unlock;
2154 }
2155
2156 /* Setup Switch Global 1 Registers */
2157 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2158 if (err)
2159 goto unlock;
2160
9729934c 2161 /* Setup Switch Global 2 Registers */
9069c13a 2162 if (chip->info->global2_addr) {
9729934c 2163 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2164 if (err)
2165 goto unlock;
2166 }
08a01261 2167
cd8da8bb
VD		 2168 err = mv88e6xxx_irl_setup(chip);
2169 if (err)
2170 goto unlock;
2171
04a69a17
VD		 2172 err = mv88e6xxx_mac_setup(chip);
2173 if (err)
2174 goto unlock;
2175
1b17aedf
VD		 2176 err = mv88e6xxx_phy_setup(chip);
2177 if (err)
2178 goto unlock;
2179
b486d7c9
VD		 2180 err = mv88e6xxx_vtu_setup(chip);
2181 if (err)
2182 goto unlock;
2183
81228996
VD		 2184 err = mv88e6xxx_pvt_setup(chip);
2185 if (err)
2186 goto unlock;
2187
a2ac29d2
VD		 2188 err = mv88e6xxx_atu_setup(chip);
2189 if (err)
2190 goto unlock;
2191
87fa886e
AL		 2192 err = mv88e6xxx_broadcast_setup(chip, 0);
2193 if (err)
2194 goto unlock;
2195
9e907d73
VD		 2196 err = mv88e6xxx_pot_setup(chip);
2197 if (err)
2198 goto unlock;
2199
51c901a7
VD		 2200 err = mv88e6xxx_rsvd2cpu_setup(chip);
2201 if (err)
2202 goto unlock;
6e55f698 2203
6b17e864 2204unlock:
fad09c73 2205 mutex_unlock(&chip->reg_lock);
db687a56 2206
48ace4ef 2207 return err;
54d792f2
AL		 2208}
2209
e57e5e77 2210static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2211{
0dd12d54
AL		 2212 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2213 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2214 u16 val;
2215 int err;
fd3a0ee4 2216
ee26a228
AL		 2217 if (!chip->info->ops->phy_read)
2218 return -EOPNOTSUPP;
2219
fad09c73 2220 mutex_lock(&chip->reg_lock);
ee26a228 2221 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2222 mutex_unlock(&chip->reg_lock);
e57e5e77 2223
da9f3301
AL		 2224 if (reg == MII_PHYSID2) {
2225 /* Some internal PHYS don't have a model number. Use
2226 * the mv88e6390 family model number instead.
2227 */
2228 if (!(val & 0x3f0))
107fcc10 2229 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
da9f3301
AL		 2230 }
2231
e57e5e77 2232 return err ? err : val;
fd3a0ee4
AL		 2233}
2234
e57e5e77 2235static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2236{
0dd12d54
AL		 2237 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2238 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2239 int err;
fd3a0ee4 2240
ee26a228
AL		 2241 if (!chip->info->ops->phy_write)
2242 return -EOPNOTSUPP;
2243
fad09c73 2244 mutex_lock(&chip->reg_lock);
ee26a228 2245 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2246 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2247
2248 return err;
fd3a0ee4
AL		 2249}
2250
fad09c73 2251static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2252 struct device_node *np,
2253 bool external)
b516d453
AL		 2254{
2255 static int index;
0dd12d54 2256 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2257 struct mii_bus *bus;
2258 int err;
2259
0dd12d54 2260 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2261 if (!bus)
2262 return -ENOMEM;
2263
0dd12d54 2264 mdio_bus = bus->priv;
a3c53be5 2265 mdio_bus->bus = bus;
0dd12d54 2266 mdio_bus->chip = chip;
a3c53be5
AL		 2267 INIT_LIST_HEAD(&mdio_bus->list);
2268 mdio_bus->external = external;
0dd12d54 2269
b516d453
AL		 2270 if (np) {
2271 bus->name = np->full_name;
f7ce9103 2272 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
b516d453
AL		 2273 } else {
2274 bus->name = "mv88e6xxx SMI";
2275 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2276 }
2277
2278 bus->read = mv88e6xxx_mdio_read;
2279 bus->write = mv88e6xxx_mdio_write;
fad09c73 2280 bus->parent = chip->dev;
b516d453 2281
a3c53be5
AL		 2282 if (np)
2283 err = of_mdiobus_register(bus, np);
b516d453
AL		 2284 else
2285 err = mdiobus_register(bus);
2286 if (err) {
fad09c73 2287 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2288 return err;
b516d453 2289 }
a3c53be5
AL		 2290
2291 if (external)
2292 list_add_tail(&mdio_bus->list, &chip->mdios);
2293 else
2294 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2295
2296 return 0;
a3c53be5 2297}
b516d453 2298
a3c53be5
AL		 2299static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2300 { .compatible = "marvell,mv88e6xxx-mdio-external",
2301 .data = (void *)true },
2302 { },
2303};
b516d453 2304
3126aeec
AL		 2305static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2306
2307{
2308 struct mv88e6xxx_mdio_bus *mdio_bus;
2309 struct mii_bus *bus;
2310
2311 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2312 bus = mdio_bus->bus;
2313
2314 mdiobus_unregister(bus);
2315 }
2316}
2317
a3c53be5
AL		 2318static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2319 struct device_node *np)
2320{
2321 const struct of_device_id *match;
2322 struct device_node *child;
2323 int err;
2324
2325 /* Always register one mdio bus for the internal/default mdio
2326 * bus. This maybe represented in the device tree, but is
2327 * optional.
2328 */
2329 child = of_get_child_by_name(np, "mdio");
2330 err = mv88e6xxx_mdio_register(chip, child, false);
2331 if (err)
2332 return err;
2333
2334 /* Walk the device tree, and see if there are any other nodes
2335 * which say they are compatible with the external mdio
2336 * bus.
2337 */
2338 for_each_available_child_of_node(np, child) {
2339 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2340 if (match) {
2341 err = mv88e6xxx_mdio_register(chip, child, true);
3126aeec
AL		 2342 if (err) {
2343 mv88e6xxx_mdios_unregister(chip);
a3c53be5 2344 return err;
3126aeec 2345 }
a3c53be5
AL		 2346 }
2347 }
2348
2349 return 0;
b516d453
AL		 2350}
2351
855b1932
VD		 2352static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2353{
04bed143 2354 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2355
2356 return chip->eeprom_len;
2357}
2358
855b1932
VD		 2359static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2360 struct ethtool_eeprom *eeprom, u8 *data)
2361{
04bed143 2362 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2363 int err;
2364
ee4dc2e7
VD		 2365 if (!chip->info->ops->get_eeprom)
2366 return -EOPNOTSUPP;
855b1932 2367
ee4dc2e7
VD		 2368 mutex_lock(&chip->reg_lock);
2369 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2370 mutex_unlock(&chip->reg_lock);
2371
2372 if (err)
2373 return err;
2374
2375 eeprom->magic = 0xc3ec4951;
2376
2377 return 0;
2378}
2379
855b1932
VD		 2380static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2381 struct ethtool_eeprom *eeprom, u8 *data)
2382{
04bed143 2383 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2384 int err;
2385
ee4dc2e7
VD		 2386 if (!chip->info->ops->set_eeprom)
2387 return -EOPNOTSUPP;
2388
855b1932
VD		 2389 if (eeprom->magic != 0xc3ec4951)
2390 return -EINVAL;
2391
2392 mutex_lock(&chip->reg_lock);
ee4dc2e7 2393 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2394 mutex_unlock(&chip->reg_lock);
2395
2396 return err;
2397}
2398
b3469dd8 2399static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2400 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2401 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2402 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2403 .phy_read = mv88e6185_phy_ppu_read,
2404 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2405 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2406 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2407 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2408 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2409 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2410 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2411 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2412 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2413 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2414 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2415 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2416 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2417 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2418 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2419 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2420 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2421 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2422 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2423 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2424 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2425 .pot_clear = mv88e6xxx_g2_pot_clear,
a199d8b6
VD		 2426 .ppu_enable = mv88e6185_g1_ppu_enable,
2427 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2428 .reset = mv88e6185_g1_reset,
f1394b78 2429 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2430 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2431};
2432
2433static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2434 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2435 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2436 .phy_read = mv88e6185_phy_ppu_read,
2437 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2438 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2439 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2440 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2441 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2442 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2443 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2444 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2445 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2446 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2447 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2448 .stats_get_stats = mv88e6095_stats_get_stats,
51c901a7 2449 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2450 .ppu_enable = mv88e6185_g1_ppu_enable,
2451 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2452 .reset = mv88e6185_g1_reset,
f1394b78 2453 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2454 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2455};
2456
7d381a02 2457static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2458 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2459 .irl_init_all = mv88e6352_g2_irl_init_all,
7d381a02
SE		 2460 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2461 .phy_read = mv88e6xxx_g2_smi_phy_read,
2462 .phy_write = mv88e6xxx_g2_smi_phy_write,
2463 .port_set_link = mv88e6xxx_port_set_link,
2464 .port_set_duplex = mv88e6xxx_port_set_duplex,
2465 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2466 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2467 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2468 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2469 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2470 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2471 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 2472 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2473 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2474 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02 2475 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2476 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
7d381a02
SE		 2477 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2478 .stats_get_strings = mv88e6095_stats_get_strings,
2479 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2480 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2481 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2482 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2483 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2484 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2485 .reset = mv88e6352_g1_reset,
f1394b78 2486 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2487 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
7d381a02
SE		 2488};
2489
b3469dd8 2490static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2491 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2492 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2493 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2494 .phy_read = mv88e6xxx_g2_smi_phy_read,
2495 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2496 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2497 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2498 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2499 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2500 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2501 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2502 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2503 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2504 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2505 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2506 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2507 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2508 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2509 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2510 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2511 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2512 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2513 .reset = mv88e6352_g1_reset,
f1394b78 2514 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2515 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2516};
2517
2518static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2519 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2520 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2521 .phy_read = mv88e6185_phy_ppu_read,
2522 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2523 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2524 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2525 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2526 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2527 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2528 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2529 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2530 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 2531 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2532 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2533 .port_pause_limit = mv88e6097_port_pause_limit,
a605a0fe 2534 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2535 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2536 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2537 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2538 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2539 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2540 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2541 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2542 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2543 .ppu_enable = mv88e6185_g1_ppu_enable,
2544 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2545 .reset = mv88e6185_g1_reset,
f1394b78 2546 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2547 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2548};
2549
990e27b0
VD		 2550static const struct mv88e6xxx_ops mv88e6141_ops = {
2551 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 2552 .irl_init_all = mv88e6352_g2_irl_init_all,
990e27b0
VD		 2553 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2554 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2555 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2556 .phy_read = mv88e6xxx_g2_smi_phy_read,
2557 .phy_write = mv88e6xxx_g2_smi_phy_write,
2558 .port_set_link = mv88e6xxx_port_set_link,
2559 .port_set_duplex = mv88e6xxx_port_set_duplex,
2560 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2561 .port_set_speed = mv88e6390_port_set_speed,
2562 .port_tag_remap = mv88e6095_port_tag_remap,
2563 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2564 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2565 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2566 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 2567 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2568 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 2569 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2570 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2571 .stats_snapshot = mv88e6390_g1_stats_snapshot,
40cff8fc 2572 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
990e27b0
VD		 2573 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2574 .stats_get_strings = mv88e6320_stats_get_strings,
2575 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2576 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2577 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 2578 .watchdog_ops = &mv88e6390_watchdog_ops,
2579 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2580 .pot_clear = mv88e6xxx_g2_pot_clear,
990e27b0 2581 .reset = mv88e6352_g1_reset,
f1394b78 2582 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2583 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
990e27b0
VD		 2584};
2585
b3469dd8 2586static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2587 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2588 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2589 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2590 .phy_read = mv88e6xxx_g2_smi_phy_read,
2591 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2592 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2593 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2594 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2595 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2596 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2597 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2598 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2599 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2600 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2601 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2602 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2603 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
f1c78eee 2604 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2605 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2606 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2607 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2608 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2609 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2610 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2611 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2612 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2613 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2614 .reset = mv88e6352_g1_reset,
f1394b78 2615 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2616 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2617};
2618
2619static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2620 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2621 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2622 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2623 .phy_read = mv88e6165_phy_read,
2624 .phy_write = mv88e6165_phy_write,
08ef7f10 2625 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2626 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2627 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 2628 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2629 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2630 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2631 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2632 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2633 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2634 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2635 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2636 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2637 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2638 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2639 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2640 .reset = mv88e6352_g1_reset,
f1394b78 2641 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2642 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2643};
2644
2645static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2646 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2647 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2648 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2649 .phy_read = mv88e6xxx_g2_smi_phy_read,
2650 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2651 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2652 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2653 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2654 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2655 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2656 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2657 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2658 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2659 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2660 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2661 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2662 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2663 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2664 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2665 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2666 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2667 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2668 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2669 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2670 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2671 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2672 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2673 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2674 .reset = mv88e6352_g1_reset,
f1394b78 2675 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2676 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2677};
2678
2679static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 2680 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2681 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2682 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2683 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2684 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2685 .phy_read = mv88e6xxx_g2_smi_phy_read,
2686 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2687 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2688 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2689 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2690 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2691 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2692 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2693 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2694 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2695 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2696 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2697 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2698 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2699 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2700 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2701 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2702 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2703 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2704 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2705 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2706 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2707 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2708 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2709 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2710 .reset = mv88e6352_g1_reset,
f1394b78 2711 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2712 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2713 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2714};
2715
2716static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 2717 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2718 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2719 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2720 .phy_read = mv88e6xxx_g2_smi_phy_read,
2721 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2722 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2723 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2724 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2725 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2726 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2727 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2728 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2729 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2730 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2731 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2732 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2733 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2734 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2735 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2736 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2737 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2738 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2739 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2740 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2741 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2742 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2743 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2744 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2745 .reset = mv88e6352_g1_reset,
f1394b78 2746 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2747 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2748};
2749
2750static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 2751 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2752 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2753 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2754 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2755 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2756 .phy_read = mv88e6xxx_g2_smi_phy_read,
2757 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2758 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2759 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2760 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2761 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2762 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2763 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2764 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2765 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2766 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2767 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2768 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2769 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2770 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2771 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2772 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2773 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2774 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2775 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2776 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2777 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2778 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2779 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2780 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2781 .reset = mv88e6352_g1_reset,
f1394b78 2782 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2783 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2784 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2785};
2786
2787static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 2788 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2789 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2790 .phy_read = mv88e6185_phy_ppu_read,
2791 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2792 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2793 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2794 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2795 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2796 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 2797 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 2798 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2799 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2800 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2801 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2802 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2803 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2804 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2805 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2806 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2807 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2808 .ppu_enable = mv88e6185_g1_ppu_enable,
2809 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2810 .reset = mv88e6185_g1_reset,
f1394b78 2811 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2812 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2813};
2814
1a3b39ec 2815static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 2816 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2817 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2818 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2819 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2820 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2821 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2822 .phy_read = mv88e6xxx_g2_smi_phy_read,
2823 .phy_write = mv88e6xxx_g2_smi_phy_write,
2824 .port_set_link = mv88e6xxx_port_set_link,
2825 .port_set_duplex = mv88e6xxx_port_set_duplex,
2826 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2827 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2828 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2829 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2830 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2831 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2832 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2833 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2834 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2835 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2836 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2837 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2838 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2839 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2840 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2841 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2842 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2843 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2844 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2845 .reset = mv88e6352_g1_reset,
931d1822
VD		 2846 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2847 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2848 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2849};
2850
2851static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 2852 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2853 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2854 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2855 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2856 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2857 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2858 .phy_read = mv88e6xxx_g2_smi_phy_read,
2859 .phy_write = mv88e6xxx_g2_smi_phy_write,
2860 .port_set_link = mv88e6xxx_port_set_link,
2861 .port_set_duplex = mv88e6xxx_port_set_duplex,
2862 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2863 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 2864 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2865 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2866 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2867 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2868 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2869 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2870 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2871 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2872 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2873 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2874 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2875 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2876 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2877 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2878 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2879 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2880 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2881 .reset = mv88e6352_g1_reset,
931d1822
VD		 2882 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2883 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2884 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2885};
2886
2887static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 2888 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2889 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2890 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2891 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2892 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2893 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2894 .phy_read = mv88e6xxx_g2_smi_phy_read,
2895 .phy_write = mv88e6xxx_g2_smi_phy_write,
2896 .port_set_link = mv88e6xxx_port_set_link,
2897 .port_set_duplex = mv88e6xxx_port_set_duplex,
2898 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2899 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2900 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2901 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2902 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2903 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2904 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2905 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2906 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2907 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2908 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2909 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2910 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2911 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2912 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2913 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2914 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2915 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2916 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2917 .reset = mv88e6352_g1_reset,
931d1822
VD		 2918 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2919 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2920 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2921};
2922
b3469dd8 2923static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 2924 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2925 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2926 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2927 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2928 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2929 .phy_read = mv88e6xxx_g2_smi_phy_read,
2930 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2931 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2932 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2933 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2934 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2935 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2936 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2937 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2938 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2939 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2940 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2941 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2942 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2943 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2944 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2945 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2946 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2947 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2948 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2949 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2950 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2951 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2952 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2953 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2954 .reset = mv88e6352_g1_reset,
f1394b78 2955 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2956 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2957 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2958};
2959
1a3b39ec 2960static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 2961 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2962 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2963 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2964 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2965 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2966 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2967 .phy_read = mv88e6xxx_g2_smi_phy_read,
2968 .phy_write = mv88e6xxx_g2_smi_phy_write,
2969 .port_set_link = mv88e6xxx_port_set_link,
2970 .port_set_duplex = mv88e6xxx_port_set_duplex,
2971 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2972 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2973 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2974 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2975 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2976 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2977 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 2978 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 2979 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2980 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2981 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2982 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2983 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2984 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2985 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2986 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2987 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2988 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2989 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2990 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2991 .reset = mv88e6352_g1_reset,
931d1822
VD		 2992 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2993 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2994 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2995};
2996
b3469dd8 2997static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 2998 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 2999 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3000 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3001 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3002 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3003 .phy_read = mv88e6xxx_g2_smi_phy_read,
3004 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3005 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3006 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3007 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3008 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3009 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3010 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3011 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3012 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3013 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3014 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3015 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3016 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3017 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3018 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3019 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3020 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3021 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 3022 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3023 .set_egress_port = mv88e6095_g1_set_egress_port,
51c901a7 3024 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3025 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3026 .reset = mv88e6352_g1_reset,
f1394b78 3027 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3028 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 3029};
3030
3031static const struct mv88e6xxx_ops mv88e6321_ops = {
bd807204 3032 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 3033 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3034 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3035 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3037 .phy_read = mv88e6xxx_g2_smi_phy_read,
3038 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3039 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3040 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3041 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3042 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3043 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3044 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3045 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3046 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3047 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3048 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3049 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3050 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3051 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3052 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3053 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3054 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3055 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 3056 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3057 .set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3058 .reset = mv88e6352_g1_reset,
f1394b78 3059 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3060 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 3061};
3062
16e329ae
VD		 3063static const struct mv88e6xxx_ops mv88e6341_ops = {
3064 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 3065 .irl_init_all = mv88e6352_g2_irl_init_all,
16e329ae
VD		 3066 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3067 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3068 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3069 .phy_read = mv88e6xxx_g2_smi_phy_read,
3070 .phy_write = mv88e6xxx_g2_smi_phy_write,
3071 .port_set_link = mv88e6xxx_port_set_link,
3072 .port_set_duplex = mv88e6xxx_port_set_duplex,
3073 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3074 .port_set_speed = mv88e6390_port_set_speed,
3075 .port_tag_remap = mv88e6095_port_tag_remap,
3076 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3077 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3078 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3079 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 3080 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3081 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 3082 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3083 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3084 .stats_snapshot = mv88e6390_g1_stats_snapshot,
40cff8fc 3085 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
16e329ae
VD		 3086 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3087 .stats_get_strings = mv88e6320_stats_get_strings,
3088 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3089 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3090 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 3091 .watchdog_ops = &mv88e6390_watchdog_ops,
3092 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3093 .pot_clear = mv88e6xxx_g2_pot_clear,
16e329ae 3094 .reset = mv88e6352_g1_reset,
f1394b78 3095 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3096 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
16e329ae
VD		 3097};
3098
b3469dd8 3099static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3100 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3101 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3102 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3103 .phy_read = mv88e6xxx_g2_smi_phy_read,
3104 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3105 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3106 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3107 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3108 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3109 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3110 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3111 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3112 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3113 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3114 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3115 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3116 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3117 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3118 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3119 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3120 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3121 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3122 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3123 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3124 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3125 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3126 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3127 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3128 .reset = mv88e6352_g1_reset,
f1394b78 3129 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3130 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3131};
3132
3133static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3134 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3135 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3136 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3137 .phy_read = mv88e6xxx_g2_smi_phy_read,
3138 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3139 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3140 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3141 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3142 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3143 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3144 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3145 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3146 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3147 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3148 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3149 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3150 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3151 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3152 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3153 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3154 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3155 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3156 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3157 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3158 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3159 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3160 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3161 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3162 .reset = mv88e6352_g1_reset,
f1394b78 3163 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3164 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3165};
3166
3167static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3168 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 3169 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3170 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3171 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3172 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3173 .phy_read = mv88e6xxx_g2_smi_phy_read,
3174 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3175 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3176 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3177 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3178 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3179 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3180 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3181 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3182 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3183 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3184 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3185 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3186 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3187 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3188 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3189 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3190 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3191 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3192 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3193 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3194 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3195 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3196 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3197 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3198 .reset = mv88e6352_g1_reset,
f1394b78 3199 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3200 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 3201 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 3202};
3203
1a3b39ec 3204static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3205 /* MV88E6XXX_FAMILY_6390 */
f843abe0 3206 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 3207 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3208 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3209 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3210 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3211 .phy_read = mv88e6xxx_g2_smi_phy_read,
3212 .phy_write = mv88e6xxx_g2_smi_phy_write,
3213 .port_set_link = mv88e6xxx_port_set_link,
3214 .port_set_duplex = mv88e6xxx_port_set_duplex,
3215 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3216 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3217 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3218 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3219 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3220 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3221 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3222 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3223 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 3224 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3225 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3226 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3227 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3228 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3229 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3230 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3231 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3232 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3233 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3234 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3235 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3236 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3237 .reset = mv88e6352_g1_reset,
931d1822
VD		 3238 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3239 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3240 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3241};
3242
3243static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3244 /* MV88E6XXX_FAMILY_6390 */
f843abe0 3245 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 3246 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3247 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3248 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3249 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3250 .phy_read = mv88e6xxx_g2_smi_phy_read,
3251 .phy_write = mv88e6xxx_g2_smi_phy_write,
3252 .port_set_link = mv88e6xxx_port_set_link,
3253 .port_set_duplex = mv88e6xxx_port_set_duplex,
3254 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3255 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3256 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3257 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3258 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3259 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3260 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3261 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3262 .port_pause_limit = mv88e6390_port_pause_limit,
bb0a2675 3263 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3264 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3265 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3266 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3267 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3268 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3269 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3270 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3271 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3272 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3273 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3274 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3275 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3276 .reset = mv88e6352_g1_reset,
931d1822
VD		 3277 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3278 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3279 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3280};
3281
f81ec90f
VD		 3282static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3283 [MV88E6085] = {
107fcc10 3284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 3285 .family = MV88E6XXX_FAMILY_6097,
3286 .name = "Marvell 88E6085",
3287 .num_databases = 4096,
3288 .num_ports = 10,
3cf3c846 3289 .max_vid = 4095,
9dddd478 3290 .port_base_addr = 0x10,
a935c052 3291 .global1_addr = 0x1b,
9069c13a 3292 .global2_addr = 0x1c,
acddbd21 3293 .age_time_coeff = 15000,
dc30c35b 3294 .g1_irqs = 8,
d6c5e6af 3295 .g2_irqs = 10,
e606ca36 3296 .atu_move_port_mask = 0xf,
f3645652 3297 .pvt = true,
b3e05aa1 3298 .multi_chip = true,
443d5a1b 3299 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3300 .ops = &mv88e6085_ops,
f81ec90f
VD		 3301 },
3302
3303 [MV88E6095] = {
107fcc10 3304 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 3305 .family = MV88E6XXX_FAMILY_6095,
3306 .name = "Marvell 88E6095/88E6095F",
3307 .num_databases = 256,
3308 .num_ports = 11,
3cf3c846 3309 .max_vid = 4095,
9dddd478 3310 .port_base_addr = 0x10,
a935c052 3311 .global1_addr = 0x1b,
9069c13a 3312 .global2_addr = 0x1c,
acddbd21 3313 .age_time_coeff = 15000,
dc30c35b 3314 .g1_irqs = 8,
e606ca36 3315 .atu_move_port_mask = 0xf,
b3e05aa1 3316 .multi_chip = true,
443d5a1b 3317 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3318 .ops = &mv88e6095_ops,
f81ec90f
VD		 3319 },
3320
7d381a02 3321 [MV88E6097] = {
107fcc10 3322 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 3323 .family = MV88E6XXX_FAMILY_6097,
3324 .name = "Marvell 88E6097/88E6097F",
3325 .num_databases = 4096,
3326 .num_ports = 11,
3cf3c846 3327 .max_vid = 4095,
7d381a02
SE		 3328 .port_base_addr = 0x10,
3329 .global1_addr = 0x1b,
9069c13a 3330 .global2_addr = 0x1c,
7d381a02 3331 .age_time_coeff = 15000,
c534178b 3332 .g1_irqs = 8,
d6c5e6af 3333 .g2_irqs = 10,
e606ca36 3334 .atu_move_port_mask = 0xf,
f3645652 3335 .pvt = true,
b3e05aa1 3336 .multi_chip = true,
2bfcfcd3 3337 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3338 .ops = &mv88e6097_ops,
3339 },
3340
f81ec90f 3341 [MV88E6123] = {
107fcc10 3342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 3343 .family = MV88E6XXX_FAMILY_6165,
3344 .name = "Marvell 88E6123",
3345 .num_databases = 4096,
3346 .num_ports = 3,
3cf3c846 3347 .max_vid = 4095,
9dddd478 3348 .port_base_addr = 0x10,
a935c052 3349 .global1_addr = 0x1b,
9069c13a 3350 .global2_addr = 0x1c,
acddbd21 3351 .age_time_coeff = 15000,
dc30c35b 3352 .g1_irqs = 9,
d6c5e6af 3353 .g2_irqs = 10,
e606ca36 3354 .atu_move_port_mask = 0xf,
f3645652 3355 .pvt = true,
b3e05aa1 3356 .multi_chip = true,
5ebe31d7 3357 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3358 .ops = &mv88e6123_ops,
f81ec90f
VD		 3359 },
3360
3361 [MV88E6131] = {
107fcc10 3362 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 3363 .family = MV88E6XXX_FAMILY_6185,
3364 .name = "Marvell 88E6131",
3365 .num_databases = 256,
3366 .num_ports = 8,
3cf3c846 3367 .max_vid = 4095,
9dddd478 3368 .port_base_addr = 0x10,
a935c052 3369 .global1_addr = 0x1b,
9069c13a 3370 .global2_addr = 0x1c,
acddbd21 3371 .age_time_coeff = 15000,
dc30c35b 3372 .g1_irqs = 9,
e606ca36 3373 .atu_move_port_mask = 0xf,
b3e05aa1 3374 .multi_chip = true,
443d5a1b 3375 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3376 .ops = &mv88e6131_ops,
f81ec90f
VD		 3377 },
3378
990e27b0 3379 [MV88E6141] = {
107fcc10 3380 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0
VD		 3381 .family = MV88E6XXX_FAMILY_6341,
3382 .name = "Marvell 88E6341",
3383 .num_databases = 4096,
3384 .num_ports = 6,
3cf3c846 3385 .max_vid = 4095,
990e27b0
VD		 3386 .port_base_addr = 0x10,
3387 .global1_addr = 0x1b,
9069c13a 3388 .global2_addr = 0x1c,
990e27b0
VD		 3389 .age_time_coeff = 3750,
3390 .atu_move_port_mask = 0x1f,
d6c5e6af 3391 .g2_irqs = 10,
f3645652 3392 .pvt = true,
b3e05aa1 3393 .multi_chip = true,
990e27b0 3394 .tag_protocol = DSA_TAG_PROTO_EDSA,
990e27b0
VD		 3395 .ops = &mv88e6141_ops,
3396 },
3397
f81ec90f 3398 [MV88E6161] = {
107fcc10 3399 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 3400 .family = MV88E6XXX_FAMILY_6165,
3401 .name = "Marvell 88E6161",
3402 .num_databases = 4096,
3403 .num_ports = 6,
3cf3c846 3404 .max_vid = 4095,
9dddd478 3405 .port_base_addr = 0x10,
a935c052 3406 .global1_addr = 0x1b,
9069c13a 3407 .global2_addr = 0x1c,
acddbd21 3408 .age_time_coeff = 15000,
dc30c35b 3409 .g1_irqs = 9,
d6c5e6af 3410 .g2_irqs = 10,
e606ca36 3411 .atu_move_port_mask = 0xf,
f3645652 3412 .pvt = true,
b3e05aa1 3413 .multi_chip = true,
5ebe31d7 3414 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3415 .ops = &mv88e6161_ops,
f81ec90f
VD		 3416 },
3417
3418 [MV88E6165] = {
107fcc10 3419 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 3420 .family = MV88E6XXX_FAMILY_6165,
3421 .name = "Marvell 88E6165",
3422 .num_databases = 4096,
3423 .num_ports = 6,
3cf3c846 3424 .max_vid = 4095,
9dddd478 3425 .port_base_addr = 0x10,
a935c052 3426 .global1_addr = 0x1b,
9069c13a 3427 .global2_addr = 0x1c,
acddbd21 3428 .age_time_coeff = 15000,
dc30c35b 3429 .g1_irqs = 9,
d6c5e6af 3430 .g2_irqs = 10,
e606ca36 3431 .atu_move_port_mask = 0xf,
f3645652 3432 .pvt = true,
b3e05aa1 3433 .multi_chip = true,
443d5a1b 3434 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3435 .ops = &mv88e6165_ops,
f81ec90f
VD		 3436 },
3437
3438 [MV88E6171] = {
107fcc10 3439 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 3440 .family = MV88E6XXX_FAMILY_6351,
3441 .name = "Marvell 88E6171",
3442 .num_databases = 4096,
3443 .num_ports = 7,
3cf3c846 3444 .max_vid = 4095,
9dddd478 3445 .port_base_addr = 0x10,
a935c052 3446 .global1_addr = 0x1b,
9069c13a 3447 .global2_addr = 0x1c,
acddbd21 3448 .age_time_coeff = 15000,
dc30c35b 3449 .g1_irqs = 9,
d6c5e6af 3450 .g2_irqs = 10,
e606ca36 3451 .atu_move_port_mask = 0xf,
f3645652 3452 .pvt = true,
b3e05aa1 3453 .multi_chip = true,
443d5a1b 3454 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3455 .ops = &mv88e6171_ops,
f81ec90f
VD		 3456 },
3457
3458 [MV88E6172] = {
107fcc10 3459 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 3460 .family = MV88E6XXX_FAMILY_6352,
3461 .name = "Marvell 88E6172",
3462 .num_databases = 4096,
3463 .num_ports = 7,
3cf3c846 3464 .max_vid = 4095,
9dddd478 3465 .port_base_addr = 0x10,
a935c052 3466 .global1_addr = 0x1b,
9069c13a 3467 .global2_addr = 0x1c,
acddbd21 3468 .age_time_coeff = 15000,
dc30c35b 3469 .g1_irqs = 9,
d6c5e6af 3470 .g2_irqs = 10,
e606ca36 3471 .atu_move_port_mask = 0xf,
f3645652 3472 .pvt = true,
b3e05aa1 3473 .multi_chip = true,
443d5a1b 3474 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3475 .ops = &mv88e6172_ops,
f81ec90f
VD		 3476 },
3477
3478 [MV88E6175] = {
107fcc10 3479 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 3480 .family = MV88E6XXX_FAMILY_6351,
3481 .name = "Marvell 88E6175",
3482 .num_databases = 4096,
3483 .num_ports = 7,
3cf3c846 3484 .max_vid = 4095,
9dddd478 3485 .port_base_addr = 0x10,
a935c052 3486 .global1_addr = 0x1b,
9069c13a 3487 .global2_addr = 0x1c,
acddbd21 3488 .age_time_coeff = 15000,
dc30c35b 3489 .g1_irqs = 9,
d6c5e6af 3490 .g2_irqs = 10,
e606ca36 3491 .atu_move_port_mask = 0xf,
f3645652 3492 .pvt = true,
b3e05aa1 3493 .multi_chip = true,
443d5a1b 3494 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3495 .ops = &mv88e6175_ops,
f81ec90f
VD		 3496 },
3497
3498 [MV88E6176] = {
107fcc10 3499 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 3500 .family = MV88E6XXX_FAMILY_6352,
3501 .name = "Marvell 88E6176",
3502 .num_databases = 4096,
3503 .num_ports = 7,
3cf3c846 3504 .max_vid = 4095,
9dddd478 3505 .port_base_addr = 0x10,
a935c052 3506 .global1_addr = 0x1b,
9069c13a 3507 .global2_addr = 0x1c,
acddbd21 3508 .age_time_coeff = 15000,
dc30c35b 3509 .g1_irqs = 9,
d6c5e6af 3510 .g2_irqs = 10,
e606ca36 3511 .atu_move_port_mask = 0xf,
f3645652 3512 .pvt = true,
b3e05aa1 3513 .multi_chip = true,
443d5a1b 3514 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3515 .ops = &mv88e6176_ops,
f81ec90f
VD		 3516 },
3517
3518 [MV88E6185] = {
107fcc10 3519 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 3520 .family = MV88E6XXX_FAMILY_6185,
3521 .name = "Marvell 88E6185",
3522 .num_databases = 256,
3523 .num_ports = 10,
3cf3c846 3524 .max_vid = 4095,
9dddd478 3525 .port_base_addr = 0x10,
a935c052 3526 .global1_addr = 0x1b,
9069c13a 3527 .global2_addr = 0x1c,
acddbd21 3528 .age_time_coeff = 15000,
dc30c35b 3529 .g1_irqs = 8,
e606ca36 3530 .atu_move_port_mask = 0xf,
b3e05aa1 3531 .multi_chip = true,
443d5a1b 3532 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3533 .ops = &mv88e6185_ops,
f81ec90f
VD		 3534 },
3535
1a3b39ec 3536 [MV88E6190] = {
107fcc10 3537 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 3538 .family = MV88E6XXX_FAMILY_6390,
3539 .name = "Marvell 88E6190",
3540 .num_databases = 4096,
3541 .num_ports = 11, /* 10 + Z80 */
931d1822 3542 .max_vid = 8191,
1a3b39ec
AL		 3543 .port_base_addr = 0x0,
3544 .global1_addr = 0x1b,
9069c13a 3545 .global2_addr = 0x1c,
443d5a1b 3546 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3547 .age_time_coeff = 3750,
1a3b39ec 3548 .g1_irqs = 9,
d6c5e6af 3549 .g2_irqs = 14,
f3645652 3550 .pvt = true,
b3e05aa1 3551 .multi_chip = true,
e606ca36 3552 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3553 .ops = &mv88e6190_ops,
3554 },
3555
3556 [MV88E6190X] = {
107fcc10 3557 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 3558 .family = MV88E6XXX_FAMILY_6390,
3559 .name = "Marvell 88E6190X",
3560 .num_databases = 4096,
3561 .num_ports = 11, /* 10 + Z80 */
931d1822 3562 .max_vid = 8191,
1a3b39ec
AL		 3563 .port_base_addr = 0x0,
3564 .global1_addr = 0x1b,
9069c13a 3565 .global2_addr = 0x1c,
b91e055c 3566 .age_time_coeff = 3750,
1a3b39ec 3567 .g1_irqs = 9,
d6c5e6af 3568 .g2_irqs = 14,
e606ca36 3569 .atu_move_port_mask = 0x1f,
f3645652 3570 .pvt = true,
b3e05aa1 3571 .multi_chip = true,
443d5a1b 3572 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3573 .ops = &mv88e6190x_ops,
3574 },
3575
3576 [MV88E6191] = {
107fcc10 3577 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 3578 .family = MV88E6XXX_FAMILY_6390,
3579 .name = "Marvell 88E6191",
3580 .num_databases = 4096,
3581 .num_ports = 11, /* 10 + Z80 */
931d1822 3582 .max_vid = 8191,
1a3b39ec
AL		 3583 .port_base_addr = 0x0,
3584 .global1_addr = 0x1b,
9069c13a 3585 .global2_addr = 0x1c,
b91e055c 3586 .age_time_coeff = 3750,
443d5a1b 3587 .g1_irqs = 9,
d6c5e6af 3588 .g2_irqs = 14,
e606ca36 3589 .atu_move_port_mask = 0x1f,
f3645652 3590 .pvt = true,
b3e05aa1 3591 .multi_chip = true,
443d5a1b 3592 .tag_protocol = DSA_TAG_PROTO_DSA,
2cf4cefb 3593 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3594 },
3595
f81ec90f 3596 [MV88E6240] = {
107fcc10 3597 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 3598 .family = MV88E6XXX_FAMILY_6352,
3599 .name = "Marvell 88E6240",
3600 .num_databases = 4096,
3601 .num_ports = 7,
3cf3c846 3602 .max_vid = 4095,
9dddd478 3603 .port_base_addr = 0x10,
a935c052 3604 .global1_addr = 0x1b,
9069c13a 3605 .global2_addr = 0x1c,
acddbd21 3606 .age_time_coeff = 15000,
dc30c35b 3607 .g1_irqs = 9,
d6c5e6af 3608 .g2_irqs = 10,
e606ca36 3609 .atu_move_port_mask = 0xf,
f3645652 3610 .pvt = true,
b3e05aa1 3611 .multi_chip = true,
443d5a1b 3612 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3613 .ops = &mv88e6240_ops,
f81ec90f
VD		 3614 },
3615
1a3b39ec 3616 [MV88E6290] = {
107fcc10 3617 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 3618 .family = MV88E6XXX_FAMILY_6390,
3619 .name = "Marvell 88E6290",
3620 .num_databases = 4096,
3621 .num_ports = 11, /* 10 + Z80 */
931d1822 3622 .max_vid = 8191,
1a3b39ec
AL		 3623 .port_base_addr = 0x0,
3624 .global1_addr = 0x1b,
9069c13a 3625 .global2_addr = 0x1c,
b91e055c 3626 .age_time_coeff = 3750,
1a3b39ec 3627 .g1_irqs = 9,
d6c5e6af 3628 .g2_irqs = 14,
e606ca36 3629 .atu_move_port_mask = 0x1f,
f3645652 3630 .pvt = true,
b3e05aa1 3631 .multi_chip = true,
443d5a1b 3632 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3633 .ops = &mv88e6290_ops,
3634 },
3635
f81ec90f 3636 [MV88E6320] = {
107fcc10 3637 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 3638 .family = MV88E6XXX_FAMILY_6320,
3639 .name = "Marvell 88E6320",
3640 .num_databases = 4096,
3641 .num_ports = 7,
3cf3c846 3642 .max_vid = 4095,
9dddd478 3643 .port_base_addr = 0x10,
a935c052 3644 .global1_addr = 0x1b,
9069c13a 3645 .global2_addr = 0x1c,
acddbd21 3646 .age_time_coeff = 15000,
dc30c35b 3647 .g1_irqs = 8,
e606ca36 3648 .atu_move_port_mask = 0xf,
f3645652 3649 .pvt = true,
b3e05aa1 3650 .multi_chip = true,
443d5a1b 3651 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3652 .ops = &mv88e6320_ops,
f81ec90f
VD		 3653 },
3654
3655 [MV88E6321] = {
107fcc10 3656 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 3657 .family = MV88E6XXX_FAMILY_6320,
3658 .name = "Marvell 88E6321",
3659 .num_databases = 4096,
3660 .num_ports = 7,
3cf3c846 3661 .max_vid = 4095,
9dddd478 3662 .port_base_addr = 0x10,
a935c052 3663 .global1_addr = 0x1b,
9069c13a 3664 .global2_addr = 0x1c,
acddbd21 3665 .age_time_coeff = 15000,
dc30c35b 3666 .g1_irqs = 8,
e606ca36 3667 .atu_move_port_mask = 0xf,
b3e05aa1 3668 .multi_chip = true,
443d5a1b 3669 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3670 .ops = &mv88e6321_ops,
f81ec90f
VD		 3671 },
3672
a75961d0 3673 [MV88E6341] = {
107fcc10 3674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 3675 .family = MV88E6XXX_FAMILY_6341,
3676 .name = "Marvell 88E6341",
3677 .num_databases = 4096,
3678 .num_ports = 6,
3cf3c846 3679 .max_vid = 4095,
a75961d0
GC		 3680 .port_base_addr = 0x10,
3681 .global1_addr = 0x1b,
9069c13a 3682 .global2_addr = 0x1c,
a75961d0 3683 .age_time_coeff = 3750,
e606ca36 3684 .atu_move_port_mask = 0x1f,
d6c5e6af 3685 .g2_irqs = 10,
f3645652 3686 .pvt = true,
b3e05aa1 3687 .multi_chip = true,
a75961d0 3688 .tag_protocol = DSA_TAG_PROTO_EDSA,
a75961d0
GC		 3689 .ops = &mv88e6341_ops,
3690 },
3691
f81ec90f 3692 [MV88E6350] = {
107fcc10 3693 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 3694 .family = MV88E6XXX_FAMILY_6351,
3695 .name = "Marvell 88E6350",
3696 .num_databases = 4096,
3697 .num_ports = 7,
3cf3c846 3698 .max_vid = 4095,
9dddd478 3699 .port_base_addr = 0x10,
a935c052 3700 .global1_addr = 0x1b,
9069c13a 3701 .global2_addr = 0x1c,
acddbd21 3702 .age_time_coeff = 15000,
dc30c35b 3703 .g1_irqs = 9,
d6c5e6af 3704 .g2_irqs = 10,
e606ca36 3705 .atu_move_port_mask = 0xf,
f3645652 3706 .pvt = true,
b3e05aa1 3707 .multi_chip = true,
443d5a1b 3708 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3709 .ops = &mv88e6350_ops,
f81ec90f
VD		 3710 },
3711
3712 [MV88E6351] = {
107fcc10 3713 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 3714 .family = MV88E6XXX_FAMILY_6351,
3715 .name = "Marvell 88E6351",
3716 .num_databases = 4096,
3717 .num_ports = 7,
3cf3c846 3718 .max_vid = 4095,
9dddd478 3719 .port_base_addr = 0x10,
a935c052 3720 .global1_addr = 0x1b,
9069c13a 3721 .global2_addr = 0x1c,
acddbd21 3722 .age_time_coeff = 15000,
dc30c35b 3723 .g1_irqs = 9,
d6c5e6af 3724 .g2_irqs = 10,
e606ca36 3725 .atu_move_port_mask = 0xf,
f3645652 3726 .pvt = true,
b3e05aa1 3727 .multi_chip = true,
443d5a1b 3728 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3729 .ops = &mv88e6351_ops,
f81ec90f
VD		 3730 },
3731
3732 [MV88E6352] = {
107fcc10 3733 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 3734 .family = MV88E6XXX_FAMILY_6352,
3735 .name = "Marvell 88E6352",
3736 .num_databases = 4096,
3737 .num_ports = 7,
3cf3c846 3738 .max_vid = 4095,
9dddd478 3739 .port_base_addr = 0x10,
a935c052 3740 .global1_addr = 0x1b,
9069c13a 3741 .global2_addr = 0x1c,
acddbd21 3742 .age_time_coeff = 15000,
dc30c35b 3743 .g1_irqs = 9,
d6c5e6af 3744 .g2_irqs = 10,
e606ca36 3745 .atu_move_port_mask = 0xf,
f3645652 3746 .pvt = true,
b3e05aa1 3747 .multi_chip = true,
443d5a1b 3748 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3749 .ops = &mv88e6352_ops,
f81ec90f 3750 },
1a3b39ec 3751 [MV88E6390] = {
107fcc10 3752 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 3753 .family = MV88E6XXX_FAMILY_6390,
3754 .name = "Marvell 88E6390",
3755 .num_databases = 4096,
3756 .num_ports = 11, /* 10 + Z80 */
931d1822 3757 .max_vid = 8191,
1a3b39ec
AL		 3758 .port_base_addr = 0x0,
3759 .global1_addr = 0x1b,
9069c13a 3760 .global2_addr = 0x1c,
b91e055c 3761 .age_time_coeff = 3750,
1a3b39ec 3762 .g1_irqs = 9,
d6c5e6af 3763 .g2_irqs = 14,
e606ca36 3764 .atu_move_port_mask = 0x1f,
f3645652 3765 .pvt = true,
b3e05aa1 3766 .multi_chip = true,
443d5a1b 3767 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3768 .ops = &mv88e6390_ops,
3769 },
3770 [MV88E6390X] = {
107fcc10 3771 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 3772 .family = MV88E6XXX_FAMILY_6390,
3773 .name = "Marvell 88E6390X",
3774 .num_databases = 4096,
3775 .num_ports = 11, /* 10 + Z80 */
931d1822 3776 .max_vid = 8191,
1a3b39ec
AL		 3777 .port_base_addr = 0x0,
3778 .global1_addr = 0x1b,
9069c13a 3779 .global2_addr = 0x1c,
b91e055c 3780 .age_time_coeff = 3750,
1a3b39ec 3781 .g1_irqs = 9,
d6c5e6af 3782 .g2_irqs = 14,
e606ca36 3783 .atu_move_port_mask = 0x1f,
f3645652 3784 .pvt = true,
b3e05aa1 3785 .multi_chip = true,
443d5a1b 3786 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3787 .ops = &mv88e6390x_ops,
3788 },
f81ec90f
VD		 3789};
3790
5f7c0367 3791static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3792{
a439c061 3793 int i;
b9b37713 3794
5f7c0367
VD		 3795 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3796 if (mv88e6xxx_table[i].prod_num == prod_num)
3797 return &mv88e6xxx_table[i];
b9b37713 3798
b9b37713
VD		 3799 return NULL;
3800}
3801
fad09c73 3802static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3803{
3804 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3805 unsigned int prod_num, rev;
3806 u16 id;
3807 int err;
bc46a3d5 3808
8f6345b2 3809 mutex_lock(&chip->reg_lock);
107fcc10 3810 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
8f6345b2
VD		 3811 mutex_unlock(&chip->reg_lock);
3812 if (err)
3813 return err;
bc46a3d5 3814
107fcc10
VD		 3815 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3816 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 3817
3818 info = mv88e6xxx_lookup_info(prod_num);
3819 if (!info)
3820 return -ENODEV;
3821
caac8545 3822 /* Update the compatible info with the probed one */
fad09c73 3823 chip->info = info;
bc46a3d5 3824
ca070c10
VD		 3825 err = mv88e6xxx_g2_require(chip);
3826 if (err)
3827 return err;
3828
fad09c73
VD		 3829 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3830 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3831
3832 return 0;
3833}
3834
fad09c73 3835static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3836{
fad09c73 3837 struct mv88e6xxx_chip *chip;
469d729f 3838
fad09c73
VD		 3839 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3840 if (!chip)
469d729f
VD		 3841 return NULL;
3842
fad09c73 3843 chip->dev = dev;
469d729f 3844
fad09c73 3845 mutex_init(&chip->reg_lock);
a3c53be5 3846 INIT_LIST_HEAD(&chip->mdios);
469d729f 3847
fad09c73 3848 return chip;
469d729f
VD		 3849}
3850
fad09c73 3851static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3852 struct mii_bus *bus, int sw_addr)
3853{
914b32f6 3854 if (sw_addr == 0)
fad09c73 3855 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
b3e05aa1 3856 else if (chip->info->multi_chip)
fad09c73 3857 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3858 else
3859 return -EINVAL;
3860
fad09c73
VD		 3861 chip->bus = bus;
3862 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3863
3864 return 0;
3865}
3866
5ed4e3eb
FF		 3867static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
3868 int port)
7b314362 3869{
04bed143 3870 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 3871
443d5a1b 3872 return chip->info->tag_protocol;
7b314362
AL		 3873}
3874
fcdce7d0
AL		 3875static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3876 struct device *host_dev, int sw_addr,
3877 void **priv)
a77d43f1 3878{
fad09c73 3879 struct mv88e6xxx_chip *chip;
a439c061 3880 struct mii_bus *bus;
b516d453 3881 int err;
a77d43f1 3882
a439c061 3883 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3884 if (!bus)
3885 return NULL;
3886
fad09c73
VD		 3887 chip = mv88e6xxx_alloc_chip(dsa_dev);
3888 if (!chip)
469d729f
VD		 3889 return NULL;
3890
caac8545 3891 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3892 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3893
fad09c73 3894 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3895 if (err)
3896 goto free;
3897
fad09c73 3898 err = mv88e6xxx_detect(chip);
bc46a3d5 3899 if (err)
469d729f 3900 goto free;
a439c061 3901
dc30c35b
AL		 3902 mutex_lock(&chip->reg_lock);
3903 err = mv88e6xxx_switch_reset(chip);
3904 mutex_unlock(&chip->reg_lock);
3905 if (err)
3906 goto free;
3907
e57e5e77
VD		 3908 mv88e6xxx_phy_init(chip);
3909
a3c53be5 3910 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 3911 if (err)
469d729f 3912 goto free;
b516d453 3913
fad09c73 3914 *priv = chip;
a439c061 3915
fad09c73 3916 return chip->info->name;
469d729f 3917free:
fad09c73 3918 devm_kfree(dsa_dev, chip);
469d729f
VD		 3919
3920 return NULL;
a77d43f1
AL		 3921}
3922
7df8fbdd
VD		 3923static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3924 const struct switchdev_obj_port_mdb *mdb,
3925 struct switchdev_trans *trans)
3926{
3927 /* We don't need any dynamic resource from the kernel (yet),
3928 * so skip the prepare phase.
3929 */
3930
3931 return 0;
3932}
3933
3934static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3935 const struct switchdev_obj_port_mdb *mdb,
3936 struct switchdev_trans *trans)
3937{
04bed143 3938 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3939
3940 mutex_lock(&chip->reg_lock);
3941 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3942 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
774439e5
VD		 3943 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3944 port);
7df8fbdd
VD		 3945 mutex_unlock(&chip->reg_lock);
3946}
3947
3948static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3949 const struct switchdev_obj_port_mdb *mdb)
3950{
04bed143 3951 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3952 int err;
3953
3954 mutex_lock(&chip->reg_lock);
3955 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3956 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
7df8fbdd
VD		 3957 mutex_unlock(&chip->reg_lock);
3958
3959 return err;
3960}
3961
a82f67af 3962static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3963 .probe = mv88e6xxx_drv_probe,
7b314362 3964 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f 3965 .setup = mv88e6xxx_setup,
f81ec90f
VD		 3966 .adjust_link = mv88e6xxx_adjust_link,
3967 .get_strings = mv88e6xxx_get_strings,
3968 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3969 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 3970 .port_enable = mv88e6xxx_port_enable,
3971 .port_disable = mv88e6xxx_port_disable,
08f50061
VD		 3972 .get_mac_eee = mv88e6xxx_get_mac_eee,
3973 .set_mac_eee = mv88e6xxx_set_mac_eee,
f8cd8753 3974 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3975 .get_eeprom = mv88e6xxx_get_eeprom,
3976 .set_eeprom = mv88e6xxx_set_eeprom,
3977 .get_regs_len = mv88e6xxx_get_regs_len,
3978 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3979 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3980 .port_bridge_join = mv88e6xxx_port_bridge_join,
3981 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3982 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3983 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3984 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3985 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3986 .port_vlan_add = mv88e6xxx_port_vlan_add,
3987 .port_vlan_del = mv88e6xxx_port_vlan_del,
f81ec90f
VD		 3988 .port_fdb_add = mv88e6xxx_port_fdb_add,
3989 .port_fdb_del = mv88e6xxx_port_fdb_del,
3990 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3991 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3992 .port_mdb_add = mv88e6xxx_port_mdb_add,
3993 .port_mdb_del = mv88e6xxx_port_mdb_del,
aec5ac88
VD		 3994 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3995 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 3996};
3997
ab3d408d
FF		 3998static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3999 .ops = &mv88e6xxx_switch_ops,
4000};
4001
55ed0ce0 4002static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4003{
fad09c73 4004 struct device *dev = chip->dev;
b7e66a5f
VD		 4005 struct dsa_switch *ds;
4006
73b1204d 4007 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 4008 if (!ds)
4009 return -ENOMEM;
4010
fad09c73 4011 ds->priv = chip;
9d490b4e 4012 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 4013 ds->ageing_time_min = chip->info->age_time_coeff;
4014 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 4015
4016 dev_set_drvdata(dev, ds);
4017
23c9ee49 4018 return dsa_register_switch(ds);
b7e66a5f
VD		 4019}
4020
fad09c73 4021static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4022{
fad09c73 4023 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4024}
4025
57d32310 4026static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4027{
14c7b3c3 4028 struct device *dev = &mdiodev->dev;
f8cd8753 4029 struct device_node *np = dev->of_node;
caac8545 4030 const struct mv88e6xxx_info *compat_info;
fad09c73 4031 struct mv88e6xxx_chip *chip;
f8cd8753 4032 u32 eeprom_len;
52638f71 4033 int err;
14c7b3c3 4034
caac8545
VD		 4035 compat_info = of_device_get_match_data(dev);
4036 if (!compat_info)
4037 return -EINVAL;
4038
fad09c73
VD		 4039 chip = mv88e6xxx_alloc_chip(dev);
4040 if (!chip)
14c7b3c3
AL		 4041 return -ENOMEM;
4042
fad09c73 4043 chip->info = compat_info;
caac8545 4044
fad09c73 4045 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4046 if (err)
4047 return err;
14c7b3c3 4048
b4308f04
AL		 4049 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4050 if (IS_ERR(chip->reset))
4051 return PTR_ERR(chip->reset);
4052
fad09c73 4053 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4054 if (err)
4055 return err;
14c7b3c3 4056
e57e5e77
VD		 4057 mv88e6xxx_phy_init(chip);
4058
ee4dc2e7 4059 if (chip->info->ops->get_eeprom &&
f8cd8753 4060 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4061 chip->eeprom_len = eeprom_len;
f8cd8753 4062
dc30c35b
AL		 4063 mutex_lock(&chip->reg_lock);
4064 err = mv88e6xxx_switch_reset(chip);
4065 mutex_unlock(&chip->reg_lock);
4066 if (err)
4067 goto out;
4068
4069 chip->irq = of_irq_get(np, 0);
4070 if (chip->irq == -EPROBE_DEFER) {
4071 err = chip->irq;
4072 goto out;
4073 }
4074
4075 if (chip->irq > 0) {
4076 /* Has to be performed before the MDIO bus is created,
4077 * because the PHYs will link there interrupts to these
4078 * interrupt controllers
4079 */
4080 mutex_lock(&chip->reg_lock);
4081 err = mv88e6xxx_g1_irq_setup(chip);
4082 mutex_unlock(&chip->reg_lock);
4083
4084 if (err)
4085 goto out;
4086
d6c5e6af 4087 if (chip->info->g2_irqs > 0) {
dc30c35b
AL		 4088 err = mv88e6xxx_g2_irq_setup(chip);
4089 if (err)
4090 goto out_g1_irq;
4091 }
4092 }
71611e57
BS		 4093 if (chip->reset)
4094 usleep_range(1000, 2000);
dc30c35b 4095
a3c53be5 4096 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4097 if (err)
dc30c35b 4098 goto out_g2_irq;
b516d453 4099
55ed0ce0 4100 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4101 if (err)
4102 goto out_mdio;
83c0afae 4103
98e67308 4104 return 0;
dc30c35b
AL		 4105
4106out_mdio:
a3c53be5 4107 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4108out_g2_irq:
d6c5e6af 4109 if (chip->info->g2_irqs > 0 && chip->irq > 0)
dc30c35b
AL		 4110 mv88e6xxx_g2_irq_free(chip);
4111out_g1_irq:
61f7c3f8
AL		 4112 if (chip->irq > 0) {
4113 mutex_lock(&chip->reg_lock);
46712644 4114 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4115 mutex_unlock(&chip->reg_lock);
4116 }
dc30c35b
AL		 4117out:
4118 return err;
98e67308 4119}
14c7b3c3
AL		 4120
4121static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4122{
4123 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4124 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4125
930188ce 4126 mv88e6xxx_phy_destroy(chip);
fad09c73 4127 mv88e6xxx_unregister_switch(chip);
a3c53be5 4128 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4129
46712644 4130 if (chip->irq > 0) {
d6c5e6af 4131 if (chip->info->g2_irqs > 0)
46712644 4132 mv88e6xxx_g2_irq_free(chip);
b32ca44a 4133 mutex_lock(&chip->reg_lock);
46712644 4134 mv88e6xxx_g1_irq_free(chip);
b32ca44a 4135 mutex_unlock(&chip->reg_lock);
46712644 4136 }
14c7b3c3
AL		 4137}
4138
4139static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4140 {
4141 .compatible = "marvell,mv88e6085",
4142 .data = &mv88e6xxx_table[MV88E6085],
4143 },
1a3b39ec
AL		 4144 {
4145 .compatible = "marvell,mv88e6190",
4146 .data = &mv88e6xxx_table[MV88E6190],
4147 },
14c7b3c3
AL		 4148 { /* sentinel */ },
4149};
4150
4151MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4152
4153static struct mdio_driver mv88e6xxx_driver = {
4154 .probe = mv88e6xxx_probe,
4155 .remove = mv88e6xxx_remove,
4156 .mdiodrv.driver = {
4157 .name = "mv88e6085",
4158 .of_match_table = mv88e6xxx_of_match,
4159 },
4160};
4161
4162static int __init mv88e6xxx_init(void)
4163{
ab3d408d 4164 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4165 return mdio_driver_register(&mv88e6xxx_driver);
4166}
98e67308
BH		 4167module_init(mv88e6xxx_init);
4168
4169static void __exit mv88e6xxx_cleanup(void)
4170{
14c7b3c3 4171 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4172 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4173}
4174module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4175
4176MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4177MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4178MODULE_LICENSE("GPL");
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