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net: dsa: mv88e6xxx: move VTU FID accessors
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
ee26a228
AL		 225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
efb3e74d
AL		 228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
ee26a228
AL		 232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
efb3e74d
AL		 235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
a3c53be5
AL		 239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
e57e5e77
VD		 251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 255 struct mii_bus *bus;
e57e5e77 256
a3c53be5
AL		 257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
e57e5e77
VD		 259 return -EOPNOTSUPP;
260
a3c53be5 261 if (!chip->info->ops->phy_read)
ee26a228
AL		 262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 271 struct mii_bus *bus;
e57e5e77 272
a3c53be5
AL		 273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
e57e5e77
VD		 275 return -EOPNOTSUPP;
276
a3c53be5 277 if (!chip->info->ops->phy_write)
ee26a228
AL		 278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 281}
282
09cb7dfd
VD		 283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
dc30c35b
AL		 351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
3460a577
AL		 452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
dc30c35b 459
5edef2f2 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 462 irq_dispose_mapping(virq);
463 }
464
a3db3d3a 465 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
3dd0ef05
AL		 470 int err, irq, virq;
471 u16 reg, mask;
dc30c35b
AL		 472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
3dd0ef05 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 487 if (err)
3dd0ef05 488 goto out_mapping;
dc30c35b 489
3dd0ef05 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 491
3dd0ef05 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 493 if (err)
3dd0ef05 494 goto out_disable;
dc30c35b
AL		 495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
3dd0ef05 499 goto out_disable;
dc30c35b
AL		 500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
3dd0ef05 506 goto out_disable;
dc30c35b
AL		 507
508 return 0;
509
3dd0ef05
AL		 510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 521
522 return err;
523}
524
ec561276 525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 526{
6441e669 527 int i;
2d79af6e 528
6441e669 529 for (i = 0; i < 16; i++) {
2d79af6e
VD		 530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
30853553 543 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 544 return -ETIMEDOUT;
545}
546
f22ab641 547/* Indirect write to single pointer-data register with an Update bit */
ec561276 548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 549{
550 u16 val;
0f02b4f7 551 int err;
f22ab641
VD		 552
553 /* Wait until the previous operation is completed */
0f02b4f7
AL		 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
f22ab641
VD		 557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
a935c052 564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 565{
a199d8b6
VD		 566 if (!chip->info->ops->ppu_disable)
567 return 0;
2e5f0320 568
a199d8b6 569 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 570}
571
fad09c73 572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 573{
a199d8b6
VD		 574 if (!chip->info->ops->ppu_enable)
575 return 0;
2e5f0320 576
a199d8b6 577 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
fad09c73 582 struct mv88e6xxx_chip *chip;
2e5f0320 583
fad09c73 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 585
fad09c73 586 mutex_lock(&chip->reg_lock);
762eb67b 587
fad09c73
VD		 588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
2e5f0320 592 }
762eb67b 593
fad09c73 594 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
fad09c73 599 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 600
fad09c73 601 schedule_work(&chip->ppu_work);
2e5f0320
LB		 602}
603
fad09c73 604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 605{
2e5f0320
LB		 606 int ret;
607
fad09c73 608 mutex_lock(&chip->ppu_mutex);
2e5f0320 609
3675c8d7 610 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
fad09c73
VD		 615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
85686581 617 if (ret < 0) {
fad09c73 618 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 619 return ret;
620 }
fad09c73 621 chip->ppu_disabled = 1;
2e5f0320 622 } else {
fad09c73 623 del_timer(&chip->ppu_timer);
85686581 624 ret = 0;
2e5f0320
LB		 625 }
626
627 return ret;
628}
629
fad09c73 630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 631{
3675c8d7 632 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 635}
636
fad09c73 637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 638{
fad09c73
VD		 639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
2e5f0320
LB		 643}
644
930188ce
AL		 645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
ee26a228
AL		 650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
2e5f0320 653{
e57e5e77 654 int err;
2e5f0320 655
e57e5e77
VD		 656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 659 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 660 }
661
e57e5e77 662 return err;
2e5f0320
LB		 663}
664
ee26a228
AL		 665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 688}
689
a75961d0
GC		 690static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
691{
692 return chip->info->family == MV88E6XXX_FAMILY_6341;
693}
694
fad09c73 695static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 696{
fad09c73 697 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 698}
699
fad09c73 700static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 703}
704
d78343d2
VD		 705static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
706 int link, int speed, int duplex,
707 phy_interface_t mode)
708{
709 int err;
710
711 if (!chip->info->ops->port_set_link)
712 return 0;
713
714 /* Port's MAC control must not be changed unless the link is down */
715 err = chip->info->ops->port_set_link(chip, port, 0);
716 if (err)
717 return err;
718
719 if (chip->info->ops->port_set_speed) {
720 err = chip->info->ops->port_set_speed(chip, port, speed);
721 if (err && err != -EOPNOTSUPP)
722 goto restore_link;
723 }
724
725 if (chip->info->ops->port_set_duplex) {
726 err = chip->info->ops->port_set_duplex(chip, port, duplex);
727 if (err && err != -EOPNOTSUPP)
728 goto restore_link;
729 }
730
731 if (chip->info->ops->port_set_rgmii_delay) {
732 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
733 if (err && err != -EOPNOTSUPP)
734 goto restore_link;
735 }
736
f39908d3
AL		 737 if (chip->info->ops->port_set_cmode) {
738 err = chip->info->ops->port_set_cmode(chip, port, mode);
739 if (err && err != -EOPNOTSUPP)
740 goto restore_link;
741 }
742
d78343d2
VD		 743 err = 0;
744restore_link:
745 if (chip->info->ops->port_set_link(chip, port, link))
746 netdev_err(chip->ds->ports[port].netdev,
747 "failed to restore MAC's link\n");
748
749 return err;
750}
751
dea87024
AL		 752/* We expect the switch to perform auto negotiation if there is a real
753 * phy. However, in the case of a fixed link phy, we force the port
754 * settings from the fixed link settings.
755 */
f81ec90f
VD		 756static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
757 struct phy_device *phydev)
dea87024 758{
04bed143 759 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 760 int err;
dea87024
AL		 761
762 if (!phy_is_pseudo_fixed_link(phydev))
763 return;
764
fad09c73 765 mutex_lock(&chip->reg_lock);
d78343d2
VD		 766 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
767 phydev->duplex, phydev->interface);
fad09c73 768 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 769
770 if (err && err != -EOPNOTSUPP)
771 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 772}
773
a605a0fe 774static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 775{
a605a0fe
AL		 776 if (!chip->info->ops->stats_snapshot)
777 return -EOPNOTSUPP;
91da11f8 778
a605a0fe 779 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 780}
781
e413e7e1 782static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 783 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
784 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
785 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
786 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
787 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
788 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
789 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
790 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
791 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
792 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
793 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
794 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
795 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
796 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
797 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
798 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
799 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
800 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
801 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
802 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
803 { "single", 4, 0x14, STATS_TYPE_BANK0, },
804 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
805 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
806 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
807 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
808 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
809 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
810 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
811 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
812 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
813 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
814 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
815 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
816 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
817 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
818 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
819 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
820 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
821 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
822 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
823 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
824 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
825 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
826 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
827 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
828 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
829 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
830 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
831 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
832 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
833 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
834 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
835 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
836 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
837 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
838 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
839 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
840 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
841 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 842};
843
fad09c73 844static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 845 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 846 int port, u16 bank1_select,
847 u16 histogram)
80c4627b 848{
80c4627b
AL		 849 u32 low;
850 u32 high = 0;
dfafe449 851 u16 reg = 0;
0e7b9925 852 int err;
80c4627b
AL		 853 u64 value;
854
f5e2ed02 855 switch (s->type) {
dfafe449 856 case STATS_TYPE_PORT:
0e7b9925
AL		 857 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
858 if (err)
80c4627b
AL		 859 return UINT64_MAX;
860
0e7b9925 861 low = reg;
80c4627b 862 if (s->sizeof_stat == 4) {
0e7b9925
AL		 863 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
864 if (err)
80c4627b 865 return UINT64_MAX;
0e7b9925 866 high = reg;
80c4627b 867 }
f5e2ed02 868 break;
dfafe449 869 case STATS_TYPE_BANK1:
e0d8b615 870 reg = bank1_select;
dfafe449
AL		 871 /* fall through */
872 case STATS_TYPE_BANK0:
e0d8b615 873 reg |= s->reg | histogram;
7f9ef3af 874 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 875 if (s->sizeof_stat == 8)
7f9ef3af 876 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 877 }
878 value = (((u64)high) << 16) | low;
879 return value;
880}
881
dfafe449
AL		 882static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
883 uint8_t *data, int types)
91da11f8 884{
f5e2ed02
AL		 885 struct mv88e6xxx_hw_stat *stat;
886 int i, j;
91da11f8 887
f5e2ed02
AL		 888 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
889 stat = &mv88e6xxx_hw_stats[i];
dfafe449 890 if (stat->type & types) {
f5e2ed02
AL		 891 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
892 ETH_GSTRING_LEN);
893 j++;
894 }
91da11f8 895 }
e413e7e1
AL		 896}
897
dfafe449
AL		 898static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
899 uint8_t *data)
900{
901 mv88e6xxx_stats_get_strings(chip, data,
902 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
903}
904
905static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
906 uint8_t *data)
907{
908 mv88e6xxx_stats_get_strings(chip, data,
909 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
910}
911
912static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
913 uint8_t *data)
e413e7e1 914{
04bed143 915 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 916
917 if (chip->info->ops->stats_get_strings)
918 chip->info->ops->stats_get_strings(chip, data);
919}
920
921static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
922 int types)
923{
f5e2ed02
AL		 924 struct mv88e6xxx_hw_stat *stat;
925 int i, j;
926
927 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
928 stat = &mv88e6xxx_hw_stats[i];
dfafe449 929 if (stat->type & types)
f5e2ed02
AL		 930 j++;
931 }
932 return j;
e413e7e1
AL		 933}
934
dfafe449
AL		 935static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
936{
937 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
938 STATS_TYPE_PORT);
939}
940
941static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
942{
943 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
944 STATS_TYPE_BANK1);
945}
946
947static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
948{
949 struct mv88e6xxx_chip *chip = ds->priv;
950
951 if (chip->info->ops->stats_get_sset_count)
952 return chip->info->ops->stats_get_sset_count(chip);
953
954 return 0;
955}
956
052f947f 957static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 958 uint64_t *data, int types,
959 u16 bank1_select, u16 histogram)
052f947f
AL		 960{
961 struct mv88e6xxx_hw_stat *stat;
962 int i, j;
963
964 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
965 stat = &mv88e6xxx_hw_stats[i];
966 if (stat->type & types) {
e0d8b615
AL		 967 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
968 bank1_select,
969 histogram);
052f947f
AL		 970 j++;
971 }
972 }
973}
974
975static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
976 uint64_t *data)
977{
978 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 979 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
980 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 981}
982
983static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
984 uint64_t *data)
985{
986 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 987 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
988 GLOBAL_STATS_OP_BANK_1_BIT_9,
989 GLOBAL_STATS_OP_HIST_RX_TX);
990}
991
992static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
993 uint64_t *data)
994{
995 return mv88e6xxx_stats_get_stats(chip, port, data,
996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
997 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 998}
999
1000static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1001 uint64_t *data)
1002{
1003 if (chip->info->ops->stats_get_stats)
1004 chip->info->ops->stats_get_stats(chip, port, data);
1005}
1006
f81ec90f
VD		 1007static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1008 uint64_t *data)
e413e7e1 1009{
04bed143 1010 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1011 int ret;
f5e2ed02 1012
fad09c73 1013 mutex_lock(&chip->reg_lock);
f5e2ed02 1014
a605a0fe 1015 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1016 if (ret < 0) {
fad09c73 1017 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1018 return;
1019 }
052f947f
AL		 1020
1021 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1022
fad09c73 1023 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1024}
1025
de227387
AL		 1026static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1027{
1028 if (chip->info->ops->stats_set_histogram)
1029 return chip->info->ops->stats_set_histogram(chip);
1030
1031 return 0;
1032}
1033
f81ec90f 1034static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1035{
1036 return 32 * sizeof(u16);
1037}
1038
f81ec90f
VD		 1039static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1040 struct ethtool_regs *regs, void *_p)
a1ab91f3 1041{
04bed143 1042 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1043 int err;
1044 u16 reg;
a1ab91f3
GR		 1045 u16 *p = _p;
1046 int i;
1047
1048 regs->version = 0;
1049
1050 memset(p, 0xff, 32 * sizeof(u16));
1051
fad09c73 1052 mutex_lock(&chip->reg_lock);
23062513 1053
a1ab91f3 1054 for (i = 0; i < 32; i++) {
a1ab91f3 1055
0e7b9925
AL		 1056 err = mv88e6xxx_port_read(chip, port, i, &reg);
1057 if (!err)
1058 p[i] = reg;
a1ab91f3 1059 }
23062513 1060
fad09c73 1061 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1062}
1063
f81ec90f
VD		 1064static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1065 struct ethtool_eee *e)
11b3b45d 1066{
04bed143 1067 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1068 u16 reg;
1069 int err;
11b3b45d 1070
fad09c73 1071 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1072 return -EOPNOTSUPP;
1073
fad09c73 1074 mutex_lock(&chip->reg_lock);
2f40c698 1075
9c93829c
VD		 1076 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1077 if (err)
2f40c698 1078 goto out;
11b3b45d
GR		 1079
1080 e->eee_enabled = !!(reg & 0x0200);
1081 e->tx_lpi_enabled = !!(reg & 0x0100);
1082
0e7b9925 1083 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1084 if (err)
2f40c698 1085 goto out;
11b3b45d 1086
cca8b133 1087 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1088out:
fad09c73 1089 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1090
1091 return err;
11b3b45d
GR		 1092}
1093
f81ec90f
VD		 1094static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1095 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1096{
04bed143 1097 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1098 u16 reg;
1099 int err;
11b3b45d 1100
fad09c73 1101 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1102 return -EOPNOTSUPP;
1103
fad09c73 1104 mutex_lock(&chip->reg_lock);
11b3b45d 1105
9c93829c
VD		 1106 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1107 if (err)
2f40c698
AL		 1108 goto out;
1109
9c93829c 1110 reg &= ~0x0300;
2f40c698
AL		 1111 if (e->eee_enabled)
1112 reg |= 0x0200;
1113 if (e->tx_lpi_enabled)
1114 reg |= 0x0100;
1115
9c93829c 1116 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1117out:
fad09c73 1118 mutex_unlock(&chip->reg_lock);
2f40c698 1119
9c93829c 1120 return err;
11b3b45d
GR		 1121}
1122
e5887a2a 1123static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 1124{
e5887a2a
VD		 1125 struct dsa_switch *ds = NULL;
1126 struct net_device *br;
1127 u16 pvlan;
b7666efe
VD		 1128 int i;
1129
e5887a2a
VD		 1130 if (dev < DSA_MAX_SWITCHES)
1131 ds = chip->ds->dst->ds[dev];
1132
1133 /* Prevent frames from unknown switch or port */
1134 if (!ds || port >= ds->num_ports)
1135 return 0;
1136
1137 /* Frames from DSA links and CPU ports can egress any local port */
1138 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1139 return mv88e6xxx_port_mask(chip);
1140
1141 br = ds->ports[port].bridge_dev;
1142 pvlan = 0;
1143
1144 /* Frames from user ports can egress any local DSA links and CPU ports,
1145 * as well as any local member of their bridge group.
1146 */
1147 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1148 if (dsa_is_cpu_port(chip->ds, i) ||
1149 dsa_is_dsa_port(chip->ds, i) ||
1150 (br && chip->ds->ports[i].bridge_dev == br))
1151 pvlan |= BIT(i);
1152
1153 return pvlan;
1154}
1155
240ea3ef 1156static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 1157{
1158 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 1159
1160 /* prevent frames from going back out of the port they came in on */
1161 output_ports &= ~BIT(port);
facd95b2 1162
5a7921f4 1163 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1164}
1165
f81ec90f
VD		 1166static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1167 u8 state)
facd95b2 1168{
04bed143 1169 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1170 int stp_state;
553eb544 1171 int err;
facd95b2
GR		 1172
1173 switch (state) {
1174 case BR_STATE_DISABLED:
cca8b133 1175 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1176 break;
1177 case BR_STATE_BLOCKING:
1178 case BR_STATE_LISTENING:
cca8b133 1179 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1180 break;
1181 case BR_STATE_LEARNING:
cca8b133 1182 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1183 break;
1184 case BR_STATE_FORWARDING:
1185 default:
cca8b133 1186 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1187 break;
1188 }
1189
fad09c73 1190 mutex_lock(&chip->reg_lock);
e28def33 1191 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1192 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1193
1194 if (err)
e28def33 1195 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1196}
1197
a2ac29d2
VD		 1198static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1199{
c3a7d4ad
VD		 1200 int err;
1201
daefc943
VD		 1202 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1203 if (err)
1204 return err;
1205
c3a7d4ad
VD		 1206 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1207 if (err)
1208 return err;
1209
a2ac29d2
VD		 1210 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1211}
1212
17a1594e
VD		 1213static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1214{
1215 u16 pvlan = 0;
1216
1217 if (!mv88e6xxx_has_pvt(chip))
1218 return -EOPNOTSUPP;
1219
1220 /* Skip the local source device, which uses in-chip port VLAN */
1221 if (dev != chip->ds->index)
aec5ac88 1222 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 1223
1224 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1225}
1226
81228996
VD		 1227static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1228{
17a1594e
VD		 1229 int dev, port;
1230 int err;
1231
81228996
VD		 1232 if (!mv88e6xxx_has_pvt(chip))
1233 return 0;
1234
1235 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1236 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1237 */
17a1594e
VD		 1238 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1239 if (err)
1240 return err;
1241
1242 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1243 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1244 err = mv88e6xxx_pvt_map(chip, dev, port);
1245 if (err)
1246 return err;
1247 }
1248 }
1249
1250 return 0;
81228996
VD		 1251}
1252
749efcb8
VD		 1253static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1254{
1255 struct mv88e6xxx_chip *chip = ds->priv;
1256 int err;
1257
1258 mutex_lock(&chip->reg_lock);
e606ca36 1259 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1260 mutex_unlock(&chip->reg_lock);
1261
1262 if (err)
1263 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1264}
1265
fad09c73 1266static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1267 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1268 unsigned int nibble_offset)
1269{
b8fee957 1270 u16 regs[3];
a935c052 1271 int i, err;
b8fee957
VD		 1272
1273 for (i = 0; i < 3; ++i) {
a935c052 1274 u16 *reg = &regs[i];
b8fee957 1275
a935c052
VD		 1276 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1277 if (err)
1278 return err;
b8fee957
VD		 1279 }
1280
370b4ffb 1281 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1282 unsigned int shift = (i % 4) * 4 + nibble_offset;
1283 u16 reg = regs[i / 4];
1284
bd00e053 1285 entry->state[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
b8fee957
VD		 1286 }
1287
1288 return 0;
1289}
1290
fad09c73 1291static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1292 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1293{
fad09c73 1294 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1295}
1296
fad09c73 1297static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1298 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1299{
fad09c73 1300 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1301}
1302
fad09c73 1303static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1304 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1305 unsigned int nibble_offset)
1306{
7dad08d7 1307 u16 regs[3] = { 0 };
a935c052 1308 int i, err;
7dad08d7 1309
370b4ffb 1310 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7 1311 unsigned int shift = (i % 4) * 4 + nibble_offset;
bd00e053 1312 u8 data = entry->state[i];
7dad08d7
VD		 1313
1314 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1315 }
1316
1317 for (i = 0; i < 3; ++i) {
a935c052
VD		 1318 u16 reg = regs[i];
1319
1320 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1321 if (err)
1322 return err;
7dad08d7
VD		 1323 }
1324
1325 return 0;
1326}
1327
fad09c73 1328static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1329 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1330{
fad09c73 1331 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1332}
1333
fad09c73 1334static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1335 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1336{
fad09c73 1337 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1338}
1339
fad09c73 1340static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1341{
a935c052
VD		 1342 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1343 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1344}
1345
fad09c73 1346static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1347 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1348{
b4e47c0f 1349 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1350 u16 val;
1351 int err;
b8fee957 1352
332aa5cc 1353 err = mv88e6xxx_g1_vtu_op_wait(chip);
a935c052
VD		 1354 if (err)
1355 return err;
b8fee957 1356
332aa5cc 1357 err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
a935c052
VD		 1358 if (err)
1359 return err;
b8fee957 1360
a935c052
VD		 1361 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1362 if (err)
1363 return err;
b8fee957 1364
a935c052
VD		 1365 next.vid = val & GLOBAL_VTU_VID_MASK;
1366 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1367
1368 if (next.valid) {
a935c052
VD		 1369 err = mv88e6xxx_vtu_data_read(chip, &next);
1370 if (err)
1371 return err;
b8fee957 1372
6dc10bbc 1373 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
8ee51f6b 1374 err = mv88e6xxx_g1_vtu_fid_read(chip, &next);
a935c052
VD		 1375 if (err)
1376 return err;
fad09c73 1377 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1378 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1379 * VTU DBNum[3:0] are located in VTU Operation 3:0
1380 */
a935c052
VD		 1381 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1382 if (err)
1383 return err;
11ea809f 1384
a935c052
VD		 1385 next.fid = (val & 0xf00) >> 4;
1386 next.fid |= val & 0xf;
2e7bd5ef 1387 }
b8fee957 1388
fad09c73 1389 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1390 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1391 if (err)
1392 return err;
b8fee957 1393
a935c052 1394 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1395 }
1396 }
1397
1398 *entry = next;
1399 return 0;
1400}
1401
b486d7c9
VD		 1402static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1403{
1404 if (!chip->info->max_vid)
1405 return 0;
1406
1407 return mv88e6xxx_g1_vtu_flush(chip);
1408}
1409
f81ec90f
VD		 1410static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1411 struct switchdev_obj_port_vlan *vlan,
1412 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1413{
04bed143 1414 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1415 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1416 u16 pvid;
1417 int err;
1418
3cf3c846 1419 if (!chip->info->max_vid)
54d77b5b
VD		 1420 return -EOPNOTSUPP;
1421
fad09c73 1422 mutex_lock(&chip->reg_lock);
ceff5eff 1423
77064f37 1424 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1425 if (err)
1426 goto unlock;
1427
fad09c73 1428 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1429 if (err)
1430 goto unlock;
1431
1432 do {
fad09c73 1433 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1434 if (err)
1435 break;
1436
1437 if (!next.valid)
1438 break;
1439
bd00e053 1440 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
ceff5eff
VD		 1441 continue;
1442
1443 /* reinit and dump this VLAN obj */
57d32310
VD		 1444 vlan->vid_begin = next.vid;
1445 vlan->vid_end = next.vid;
ceff5eff
VD		 1446 vlan->flags = 0;
1447
bd00e053 1448 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
ceff5eff
VD		 1449 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1450
1451 if (next.vid == pvid)
1452 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1453
1454 err = cb(&vlan->obj);
1455 if (err)
1456 break;
3cf3c846 1457 } while (next.vid < chip->info->max_vid);
ceff5eff
VD		 1458
1459unlock:
fad09c73 1460 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1461
1462 return err;
1463}
1464
fad09c73 1465static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1466 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1467{
11ea809f 1468 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1469 u16 reg = 0;
a935c052 1470 int err;
7dad08d7 1471
332aa5cc 1472 err = mv88e6xxx_g1_vtu_op_wait(chip);
a935c052
VD		 1473 if (err)
1474 return err;
7dad08d7
VD		 1475
1476 if (!entry->valid)
1477 goto loadpurge;
1478
1479 /* Write port member tags */
a935c052
VD		 1480 err = mv88e6xxx_vtu_data_write(chip, entry);
1481 if (err)
1482 return err;
7dad08d7 1483
fad09c73 1484 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1485 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1486 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1487 if (err)
1488 return err;
b426e5f7 1489 }
7dad08d7 1490
6dc10bbc 1491 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
8ee51f6b 1492 err = mv88e6xxx_g1_vtu_fid_write(chip, entry);
a935c052
VD		 1493 if (err)
1494 return err;
fad09c73 1495 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1496 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1497 * VTU DBNum[3:0] are located in VTU Operation 3:0
1498 */
1499 op |= (entry->fid & 0xf0) << 8;
1500 op |= entry->fid & 0xf;
7dad08d7
VD		 1501 }
1502
1503 reg = GLOBAL_VTU_VID_VALID;
1504loadpurge:
1505 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1506 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1507 if (err)
1508 return err;
7dad08d7 1509
332aa5cc 1510 return mv88e6xxx_g1_vtu_op(chip, op);
7dad08d7
VD		 1511}
1512
fad09c73 1513static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1514 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1515{
b4e47c0f 1516 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1517 u16 val;
1518 int err;
0d3b33e6 1519
332aa5cc 1520 err = mv88e6xxx_g1_vtu_op_wait(chip);
a935c052
VD		 1521 if (err)
1522 return err;
0d3b33e6 1523
a935c052
VD		 1524 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1525 sid & GLOBAL_VTU_SID_MASK);
1526 if (err)
1527 return err;
0d3b33e6 1528
332aa5cc 1529 err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
a935c052
VD		 1530 if (err)
1531 return err;
0d3b33e6 1532
a935c052
VD		 1533 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1534 if (err)
1535 return err;
0d3b33e6 1536
a935c052 1537 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1538
a935c052
VD		 1539 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1540 if (err)
1541 return err;
0d3b33e6 1542
a935c052 1543 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1544
1545 if (next.valid) {
a935c052
VD		 1546 err = mv88e6xxx_stu_data_read(chip, &next);
1547 if (err)
1548 return err;
0d3b33e6
VD		 1549 }
1550
1551 *entry = next;
1552 return 0;
1553}
1554
fad09c73 1555static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1556 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1557{
1558 u16 reg = 0;
a935c052 1559 int err;
0d3b33e6 1560
332aa5cc 1561 err = mv88e6xxx_g1_vtu_op_wait(chip);
a935c052
VD		 1562 if (err)
1563 return err;
0d3b33e6
VD		 1564
1565 if (!entry->valid)
1566 goto loadpurge;
1567
1568 /* Write port states */
a935c052
VD		 1569 err = mv88e6xxx_stu_data_write(chip, entry);
1570 if (err)
1571 return err;
0d3b33e6
VD		 1572
1573 reg = GLOBAL_VTU_VID_VALID;
1574loadpurge:
a935c052
VD		 1575 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1576 if (err)
1577 return err;
0d3b33e6
VD		 1578
1579 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1580 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1581 if (err)
1582 return err;
0d3b33e6 1583
332aa5cc 1584 return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1585}
1586
d7f435f9 1587static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1588{
1589 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1590 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1591 int i, err;
3285f9e8
VD		 1592
1593 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1594
2db9ce1f 1595 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1596 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1597 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1598 if (err)
1599 return err;
1600
1601 set_bit(*fid, fid_bitmap);
1602 }
1603
3285f9e8 1604 /* Set every FID bit used by the VLAN entries */
fad09c73 1605 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1606 if (err)
1607 return err;
1608
1609 do {
fad09c73 1610 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1611 if (err)
1612 return err;
1613
1614 if (!vlan.valid)
1615 break;
1616
1617 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1618 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1619
1620 /* The reset value 0x000 is used to indicate that multiple address
1621 * databases are not needed. Return the next positive available.
1622 */
1623 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1624 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1625 return -ENOSPC;
1626
1627 /* Clear the database */
daefc943 1628 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1629}
1630
fad09c73 1631static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1632 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1633{
fad09c73 1634 struct dsa_switch *ds = chip->ds;
b4e47c0f 1635 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1636 .valid = true,
1637 .vid = vid,
1638 };
3285f9e8
VD		 1639 int i, err;
1640
d7f435f9 1641 err = mv88e6xxx_atu_new(chip, &vlan.fid);
3285f9e8
VD		 1642 if (err)
1643 return err;
0d3b33e6 1644
3d131f07 1645 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1646 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
bd00e053
VD		 1647 vlan.member[i] = dsa_is_cpu_port(ds, i) ||
1648 dsa_is_dsa_port(ds, i)
3d131f07
VD		 1649 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1650 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1651
fad09c73 1652 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
a75961d0
GC		 1653 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1654 mv88e6xxx_6341_family(chip)) {
b4e47c0f 1655 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1656
1657 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1658 * implemented, only one STU entry is needed to cover all VTU
1659 * entries. Thus, validate the SID 0.
1660 */
1661 vlan.sid = 0;
fad09c73 1662 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1663 if (err)
1664 return err;
1665
1666 if (vstp.sid != vlan.sid || !vstp.valid) {
1667 memset(&vstp, 0, sizeof(vstp));
1668 vstp.valid = true;
1669 vstp.sid = vlan.sid;
1670
fad09c73 1671 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1672 if (err)
1673 return err;
1674 }
0d3b33e6
VD		 1675 }
1676
1677 *entry = vlan;
1678 return 0;
1679}
1680
fad09c73 1681static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1682 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1683{
1684 int err;
1685
1686 if (!vid)
1687 return -EINVAL;
1688
fad09c73 1689 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1690 if (err)
1691 return err;
1692
fad09c73 1693 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1694 if (err)
1695 return err;
1696
1697 if (entry->vid != vid || !entry->valid) {
1698 if (!creat)
1699 return -EOPNOTSUPP;
1700 /* -ENOENT would've been more appropriate, but switchdev expects
1701 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1702 */
1703
fad09c73 1704 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1705 }
1706
1707 return err;
1708}
1709
da9c359e
VD		 1710static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1711 u16 vid_begin, u16 vid_end)
1712{
04bed143 1713 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1714 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1715 int i, err;
1716
1717 if (!vid_begin)
1718 return -EOPNOTSUPP;
1719
fad09c73 1720 mutex_lock(&chip->reg_lock);
da9c359e 1721
fad09c73 1722 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1723 if (err)
1724 goto unlock;
1725
1726 do {
fad09c73 1727 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1728 if (err)
1729 goto unlock;
1730
1731 if (!vlan.valid)
1732 break;
1733
1734 if (vlan.vid > vid_end)
1735 break;
1736
370b4ffb 1737 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1738 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1739 continue;
1740
66e2809d
AL		 1741 if (!ds->ports[port].netdev)
1742 continue;
1743
bd00e053 1744 if (vlan.member[i] ==
da9c359e
VD		 1745 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1746 continue;
1747
fae8a25e
VD		 1748 if (ds->ports[i].bridge_dev ==
1749 ds->ports[port].bridge_dev)
da9c359e
VD		 1750 break; /* same bridge, check next VLAN */
1751
fae8a25e 1752 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1753 continue;
1754
c8b09808 1755 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1756 "hardware VLAN %d already used by %s\n",
1757 vlan.vid,
fae8a25e 1758 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1759 err = -EOPNOTSUPP;
1760 goto unlock;
1761 }
1762 } while (vlan.vid < vid_end);
1763
1764unlock:
fad09c73 1765 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1766
1767 return err;
1768}
1769
f81ec90f
VD		 1770static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1771 bool vlan_filtering)
214cdb99 1772{
04bed143 1773 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1774 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1775 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1776 int err;
214cdb99 1777
3cf3c846 1778 if (!chip->info->max_vid)
54d77b5b
VD		 1779 return -EOPNOTSUPP;
1780
fad09c73 1781 mutex_lock(&chip->reg_lock);
385a0995 1782 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1783 mutex_unlock(&chip->reg_lock);
214cdb99 1784
0e7b9925 1785 return err;
214cdb99
VD		 1786}
1787
57d32310
VD		 1788static int
1789mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1790 const struct switchdev_obj_port_vlan *vlan,
1791 struct switchdev_trans *trans)
76e398a6 1792{
04bed143 1793 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1794 int err;
1795
3cf3c846 1796 if (!chip->info->max_vid)
54d77b5b
VD		 1797 return -EOPNOTSUPP;
1798
da9c359e
VD		 1799 /* If the requested port doesn't belong to the same bridge as the VLAN
1800 * members, do not support it (yet) and fallback to software VLAN.
1801 */
1802 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1803 vlan->vid_end);
1804 if (err)
1805 return err;
1806
76e398a6
VD		 1807 /* We don't need any dynamic resource from the kernel (yet),
1808 * so skip the prepare phase.
1809 */
1810 return 0;
1811}
1812
fad09c73 1813static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1814 u16 vid, bool untagged)
0d3b33e6 1815{
b4e47c0f 1816 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1817 int err;
1818
fad09c73 1819 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1820 if (err)
76e398a6 1821 return err;
0d3b33e6 1822
bd00e053 1823 vlan.member[port] = untagged ?
0d3b33e6
VD		 1824 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1825 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1826
fad09c73 1827 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1828}
1829
f81ec90f
VD		 1830static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1831 const struct switchdev_obj_port_vlan *vlan,
1832 struct switchdev_trans *trans)
76e398a6 1833{
04bed143 1834 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1835 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1836 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1837 u16 vid;
76e398a6 1838
3cf3c846 1839 if (!chip->info->max_vid)
54d77b5b
VD		 1840 return;
1841
fad09c73 1842 mutex_lock(&chip->reg_lock);
76e398a6 1843
4d5770b3 1844 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1845 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1846 netdev_err(ds->ports[port].netdev,
1847 "failed to add VLAN %d%c\n",
4d5770b3 1848 vid, untagged ? 'u' : 't');
76e398a6 1849
77064f37 1850 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1851 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1852 vlan->vid_end);
0d3b33e6 1853
fad09c73 1854 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1855}
1856
fad09c73 1857static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1858 int port, u16 vid)
7dad08d7 1859{
fad09c73 1860 struct dsa_switch *ds = chip->ds;
b4e47c0f 1861 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1862 int i, err;
1863
fad09c73 1864 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1865 if (err)
76e398a6 1866 return err;
7dad08d7 1867
2fb5ef09 1868 /* Tell switchdev if this VLAN is handled in software */
bd00e053 1869 if (vlan.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1870 return -EOPNOTSUPP;
7dad08d7 1871
bd00e053 1872 vlan.member[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1873
1874 /* keep the VLAN unless all ports are excluded */
f02bdffc 1875 vlan.valid = false;
370b4ffb 1876 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1877 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1878 continue;
1879
bd00e053 1880 if (vlan.member[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1881 vlan.valid = true;
7dad08d7
VD		 1882 break;
1883 }
1884 }
1885
fad09c73 1886 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1887 if (err)
1888 return err;
1889
e606ca36 1890 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1891}
1892
f81ec90f
VD		 1893static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1894 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1895{
04bed143 1896 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1897 u16 pvid, vid;
1898 int err = 0;
1899
3cf3c846 1900 if (!chip->info->max_vid)
54d77b5b
VD		 1901 return -EOPNOTSUPP;
1902
fad09c73 1903 mutex_lock(&chip->reg_lock);
76e398a6 1904
77064f37 1905 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1906 if (err)
1907 goto unlock;
1908
76e398a6 1909 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1910 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1911 if (err)
1912 goto unlock;
1913
1914 if (vid == pvid) {
77064f37 1915 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1916 if (err)
1917 goto unlock;
1918 }
1919 }
1920
7dad08d7 1921unlock:
fad09c73 1922 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1923
1924 return err;
1925}
1926
83dabd1f
VD		 1927static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1928 const unsigned char *addr, u16 vid,
1929 u8 state)
fd231c82 1930{
b4e47c0f 1931 struct mv88e6xxx_vtu_entry vlan;
88472939 1932 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1933 int err;
1934
2db9ce1f
VD		 1935 /* Null VLAN ID corresponds to the port private database */
1936 if (vid == 0)
b4e48c50 1937 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1938 else
fad09c73 1939 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1940 if (err)
1941 return err;
fd231c82 1942
dabc1a96
VD		 1943 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1944 ether_addr_copy(entry.mac, addr);
1945 eth_addr_dec(entry.mac);
1946
1947 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1948 if (err)
1949 return err;
1950
dabc1a96
VD		 1951 /* Initialize a fresh ATU entry if it isn't found */
1952 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1953 !ether_addr_equal(entry.mac, addr)) {
1954 memset(&entry, 0, sizeof(entry));
1955 ether_addr_copy(entry.mac, addr);
1956 }
1957
88472939
VD		 1958 /* Purge the ATU entry only if no port is using it anymore */
1959 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1960 entry.portvec &= ~BIT(port);
1961 if (!entry.portvec)
88472939
VD		 1962 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1963 } else {
01bd96c8 1964 entry.portvec |= BIT(port);
88472939 1965 entry.state = state;
fd231c82
VD		 1966 }
1967
9c13c026 1968 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1969}
1970
f81ec90f
VD		 1971static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1972 const struct switchdev_obj_port_fdb *fdb,
1973 struct switchdev_trans *trans)
146a3206
VD		 1974{
1975 /* We don't need any dynamic resource from the kernel (yet),
1976 * so skip the prepare phase.
1977 */
1978 return 0;
1979}
1980
f81ec90f
VD		 1981static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1982 const struct switchdev_obj_port_fdb *fdb,
1983 struct switchdev_trans *trans)
87820510 1984{
04bed143 1985 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1986
fad09c73 1987 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1988 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1989 GLOBAL_ATU_DATA_STATE_UC_STATIC))
1990 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 1991 mutex_unlock(&chip->reg_lock);
87820510
VD		 1992}
1993
f81ec90f
VD		 1994static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1995 const struct switchdev_obj_port_fdb *fdb)
87820510 1996{
04bed143 1997 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1998 int err;
87820510 1999
fad09c73 2000 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2001 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2002 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2003 mutex_unlock(&chip->reg_lock);
87820510 2004
83dabd1f 2005 return err;
87820510
VD		 2006}
2007
83dabd1f
VD		 2008static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2009 u16 fid, u16 vid, int port,
2010 struct switchdev_obj *obj,
2011 int (*cb)(struct switchdev_obj *obj))
74b6ba0d 2012{
dabc1a96 2013 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 2014 int err;
2015
dabc1a96
VD		 2016 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2017 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 2018
2019 do {
dabc1a96 2020 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 2021 if (err)
83dabd1f 2022 return err;
74b6ba0d
VD		 2023
2024 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2025 break;
2026
01bd96c8 2027 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 2028 continue;
2029
2030 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2031 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2032
83dabd1f
VD		 2033 if (!is_unicast_ether_addr(addr.mac))
2034 continue;
2035
2036 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2037 fdb->vid = vid;
2038 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2039 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2040 fdb->ndm_state = NUD_NOARP;
2041 else
2042 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2043 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2044 struct switchdev_obj_port_mdb *mdb;
2045
2046 if (!is_multicast_ether_addr(addr.mac))
2047 continue;
2048
2049 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2050 mdb->vid = vid;
2051 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2052 } else {
2053 return -EOPNOTSUPP;
74b6ba0d 2054 }
83dabd1f
VD		 2055
2056 err = cb(obj);
2057 if (err)
2058 return err;
74b6ba0d
VD		 2059 } while (!is_broadcast_ether_addr(addr.mac));
2060
2061 return err;
2062}
2063
83dabd1f
VD		 2064static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2065 struct switchdev_obj *obj,
2066 int (*cb)(struct switchdev_obj *obj))
f33475bd 2067{
b4e47c0f 2068 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 2069 .vid = chip->info->max_vid,
f33475bd 2070 };
2db9ce1f 2071 u16 fid;
f33475bd
VD		 2072 int err;
2073
2db9ce1f 2074 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2075 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2076 if (err)
83dabd1f 2077 return err;
2db9ce1f 2078
83dabd1f 2079 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2080 if (err)
83dabd1f 2081 return err;
2db9ce1f 2082
74b6ba0d 2083 /* Dump VLANs' Filtering Information Databases */
fad09c73 2084 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2085 if (err)
83dabd1f 2086 return err;
f33475bd
VD		 2087
2088 do {
fad09c73 2089 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2090 if (err)
83dabd1f 2091 return err;
f33475bd
VD		 2092
2093 if (!vlan.valid)
2094 break;
2095
83dabd1f
VD		 2096 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2097 obj, cb);
f33475bd 2098 if (err)
83dabd1f 2099 return err;
3cf3c846 2100 } while (vlan.vid < chip->info->max_vid);
f33475bd 2101
83dabd1f
VD		 2102 return err;
2103}
2104
2105static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2106 struct switchdev_obj_port_fdb *fdb,
2107 int (*cb)(struct switchdev_obj *obj))
2108{
04bed143 2109 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2110 int err;
2111
2112 mutex_lock(&chip->reg_lock);
2113 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2114 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2115
2116 return err;
2117}
2118
240ea3ef
VD		 2119static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2120 struct net_device *br)
e79a8bcb 2121{
e96a6e02 2122 struct dsa_switch *ds;
240ea3ef 2123 int port;
e96a6e02 2124 int dev;
240ea3ef 2125 int err;
466dfa07 2126
240ea3ef
VD		 2127 /* Remap the Port VLAN of each local bridge group member */
2128 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
2129 if (chip->ds->ports[port].bridge_dev == br) {
2130 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 2131 if (err)
240ea3ef 2132 return err;
b7666efe
VD		 2133 }
2134 }
2135
e96a6e02
VD		 2136 if (!mv88e6xxx_has_pvt(chip))
2137 return 0;
2138
2139 /* Remap the Port VLAN of each cross-chip bridge group member */
2140 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
2141 ds = chip->ds->dst->ds[dev];
2142 if (!ds)
2143 break;
2144
2145 for (port = 0; port < ds->num_ports; ++port) {
2146 if (ds->ports[port].bridge_dev == br) {
2147 err = mv88e6xxx_pvt_map(chip, dev, port);
2148 if (err)
2149 return err;
2150 }
2151 }
2152 }
2153
240ea3ef
VD		 2154 return 0;
2155}
2156
2157static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2158 struct net_device *br)
2159{
2160 struct mv88e6xxx_chip *chip = ds->priv;
2161 int err;
2162
2163 mutex_lock(&chip->reg_lock);
2164 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 2165 mutex_unlock(&chip->reg_lock);
a6692754 2166
466dfa07 2167 return err;
e79a8bcb
VD		 2168}
2169
f123f2fb
VD		 2170static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2171 struct net_device *br)
66d9cd0f 2172{
04bed143 2173 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 2174
fad09c73 2175 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 2176 if (mv88e6xxx_bridge_map(chip, br) ||
2177 mv88e6xxx_port_vlan_map(chip, port))
2178 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 2179 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2180}
2181
aec5ac88
VD		 2182static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2183 int port, struct net_device *br)
2184{
2185 struct mv88e6xxx_chip *chip = ds->priv;
2186 int err;
2187
2188 if (!mv88e6xxx_has_pvt(chip))
2189 return 0;
2190
2191 mutex_lock(&chip->reg_lock);
2192 err = mv88e6xxx_pvt_map(chip, dev, port);
2193 mutex_unlock(&chip->reg_lock);
2194
2195 return err;
2196}
2197
2198static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2199 int port, struct net_device *br)
2200{
2201 struct mv88e6xxx_chip *chip = ds->priv;
2202
2203 if (!mv88e6xxx_has_pvt(chip))
2204 return;
2205
2206 mutex_lock(&chip->reg_lock);
2207 if (mv88e6xxx_pvt_map(chip, dev, port))
2208 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2209 mutex_unlock(&chip->reg_lock);
2210}
2211
17e708ba
VD		 2212static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2213{
2214 if (chip->info->ops->reset)
2215 return chip->info->ops->reset(chip);
2216
2217 return 0;
2218}
2219
309eca6d
VD		 2220static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2221{
2222 struct gpio_desc *gpiod = chip->reset;
2223
2224 /* If there is a GPIO connected to the reset pin, toggle it */
2225 if (gpiod) {
2226 gpiod_set_value_cansleep(gpiod, 1);
2227 usleep_range(10000, 20000);
2228 gpiod_set_value_cansleep(gpiod, 0);
2229 usleep_range(10000, 20000);
2230 }
2231}
2232
4ac4b5a6 2233static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2234{
4ac4b5a6 2235 int i, err;
552238b5 2236
4ac4b5a6 2237 /* Set all ports to the Disabled state */
370b4ffb 2238 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2239 err = mv88e6xxx_port_set_state(chip, i,
2240 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2241 if (err)
2242 return err;
552238b5
VD		 2243 }
2244
4ac4b5a6
VD		 2245 /* Wait for transmit queues to drain,
2246 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2247 */
552238b5
VD		 2248 usleep_range(2000, 4000);
2249
4ac4b5a6
VD		 2250 return 0;
2251}
2252
2253static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2254{
4ac4b5a6
VD		 2255 int err;
2256
2257 err = mv88e6xxx_disable_ports(chip);
2258 if (err)
2259 return err;
2260
309eca6d 2261 mv88e6xxx_hardware_reset(chip);
552238b5 2262
17e708ba 2263 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2264}
2265
09cb7dfd 2266static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2267{
09cb7dfd
VD		 2268 u16 val;
2269 int err;
13a7ebb3 2270
09cb7dfd
VD		 2271 /* Clear Power Down bit */
2272 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2273 if (err)
2274 return err;
13a7ebb3 2275
09cb7dfd
VD		 2276 if (val & BMCR_PDOWN) {
2277 val &= ~BMCR_PDOWN;
2278 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2279 }
2280
09cb7dfd 2281 return err;
13a7ebb3
PU		 2282}
2283
4314557c
VD		 2284static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2285 enum mv88e6xxx_frame_mode frame, u16 egress,
2286 u16 etype)
56995cbc
AL		 2287{
2288 int err;
2289
4314557c
VD		 2290 if (!chip->info->ops->port_set_frame_mode)
2291 return -EOPNOTSUPP;
2292
2293 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 2294 if (err)
2295 return err;
2296
4314557c
VD		 2297 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2298 if (err)
2299 return err;
2300
2301 if (chip->info->ops->port_set_ether_type)
2302 return chip->info->ops->port_set_ether_type(chip, port, etype);
2303
2304 return 0;
56995cbc
AL		 2305}
2306
4314557c 2307static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 2308{
4314557c
VD		 2309 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2310 PORT_CONTROL_EGRESS_UNMODIFIED,
2311 PORT_ETH_TYPE_DEFAULT);
2312}
56995cbc 2313
4314557c
VD		 2314static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2315{
2316 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2317 PORT_CONTROL_EGRESS_UNMODIFIED,
2318 PORT_ETH_TYPE_DEFAULT);
2319}
56995cbc 2320
4314557c
VD		 2321static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2322{
2323 return mv88e6xxx_set_port_mode(chip, port,
2324 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2325 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2326}
56995cbc 2327
4314557c
VD		 2328static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2329{
2330 if (dsa_is_dsa_port(chip->ds, port))
2331 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2332
4314557c
VD		 2333 if (dsa_is_normal_port(chip->ds, port))
2334 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 2335
4314557c
VD		 2336 /* Setup CPU port mode depending on its supported tag format */
2337 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2338 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2339
4314557c
VD		 2340 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2341 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 2342
4314557c 2343 return -EINVAL;
56995cbc
AL		 2344}
2345
601aeed3 2346static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 2347{
601aeed3 2348 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 2349
601aeed3 2350 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 2351}
56995cbc 2352
601aeed3 2353static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 2354{
601aeed3 2355 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 2356
601aeed3
VD		 2357 /* Upstream ports flood frames with unknown unicast or multicast DA */
2358 if (chip->info->ops->port_set_egress_floods)
2359 return chip->info->ops->port_set_egress_floods(chip, port,
2360 flood, flood);
ea698f4f 2361
601aeed3 2362 return 0;
ea698f4f
VD		 2363}
2364
fad09c73 2365static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2366{
fad09c73 2367 struct dsa_switch *ds = chip->ds;
0e7b9925 2368 int err;
54d792f2 2369 u16 reg;
d827e88a 2370
d78343d2
VD		 2371 /* MAC Forcing register: don't force link, speed, duplex or flow control
2372 * state to any particular values on physical ports, but force the CPU
2373 * port and all DSA ports to their maximum bandwidth and full duplex.
2374 */
2375 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2376 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2377 SPEED_MAX, DUPLEX_FULL,
2378 PHY_INTERFACE_MODE_NA);
2379 else
2380 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2381 SPEED_UNFORCED, DUPLEX_UNFORCED,
2382 PHY_INTERFACE_MODE_NA);
2383 if (err)
2384 return err;
54d792f2
AL		 2385
2386 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2387 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2388 * tunneling, determine priority by looking at 802.1p and IP
2389 * priority fields (IP prio has precedence), and set STP state
2390 * to Forwarding.
2391 *
2392 * If this is the CPU link, use DSA or EDSA tagging depending
2393 * on which tagging mode was configured.
2394 *
2395 * If this is a link to another switch, use DSA tagging mode.
2396 *
2397 * If this is the upstream port for this switch, enable
2398 * forwarding of unknown unicasts and multicasts.
2399 */
56995cbc 2400 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2401 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2402 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2403 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2404 if (err)
2405 return err;
6083ce71 2406
601aeed3 2407 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 2408 if (err)
2409 return err;
54d792f2 2410
601aeed3 2411 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 2412 if (err)
2413 return err;
2414
13a7ebb3
PU		 2415 /* If this port is connected to a SerDes, make sure the SerDes is not
2416 * powered down.
2417 */
09cb7dfd 2418 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2419 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2420 if (err)
2421 return err;
2422 reg &= PORT_STATUS_CMODE_MASK;
2423 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2424 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2425 (reg == PORT_STATUS_CMODE_SGMII)) {
2426 err = mv88e6xxx_serdes_power_on(chip);
2427 if (err < 0)
2428 return err;
13a7ebb3
PU		 2429 }
2430 }
2431
8efdda4a 2432 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2433 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2434 * untagged frames on this port, do a destination address lookup on all
2435 * received packets as usual, disable ARP mirroring and don't send a
2436 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2437 */
a23b2961
AL		 2438 err = mv88e6xxx_port_set_map_da(chip, port);
2439 if (err)
2440 return err;
8efdda4a 2441
a23b2961
AL		 2442 reg = 0;
2443 if (chip->info->ops->port_set_upstream_port) {
2444 err = chip->info->ops->port_set_upstream_port(
2445 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 2446 if (err)
2447 return err;
54d792f2
AL		 2448 }
2449
a23b2961
AL		 2450 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2451 PORT_CONTROL_2_8021Q_DISABLED);
2452 if (err)
2453 return err;
2454
5f436666
AL		 2455 if (chip->info->ops->port_jumbo_config) {
2456 err = chip->info->ops->port_jumbo_config(chip, port);
2457 if (err)
2458 return err;
2459 }
2460
54d792f2
AL		 2461 /* Port Association Vector: when learning source addresses
2462 * of packets, add the address to the address database using
2463 * a port bitmap that has only the bit for this port set and
2464 * the other bits clear.
2465 */
4c7ea3c0 2466 reg = 1 << port;
996ecb82
VD		 2467 /* Disable learning for CPU port */
2468 if (dsa_is_cpu_port(ds, port))
65fa4027 2469 reg = 0;
4c7ea3c0 2470
0e7b9925
AL		 2471 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2472 if (err)
2473 return err;
54d792f2
AL		 2474
2475 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2476 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2477 if (err)
2478 return err;
54d792f2 2479
b35d322a
AL		 2480 if (chip->info->ops->port_pause_config) {
2481 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2482 if (err)
2483 return err;
b35d322a 2484 }
54d792f2 2485
c8c94891
VD		 2486 if (chip->info->ops->port_disable_learn_limit) {
2487 err = chip->info->ops->port_disable_learn_limit(chip, port);
2488 if (err)
2489 return err;
2490 }
2491
9dbfb4e1
VD		 2492 if (chip->info->ops->port_disable_pri_override) {
2493 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 2494 if (err)
2495 return err;
ef0a7318 2496 }
2bbb33be 2497
ef0a7318
AL		 2498 if (chip->info->ops->port_tag_remap) {
2499 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2500 if (err)
2501 return err;
54d792f2
AL		 2502 }
2503
ef70b111
AL		 2504 if (chip->info->ops->port_egress_rate_limiting) {
2505 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2506 if (err)
2507 return err;
54d792f2
AL		 2508 }
2509
ea698f4f 2510 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 2511 if (err)
2512 return err;
d827e88a 2513
207afda1 2514 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2515 * database, and allow bidirectional communication between the
2516 * CPU and DSA port(s), and the other ports.
d827e88a 2517 */
b4e48c50 2518 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2519 if (err)
2520 return err;
2db9ce1f 2521
240ea3ef 2522 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 2523 if (err)
2524 return err;
d827e88a
GR		 2525
2526 /* Default VLAN ID and priority: don't set a default VLAN
2527 * ID, and set the default packet priority to zero.
2528 */
0e7b9925 2529 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2530}
2531
aa0938c6 2532static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2533{
2534 int err;
2535
a935c052 2536 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2537 if (err)
2538 return err;
2539
a935c052 2540 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2541 if (err)
2542 return err;
2543
a935c052
VD		 2544 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2545 if (err)
2546 return err;
2547
2548 return 0;
3b4caa1b
VD		 2549}
2550
2cfcd964
VD		 2551static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2552 unsigned int ageing_time)
2553{
04bed143 2554 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2555 int err;
2556
2557 mutex_lock(&chip->reg_lock);
720c6343 2558 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2559 mutex_unlock(&chip->reg_lock);
2560
2561 return err;
2562}
2563
9729934c 2564static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2565{
fad09c73 2566 struct dsa_switch *ds = chip->ds;
b0745e87 2567 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2568 int err;
54d792f2 2569
119477bd
VD		 2570 /* Enable the PHY Polling Unit if present, don't discard any packets,
2571 * and mask all interrupt sources.
2572 */
a199d8b6 2573 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2574 if (err)
2575 return err;
2576
33641994
AL		 2577 if (chip->info->ops->g1_set_cpu_port) {
2578 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2579 if (err)
2580 return err;
2581 }
2582
2583 if (chip->info->ops->g1_set_egress_port) {
2584 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2585 if (err)
2586 return err;
2587 }
b0745e87 2588
50484ff4 2589 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2590 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2591 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2592 (ds->index & 0x1f));
50484ff4
VD		 2593 if (err)
2594 return err;
2595
54d792f2 2596 /* Configure the IP ToS mapping registers. */
a935c052 2597 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2598 if (err)
08a01261 2599 return err;
a935c052 2600 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2601 if (err)
08a01261 2602 return err;
a935c052 2603 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2604 if (err)
08a01261 2605 return err;
a935c052 2606 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2607 if (err)
08a01261 2608 return err;
a935c052 2609 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2610 if (err)
08a01261 2611 return err;
a935c052 2612 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2613 if (err)
08a01261 2614 return err;
a935c052 2615 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2616 if (err)
08a01261 2617 return err;
a935c052 2618 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2619 if (err)
08a01261 2620 return err;
54d792f2
AL		 2621
2622 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2623 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2624 if (err)
08a01261 2625 return err;
54d792f2 2626
de227387
AL		 2627 /* Initialize the statistics unit */
2628 err = mv88e6xxx_stats_set_histogram(chip);
2629 if (err)
2630 return err;
2631
9729934c 2632 /* Clear the statistics counters for all ports */
a935c052
VD		 2633 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2634 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2635 if (err)
2636 return err;
2637
2638 /* Wait for the flush to complete. */
7f9ef3af 2639 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2640 if (err)
2641 return err;
2642
2643 return 0;
2644}
2645
f81ec90f 2646static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2647{
04bed143 2648 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2649 int err;
a1a6a4d1
VD		 2650 int i;
2651
fad09c73 2652 chip->ds = ds;
a3c53be5 2653 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2654
fad09c73 2655 mutex_lock(&chip->reg_lock);
08a01261 2656
9729934c 2657 /* Setup Switch Port Registers */
370b4ffb 2658 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2659 err = mv88e6xxx_setup_port(chip, i);
2660 if (err)
2661 goto unlock;
2662 }
2663
2664 /* Setup Switch Global 1 Registers */
2665 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2666 if (err)
2667 goto unlock;
2668
9729934c
VD		 2669 /* Setup Switch Global 2 Registers */
2670 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2671 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2672 if (err)
2673 goto unlock;
2674 }
08a01261 2675
b486d7c9
VD		 2676 err = mv88e6xxx_vtu_setup(chip);
2677 if (err)
2678 goto unlock;
2679
81228996
VD		 2680 err = mv88e6xxx_pvt_setup(chip);
2681 if (err)
2682 goto unlock;
2683
a2ac29d2
VD		 2684 err = mv88e6xxx_atu_setup(chip);
2685 if (err)
2686 goto unlock;
2687
6e55f698
AL		 2688 /* Some generations have the configuration of sending reserved
2689 * management frames to the CPU in global2, others in
2690 * global1. Hence it does not fit the two setup functions
2691 * above.
2692 */
2693 if (chip->info->ops->mgmt_rsvd2cpu) {
2694 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2695 if (err)
2696 goto unlock;
2697 }
2698
6b17e864 2699unlock:
fad09c73 2700 mutex_unlock(&chip->reg_lock);
db687a56 2701
48ace4ef 2702 return err;
54d792f2
AL		 2703}
2704
3b4caa1b
VD		 2705static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2706{
04bed143 2707 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2708 int err;
2709
b073d4e2
VD		 2710 if (!chip->info->ops->set_switch_mac)
2711 return -EOPNOTSUPP;
3b4caa1b 2712
b073d4e2
VD		 2713 mutex_lock(&chip->reg_lock);
2714 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2715 mutex_unlock(&chip->reg_lock);
2716
2717 return err;
2718}
2719
e57e5e77 2720static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2721{
0dd12d54
AL		 2722 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2723 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2724 u16 val;
2725 int err;
fd3a0ee4 2726
ee26a228
AL		 2727 if (!chip->info->ops->phy_read)
2728 return -EOPNOTSUPP;
2729
fad09c73 2730 mutex_lock(&chip->reg_lock);
ee26a228 2731 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2732 mutex_unlock(&chip->reg_lock);
e57e5e77 2733
da9f3301
AL		 2734 if (reg == MII_PHYSID2) {
2735 /* Some internal PHYS don't have a model number. Use
2736 * the mv88e6390 family model number instead.
2737 */
2738 if (!(val & 0x3f0))
2739 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2740 }
2741
e57e5e77 2742 return err ? err : val;
fd3a0ee4
AL		 2743}
2744
e57e5e77 2745static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2746{
0dd12d54
AL		 2747 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2748 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2749 int err;
fd3a0ee4 2750
ee26a228
AL		 2751 if (!chip->info->ops->phy_write)
2752 return -EOPNOTSUPP;
2753
fad09c73 2754 mutex_lock(&chip->reg_lock);
ee26a228 2755 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2756 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2757
2758 return err;
fd3a0ee4
AL		 2759}
2760
fad09c73 2761static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2762 struct device_node *np,
2763 bool external)
b516d453
AL		 2764{
2765 static int index;
0dd12d54 2766 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2767 struct mii_bus *bus;
2768 int err;
2769
0dd12d54 2770 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2771 if (!bus)
2772 return -ENOMEM;
2773
0dd12d54 2774 mdio_bus = bus->priv;
a3c53be5 2775 mdio_bus->bus = bus;
0dd12d54 2776 mdio_bus->chip = chip;
a3c53be5
AL		 2777 INIT_LIST_HEAD(&mdio_bus->list);
2778 mdio_bus->external = external;
0dd12d54 2779
b516d453
AL		 2780 if (np) {
2781 bus->name = np->full_name;
2782 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2783 } else {
2784 bus->name = "mv88e6xxx SMI";
2785 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2786 }
2787
2788 bus->read = mv88e6xxx_mdio_read;
2789 bus->write = mv88e6xxx_mdio_write;
fad09c73 2790 bus->parent = chip->dev;
b516d453 2791
a3c53be5
AL		 2792 if (np)
2793 err = of_mdiobus_register(bus, np);
b516d453
AL		 2794 else
2795 err = mdiobus_register(bus);
2796 if (err) {
fad09c73 2797 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2798 return err;
b516d453 2799 }
a3c53be5
AL		 2800
2801 if (external)
2802 list_add_tail(&mdio_bus->list, &chip->mdios);
2803 else
2804 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2805
2806 return 0;
a3c53be5 2807}
b516d453 2808
a3c53be5
AL		 2809static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2810 { .compatible = "marvell,mv88e6xxx-mdio-external",
2811 .data = (void *)true },
2812 { },
2813};
b516d453 2814
a3c53be5
AL		 2815static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2816 struct device_node *np)
2817{
2818 const struct of_device_id *match;
2819 struct device_node *child;
2820 int err;
2821
2822 /* Always register one mdio bus for the internal/default mdio
2823 * bus. This maybe represented in the device tree, but is
2824 * optional.
2825 */
2826 child = of_get_child_by_name(np, "mdio");
2827 err = mv88e6xxx_mdio_register(chip, child, false);
2828 if (err)
2829 return err;
2830
2831 /* Walk the device tree, and see if there are any other nodes
2832 * which say they are compatible with the external mdio
2833 * bus.
2834 */
2835 for_each_available_child_of_node(np, child) {
2836 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2837 if (match) {
2838 err = mv88e6xxx_mdio_register(chip, child, true);
2839 if (err)
2840 return err;
2841 }
2842 }
2843
2844 return 0;
b516d453
AL		 2845}
2846
a3c53be5 2847static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2848
2849{
a3c53be5
AL		 2850 struct mv88e6xxx_mdio_bus *mdio_bus;
2851 struct mii_bus *bus;
b516d453 2852
a3c53be5
AL		 2853 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2854 bus = mdio_bus->bus;
b516d453 2855
a3c53be5
AL		 2856 mdiobus_unregister(bus);
2857 }
b516d453
AL		 2858}
2859
855b1932
VD		 2860static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2861{
04bed143 2862 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2863
2864 return chip->eeprom_len;
2865}
2866
855b1932
VD		 2867static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2868 struct ethtool_eeprom *eeprom, u8 *data)
2869{
04bed143 2870 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2871 int err;
2872
ee4dc2e7
VD		 2873 if (!chip->info->ops->get_eeprom)
2874 return -EOPNOTSUPP;
855b1932 2875
ee4dc2e7
VD		 2876 mutex_lock(&chip->reg_lock);
2877 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2878 mutex_unlock(&chip->reg_lock);
2879
2880 if (err)
2881 return err;
2882
2883 eeprom->magic = 0xc3ec4951;
2884
2885 return 0;
2886}
2887
855b1932
VD		 2888static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2889 struct ethtool_eeprom *eeprom, u8 *data)
2890{
04bed143 2891 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2892 int err;
2893
ee4dc2e7
VD		 2894 if (!chip->info->ops->set_eeprom)
2895 return -EOPNOTSUPP;
2896
855b1932
VD		 2897 if (eeprom->magic != 0xc3ec4951)
2898 return -EINVAL;
2899
2900 mutex_lock(&chip->reg_lock);
ee4dc2e7 2901 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2902 mutex_unlock(&chip->reg_lock);
2903
2904 return err;
2905}
2906
b3469dd8 2907static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2908 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 2909 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2910 .phy_read = mv88e6xxx_phy_ppu_read,
2911 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2912 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2913 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2914 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2915 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2916 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2917 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2918 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2919 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 2920 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2921 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2922 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2923 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2924 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2925 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2926 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2927 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2928 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2929 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2930 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2931 .ppu_enable = mv88e6185_g1_ppu_enable,
2932 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2933 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2934};
2935
2936static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2937 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2938 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 2939 .phy_read = mv88e6xxx_phy_ppu_read,
2940 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 2941 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2942 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2943 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2944 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2945 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2946 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2947 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2948 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2949 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2950 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 2951 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2952 .ppu_enable = mv88e6185_g1_ppu_enable,
2953 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2954 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 2955};
2956
7d381a02 2957static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2958 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 2959 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2960 .phy_read = mv88e6xxx_g2_smi_phy_read,
2961 .phy_write = mv88e6xxx_g2_smi_phy_write,
2962 .port_set_link = mv88e6xxx_port_set_link,
2963 .port_set_duplex = mv88e6xxx_port_set_duplex,
2964 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2965 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2966 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2967 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2968 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 2969 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 2970 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 2971 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 2972 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2973 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2974 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2975 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2976 .stats_get_strings = mv88e6095_stats_get_strings,
2977 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 2978 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2979 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2980 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2981 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2982 .reset = mv88e6352_g1_reset,
7d381a02
SE		 2983};
2984
b3469dd8 2985static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2986 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2987 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2988 .phy_read = mv88e6165_phy_read,
2989 .phy_write = mv88e6165_phy_write,
08ef7f10 2990 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2991 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2992 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2993 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2994 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2995 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2996 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2997 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2998 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2999 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3000 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3001 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3002 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3003 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3004 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3005 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3006};
3007
3008static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3009 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3010 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3011 .phy_read = mv88e6xxx_phy_ppu_read,
3012 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3013 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3014 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3015 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3016 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3017 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3018 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 3019 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 3020 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
5f436666 3021 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3022 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3023 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3024 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3025 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3026 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3027 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3028 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3029 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3030 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3031 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3032 .ppu_enable = mv88e6185_g1_ppu_enable,
3033 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3034 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3035};
3036
990e27b0
VD		 3037static const struct mv88e6xxx_ops mv88e6141_ops = {
3038 /* MV88E6XXX_FAMILY_6341 */
3039 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3040 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3042 .phy_read = mv88e6xxx_g2_smi_phy_read,
3043 .phy_write = mv88e6xxx_g2_smi_phy_write,
3044 .port_set_link = mv88e6xxx_port_set_link,
3045 .port_set_duplex = mv88e6xxx_port_set_duplex,
3046 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3047 .port_set_speed = mv88e6390_port_set_speed,
3048 .port_tag_remap = mv88e6095_port_tag_remap,
3049 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3050 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3051 .port_set_ether_type = mv88e6351_port_set_ether_type,
3052 .port_jumbo_config = mv88e6165_port_jumbo_config,
3053 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3054 .port_pause_config = mv88e6097_port_pause_config,
3055 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3056 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3057 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3058 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3059 .stats_get_strings = mv88e6320_stats_get_strings,
3060 .stats_get_stats = mv88e6390_stats_get_stats,
3061 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3062 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3063 .watchdog_ops = &mv88e6390_watchdog_ops,
3064 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3065 .reset = mv88e6352_g1_reset,
3066};
3067
b3469dd8 3068static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3069 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3070 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3071 .phy_read = mv88e6165_phy_read,
3072 .phy_write = mv88e6165_phy_write,
08ef7f10 3073 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3074 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3075 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3076 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3077 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3078 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3079 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3080 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3081 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3082 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3085 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3086 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3087 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3088 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3089 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3090 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3091 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3092 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3093 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3094};
3095
3096static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3097 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3098 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3099 .phy_read = mv88e6165_phy_read,
3100 .phy_write = mv88e6165_phy_write,
08ef7f10 3101 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3102 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3103 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 3104 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3105 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3106 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3107 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3108 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3109 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3110 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3111 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3112 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3113 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3114 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3115};
3116
3117static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3118 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3119 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3120 .phy_read = mv88e6xxx_g2_smi_phy_read,
3121 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3122 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3123 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3124 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3125 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3126 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3127 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3128 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3129 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3130 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3131 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3132 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3133 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3134 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3135 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3136 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3137 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3138 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3139 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3140 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3141 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3142 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3143 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3144};
3145
3146static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3147 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3148 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3149 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3150 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3151 .phy_read = mv88e6xxx_g2_smi_phy_read,
3152 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3153 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3154 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3155 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3156 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3157 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3158 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3159 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3160 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3161 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3162 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3163 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3164 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3165 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3166 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3167 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3168 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3169 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3170 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3171 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3172 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3173 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3174 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3175};
3176
3177static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3178 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3179 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3180 .phy_read = mv88e6xxx_g2_smi_phy_read,
3181 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3182 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3183 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3184 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3185 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3186 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3187 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3188 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3189 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3190 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3191 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3192 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3193 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3194 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3195 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3196 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3197 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3198 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3199 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3200 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3201 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3202 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3203 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3204};
3205
3206static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3207 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3208 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3209 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3210 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3211 .phy_read = mv88e6xxx_g2_smi_phy_read,
3212 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3213 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3214 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3215 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3216 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3217 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3218 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3219 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3220 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3221 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3222 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3223 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3224 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3225 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3226 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3227 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3228 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3229 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3230 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3231 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3232 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3233 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3234 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3235};
3236
3237static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3238 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3239 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3240 .phy_read = mv88e6xxx_phy_ppu_read,
3241 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3242 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3243 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3244 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3245 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 3246 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 3247 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 3248 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3249 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3250 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3251 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3252 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3253 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3254 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3255 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3256 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3257 .ppu_enable = mv88e6185_g1_ppu_enable,
3258 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3259 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3260};
3261
1a3b39ec 3262static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3263 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3264 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3265 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3266 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3267 .phy_read = mv88e6xxx_g2_smi_phy_read,
3268 .phy_write = mv88e6xxx_g2_smi_phy_write,
3269 .port_set_link = mv88e6xxx_port_set_link,
3270 .port_set_duplex = mv88e6xxx_port_set_duplex,
3271 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3272 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3273 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3274 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3275 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3276 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3277 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3278 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3279 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3280 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3281 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3282 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3283 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3284 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3285 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3286 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3287 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3288 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3289 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3290};
3291
3292static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3293 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3294 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3295 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3296 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3297 .phy_read = mv88e6xxx_g2_smi_phy_read,
3298 .phy_write = mv88e6xxx_g2_smi_phy_write,
3299 .port_set_link = mv88e6xxx_port_set_link,
3300 .port_set_duplex = mv88e6xxx_port_set_duplex,
3301 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3302 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3303 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3304 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3305 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3306 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3307 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3308 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3309 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3310 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3311 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3312 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3313 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3314 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3315 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3316 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3317 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3318 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3319 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3320};
3321
3322static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3323 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3324 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3325 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3326 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3327 .phy_read = mv88e6xxx_g2_smi_phy_read,
3328 .phy_write = mv88e6xxx_g2_smi_phy_write,
3329 .port_set_link = mv88e6xxx_port_set_link,
3330 .port_set_duplex = mv88e6xxx_port_set_duplex,
3331 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3332 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3333 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3334 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3335 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3336 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3337 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3338 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3339 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3340 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3341 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3342 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3343 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3344 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3345 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3346 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3347 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3348 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3349 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3350};
3351
b3469dd8 3352static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3353 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3354 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3355 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3356 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3357 .phy_read = mv88e6xxx_g2_smi_phy_read,
3358 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3359 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3360 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3361 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3362 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3363 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3364 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3365 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3366 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3367 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3368 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3369 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3370 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3371 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3372 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3373 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3374 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3375 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3376 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3377 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3378 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3379 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3380 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3381};
3382
1a3b39ec 3383static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3384 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3385 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3386 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3387 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3388 .phy_read = mv88e6xxx_g2_smi_phy_read,
3389 .phy_write = mv88e6xxx_g2_smi_phy_write,
3390 .port_set_link = mv88e6xxx_port_set_link,
3391 .port_set_duplex = mv88e6xxx_port_set_duplex,
3392 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3393 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3394 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3395 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3396 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3397 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3398 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3399 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3400 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3401 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3402 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3403 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3404 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3405 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3406 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3407 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3408 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3409 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3410 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3411 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3412};
3413
b3469dd8 3414static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3415 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3416 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3417 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3418 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3419 .phy_read = mv88e6xxx_g2_smi_phy_read,
3420 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3421 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3422 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3423 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3424 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3425 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3426 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3427 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3428 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3429 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3430 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3431 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3432 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3433 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3434 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3435 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3436 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3437 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3438 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3439 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3440 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3441};
3442
3443static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3444 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3445 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3446 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3447 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3448 .phy_read = mv88e6xxx_g2_smi_phy_read,
3449 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3450 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3451 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3452 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3453 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3454 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3455 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3456 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3457 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3459 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3462 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3463 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3464 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3465 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3466 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3467 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3468 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3469};
3470
16e329ae
VD		 3471static const struct mv88e6xxx_ops mv88e6341_ops = {
3472 /* MV88E6XXX_FAMILY_6341 */
3473 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3474 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3475 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3476 .phy_read = mv88e6xxx_g2_smi_phy_read,
3477 .phy_write = mv88e6xxx_g2_smi_phy_write,
3478 .port_set_link = mv88e6xxx_port_set_link,
3479 .port_set_duplex = mv88e6xxx_port_set_duplex,
3480 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3481 .port_set_speed = mv88e6390_port_set_speed,
3482 .port_tag_remap = mv88e6095_port_tag_remap,
3483 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3484 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3485 .port_set_ether_type = mv88e6351_port_set_ether_type,
3486 .port_jumbo_config = mv88e6165_port_jumbo_config,
3487 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3488 .port_pause_config = mv88e6097_port_pause_config,
3489 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3490 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3491 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3492 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3493 .stats_get_strings = mv88e6320_stats_get_strings,
3494 .stats_get_stats = mv88e6390_stats_get_stats,
3495 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3496 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3497 .watchdog_ops = &mv88e6390_watchdog_ops,
3498 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3499 .reset = mv88e6352_g1_reset,
3500};
3501
b3469dd8 3502static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3503 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3504 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3505 .phy_read = mv88e6xxx_g2_smi_phy_read,
3506 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3507 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3508 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3509 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3510 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3511 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3512 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3513 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3514 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3515 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3516 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3517 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3518 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3519 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3520 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3521 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3522 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3523 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3524 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3525 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3526 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3527 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3528 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3529};
3530
3531static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3532 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3534 .phy_read = mv88e6xxx_g2_smi_phy_read,
3535 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3536 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3537 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3538 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3539 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3540 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3542 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3543 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3544 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3545 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3546 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3547 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3548 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3549 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3550 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3551 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3552 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3553 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3554 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3555 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3556 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3557 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3558};
3559
3560static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3561 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3562 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3563 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3564 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3565 .phy_read = mv88e6xxx_g2_smi_phy_read,
3566 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3567 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3568 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3569 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3570 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3571 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3572 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3573 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3574 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3575 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3576 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3577 .port_pause_config = mv88e6097_port_pause_config,
c8c94891 3578 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3579 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3580 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3581 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3582 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3583 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3584 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3585 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3586 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3587 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3588 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3589};
3590
1a3b39ec 3591static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3592 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3593 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3594 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3595 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3596 .phy_read = mv88e6xxx_g2_smi_phy_read,
3597 .phy_write = mv88e6xxx_g2_smi_phy_write,
3598 .port_set_link = mv88e6xxx_port_set_link,
3599 .port_set_duplex = mv88e6xxx_port_set_duplex,
3600 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3601 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3602 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3603 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3604 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3605 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3606 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3607 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3608 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3609 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3610 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3611 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3612 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3613 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3614 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3615 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3616 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3617 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3618 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3619 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3620 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3621 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3622};
3623
3624static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3625 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3626 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3627 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3628 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3629 .phy_read = mv88e6xxx_g2_smi_phy_read,
3630 .phy_write = mv88e6xxx_g2_smi_phy_write,
3631 .port_set_link = mv88e6xxx_port_set_link,
3632 .port_set_duplex = mv88e6xxx_port_set_duplex,
3633 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3634 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3635 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3636 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3637 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3638 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3639 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3640 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3641 .port_pause_config = mv88e6390_port_pause_config,
c8c94891 3642 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3643 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3644 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3645 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3646 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3647 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3648 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3649 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3650 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3651 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3652 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3653 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3654};
3655
f81ec90f
VD		 3656static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3657 [MV88E6085] = {
3658 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3659 .family = MV88E6XXX_FAMILY_6097,
3660 .name = "Marvell 88E6085",
3661 .num_databases = 4096,
3662 .num_ports = 10,
3cf3c846 3663 .max_vid = 4095,
9dddd478 3664 .port_base_addr = 0x10,
a935c052 3665 .global1_addr = 0x1b,
acddbd21 3666 .age_time_coeff = 15000,
dc30c35b 3667 .g1_irqs = 8,
e606ca36 3668 .atu_move_port_mask = 0xf,
f3645652 3669 .pvt = true,
443d5a1b 3670 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3671 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3672 .ops = &mv88e6085_ops,
f81ec90f
VD		 3673 },
3674
3675 [MV88E6095] = {
3676 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3677 .family = MV88E6XXX_FAMILY_6095,
3678 .name = "Marvell 88E6095/88E6095F",
3679 .num_databases = 256,
3680 .num_ports = 11,
3cf3c846 3681 .max_vid = 4095,
9dddd478 3682 .port_base_addr = 0x10,
a935c052 3683 .global1_addr = 0x1b,
acddbd21 3684 .age_time_coeff = 15000,
dc30c35b 3685 .g1_irqs = 8,
e606ca36 3686 .atu_move_port_mask = 0xf,
443d5a1b 3687 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3688 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3689 .ops = &mv88e6095_ops,
f81ec90f
VD		 3690 },
3691
7d381a02
SE		 3692 [MV88E6097] = {
3693 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3694 .family = MV88E6XXX_FAMILY_6097,
3695 .name = "Marvell 88E6097/88E6097F",
3696 .num_databases = 4096,
3697 .num_ports = 11,
3cf3c846 3698 .max_vid = 4095,
7d381a02
SE		 3699 .port_base_addr = 0x10,
3700 .global1_addr = 0x1b,
3701 .age_time_coeff = 15000,
c534178b 3702 .g1_irqs = 8,
e606ca36 3703 .atu_move_port_mask = 0xf,
f3645652 3704 .pvt = true,
2bfcfcd3 3705 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3706 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3707 .ops = &mv88e6097_ops,
3708 },
3709
f81ec90f
VD		 3710 [MV88E6123] = {
3711 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3712 .family = MV88E6XXX_FAMILY_6165,
3713 .name = "Marvell 88E6123",
3714 .num_databases = 4096,
3715 .num_ports = 3,
3cf3c846 3716 .max_vid = 4095,
9dddd478 3717 .port_base_addr = 0x10,
a935c052 3718 .global1_addr = 0x1b,
acddbd21 3719 .age_time_coeff = 15000,
dc30c35b 3720 .g1_irqs = 9,
e606ca36 3721 .atu_move_port_mask = 0xf,
f3645652 3722 .pvt = true,
443d5a1b 3723 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3724 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3725 .ops = &mv88e6123_ops,
f81ec90f
VD		 3726 },
3727
3728 [MV88E6131] = {
3729 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3730 .family = MV88E6XXX_FAMILY_6185,
3731 .name = "Marvell 88E6131",
3732 .num_databases = 256,
3733 .num_ports = 8,
3cf3c846 3734 .max_vid = 4095,
9dddd478 3735 .port_base_addr = 0x10,
a935c052 3736 .global1_addr = 0x1b,
acddbd21 3737 .age_time_coeff = 15000,
dc30c35b 3738 .g1_irqs = 9,
e606ca36 3739 .atu_move_port_mask = 0xf,
443d5a1b 3740 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3741 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3742 .ops = &mv88e6131_ops,
f81ec90f
VD		 3743 },
3744
990e27b0
VD		 3745 [MV88E6141] = {
3746 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3747 .family = MV88E6XXX_FAMILY_6341,
3748 .name = "Marvell 88E6341",
3749 .num_databases = 4096,
3750 .num_ports = 6,
3cf3c846 3751 .max_vid = 4095,
990e27b0
VD		 3752 .port_base_addr = 0x10,
3753 .global1_addr = 0x1b,
3754 .age_time_coeff = 3750,
3755 .atu_move_port_mask = 0x1f,
f3645652 3756 .pvt = true,
990e27b0
VD		 3757 .tag_protocol = DSA_TAG_PROTO_EDSA,
3758 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3759 .ops = &mv88e6141_ops,
3760 },
3761
f81ec90f
VD		 3762 [MV88E6161] = {
3763 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3764 .family = MV88E6XXX_FAMILY_6165,
3765 .name = "Marvell 88E6161",
3766 .num_databases = 4096,
3767 .num_ports = 6,
3cf3c846 3768 .max_vid = 4095,
9dddd478 3769 .port_base_addr = 0x10,
a935c052 3770 .global1_addr = 0x1b,
acddbd21 3771 .age_time_coeff = 15000,
dc30c35b 3772 .g1_irqs = 9,
e606ca36 3773 .atu_move_port_mask = 0xf,
f3645652 3774 .pvt = true,
443d5a1b 3775 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3776 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3777 .ops = &mv88e6161_ops,
f81ec90f
VD		 3778 },
3779
3780 [MV88E6165] = {
3781 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3782 .family = MV88E6XXX_FAMILY_6165,
3783 .name = "Marvell 88E6165",
3784 .num_databases = 4096,
3785 .num_ports = 6,
3cf3c846 3786 .max_vid = 4095,
9dddd478 3787 .port_base_addr = 0x10,
a935c052 3788 .global1_addr = 0x1b,
acddbd21 3789 .age_time_coeff = 15000,
dc30c35b 3790 .g1_irqs = 9,
e606ca36 3791 .atu_move_port_mask = 0xf,
f3645652 3792 .pvt = true,
443d5a1b 3793 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3794 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3795 .ops = &mv88e6165_ops,
f81ec90f
VD		 3796 },
3797
3798 [MV88E6171] = {
3799 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3800 .family = MV88E6XXX_FAMILY_6351,
3801 .name = "Marvell 88E6171",
3802 .num_databases = 4096,
3803 .num_ports = 7,
3cf3c846 3804 .max_vid = 4095,
9dddd478 3805 .port_base_addr = 0x10,
a935c052 3806 .global1_addr = 0x1b,
acddbd21 3807 .age_time_coeff = 15000,
dc30c35b 3808 .g1_irqs = 9,
e606ca36 3809 .atu_move_port_mask = 0xf,
f3645652 3810 .pvt = true,
443d5a1b 3811 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3812 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3813 .ops = &mv88e6171_ops,
f81ec90f
VD		 3814 },
3815
3816 [MV88E6172] = {
3817 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3818 .family = MV88E6XXX_FAMILY_6352,
3819 .name = "Marvell 88E6172",
3820 .num_databases = 4096,
3821 .num_ports = 7,
3cf3c846 3822 .max_vid = 4095,
9dddd478 3823 .port_base_addr = 0x10,
a935c052 3824 .global1_addr = 0x1b,
acddbd21 3825 .age_time_coeff = 15000,
dc30c35b 3826 .g1_irqs = 9,
e606ca36 3827 .atu_move_port_mask = 0xf,
f3645652 3828 .pvt = true,
443d5a1b 3829 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3830 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3831 .ops = &mv88e6172_ops,
f81ec90f
VD		 3832 },
3833
3834 [MV88E6175] = {
3835 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3836 .family = MV88E6XXX_FAMILY_6351,
3837 .name = "Marvell 88E6175",
3838 .num_databases = 4096,
3839 .num_ports = 7,
3cf3c846 3840 .max_vid = 4095,
9dddd478 3841 .port_base_addr = 0x10,
a935c052 3842 .global1_addr = 0x1b,
acddbd21 3843 .age_time_coeff = 15000,
dc30c35b 3844 .g1_irqs = 9,
e606ca36 3845 .atu_move_port_mask = 0xf,
f3645652 3846 .pvt = true,
443d5a1b 3847 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3848 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3849 .ops = &mv88e6175_ops,
f81ec90f
VD		 3850 },
3851
3852 [MV88E6176] = {
3853 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3854 .family = MV88E6XXX_FAMILY_6352,
3855 .name = "Marvell 88E6176",
3856 .num_databases = 4096,
3857 .num_ports = 7,
3cf3c846 3858 .max_vid = 4095,
9dddd478 3859 .port_base_addr = 0x10,
a935c052 3860 .global1_addr = 0x1b,
acddbd21 3861 .age_time_coeff = 15000,
dc30c35b 3862 .g1_irqs = 9,
e606ca36 3863 .atu_move_port_mask = 0xf,
f3645652 3864 .pvt = true,
443d5a1b 3865 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3866 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3867 .ops = &mv88e6176_ops,
f81ec90f
VD		 3868 },
3869
3870 [MV88E6185] = {
3871 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3872 .family = MV88E6XXX_FAMILY_6185,
3873 .name = "Marvell 88E6185",
3874 .num_databases = 256,
3875 .num_ports = 10,
3cf3c846 3876 .max_vid = 4095,
9dddd478 3877 .port_base_addr = 0x10,
a935c052 3878 .global1_addr = 0x1b,
acddbd21 3879 .age_time_coeff = 15000,
dc30c35b 3880 .g1_irqs = 8,
e606ca36 3881 .atu_move_port_mask = 0xf,
443d5a1b 3882 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3883 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3884 .ops = &mv88e6185_ops,
f81ec90f
VD		 3885 },
3886
1a3b39ec
AL		 3887 [MV88E6190] = {
3888 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3889 .family = MV88E6XXX_FAMILY_6390,
3890 .name = "Marvell 88E6190",
3891 .num_databases = 4096,
3892 .num_ports = 11, /* 10 + Z80 */
3893 .port_base_addr = 0x0,
3894 .global1_addr = 0x1b,
443d5a1b 3895 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3896 .age_time_coeff = 3750,
1a3b39ec 3897 .g1_irqs = 9,
f3645652 3898 .pvt = true,
e606ca36 3899 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3900 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3901 .ops = &mv88e6190_ops,
3902 },
3903
3904 [MV88E6190X] = {
3905 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3906 .family = MV88E6XXX_FAMILY_6390,
3907 .name = "Marvell 88E6190X",
3908 .num_databases = 4096,
3909 .num_ports = 11, /* 10 + Z80 */
3910 .port_base_addr = 0x0,
3911 .global1_addr = 0x1b,
b91e055c 3912 .age_time_coeff = 3750,
1a3b39ec 3913 .g1_irqs = 9,
e606ca36 3914 .atu_move_port_mask = 0x1f,
f3645652 3915 .pvt = true,
443d5a1b 3916 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3917 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3918 .ops = &mv88e6190x_ops,
3919 },
3920
3921 [MV88E6191] = {
3922 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3923 .family = MV88E6XXX_FAMILY_6390,
3924 .name = "Marvell 88E6191",
3925 .num_databases = 4096,
3926 .num_ports = 11, /* 10 + Z80 */
3927 .port_base_addr = 0x0,
3928 .global1_addr = 0x1b,
b91e055c 3929 .age_time_coeff = 3750,
443d5a1b 3930 .g1_irqs = 9,
e606ca36 3931 .atu_move_port_mask = 0x1f,
f3645652 3932 .pvt = true,
443d5a1b 3933 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec 3934 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
2cf4cefb 3935 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3936 },
3937
f81ec90f
VD		 3938 [MV88E6240] = {
3939 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3940 .family = MV88E6XXX_FAMILY_6352,
3941 .name = "Marvell 88E6240",
3942 .num_databases = 4096,
3943 .num_ports = 7,
3cf3c846 3944 .max_vid = 4095,
9dddd478 3945 .port_base_addr = 0x10,
a935c052 3946 .global1_addr = 0x1b,
acddbd21 3947 .age_time_coeff = 15000,
dc30c35b 3948 .g1_irqs = 9,
e606ca36 3949 .atu_move_port_mask = 0xf,
f3645652 3950 .pvt = true,
443d5a1b 3951 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3952 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3953 .ops = &mv88e6240_ops,
f81ec90f
VD		 3954 },
3955
1a3b39ec
AL		 3956 [MV88E6290] = {
3957 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3958 .family = MV88E6XXX_FAMILY_6390,
3959 .name = "Marvell 88E6290",
3960 .num_databases = 4096,
3961 .num_ports = 11, /* 10 + Z80 */
3962 .port_base_addr = 0x0,
3963 .global1_addr = 0x1b,
b91e055c 3964 .age_time_coeff = 3750,
1a3b39ec 3965 .g1_irqs = 9,
e606ca36 3966 .atu_move_port_mask = 0x1f,
f3645652 3967 .pvt = true,
443d5a1b 3968 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3969 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3970 .ops = &mv88e6290_ops,
3971 },
3972
f81ec90f
VD		 3973 [MV88E6320] = {
3974 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3975 .family = MV88E6XXX_FAMILY_6320,
3976 .name = "Marvell 88E6320",
3977 .num_databases = 4096,
3978 .num_ports = 7,
3cf3c846 3979 .max_vid = 4095,
9dddd478 3980 .port_base_addr = 0x10,
a935c052 3981 .global1_addr = 0x1b,
acddbd21 3982 .age_time_coeff = 15000,
dc30c35b 3983 .g1_irqs = 8,
e606ca36 3984 .atu_move_port_mask = 0xf,
f3645652 3985 .pvt = true,
443d5a1b 3986 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3987 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3988 .ops = &mv88e6320_ops,
f81ec90f
VD		 3989 },
3990
3991 [MV88E6321] = {
3992 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3993 .family = MV88E6XXX_FAMILY_6320,
3994 .name = "Marvell 88E6321",
3995 .num_databases = 4096,
3996 .num_ports = 7,
3cf3c846 3997 .max_vid = 4095,
9dddd478 3998 .port_base_addr = 0x10,
a935c052 3999 .global1_addr = 0x1b,
acddbd21 4000 .age_time_coeff = 15000,
dc30c35b 4001 .g1_irqs = 8,
e606ca36 4002 .atu_move_port_mask = 0xf,
443d5a1b 4003 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4004 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4005 .ops = &mv88e6321_ops,
f81ec90f
VD		 4006 },
4007
a75961d0
GC		 4008 [MV88E6341] = {
4009 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
4010 .family = MV88E6XXX_FAMILY_6341,
4011 .name = "Marvell 88E6341",
4012 .num_databases = 4096,
4013 .num_ports = 6,
3cf3c846 4014 .max_vid = 4095,
a75961d0
GC		 4015 .port_base_addr = 0x10,
4016 .global1_addr = 0x1b,
4017 .age_time_coeff = 3750,
e606ca36 4018 .atu_move_port_mask = 0x1f,
f3645652 4019 .pvt = true,
a75961d0
GC		 4020 .tag_protocol = DSA_TAG_PROTO_EDSA,
4021 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4022 .ops = &mv88e6341_ops,
4023 },
4024
f81ec90f
VD		 4025 [MV88E6350] = {
4026 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4027 .family = MV88E6XXX_FAMILY_6351,
4028 .name = "Marvell 88E6350",
4029 .num_databases = 4096,
4030 .num_ports = 7,
3cf3c846 4031 .max_vid = 4095,
9dddd478 4032 .port_base_addr = 0x10,
a935c052 4033 .global1_addr = 0x1b,
acddbd21 4034 .age_time_coeff = 15000,
dc30c35b 4035 .g1_irqs = 9,
e606ca36 4036 .atu_move_port_mask = 0xf,
f3645652 4037 .pvt = true,
443d5a1b 4038 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4039 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4040 .ops = &mv88e6350_ops,
f81ec90f
VD		 4041 },
4042
4043 [MV88E6351] = {
4044 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4045 .family = MV88E6XXX_FAMILY_6351,
4046 .name = "Marvell 88E6351",
4047 .num_databases = 4096,
4048 .num_ports = 7,
3cf3c846 4049 .max_vid = 4095,
9dddd478 4050 .port_base_addr = 0x10,
a935c052 4051 .global1_addr = 0x1b,
acddbd21 4052 .age_time_coeff = 15000,
dc30c35b 4053 .g1_irqs = 9,
e606ca36 4054 .atu_move_port_mask = 0xf,
f3645652 4055 .pvt = true,
443d5a1b 4056 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4057 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4058 .ops = &mv88e6351_ops,
f81ec90f
VD		 4059 },
4060
4061 [MV88E6352] = {
4062 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4063 .family = MV88E6XXX_FAMILY_6352,
4064 .name = "Marvell 88E6352",
4065 .num_databases = 4096,
4066 .num_ports = 7,
3cf3c846 4067 .max_vid = 4095,
9dddd478 4068 .port_base_addr = 0x10,
a935c052 4069 .global1_addr = 0x1b,
acddbd21 4070 .age_time_coeff = 15000,
dc30c35b 4071 .g1_irqs = 9,
e606ca36 4072 .atu_move_port_mask = 0xf,
f3645652 4073 .pvt = true,
443d5a1b 4074 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4075 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4076 .ops = &mv88e6352_ops,
f81ec90f 4077 },
1a3b39ec
AL		 4078 [MV88E6390] = {
4079 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4080 .family = MV88E6XXX_FAMILY_6390,
4081 .name = "Marvell 88E6390",
4082 .num_databases = 4096,
4083 .num_ports = 11, /* 10 + Z80 */
4084 .port_base_addr = 0x0,
4085 .global1_addr = 0x1b,
b91e055c 4086 .age_time_coeff = 3750,
1a3b39ec 4087 .g1_irqs = 9,
e606ca36 4088 .atu_move_port_mask = 0x1f,
f3645652 4089 .pvt = true,
443d5a1b 4090 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4091 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4092 .ops = &mv88e6390_ops,
4093 },
4094 [MV88E6390X] = {
4095 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4096 .family = MV88E6XXX_FAMILY_6390,
4097 .name = "Marvell 88E6390X",
4098 .num_databases = 4096,
4099 .num_ports = 11, /* 10 + Z80 */
4100 .port_base_addr = 0x0,
4101 .global1_addr = 0x1b,
b91e055c 4102 .age_time_coeff = 3750,
1a3b39ec 4103 .g1_irqs = 9,
e606ca36 4104 .atu_move_port_mask = 0x1f,
f3645652 4105 .pvt = true,
443d5a1b 4106 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4107 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4108 .ops = &mv88e6390x_ops,
4109 },
f81ec90f
VD		 4110};
4111
5f7c0367 4112static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4113{
a439c061 4114 int i;
b9b37713 4115
5f7c0367
VD		 4116 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4117 if (mv88e6xxx_table[i].prod_num == prod_num)
4118 return &mv88e6xxx_table[i];
b9b37713 4119
b9b37713
VD		 4120 return NULL;
4121}
4122
fad09c73 4123static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4124{
4125 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4126 unsigned int prod_num, rev;
4127 u16 id;
4128 int err;
bc46a3d5 4129
8f6345b2
VD		 4130 mutex_lock(&chip->reg_lock);
4131 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4132 mutex_unlock(&chip->reg_lock);
4133 if (err)
4134 return err;
bc46a3d5
VD		 4135
4136 prod_num = (id & 0xfff0) >> 4;
4137 rev = id & 0x000f;
4138
4139 info = mv88e6xxx_lookup_info(prod_num);
4140 if (!info)
4141 return -ENODEV;
4142
caac8545 4143 /* Update the compatible info with the probed one */
fad09c73 4144 chip->info = info;
bc46a3d5 4145
ca070c10
VD		 4146 err = mv88e6xxx_g2_require(chip);
4147 if (err)
4148 return err;
4149
fad09c73
VD		 4150 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4151 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4152
4153 return 0;
4154}
4155
fad09c73 4156static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4157{
fad09c73 4158 struct mv88e6xxx_chip *chip;
469d729f 4159
fad09c73
VD		 4160 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4161 if (!chip)
469d729f
VD		 4162 return NULL;
4163
fad09c73 4164 chip->dev = dev;
469d729f 4165
fad09c73 4166 mutex_init(&chip->reg_lock);
a3c53be5 4167 INIT_LIST_HEAD(&chip->mdios);
469d729f 4168
fad09c73 4169 return chip;
469d729f
VD		 4170}
4171
e57e5e77
VD		 4172static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4173{
a199d8b6 4174 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4175 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4176}
4177
930188ce
AL		 4178static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4179{
a199d8b6 4180 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4181 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4182}
4183
fad09c73 4184static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4185 struct mii_bus *bus, int sw_addr)
4186{
914b32f6 4187 if (sw_addr == 0)
fad09c73 4188 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4189 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4190 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4191 else
4192 return -EINVAL;
4193
fad09c73
VD		 4194 chip->bus = bus;
4195 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4196
4197 return 0;
4198}
4199
7b314362
AL		 4200static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4201{
04bed143 4202 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4203
443d5a1b 4204 return chip->info->tag_protocol;
7b314362
AL		 4205}
4206
fcdce7d0
AL		 4207static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4208 struct device *host_dev, int sw_addr,
4209 void **priv)
a77d43f1 4210{
fad09c73 4211 struct mv88e6xxx_chip *chip;
a439c061 4212 struct mii_bus *bus;
b516d453 4213 int err;
a77d43f1 4214
a439c061 4215 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4216 if (!bus)
4217 return NULL;
4218
fad09c73
VD		 4219 chip = mv88e6xxx_alloc_chip(dsa_dev);
4220 if (!chip)
469d729f
VD		 4221 return NULL;
4222
caac8545 4223 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4224 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4225
fad09c73 4226 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4227 if (err)
4228 goto free;
4229
fad09c73 4230 err = mv88e6xxx_detect(chip);
bc46a3d5 4231 if (err)
469d729f 4232 goto free;
a439c061 4233
dc30c35b
AL		 4234 mutex_lock(&chip->reg_lock);
4235 err = mv88e6xxx_switch_reset(chip);
4236 mutex_unlock(&chip->reg_lock);
4237 if (err)
4238 goto free;
4239
e57e5e77
VD		 4240 mv88e6xxx_phy_init(chip);
4241
a3c53be5 4242 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4243 if (err)
469d729f 4244 goto free;
b516d453 4245
fad09c73 4246 *priv = chip;
a439c061 4247
fad09c73 4248 return chip->info->name;
469d729f 4249free:
fad09c73 4250 devm_kfree(dsa_dev, chip);
469d729f
VD		 4251
4252 return NULL;
a77d43f1
AL		 4253}
4254
7df8fbdd
VD		 4255static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4256 const struct switchdev_obj_port_mdb *mdb,
4257 struct switchdev_trans *trans)
4258{
4259 /* We don't need any dynamic resource from the kernel (yet),
4260 * so skip the prepare phase.
4261 */
4262
4263 return 0;
4264}
4265
4266static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4267 const struct switchdev_obj_port_mdb *mdb,
4268 struct switchdev_trans *trans)
4269{
04bed143 4270 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4271
4272 mutex_lock(&chip->reg_lock);
4273 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4274 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4275 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4276 mutex_unlock(&chip->reg_lock);
4277}
4278
4279static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4280 const struct switchdev_obj_port_mdb *mdb)
4281{
04bed143 4282 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4283 int err;
4284
4285 mutex_lock(&chip->reg_lock);
4286 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4287 GLOBAL_ATU_DATA_STATE_UNUSED);
4288 mutex_unlock(&chip->reg_lock);
4289
4290 return err;
4291}
4292
4293static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4294 struct switchdev_obj_port_mdb *mdb,
4295 int (*cb)(struct switchdev_obj *obj))
4296{
04bed143 4297 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4298 int err;
4299
4300 mutex_lock(&chip->reg_lock);
4301 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4302 mutex_unlock(&chip->reg_lock);
4303
4304 return err;
4305}
4306
a82f67af 4307static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4308 .probe = mv88e6xxx_drv_probe,
7b314362 4309 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4310 .setup = mv88e6xxx_setup,
4311 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4312 .adjust_link = mv88e6xxx_adjust_link,
4313 .get_strings = mv88e6xxx_get_strings,
4314 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4315 .get_sset_count = mv88e6xxx_get_sset_count,
4316 .set_eee = mv88e6xxx_set_eee,
4317 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4318 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4319 .get_eeprom = mv88e6xxx_get_eeprom,
4320 .set_eeprom = mv88e6xxx_set_eeprom,
4321 .get_regs_len = mv88e6xxx_get_regs_len,
4322 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4323 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4324 .port_bridge_join = mv88e6xxx_port_bridge_join,
4325 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4326 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4327 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4328 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4329 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4330 .port_vlan_add = mv88e6xxx_port_vlan_add,
4331 .port_vlan_del = mv88e6xxx_port_vlan_del,
4332 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4333 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4334 .port_fdb_add = mv88e6xxx_port_fdb_add,
4335 .port_fdb_del = mv88e6xxx_port_fdb_del,
4336 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4337 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4338 .port_mdb_add = mv88e6xxx_port_mdb_add,
4339 .port_mdb_del = mv88e6xxx_port_mdb_del,
4340 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
aec5ac88
VD		 4341 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4342 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 4343};
4344
ab3d408d
FF		 4345static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4346 .ops = &mv88e6xxx_switch_ops,
4347};
4348
55ed0ce0 4349static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4350{
fad09c73 4351 struct device *dev = chip->dev;
b7e66a5f
VD		 4352 struct dsa_switch *ds;
4353
73b1204d 4354 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 4355 if (!ds)
4356 return -ENOMEM;
4357
fad09c73 4358 ds->priv = chip;
9d490b4e 4359 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 4360 ds->ageing_time_min = chip->info->age_time_coeff;
4361 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 4362
4363 dev_set_drvdata(dev, ds);
4364
55ed0ce0 4365 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4366}
4367
fad09c73 4368static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4369{
fad09c73 4370 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4371}
4372
57d32310 4373static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4374{
14c7b3c3 4375 struct device *dev = &mdiodev->dev;
f8cd8753 4376 struct device_node *np = dev->of_node;
caac8545 4377 const struct mv88e6xxx_info *compat_info;
fad09c73 4378 struct mv88e6xxx_chip *chip;
f8cd8753 4379 u32 eeprom_len;
52638f71 4380 int err;
14c7b3c3 4381
caac8545
VD		 4382 compat_info = of_device_get_match_data(dev);
4383 if (!compat_info)
4384 return -EINVAL;
4385
fad09c73
VD		 4386 chip = mv88e6xxx_alloc_chip(dev);
4387 if (!chip)
14c7b3c3
AL		 4388 return -ENOMEM;
4389
fad09c73 4390 chip->info = compat_info;
caac8545 4391
fad09c73 4392 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4393 if (err)
4394 return err;
14c7b3c3 4395
b4308f04
AL		 4396 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4397 if (IS_ERR(chip->reset))
4398 return PTR_ERR(chip->reset);
4399
fad09c73 4400 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4401 if (err)
4402 return err;
14c7b3c3 4403
e57e5e77
VD		 4404 mv88e6xxx_phy_init(chip);
4405
ee4dc2e7 4406 if (chip->info->ops->get_eeprom &&
f8cd8753 4407 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4408 chip->eeprom_len = eeprom_len;
f8cd8753 4409
dc30c35b
AL		 4410 mutex_lock(&chip->reg_lock);
4411 err = mv88e6xxx_switch_reset(chip);
4412 mutex_unlock(&chip->reg_lock);
4413 if (err)
4414 goto out;
4415
4416 chip->irq = of_irq_get(np, 0);
4417 if (chip->irq == -EPROBE_DEFER) {
4418 err = chip->irq;
4419 goto out;
4420 }
4421
4422 if (chip->irq > 0) {
4423 /* Has to be performed before the MDIO bus is created,
4424 * because the PHYs will link there interrupts to these
4425 * interrupt controllers
4426 */
4427 mutex_lock(&chip->reg_lock);
4428 err = mv88e6xxx_g1_irq_setup(chip);
4429 mutex_unlock(&chip->reg_lock);
4430
4431 if (err)
4432 goto out;
4433
4434 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4435 err = mv88e6xxx_g2_irq_setup(chip);
4436 if (err)
4437 goto out_g1_irq;
4438 }
4439 }
4440
a3c53be5 4441 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4442 if (err)
dc30c35b 4443 goto out_g2_irq;
b516d453 4444
55ed0ce0 4445 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4446 if (err)
4447 goto out_mdio;
83c0afae 4448
98e67308 4449 return 0;
dc30c35b
AL		 4450
4451out_mdio:
a3c53be5 4452 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4453out_g2_irq:
46712644 4454 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4455 mv88e6xxx_g2_irq_free(chip);
4456out_g1_irq:
61f7c3f8
AL		 4457 if (chip->irq > 0) {
4458 mutex_lock(&chip->reg_lock);
46712644 4459 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4460 mutex_unlock(&chip->reg_lock);
4461 }
dc30c35b
AL		 4462out:
4463 return err;
98e67308 4464}
14c7b3c3
AL		 4465
4466static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4467{
4468 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4469 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4470
930188ce 4471 mv88e6xxx_phy_destroy(chip);
fad09c73 4472 mv88e6xxx_unregister_switch(chip);
a3c53be5 4473 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4474
46712644
AL		 4475 if (chip->irq > 0) {
4476 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4477 mv88e6xxx_g2_irq_free(chip);
4478 mv88e6xxx_g1_irq_free(chip);
4479 }
14c7b3c3
AL		 4480}
4481
4482static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4483 {
4484 .compatible = "marvell,mv88e6085",
4485 .data = &mv88e6xxx_table[MV88E6085],
4486 },
1a3b39ec
AL		 4487 {
4488 .compatible = "marvell,mv88e6190",
4489 .data = &mv88e6xxx_table[MV88E6190],
4490 },
14c7b3c3
AL		 4491 { /* sentinel */ },
4492};
4493
4494MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4495
4496static struct mdio_driver mv88e6xxx_driver = {
4497 .probe = mv88e6xxx_probe,
4498 .remove = mv88e6xxx_remove,
4499 .mdiodrv.driver = {
4500 .name = "mv88e6085",
4501 .of_match_table = mv88e6xxx_of_match,
4502 },
4503};
4504
4505static int __init mv88e6xxx_init(void)
4506{
ab3d408d 4507 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4508 return mdio_driver_register(&mv88e6xxx_driver);
4509}
98e67308
BH		 4510module_init(mv88e6xxx_init);
4511
4512static void __exit mv88e6xxx_cleanup(void)
4513{
14c7b3c3 4514 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4515 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4516}
4517module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4518
4519MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4520MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4521MODULE_LICENSE("GPL");
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