]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/dsa/mv88e6xxx/chip.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net:dsa:mv88e6xxx: use watchdog ops for 6097 chip
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
ee26a228
AL		 225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
efb3e74d
AL		 228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
ee26a228
AL		 232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
efb3e74d
AL		 235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
a3c53be5
AL		 239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
e57e5e77
VD		 251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 255 struct mii_bus *bus;
e57e5e77 256
a3c53be5
AL		 257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
e57e5e77
VD		 259 return -EOPNOTSUPP;
260
a3c53be5 261 if (!chip->info->ops->phy_read)
ee26a228
AL		 262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 271 struct mii_bus *bus;
e57e5e77 272
a3c53be5
AL		 273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
e57e5e77
VD		 275 return -EOPNOTSUPP;
276
a3c53be5 277 if (!chip->info->ops->phy_write)
ee26a228
AL		 278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 281}
282
09cb7dfd
VD		 283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
dc30c35b
AL		 351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
3460a577
AL		 452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
dc30c35b 459
5edef2f2 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 462 irq_dispose_mapping(virq);
463 }
464
a3db3d3a 465 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
3dd0ef05
AL		 470 int err, irq, virq;
471 u16 reg, mask;
dc30c35b
AL		 472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
3dd0ef05 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 487 if (err)
3dd0ef05 488 goto out_mapping;
dc30c35b 489
3dd0ef05 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 491
3dd0ef05 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 493 if (err)
3dd0ef05 494 goto out_disable;
dc30c35b
AL		 495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
3dd0ef05 499 goto out_disable;
dc30c35b
AL		 500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
3dd0ef05 506 goto out_disable;
dc30c35b
AL		 507
508 return 0;
509
3dd0ef05
AL		 510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 521
522 return err;
523}
524
ec561276 525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 526{
6441e669 527 int i;
2d79af6e 528
6441e669 529 for (i = 0; i < 16; i++) {
2d79af6e
VD		 530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
30853553 543 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 544 return -ETIMEDOUT;
545}
546
f22ab641 547/* Indirect write to single pointer-data register with an Update bit */
ec561276 548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 549{
550 u16 val;
0f02b4f7 551 int err;
f22ab641
VD		 552
553 /* Wait until the previous operation is completed */
0f02b4f7
AL		 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
f22ab641
VD		 557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
a935c052 564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 565{
a199d8b6
VD		 566 if (!chip->info->ops->ppu_disable)
567 return 0;
2e5f0320 568
a199d8b6 569 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 570}
571
fad09c73 572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 573{
a199d8b6
VD		 574 if (!chip->info->ops->ppu_enable)
575 return 0;
2e5f0320 576
a199d8b6 577 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
fad09c73 582 struct mv88e6xxx_chip *chip;
2e5f0320 583
fad09c73 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 585
fad09c73 586 mutex_lock(&chip->reg_lock);
762eb67b 587
fad09c73
VD		 588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
2e5f0320 592 }
762eb67b 593
fad09c73 594 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
fad09c73 599 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 600
fad09c73 601 schedule_work(&chip->ppu_work);
2e5f0320
LB		 602}
603
fad09c73 604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 605{
2e5f0320
LB		 606 int ret;
607
fad09c73 608 mutex_lock(&chip->ppu_mutex);
2e5f0320 609
3675c8d7 610 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
fad09c73
VD		 615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
85686581 617 if (ret < 0) {
fad09c73 618 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 619 return ret;
620 }
fad09c73 621 chip->ppu_disabled = 1;
2e5f0320 622 } else {
fad09c73 623 del_timer(&chip->ppu_timer);
85686581 624 ret = 0;
2e5f0320
LB		 625 }
626
627 return ret;
628}
629
fad09c73 630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 631{
3675c8d7 632 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 635}
636
fad09c73 637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 638{
fad09c73
VD		 639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
2e5f0320
LB		 643}
644
930188ce
AL		 645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
ee26a228
AL		 650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
2e5f0320 653{
e57e5e77 654 int err;
2e5f0320 655
e57e5e77
VD		 656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 659 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 660 }
661
e57e5e77 662 return err;
2e5f0320
LB		 663}
664
ee26a228
AL		 665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 693}
694
a75961d0
GC		 695static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
696{
697 return chip->info->family == MV88E6XXX_FAMILY_6341;
698}
699
fad09c73 700static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 703}
704
fad09c73 705static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 708}
709
d78343d2
VD		 710static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
711 int link, int speed, int duplex,
712 phy_interface_t mode)
713{
714 int err;
715
716 if (!chip->info->ops->port_set_link)
717 return 0;
718
719 /* Port's MAC control must not be changed unless the link is down */
720 err = chip->info->ops->port_set_link(chip, port, 0);
721 if (err)
722 return err;
723
724 if (chip->info->ops->port_set_speed) {
725 err = chip->info->ops->port_set_speed(chip, port, speed);
726 if (err && err != -EOPNOTSUPP)
727 goto restore_link;
728 }
729
730 if (chip->info->ops->port_set_duplex) {
731 err = chip->info->ops->port_set_duplex(chip, port, duplex);
732 if (err && err != -EOPNOTSUPP)
733 goto restore_link;
734 }
735
736 if (chip->info->ops->port_set_rgmii_delay) {
737 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
738 if (err && err != -EOPNOTSUPP)
739 goto restore_link;
740 }
741
f39908d3
AL		 742 if (chip->info->ops->port_set_cmode) {
743 err = chip->info->ops->port_set_cmode(chip, port, mode);
744 if (err && err != -EOPNOTSUPP)
745 goto restore_link;
746 }
747
d78343d2
VD		 748 err = 0;
749restore_link:
750 if (chip->info->ops->port_set_link(chip, port, link))
751 netdev_err(chip->ds->ports[port].netdev,
752 "failed to restore MAC's link\n");
753
754 return err;
755}
756
dea87024
AL		 757/* We expect the switch to perform auto negotiation if there is a real
758 * phy. However, in the case of a fixed link phy, we force the port
759 * settings from the fixed link settings.
760 */
f81ec90f
VD		 761static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
762 struct phy_device *phydev)
dea87024 763{
04bed143 764 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 765 int err;
dea87024
AL		 766
767 if (!phy_is_pseudo_fixed_link(phydev))
768 return;
769
fad09c73 770 mutex_lock(&chip->reg_lock);
d78343d2
VD		 771 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
772 phydev->duplex, phydev->interface);
fad09c73 773 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 774
775 if (err && err != -EOPNOTSUPP)
776 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 777}
778
a605a0fe 779static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 780{
a605a0fe
AL		 781 if (!chip->info->ops->stats_snapshot)
782 return -EOPNOTSUPP;
91da11f8 783
a605a0fe 784 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 785}
786
e413e7e1 787static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 788 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
789 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
790 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
791 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
792 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
793 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
794 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
795 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
796 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
797 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
798 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
799 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
800 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
801 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
802 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
803 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
804 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
805 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
806 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
807 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
808 { "single", 4, 0x14, STATS_TYPE_BANK0, },
809 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
810 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
811 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
812 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
813 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
814 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
815 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
816 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
817 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
818 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
819 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
820 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
821 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
822 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
823 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
824 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
826 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
828 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
829 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
830 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
831 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
832 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
833 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
834 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
835 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
836 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
837 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
838 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
839 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
840 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
841 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
842 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
843 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
844 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
845 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
846 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 847};
848
fad09c73 849static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 850 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 851 int port, u16 bank1_select,
852 u16 histogram)
80c4627b 853{
80c4627b
AL		 854 u32 low;
855 u32 high = 0;
dfafe449 856 u16 reg = 0;
0e7b9925 857 int err;
80c4627b
AL		 858 u64 value;
859
f5e2ed02 860 switch (s->type) {
dfafe449 861 case STATS_TYPE_PORT:
0e7b9925
AL		 862 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
863 if (err)
80c4627b
AL		 864 return UINT64_MAX;
865
0e7b9925 866 low = reg;
80c4627b 867 if (s->sizeof_stat == 4) {
0e7b9925
AL		 868 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
869 if (err)
80c4627b 870 return UINT64_MAX;
0e7b9925 871 high = reg;
80c4627b 872 }
f5e2ed02 873 break;
dfafe449 874 case STATS_TYPE_BANK1:
e0d8b615 875 reg = bank1_select;
dfafe449
AL		 876 /* fall through */
877 case STATS_TYPE_BANK0:
e0d8b615 878 reg |= s->reg | histogram;
7f9ef3af 879 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 880 if (s->sizeof_stat == 8)
7f9ef3af 881 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 882 }
883 value = (((u64)high) << 16) | low;
884 return value;
885}
886
dfafe449
AL		 887static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
888 uint8_t *data, int types)
91da11f8 889{
f5e2ed02
AL		 890 struct mv88e6xxx_hw_stat *stat;
891 int i, j;
91da11f8 892
f5e2ed02
AL		 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 stat = &mv88e6xxx_hw_stats[i];
dfafe449 895 if (stat->type & types) {
f5e2ed02
AL		 896 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
897 ETH_GSTRING_LEN);
898 j++;
899 }
91da11f8 900 }
e413e7e1
AL		 901}
902
dfafe449
AL		 903static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
904 uint8_t *data)
905{
906 mv88e6xxx_stats_get_strings(chip, data,
907 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
908}
909
910static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
911 uint8_t *data)
912{
913 mv88e6xxx_stats_get_strings(chip, data,
914 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
915}
916
917static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
918 uint8_t *data)
e413e7e1 919{
04bed143 920 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 921
922 if (chip->info->ops->stats_get_strings)
923 chip->info->ops->stats_get_strings(chip, data);
924}
925
926static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
927 int types)
928{
f5e2ed02
AL		 929 struct mv88e6xxx_hw_stat *stat;
930 int i, j;
931
932 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
933 stat = &mv88e6xxx_hw_stats[i];
dfafe449 934 if (stat->type & types)
f5e2ed02
AL		 935 j++;
936 }
937 return j;
e413e7e1
AL		 938}
939
dfafe449
AL		 940static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
941{
942 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
943 STATS_TYPE_PORT);
944}
945
946static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
947{
948 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
949 STATS_TYPE_BANK1);
950}
951
952static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
953{
954 struct mv88e6xxx_chip *chip = ds->priv;
955
956 if (chip->info->ops->stats_get_sset_count)
957 return chip->info->ops->stats_get_sset_count(chip);
958
959 return 0;
960}
961
052f947f 962static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 963 uint64_t *data, int types,
964 u16 bank1_select, u16 histogram)
052f947f
AL		 965{
966 struct mv88e6xxx_hw_stat *stat;
967 int i, j;
968
969 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
970 stat = &mv88e6xxx_hw_stats[i];
971 if (stat->type & types) {
e0d8b615
AL		 972 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
973 bank1_select,
974 histogram);
052f947f
AL		 975 j++;
976 }
977 }
978}
979
980static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
981 uint64_t *data)
982{
983 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 984 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
985 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 986}
987
988static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
989 uint64_t *data)
990{
991 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 992 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
993 GLOBAL_STATS_OP_BANK_1_BIT_9,
994 GLOBAL_STATS_OP_HIST_RX_TX);
995}
996
997static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
998 uint64_t *data)
999{
1000 return mv88e6xxx_stats_get_stats(chip, port, data,
1001 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1002 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1003}
1004
1005static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1006 uint64_t *data)
1007{
1008 if (chip->info->ops->stats_get_stats)
1009 chip->info->ops->stats_get_stats(chip, port, data);
1010}
1011
f81ec90f
VD		 1012static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1013 uint64_t *data)
e413e7e1 1014{
04bed143 1015 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1016 int ret;
f5e2ed02 1017
fad09c73 1018 mutex_lock(&chip->reg_lock);
f5e2ed02 1019
a605a0fe 1020 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1021 if (ret < 0) {
fad09c73 1022 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1023 return;
1024 }
052f947f
AL		 1025
1026 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1027
fad09c73 1028 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1029}
1030
de227387
AL		 1031static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1032{
1033 if (chip->info->ops->stats_set_histogram)
1034 return chip->info->ops->stats_set_histogram(chip);
1035
1036 return 0;
1037}
1038
f81ec90f 1039static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1040{
1041 return 32 * sizeof(u16);
1042}
1043
f81ec90f
VD		 1044static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1045 struct ethtool_regs *regs, void *_p)
a1ab91f3 1046{
04bed143 1047 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1048 int err;
1049 u16 reg;
a1ab91f3
GR		 1050 u16 *p = _p;
1051 int i;
1052
1053 regs->version = 0;
1054
1055 memset(p, 0xff, 32 * sizeof(u16));
1056
fad09c73 1057 mutex_lock(&chip->reg_lock);
23062513 1058
a1ab91f3 1059 for (i = 0; i < 32; i++) {
a1ab91f3 1060
0e7b9925
AL		 1061 err = mv88e6xxx_port_read(chip, port, i, &reg);
1062 if (!err)
1063 p[i] = reg;
a1ab91f3 1064 }
23062513 1065
fad09c73 1066 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1067}
1068
fad09c73 1069static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1070{
a935c052 1071 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1072}
1073
f81ec90f
VD		 1074static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1075 struct ethtool_eee *e)
11b3b45d 1076{
04bed143 1077 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1078 u16 reg;
1079 int err;
11b3b45d 1080
fad09c73 1081 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1082 return -EOPNOTSUPP;
1083
fad09c73 1084 mutex_lock(&chip->reg_lock);
2f40c698 1085
9c93829c
VD		 1086 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1087 if (err)
2f40c698 1088 goto out;
11b3b45d
GR		 1089
1090 e->eee_enabled = !!(reg & 0x0200);
1091 e->tx_lpi_enabled = !!(reg & 0x0100);
1092
0e7b9925 1093 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1094 if (err)
2f40c698 1095 goto out;
11b3b45d 1096
cca8b133 1097 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1098out:
fad09c73 1099 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1100
1101 return err;
11b3b45d
GR		 1102}
1103
f81ec90f
VD		 1104static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1105 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1106{
04bed143 1107 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1108 u16 reg;
1109 int err;
11b3b45d 1110
fad09c73 1111 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1112 return -EOPNOTSUPP;
1113
fad09c73 1114 mutex_lock(&chip->reg_lock);
11b3b45d 1115
9c93829c
VD		 1116 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1117 if (err)
2f40c698
AL		 1118 goto out;
1119
9c93829c 1120 reg &= ~0x0300;
2f40c698
AL		 1121 if (e->eee_enabled)
1122 reg |= 0x0200;
1123 if (e->tx_lpi_enabled)
1124 reg |= 0x0100;
1125
9c93829c 1126 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1127out:
fad09c73 1128 mutex_unlock(&chip->reg_lock);
2f40c698 1129
9c93829c 1130 return err;
11b3b45d
GR		 1131}
1132
fad09c73 1133static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1134{
a935c052
VD		 1135 u16 val;
1136 int err;
facd95b2 1137
6dc10bbc 1138 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1139 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1140 if (err)
1141 return err;
fad09c73 1142 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1143 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1144 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1145 if (err)
1146 return err;
11ea809f 1147
a935c052
VD		 1148 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1149 (val & 0xfff) | ((fid << 8) & 0xf000));
1150 if (err)
1151 return err;
11ea809f
VD		 1152
1153 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1154 cmd |= fid & 0xf;
b426e5f7
VD		 1155 }
1156
a935c052
VD		 1157 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1158 if (err)
1159 return err;
facd95b2 1160
fad09c73 1161 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1162}
1163
fad09c73 1164static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1165 struct mv88e6xxx_atu_entry *entry)
1166{
1167 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1168
1169 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1170 unsigned int mask, shift;
1171
1172 if (entry->trunk) {
1173 data |= GLOBAL_ATU_DATA_TRUNK;
1174 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1175 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1176 } else {
1177 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1178 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1179 }
1180
1181 data |= (entry->portv_trunkid << shift) & mask;
1182 }
1183
a935c052 1184 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1185}
1186
fad09c73 1187static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1188 struct mv88e6xxx_atu_entry *entry,
1189 bool static_too)
facd95b2 1190{
7fb5e755
VD		 1191 int op;
1192 int err;
facd95b2 1193
fad09c73 1194 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1195 if (err)
1196 return err;
facd95b2 1197
fad09c73 1198 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1199 if (err)
1200 return err;
1201
1202 if (entry->fid) {
7fb5e755
VD		 1203 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1204 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1205 } else {
1206 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1207 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1208 }
1209
fad09c73 1210 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1211}
1212
fad09c73 1213static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1214 u16 fid, bool static_too)
7fb5e755
VD		 1215{
1216 struct mv88e6xxx_atu_entry entry = {
1217 .fid = fid,
1218 .state = 0, /* EntryState bits must be 0 */
1219 };
70cc99d1 1220
fad09c73 1221 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1222}
1223
fad09c73 1224static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1225 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1226{
1227 struct mv88e6xxx_atu_entry entry = {
1228 .trunk = false,
1229 .fid = fid,
1230 };
1231
1232 /* EntryState bits must be 0xF */
1233 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1234
1235 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1236 entry.portv_trunkid = (to_port & 0x0f) << 4;
1237 entry.portv_trunkid |= from_port & 0x0f;
1238
fad09c73 1239 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1240}
1241
fad09c73 1242static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1243 int port, bool static_too)
9f4d55d2
VD		 1244{
1245 /* Destination port 0xF means remove the entries */
fad09c73 1246 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1247}
1248
fad09c73 1249static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1250{
fad09c73 1251 struct dsa_switch *ds = chip->ds;
fae8a25e 1252 struct net_device *bridge = ds->ports[port].bridge_dev;
b7666efe 1253 u16 output_ports = 0;
b7666efe
VD		 1254 int i;
1255
1256 /* allow CPU port or DSA link(s) to send frames to every port */
1257 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1258 output_ports = ~0;
b7666efe 1259 } else {
370b4ffb 1260 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1261 /* allow sending frames to every group member */
fae8a25e 1262 if (bridge && ds->ports[i].bridge_dev == bridge)
b7666efe
VD		 1263 output_ports |= BIT(i);
1264
1265 /* allow sending frames to CPU port and DSA link(s) */
1266 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1267 output_ports |= BIT(i);
1268 }
1269 }
1270
1271 /* prevent frames from going back out of the port they came in on */
1272 output_ports &= ~BIT(port);
facd95b2 1273
5a7921f4 1274 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1275}
1276
f81ec90f
VD		 1277static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1278 u8 state)
facd95b2 1279{
04bed143 1280 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1281 int stp_state;
553eb544 1282 int err;
facd95b2
GR		 1283
1284 switch (state) {
1285 case BR_STATE_DISABLED:
cca8b133 1286 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1287 break;
1288 case BR_STATE_BLOCKING:
1289 case BR_STATE_LISTENING:
cca8b133 1290 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1291 break;
1292 case BR_STATE_LEARNING:
cca8b133 1293 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1294 break;
1295 case BR_STATE_FORWARDING:
1296 default:
cca8b133 1297 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1298 break;
1299 }
1300
fad09c73 1301 mutex_lock(&chip->reg_lock);
e28def33 1302 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1303 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1304
1305 if (err)
e28def33 1306 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1307}
1308
749efcb8
VD		 1309static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1310{
1311 struct mv88e6xxx_chip *chip = ds->priv;
1312 int err;
1313
1314 mutex_lock(&chip->reg_lock);
1315 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1316 mutex_unlock(&chip->reg_lock);
1317
1318 if (err)
1319 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1320}
1321
fad09c73 1322static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1323{
a935c052 1324 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1325}
1326
fad09c73 1327static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1328{
a935c052 1329 int err;
6b17e864 1330
a935c052
VD		 1331 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1332 if (err)
1333 return err;
6b17e864 1334
fad09c73 1335 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1336}
1337
fad09c73 1338static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1339{
1340 int ret;
1341
fad09c73 1342 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1343 if (ret < 0)
1344 return ret;
1345
fad09c73 1346 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1347}
1348
fad09c73 1349static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1350 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1351 unsigned int nibble_offset)
1352{
b8fee957 1353 u16 regs[3];
a935c052 1354 int i, err;
b8fee957
VD		 1355
1356 for (i = 0; i < 3; ++i) {
a935c052 1357 u16 *reg = &regs[i];
b8fee957 1358
a935c052
VD		 1359 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1360 if (err)
1361 return err;
b8fee957
VD		 1362 }
1363
370b4ffb 1364 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1365 unsigned int shift = (i % 4) * 4 + nibble_offset;
1366 u16 reg = regs[i / 4];
1367
1368 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1369 }
1370
1371 return 0;
1372}
1373
fad09c73 1374static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1375 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1376{
fad09c73 1377 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1378}
1379
fad09c73 1380static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1381 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1382{
fad09c73 1383 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1384}
1385
fad09c73 1386static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1387 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1388 unsigned int nibble_offset)
1389{
7dad08d7 1390 u16 regs[3] = { 0 };
a935c052 1391 int i, err;
7dad08d7 1392
370b4ffb 1393 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1394 unsigned int shift = (i % 4) * 4 + nibble_offset;
1395 u8 data = entry->data[i];
1396
1397 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1398 }
1399
1400 for (i = 0; i < 3; ++i) {
a935c052
VD		 1401 u16 reg = regs[i];
1402
1403 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1404 if (err)
1405 return err;
7dad08d7
VD		 1406 }
1407
1408 return 0;
1409}
1410
fad09c73 1411static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1412 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1413{
fad09c73 1414 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1415}
1416
fad09c73 1417static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1418 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1419{
fad09c73 1420 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1421}
1422
fad09c73 1423static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1424{
a935c052
VD		 1425 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1426 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1427}
1428
fad09c73 1429static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1430 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1431{
b4e47c0f 1432 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1433 u16 val;
1434 int err;
b8fee957 1435
a935c052
VD		 1436 err = _mv88e6xxx_vtu_wait(chip);
1437 if (err)
1438 return err;
b8fee957 1439
a935c052
VD		 1440 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1441 if (err)
1442 return err;
b8fee957 1443
a935c052
VD		 1444 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1445 if (err)
1446 return err;
b8fee957 1447
a935c052
VD		 1448 next.vid = val & GLOBAL_VTU_VID_MASK;
1449 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1450
1451 if (next.valid) {
a935c052
VD		 1452 err = mv88e6xxx_vtu_data_read(chip, &next);
1453 if (err)
1454 return err;
b8fee957 1455
6dc10bbc 1456 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1457 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1458 if (err)
1459 return err;
b8fee957 1460
a935c052 1461 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1462 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1463 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1464 * VTU DBNum[3:0] are located in VTU Operation 3:0
1465 */
a935c052
VD		 1466 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1467 if (err)
1468 return err;
11ea809f 1469
a935c052
VD		 1470 next.fid = (val & 0xf00) >> 4;
1471 next.fid |= val & 0xf;
2e7bd5ef 1472 }
b8fee957 1473
fad09c73 1474 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1475 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1476 if (err)
1477 return err;
b8fee957 1478
a935c052 1479 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1480 }
1481 }
1482
1483 *entry = next;
1484 return 0;
1485}
1486
f81ec90f
VD		 1487static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1488 struct switchdev_obj_port_vlan *vlan,
1489 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1490{
04bed143 1491 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1492 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1493 u16 pvid;
1494 int err;
1495
fad09c73 1496 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1497 return -EOPNOTSUPP;
1498
fad09c73 1499 mutex_lock(&chip->reg_lock);
ceff5eff 1500
77064f37 1501 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1502 if (err)
1503 goto unlock;
1504
fad09c73 1505 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1506 if (err)
1507 goto unlock;
1508
1509 do {
fad09c73 1510 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1511 if (err)
1512 break;
1513
1514 if (!next.valid)
1515 break;
1516
1517 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1518 continue;
1519
1520 /* reinit and dump this VLAN obj */
57d32310
VD		 1521 vlan->vid_begin = next.vid;
1522 vlan->vid_end = next.vid;
ceff5eff
VD		 1523 vlan->flags = 0;
1524
1525 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1526 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1527
1528 if (next.vid == pvid)
1529 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1530
1531 err = cb(&vlan->obj);
1532 if (err)
1533 break;
1534 } while (next.vid < GLOBAL_VTU_VID_MASK);
1535
1536unlock:
fad09c73 1537 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1538
1539 return err;
1540}
1541
fad09c73 1542static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1543 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1544{
11ea809f 1545 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1546 u16 reg = 0;
a935c052 1547 int err;
7dad08d7 1548
a935c052
VD		 1549 err = _mv88e6xxx_vtu_wait(chip);
1550 if (err)
1551 return err;
7dad08d7
VD		 1552
1553 if (!entry->valid)
1554 goto loadpurge;
1555
1556 /* Write port member tags */
a935c052
VD		 1557 err = mv88e6xxx_vtu_data_write(chip, entry);
1558 if (err)
1559 return err;
7dad08d7 1560
fad09c73 1561 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1562 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1563 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1564 if (err)
1565 return err;
b426e5f7 1566 }
7dad08d7 1567
6dc10bbc 1568 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1569 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1570 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1571 if (err)
1572 return err;
fad09c73 1573 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1574 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1575 * VTU DBNum[3:0] are located in VTU Operation 3:0
1576 */
1577 op |= (entry->fid & 0xf0) << 8;
1578 op |= entry->fid & 0xf;
7dad08d7
VD		 1579 }
1580
1581 reg = GLOBAL_VTU_VID_VALID;
1582loadpurge:
1583 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1584 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1585 if (err)
1586 return err;
7dad08d7 1587
fad09c73 1588 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1589}
1590
fad09c73 1591static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1592 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1593{
b4e47c0f 1594 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1595 u16 val;
1596 int err;
0d3b33e6 1597
a935c052
VD		 1598 err = _mv88e6xxx_vtu_wait(chip);
1599 if (err)
1600 return err;
0d3b33e6 1601
a935c052
VD		 1602 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1603 sid & GLOBAL_VTU_SID_MASK);
1604 if (err)
1605 return err;
0d3b33e6 1606
a935c052
VD		 1607 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1608 if (err)
1609 return err;
0d3b33e6 1610
a935c052
VD		 1611 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1612 if (err)
1613 return err;
0d3b33e6 1614
a935c052 1615 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1616
a935c052
VD		 1617 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1618 if (err)
1619 return err;
0d3b33e6 1620
a935c052 1621 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1622
1623 if (next.valid) {
a935c052
VD		 1624 err = mv88e6xxx_stu_data_read(chip, &next);
1625 if (err)
1626 return err;
0d3b33e6
VD		 1627 }
1628
1629 *entry = next;
1630 return 0;
1631}
1632
fad09c73 1633static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1634 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1635{
1636 u16 reg = 0;
a935c052 1637 int err;
0d3b33e6 1638
a935c052
VD		 1639 err = _mv88e6xxx_vtu_wait(chip);
1640 if (err)
1641 return err;
0d3b33e6
VD		 1642
1643 if (!entry->valid)
1644 goto loadpurge;
1645
1646 /* Write port states */
a935c052
VD		 1647 err = mv88e6xxx_stu_data_write(chip, entry);
1648 if (err)
1649 return err;
0d3b33e6
VD		 1650
1651 reg = GLOBAL_VTU_VID_VALID;
1652loadpurge:
a935c052
VD		 1653 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1654 if (err)
1655 return err;
0d3b33e6
VD		 1656
1657 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1658 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1659 if (err)
1660 return err;
0d3b33e6 1661
fad09c73 1662 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1663}
1664
fad09c73 1665static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1666{
1667 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1668 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1669 int i, err;
3285f9e8
VD		 1670
1671 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1672
2db9ce1f 1673 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1674 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1675 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1676 if (err)
1677 return err;
1678
1679 set_bit(*fid, fid_bitmap);
1680 }
1681
3285f9e8 1682 /* Set every FID bit used by the VLAN entries */
fad09c73 1683 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1684 if (err)
1685 return err;
1686
1687 do {
fad09c73 1688 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1689 if (err)
1690 return err;
1691
1692 if (!vlan.valid)
1693 break;
1694
1695 set_bit(vlan.fid, fid_bitmap);
1696 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1697
1698 /* The reset value 0x000 is used to indicate that multiple address
1699 * databases are not needed. Return the next positive available.
1700 */
1701 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1702 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1703 return -ENOSPC;
1704
1705 /* Clear the database */
fad09c73 1706 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1707}
1708
fad09c73 1709static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1710 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1711{
fad09c73 1712 struct dsa_switch *ds = chip->ds;
b4e47c0f 1713 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1714 .valid = true,
1715 .vid = vid,
1716 };
3285f9e8
VD		 1717 int i, err;
1718
fad09c73 1719 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1720 if (err)
1721 return err;
0d3b33e6 1722
3d131f07 1723 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1724 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1725 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1726 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1727 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1728
fad09c73 1729 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
a75961d0
GC		 1730 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1731 mv88e6xxx_6341_family(chip)) {
b4e47c0f 1732 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1733
1734 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1735 * implemented, only one STU entry is needed to cover all VTU
1736 * entries. Thus, validate the SID 0.
1737 */
1738 vlan.sid = 0;
fad09c73 1739 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1740 if (err)
1741 return err;
1742
1743 if (vstp.sid != vlan.sid || !vstp.valid) {
1744 memset(&vstp, 0, sizeof(vstp));
1745 vstp.valid = true;
1746 vstp.sid = vlan.sid;
1747
fad09c73 1748 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1749 if (err)
1750 return err;
1751 }
0d3b33e6
VD		 1752 }
1753
1754 *entry = vlan;
1755 return 0;
1756}
1757
fad09c73 1758static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1759 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1760{
1761 int err;
1762
1763 if (!vid)
1764 return -EINVAL;
1765
fad09c73 1766 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1767 if (err)
1768 return err;
1769
fad09c73 1770 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1771 if (err)
1772 return err;
1773
1774 if (entry->vid != vid || !entry->valid) {
1775 if (!creat)
1776 return -EOPNOTSUPP;
1777 /* -ENOENT would've been more appropriate, but switchdev expects
1778 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1779 */
1780
fad09c73 1781 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1782 }
1783
1784 return err;
1785}
1786
da9c359e
VD		 1787static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1788 u16 vid_begin, u16 vid_end)
1789{
04bed143 1790 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1791 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1792 int i, err;
1793
1794 if (!vid_begin)
1795 return -EOPNOTSUPP;
1796
fad09c73 1797 mutex_lock(&chip->reg_lock);
da9c359e 1798
fad09c73 1799 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1800 if (err)
1801 goto unlock;
1802
1803 do {
fad09c73 1804 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1805 if (err)
1806 goto unlock;
1807
1808 if (!vlan.valid)
1809 break;
1810
1811 if (vlan.vid > vid_end)
1812 break;
1813
370b4ffb 1814 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1815 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1816 continue;
1817
66e2809d
AL		 1818 if (!ds->ports[port].netdev)
1819 continue;
1820
da9c359e
VD		 1821 if (vlan.data[i] ==
1822 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1823 continue;
1824
fae8a25e
VD		 1825 if (ds->ports[i].bridge_dev ==
1826 ds->ports[port].bridge_dev)
da9c359e
VD		 1827 break; /* same bridge, check next VLAN */
1828
fae8a25e 1829 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1830 continue;
1831
c8b09808 1832 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1833 "hardware VLAN %d already used by %s\n",
1834 vlan.vid,
fae8a25e 1835 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1836 err = -EOPNOTSUPP;
1837 goto unlock;
1838 }
1839 } while (vlan.vid < vid_end);
1840
1841unlock:
fad09c73 1842 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1843
1844 return err;
1845}
1846
f81ec90f
VD		 1847static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1848 bool vlan_filtering)
214cdb99 1849{
04bed143 1850 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1851 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1852 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1853 int err;
214cdb99 1854
fad09c73 1855 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1856 return -EOPNOTSUPP;
1857
fad09c73 1858 mutex_lock(&chip->reg_lock);
385a0995 1859 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1860 mutex_unlock(&chip->reg_lock);
214cdb99 1861
0e7b9925 1862 return err;
214cdb99
VD		 1863}
1864
57d32310
VD		 1865static int
1866mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1867 const struct switchdev_obj_port_vlan *vlan,
1868 struct switchdev_trans *trans)
76e398a6 1869{
04bed143 1870 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1871 int err;
1872
fad09c73 1873 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1874 return -EOPNOTSUPP;
1875
da9c359e
VD		 1876 /* If the requested port doesn't belong to the same bridge as the VLAN
1877 * members, do not support it (yet) and fallback to software VLAN.
1878 */
1879 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1880 vlan->vid_end);
1881 if (err)
1882 return err;
1883
76e398a6
VD		 1884 /* We don't need any dynamic resource from the kernel (yet),
1885 * so skip the prepare phase.
1886 */
1887 return 0;
1888}
1889
fad09c73 1890static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1891 u16 vid, bool untagged)
0d3b33e6 1892{
b4e47c0f 1893 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1894 int err;
1895
fad09c73 1896 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1897 if (err)
76e398a6 1898 return err;
0d3b33e6 1899
0d3b33e6
VD		 1900 vlan.data[port] = untagged ?
1901 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1902 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1903
fad09c73 1904 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1905}
1906
f81ec90f
VD		 1907static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1908 const struct switchdev_obj_port_vlan *vlan,
1909 struct switchdev_trans *trans)
76e398a6 1910{
04bed143 1911 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1912 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1913 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1914 u16 vid;
76e398a6 1915
fad09c73 1916 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1917 return;
1918
fad09c73 1919 mutex_lock(&chip->reg_lock);
76e398a6 1920
4d5770b3 1921 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1922 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1923 netdev_err(ds->ports[port].netdev,
1924 "failed to add VLAN %d%c\n",
4d5770b3 1925 vid, untagged ? 'u' : 't');
76e398a6 1926
77064f37 1927 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1928 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1929 vlan->vid_end);
0d3b33e6 1930
fad09c73 1931 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1932}
1933
fad09c73 1934static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1935 int port, u16 vid)
7dad08d7 1936{
fad09c73 1937 struct dsa_switch *ds = chip->ds;
b4e47c0f 1938 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1939 int i, err;
1940
fad09c73 1941 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1942 if (err)
76e398a6 1943 return err;
7dad08d7 1944
2fb5ef09
VD		 1945 /* Tell switchdev if this VLAN is handled in software */
1946 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1947 return -EOPNOTSUPP;
7dad08d7
VD		 1948
1949 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1950
1951 /* keep the VLAN unless all ports are excluded */
f02bdffc 1952 vlan.valid = false;
370b4ffb 1953 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1954 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1955 continue;
1956
1957 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1958 vlan.valid = true;
7dad08d7
VD		 1959 break;
1960 }
1961 }
1962
fad09c73 1963 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1964 if (err)
1965 return err;
1966
fad09c73 1967 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1968}
1969
f81ec90f
VD		 1970static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1971 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1972{
04bed143 1973 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1974 u16 pvid, vid;
1975 int err = 0;
1976
fad09c73 1977 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1978 return -EOPNOTSUPP;
1979
fad09c73 1980 mutex_lock(&chip->reg_lock);
76e398a6 1981
77064f37 1982 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1983 if (err)
1984 goto unlock;
1985
76e398a6 1986 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1987 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1988 if (err)
1989 goto unlock;
1990
1991 if (vid == pvid) {
77064f37 1992 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1993 if (err)
1994 goto unlock;
1995 }
1996 }
1997
7dad08d7 1998unlock:
fad09c73 1999 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2000
2001 return err;
2002}
2003
fad09c73 2004static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2005 const unsigned char *addr)
defb05b9 2006{
a935c052 2007 int i, err;
defb05b9
GR		 2008
2009 for (i = 0; i < 3; i++) {
a935c052
VD		 2010 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2011 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2012 if (err)
2013 return err;
defb05b9
GR		 2014 }
2015
2016 return 0;
2017}
2018
fad09c73 2019static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2020 unsigned char *addr)
defb05b9 2021{
a935c052
VD		 2022 u16 val;
2023 int i, err;
defb05b9
GR		 2024
2025 for (i = 0; i < 3; i++) {
a935c052
VD		 2026 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2027 if (err)
2028 return err;
2029
2030 addr[i * 2] = val >> 8;
2031 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2032 }
2033
2034 return 0;
2035}
2036
fad09c73 2037static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2038 struct mv88e6xxx_atu_entry *entry)
defb05b9 2039{
6630e236
VD		 2040 int ret;
2041
fad09c73 2042 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2043 if (ret < 0)
2044 return ret;
2045
fad09c73 2046 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2047 if (ret < 0)
2048 return ret;
2049
fad09c73 2050 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2051 if (ret < 0)
87820510
VD		 2052 return ret;
2053
fad09c73 2054 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2055}
87820510 2056
88472939
VD		 2057static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2058 struct mv88e6xxx_atu_entry *entry);
2059
2060static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2061 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2062{
2063 struct mv88e6xxx_atu_entry next;
2064 int err;
2065
59527581
AL		 2066 memcpy(next.mac, addr, ETH_ALEN);
2067 eth_addr_dec(next.mac);
88472939
VD		 2068
2069 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2070 if (err)
2071 return err;
2072
2073 do {
2074 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2075 if (err)
2076 return err;
2077
2078 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2079 break;
2080
2081 if (ether_addr_equal(next.mac, addr)) {
2082 *entry = next;
2083 return 0;
2084 }
59527581 2085 } while (ether_addr_greater(addr, next.mac));
88472939
VD		 2086
2087 memset(entry, 0, sizeof(*entry));
2088 entry->fid = fid;
2089 ether_addr_copy(entry->mac, addr);
2090
2091 return 0;
2092}
2093
83dabd1f
VD		 2094static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2095 const unsigned char *addr, u16 vid,
2096 u8 state)
fd231c82 2097{
b4e47c0f 2098 struct mv88e6xxx_vtu_entry vlan;
88472939 2099 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2100 int err;
2101
2db9ce1f
VD		 2102 /* Null VLAN ID corresponds to the port private database */
2103 if (vid == 0)
b4e48c50 2104 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2105 else
fad09c73 2106 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2107 if (err)
2108 return err;
fd231c82 2109
88472939
VD		 2110 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2111 if (err)
2112 return err;
2113
2114 /* Purge the ATU entry only if no port is using it anymore */
2115 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2116 entry.portv_trunkid &= ~BIT(port);
2117 if (!entry.portv_trunkid)
2118 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2119 } else {
2120 entry.portv_trunkid |= BIT(port);
2121 entry.state = state;
fd231c82
VD		 2122 }
2123
fad09c73 2124 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2125}
2126
f81ec90f
VD		 2127static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2128 const struct switchdev_obj_port_fdb *fdb,
2129 struct switchdev_trans *trans)
146a3206
VD		 2130{
2131 /* We don't need any dynamic resource from the kernel (yet),
2132 * so skip the prepare phase.
2133 */
2134 return 0;
2135}
2136
f81ec90f
VD		 2137static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2138 const struct switchdev_obj_port_fdb *fdb,
2139 struct switchdev_trans *trans)
87820510 2140{
04bed143 2141 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2142
fad09c73 2143 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2144 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2145 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2146 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2147 mutex_unlock(&chip->reg_lock);
87820510
VD		 2148}
2149
f81ec90f
VD		 2150static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2151 const struct switchdev_obj_port_fdb *fdb)
87820510 2152{
04bed143 2153 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2154 int err;
87820510 2155
fad09c73 2156 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2157 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2158 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2159 mutex_unlock(&chip->reg_lock);
87820510 2160
83dabd1f 2161 return err;
87820510
VD		 2162}
2163
fad09c73 2164static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2165 struct mv88e6xxx_atu_entry *entry)
6630e236 2166{
1d194046 2167 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2168 u16 val;
2169 int err;
1d194046
VD		 2170
2171 next.fid = fid;
defb05b9 2172
a935c052
VD		 2173 err = _mv88e6xxx_atu_wait(chip);
2174 if (err)
2175 return err;
6630e236 2176
a935c052
VD		 2177 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2178 if (err)
2179 return err;
6630e236 2180
a935c052
VD		 2181 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2182 if (err)
2183 return err;
6630e236 2184
a935c052
VD		 2185 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2186 if (err)
2187 return err;
6630e236 2188
a935c052 2189 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2190 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2191 unsigned int mask, shift;
2192
a935c052 2193 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2194 next.trunk = true;
2195 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2196 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2197 } else {
2198 next.trunk = false;
2199 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2200 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2201 }
2202
a935c052 2203 next.portv_trunkid = (val & mask) >> shift;
1d194046 2204 }
cdf09697 2205
1d194046 2206 *entry = next;
cdf09697
DM		 2207 return 0;
2208}
2209
83dabd1f
VD		 2210static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2211 u16 fid, u16 vid, int port,
2212 struct switchdev_obj *obj,
2213 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2214{
2215 struct mv88e6xxx_atu_entry addr = {
2216 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2217 };
2218 int err;
2219
fad09c73 2220 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2221 if (err)
2222 return err;
2223
2224 do {
fad09c73 2225 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2226 if (err)
83dabd1f 2227 return err;
74b6ba0d
VD		 2228
2229 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2230 break;
2231
83dabd1f
VD		 2232 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2233 continue;
2234
2235 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2236 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2237
83dabd1f
VD		 2238 if (!is_unicast_ether_addr(addr.mac))
2239 continue;
2240
2241 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2242 fdb->vid = vid;
2243 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2244 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2245 fdb->ndm_state = NUD_NOARP;
2246 else
2247 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2248 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2249 struct switchdev_obj_port_mdb *mdb;
2250
2251 if (!is_multicast_ether_addr(addr.mac))
2252 continue;
2253
2254 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2255 mdb->vid = vid;
2256 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2257 } else {
2258 return -EOPNOTSUPP;
74b6ba0d 2259 }
83dabd1f
VD		 2260
2261 err = cb(obj);
2262 if (err)
2263 return err;
74b6ba0d
VD		 2264 } while (!is_broadcast_ether_addr(addr.mac));
2265
2266 return err;
2267}
2268
83dabd1f
VD		 2269static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2270 struct switchdev_obj *obj,
2271 int (*cb)(struct switchdev_obj *obj))
f33475bd 2272{
b4e47c0f 2273 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2274 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2275 };
2db9ce1f 2276 u16 fid;
f33475bd
VD		 2277 int err;
2278
2db9ce1f 2279 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2280 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2281 if (err)
83dabd1f 2282 return err;
2db9ce1f 2283
83dabd1f 2284 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2285 if (err)
83dabd1f 2286 return err;
2db9ce1f 2287
74b6ba0d 2288 /* Dump VLANs' Filtering Information Databases */
fad09c73 2289 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2290 if (err)
83dabd1f 2291 return err;
f33475bd
VD		 2292
2293 do {
fad09c73 2294 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2295 if (err)
83dabd1f 2296 return err;
f33475bd
VD		 2297
2298 if (!vlan.valid)
2299 break;
2300
83dabd1f
VD		 2301 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2302 obj, cb);
f33475bd 2303 if (err)
83dabd1f 2304 return err;
f33475bd
VD		 2305 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2306
83dabd1f
VD		 2307 return err;
2308}
2309
2310static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2311 struct switchdev_obj_port_fdb *fdb,
2312 int (*cb)(struct switchdev_obj *obj))
2313{
04bed143 2314 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2315 int err;
2316
2317 mutex_lock(&chip->reg_lock);
2318 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2319 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2320
2321 return err;
2322}
2323
f81ec90f 2324static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
fae8a25e 2325 struct net_device *br)
e79a8bcb 2326{
04bed143 2327 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2328 int i, err = 0;
466dfa07 2329
fad09c73 2330 mutex_lock(&chip->reg_lock);
466dfa07 2331
fae8a25e 2332 /* Remap each port's VLANTable */
370b4ffb 2333 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fae8a25e 2334 if (ds->ports[i].bridge_dev == br) {
fad09c73 2335 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2336 if (err)
2337 break;
2338 }
2339 }
2340
fad09c73 2341 mutex_unlock(&chip->reg_lock);
a6692754 2342
466dfa07 2343 return err;
e79a8bcb
VD		 2344}
2345
f123f2fb
VD		 2346static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2347 struct net_device *br)
66d9cd0f 2348{
04bed143 2349 struct mv88e6xxx_chip *chip = ds->priv;
16bfa702 2350 int i;
466dfa07 2351
fad09c73 2352 mutex_lock(&chip->reg_lock);
466dfa07 2353
fae8a25e 2354 /* Remap each port's VLANTable */
370b4ffb 2355 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fae8a25e 2356 if (i == port || ds->ports[i].bridge_dev == br)
fad09c73 2357 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2358 netdev_warn(ds->ports[i].netdev,
2359 "failed to remap\n");
b7666efe 2360
fad09c73 2361 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2362}
2363
17e708ba
VD		 2364static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2365{
2366 if (chip->info->ops->reset)
2367 return chip->info->ops->reset(chip);
2368
2369 return 0;
2370}
2371
309eca6d
VD		 2372static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2373{
2374 struct gpio_desc *gpiod = chip->reset;
2375
2376 /* If there is a GPIO connected to the reset pin, toggle it */
2377 if (gpiod) {
2378 gpiod_set_value_cansleep(gpiod, 1);
2379 usleep_range(10000, 20000);
2380 gpiod_set_value_cansleep(gpiod, 0);
2381 usleep_range(10000, 20000);
2382 }
2383}
2384
4ac4b5a6 2385static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2386{
4ac4b5a6 2387 int i, err;
552238b5 2388
4ac4b5a6 2389 /* Set all ports to the Disabled state */
370b4ffb 2390 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2391 err = mv88e6xxx_port_set_state(chip, i,
2392 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2393 if (err)
2394 return err;
552238b5
VD		 2395 }
2396
4ac4b5a6
VD		 2397 /* Wait for transmit queues to drain,
2398 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2399 */
552238b5
VD		 2400 usleep_range(2000, 4000);
2401
4ac4b5a6
VD		 2402 return 0;
2403}
2404
2405static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2406{
4ac4b5a6
VD		 2407 int err;
2408
2409 err = mv88e6xxx_disable_ports(chip);
2410 if (err)
2411 return err;
2412
309eca6d 2413 mv88e6xxx_hardware_reset(chip);
552238b5 2414
17e708ba 2415 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2416}
2417
09cb7dfd 2418static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2419{
09cb7dfd
VD		 2420 u16 val;
2421 int err;
13a7ebb3 2422
09cb7dfd
VD		 2423 /* Clear Power Down bit */
2424 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2425 if (err)
2426 return err;
13a7ebb3 2427
09cb7dfd
VD		 2428 if (val & BMCR_PDOWN) {
2429 val &= ~BMCR_PDOWN;
2430 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2431 }
2432
09cb7dfd 2433 return err;
13a7ebb3
PU		 2434}
2435
56995cbc
AL		 2436static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2437 int upstream_port)
2438{
2439 int err;
2440
2441 err = chip->info->ops->port_set_frame_mode(
2442 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2443 if (err)
2444 return err;
2445
2446 return chip->info->ops->port_set_egress_unknowns(
2447 chip, port, port == upstream_port);
2448}
2449
2450static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2451{
2452 int err;
2453
2454 switch (chip->info->tag_protocol) {
2455 case DSA_TAG_PROTO_EDSA:
2456 err = chip->info->ops->port_set_frame_mode(
2457 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2458 if (err)
2459 return err;
2460
2461 err = mv88e6xxx_port_set_egress_mode(
2462 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2463 if (err)
2464 return err;
2465
2466 if (chip->info->ops->port_set_ether_type)
2467 err = chip->info->ops->port_set_ether_type(
2468 chip, port, ETH_P_EDSA);
2469 break;
2470
2471 case DSA_TAG_PROTO_DSA:
2472 err = chip->info->ops->port_set_frame_mode(
2473 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2474 if (err)
2475 return err;
2476
2477 err = mv88e6xxx_port_set_egress_mode(
2478 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2479 break;
2480 default:
2481 err = -EINVAL;
2482 }
2483
2484 if (err)
2485 return err;
2486
2487 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2488}
2489
2490static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2491{
2492 int err;
2493
2494 err = chip->info->ops->port_set_frame_mode(
2495 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2496 if (err)
2497 return err;
2498
2499 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2500}
2501
fad09c73 2502static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2503{
fad09c73 2504 struct dsa_switch *ds = chip->ds;
0e7b9925 2505 int err;
54d792f2 2506 u16 reg;
d827e88a 2507
d78343d2
VD		 2508 /* MAC Forcing register: don't force link, speed, duplex or flow control
2509 * state to any particular values on physical ports, but force the CPU
2510 * port and all DSA ports to their maximum bandwidth and full duplex.
2511 */
2512 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2513 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2514 SPEED_MAX, DUPLEX_FULL,
2515 PHY_INTERFACE_MODE_NA);
2516 else
2517 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2518 SPEED_UNFORCED, DUPLEX_UNFORCED,
2519 PHY_INTERFACE_MODE_NA);
2520 if (err)
2521 return err;
54d792f2
AL		 2522
2523 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2524 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2525 * tunneling, determine priority by looking at 802.1p and IP
2526 * priority fields (IP prio has precedence), and set STP state
2527 * to Forwarding.
2528 *
2529 * If this is the CPU link, use DSA or EDSA tagging depending
2530 * on which tagging mode was configured.
2531 *
2532 * If this is a link to another switch, use DSA tagging mode.
2533 *
2534 * If this is the upstream port for this switch, enable
2535 * forwarding of unknown unicasts and multicasts.
2536 */
56995cbc 2537 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2538 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2539 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2540 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2541 if (err)
2542 return err;
6083ce71 2543
56995cbc
AL		 2544 if (dsa_is_cpu_port(ds, port)) {
2545 err = mv88e6xxx_setup_port_cpu(chip, port);
2546 } else if (dsa_is_dsa_port(ds, port)) {
2547 err = mv88e6xxx_setup_port_dsa(chip, port,
2548 dsa_upstream_port(ds));
2549 } else {
2550 err = mv88e6xxx_setup_port_normal(chip, port);
54d792f2 2551 }
56995cbc
AL		 2552 if (err)
2553 return err;
54d792f2 2554
13a7ebb3
PU		 2555 /* If this port is connected to a SerDes, make sure the SerDes is not
2556 * powered down.
2557 */
09cb7dfd 2558 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2559 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2560 if (err)
2561 return err;
2562 reg &= PORT_STATUS_CMODE_MASK;
2563 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2564 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2565 (reg == PORT_STATUS_CMODE_SGMII)) {
2566 err = mv88e6xxx_serdes_power_on(chip);
2567 if (err < 0)
2568 return err;
13a7ebb3
PU		 2569 }
2570 }
2571
8efdda4a 2572 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2573 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2574 * untagged frames on this port, do a destination address lookup on all
2575 * received packets as usual, disable ARP mirroring and don't send a
2576 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2577 */
a23b2961
AL		 2578 err = mv88e6xxx_port_set_map_da(chip, port);
2579 if (err)
2580 return err;
8efdda4a 2581
a23b2961
AL		 2582 reg = 0;
2583 if (chip->info->ops->port_set_upstream_port) {
2584 err = chip->info->ops->port_set_upstream_port(
2585 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 2586 if (err)
2587 return err;
54d792f2
AL		 2588 }
2589
a23b2961
AL		 2590 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2591 PORT_CONTROL_2_8021Q_DISABLED);
2592 if (err)
2593 return err;
2594
5f436666
AL		 2595 if (chip->info->ops->port_jumbo_config) {
2596 err = chip->info->ops->port_jumbo_config(chip, port);
2597 if (err)
2598 return err;
2599 }
2600
54d792f2
AL		 2601 /* Port Association Vector: when learning source addresses
2602 * of packets, add the address to the address database using
2603 * a port bitmap that has only the bit for this port set and
2604 * the other bits clear.
2605 */
4c7ea3c0 2606 reg = 1 << port;
996ecb82
VD		 2607 /* Disable learning for CPU port */
2608 if (dsa_is_cpu_port(ds, port))
65fa4027 2609 reg = 0;
4c7ea3c0 2610
0e7b9925
AL		 2611 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2612 if (err)
2613 return err;
54d792f2
AL		 2614
2615 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2616 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2617 if (err)
2618 return err;
54d792f2 2619
b35d322a
AL		 2620 if (chip->info->ops->port_pause_config) {
2621 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2622 if (err)
2623 return err;
b35d322a 2624 }
54d792f2 2625
b35d322a
AL		 2626 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2627 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
a75961d0 2628 mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) {
54d792f2
AL		 2629 /* Port ATU control: disable limiting the number of
2630 * address database entries that this port is allowed
2631 * to use.
2632 */
0e7b9925
AL		 2633 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2634 0x0000);
54d792f2
AL		 2635 /* Priority Override: disable DA, SA and VTU priority
2636 * override.
2637 */
0e7b9925
AL		 2638 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2639 0x0000);
2640 if (err)
2641 return err;
ef0a7318 2642 }
2bbb33be 2643
ef0a7318
AL		 2644 if (chip->info->ops->port_tag_remap) {
2645 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2646 if (err)
2647 return err;
54d792f2
AL		 2648 }
2649
ef70b111
AL		 2650 if (chip->info->ops->port_egress_rate_limiting) {
2651 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2652 if (err)
2653 return err;
54d792f2
AL		 2654 }
2655
366f0a0f
GR		 2656 /* Port Control 1: disable trunking, disable sending
2657 * learning messages to this port.
d827e88a 2658 */
0e7b9925
AL		 2659 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2660 if (err)
2661 return err;
d827e88a 2662
207afda1 2663 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2664 * database, and allow bidirectional communication between the
2665 * CPU and DSA port(s), and the other ports.
d827e88a 2666 */
b4e48c50 2667 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2668 if (err)
2669 return err;
2db9ce1f 2670
0e7b9925
AL		 2671 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2672 if (err)
2673 return err;
d827e88a
GR		 2674
2675 /* Default VLAN ID and priority: don't set a default VLAN
2676 * ID, and set the default packet priority to zero.
2677 */
0e7b9925 2678 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2679}
2680
aa0938c6 2681static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2682{
2683 int err;
2684
a935c052 2685 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2686 if (err)
2687 return err;
2688
a935c052 2689 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2690 if (err)
2691 return err;
2692
a935c052
VD		 2693 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2694 if (err)
2695 return err;
2696
2697 return 0;
3b4caa1b
VD		 2698}
2699
acddbd21
VD		 2700static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2701 unsigned int msecs)
2702{
2703 const unsigned int coeff = chip->info->age_time_coeff;
2704 const unsigned int min = 0x01 * coeff;
2705 const unsigned int max = 0xff * coeff;
2706 u8 age_time;
2707 u16 val;
2708 int err;
2709
2710 if (msecs < min || msecs > max)
2711 return -ERANGE;
2712
2713 /* Round to nearest multiple of coeff */
2714 age_time = (msecs + coeff / 2) / coeff;
2715
a935c052 2716 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2717 if (err)
2718 return err;
2719
2720 /* AgeTime is 11:4 bits */
2721 val &= ~0xff0;
2722 val |= age_time << 4;
2723
a935c052 2724 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2725}
2726
2cfcd964
VD		 2727static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2728 unsigned int ageing_time)
2729{
04bed143 2730 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2731 int err;
2732
2733 mutex_lock(&chip->reg_lock);
2734 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2735 mutex_unlock(&chip->reg_lock);
2736
2737 return err;
2738}
2739
9729934c 2740static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2741{
fad09c73 2742 struct dsa_switch *ds = chip->ds;
b0745e87 2743 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2744 int err;
54d792f2 2745
119477bd
VD		 2746 /* Enable the PHY Polling Unit if present, don't discard any packets,
2747 * and mask all interrupt sources.
2748 */
a199d8b6 2749 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2750 if (err)
2751 return err;
2752
33641994
AL		 2753 if (chip->info->ops->g1_set_cpu_port) {
2754 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2755 if (err)
2756 return err;
2757 }
2758
2759 if (chip->info->ops->g1_set_egress_port) {
2760 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2761 if (err)
2762 return err;
2763 }
b0745e87 2764
50484ff4 2765 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2766 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2767 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2768 (ds->index & 0x1f));
50484ff4
VD		 2769 if (err)
2770 return err;
2771
acddbd21
VD		 2772 /* Clear all the VTU and STU entries */
2773 err = _mv88e6xxx_vtu_stu_flush(chip);
2774 if (err < 0)
2775 return err;
2776
54d792f2
AL		 2777 /* Set the default address aging time to 5 minutes, and
2778 * enable address learn messages to be sent to all message
2779 * ports.
2780 */
a935c052
VD		 2781 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2782 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2783 if (err)
08a01261 2784 return err;
54d792f2 2785
acddbd21
VD		 2786 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2787 if (err)
9729934c
VD		 2788 return err;
2789
2790 /* Clear all ATU entries */
2791 err = _mv88e6xxx_atu_flush(chip, 0, true);
2792 if (err)
2793 return err;
2794
54d792f2 2795 /* Configure the IP ToS mapping registers. */
a935c052 2796 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2797 if (err)
08a01261 2798 return err;
a935c052 2799 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2800 if (err)
08a01261 2801 return err;
a935c052 2802 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2803 if (err)
08a01261 2804 return err;
a935c052 2805 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2806 if (err)
08a01261 2807 return err;
a935c052 2808 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2809 if (err)
08a01261 2810 return err;
a935c052 2811 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2812 if (err)
08a01261 2813 return err;
a935c052 2814 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2815 if (err)
08a01261 2816 return err;
a935c052 2817 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2818 if (err)
08a01261 2819 return err;
54d792f2
AL		 2820
2821 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2822 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2823 if (err)
08a01261 2824 return err;
54d792f2 2825
de227387
AL		 2826 /* Initialize the statistics unit */
2827 err = mv88e6xxx_stats_set_histogram(chip);
2828 if (err)
2829 return err;
2830
9729934c 2831 /* Clear the statistics counters for all ports */
a935c052
VD		 2832 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2833 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2834 if (err)
2835 return err;
2836
2837 /* Wait for the flush to complete. */
7f9ef3af 2838 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2839 if (err)
2840 return err;
2841
2842 return 0;
2843}
2844
f81ec90f 2845static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2846{
04bed143 2847 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2848 int err;
a1a6a4d1
VD		 2849 int i;
2850
fad09c73 2851 chip->ds = ds;
a3c53be5 2852 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2853
fad09c73 2854 mutex_lock(&chip->reg_lock);
08a01261 2855
9729934c 2856 /* Setup Switch Port Registers */
370b4ffb 2857 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2858 err = mv88e6xxx_setup_port(chip, i);
2859 if (err)
2860 goto unlock;
2861 }
2862
2863 /* Setup Switch Global 1 Registers */
2864 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2865 if (err)
2866 goto unlock;
2867
9729934c
VD		 2868 /* Setup Switch Global 2 Registers */
2869 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2870 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2871 if (err)
2872 goto unlock;
2873 }
08a01261 2874
6e55f698
AL		 2875 /* Some generations have the configuration of sending reserved
2876 * management frames to the CPU in global2, others in
2877 * global1. Hence it does not fit the two setup functions
2878 * above.
2879 */
2880 if (chip->info->ops->mgmt_rsvd2cpu) {
2881 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2882 if (err)
2883 goto unlock;
2884 }
2885
6b17e864 2886unlock:
fad09c73 2887 mutex_unlock(&chip->reg_lock);
db687a56 2888
48ace4ef 2889 return err;
54d792f2
AL		 2890}
2891
3b4caa1b
VD		 2892static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2893{
04bed143 2894 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2895 int err;
2896
b073d4e2
VD		 2897 if (!chip->info->ops->set_switch_mac)
2898 return -EOPNOTSUPP;
3b4caa1b 2899
b073d4e2
VD		 2900 mutex_lock(&chip->reg_lock);
2901 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2902 mutex_unlock(&chip->reg_lock);
2903
2904 return err;
2905}
2906
e57e5e77 2907static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2908{
0dd12d54
AL		 2909 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2910 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2911 u16 val;
2912 int err;
fd3a0ee4 2913
ee26a228
AL		 2914 if (!chip->info->ops->phy_read)
2915 return -EOPNOTSUPP;
2916
fad09c73 2917 mutex_lock(&chip->reg_lock);
ee26a228 2918 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2919 mutex_unlock(&chip->reg_lock);
e57e5e77 2920
da9f3301
AL		 2921 if (reg == MII_PHYSID2) {
2922 /* Some internal PHYS don't have a model number. Use
2923 * the mv88e6390 family model number instead.
2924 */
2925 if (!(val & 0x3f0))
2926 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2927 }
2928
e57e5e77 2929 return err ? err : val;
fd3a0ee4
AL		 2930}
2931
e57e5e77 2932static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2933{
0dd12d54
AL		 2934 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2935 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2936 int err;
fd3a0ee4 2937
ee26a228
AL		 2938 if (!chip->info->ops->phy_write)
2939 return -EOPNOTSUPP;
2940
fad09c73 2941 mutex_lock(&chip->reg_lock);
ee26a228 2942 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2943 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2944
2945 return err;
fd3a0ee4
AL		 2946}
2947
fad09c73 2948static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2949 struct device_node *np,
2950 bool external)
b516d453
AL		 2951{
2952 static int index;
0dd12d54 2953 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2954 struct mii_bus *bus;
2955 int err;
2956
0dd12d54 2957 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2958 if (!bus)
2959 return -ENOMEM;
2960
0dd12d54 2961 mdio_bus = bus->priv;
a3c53be5 2962 mdio_bus->bus = bus;
0dd12d54 2963 mdio_bus->chip = chip;
a3c53be5
AL		 2964 INIT_LIST_HEAD(&mdio_bus->list);
2965 mdio_bus->external = external;
0dd12d54 2966
b516d453
AL		 2967 if (np) {
2968 bus->name = np->full_name;
2969 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2970 } else {
2971 bus->name = "mv88e6xxx SMI";
2972 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2973 }
2974
2975 bus->read = mv88e6xxx_mdio_read;
2976 bus->write = mv88e6xxx_mdio_write;
fad09c73 2977 bus->parent = chip->dev;
b516d453 2978
a3c53be5
AL		 2979 if (np)
2980 err = of_mdiobus_register(bus, np);
b516d453
AL		 2981 else
2982 err = mdiobus_register(bus);
2983 if (err) {
fad09c73 2984 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2985 return err;
b516d453 2986 }
a3c53be5
AL		 2987
2988 if (external)
2989 list_add_tail(&mdio_bus->list, &chip->mdios);
2990 else
2991 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2992
2993 return 0;
a3c53be5 2994}
b516d453 2995
a3c53be5
AL		 2996static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2997 { .compatible = "marvell,mv88e6xxx-mdio-external",
2998 .data = (void *)true },
2999 { },
3000};
b516d453 3001
a3c53be5
AL		 3002static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3003 struct device_node *np)
3004{
3005 const struct of_device_id *match;
3006 struct device_node *child;
3007 int err;
3008
3009 /* Always register one mdio bus for the internal/default mdio
3010 * bus. This maybe represented in the device tree, but is
3011 * optional.
3012 */
3013 child = of_get_child_by_name(np, "mdio");
3014 err = mv88e6xxx_mdio_register(chip, child, false);
3015 if (err)
3016 return err;
3017
3018 /* Walk the device tree, and see if there are any other nodes
3019 * which say they are compatible with the external mdio
3020 * bus.
3021 */
3022 for_each_available_child_of_node(np, child) {
3023 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3024 if (match) {
3025 err = mv88e6xxx_mdio_register(chip, child, true);
3026 if (err)
3027 return err;
3028 }
3029 }
3030
3031 return 0;
b516d453
AL		 3032}
3033
a3c53be5 3034static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3035
3036{
a3c53be5
AL		 3037 struct mv88e6xxx_mdio_bus *mdio_bus;
3038 struct mii_bus *bus;
b516d453 3039
a3c53be5
AL		 3040 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3041 bus = mdio_bus->bus;
b516d453 3042
a3c53be5
AL		 3043 mdiobus_unregister(bus);
3044 }
b516d453
AL		 3045}
3046
855b1932
VD		 3047static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3048{
04bed143 3049 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3050
3051 return chip->eeprom_len;
3052}
3053
855b1932
VD		 3054static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3055 struct ethtool_eeprom *eeprom, u8 *data)
3056{
04bed143 3057 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3058 int err;
3059
ee4dc2e7
VD		 3060 if (!chip->info->ops->get_eeprom)
3061 return -EOPNOTSUPP;
855b1932 3062
ee4dc2e7
VD		 3063 mutex_lock(&chip->reg_lock);
3064 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3065 mutex_unlock(&chip->reg_lock);
3066
3067 if (err)
3068 return err;
3069
3070 eeprom->magic = 0xc3ec4951;
3071
3072 return 0;
3073}
3074
855b1932
VD		 3075static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3076 struct ethtool_eeprom *eeprom, u8 *data)
3077{
04bed143 3078 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3079 int err;
3080
ee4dc2e7
VD		 3081 if (!chip->info->ops->set_eeprom)
3082 return -EOPNOTSUPP;
3083
855b1932
VD		 3084 if (eeprom->magic != 0xc3ec4951)
3085 return -EINVAL;
3086
3087 mutex_lock(&chip->reg_lock);
ee4dc2e7 3088 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3089 mutex_unlock(&chip->reg_lock);
3090
3091 return err;
3092}
3093
b3469dd8 3094static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3095 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3096 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3097 .phy_read = mv88e6xxx_phy_ppu_read,
3098 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3099 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3100 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3101 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3102 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3103 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3104 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3105 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3106 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3107 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3108 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3109 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3110 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3111 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3112 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3113 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3114 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3115 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3116 .ppu_enable = mv88e6185_g1_ppu_enable,
3117 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3118 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3119};
3120
3121static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3122 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3123 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3124 .phy_read = mv88e6xxx_phy_ppu_read,
3125 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3126 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3127 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3128 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3129 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a23b2961
AL		 3130 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
3131 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3132 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3133 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3134 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3135 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 3136 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3137 .ppu_enable = mv88e6185_g1_ppu_enable,
3138 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3139 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3140};
3141
7d381a02 3142static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3143 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 3144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3145 .phy_read = mv88e6xxx_g2_smi_phy_read,
3146 .phy_write = mv88e6xxx_g2_smi_phy_write,
3147 .port_set_link = mv88e6xxx_port_set_link,
3148 .port_set_duplex = mv88e6xxx_port_set_duplex,
3149 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3150 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3151 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3152 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3153 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3154 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3155 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 3156 .port_pause_config = mv88e6097_port_pause_config,
7d381a02
SE		 3157 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3158 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3159 .stats_get_strings = mv88e6095_stats_get_strings,
3160 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3161 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3162 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 3163 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3164 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3165 .reset = mv88e6352_g1_reset,
7d381a02
SE		 3166};
3167
b3469dd8 3168static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3169 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3170 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3171 .phy_read = mv88e6165_phy_read,
3172 .phy_write = mv88e6165_phy_write,
08ef7f10 3173 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3174 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3175 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3176 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3177 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3178 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3179 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3180 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3181 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3182 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3183 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3184 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3185 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3186 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3187};
3188
3189static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3190 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3191 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3192 .phy_read = mv88e6xxx_phy_ppu_read,
3193 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3194 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3195 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3196 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3197 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3198 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a23b2961 3199 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
56995cbc 3200 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 3201 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
5f436666 3202 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3203 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3204 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3205 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3206 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3207 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3208 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3209 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3210 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3211 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3212 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3213 .ppu_enable = mv88e6185_g1_ppu_enable,
3214 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3215 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3216};
3217
3218static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3219 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3221 .phy_read = mv88e6165_phy_read,
3222 .phy_write = mv88e6165_phy_write,
08ef7f10 3223 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3224 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3225 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3226 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3227 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3228 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3229 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3230 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3231 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3232 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3234 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3235 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3236 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3237 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3238 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3239 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3240 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3241 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3242};
3243
3244static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3245 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3246 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3247 .phy_read = mv88e6165_phy_read,
3248 .phy_write = mv88e6165_phy_write,
08ef7f10 3249 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3250 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3251 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3252 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3253 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3254 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3255 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3256 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3257 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3258 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3259 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3260 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3261};
3262
3263static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3264 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3266 .phy_read = mv88e6xxx_g2_smi_phy_read,
3267 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3268 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3269 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3270 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3271 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3272 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3273 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3274 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3275 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3276 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3277 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3278 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3279 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3280 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3281 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3282 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3283 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3284 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3285 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3286 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3287 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3288};
3289
3290static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3291 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3292 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3293 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3295 .phy_read = mv88e6xxx_g2_smi_phy_read,
3296 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3297 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3298 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3299 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3300 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3301 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3302 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3303 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3304 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3305 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3306 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3307 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3308 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3309 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3310 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3311 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3312 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3313 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3314 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3315 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3316 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3317};
3318
3319static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3320 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3321 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3322 .phy_read = mv88e6xxx_g2_smi_phy_read,
3323 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3324 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3325 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3326 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3327 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3328 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3329 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3330 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3331 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3332 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3333 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3334 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3335 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3336 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3337 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3338 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3339 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3340 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3341 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3342 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3343 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3344};
3345
3346static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3347 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3348 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3349 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3350 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3351 .phy_read = mv88e6xxx_g2_smi_phy_read,
3352 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3353 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3354 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3355 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3356 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3357 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3358 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3359 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3360 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3361 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3362 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3363 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3364 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3365 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3366 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3367 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3368 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3369 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3370 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3371 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3372 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3373};
3374
3375static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3376 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3377 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3378 .phy_read = mv88e6xxx_phy_ppu_read,
3379 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3380 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3381 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3382 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3383 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a23b2961 3384 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
ef70b111 3385 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 3386 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3387 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3388 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3389 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3390 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3391 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3392 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3393 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3394 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3395 .ppu_enable = mv88e6185_g1_ppu_enable,
3396 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3397 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3398};
3399
1a3b39ec 3400static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3401 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3402 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3403 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3405 .phy_read = mv88e6xxx_g2_smi_phy_read,
3406 .phy_write = mv88e6xxx_g2_smi_phy_write,
3407 .port_set_link = mv88e6xxx_port_set_link,
3408 .port_set_duplex = mv88e6xxx_port_set_duplex,
3409 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3410 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3411 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3412 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3413 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3414 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3415 .port_pause_config = mv88e6390_port_pause_config,
79523473 3416 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3417 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3418 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3419 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3420 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3421 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3422 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3423 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3424 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3425 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3426};
3427
3428static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3429 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3430 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3431 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3432 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3433 .phy_read = mv88e6xxx_g2_smi_phy_read,
3434 .phy_write = mv88e6xxx_g2_smi_phy_write,
3435 .port_set_link = mv88e6xxx_port_set_link,
3436 .port_set_duplex = mv88e6xxx_port_set_duplex,
3437 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3438 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3439 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3440 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3441 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3442 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3443 .port_pause_config = mv88e6390_port_pause_config,
79523473 3444 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3445 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3446 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3447 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3448 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3449 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3450 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3451 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3452 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3453 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3454};
3455
3456static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3457 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3458 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3459 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3460 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3461 .phy_read = mv88e6xxx_g2_smi_phy_read,
3462 .phy_write = mv88e6xxx_g2_smi_phy_write,
3463 .port_set_link = mv88e6xxx_port_set_link,
3464 .port_set_duplex = mv88e6xxx_port_set_duplex,
3465 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3466 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3467 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3468 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3469 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3470 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3471 .port_pause_config = mv88e6390_port_pause_config,
79523473 3472 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3473 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3474 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3475 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3476 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3477 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3478 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3479 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3480 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3481 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3482};
3483
b3469dd8 3484static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3485 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3486 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3487 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3488 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3489 .phy_read = mv88e6xxx_g2_smi_phy_read,
3490 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3491 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3492 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3493 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3494 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3495 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3496 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3497 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3498 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3499 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3500 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3501 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3502 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3503 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3504 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3505 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3506 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3507 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3508 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3509 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3510 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3511};
3512
1a3b39ec 3513static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3514 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3515 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3516 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3517 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3518 .phy_read = mv88e6xxx_g2_smi_phy_read,
3519 .phy_write = mv88e6xxx_g2_smi_phy_write,
3520 .port_set_link = mv88e6xxx_port_set_link,
3521 .port_set_duplex = mv88e6xxx_port_set_duplex,
3522 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3523 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3524 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3525 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3526 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3527 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3528 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3529 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3530 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3531 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3532 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3533 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3534 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3535 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3536 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3537 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3538 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3539 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3540};
3541
b3469dd8 3542static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3543 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3544 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3545 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3546 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3547 .phy_read = mv88e6xxx_g2_smi_phy_read,
3548 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3549 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3550 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3551 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3552 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3553 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3554 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3555 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3556 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3557 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3558 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3559 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3560 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3561 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3562 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3563 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3564 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3565 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3566 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3567};
3568
3569static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3570 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3571 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3572 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3573 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3574 .phy_read = mv88e6xxx_g2_smi_phy_read,
3575 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3576 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3577 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3578 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3579 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3580 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3581 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3582 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3583 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3584 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3585 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3586 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3587 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3588 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3589 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3590 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3591 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3592 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3593};
3594
3595static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3596 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3597 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3598 .phy_read = mv88e6xxx_g2_smi_phy_read,
3599 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3600 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3601 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3602 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3603 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3604 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3605 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3606 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3607 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3608 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3609 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3610 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3611 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3612 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3613 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3614 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3615 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3616 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3617 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3618 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3619 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3620};
3621
3622static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3623 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3624 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3625 .phy_read = mv88e6xxx_g2_smi_phy_read,
3626 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3627 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3628 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3629 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3630 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3631 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3632 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3633 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3634 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3635 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3636 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3637 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3638 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3639 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3640 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3641 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3642 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3643 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3644 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3645 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3646 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3647};
3648
3649static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3650 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3651 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3652 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3653 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3654 .phy_read = mv88e6xxx_g2_smi_phy_read,
3655 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3656 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3657 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3658 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3659 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3660 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3661 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3662 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3663 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3664 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3665 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3666 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3667 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3668 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3669 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3670 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3671 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3672 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3673 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3674 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3675 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3676};
3677
1558727a
GC		 3678static const struct mv88e6xxx_ops mv88e6141_ops = {
3679 /* MV88E6XXX_FAMILY_6341 */
3680 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3681 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3682 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3683 .phy_read = mv88e6xxx_g2_smi_phy_read,
3684 .phy_write = mv88e6xxx_g2_smi_phy_write,
3685 .port_set_link = mv88e6xxx_port_set_link,
3686 .port_set_duplex = mv88e6xxx_port_set_duplex,
3687 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3688 .port_set_speed = mv88e6390_port_set_speed,
3689 .port_tag_remap = mv88e6095_port_tag_remap,
3690 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3691 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3692 .port_set_ether_type = mv88e6351_port_set_ether_type,
3693 .port_jumbo_config = mv88e6165_port_jumbo_config,
3694 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3695 .port_pause_config = mv88e6097_port_pause_config,
3696 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3697 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3698 .stats_get_strings = mv88e6320_stats_get_strings,
3699 .stats_get_stats = mv88e6390_stats_get_stats,
3700 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3701 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3702 .watchdog_ops = &mv88e6390_watchdog_ops,
1558727a
GC		 3703 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3704 .reset = mv88e6352_g1_reset,
3705};
3706
a75961d0
GC		 3707static const struct mv88e6xxx_ops mv88e6341_ops = {
3708 /* MV88E6XXX_FAMILY_6341 */
3709 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3710 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3712 .phy_read = mv88e6xxx_g2_smi_phy_read,
3713 .phy_write = mv88e6xxx_g2_smi_phy_write,
3714 .port_set_link = mv88e6xxx_port_set_link,
3715 .port_set_duplex = mv88e6xxx_port_set_duplex,
3716 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3717 .port_set_speed = mv88e6390_port_set_speed,
3718 .port_tag_remap = mv88e6095_port_tag_remap,
3719 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3720 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3721 .port_set_ether_type = mv88e6351_port_set_ether_type,
3722 .port_jumbo_config = mv88e6165_port_jumbo_config,
3723 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3724 .port_pause_config = mv88e6097_port_pause_config,
3725 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3726 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3727 .stats_get_strings = mv88e6320_stats_get_strings,
3728 .stats_get_stats = mv88e6390_stats_get_stats,
3729 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3730 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3731 .watchdog_ops = &mv88e6390_watchdog_ops,
a75961d0
GC		 3732 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3733 .reset = mv88e6352_g1_reset,
3734};
3735
1a3b39ec 3736static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3737 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3738 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3739 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3740 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3741 .phy_read = mv88e6xxx_g2_smi_phy_read,
3742 .phy_write = mv88e6xxx_g2_smi_phy_write,
3743 .port_set_link = mv88e6xxx_port_set_link,
3744 .port_set_duplex = mv88e6xxx_port_set_duplex,
3745 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3746 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3747 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3748 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3749 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3750 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3751 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3752 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3753 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3754 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3755 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3756 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3757 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3758 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3759 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3760 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3761 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3762 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3763 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3764 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3765};
3766
3767static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3768 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3769 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3770 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3771 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3772 .phy_read = mv88e6xxx_g2_smi_phy_read,
3773 .phy_write = mv88e6xxx_g2_smi_phy_write,
3774 .port_set_link = mv88e6xxx_port_set_link,
3775 .port_set_duplex = mv88e6xxx_port_set_duplex,
3776 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3777 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3778 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3779 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3780 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3781 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3782 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3783 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3784 .port_pause_config = mv88e6390_port_pause_config,
79523473 3785 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3786 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3787 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3788 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3789 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3790 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3791 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3792 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3793 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3794 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3795};
3796
3797static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3798 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3799 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3800 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3801 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3802 .phy_read = mv88e6xxx_g2_smi_phy_read,
3803 .phy_write = mv88e6xxx_g2_smi_phy_write,
3804 .port_set_link = mv88e6xxx_port_set_link,
3805 .port_set_duplex = mv88e6xxx_port_set_duplex,
3806 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3807 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3808 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3809 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3810 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3811 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3812 .port_pause_config = mv88e6390_port_pause_config,
79523473 3813 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3814 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3815 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3816 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3817 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3818 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3819 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3820 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3821 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3822 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3823};
3824
56995cbc
AL		 3825static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3826 const struct mv88e6xxx_ops *ops)
3827{
3828 if (!ops->port_set_frame_mode) {
3829 dev_err(chip->dev, "Missing port_set_frame_mode");
3830 return -EINVAL;
3831 }
3832
3833 if (!ops->port_set_egress_unknowns) {
3834 dev_err(chip->dev, "Missing port_set_egress_mode");
3835 return -EINVAL;
3836 }
3837
3838 return 0;
3839}
3840
f81ec90f
VD		 3841static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3842 [MV88E6085] = {
3843 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3844 .family = MV88E6XXX_FAMILY_6097,
3845 .name = "Marvell 88E6085",
3846 .num_databases = 4096,
3847 .num_ports = 10,
9dddd478 3848 .port_base_addr = 0x10,
a935c052 3849 .global1_addr = 0x1b,
acddbd21 3850 .age_time_coeff = 15000,
dc30c35b 3851 .g1_irqs = 8,
443d5a1b 3852 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3853 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3854 .ops = &mv88e6085_ops,
f81ec90f
VD		 3855 },
3856
3857 [MV88E6095] = {
3858 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3859 .family = MV88E6XXX_FAMILY_6095,
3860 .name = "Marvell 88E6095/88E6095F",
3861 .num_databases = 256,
3862 .num_ports = 11,
9dddd478 3863 .port_base_addr = 0x10,
a935c052 3864 .global1_addr = 0x1b,
acddbd21 3865 .age_time_coeff = 15000,
dc30c35b 3866 .g1_irqs = 8,
443d5a1b 3867 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3868 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3869 .ops = &mv88e6095_ops,
f81ec90f
VD		 3870 },
3871
7d381a02
SE		 3872 [MV88E6097] = {
3873 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3874 .family = MV88E6XXX_FAMILY_6097,
3875 .name = "Marvell 88E6097/88E6097F",
3876 .num_databases = 4096,
3877 .num_ports = 11,
3878 .port_base_addr = 0x10,
3879 .global1_addr = 0x1b,
3880 .age_time_coeff = 15000,
c534178b 3881 .g1_irqs = 8,
2bfcfcd3 3882 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3883 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3884 .ops = &mv88e6097_ops,
3885 },
3886
f81ec90f
VD		 3887 [MV88E6123] = {
3888 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3889 .family = MV88E6XXX_FAMILY_6165,
3890 .name = "Marvell 88E6123",
3891 .num_databases = 4096,
3892 .num_ports = 3,
9dddd478 3893 .port_base_addr = 0x10,
a935c052 3894 .global1_addr = 0x1b,
acddbd21 3895 .age_time_coeff = 15000,
dc30c35b 3896 .g1_irqs = 9,
443d5a1b 3897 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3898 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3899 .ops = &mv88e6123_ops,
f81ec90f
VD		 3900 },
3901
3902 [MV88E6131] = {
3903 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3904 .family = MV88E6XXX_FAMILY_6185,
3905 .name = "Marvell 88E6131",
3906 .num_databases = 256,
3907 .num_ports = 8,
9dddd478 3908 .port_base_addr = 0x10,
a935c052 3909 .global1_addr = 0x1b,
acddbd21 3910 .age_time_coeff = 15000,
dc30c35b 3911 .g1_irqs = 9,
443d5a1b 3912 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3913 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3914 .ops = &mv88e6131_ops,
f81ec90f
VD		 3915 },
3916
3917 [MV88E6161] = {
3918 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3919 .family = MV88E6XXX_FAMILY_6165,
3920 .name = "Marvell 88E6161",
3921 .num_databases = 4096,
3922 .num_ports = 6,
9dddd478 3923 .port_base_addr = 0x10,
a935c052 3924 .global1_addr = 0x1b,
acddbd21 3925 .age_time_coeff = 15000,
dc30c35b 3926 .g1_irqs = 9,
443d5a1b 3927 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3928 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3929 .ops = &mv88e6161_ops,
f81ec90f
VD		 3930 },
3931
3932 [MV88E6165] = {
3933 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3934 .family = MV88E6XXX_FAMILY_6165,
3935 .name = "Marvell 88E6165",
3936 .num_databases = 4096,
3937 .num_ports = 6,
9dddd478 3938 .port_base_addr = 0x10,
a935c052 3939 .global1_addr = 0x1b,
acddbd21 3940 .age_time_coeff = 15000,
dc30c35b 3941 .g1_irqs = 9,
443d5a1b 3942 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3943 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3944 .ops = &mv88e6165_ops,
f81ec90f
VD		 3945 },
3946
3947 [MV88E6171] = {
3948 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3949 .family = MV88E6XXX_FAMILY_6351,
3950 .name = "Marvell 88E6171",
3951 .num_databases = 4096,
3952 .num_ports = 7,
9dddd478 3953 .port_base_addr = 0x10,
a935c052 3954 .global1_addr = 0x1b,
acddbd21 3955 .age_time_coeff = 15000,
dc30c35b 3956 .g1_irqs = 9,
443d5a1b 3957 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3958 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3959 .ops = &mv88e6171_ops,
f81ec90f
VD		 3960 },
3961
3962 [MV88E6172] = {
3963 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3964 .family = MV88E6XXX_FAMILY_6352,
3965 .name = "Marvell 88E6172",
3966 .num_databases = 4096,
3967 .num_ports = 7,
9dddd478 3968 .port_base_addr = 0x10,
a935c052 3969 .global1_addr = 0x1b,
acddbd21 3970 .age_time_coeff = 15000,
dc30c35b 3971 .g1_irqs = 9,
443d5a1b 3972 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3973 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3974 .ops = &mv88e6172_ops,
f81ec90f
VD		 3975 },
3976
3977 [MV88E6175] = {
3978 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3979 .family = MV88E6XXX_FAMILY_6351,
3980 .name = "Marvell 88E6175",
3981 .num_databases = 4096,
3982 .num_ports = 7,
9dddd478 3983 .port_base_addr = 0x10,
a935c052 3984 .global1_addr = 0x1b,
acddbd21 3985 .age_time_coeff = 15000,
dc30c35b 3986 .g1_irqs = 9,
443d5a1b 3987 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3988 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3989 .ops = &mv88e6175_ops,
f81ec90f
VD		 3990 },
3991
3992 [MV88E6176] = {
3993 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3994 .family = MV88E6XXX_FAMILY_6352,
3995 .name = "Marvell 88E6176",
3996 .num_databases = 4096,
3997 .num_ports = 7,
9dddd478 3998 .port_base_addr = 0x10,
a935c052 3999 .global1_addr = 0x1b,
acddbd21 4000 .age_time_coeff = 15000,
dc30c35b 4001 .g1_irqs = 9,
443d5a1b 4002 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4003 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4004 .ops = &mv88e6176_ops,
f81ec90f
VD		 4005 },
4006
4007 [MV88E6185] = {
4008 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
4009 .family = MV88E6XXX_FAMILY_6185,
4010 .name = "Marvell 88E6185",
4011 .num_databases = 256,
4012 .num_ports = 10,
9dddd478 4013 .port_base_addr = 0x10,
a935c052 4014 .global1_addr = 0x1b,
acddbd21 4015 .age_time_coeff = 15000,
dc30c35b 4016 .g1_irqs = 8,
443d5a1b 4017 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4018 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 4019 .ops = &mv88e6185_ops,
f81ec90f
VD		 4020 },
4021
1a3b39ec
AL		 4022 [MV88E6190] = {
4023 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
4024 .family = MV88E6XXX_FAMILY_6390,
4025 .name = "Marvell 88E6190",
4026 .num_databases = 4096,
4027 .num_ports = 11, /* 10 + Z80 */
4028 .port_base_addr = 0x0,
4029 .global1_addr = 0x1b,
443d5a1b 4030 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 4031 .age_time_coeff = 3750,
1a3b39ec
AL		 4032 .g1_irqs = 9,
4033 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4034 .ops = &mv88e6190_ops,
4035 },
4036
4037 [MV88E6190X] = {
4038 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
4039 .family = MV88E6XXX_FAMILY_6390,
4040 .name = "Marvell 88E6190X",
4041 .num_databases = 4096,
4042 .num_ports = 11, /* 10 + Z80 */
4043 .port_base_addr = 0x0,
4044 .global1_addr = 0x1b,
b91e055c 4045 .age_time_coeff = 3750,
1a3b39ec 4046 .g1_irqs = 9,
443d5a1b 4047 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4048 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4049 .ops = &mv88e6190x_ops,
4050 },
4051
4052 [MV88E6191] = {
4053 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
4054 .family = MV88E6XXX_FAMILY_6390,
4055 .name = "Marvell 88E6191",
4056 .num_databases = 4096,
4057 .num_ports = 11, /* 10 + Z80 */
4058 .port_base_addr = 0x0,
4059 .global1_addr = 0x1b,
b91e055c 4060 .age_time_coeff = 3750,
443d5a1b
AL		 4061 .g1_irqs = 9,
4062 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4063 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4064 .ops = &mv88e6391_ops,
4065 },
4066
f81ec90f
VD		 4067 [MV88E6240] = {
4068 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
4069 .family = MV88E6XXX_FAMILY_6352,
4070 .name = "Marvell 88E6240",
4071 .num_databases = 4096,
4072 .num_ports = 7,
9dddd478 4073 .port_base_addr = 0x10,
a935c052 4074 .global1_addr = 0x1b,
acddbd21 4075 .age_time_coeff = 15000,
dc30c35b 4076 .g1_irqs = 9,
443d5a1b 4077 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4078 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4079 .ops = &mv88e6240_ops,
f81ec90f
VD		 4080 },
4081
1a3b39ec
AL		 4082 [MV88E6290] = {
4083 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4084 .family = MV88E6XXX_FAMILY_6390,
4085 .name = "Marvell 88E6290",
4086 .num_databases = 4096,
4087 .num_ports = 11, /* 10 + Z80 */
4088 .port_base_addr = 0x0,
4089 .global1_addr = 0x1b,
b91e055c 4090 .age_time_coeff = 3750,
1a3b39ec 4091 .g1_irqs = 9,
443d5a1b 4092 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4093 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4094 .ops = &mv88e6290_ops,
4095 },
4096
f81ec90f
VD		 4097 [MV88E6320] = {
4098 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4099 .family = MV88E6XXX_FAMILY_6320,
4100 .name = "Marvell 88E6320",
4101 .num_databases = 4096,
4102 .num_ports = 7,
9dddd478 4103 .port_base_addr = 0x10,
a935c052 4104 .global1_addr = 0x1b,
acddbd21 4105 .age_time_coeff = 15000,
dc30c35b 4106 .g1_irqs = 8,
443d5a1b 4107 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4108 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4109 .ops = &mv88e6320_ops,
f81ec90f
VD		 4110 },
4111
4112 [MV88E6321] = {
4113 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4114 .family = MV88E6XXX_FAMILY_6320,
4115 .name = "Marvell 88E6321",
4116 .num_databases = 4096,
4117 .num_ports = 7,
9dddd478 4118 .port_base_addr = 0x10,
a935c052 4119 .global1_addr = 0x1b,
acddbd21 4120 .age_time_coeff = 15000,
dc30c35b 4121 .g1_irqs = 8,
443d5a1b 4122 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4123 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4124 .ops = &mv88e6321_ops,
f81ec90f
VD		 4125 },
4126
1558727a
GC		 4127 [MV88E6141] = {
4128 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
4129 .family = MV88E6XXX_FAMILY_6341,
4130 .name = "Marvell 88E6341",
4131 .num_databases = 4096,
4132 .num_ports = 6,
4133 .port_base_addr = 0x10,
4134 .global1_addr = 0x1b,
4135 .age_time_coeff = 3750,
4136 .tag_protocol = DSA_TAG_PROTO_EDSA,
4137 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4138 .ops = &mv88e6141_ops,
4139 },
4140
a75961d0
GC		 4141 [MV88E6341] = {
4142 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
4143 .family = MV88E6XXX_FAMILY_6341,
4144 .name = "Marvell 88E6341",
4145 .num_databases = 4096,
4146 .num_ports = 6,
4147 .port_base_addr = 0x10,
4148 .global1_addr = 0x1b,
4149 .age_time_coeff = 3750,
4150 .tag_protocol = DSA_TAG_PROTO_EDSA,
4151 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4152 .ops = &mv88e6341_ops,
4153 },
4154
f81ec90f
VD		 4155 [MV88E6350] = {
4156 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4157 .family = MV88E6XXX_FAMILY_6351,
4158 .name = "Marvell 88E6350",
4159 .num_databases = 4096,
4160 .num_ports = 7,
9dddd478 4161 .port_base_addr = 0x10,
a935c052 4162 .global1_addr = 0x1b,
acddbd21 4163 .age_time_coeff = 15000,
dc30c35b 4164 .g1_irqs = 9,
443d5a1b 4165 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4166 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4167 .ops = &mv88e6350_ops,
f81ec90f
VD		 4168 },
4169
4170 [MV88E6351] = {
4171 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4172 .family = MV88E6XXX_FAMILY_6351,
4173 .name = "Marvell 88E6351",
4174 .num_databases = 4096,
4175 .num_ports = 7,
9dddd478 4176 .port_base_addr = 0x10,
a935c052 4177 .global1_addr = 0x1b,
acddbd21 4178 .age_time_coeff = 15000,
dc30c35b 4179 .g1_irqs = 9,
443d5a1b 4180 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4181 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4182 .ops = &mv88e6351_ops,
f81ec90f
VD		 4183 },
4184
4185 [MV88E6352] = {
4186 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4187 .family = MV88E6XXX_FAMILY_6352,
4188 .name = "Marvell 88E6352",
4189 .num_databases = 4096,
4190 .num_ports = 7,
9dddd478 4191 .port_base_addr = 0x10,
a935c052 4192 .global1_addr = 0x1b,
acddbd21 4193 .age_time_coeff = 15000,
dc30c35b 4194 .g1_irqs = 9,
443d5a1b 4195 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4196 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4197 .ops = &mv88e6352_ops,
f81ec90f 4198 },
1a3b39ec
AL		 4199 [MV88E6390] = {
4200 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4201 .family = MV88E6XXX_FAMILY_6390,
4202 .name = "Marvell 88E6390",
4203 .num_databases = 4096,
4204 .num_ports = 11, /* 10 + Z80 */
4205 .port_base_addr = 0x0,
4206 .global1_addr = 0x1b,
b91e055c 4207 .age_time_coeff = 3750,
1a3b39ec 4208 .g1_irqs = 9,
443d5a1b 4209 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4210 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4211 .ops = &mv88e6390_ops,
4212 },
4213 [MV88E6390X] = {
4214 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4215 .family = MV88E6XXX_FAMILY_6390,
4216 .name = "Marvell 88E6390X",
4217 .num_databases = 4096,
4218 .num_ports = 11, /* 10 + Z80 */
4219 .port_base_addr = 0x0,
4220 .global1_addr = 0x1b,
b91e055c 4221 .age_time_coeff = 3750,
1a3b39ec 4222 .g1_irqs = 9,
443d5a1b 4223 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4224 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4225 .ops = &mv88e6390x_ops,
4226 },
f81ec90f
VD		 4227};
4228
5f7c0367 4229static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4230{
a439c061 4231 int i;
b9b37713 4232
5f7c0367
VD		 4233 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4234 if (mv88e6xxx_table[i].prod_num == prod_num)
4235 return &mv88e6xxx_table[i];
b9b37713 4236
b9b37713
VD		 4237 return NULL;
4238}
4239
fad09c73 4240static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4241{
4242 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4243 unsigned int prod_num, rev;
4244 u16 id;
4245 int err;
bc46a3d5 4246
8f6345b2
VD		 4247 mutex_lock(&chip->reg_lock);
4248 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4249 mutex_unlock(&chip->reg_lock);
4250 if (err)
4251 return err;
bc46a3d5
VD		 4252
4253 prod_num = (id & 0xfff0) >> 4;
4254 rev = id & 0x000f;
4255
4256 info = mv88e6xxx_lookup_info(prod_num);
4257 if (!info)
4258 return -ENODEV;
4259
caac8545 4260 /* Update the compatible info with the probed one */
fad09c73 4261 chip->info = info;
bc46a3d5 4262
ca070c10
VD		 4263 err = mv88e6xxx_g2_require(chip);
4264 if (err)
4265 return err;
4266
fad09c73
VD		 4267 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4268 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4269
4270 return 0;
4271}
4272
fad09c73 4273static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4274{
fad09c73 4275 struct mv88e6xxx_chip *chip;
469d729f 4276
fad09c73
VD		 4277 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4278 if (!chip)
469d729f
VD		 4279 return NULL;
4280
fad09c73 4281 chip->dev = dev;
469d729f 4282
fad09c73 4283 mutex_init(&chip->reg_lock);
a3c53be5 4284 INIT_LIST_HEAD(&chip->mdios);
469d729f 4285
fad09c73 4286 return chip;
469d729f
VD		 4287}
4288
e57e5e77
VD		 4289static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4290{
a199d8b6 4291 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4292 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4293}
4294
930188ce
AL		 4295static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4296{
a199d8b6 4297 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4298 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4299}
4300
fad09c73 4301static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4302 struct mii_bus *bus, int sw_addr)
4303{
914b32f6 4304 if (sw_addr == 0)
fad09c73 4305 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4306 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4307 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4308 else
4309 return -EINVAL;
4310
fad09c73
VD		 4311 chip->bus = bus;
4312 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4313
4314 return 0;
4315}
4316
7b314362
AL		 4317static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4318{
04bed143 4319 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4320
443d5a1b 4321 return chip->info->tag_protocol;
7b314362
AL		 4322}
4323
fcdce7d0
AL		 4324static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4325 struct device *host_dev, int sw_addr,
4326 void **priv)
a77d43f1 4327{
fad09c73 4328 struct mv88e6xxx_chip *chip;
a439c061 4329 struct mii_bus *bus;
b516d453 4330 int err;
a77d43f1 4331
a439c061 4332 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4333 if (!bus)
4334 return NULL;
4335
fad09c73
VD		 4336 chip = mv88e6xxx_alloc_chip(dsa_dev);
4337 if (!chip)
469d729f
VD		 4338 return NULL;
4339
caac8545 4340 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4341 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4342
fad09c73 4343 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4344 if (err)
4345 goto free;
4346
fad09c73 4347 err = mv88e6xxx_detect(chip);
bc46a3d5 4348 if (err)
469d729f 4349 goto free;
a439c061 4350
dc30c35b
AL		 4351 mutex_lock(&chip->reg_lock);
4352 err = mv88e6xxx_switch_reset(chip);
4353 mutex_unlock(&chip->reg_lock);
4354 if (err)
4355 goto free;
4356
e57e5e77
VD		 4357 mv88e6xxx_phy_init(chip);
4358
a3c53be5 4359 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4360 if (err)
469d729f 4361 goto free;
b516d453 4362
fad09c73 4363 *priv = chip;
a439c061 4364
fad09c73 4365 return chip->info->name;
469d729f 4366free:
fad09c73 4367 devm_kfree(dsa_dev, chip);
469d729f
VD		 4368
4369 return NULL;
a77d43f1
AL		 4370}
4371
7df8fbdd
VD		 4372static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4373 const struct switchdev_obj_port_mdb *mdb,
4374 struct switchdev_trans *trans)
4375{
4376 /* We don't need any dynamic resource from the kernel (yet),
4377 * so skip the prepare phase.
4378 */
4379
4380 return 0;
4381}
4382
4383static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4384 const struct switchdev_obj_port_mdb *mdb,
4385 struct switchdev_trans *trans)
4386{
04bed143 4387 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4388
4389 mutex_lock(&chip->reg_lock);
4390 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4391 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4392 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4393 mutex_unlock(&chip->reg_lock);
4394}
4395
4396static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4397 const struct switchdev_obj_port_mdb *mdb)
4398{
04bed143 4399 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4400 int err;
4401
4402 mutex_lock(&chip->reg_lock);
4403 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4404 GLOBAL_ATU_DATA_STATE_UNUSED);
4405 mutex_unlock(&chip->reg_lock);
4406
4407 return err;
4408}
4409
4410static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4411 struct switchdev_obj_port_mdb *mdb,
4412 int (*cb)(struct switchdev_obj *obj))
4413{
04bed143 4414 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4415 int err;
4416
4417 mutex_lock(&chip->reg_lock);
4418 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4419 mutex_unlock(&chip->reg_lock);
4420
4421 return err;
4422}
4423
a82f67af 4424static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4425 .probe = mv88e6xxx_drv_probe,
7b314362 4426 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4427 .setup = mv88e6xxx_setup,
4428 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4429 .adjust_link = mv88e6xxx_adjust_link,
4430 .get_strings = mv88e6xxx_get_strings,
4431 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4432 .get_sset_count = mv88e6xxx_get_sset_count,
4433 .set_eee = mv88e6xxx_set_eee,
4434 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4435 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4436 .get_eeprom = mv88e6xxx_get_eeprom,
4437 .set_eeprom = mv88e6xxx_set_eeprom,
4438 .get_regs_len = mv88e6xxx_get_regs_len,
4439 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4440 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4441 .port_bridge_join = mv88e6xxx_port_bridge_join,
4442 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4443 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4444 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4445 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4446 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4447 .port_vlan_add = mv88e6xxx_port_vlan_add,
4448 .port_vlan_del = mv88e6xxx_port_vlan_del,
4449 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4450 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4451 .port_fdb_add = mv88e6xxx_port_fdb_add,
4452 .port_fdb_del = mv88e6xxx_port_fdb_del,
4453 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4454 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4455 .port_mdb_add = mv88e6xxx_port_mdb_add,
4456 .port_mdb_del = mv88e6xxx_port_mdb_del,
4457 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4458};
4459
ab3d408d
FF		 4460static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4461 .ops = &mv88e6xxx_switch_ops,
4462};
4463
55ed0ce0 4464static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4465{
fad09c73 4466 struct device *dev = chip->dev;
b7e66a5f
VD		 4467 struct dsa_switch *ds;
4468
a0c02161 4469 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
b7e66a5f
VD		 4470 if (!ds)
4471 return -ENOMEM;
4472
fad09c73 4473 ds->priv = chip;
9d490b4e 4474 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4475
4476 dev_set_drvdata(dev, ds);
4477
55ed0ce0 4478 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4479}
4480
fad09c73 4481static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4482{
fad09c73 4483 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4484}
4485
57d32310 4486static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4487{
14c7b3c3 4488 struct device *dev = &mdiodev->dev;
f8cd8753 4489 struct device_node *np = dev->of_node;
caac8545 4490 const struct mv88e6xxx_info *compat_info;
fad09c73 4491 struct mv88e6xxx_chip *chip;
f8cd8753 4492 u32 eeprom_len;
52638f71 4493 int err;
14c7b3c3 4494
caac8545
VD		 4495 compat_info = of_device_get_match_data(dev);
4496 if (!compat_info)
4497 return -EINVAL;
4498
fad09c73
VD		 4499 chip = mv88e6xxx_alloc_chip(dev);
4500 if (!chip)
14c7b3c3
AL		 4501 return -ENOMEM;
4502
fad09c73 4503 chip->info = compat_info;
caac8545 4504
56995cbc
AL		 4505 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4506 if (err)
4507 return err;
4508
fad09c73 4509 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4510 if (err)
4511 return err;
14c7b3c3 4512
b4308f04
AL		 4513 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4514 if (IS_ERR(chip->reset))
4515 return PTR_ERR(chip->reset);
4516
fad09c73 4517 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4518 if (err)
4519 return err;
14c7b3c3 4520
e57e5e77
VD		 4521 mv88e6xxx_phy_init(chip);
4522
ee4dc2e7 4523 if (chip->info->ops->get_eeprom &&
f8cd8753 4524 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4525 chip->eeprom_len = eeprom_len;
f8cd8753 4526
dc30c35b
AL		 4527 mutex_lock(&chip->reg_lock);
4528 err = mv88e6xxx_switch_reset(chip);
4529 mutex_unlock(&chip->reg_lock);
4530 if (err)
4531 goto out;
4532
4533 chip->irq = of_irq_get(np, 0);
4534 if (chip->irq == -EPROBE_DEFER) {
4535 err = chip->irq;
4536 goto out;
4537 }
4538
4539 if (chip->irq > 0) {
4540 /* Has to be performed before the MDIO bus is created,
4541 * because the PHYs will link there interrupts to these
4542 * interrupt controllers
4543 */
4544 mutex_lock(&chip->reg_lock);
4545 err = mv88e6xxx_g1_irq_setup(chip);
4546 mutex_unlock(&chip->reg_lock);
4547
4548 if (err)
4549 goto out;
4550
4551 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4552 err = mv88e6xxx_g2_irq_setup(chip);
4553 if (err)
4554 goto out_g1_irq;
4555 }
4556 }
4557
a3c53be5 4558 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4559 if (err)
dc30c35b 4560 goto out_g2_irq;
b516d453 4561
55ed0ce0 4562 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4563 if (err)
4564 goto out_mdio;
83c0afae 4565
98e67308 4566 return 0;
dc30c35b
AL		 4567
4568out_mdio:
a3c53be5 4569 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4570out_g2_irq:
46712644 4571 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4572 mv88e6xxx_g2_irq_free(chip);
4573out_g1_irq:
61f7c3f8
AL		 4574 if (chip->irq > 0) {
4575 mutex_lock(&chip->reg_lock);
46712644 4576 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4577 mutex_unlock(&chip->reg_lock);
4578 }
dc30c35b
AL		 4579out:
4580 return err;
98e67308 4581}
14c7b3c3
AL		 4582
4583static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4584{
4585 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4586 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4587
930188ce 4588 mv88e6xxx_phy_destroy(chip);
fad09c73 4589 mv88e6xxx_unregister_switch(chip);
a3c53be5 4590 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4591
46712644
AL		 4592 if (chip->irq > 0) {
4593 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4594 mv88e6xxx_g2_irq_free(chip);
4595 mv88e6xxx_g1_irq_free(chip);
4596 }
14c7b3c3
AL		 4597}
4598
4599static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4600 {
4601 .compatible = "marvell,mv88e6085",
4602 .data = &mv88e6xxx_table[MV88E6085],
4603 },
1a3b39ec
AL		 4604 {
4605 .compatible = "marvell,mv88e6190",
4606 .data = &mv88e6xxx_table[MV88E6190],
4607 },
14c7b3c3
AL		 4608 { /* sentinel */ },
4609};
4610
4611MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4612
4613static struct mdio_driver mv88e6xxx_driver = {
4614 .probe = mv88e6xxx_probe,
4615 .remove = mv88e6xxx_remove,
4616 .mdiodrv.driver = {
4617 .name = "mv88e6085",
4618 .of_match_table = mv88e6xxx_of_match,
4619 },
4620};
4621
4622static int __init mv88e6xxx_init(void)
4623{
ab3d408d 4624 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4625 return mdio_driver_register(&mv88e6xxx_driver);
4626}
98e67308
BH		 4627module_init(mv88e6xxx_init);
4628
4629static void __exit mv88e6xxx_cleanup(void)
4630{
14c7b3c3 4631 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4632 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4633}
4634module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4635
4636MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4637MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4638MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror