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net: dsa: mv88e6xxx: Move mv88e6xxx_port_db_load_purge()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
ec561276 35
4d5f2ba7 36#include "chip.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
6d91782f 41#include "serdes.h"
91da11f8 42
fad09c73 43static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 44{
fad09c73
VD		 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 47 dump_stack();
48 }
49}
50
914b32f6
VD		 51/* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 *
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 *
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 61 */
914b32f6 62
fad09c73 63static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 *val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 val)
74{
fad09c73 75 if (!chip->smi_ops)
914b32f6
VD		 76 return -EOPNOTSUPP;
77
fad09c73 78 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 79}
80
fad09c73 81static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 82 int addr, int reg, u16 *val)
83{
84 int ret;
85
fad09c73 86 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 87 if (ret < 0)
88 return ret;
89
90 *val = ret & 0xffff;
91
92 return 0;
93}
94
fad09c73 95static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 96 int addr, int reg, u16 val)
97{
98 int ret;
99
fad09c73 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 101 if (ret < 0)
102 return ret;
103
104 return 0;
105}
106
c08026ab 107static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
110};
111
fad09c73 112static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 113{
114 int ret;
115 int i;
116
117 for (i = 0; i < 16; i++) {
fad09c73 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 119 if (ret < 0)
120 return ret;
121
cca8b133 122 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 123 return 0;
124 }
125
126 return -ETIMEDOUT;
127}
128
fad09c73 129static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 130 int addr, int reg, u16 *val)
91da11f8
LB		 131{
132 int ret;
133
3675c8d7 134 /* Wait for the bus to become free. */
fad09c73 135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the read command. */
fad09c73 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the read command to complete. */
fad09c73 146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 147 if (ret < 0)
148 return ret;
149
3675c8d7 150 /* Read the data. */
fad09c73 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 152 if (ret < 0)
153 return ret;
154
914b32f6 155 *val = ret & 0xffff;
91da11f8 156
914b32f6 157 return 0;
8d6d09e7
GR		 158}
159
fad09c73 160static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 161 int addr, int reg, u16 val)
91da11f8
LB		 162{
163 int ret;
164
3675c8d7 165 /* Wait for the bus to become free. */
fad09c73 166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 167 if (ret < 0)
168 return ret;
169
3675c8d7 170 /* Transmit the data to write. */
fad09c73 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Transmit the write command. */
fad09c73 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 178 if (ret < 0)
179 return ret;
180
3675c8d7 181 /* Wait for the write command to complete. */
fad09c73 182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 183 if (ret < 0)
184 return ret;
185
186 return 0;
187}
188
c08026ab 189static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
192};
193
ec561276 194int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 195{
196 int err;
197
fad09c73 198 assert_reg_lock(chip);
914b32f6 199
fad09c73 200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 201 if (err)
202 return err;
203
fad09c73 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 205 addr, reg, *val);
206
207 return 0;
208}
209
ec561276 210int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 211{
914b32f6
VD		 212 int err;
213
fad09c73 214 assert_reg_lock(chip);
91da11f8 215
fad09c73 216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 217 if (err)
218 return err;
219
fad09c73 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 221 addr, reg, val);
222
914b32f6
VD		 223 return 0;
224}
225
10fa5bfc 226struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 227{
228 struct mv88e6xxx_mdio_bus *mdio_bus;
229
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
231 list);
232 if (!mdio_bus)
233 return NULL;
234
235 return mdio_bus->bus;
236}
237
dc30c35b
AL		 238static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
239{
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
242
243 chip->g1_irq.masked |= (1 << n);
244}
245
246static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
247{
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
250
251 chip->g1_irq.masked &= ~(1 << n);
252}
253
254static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
255{
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
259 unsigned int n;
260 u16 reg;
261 int err;
262
263 mutex_lock(&chip->reg_lock);
82466921 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b
AL		 265 mutex_unlock(&chip->reg_lock);
266
267 if (err)
268 goto out;
269
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
274 ++nhandled;
275 }
276 }
277out:
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
279}
280
281static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
282{
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
284
285 mutex_lock(&chip->reg_lock);
286}
287
288static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
289{
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
292 u16 reg;
293 int err;
294
d77f4321 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 296 if (err)
297 goto out;
298
299 reg &= ~mask;
300 reg |= (~chip->g1_irq.masked & mask);
301
d77f4321 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 303 if (err)
304 goto out;
305
306out:
307 mutex_unlock(&chip->reg_lock);
308}
309
6eb15e21 310static const struct irq_chip mv88e6xxx_g1_irq_chip = {
dc30c35b
AL		 311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
316};
317
318static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
319 unsigned int irq,
320 irq_hw_number_t hwirq)
321{
322 struct mv88e6xxx_chip *chip = d->host_data;
323
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
327
328 return 0;
329}
330
331static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
334};
335
336static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
337{
338 int irq, virq;
3460a577
AL		 339 u16 mask;
340
d77f4321 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3460a577 342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577
AL		 344
345 free_irq(chip->irq, chip);
dc30c35b 346
5edef2f2 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 349 irq_dispose_mapping(virq);
350 }
351
a3db3d3a 352 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 353}
354
355static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
356{
3dd0ef05
AL		 357 int err, irq, virq;
358 u16 reg, mask;
dc30c35b
AL		 359
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
365 return -ENOMEM;
366
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
369
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
372
d77f4321 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 374 if (err)
3dd0ef05 375 goto out_mapping;
dc30c35b 376
3dd0ef05 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 378
d77f4321 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 380 if (err)
3dd0ef05 381 goto out_disable;
dc30c35b
AL		 382
383 /* Reading the interrupt status clears (most of) them */
82466921 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 385 if (err)
3dd0ef05 386 goto out_disable;
dc30c35b
AL		 387
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
392 if (err)
3dd0ef05 393 goto out_disable;
dc30c35b
AL		 394
395 return 0;
396
3dd0ef05
AL		 397out_disable:
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 400
401out_mapping:
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
405 }
406
407 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 408
409 return err;
410}
411
ec561276 412int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 413{
6441e669 414 int i;
2d79af6e 415
6441e669 416 for (i = 0; i < 16; i++) {
2d79af6e
VD		 417 u16 val;
418 int err;
419
420 err = mv88e6xxx_read(chip, addr, reg, &val);
421 if (err)
422 return err;
423
424 if (!(val & mask))
425 return 0;
426
427 usleep_range(1000, 2000);
428 }
429
30853553 430 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 431 return -ETIMEDOUT;
432}
433
f22ab641 434/* Indirect write to single pointer-data register with an Update bit */
ec561276 435int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 436{
437 u16 val;
0f02b4f7 438 int err;
f22ab641
VD		 439
440 /* Wait until the previous operation is completed */
0f02b4f7
AL		 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
442 if (err)
443 return err;
f22ab641
VD		 444
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
447
448 return mv88e6xxx_write(chip, addr, reg, val);
449}
450
d78343d2
VD		 451static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
454{
455 int err;
456
457 if (!chip->info->ops->port_set_link)
458 return 0;
459
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
462 if (err)
463 return err;
464
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
468 goto restore_link;
469 }
470
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
474 goto restore_link;
475 }
476
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
480 goto restore_link;
481 }
482
f39908d3
AL		 483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
486 goto restore_link;
487 }
488
d78343d2
VD		 489 err = 0;
490restore_link:
491 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 493
494 return err;
495}
496
dea87024
AL		 497/* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
500 */
f81ec90f
VD		 501static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
dea87024 503{
04bed143 504 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 505 int err;
dea87024
AL		 506
507 if (!phy_is_pseudo_fixed_link(phydev))
508 return;
509
fad09c73 510 mutex_lock(&chip->reg_lock);
d78343d2
VD		 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
fad09c73 513 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 514
515 if (err && err != -EOPNOTSUPP)
774439e5 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
dea87024
AL		 517}
518
a605a0fe 519static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 520{
a605a0fe
AL		 521 if (!chip->info->ops->stats_snapshot)
522 return -EOPNOTSUPP;
91da11f8 523
a605a0fe 524 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 525}
526
e413e7e1 527static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 587};
588
fad09c73 589static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 590 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 591 int port, u16 bank1_select,
592 u16 histogram)
80c4627b 593{
80c4627b
AL		 594 u32 low;
595 u32 high = 0;
dfafe449 596 u16 reg = 0;
0e7b9925 597 int err;
80c4627b
AL		 598 u64 value;
599
f5e2ed02 600 switch (s->type) {
dfafe449 601 case STATS_TYPE_PORT:
0e7b9925
AL		 602 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
603 if (err)
80c4627b
AL		 604 return UINT64_MAX;
605
0e7b9925 606 low = reg;
80c4627b 607 if (s->sizeof_stat == 4) {
0e7b9925
AL		 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
609 if (err)
80c4627b 610 return UINT64_MAX;
0e7b9925 611 high = reg;
80c4627b 612 }
f5e2ed02 613 break;
dfafe449 614 case STATS_TYPE_BANK1:
e0d8b615 615 reg = bank1_select;
dfafe449
AL		 616 /* fall through */
617 case STATS_TYPE_BANK0:
e0d8b615 618 reg |= s->reg | histogram;
7f9ef3af 619 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 620 if (s->sizeof_stat == 8)
7f9ef3af 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 622 break;
623 default:
624 return UINT64_MAX;
80c4627b
AL		 625 }
626 value = (((u64)high) << 16) | low;
627 return value;
628}
629
dfafe449
AL		 630static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
91da11f8 632{
f5e2ed02
AL		 633 struct mv88e6xxx_hw_stat *stat;
634 int i, j;
91da11f8 635
f5e2ed02
AL		 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
dfafe449 638 if (stat->type & types) {
f5e2ed02
AL		 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
640 ETH_GSTRING_LEN);
641 j++;
642 }
91da11f8 643 }
e413e7e1
AL		 644}
645
dfafe449
AL		 646static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
647 uint8_t *data)
648{
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
651}
652
653static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
654 uint8_t *data)
655{
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
658}
659
660static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
661 uint8_t *data)
e413e7e1 662{
04bed143 663 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 664
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
667}
668
669static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
670 int types)
671{
f5e2ed02
AL		 672 struct mv88e6xxx_hw_stat *stat;
673 int i, j;
674
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
dfafe449 677 if (stat->type & types)
f5e2ed02
AL		 678 j++;
679 }
680 return j;
e413e7e1
AL		 681}
682
dfafe449
AL		 683static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
684{
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
686 STATS_TYPE_PORT);
687}
688
689static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
690{
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
692 STATS_TYPE_BANK1);
693}
694
695static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
696{
697 struct mv88e6xxx_chip *chip = ds->priv;
698
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
701
702 return 0;
703}
704
052f947f 705static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
052f947f
AL		 708{
709 struct mv88e6xxx_hw_stat *stat;
710 int i, j;
711
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
e0d8b615
AL		 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
716 bank1_select,
717 histogram);
052f947f
AL		 718 j++;
719 }
720 }
721}
722
723static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
724 uint64_t *data)
725{
726 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 729}
730
731static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
732 uint64_t *data)
733{
734 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 738}
739
740static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
741 uint64_t *data)
742{
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
746 0);
052f947f
AL		 747}
748
749static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
750 uint64_t *data)
751{
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
754}
755
f81ec90f
VD		 756static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
757 uint64_t *data)
e413e7e1 758{
04bed143 759 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 760 int ret;
f5e2ed02 761
fad09c73 762 mutex_lock(&chip->reg_lock);
f5e2ed02 763
a605a0fe 764 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 765 if (ret < 0) {
fad09c73 766 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 767 return;
768 }
052f947f
AL		 769
770 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 771
fad09c73 772 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 773}
774
de227387
AL		 775static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
776{
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
779
780 return 0;
781}
782
f81ec90f 783static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 784{
785 return 32 * sizeof(u16);
786}
787
f81ec90f
VD		 788static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
a1ab91f3 790{
04bed143 791 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 792 int err;
793 u16 reg;
a1ab91f3
GR		 794 u16 *p = _p;
795 int i;
796
797 regs->version = 0;
798
799 memset(p, 0xff, 32 * sizeof(u16));
800
fad09c73 801 mutex_lock(&chip->reg_lock);
23062513 802
a1ab91f3 803 for (i = 0; i < 32; i++) {
a1ab91f3 804
0e7b9925
AL		 805 err = mv88e6xxx_port_read(chip, port, i, &reg);
806 if (!err)
807 p[i] = reg;
a1ab91f3 808 }
23062513 809
fad09c73 810 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 811}
812
08f50061
VD		 813static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
814 struct ethtool_eee *e)
68b8f60c 815{
5480db69
VD		 816 /* Nothing to do on the port's MAC */
817 return 0;
11b3b45d
GR		 818}
819
08f50061
VD		 820static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
821 struct ethtool_eee *e)
11b3b45d 822{
5480db69
VD		 823 /* Nothing to do on the port's MAC */
824 return 0;
11b3b45d
GR		 825}
826
e5887a2a 827static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 828{
e5887a2a
VD		 829 struct dsa_switch *ds = NULL;
830 struct net_device *br;
831 u16 pvlan;
b7666efe
VD		 832 int i;
833
e5887a2a
VD		 834 if (dev < DSA_MAX_SWITCHES)
835 ds = chip->ds->dst->ds[dev];
836
837 /* Prevent frames from unknown switch or port */
838 if (!ds || port >= ds->num_ports)
839 return 0;
840
841 /* Frames from DSA links and CPU ports can egress any local port */
842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
843 return mv88e6xxx_port_mask(chip);
844
845 br = ds->ports[port].bridge_dev;
846 pvlan = 0;
847
848 /* Frames from user ports can egress any local DSA links and CPU ports,
849 * as well as any local member of their bridge group.
850 */
851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
852 if (dsa_is_cpu_port(chip->ds, i) ||
853 dsa_is_dsa_port(chip->ds, i) ||
c8652c83 854 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
e5887a2a
VD		 855 pvlan |= BIT(i);
856
857 return pvlan;
858}
859
240ea3ef 860static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 861{
862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 863
864 /* prevent frames from going back out of the port they came in on */
865 output_ports &= ~BIT(port);
facd95b2 866
5a7921f4 867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 868}
869
f81ec90f
VD		 870static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
871 u8 state)
facd95b2 872{
04bed143 873 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 874 int err;
facd95b2 875
fad09c73 876 mutex_lock(&chip->reg_lock);
f894c29c 877 err = mv88e6xxx_port_set_state(chip, port, state);
fad09c73 878 mutex_unlock(&chip->reg_lock);
553eb544
VD		 879
880 if (err)
774439e5 881 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 882}
883
9e907d73
VD		 884static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
885{
886 if (chip->info->ops->pot_clear)
887 return chip->info->ops->pot_clear(chip);
888
889 return 0;
890}
891
51c901a7
VD		 892static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
893{
894 if (chip->info->ops->mgmt_rsvd2cpu)
895 return chip->info->ops->mgmt_rsvd2cpu(chip);
896
897 return 0;
898}
899
a2ac29d2
VD		 900static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
901{
c3a7d4ad
VD		 902 int err;
903
daefc943
VD		 904 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
905 if (err)
906 return err;
907
c3a7d4ad
VD		 908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
909 if (err)
910 return err;
911
a2ac29d2
VD		 912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
913}
914
cd8da8bb
VD		 915static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
916{
917 int port;
918 int err;
919
920 if (!chip->info->ops->irl_init_all)
921 return 0;
922
923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
924 /* Disable ingress rate limiting by resetting all per port
925 * ingress rate limit resources to their initial state.
926 */
927 err = chip->info->ops->irl_init_all(chip, port);
928 if (err)
929 return err;
930 }
931
932 return 0;
933}
934
04a69a17
VD		 935static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
936{
937 if (chip->info->ops->set_switch_mac) {
938 u8 addr[ETH_ALEN];
939
940 eth_random_addr(addr);
941
942 return chip->info->ops->set_switch_mac(chip, addr);
943 }
944
945 return 0;
946}
947
17a1594e
VD		 948static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
949{
950 u16 pvlan = 0;
951
952 if (!mv88e6xxx_has_pvt(chip))
953 return -EOPNOTSUPP;
954
955 /* Skip the local source device, which uses in-chip port VLAN */
956 if (dev != chip->ds->index)
aec5ac88 957 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 958
959 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
960}
961
81228996
VD		 962static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
963{
17a1594e
VD		 964 int dev, port;
965 int err;
966
81228996
VD		 967 if (!mv88e6xxx_has_pvt(chip))
968 return 0;
969
970 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
971 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
972 */
17a1594e
VD		 973 err = mv88e6xxx_g2_misc_4_bit_port(chip);
974 if (err)
975 return err;
976
977 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
978 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
979 err = mv88e6xxx_pvt_map(chip, dev, port);
980 if (err)
981 return err;
982 }
983 }
984
985 return 0;
81228996
VD		 986}
987
749efcb8
VD		 988static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
989{
990 struct mv88e6xxx_chip *chip = ds->priv;
991 int err;
992
993 mutex_lock(&chip->reg_lock);
e606ca36 994 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 995 mutex_unlock(&chip->reg_lock);
996
997 if (err)
774439e5 998 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 999}
1000
b486d7c9
VD		 1001static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1002{
1003 if (!chip->info->max_vid)
1004 return 0;
1005
1006 return mv88e6xxx_g1_vtu_flush(chip);
1007}
1008
f1394b78
VD		 1009static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1010 struct mv88e6xxx_vtu_entry *entry)
1011{
1012 if (!chip->info->ops->vtu_getnext)
1013 return -EOPNOTSUPP;
1014
1015 return chip->info->ops->vtu_getnext(chip, entry);
1016}
1017
0ad5daf6
VD		 1018static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1019 struct mv88e6xxx_vtu_entry *entry)
1020{
1021 if (!chip->info->ops->vtu_loadpurge)
1022 return -EOPNOTSUPP;
1023
1024 return chip->info->ops->vtu_loadpurge(chip, entry);
1025}
1026
d7f435f9 1027static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1028{
1029 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
3afb4bde
VD		 1030 struct mv88e6xxx_vtu_entry vlan = {
1031 .vid = chip->info->max_vid,
1032 };
2db9ce1f 1033 int i, err;
3285f9e8
VD		 1034
1035 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1036
2db9ce1f 1037 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1038 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1039 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1040 if (err)
1041 return err;
1042
1043 set_bit(*fid, fid_bitmap);
1044 }
1045
3285f9e8 1046 /* Set every FID bit used by the VLAN entries */
3285f9e8 1047 do {
f1394b78 1048 err = mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1049 if (err)
1050 return err;
1051
1052 if (!vlan.valid)
1053 break;
1054
1055 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1056 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1057
1058 /* The reset value 0x000 is used to indicate that multiple address
1059 * databases are not needed. Return the next positive available.
1060 */
1061 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1062 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1063 return -ENOSPC;
1064
1065 /* Clear the database */
daefc943 1066 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1067}
1068
567aa59a
VD		 1069static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1070 struct mv88e6xxx_vtu_entry *entry, bool new)
2fb5ef09
VD		 1071{
1072 int err;
1073
1074 if (!vid)
1075 return -EINVAL;
1076
3afb4bde
VD		 1077 entry->vid = vid - 1;
1078 entry->valid = false;
2fb5ef09 1079
f1394b78 1080 err = mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1081 if (err)
1082 return err;
1083
567aa59a
VD		 1084 if (entry->vid == vid && entry->valid)
1085 return 0;
2fb5ef09 1086
567aa59a
VD		 1087 if (new) {
1088 int i;
1089
1090 /* Initialize a fresh VLAN entry */
1091 memset(entry, 0, sizeof(*entry));
1092 entry->valid = true;
1093 entry->vid = vid;
1094
553a768d 1095 /* Exclude all ports */
567aa59a 1096 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
553a768d 1097 entry->member[i] =
7ec60d6e 1098 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
567aa59a
VD		 1099
1100 return mv88e6xxx_atu_new(chip, &entry->fid);
2fb5ef09
VD		 1101 }
1102
567aa59a
VD		 1103 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1104 return -EOPNOTSUPP;
2fb5ef09
VD		 1105}
1106
da9c359e
VD		 1107static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1108 u16 vid_begin, u16 vid_end)
1109{
04bed143 1110 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1111 struct mv88e6xxx_vtu_entry vlan = {
1112 .vid = vid_begin - 1,
1113 };
da9c359e
VD		 1114 int i, err;
1115
db06ae41
AL		 1116 /* DSA and CPU ports have to be members of multiple vlans */
1117 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1118 return 0;
1119
da9c359e
VD		 1120 if (!vid_begin)
1121 return -EOPNOTSUPP;
1122
fad09c73 1123 mutex_lock(&chip->reg_lock);
da9c359e 1124
da9c359e 1125 do {
f1394b78 1126 err = mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1127 if (err)
1128 goto unlock;
1129
1130 if (!vlan.valid)
1131 break;
1132
1133 if (vlan.vid > vid_end)
1134 break;
1135
370b4ffb 1136 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1137 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1138 continue;
1139
cd886469 1140 if (!ds->ports[i].slave)
66e2809d
AL		 1141 continue;
1142
bd00e053 1143 if (vlan.member[i] ==
7ec60d6e 1144 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
da9c359e
VD		 1145 continue;
1146
c8652c83 1147 if (dsa_to_port(ds, i)->bridge_dev ==
fae8a25e 1148 ds->ports[port].bridge_dev)
da9c359e
VD		 1149 break; /* same bridge, check next VLAN */
1150
c8652c83 1151 if (!dsa_to_port(ds, i)->bridge_dev)
66e2809d
AL		 1152 continue;
1153
743fcc28
AL		 1154 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1155 port, vlan.vid, i,
c8652c83 1156 netdev_name(dsa_to_port(ds, i)->bridge_dev));
da9c359e
VD		 1157 err = -EOPNOTSUPP;
1158 goto unlock;
1159 }
1160 } while (vlan.vid < vid_end);
1161
1162unlock:
fad09c73 1163 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1164
1165 return err;
1166}
1167
f81ec90f
VD		 1168static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1169 bool vlan_filtering)
214cdb99 1170{
04bed143 1171 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1172 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1173 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1174 int err;
214cdb99 1175
3cf3c846 1176 if (!chip->info->max_vid)
54d77b5b
VD		 1177 return -EOPNOTSUPP;
1178
fad09c73 1179 mutex_lock(&chip->reg_lock);
385a0995 1180 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1181 mutex_unlock(&chip->reg_lock);
214cdb99 1182
0e7b9925 1183 return err;
214cdb99
VD		 1184}
1185
57d32310
VD		 1186static int
1187mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1188 const struct switchdev_obj_port_vlan *vlan,
1189 struct switchdev_trans *trans)
76e398a6 1190{
04bed143 1191 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1192 int err;
1193
3cf3c846 1194 if (!chip->info->max_vid)
54d77b5b
VD		 1195 return -EOPNOTSUPP;
1196
da9c359e
VD		 1197 /* If the requested port doesn't belong to the same bridge as the VLAN
1198 * members, do not support it (yet) and fallback to software VLAN.
1199 */
1200 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1201 vlan->vid_end);
1202 if (err)
1203 return err;
1204
76e398a6
VD		 1205 /* We don't need any dynamic resource from the kernel (yet),
1206 * so skip the prepare phase.
1207 */
1208 return 0;
1209}
1210
a4c93ae1
AL		 1211static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1212 const unsigned char *addr, u16 vid,
1213 u8 state)
1214{
1215 struct mv88e6xxx_vtu_entry vlan;
1216 struct mv88e6xxx_atu_entry entry;
1217 int err;
1218
1219 /* Null VLAN ID corresponds to the port private database */
1220 if (vid == 0)
1221 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1222 else
1223 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1224 if (err)
1225 return err;
1226
1227 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1228 ether_addr_copy(entry.mac, addr);
1229 eth_addr_dec(entry.mac);
1230
1231 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1232 if (err)
1233 return err;
1234
1235 /* Initialize a fresh ATU entry if it isn't found */
1236 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1237 !ether_addr_equal(entry.mac, addr)) {
1238 memset(&entry, 0, sizeof(entry));
1239 ether_addr_copy(entry.mac, addr);
1240 }
1241
1242 /* Purge the ATU entry only if no port is using it anymore */
1243 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1244 entry.portvec &= ~BIT(port);
1245 if (!entry.portvec)
1246 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1247 } else {
1248 entry.portvec |= BIT(port);
1249 entry.state = state;
1250 }
1251
1252 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1253}
1254
fad09c73 1255static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
c91498e1 1256 u16 vid, u8 member)
0d3b33e6 1257{
b4e47c0f 1258 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1259 int err;
1260
567aa59a 1261 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1262 if (err)
76e398a6 1263 return err;
0d3b33e6 1264
c91498e1 1265 vlan.member[port] = member;
0d3b33e6 1266
0ad5daf6 1267 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1268}
1269
f81ec90f
VD		 1270static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1271 const struct switchdev_obj_port_vlan *vlan,
1272 struct switchdev_trans *trans)
76e398a6 1273{
04bed143 1274 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1275 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1276 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
c91498e1 1277 u8 member;
76e398a6 1278 u16 vid;
76e398a6 1279
3cf3c846 1280 if (!chip->info->max_vid)
54d77b5b
VD		 1281 return;
1282
c91498e1 1283 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 1284 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 1285 else if (untagged)
7ec60d6e 1286 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 1287 else
7ec60d6e 1288 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 1289
fad09c73 1290 mutex_lock(&chip->reg_lock);
76e398a6 1291
4d5770b3 1292 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
c91498e1 1293 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
774439e5
VD		 1294 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1295 vid, untagged ? 'u' : 't');
76e398a6 1296
77064f37 1297 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
774439e5
VD		 1298 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1299 vlan->vid_end);
0d3b33e6 1300
fad09c73 1301 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1302}
1303
fad09c73 1304static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1305 int port, u16 vid)
7dad08d7 1306{
b4e47c0f 1307 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1308 int i, err;
1309
567aa59a 1310 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1311 if (err)
76e398a6 1312 return err;
7dad08d7 1313
2fb5ef09 1314 /* Tell switchdev if this VLAN is handled in software */
7ec60d6e 1315 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1316 return -EOPNOTSUPP;
7dad08d7 1317
7ec60d6e 1318 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1319
1320 /* keep the VLAN unless all ports are excluded */
f02bdffc 1321 vlan.valid = false;
370b4ffb 1322 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 1323 if (vlan.member[i] !=
1324 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1325 vlan.valid = true;
7dad08d7
VD		 1326 break;
1327 }
1328 }
1329
0ad5daf6 1330 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1331 if (err)
1332 return err;
1333
e606ca36 1334 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1335}
1336
f81ec90f
VD		 1337static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1338 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1339{
04bed143 1340 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1341 u16 pvid, vid;
1342 int err = 0;
1343
3cf3c846 1344 if (!chip->info->max_vid)
54d77b5b
VD		 1345 return -EOPNOTSUPP;
1346
fad09c73 1347 mutex_lock(&chip->reg_lock);
76e398a6 1348
77064f37 1349 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1350 if (err)
1351 goto unlock;
1352
76e398a6 1353 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1354 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1355 if (err)
1356 goto unlock;
1357
1358 if (vid == pvid) {
77064f37 1359 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1360 if (err)
1361 goto unlock;
1362 }
1363 }
1364
7dad08d7 1365unlock:
fad09c73 1366 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1367
1368 return err;
1369}
1370
1b6dd556
AS		 1371static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1372 const unsigned char *addr, u16 vid)
87820510 1373{
04bed143 1374 struct mv88e6xxx_chip *chip = ds->priv;
1b6dd556 1375 int err;
87820510 1376
fad09c73 1377 mutex_lock(&chip->reg_lock);
1b6dd556
AS		 1378 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1379 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
fad09c73 1380 mutex_unlock(&chip->reg_lock);
1b6dd556
AS		 1381
1382 return err;
87820510
VD		 1383}
1384
f81ec90f 1385static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1386 const unsigned char *addr, u16 vid)
87820510 1387{
04bed143 1388 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1389 int err;
87820510 1390
fad09c73 1391 mutex_lock(&chip->reg_lock);
6c2c1dcb 1392 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
27c0e600 1393 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
fad09c73 1394 mutex_unlock(&chip->reg_lock);
87820510 1395
83dabd1f 1396 return err;
87820510
VD		 1397}
1398
83dabd1f
VD		 1399static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1400 u16 fid, u16 vid, int port,
2bedde1a 1401 dsa_fdb_dump_cb_t *cb, void *data)
74b6ba0d 1402{
dabc1a96 1403 struct mv88e6xxx_atu_entry addr;
2bedde1a 1404 bool is_static;
74b6ba0d
VD		 1405 int err;
1406
27c0e600 1407 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96 1408 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1409
1410 do {
dabc1a96 1411 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1412 if (err)
83dabd1f 1413 return err;
74b6ba0d 1414
27c0e600 1415 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
74b6ba0d
VD		 1416 break;
1417
01bd96c8 1418 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1419 continue;
1420
2bedde1a
AS		 1421 if (!is_unicast_ether_addr(addr.mac))
1422 continue;
83dabd1f 1423
2bedde1a
AS		 1424 is_static = (addr.state ==
1425 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1426 err = cb(addr.mac, vid, is_static, data);
83dabd1f
VD		 1427 if (err)
1428 return err;
74b6ba0d
VD		 1429 } while (!is_broadcast_ether_addr(addr.mac));
1430
1431 return err;
1432}
1433
83dabd1f 1434static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2bedde1a 1435 dsa_fdb_dump_cb_t *cb, void *data)
f33475bd 1436{
b4e47c0f 1437 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 1438 .vid = chip->info->max_vid,
f33475bd 1439 };
2db9ce1f 1440 u16 fid;
f33475bd
VD		 1441 int err;
1442
2db9ce1f 1443 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 1444 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 1445 if (err)
83dabd1f 1446 return err;
2db9ce1f 1447
2bedde1a 1448 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2db9ce1f 1449 if (err)
83dabd1f 1450 return err;
2db9ce1f 1451
74b6ba0d 1452 /* Dump VLANs' Filtering Information Databases */
f33475bd 1453 do {
f1394b78 1454 err = mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 1455 if (err)
83dabd1f 1456 return err;
f33475bd
VD		 1457
1458 if (!vlan.valid)
1459 break;
1460
83dabd1f 1461 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2bedde1a 1462 cb, data);
f33475bd 1463 if (err)
83dabd1f 1464 return err;
3cf3c846 1465 } while (vlan.vid < chip->info->max_vid);
f33475bd 1466
83dabd1f
VD		 1467 return err;
1468}
1469
1470static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1471 dsa_fdb_dump_cb_t *cb, void *data)
83dabd1f 1472{
04bed143 1473 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 1474 int err;
1475
1476 mutex_lock(&chip->reg_lock);
2bedde1a 1477 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
fad09c73 1478 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 1479
1480 return err;
1481}
1482
240ea3ef
VD		 1483static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1484 struct net_device *br)
e79a8bcb 1485{
e96a6e02 1486 struct dsa_switch *ds;
240ea3ef 1487 int port;
e96a6e02 1488 int dev;
240ea3ef 1489 int err;
466dfa07 1490
240ea3ef
VD		 1491 /* Remap the Port VLAN of each local bridge group member */
1492 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1493 if (chip->ds->ports[port].bridge_dev == br) {
1494 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 1495 if (err)
240ea3ef 1496 return err;
b7666efe
VD		 1497 }
1498 }
1499
e96a6e02
VD		 1500 if (!mv88e6xxx_has_pvt(chip))
1501 return 0;
1502
1503 /* Remap the Port VLAN of each cross-chip bridge group member */
1504 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1505 ds = chip->ds->dst->ds[dev];
1506 if (!ds)
1507 break;
1508
1509 for (port = 0; port < ds->num_ports; ++port) {
1510 if (ds->ports[port].bridge_dev == br) {
1511 err = mv88e6xxx_pvt_map(chip, dev, port);
1512 if (err)
1513 return err;
1514 }
1515 }
1516 }
1517
240ea3ef
VD		 1518 return 0;
1519}
1520
1521static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1522 struct net_device *br)
1523{
1524 struct mv88e6xxx_chip *chip = ds->priv;
1525 int err;
1526
1527 mutex_lock(&chip->reg_lock);
1528 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 1529 mutex_unlock(&chip->reg_lock);
a6692754 1530
466dfa07 1531 return err;
e79a8bcb
VD		 1532}
1533
f123f2fb
VD		 1534static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1535 struct net_device *br)
66d9cd0f 1536{
04bed143 1537 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 1538
fad09c73 1539 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 1540 if (mv88e6xxx_bridge_map(chip, br) ||
1541 mv88e6xxx_port_vlan_map(chip, port))
1542 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 1543 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 1544}
1545
aec5ac88
VD		 1546static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1547 int port, struct net_device *br)
1548{
1549 struct mv88e6xxx_chip *chip = ds->priv;
1550 int err;
1551
1552 if (!mv88e6xxx_has_pvt(chip))
1553 return 0;
1554
1555 mutex_lock(&chip->reg_lock);
1556 err = mv88e6xxx_pvt_map(chip, dev, port);
1557 mutex_unlock(&chip->reg_lock);
1558
1559 return err;
1560}
1561
1562static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1563 int port, struct net_device *br)
1564{
1565 struct mv88e6xxx_chip *chip = ds->priv;
1566
1567 if (!mv88e6xxx_has_pvt(chip))
1568 return;
1569
1570 mutex_lock(&chip->reg_lock);
1571 if (mv88e6xxx_pvt_map(chip, dev, port))
1572 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1573 mutex_unlock(&chip->reg_lock);
1574}
1575
17e708ba
VD		 1576static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1577{
1578 if (chip->info->ops->reset)
1579 return chip->info->ops->reset(chip);
1580
1581 return 0;
1582}
1583
309eca6d
VD		 1584static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1585{
1586 struct gpio_desc *gpiod = chip->reset;
1587
1588 /* If there is a GPIO connected to the reset pin, toggle it */
1589 if (gpiod) {
1590 gpiod_set_value_cansleep(gpiod, 1);
1591 usleep_range(10000, 20000);
1592 gpiod_set_value_cansleep(gpiod, 0);
1593 usleep_range(10000, 20000);
1594 }
1595}
1596
4ac4b5a6 1597static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 1598{
4ac4b5a6 1599 int i, err;
552238b5 1600
4ac4b5a6 1601 /* Set all ports to the Disabled state */
370b4ffb 1602 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 1603 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 1604 if (err)
1605 return err;
552238b5
VD		 1606 }
1607
4ac4b5a6
VD		 1608 /* Wait for transmit queues to drain,
1609 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1610 */
552238b5
VD		 1611 usleep_range(2000, 4000);
1612
4ac4b5a6
VD		 1613 return 0;
1614}
1615
1616static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1617{
4ac4b5a6
VD		 1618 int err;
1619
1620 err = mv88e6xxx_disable_ports(chip);
1621 if (err)
1622 return err;
1623
309eca6d 1624 mv88e6xxx_hardware_reset(chip);
552238b5 1625
17e708ba 1626 return mv88e6xxx_software_reset(chip);
552238b5
VD		 1627}
1628
4314557c 1629static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 1630 enum mv88e6xxx_frame_mode frame,
1631 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 1632{
1633 int err;
1634
4314557c
VD		 1635 if (!chip->info->ops->port_set_frame_mode)
1636 return -EOPNOTSUPP;
1637
1638 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 1639 if (err)
1640 return err;
1641
4314557c
VD		 1642 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1643 if (err)
1644 return err;
1645
1646 if (chip->info->ops->port_set_ether_type)
1647 return chip->info->ops->port_set_ether_type(chip, port, etype);
1648
1649 return 0;
56995cbc
AL		 1650}
1651
4314557c 1652static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 1653{
4314557c 1654 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 1655 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1656 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1657}
56995cbc 1658
4314557c
VD		 1659static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1660{
1661 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 1662 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1663 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1664}
56995cbc 1665
4314557c
VD		 1666static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1667{
1668 return mv88e6xxx_set_port_mode(chip, port,
1669 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 1670 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1671 ETH_P_EDSA);
4314557c 1672}
56995cbc 1673
4314557c
VD		 1674static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1675{
1676 if (dsa_is_dsa_port(chip->ds, port))
1677 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1678
2b3e9891 1679 if (dsa_is_user_port(chip->ds, port))
4314557c 1680 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 1681
4314557c
VD		 1682 /* Setup CPU port mode depending on its supported tag format */
1683 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1684 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1685
4314557c
VD		 1686 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1687 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 1688
4314557c 1689 return -EINVAL;
56995cbc
AL		 1690}
1691
601aeed3 1692static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 1693{
601aeed3 1694 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 1695
601aeed3 1696 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 1697}
56995cbc 1698
601aeed3 1699static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 1700{
601aeed3 1701 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 1702
601aeed3
VD		 1703 /* Upstream ports flood frames with unknown unicast or multicast DA */
1704 if (chip->info->ops->port_set_egress_floods)
1705 return chip->info->ops->port_set_egress_floods(chip, port,
1706 flood, flood);
ea698f4f 1707
601aeed3 1708 return 0;
ea698f4f
VD		 1709}
1710
6d91782f
AL		 1711static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1712 bool on)
1713{
523a8904
VD		 1714 if (chip->info->ops->serdes_power)
1715 return chip->info->ops->serdes_power(chip, port, on);
04aca993 1716
523a8904 1717 return 0;
6d91782f
AL		 1718}
1719
fad09c73 1720static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 1721{
fad09c73 1722 struct dsa_switch *ds = chip->ds;
0e7b9925 1723 int err;
54d792f2 1724 u16 reg;
d827e88a 1725
d78343d2
VD		 1726 /* MAC Forcing register: don't force link, speed, duplex or flow control
1727 * state to any particular values on physical ports, but force the CPU
1728 * port and all DSA ports to their maximum bandwidth and full duplex.
1729 */
1730 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1731 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1732 SPEED_MAX, DUPLEX_FULL,
1733 PHY_INTERFACE_MODE_NA);
1734 else
1735 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1736 SPEED_UNFORCED, DUPLEX_UNFORCED,
1737 PHY_INTERFACE_MODE_NA);
1738 if (err)
1739 return err;
54d792f2
AL		 1740
1741 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1742 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1743 * tunneling, determine priority by looking at 802.1p and IP
1744 * priority fields (IP prio has precedence), and set STP state
1745 * to Forwarding.
1746 *
1747 * If this is the CPU link, use DSA or EDSA tagging depending
1748 * on which tagging mode was configured.
1749 *
1750 * If this is a link to another switch, use DSA tagging mode.
1751 *
1752 * If this is the upstream port for this switch, enable
1753 * forwarding of unknown unicasts and multicasts.
1754 */
a89b433b
VD		 1755 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1756 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1757 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1758 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 1759 if (err)
1760 return err;
6083ce71 1761
601aeed3 1762 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 1763 if (err)
1764 return err;
54d792f2 1765
601aeed3 1766 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 1767 if (err)
1768 return err;
1769
04aca993
AL		 1770 /* Enable the SERDES interface for DSA and CPU ports. Normal
1771 * ports SERDES are enabled when the port is enabled, thus
1772 * saving a bit of power.
13a7ebb3 1773 */
04aca993
AL		 1774 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1775 err = mv88e6xxx_serdes_power(chip, port, true);
1776 if (err)
1777 return err;
1778 }
13a7ebb3 1779
8efdda4a 1780 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 1781 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 1782 * untagged frames on this port, do a destination address lookup on all
1783 * received packets as usual, disable ARP mirroring and don't send a
1784 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 1785 */
a23b2961
AL		 1786 err = mv88e6xxx_port_set_map_da(chip, port);
1787 if (err)
1788 return err;
8efdda4a 1789
a23b2961
AL		 1790 reg = 0;
1791 if (chip->info->ops->port_set_upstream_port) {
1792 err = chip->info->ops->port_set_upstream_port(
1793 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 1794 if (err)
1795 return err;
54d792f2
AL		 1796 }
1797
a23b2961 1798 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 1799 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 1800 if (err)
1801 return err;
1802
cd782656
VD		 1803 if (chip->info->ops->port_set_jumbo_size) {
1804 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 1805 if (err)
1806 return err;
1807 }
1808
54d792f2
AL		 1809 /* Port Association Vector: when learning source addresses
1810 * of packets, add the address to the address database using
1811 * a port bitmap that has only the bit for this port set and
1812 * the other bits clear.
1813 */
4c7ea3c0 1814 reg = 1 << port;
996ecb82
VD		 1815 /* Disable learning for CPU port */
1816 if (dsa_is_cpu_port(ds, port))
65fa4027 1817 reg = 0;
4c7ea3c0 1818
2a4614e4
VD		 1819 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1820 reg);
0e7b9925
AL		 1821 if (err)
1822 return err;
54d792f2
AL		 1823
1824 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 1825 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1826 0x0000);
0e7b9925
AL		 1827 if (err)
1828 return err;
54d792f2 1829
0898432c
VD		 1830 if (chip->info->ops->port_pause_limit) {
1831 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 1832 if (err)
1833 return err;
b35d322a 1834 }
54d792f2 1835
c8c94891
VD		 1836 if (chip->info->ops->port_disable_learn_limit) {
1837 err = chip->info->ops->port_disable_learn_limit(chip, port);
1838 if (err)
1839 return err;
1840 }
1841
9dbfb4e1
VD		 1842 if (chip->info->ops->port_disable_pri_override) {
1843 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 1844 if (err)
1845 return err;
ef0a7318 1846 }
2bbb33be 1847
ef0a7318
AL		 1848 if (chip->info->ops->port_tag_remap) {
1849 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 1850 if (err)
1851 return err;
54d792f2
AL		 1852 }
1853
ef70b111
AL		 1854 if (chip->info->ops->port_egress_rate_limiting) {
1855 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 1856 if (err)
1857 return err;
54d792f2
AL		 1858 }
1859
ea698f4f 1860 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 1861 if (err)
1862 return err;
d827e88a 1863
207afda1 1864 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 1865 * database, and allow bidirectional communication between the
1866 * CPU and DSA port(s), and the other ports.
d827e88a 1867 */
b4e48c50 1868 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 1869 if (err)
1870 return err;
2db9ce1f 1871
240ea3ef 1872 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 1873 if (err)
1874 return err;
d827e88a
GR		 1875
1876 /* Default VLAN ID and priority: don't set a default VLAN
1877 * ID, and set the default packet priority to zero.
1878 */
b7929fb3 1879 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 1880}
1881
04aca993
AL		 1882static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1883 struct phy_device *phydev)
1884{
1885 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 1886 int err;
04aca993
AL		 1887
1888 mutex_lock(&chip->reg_lock);
523a8904 1889 err = mv88e6xxx_serdes_power(chip, port, true);
04aca993
AL		 1890 mutex_unlock(&chip->reg_lock);
1891
1892 return err;
1893}
1894
1895static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1896 struct phy_device *phydev)
1897{
1898 struct mv88e6xxx_chip *chip = ds->priv;
1899
1900 mutex_lock(&chip->reg_lock);
523a8904
VD		 1901 if (mv88e6xxx_serdes_power(chip, port, false))
1902 dev_err(chip->dev, "failed to power off SERDES\n");
04aca993
AL		 1903 mutex_unlock(&chip->reg_lock);
1904}
1905
2cfcd964
VD		 1906static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
1907 unsigned int ageing_time)
1908{
04bed143 1909 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 1910 int err;
1911
1912 mutex_lock(&chip->reg_lock);
720c6343 1913 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 1914 mutex_unlock(&chip->reg_lock);
1915
1916 return err;
1917}
1918
9729934c 1919static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 1920{
fad09c73 1921 struct dsa_switch *ds = chip->ds;
b0745e87 1922 u32 upstream_port = dsa_upstream_port(ds);
552238b5 1923 int err;
54d792f2 1924
fa8d1179
VD		 1925 if (chip->info->ops->set_cpu_port) {
1926 err = chip->info->ops->set_cpu_port(chip, upstream_port);
33641994
AL		 1927 if (err)
1928 return err;
1929 }
1930
fa8d1179
VD		 1931 if (chip->info->ops->set_egress_port) {
1932 err = chip->info->ops->set_egress_port(chip, upstream_port);
33641994
AL		 1933 if (err)
1934 return err;
1935 }
b0745e87 1936
50484ff4 1937 /* Disable remote management, and set the switch's DSA device number. */
d77f4321
VD		 1938 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
1939 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
a935c052 1940 (ds->index & 0x1f));
50484ff4
VD		 1941 if (err)
1942 return err;
1943
54d792f2 1944 /* Configure the IP ToS mapping registers. */
ccba8f3a 1945 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
48ace4ef 1946 if (err)
08a01261 1947 return err;
ccba8f3a 1948 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
48ace4ef 1949 if (err)
08a01261 1950 return err;
ccba8f3a 1951 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
48ace4ef 1952 if (err)
08a01261 1953 return err;
ccba8f3a 1954 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
48ace4ef 1955 if (err)
08a01261 1956 return err;
ccba8f3a 1957 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
48ace4ef 1958 if (err)
08a01261 1959 return err;
ccba8f3a 1960 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
48ace4ef 1961 if (err)
08a01261 1962 return err;
ccba8f3a 1963 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
48ace4ef 1964 if (err)
08a01261 1965 return err;
ccba8f3a 1966 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
48ace4ef 1967 if (err)
08a01261 1968 return err;
54d792f2
AL		 1969
1970 /* Configure the IEEE 802.1p priority mapping register. */
ccba8f3a 1971 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
48ace4ef 1972 if (err)
08a01261 1973 return err;
54d792f2 1974
de227387
AL		 1975 /* Initialize the statistics unit */
1976 err = mv88e6xxx_stats_set_histogram(chip);
1977 if (err)
1978 return err;
1979
9729934c 1980 /* Clear the statistics counters for all ports */
57d1ef38
VD		 1981 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
1982 MV88E6XXX_G1_STATS_OP_BUSY |
1983 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
9729934c
VD		 1984 if (err)
1985 return err;
1986
1987 /* Wait for the flush to complete. */
7f9ef3af 1988 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 1989 if (err)
1990 return err;
1991
1992 return 0;
1993}
1994
f81ec90f 1995static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 1996{
04bed143 1997 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 1998 int err;
a1a6a4d1
VD		 1999 int i;
2000
fad09c73 2001 chip->ds = ds;
a3c53be5 2002 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2003
fad09c73 2004 mutex_lock(&chip->reg_lock);
08a01261 2005
9729934c 2006 /* Setup Switch Port Registers */
370b4ffb 2007 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
91dee144
VD		 2008 if (dsa_is_unused_port(ds, i))
2009 continue;
2010
9729934c
VD		 2011 err = mv88e6xxx_setup_port(chip, i);
2012 if (err)
2013 goto unlock;
2014 }
2015
2016 /* Setup Switch Global 1 Registers */
2017 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2018 if (err)
2019 goto unlock;
2020
9729934c 2021 /* Setup Switch Global 2 Registers */
9069c13a 2022 if (chip->info->global2_addr) {
9729934c 2023 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2024 if (err)
2025 goto unlock;
2026 }
08a01261 2027
cd8da8bb
VD		 2028 err = mv88e6xxx_irl_setup(chip);
2029 if (err)
2030 goto unlock;
2031
04a69a17
VD		 2032 err = mv88e6xxx_mac_setup(chip);
2033 if (err)
2034 goto unlock;
2035
1b17aedf
VD		 2036 err = mv88e6xxx_phy_setup(chip);
2037 if (err)
2038 goto unlock;
2039
b486d7c9
VD		 2040 err = mv88e6xxx_vtu_setup(chip);
2041 if (err)
2042 goto unlock;
2043
81228996
VD		 2044 err = mv88e6xxx_pvt_setup(chip);
2045 if (err)
2046 goto unlock;
2047
a2ac29d2
VD		 2048 err = mv88e6xxx_atu_setup(chip);
2049 if (err)
2050 goto unlock;
2051
9e907d73
VD		 2052 err = mv88e6xxx_pot_setup(chip);
2053 if (err)
2054 goto unlock;
2055
51c901a7
VD		 2056 err = mv88e6xxx_rsvd2cpu_setup(chip);
2057 if (err)
2058 goto unlock;
6e55f698 2059
6b17e864 2060unlock:
fad09c73 2061 mutex_unlock(&chip->reg_lock);
db687a56 2062
48ace4ef 2063 return err;
54d792f2
AL		 2064}
2065
e57e5e77 2066static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2067{
0dd12d54
AL		 2068 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2069 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2070 u16 val;
2071 int err;
fd3a0ee4 2072
ee26a228
AL		 2073 if (!chip->info->ops->phy_read)
2074 return -EOPNOTSUPP;
2075
fad09c73 2076 mutex_lock(&chip->reg_lock);
ee26a228 2077 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2078 mutex_unlock(&chip->reg_lock);
e57e5e77 2079
da9f3301
AL		 2080 if (reg == MII_PHYSID2) {
2081 /* Some internal PHYS don't have a model number. Use
2082 * the mv88e6390 family model number instead.
2083 */
2084 if (!(val & 0x3f0))
107fcc10 2085 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
da9f3301
AL		 2086 }
2087
e57e5e77 2088 return err ? err : val;
fd3a0ee4
AL		 2089}
2090
e57e5e77 2091static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2092{
0dd12d54
AL		 2093 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2094 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2095 int err;
fd3a0ee4 2096
ee26a228
AL		 2097 if (!chip->info->ops->phy_write)
2098 return -EOPNOTSUPP;
2099
fad09c73 2100 mutex_lock(&chip->reg_lock);
ee26a228 2101 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2102 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2103
2104 return err;
fd3a0ee4
AL		 2105}
2106
fad09c73 2107static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2108 struct device_node *np,
2109 bool external)
b516d453
AL		 2110{
2111 static int index;
0dd12d54 2112 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2113 struct mii_bus *bus;
2114 int err;
2115
0dd12d54 2116 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2117 if (!bus)
2118 return -ENOMEM;
2119
0dd12d54 2120 mdio_bus = bus->priv;
a3c53be5 2121 mdio_bus->bus = bus;
0dd12d54 2122 mdio_bus->chip = chip;
a3c53be5
AL		 2123 INIT_LIST_HEAD(&mdio_bus->list);
2124 mdio_bus->external = external;
0dd12d54 2125
b516d453
AL		 2126 if (np) {
2127 bus->name = np->full_name;
f7ce9103 2128 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
b516d453
AL		 2129 } else {
2130 bus->name = "mv88e6xxx SMI";
2131 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2132 }
2133
2134 bus->read = mv88e6xxx_mdio_read;
2135 bus->write = mv88e6xxx_mdio_write;
fad09c73 2136 bus->parent = chip->dev;
b516d453 2137
a3c53be5
AL		 2138 if (np)
2139 err = of_mdiobus_register(bus, np);
b516d453
AL		 2140 else
2141 err = mdiobus_register(bus);
2142 if (err) {
fad09c73 2143 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2144 return err;
b516d453 2145 }
a3c53be5
AL		 2146
2147 if (external)
2148 list_add_tail(&mdio_bus->list, &chip->mdios);
2149 else
2150 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2151
2152 return 0;
a3c53be5 2153}
b516d453 2154
a3c53be5
AL		 2155static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2156 { .compatible = "marvell,mv88e6xxx-mdio-external",
2157 .data = (void *)true },
2158 { },
2159};
b516d453 2160
a3c53be5
AL		 2161static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2162 struct device_node *np)
2163{
2164 const struct of_device_id *match;
2165 struct device_node *child;
2166 int err;
2167
2168 /* Always register one mdio bus for the internal/default mdio
2169 * bus. This maybe represented in the device tree, but is
2170 * optional.
2171 */
2172 child = of_get_child_by_name(np, "mdio");
2173 err = mv88e6xxx_mdio_register(chip, child, false);
2174 if (err)
2175 return err;
2176
2177 /* Walk the device tree, and see if there are any other nodes
2178 * which say they are compatible with the external mdio
2179 * bus.
2180 */
2181 for_each_available_child_of_node(np, child) {
2182 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2183 if (match) {
2184 err = mv88e6xxx_mdio_register(chip, child, true);
2185 if (err)
2186 return err;
2187 }
2188 }
2189
2190 return 0;
b516d453
AL		 2191}
2192
a3c53be5 2193static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2194
2195{
a3c53be5
AL		 2196 struct mv88e6xxx_mdio_bus *mdio_bus;
2197 struct mii_bus *bus;
b516d453 2198
a3c53be5
AL		 2199 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2200 bus = mdio_bus->bus;
b516d453 2201
a3c53be5
AL		 2202 mdiobus_unregister(bus);
2203 }
b516d453
AL		 2204}
2205
855b1932
VD		 2206static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2207{
04bed143 2208 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2209
2210 return chip->eeprom_len;
2211}
2212
855b1932
VD		 2213static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2214 struct ethtool_eeprom *eeprom, u8 *data)
2215{
04bed143 2216 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2217 int err;
2218
ee4dc2e7
VD		 2219 if (!chip->info->ops->get_eeprom)
2220 return -EOPNOTSUPP;
855b1932 2221
ee4dc2e7
VD		 2222 mutex_lock(&chip->reg_lock);
2223 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2224 mutex_unlock(&chip->reg_lock);
2225
2226 if (err)
2227 return err;
2228
2229 eeprom->magic = 0xc3ec4951;
2230
2231 return 0;
2232}
2233
855b1932
VD		 2234static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2235 struct ethtool_eeprom *eeprom, u8 *data)
2236{
04bed143 2237 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2238 int err;
2239
ee4dc2e7
VD		 2240 if (!chip->info->ops->set_eeprom)
2241 return -EOPNOTSUPP;
2242
855b1932
VD		 2243 if (eeprom->magic != 0xc3ec4951)
2244 return -EINVAL;
2245
2246 mutex_lock(&chip->reg_lock);
ee4dc2e7 2247 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2248 mutex_unlock(&chip->reg_lock);
2249
2250 return err;
2251}
2252
b3469dd8 2253static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2254 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2255 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2256 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2257 .phy_read = mv88e6185_phy_ppu_read,
2258 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2259 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2260 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2261 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2262 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2263 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2264 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2265 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2266 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2267 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2268 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2269 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2270 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2271 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2272 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2273 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2274 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2275 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2276 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2277 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2278 .pot_clear = mv88e6xxx_g2_pot_clear,
a199d8b6
VD		 2279 .ppu_enable = mv88e6185_g1_ppu_enable,
2280 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2281 .reset = mv88e6185_g1_reset,
f1394b78 2282 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2283 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2284};
2285
2286static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2287 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2288 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2289 .phy_read = mv88e6185_phy_ppu_read,
2290 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2291 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2292 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2293 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2294 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2295 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2296 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2297 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2298 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2299 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2300 .stats_get_stats = mv88e6095_stats_get_stats,
51c901a7 2301 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2302 .ppu_enable = mv88e6185_g1_ppu_enable,
2303 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2304 .reset = mv88e6185_g1_reset,
f1394b78 2305 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2306 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2307};
2308
7d381a02 2309static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2310 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2311 .irl_init_all = mv88e6352_g2_irl_init_all,
7d381a02
SE		 2312 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2313 .phy_read = mv88e6xxx_g2_smi_phy_read,
2314 .phy_write = mv88e6xxx_g2_smi_phy_write,
2315 .port_set_link = mv88e6xxx_port_set_link,
2316 .port_set_duplex = mv88e6xxx_port_set_duplex,
2317 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2318 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2319 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2320 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2321 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2322 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2323 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 2324 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2325 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2326 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2327 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2328 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2329 .stats_get_strings = mv88e6095_stats_get_strings,
2330 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2331 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2332 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2333 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2334 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2335 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2336 .reset = mv88e6352_g1_reset,
f1394b78 2337 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2338 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
7d381a02
SE		 2339};
2340
b3469dd8 2341static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2342 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2343 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2344 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2345 .phy_read = mv88e6xxx_g2_smi_phy_read,
2346 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2347 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2348 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2349 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2350 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2351 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2354 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2355 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2356 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2357 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2358 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2359 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2360 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2361 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2362 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2363 .reset = mv88e6352_g1_reset,
f1394b78 2364 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2365 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2366};
2367
2368static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2369 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2370 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2371 .phy_read = mv88e6185_phy_ppu_read,
2372 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2373 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2374 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2375 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2376 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2377 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2378 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2379 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2380 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 2381 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2383 .port_pause_limit = mv88e6097_port_pause_limit,
a605a0fe 2384 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2385 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2386 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2387 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2388 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2389 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2390 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2391 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2392 .ppu_enable = mv88e6185_g1_ppu_enable,
2393 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2394 .reset = mv88e6185_g1_reset,
f1394b78 2395 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2396 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2397};
2398
990e27b0
VD		 2399static const struct mv88e6xxx_ops mv88e6141_ops = {
2400 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 2401 .irl_init_all = mv88e6352_g2_irl_init_all,
990e27b0
VD		 2402 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2403 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2405 .phy_read = mv88e6xxx_g2_smi_phy_read,
2406 .phy_write = mv88e6xxx_g2_smi_phy_write,
2407 .port_set_link = mv88e6xxx_port_set_link,
2408 .port_set_duplex = mv88e6xxx_port_set_duplex,
2409 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2410 .port_set_speed = mv88e6390_port_set_speed,
2411 .port_tag_remap = mv88e6095_port_tag_remap,
2412 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2413 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2414 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2415 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 2416 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2417 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 2418 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2419 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2420 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2421 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2422 .stats_get_strings = mv88e6320_stats_get_strings,
2423 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2424 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2425 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 2426 .watchdog_ops = &mv88e6390_watchdog_ops,
2427 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2428 .pot_clear = mv88e6xxx_g2_pot_clear,
990e27b0 2429 .reset = mv88e6352_g1_reset,
f1394b78 2430 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2431 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
990e27b0
VD		 2432};
2433
b3469dd8 2434static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2435 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2436 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2437 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2438 .phy_read = mv88e6xxx_g2_smi_phy_read,
2439 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2440 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2441 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2442 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2443 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2444 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2445 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2446 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2447 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2448 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2449 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2450 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2451 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2452 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2453 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2454 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2455 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2456 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2457 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2458 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2459 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2460 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2461 .reset = mv88e6352_g1_reset,
f1394b78 2462 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2463 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2464};
2465
2466static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2467 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2468 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2469 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2470 .phy_read = mv88e6165_phy_read,
2471 .phy_write = mv88e6165_phy_write,
08ef7f10 2472 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2473 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2474 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 2475 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2476 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2477 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2478 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2479 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2480 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2481 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2482 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2483 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2484 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2485 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2486 .reset = mv88e6352_g1_reset,
f1394b78 2487 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2488 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2489};
2490
2491static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2492 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2493 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2494 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2495 .phy_read = mv88e6xxx_g2_smi_phy_read,
2496 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2497 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2498 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2499 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2500 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2501 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2502 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2503 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2504 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2505 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2506 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2507 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2508 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2509 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2510 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2511 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2512 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2513 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2514 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2515 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2516 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2517 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2518 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2519 .reset = mv88e6352_g1_reset,
f1394b78 2520 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2521 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2522};
2523
2524static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 2525 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2526 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2527 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2528 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2529 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2530 .phy_read = mv88e6xxx_g2_smi_phy_read,
2531 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2532 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2533 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2534 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2535 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2536 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2537 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2538 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2539 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2540 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2541 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2542 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2545 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2546 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2547 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2548 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2549 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2550 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2551 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2552 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2553 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2554 .reset = mv88e6352_g1_reset,
f1394b78 2555 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2556 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2557 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2558};
2559
2560static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 2561 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2562 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2563 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2564 .phy_read = mv88e6xxx_g2_smi_phy_read,
2565 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2566 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2567 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2568 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2569 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2570 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2571 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2572 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2573 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2574 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2575 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2576 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2577 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2578 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2579 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2580 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2581 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2582 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2583 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2584 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2585 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2586 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2587 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2588 .reset = mv88e6352_g1_reset,
f1394b78 2589 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2590 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2591};
2592
2593static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 2594 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2595 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2596 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2597 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2598 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2599 .phy_read = mv88e6xxx_g2_smi_phy_read,
2600 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2601 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2602 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2603 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2604 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2605 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2606 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2607 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2608 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2609 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2610 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2611 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2612 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2613 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2614 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2615 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2616 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2617 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2618 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2619 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2620 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2621 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2622 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2623 .reset = mv88e6352_g1_reset,
f1394b78 2624 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2625 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2626 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2627};
2628
2629static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 2630 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2631 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2632 .phy_read = mv88e6185_phy_ppu_read,
2633 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2634 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2635 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2636 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2637 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2638 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 2639 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 2640 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2641 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2642 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2643 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2644 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2645 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2646 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2647 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2648 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2649 .ppu_enable = mv88e6185_g1_ppu_enable,
2650 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2651 .reset = mv88e6185_g1_reset,
f1394b78 2652 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2653 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2654};
2655
1a3b39ec 2656static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 2657 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2658 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2659 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2660 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2661 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2662 .phy_read = mv88e6xxx_g2_smi_phy_read,
2663 .phy_write = mv88e6xxx_g2_smi_phy_write,
2664 .port_set_link = mv88e6xxx_port_set_link,
2665 .port_set_duplex = mv88e6xxx_port_set_duplex,
2666 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2667 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2668 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2669 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2670 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2671 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2672 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2673 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2674 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2675 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2676 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2677 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2678 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2679 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2680 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2681 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2682 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2683 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2684 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2685 .reset = mv88e6352_g1_reset,
931d1822
VD		 2686 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2687 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2688 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2689};
2690
2691static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 2692 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2693 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2694 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2695 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2696 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2697 .phy_read = mv88e6xxx_g2_smi_phy_read,
2698 .phy_write = mv88e6xxx_g2_smi_phy_write,
2699 .port_set_link = mv88e6xxx_port_set_link,
2700 .port_set_duplex = mv88e6xxx_port_set_duplex,
2701 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2702 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 2703 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2704 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2705 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2706 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2707 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2708 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2709 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2710 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2711 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2712 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2713 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2714 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2715 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2716 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2717 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2718 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2719 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2720 .reset = mv88e6352_g1_reset,
931d1822
VD		 2721 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2722 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2723 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2724};
2725
2726static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 2727 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2728 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2729 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2730 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2731 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2732 .phy_read = mv88e6xxx_g2_smi_phy_read,
2733 .phy_write = mv88e6xxx_g2_smi_phy_write,
2734 .port_set_link = mv88e6xxx_port_set_link,
2735 .port_set_duplex = mv88e6xxx_port_set_duplex,
2736 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2737 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2738 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2739 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2740 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2741 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2742 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2743 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2744 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2745 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2746 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2747 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2748 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2749 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2750 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2751 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2752 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2753 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2754 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2755 .reset = mv88e6352_g1_reset,
931d1822
VD		 2756 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2757 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2758 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2759};
2760
b3469dd8 2761static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 2762 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2763 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2764 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2765 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2766 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2767 .phy_read = mv88e6xxx_g2_smi_phy_read,
2768 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2769 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2770 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2771 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2772 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2773 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2774 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2775 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2776 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2777 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2778 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2779 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2780 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2781 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2782 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2783 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2784 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2785 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2786 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2787 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2788 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2789 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2790 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2791 .reset = mv88e6352_g1_reset,
f1394b78 2792 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2793 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2794 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2795};
2796
1a3b39ec 2797static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 2798 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2799 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2800 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2801 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2802 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2803 .phy_read = mv88e6xxx_g2_smi_phy_read,
2804 .phy_write = mv88e6xxx_g2_smi_phy_write,
2805 .port_set_link = mv88e6xxx_port_set_link,
2806 .port_set_duplex = mv88e6xxx_port_set_duplex,
2807 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2808 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2809 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2810 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2811 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2812 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2813 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 2814 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 2815 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2816 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2817 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2818 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2819 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2820 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2821 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2822 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2823 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2824 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2825 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2826 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2827 .reset = mv88e6352_g1_reset,
931d1822
VD		 2828 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2829 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2830 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2831};
2832
b3469dd8 2833static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 2834 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 2835 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2836 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2837 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2838 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2839 .phy_read = mv88e6xxx_g2_smi_phy_read,
2840 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2841 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2842 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2843 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2844 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2845 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2846 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2847 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2848 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2849 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2850 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2851 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2852 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2853 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2854 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2855 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2856 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2857 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2858 .set_egress_port = mv88e6095_g1_set_egress_port,
51c901a7 2859 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2860 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2861 .reset = mv88e6352_g1_reset,
f1394b78 2862 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2863 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2864};
2865
2866static const struct mv88e6xxx_ops mv88e6321_ops = {
bd807204 2867 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 2868 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2869 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2870 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2871 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2872 .phy_read = mv88e6xxx_g2_smi_phy_read,
2873 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2874 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2875 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2876 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2877 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2878 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2879 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2880 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2881 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2882 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2883 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2884 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2885 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2886 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2887 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2888 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2889 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2890 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2891 .set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 2892 .reset = mv88e6352_g1_reset,
f1394b78 2893 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2894 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2895};
2896
16e329ae
VD		 2897static const struct mv88e6xxx_ops mv88e6341_ops = {
2898 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 2899 .irl_init_all = mv88e6352_g2_irl_init_all,
16e329ae
VD		 2900 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2901 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2902 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2903 .phy_read = mv88e6xxx_g2_smi_phy_read,
2904 .phy_write = mv88e6xxx_g2_smi_phy_write,
2905 .port_set_link = mv88e6xxx_port_set_link,
2906 .port_set_duplex = mv88e6xxx_port_set_duplex,
2907 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2908 .port_set_speed = mv88e6390_port_set_speed,
2909 .port_tag_remap = mv88e6095_port_tag_remap,
2910 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2911 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2912 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2913 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 2914 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2915 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 2916 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2917 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2918 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2919 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2920 .stats_get_strings = mv88e6320_stats_get_strings,
2921 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2922 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2923 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 2924 .watchdog_ops = &mv88e6390_watchdog_ops,
2925 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2926 .pot_clear = mv88e6xxx_g2_pot_clear,
16e329ae 2927 .reset = mv88e6352_g1_reset,
f1394b78 2928 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2929 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
16e329ae
VD		 2930};
2931
b3469dd8 2932static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 2933 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2934 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2935 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2936 .phy_read = mv88e6xxx_g2_smi_phy_read,
2937 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2938 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2939 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2940 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2941 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2942 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2943 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2944 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2945 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2946 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2947 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2948 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2949 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2950 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2951 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2952 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2953 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2954 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2955 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2956 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2957 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2958 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2959 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2960 .reset = mv88e6352_g1_reset,
f1394b78 2961 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2962 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2963};
2964
2965static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 2966 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2967 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2968 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2969 .phy_read = mv88e6xxx_g2_smi_phy_read,
2970 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2971 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2972 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2973 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2974 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2975 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2976 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2977 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2978 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2979 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2980 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2981 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2984 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2985 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2986 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2987 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2988 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2989 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2990 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2991 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2992 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2993 .reset = mv88e6352_g1_reset,
f1394b78 2994 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2995 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2996};
2997
2998static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 2999 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 3000 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3001 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3002 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3003 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3004 .phy_read = mv88e6xxx_g2_smi_phy_read,
3005 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3006 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3007 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3008 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3009 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3010 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3011 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3012 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3013 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3014 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3015 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3016 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3017 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3018 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3019 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3020 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3021 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3022 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3023 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3024 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3025 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3026 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3027 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3028 .reset = mv88e6352_g1_reset,
f1394b78 3029 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3030 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 3031 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 3032};
3033
1a3b39ec 3034static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3035 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 3036 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3037 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3038 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3039 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3040 .phy_read = mv88e6xxx_g2_smi_phy_read,
3041 .phy_write = mv88e6xxx_g2_smi_phy_write,
3042 .port_set_link = mv88e6xxx_port_set_link,
3043 .port_set_duplex = mv88e6xxx_port_set_duplex,
3044 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3045 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3046 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3047 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3048 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3049 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3050 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3051 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3052 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 3053 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3054 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3055 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3056 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3057 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3058 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3059 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3060 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3061 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3062 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3063 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3064 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3065 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3066 .reset = mv88e6352_g1_reset,
931d1822
VD		 3067 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3068 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3069 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3070};
3071
3072static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3073 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 3074 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3075 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3076 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3077 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3078 .phy_read = mv88e6xxx_g2_smi_phy_read,
3079 .phy_write = mv88e6xxx_g2_smi_phy_write,
3080 .port_set_link = mv88e6xxx_port_set_link,
3081 .port_set_duplex = mv88e6xxx_port_set_duplex,
3082 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3083 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3084 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3085 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3086 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3087 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3088 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3089 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3090 .port_pause_limit = mv88e6390_port_pause_limit,
bb0a2675 3091 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3092 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3093 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3094 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3095 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3096 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3097 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3098 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3099 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3100 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3101 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3102 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3103 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3104 .reset = mv88e6352_g1_reset,
931d1822
VD		 3105 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3106 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3107 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3108};
3109
f81ec90f
VD		 3110static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3111 [MV88E6085] = {
107fcc10 3112 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 3113 .family = MV88E6XXX_FAMILY_6097,
3114 .name = "Marvell 88E6085",
3115 .num_databases = 4096,
3116 .num_ports = 10,
3cf3c846 3117 .max_vid = 4095,
9dddd478 3118 .port_base_addr = 0x10,
a935c052 3119 .global1_addr = 0x1b,
9069c13a 3120 .global2_addr = 0x1c,
acddbd21 3121 .age_time_coeff = 15000,
dc30c35b 3122 .g1_irqs = 8,
d6c5e6af 3123 .g2_irqs = 10,
e606ca36 3124 .atu_move_port_mask = 0xf,
f3645652 3125 .pvt = true,
b3e05aa1 3126 .multi_chip = true,
443d5a1b 3127 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3128 .ops = &mv88e6085_ops,
f81ec90f
VD		 3129 },
3130
3131 [MV88E6095] = {
107fcc10 3132 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 3133 .family = MV88E6XXX_FAMILY_6095,
3134 .name = "Marvell 88E6095/88E6095F",
3135 .num_databases = 256,
3136 .num_ports = 11,
3cf3c846 3137 .max_vid = 4095,
9dddd478 3138 .port_base_addr = 0x10,
a935c052 3139 .global1_addr = 0x1b,
9069c13a 3140 .global2_addr = 0x1c,
acddbd21 3141 .age_time_coeff = 15000,
dc30c35b 3142 .g1_irqs = 8,
e606ca36 3143 .atu_move_port_mask = 0xf,
b3e05aa1 3144 .multi_chip = true,
443d5a1b 3145 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3146 .ops = &mv88e6095_ops,
f81ec90f
VD		 3147 },
3148
7d381a02 3149 [MV88E6097] = {
107fcc10 3150 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 3151 .family = MV88E6XXX_FAMILY_6097,
3152 .name = "Marvell 88E6097/88E6097F",
3153 .num_databases = 4096,
3154 .num_ports = 11,
3cf3c846 3155 .max_vid = 4095,
7d381a02
SE		 3156 .port_base_addr = 0x10,
3157 .global1_addr = 0x1b,
9069c13a 3158 .global2_addr = 0x1c,
7d381a02 3159 .age_time_coeff = 15000,
c534178b 3160 .g1_irqs = 8,
d6c5e6af 3161 .g2_irqs = 10,
e606ca36 3162 .atu_move_port_mask = 0xf,
f3645652 3163 .pvt = true,
b3e05aa1 3164 .multi_chip = true,
2bfcfcd3 3165 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3166 .ops = &mv88e6097_ops,
3167 },
3168
f81ec90f 3169 [MV88E6123] = {
107fcc10 3170 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 3171 .family = MV88E6XXX_FAMILY_6165,
3172 .name = "Marvell 88E6123",
3173 .num_databases = 4096,
3174 .num_ports = 3,
3cf3c846 3175 .max_vid = 4095,
9dddd478 3176 .port_base_addr = 0x10,
a935c052 3177 .global1_addr = 0x1b,
9069c13a 3178 .global2_addr = 0x1c,
acddbd21 3179 .age_time_coeff = 15000,
dc30c35b 3180 .g1_irqs = 9,
d6c5e6af 3181 .g2_irqs = 10,
e606ca36 3182 .atu_move_port_mask = 0xf,
f3645652 3183 .pvt = true,
b3e05aa1 3184 .multi_chip = true,
5ebe31d7 3185 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3186 .ops = &mv88e6123_ops,
f81ec90f
VD		 3187 },
3188
3189 [MV88E6131] = {
107fcc10 3190 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 3191 .family = MV88E6XXX_FAMILY_6185,
3192 .name = "Marvell 88E6131",
3193 .num_databases = 256,
3194 .num_ports = 8,
3cf3c846 3195 .max_vid = 4095,
9dddd478 3196 .port_base_addr = 0x10,
a935c052 3197 .global1_addr = 0x1b,
9069c13a 3198 .global2_addr = 0x1c,
acddbd21 3199 .age_time_coeff = 15000,
dc30c35b 3200 .g1_irqs = 9,
e606ca36 3201 .atu_move_port_mask = 0xf,
b3e05aa1 3202 .multi_chip = true,
443d5a1b 3203 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3204 .ops = &mv88e6131_ops,
f81ec90f
VD		 3205 },
3206
990e27b0 3207 [MV88E6141] = {
107fcc10 3208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0
VD		 3209 .family = MV88E6XXX_FAMILY_6341,
3210 .name = "Marvell 88E6341",
3211 .num_databases = 4096,
3212 .num_ports = 6,
3cf3c846 3213 .max_vid = 4095,
990e27b0
VD		 3214 .port_base_addr = 0x10,
3215 .global1_addr = 0x1b,
9069c13a 3216 .global2_addr = 0x1c,
990e27b0
VD		 3217 .age_time_coeff = 3750,
3218 .atu_move_port_mask = 0x1f,
d6c5e6af 3219 .g2_irqs = 10,
f3645652 3220 .pvt = true,
b3e05aa1 3221 .multi_chip = true,
990e27b0 3222 .tag_protocol = DSA_TAG_PROTO_EDSA,
990e27b0
VD		 3223 .ops = &mv88e6141_ops,
3224 },
3225
f81ec90f 3226 [MV88E6161] = {
107fcc10 3227 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 3228 .family = MV88E6XXX_FAMILY_6165,
3229 .name = "Marvell 88E6161",
3230 .num_databases = 4096,
3231 .num_ports = 6,
3cf3c846 3232 .max_vid = 4095,
9dddd478 3233 .port_base_addr = 0x10,
a935c052 3234 .global1_addr = 0x1b,
9069c13a 3235 .global2_addr = 0x1c,
acddbd21 3236 .age_time_coeff = 15000,
dc30c35b 3237 .g1_irqs = 9,
d6c5e6af 3238 .g2_irqs = 10,
e606ca36 3239 .atu_move_port_mask = 0xf,
f3645652 3240 .pvt = true,
b3e05aa1 3241 .multi_chip = true,
5ebe31d7 3242 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3243 .ops = &mv88e6161_ops,
f81ec90f
VD		 3244 },
3245
3246 [MV88E6165] = {
107fcc10 3247 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 3248 .family = MV88E6XXX_FAMILY_6165,
3249 .name = "Marvell 88E6165",
3250 .num_databases = 4096,
3251 .num_ports = 6,
3cf3c846 3252 .max_vid = 4095,
9dddd478 3253 .port_base_addr = 0x10,
a935c052 3254 .global1_addr = 0x1b,
9069c13a 3255 .global2_addr = 0x1c,
acddbd21 3256 .age_time_coeff = 15000,
dc30c35b 3257 .g1_irqs = 9,
d6c5e6af 3258 .g2_irqs = 10,
e606ca36 3259 .atu_move_port_mask = 0xf,
f3645652 3260 .pvt = true,
b3e05aa1 3261 .multi_chip = true,
443d5a1b 3262 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3263 .ops = &mv88e6165_ops,
f81ec90f
VD		 3264 },
3265
3266 [MV88E6171] = {
107fcc10 3267 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 3268 .family = MV88E6XXX_FAMILY_6351,
3269 .name = "Marvell 88E6171",
3270 .num_databases = 4096,
3271 .num_ports = 7,
3cf3c846 3272 .max_vid = 4095,
9dddd478 3273 .port_base_addr = 0x10,
a935c052 3274 .global1_addr = 0x1b,
9069c13a 3275 .global2_addr = 0x1c,
acddbd21 3276 .age_time_coeff = 15000,
dc30c35b 3277 .g1_irqs = 9,
d6c5e6af 3278 .g2_irqs = 10,
e606ca36 3279 .atu_move_port_mask = 0xf,
f3645652 3280 .pvt = true,
b3e05aa1 3281 .multi_chip = true,
443d5a1b 3282 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3283 .ops = &mv88e6171_ops,
f81ec90f
VD		 3284 },
3285
3286 [MV88E6172] = {
107fcc10 3287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 3288 .family = MV88E6XXX_FAMILY_6352,
3289 .name = "Marvell 88E6172",
3290 .num_databases = 4096,
3291 .num_ports = 7,
3cf3c846 3292 .max_vid = 4095,
9dddd478 3293 .port_base_addr = 0x10,
a935c052 3294 .global1_addr = 0x1b,
9069c13a 3295 .global2_addr = 0x1c,
acddbd21 3296 .age_time_coeff = 15000,
dc30c35b 3297 .g1_irqs = 9,
d6c5e6af 3298 .g2_irqs = 10,
e606ca36 3299 .atu_move_port_mask = 0xf,
f3645652 3300 .pvt = true,
b3e05aa1 3301 .multi_chip = true,
443d5a1b 3302 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3303 .ops = &mv88e6172_ops,
f81ec90f
VD		 3304 },
3305
3306 [MV88E6175] = {
107fcc10 3307 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 3308 .family = MV88E6XXX_FAMILY_6351,
3309 .name = "Marvell 88E6175",
3310 .num_databases = 4096,
3311 .num_ports = 7,
3cf3c846 3312 .max_vid = 4095,
9dddd478 3313 .port_base_addr = 0x10,
a935c052 3314 .global1_addr = 0x1b,
9069c13a 3315 .global2_addr = 0x1c,
acddbd21 3316 .age_time_coeff = 15000,
dc30c35b 3317 .g1_irqs = 9,
d6c5e6af 3318 .g2_irqs = 10,
e606ca36 3319 .atu_move_port_mask = 0xf,
f3645652 3320 .pvt = true,
b3e05aa1 3321 .multi_chip = true,
443d5a1b 3322 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3323 .ops = &mv88e6175_ops,
f81ec90f
VD		 3324 },
3325
3326 [MV88E6176] = {
107fcc10 3327 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 3328 .family = MV88E6XXX_FAMILY_6352,
3329 .name = "Marvell 88E6176",
3330 .num_databases = 4096,
3331 .num_ports = 7,
3cf3c846 3332 .max_vid = 4095,
9dddd478 3333 .port_base_addr = 0x10,
a935c052 3334 .global1_addr = 0x1b,
9069c13a 3335 .global2_addr = 0x1c,
acddbd21 3336 .age_time_coeff = 15000,
dc30c35b 3337 .g1_irqs = 9,
d6c5e6af 3338 .g2_irqs = 10,
e606ca36 3339 .atu_move_port_mask = 0xf,
f3645652 3340 .pvt = true,
b3e05aa1 3341 .multi_chip = true,
443d5a1b 3342 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3343 .ops = &mv88e6176_ops,
f81ec90f
VD		 3344 },
3345
3346 [MV88E6185] = {
107fcc10 3347 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 3348 .family = MV88E6XXX_FAMILY_6185,
3349 .name = "Marvell 88E6185",
3350 .num_databases = 256,
3351 .num_ports = 10,
3cf3c846 3352 .max_vid = 4095,
9dddd478 3353 .port_base_addr = 0x10,
a935c052 3354 .global1_addr = 0x1b,
9069c13a 3355 .global2_addr = 0x1c,
acddbd21 3356 .age_time_coeff = 15000,
dc30c35b 3357 .g1_irqs = 8,
e606ca36 3358 .atu_move_port_mask = 0xf,
b3e05aa1 3359 .multi_chip = true,
443d5a1b 3360 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3361 .ops = &mv88e6185_ops,
f81ec90f
VD		 3362 },
3363
1a3b39ec 3364 [MV88E6190] = {
107fcc10 3365 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 3366 .family = MV88E6XXX_FAMILY_6390,
3367 .name = "Marvell 88E6190",
3368 .num_databases = 4096,
3369 .num_ports = 11, /* 10 + Z80 */
931d1822 3370 .max_vid = 8191,
1a3b39ec
AL		 3371 .port_base_addr = 0x0,
3372 .global1_addr = 0x1b,
9069c13a 3373 .global2_addr = 0x1c,
443d5a1b 3374 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3375 .age_time_coeff = 3750,
1a3b39ec 3376 .g1_irqs = 9,
d6c5e6af 3377 .g2_irqs = 14,
f3645652 3378 .pvt = true,
b3e05aa1 3379 .multi_chip = true,
e606ca36 3380 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3381 .ops = &mv88e6190_ops,
3382 },
3383
3384 [MV88E6190X] = {
107fcc10 3385 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 3386 .family = MV88E6XXX_FAMILY_6390,
3387 .name = "Marvell 88E6190X",
3388 .num_databases = 4096,
3389 .num_ports = 11, /* 10 + Z80 */
931d1822 3390 .max_vid = 8191,
1a3b39ec
AL		 3391 .port_base_addr = 0x0,
3392 .global1_addr = 0x1b,
9069c13a 3393 .global2_addr = 0x1c,
b91e055c 3394 .age_time_coeff = 3750,
1a3b39ec 3395 .g1_irqs = 9,
d6c5e6af 3396 .g2_irqs = 14,
e606ca36 3397 .atu_move_port_mask = 0x1f,
f3645652 3398 .pvt = true,
b3e05aa1 3399 .multi_chip = true,
443d5a1b 3400 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3401 .ops = &mv88e6190x_ops,
3402 },
3403
3404 [MV88E6191] = {
107fcc10 3405 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 3406 .family = MV88E6XXX_FAMILY_6390,
3407 .name = "Marvell 88E6191",
3408 .num_databases = 4096,
3409 .num_ports = 11, /* 10 + Z80 */
931d1822 3410 .max_vid = 8191,
1a3b39ec
AL		 3411 .port_base_addr = 0x0,
3412 .global1_addr = 0x1b,
9069c13a 3413 .global2_addr = 0x1c,
b91e055c 3414 .age_time_coeff = 3750,
443d5a1b 3415 .g1_irqs = 9,
d6c5e6af 3416 .g2_irqs = 14,
e606ca36 3417 .atu_move_port_mask = 0x1f,
f3645652 3418 .pvt = true,
b3e05aa1 3419 .multi_chip = true,
443d5a1b 3420 .tag_protocol = DSA_TAG_PROTO_DSA,
2cf4cefb 3421 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3422 },
3423
f81ec90f 3424 [MV88E6240] = {
107fcc10 3425 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 3426 .family = MV88E6XXX_FAMILY_6352,
3427 .name = "Marvell 88E6240",
3428 .num_databases = 4096,
3429 .num_ports = 7,
3cf3c846 3430 .max_vid = 4095,
9dddd478 3431 .port_base_addr = 0x10,
a935c052 3432 .global1_addr = 0x1b,
9069c13a 3433 .global2_addr = 0x1c,
acddbd21 3434 .age_time_coeff = 15000,
dc30c35b 3435 .g1_irqs = 9,
d6c5e6af 3436 .g2_irqs = 10,
e606ca36 3437 .atu_move_port_mask = 0xf,
f3645652 3438 .pvt = true,
b3e05aa1 3439 .multi_chip = true,
443d5a1b 3440 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3441 .ops = &mv88e6240_ops,
f81ec90f
VD		 3442 },
3443
1a3b39ec 3444 [MV88E6290] = {
107fcc10 3445 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 3446 .family = MV88E6XXX_FAMILY_6390,
3447 .name = "Marvell 88E6290",
3448 .num_databases = 4096,
3449 .num_ports = 11, /* 10 + Z80 */
931d1822 3450 .max_vid = 8191,
1a3b39ec
AL		 3451 .port_base_addr = 0x0,
3452 .global1_addr = 0x1b,
9069c13a 3453 .global2_addr = 0x1c,
b91e055c 3454 .age_time_coeff = 3750,
1a3b39ec 3455 .g1_irqs = 9,
d6c5e6af 3456 .g2_irqs = 14,
e606ca36 3457 .atu_move_port_mask = 0x1f,
f3645652 3458 .pvt = true,
b3e05aa1 3459 .multi_chip = true,
443d5a1b 3460 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3461 .ops = &mv88e6290_ops,
3462 },
3463
f81ec90f 3464 [MV88E6320] = {
107fcc10 3465 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 3466 .family = MV88E6XXX_FAMILY_6320,
3467 .name = "Marvell 88E6320",
3468 .num_databases = 4096,
3469 .num_ports = 7,
3cf3c846 3470 .max_vid = 4095,
9dddd478 3471 .port_base_addr = 0x10,
a935c052 3472 .global1_addr = 0x1b,
9069c13a 3473 .global2_addr = 0x1c,
acddbd21 3474 .age_time_coeff = 15000,
dc30c35b 3475 .g1_irqs = 8,
e606ca36 3476 .atu_move_port_mask = 0xf,
f3645652 3477 .pvt = true,
b3e05aa1 3478 .multi_chip = true,
443d5a1b 3479 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3480 .ops = &mv88e6320_ops,
f81ec90f
VD		 3481 },
3482
3483 [MV88E6321] = {
107fcc10 3484 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 3485 .family = MV88E6XXX_FAMILY_6320,
3486 .name = "Marvell 88E6321",
3487 .num_databases = 4096,
3488 .num_ports = 7,
3cf3c846 3489 .max_vid = 4095,
9dddd478 3490 .port_base_addr = 0x10,
a935c052 3491 .global1_addr = 0x1b,
9069c13a 3492 .global2_addr = 0x1c,
acddbd21 3493 .age_time_coeff = 15000,
dc30c35b 3494 .g1_irqs = 8,
e606ca36 3495 .atu_move_port_mask = 0xf,
b3e05aa1 3496 .multi_chip = true,
443d5a1b 3497 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3498 .ops = &mv88e6321_ops,
f81ec90f
VD		 3499 },
3500
a75961d0 3501 [MV88E6341] = {
107fcc10 3502 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 3503 .family = MV88E6XXX_FAMILY_6341,
3504 .name = "Marvell 88E6341",
3505 .num_databases = 4096,
3506 .num_ports = 6,
3cf3c846 3507 .max_vid = 4095,
a75961d0
GC		 3508 .port_base_addr = 0x10,
3509 .global1_addr = 0x1b,
9069c13a 3510 .global2_addr = 0x1c,
a75961d0 3511 .age_time_coeff = 3750,
e606ca36 3512 .atu_move_port_mask = 0x1f,
d6c5e6af 3513 .g2_irqs = 10,
f3645652 3514 .pvt = true,
b3e05aa1 3515 .multi_chip = true,
a75961d0 3516 .tag_protocol = DSA_TAG_PROTO_EDSA,
a75961d0
GC		 3517 .ops = &mv88e6341_ops,
3518 },
3519
f81ec90f 3520 [MV88E6350] = {
107fcc10 3521 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 3522 .family = MV88E6XXX_FAMILY_6351,
3523 .name = "Marvell 88E6350",
3524 .num_databases = 4096,
3525 .num_ports = 7,
3cf3c846 3526 .max_vid = 4095,
9dddd478 3527 .port_base_addr = 0x10,
a935c052 3528 .global1_addr = 0x1b,
9069c13a 3529 .global2_addr = 0x1c,
acddbd21 3530 .age_time_coeff = 15000,
dc30c35b 3531 .g1_irqs = 9,
d6c5e6af 3532 .g2_irqs = 10,
e606ca36 3533 .atu_move_port_mask = 0xf,
f3645652 3534 .pvt = true,
b3e05aa1 3535 .multi_chip = true,
443d5a1b 3536 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3537 .ops = &mv88e6350_ops,
f81ec90f
VD		 3538 },
3539
3540 [MV88E6351] = {
107fcc10 3541 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 3542 .family = MV88E6XXX_FAMILY_6351,
3543 .name = "Marvell 88E6351",
3544 .num_databases = 4096,
3545 .num_ports = 7,
3cf3c846 3546 .max_vid = 4095,
9dddd478 3547 .port_base_addr = 0x10,
a935c052 3548 .global1_addr = 0x1b,
9069c13a 3549 .global2_addr = 0x1c,
acddbd21 3550 .age_time_coeff = 15000,
dc30c35b 3551 .g1_irqs = 9,
d6c5e6af 3552 .g2_irqs = 10,
e606ca36 3553 .atu_move_port_mask = 0xf,
f3645652 3554 .pvt = true,
b3e05aa1 3555 .multi_chip = true,
443d5a1b 3556 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3557 .ops = &mv88e6351_ops,
f81ec90f
VD		 3558 },
3559
3560 [MV88E6352] = {
107fcc10 3561 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 3562 .family = MV88E6XXX_FAMILY_6352,
3563 .name = "Marvell 88E6352",
3564 .num_databases = 4096,
3565 .num_ports = 7,
3cf3c846 3566 .max_vid = 4095,
9dddd478 3567 .port_base_addr = 0x10,
a935c052 3568 .global1_addr = 0x1b,
9069c13a 3569 .global2_addr = 0x1c,
acddbd21 3570 .age_time_coeff = 15000,
dc30c35b 3571 .g1_irqs = 9,
d6c5e6af 3572 .g2_irqs = 10,
e606ca36 3573 .atu_move_port_mask = 0xf,
f3645652 3574 .pvt = true,
b3e05aa1 3575 .multi_chip = true,
443d5a1b 3576 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3577 .ops = &mv88e6352_ops,
f81ec90f 3578 },
1a3b39ec 3579 [MV88E6390] = {
107fcc10 3580 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 3581 .family = MV88E6XXX_FAMILY_6390,
3582 .name = "Marvell 88E6390",
3583 .num_databases = 4096,
3584 .num_ports = 11, /* 10 + Z80 */
931d1822 3585 .max_vid = 8191,
1a3b39ec
AL		 3586 .port_base_addr = 0x0,
3587 .global1_addr = 0x1b,
9069c13a 3588 .global2_addr = 0x1c,
b91e055c 3589 .age_time_coeff = 3750,
1a3b39ec 3590 .g1_irqs = 9,
d6c5e6af 3591 .g2_irqs = 14,
e606ca36 3592 .atu_move_port_mask = 0x1f,
f3645652 3593 .pvt = true,
b3e05aa1 3594 .multi_chip = true,
443d5a1b 3595 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3596 .ops = &mv88e6390_ops,
3597 },
3598 [MV88E6390X] = {
107fcc10 3599 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 3600 .family = MV88E6XXX_FAMILY_6390,
3601 .name = "Marvell 88E6390X",
3602 .num_databases = 4096,
3603 .num_ports = 11, /* 10 + Z80 */
931d1822 3604 .max_vid = 8191,
1a3b39ec
AL		 3605 .port_base_addr = 0x0,
3606 .global1_addr = 0x1b,
9069c13a 3607 .global2_addr = 0x1c,
b91e055c 3608 .age_time_coeff = 3750,
1a3b39ec 3609 .g1_irqs = 9,
d6c5e6af 3610 .g2_irqs = 14,
e606ca36 3611 .atu_move_port_mask = 0x1f,
f3645652 3612 .pvt = true,
b3e05aa1 3613 .multi_chip = true,
443d5a1b 3614 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3615 .ops = &mv88e6390x_ops,
3616 },
f81ec90f
VD		 3617};
3618
5f7c0367 3619static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3620{
a439c061 3621 int i;
b9b37713 3622
5f7c0367
VD		 3623 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3624 if (mv88e6xxx_table[i].prod_num == prod_num)
3625 return &mv88e6xxx_table[i];
b9b37713 3626
b9b37713
VD		 3627 return NULL;
3628}
3629
fad09c73 3630static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3631{
3632 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3633 unsigned int prod_num, rev;
3634 u16 id;
3635 int err;
bc46a3d5 3636
8f6345b2 3637 mutex_lock(&chip->reg_lock);
107fcc10 3638 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
8f6345b2
VD		 3639 mutex_unlock(&chip->reg_lock);
3640 if (err)
3641 return err;
bc46a3d5 3642
107fcc10
VD		 3643 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3644 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 3645
3646 info = mv88e6xxx_lookup_info(prod_num);
3647 if (!info)
3648 return -ENODEV;
3649
caac8545 3650 /* Update the compatible info with the probed one */
fad09c73 3651 chip->info = info;
bc46a3d5 3652
ca070c10
VD		 3653 err = mv88e6xxx_g2_require(chip);
3654 if (err)
3655 return err;
3656
fad09c73
VD		 3657 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3658 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3659
3660 return 0;
3661}
3662
fad09c73 3663static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3664{
fad09c73 3665 struct mv88e6xxx_chip *chip;
469d729f 3666
fad09c73
VD		 3667 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3668 if (!chip)
469d729f
VD		 3669 return NULL;
3670
fad09c73 3671 chip->dev = dev;
469d729f 3672
fad09c73 3673 mutex_init(&chip->reg_lock);
a3c53be5 3674 INIT_LIST_HEAD(&chip->mdios);
469d729f 3675
fad09c73 3676 return chip;
469d729f
VD		 3677}
3678
fad09c73 3679static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3680 struct mii_bus *bus, int sw_addr)
3681{
914b32f6 3682 if (sw_addr == 0)
fad09c73 3683 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
b3e05aa1 3684 else if (chip->info->multi_chip)
fad09c73 3685 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3686 else
3687 return -EINVAL;
3688
fad09c73
VD		 3689 chip->bus = bus;
3690 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3691
3692 return 0;
3693}
3694
7b314362
AL		 3695static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3696{
04bed143 3697 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 3698
443d5a1b 3699 return chip->info->tag_protocol;
7b314362
AL		 3700}
3701
fcdce7d0
AL		 3702static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3703 struct device *host_dev, int sw_addr,
3704 void **priv)
a77d43f1 3705{
fad09c73 3706 struct mv88e6xxx_chip *chip;
a439c061 3707 struct mii_bus *bus;
b516d453 3708 int err;
a77d43f1 3709
a439c061 3710 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3711 if (!bus)
3712 return NULL;
3713
fad09c73
VD		 3714 chip = mv88e6xxx_alloc_chip(dsa_dev);
3715 if (!chip)
469d729f
VD		 3716 return NULL;
3717
caac8545 3718 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3719 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3720
fad09c73 3721 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3722 if (err)
3723 goto free;
3724
fad09c73 3725 err = mv88e6xxx_detect(chip);
bc46a3d5 3726 if (err)
469d729f 3727 goto free;
a439c061 3728
dc30c35b
AL		 3729 mutex_lock(&chip->reg_lock);
3730 err = mv88e6xxx_switch_reset(chip);
3731 mutex_unlock(&chip->reg_lock);
3732 if (err)
3733 goto free;
3734
e57e5e77
VD		 3735 mv88e6xxx_phy_init(chip);
3736
a3c53be5 3737 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 3738 if (err)
469d729f 3739 goto free;
b516d453 3740
fad09c73 3741 *priv = chip;
a439c061 3742
fad09c73 3743 return chip->info->name;
469d729f 3744free:
fad09c73 3745 devm_kfree(dsa_dev, chip);
469d729f
VD		 3746
3747 return NULL;
a77d43f1
AL		 3748}
3749
7df8fbdd
VD		 3750static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3751 const struct switchdev_obj_port_mdb *mdb,
3752 struct switchdev_trans *trans)
3753{
3754 /* We don't need any dynamic resource from the kernel (yet),
3755 * so skip the prepare phase.
3756 */
3757
3758 return 0;
3759}
3760
3761static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3762 const struct switchdev_obj_port_mdb *mdb,
3763 struct switchdev_trans *trans)
3764{
04bed143 3765 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3766
3767 mutex_lock(&chip->reg_lock);
3768 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3769 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
774439e5
VD		 3770 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3771 port);
7df8fbdd
VD		 3772 mutex_unlock(&chip->reg_lock);
3773}
3774
3775static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3776 const struct switchdev_obj_port_mdb *mdb)
3777{
04bed143 3778 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3779 int err;
3780
3781 mutex_lock(&chip->reg_lock);
3782 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3783 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
7df8fbdd
VD		 3784 mutex_unlock(&chip->reg_lock);
3785
3786 return err;
3787}
3788
a82f67af 3789static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3790 .probe = mv88e6xxx_drv_probe,
7b314362 3791 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f 3792 .setup = mv88e6xxx_setup,
f81ec90f
VD		 3793 .adjust_link = mv88e6xxx_adjust_link,
3794 .get_strings = mv88e6xxx_get_strings,
3795 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3796 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 3797 .port_enable = mv88e6xxx_port_enable,
3798 .port_disable = mv88e6xxx_port_disable,
08f50061
VD		 3799 .get_mac_eee = mv88e6xxx_get_mac_eee,
3800 .set_mac_eee = mv88e6xxx_set_mac_eee,
f8cd8753 3801 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3802 .get_eeprom = mv88e6xxx_get_eeprom,
3803 .set_eeprom = mv88e6xxx_set_eeprom,
3804 .get_regs_len = mv88e6xxx_get_regs_len,
3805 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3806 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3807 .port_bridge_join = mv88e6xxx_port_bridge_join,
3808 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3809 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3810 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3811 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3812 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3813 .port_vlan_add = mv88e6xxx_port_vlan_add,
3814 .port_vlan_del = mv88e6xxx_port_vlan_del,
f81ec90f
VD		 3815 .port_fdb_add = mv88e6xxx_port_fdb_add,
3816 .port_fdb_del = mv88e6xxx_port_fdb_del,
3817 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3818 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3819 .port_mdb_add = mv88e6xxx_port_mdb_add,
3820 .port_mdb_del = mv88e6xxx_port_mdb_del,
aec5ac88
VD		 3821 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3822 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 3823};
3824
ab3d408d
FF		 3825static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3826 .ops = &mv88e6xxx_switch_ops,
3827};
3828
55ed0ce0 3829static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3830{
fad09c73 3831 struct device *dev = chip->dev;
b7e66a5f
VD		 3832 struct dsa_switch *ds;
3833
73b1204d 3834 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 3835 if (!ds)
3836 return -ENOMEM;
3837
fad09c73 3838 ds->priv = chip;
9d490b4e 3839 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 3840 ds->ageing_time_min = chip->info->age_time_coeff;
3841 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 3842
3843 dev_set_drvdata(dev, ds);
3844
23c9ee49 3845 return dsa_register_switch(ds);
b7e66a5f
VD		 3846}
3847
fad09c73 3848static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3849{
fad09c73 3850 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3851}
3852
57d32310 3853static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3854{
14c7b3c3 3855 struct device *dev = &mdiodev->dev;
f8cd8753 3856 struct device_node *np = dev->of_node;
caac8545 3857 const struct mv88e6xxx_info *compat_info;
fad09c73 3858 struct mv88e6xxx_chip *chip;
f8cd8753 3859 u32 eeprom_len;
52638f71 3860 int err;
14c7b3c3 3861
caac8545
VD		 3862 compat_info = of_device_get_match_data(dev);
3863 if (!compat_info)
3864 return -EINVAL;
3865
fad09c73
VD		 3866 chip = mv88e6xxx_alloc_chip(dev);
3867 if (!chip)
14c7b3c3
AL		 3868 return -ENOMEM;
3869
fad09c73 3870 chip->info = compat_info;
caac8545 3871
fad09c73 3872 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3873 if (err)
3874 return err;
14c7b3c3 3875
b4308f04
AL		 3876 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
3877 if (IS_ERR(chip->reset))
3878 return PTR_ERR(chip->reset);
3879
fad09c73 3880 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3881 if (err)
3882 return err;
14c7b3c3 3883
e57e5e77
VD		 3884 mv88e6xxx_phy_init(chip);
3885
ee4dc2e7 3886 if (chip->info->ops->get_eeprom &&
f8cd8753 3887 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3888 chip->eeprom_len = eeprom_len;
f8cd8753 3889
dc30c35b
AL		 3890 mutex_lock(&chip->reg_lock);
3891 err = mv88e6xxx_switch_reset(chip);
3892 mutex_unlock(&chip->reg_lock);
3893 if (err)
3894 goto out;
3895
3896 chip->irq = of_irq_get(np, 0);
3897 if (chip->irq == -EPROBE_DEFER) {
3898 err = chip->irq;
3899 goto out;
3900 }
3901
3902 if (chip->irq > 0) {
3903 /* Has to be performed before the MDIO bus is created,
3904 * because the PHYs will link there interrupts to these
3905 * interrupt controllers
3906 */
3907 mutex_lock(&chip->reg_lock);
3908 err = mv88e6xxx_g1_irq_setup(chip);
3909 mutex_unlock(&chip->reg_lock);
3910
3911 if (err)
3912 goto out;
3913
d6c5e6af 3914 if (chip->info->g2_irqs > 0) {
dc30c35b
AL		 3915 err = mv88e6xxx_g2_irq_setup(chip);
3916 if (err)
3917 goto out_g1_irq;
3918 }
3919 }
3920
a3c53be5 3921 err = mv88e6xxx_mdios_register(chip, np);
b516d453 3922 if (err)
dc30c35b 3923 goto out_g2_irq;
b516d453 3924
55ed0ce0 3925 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 3926 if (err)
3927 goto out_mdio;
83c0afae 3928
98e67308 3929 return 0;
dc30c35b
AL		 3930
3931out_mdio:
a3c53be5 3932 mv88e6xxx_mdios_unregister(chip);
dc30c35b 3933out_g2_irq:
d6c5e6af 3934 if (chip->info->g2_irqs > 0 && chip->irq > 0)
dc30c35b
AL		 3935 mv88e6xxx_g2_irq_free(chip);
3936out_g1_irq:
61f7c3f8
AL		 3937 if (chip->irq > 0) {
3938 mutex_lock(&chip->reg_lock);
46712644 3939 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 3940 mutex_unlock(&chip->reg_lock);
3941 }
dc30c35b
AL		 3942out:
3943 return err;
98e67308 3944}
14c7b3c3
AL		 3945
3946static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3947{
3948 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 3949 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 3950
930188ce 3951 mv88e6xxx_phy_destroy(chip);
fad09c73 3952 mv88e6xxx_unregister_switch(chip);
a3c53be5 3953 mv88e6xxx_mdios_unregister(chip);
dc30c35b 3954
46712644 3955 if (chip->irq > 0) {
d6c5e6af 3956 if (chip->info->g2_irqs > 0)
46712644 3957 mv88e6xxx_g2_irq_free(chip);
b32ca44a 3958 mutex_lock(&chip->reg_lock);
46712644 3959 mv88e6xxx_g1_irq_free(chip);
b32ca44a 3960 mutex_unlock(&chip->reg_lock);
46712644 3961 }
14c7b3c3
AL		 3962}
3963
3964static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 3965 {
3966 .compatible = "marvell,mv88e6085",
3967 .data = &mv88e6xxx_table[MV88E6085],
3968 },
1a3b39ec
AL		 3969 {
3970 .compatible = "marvell,mv88e6190",
3971 .data = &mv88e6xxx_table[MV88E6190],
3972 },
14c7b3c3
AL		 3973 { /* sentinel */ },
3974};
3975
3976MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3977
3978static struct mdio_driver mv88e6xxx_driver = {
3979 .probe = mv88e6xxx_probe,
3980 .remove = mv88e6xxx_remove,
3981 .mdiodrv.driver = {
3982 .name = "mv88e6085",
3983 .of_match_table = mv88e6xxx_of_match,
3984 },
3985};
3986
3987static int __init mv88e6xxx_init(void)
3988{
ab3d408d 3989 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 3990 return mdio_driver_register(&mv88e6xxx_driver);
3991}
98e67308
BH		 3992module_init(mv88e6xxx_init);
3993
3994static void __exit mv88e6xxx_cleanup(void)
3995{
14c7b3c3 3996 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 3997 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 3998}
3999module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4000
4001MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4002MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4003MODULE_LICENSE("GPL");
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