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net: dsa: mv88e6xxx: prefix Port Default VLAN macros
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
ec561276 35
4d5f2ba7 36#include "chip.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
6d91782f 41#include "serdes.h"
91da11f8 42
fad09c73 43static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 44{
fad09c73
VD		 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 47 dump_stack();
48 }
49}
50
914b32f6
VD		 51/* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 *
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 *
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 61 */
914b32f6 62
fad09c73 63static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 *val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 val)
74{
fad09c73 75 if (!chip->smi_ops)
914b32f6
VD		 76 return -EOPNOTSUPP;
77
fad09c73 78 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 79}
80
fad09c73 81static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 82 int addr, int reg, u16 *val)
83{
84 int ret;
85
fad09c73 86 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 87 if (ret < 0)
88 return ret;
89
90 *val = ret & 0xffff;
91
92 return 0;
93}
94
fad09c73 95static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 96 int addr, int reg, u16 val)
97{
98 int ret;
99
fad09c73 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 101 if (ret < 0)
102 return ret;
103
104 return 0;
105}
106
c08026ab 107static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
110};
111
fad09c73 112static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 113{
114 int ret;
115 int i;
116
117 for (i = 0; i < 16; i++) {
fad09c73 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 119 if (ret < 0)
120 return ret;
121
cca8b133 122 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 123 return 0;
124 }
125
126 return -ETIMEDOUT;
127}
128
fad09c73 129static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 130 int addr, int reg, u16 *val)
91da11f8
LB		 131{
132 int ret;
133
3675c8d7 134 /* Wait for the bus to become free. */
fad09c73 135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the read command. */
fad09c73 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the read command to complete. */
fad09c73 146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 147 if (ret < 0)
148 return ret;
149
3675c8d7 150 /* Read the data. */
fad09c73 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 152 if (ret < 0)
153 return ret;
154
914b32f6 155 *val = ret & 0xffff;
91da11f8 156
914b32f6 157 return 0;
8d6d09e7
GR		 158}
159
fad09c73 160static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 161 int addr, int reg, u16 val)
91da11f8
LB		 162{
163 int ret;
164
3675c8d7 165 /* Wait for the bus to become free. */
fad09c73 166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 167 if (ret < 0)
168 return ret;
169
3675c8d7 170 /* Transmit the data to write. */
fad09c73 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Transmit the write command. */
fad09c73 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 178 if (ret < 0)
179 return ret;
180
3675c8d7 181 /* Wait for the write command to complete. */
fad09c73 182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 183 if (ret < 0)
184 return ret;
185
186 return 0;
187}
188
c08026ab 189static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
192};
193
ec561276 194int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 195{
196 int err;
197
fad09c73 198 assert_reg_lock(chip);
914b32f6 199
fad09c73 200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 201 if (err)
202 return err;
203
fad09c73 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 205 addr, reg, *val);
206
207 return 0;
208}
209
ec561276 210int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 211{
914b32f6
VD		 212 int err;
213
fad09c73 214 assert_reg_lock(chip);
91da11f8 215
fad09c73 216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 217 if (err)
218 return err;
219
fad09c73 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 221 addr, reg, val);
222
914b32f6
VD		 223 return 0;
224}
225
10fa5bfc 226struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 227{
228 struct mv88e6xxx_mdio_bus *mdio_bus;
229
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
231 list);
232 if (!mdio_bus)
233 return NULL;
234
235 return mdio_bus->bus;
236}
237
dc30c35b
AL		 238static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
239{
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
242
243 chip->g1_irq.masked |= (1 << n);
244}
245
246static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
247{
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
250
251 chip->g1_irq.masked &= ~(1 << n);
252}
253
254static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
255{
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
259 unsigned int n;
260 u16 reg;
261 int err;
262
263 mutex_lock(&chip->reg_lock);
264 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
265 mutex_unlock(&chip->reg_lock);
266
267 if (err)
268 goto out;
269
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
274 ++nhandled;
275 }
276 }
277out:
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
279}
280
281static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
282{
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
284
285 mutex_lock(&chip->reg_lock);
286}
287
288static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
289{
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
292 u16 reg;
293 int err;
294
295 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
296 if (err)
297 goto out;
298
299 reg &= ~mask;
300 reg |= (~chip->g1_irq.masked & mask);
301
302 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
303 if (err)
304 goto out;
305
306out:
307 mutex_unlock(&chip->reg_lock);
308}
309
310static struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
316};
317
318static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
319 unsigned int irq,
320 irq_hw_number_t hwirq)
321{
322 struct mv88e6xxx_chip *chip = d->host_data;
323
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
327
328 return 0;
329}
330
331static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
334};
335
336static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
337{
338 int irq, virq;
3460a577
AL		 339 u16 mask;
340
341 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
343 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
344
345 free_irq(chip->irq, chip);
dc30c35b 346
5edef2f2 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 349 irq_dispose_mapping(virq);
350 }
351
a3db3d3a 352 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 353}
354
355static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
356{
3dd0ef05
AL		 357 int err, irq, virq;
358 u16 reg, mask;
dc30c35b
AL		 359
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
365 return -ENOMEM;
366
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
369
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
372
3dd0ef05 373 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 374 if (err)
3dd0ef05 375 goto out_mapping;
dc30c35b 376
3dd0ef05 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 378
3dd0ef05 379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 380 if (err)
3dd0ef05 381 goto out_disable;
dc30c35b
AL		 382
383 /* Reading the interrupt status clears (most of) them */
384 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
385 if (err)
3dd0ef05 386 goto out_disable;
dc30c35b
AL		 387
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
392 if (err)
3dd0ef05 393 goto out_disable;
dc30c35b
AL		 394
395 return 0;
396
3dd0ef05
AL		 397out_disable:
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
399 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
400
401out_mapping:
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
405 }
406
407 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 408
409 return err;
410}
411
ec561276 412int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 413{
6441e669 414 int i;
2d79af6e 415
6441e669 416 for (i = 0; i < 16; i++) {
2d79af6e
VD		 417 u16 val;
418 int err;
419
420 err = mv88e6xxx_read(chip, addr, reg, &val);
421 if (err)
422 return err;
423
424 if (!(val & mask))
425 return 0;
426
427 usleep_range(1000, 2000);
428 }
429
30853553 430 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 431 return -ETIMEDOUT;
432}
433
f22ab641 434/* Indirect write to single pointer-data register with an Update bit */
ec561276 435int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 436{
437 u16 val;
0f02b4f7 438 int err;
f22ab641
VD		 439
440 /* Wait until the previous operation is completed */
0f02b4f7
AL		 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
442 if (err)
443 return err;
f22ab641
VD		 444
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
447
448 return mv88e6xxx_write(chip, addr, reg, val);
449}
450
d78343d2
VD		 451static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
454{
455 int err;
456
457 if (!chip->info->ops->port_set_link)
458 return 0;
459
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
462 if (err)
463 return err;
464
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
468 goto restore_link;
469 }
470
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
474 goto restore_link;
475 }
476
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
480 goto restore_link;
481 }
482
f39908d3
AL		 483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
486 goto restore_link;
487 }
488
d78343d2
VD		 489 err = 0;
490restore_link:
491 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 493
494 return err;
495}
496
dea87024
AL		 497/* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
500 */
f81ec90f
VD		 501static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
dea87024 503{
04bed143 504 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 505 int err;
dea87024
AL		 506
507 if (!phy_is_pseudo_fixed_link(phydev))
508 return;
509
fad09c73 510 mutex_lock(&chip->reg_lock);
d78343d2
VD		 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
fad09c73 513 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 514
515 if (err && err != -EOPNOTSUPP)
774439e5 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
dea87024
AL		 517}
518
a605a0fe 519static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 520{
a605a0fe
AL		 521 if (!chip->info->ops->stats_snapshot)
522 return -EOPNOTSUPP;
91da11f8 523
a605a0fe 524 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 525}
526
e413e7e1 527static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 587};
588
fad09c73 589static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 590 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 591 int port, u16 bank1_select,
592 u16 histogram)
80c4627b 593{
80c4627b
AL		 594 u32 low;
595 u32 high = 0;
dfafe449 596 u16 reg = 0;
0e7b9925 597 int err;
80c4627b
AL		 598 u64 value;
599
f5e2ed02 600 switch (s->type) {
dfafe449 601 case STATS_TYPE_PORT:
0e7b9925
AL		 602 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
603 if (err)
80c4627b
AL		 604 return UINT64_MAX;
605
0e7b9925 606 low = reg;
80c4627b 607 if (s->sizeof_stat == 4) {
0e7b9925
AL		 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
609 if (err)
80c4627b 610 return UINT64_MAX;
0e7b9925 611 high = reg;
80c4627b 612 }
f5e2ed02 613 break;
dfafe449 614 case STATS_TYPE_BANK1:
e0d8b615 615 reg = bank1_select;
dfafe449
AL		 616 /* fall through */
617 case STATS_TYPE_BANK0:
e0d8b615 618 reg |= s->reg | histogram;
7f9ef3af 619 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 620 if (s->sizeof_stat == 8)
7f9ef3af 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 622 break;
623 default:
624 return UINT64_MAX;
80c4627b
AL		 625 }
626 value = (((u64)high) << 16) | low;
627 return value;
628}
629
dfafe449
AL		 630static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
91da11f8 632{
f5e2ed02
AL		 633 struct mv88e6xxx_hw_stat *stat;
634 int i, j;
91da11f8 635
f5e2ed02
AL		 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
dfafe449 638 if (stat->type & types) {
f5e2ed02
AL		 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
640 ETH_GSTRING_LEN);
641 j++;
642 }
91da11f8 643 }
e413e7e1
AL		 644}
645
dfafe449
AL		 646static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
647 uint8_t *data)
648{
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
651}
652
653static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
654 uint8_t *data)
655{
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
658}
659
660static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
661 uint8_t *data)
e413e7e1 662{
04bed143 663 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 664
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
667}
668
669static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
670 int types)
671{
f5e2ed02
AL		 672 struct mv88e6xxx_hw_stat *stat;
673 int i, j;
674
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
dfafe449 677 if (stat->type & types)
f5e2ed02
AL		 678 j++;
679 }
680 return j;
e413e7e1
AL		 681}
682
dfafe449
AL		 683static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
684{
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
686 STATS_TYPE_PORT);
687}
688
689static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
690{
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
692 STATS_TYPE_BANK1);
693}
694
695static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
696{
697 struct mv88e6xxx_chip *chip = ds->priv;
698
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
701
702 return 0;
703}
704
052f947f 705static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
052f947f
AL		 708{
709 struct mv88e6xxx_hw_stat *stat;
710 int i, j;
711
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
e0d8b615
AL		 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
716 bank1_select,
717 histogram);
052f947f
AL		 718 j++;
719 }
720 }
721}
722
723static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
724 uint64_t *data)
725{
726 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
728 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 729}
730
731static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
732 uint64_t *data)
733{
734 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
736 GLOBAL_STATS_OP_BANK_1_BIT_9,
737 GLOBAL_STATS_OP_HIST_RX_TX);
738}
739
740static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
741 uint64_t *data)
742{
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
745 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 746}
747
748static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
749 uint64_t *data)
750{
751 if (chip->info->ops->stats_get_stats)
752 chip->info->ops->stats_get_stats(chip, port, data);
753}
754
f81ec90f
VD		 755static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
756 uint64_t *data)
e413e7e1 757{
04bed143 758 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 759 int ret;
f5e2ed02 760
fad09c73 761 mutex_lock(&chip->reg_lock);
f5e2ed02 762
a605a0fe 763 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 764 if (ret < 0) {
fad09c73 765 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 766 return;
767 }
052f947f
AL		 768
769 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 770
fad09c73 771 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 772}
773
de227387
AL		 774static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
775{
776 if (chip->info->ops->stats_set_histogram)
777 return chip->info->ops->stats_set_histogram(chip);
778
779 return 0;
780}
781
f81ec90f 782static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 783{
784 return 32 * sizeof(u16);
785}
786
f81ec90f
VD		 787static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
788 struct ethtool_regs *regs, void *_p)
a1ab91f3 789{
04bed143 790 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 791 int err;
792 u16 reg;
a1ab91f3
GR		 793 u16 *p = _p;
794 int i;
795
796 regs->version = 0;
797
798 memset(p, 0xff, 32 * sizeof(u16));
799
fad09c73 800 mutex_lock(&chip->reg_lock);
23062513 801
a1ab91f3 802 for (i = 0; i < 32; i++) {
a1ab91f3 803
0e7b9925
AL		 804 err = mv88e6xxx_port_read(chip, port, i, &reg);
805 if (!err)
806 p[i] = reg;
a1ab91f3 807 }
23062513 808
fad09c73 809 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 810}
811
f81ec90f
VD		 812static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
813 struct ethtool_eee *e)
11b3b45d 814{
04bed143 815 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 816 u16 reg;
817 int err;
11b3b45d 818
fad09c73 819 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 820 return -EOPNOTSUPP;
821
fad09c73 822 mutex_lock(&chip->reg_lock);
2f40c698 823
9c93829c
VD		 824 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
825 if (err)
2f40c698 826 goto out;
11b3b45d
GR		 827
828 e->eee_enabled = !!(reg & 0x0200);
829 e->tx_lpi_enabled = !!(reg & 0x0100);
830
5f83dc93 831 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
9c93829c 832 if (err)
2f40c698 833 goto out;
11b3b45d 834
5f83dc93 835 e->eee_active = !!(reg & MV88E6352_PORT_STS_EEE);
2f40c698 836out:
fad09c73 837 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 838
839 return err;
11b3b45d
GR		 840}
841
f81ec90f
VD		 842static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
843 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 844{
04bed143 845 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 846 u16 reg;
847 int err;
11b3b45d 848
fad09c73 849 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 850 return -EOPNOTSUPP;
851
fad09c73 852 mutex_lock(&chip->reg_lock);
11b3b45d 853
9c93829c
VD		 854 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
855 if (err)
2f40c698
AL		 856 goto out;
857
9c93829c 858 reg &= ~0x0300;
2f40c698
AL		 859 if (e->eee_enabled)
860 reg |= 0x0200;
861 if (e->tx_lpi_enabled)
862 reg |= 0x0100;
863
9c93829c 864 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 865out:
fad09c73 866 mutex_unlock(&chip->reg_lock);
2f40c698 867
9c93829c 868 return err;
11b3b45d
GR		 869}
870
e5887a2a 871static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 872{
e5887a2a
VD		 873 struct dsa_switch *ds = NULL;
874 struct net_device *br;
875 u16 pvlan;
b7666efe
VD		 876 int i;
877
e5887a2a
VD		 878 if (dev < DSA_MAX_SWITCHES)
879 ds = chip->ds->dst->ds[dev];
880
881 /* Prevent frames from unknown switch or port */
882 if (!ds || port >= ds->num_ports)
883 return 0;
884
885 /* Frames from DSA links and CPU ports can egress any local port */
886 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
887 return mv88e6xxx_port_mask(chip);
888
889 br = ds->ports[port].bridge_dev;
890 pvlan = 0;
891
892 /* Frames from user ports can egress any local DSA links and CPU ports,
893 * as well as any local member of their bridge group.
894 */
895 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
896 if (dsa_is_cpu_port(chip->ds, i) ||
897 dsa_is_dsa_port(chip->ds, i) ||
898 (br && chip->ds->ports[i].bridge_dev == br))
899 pvlan |= BIT(i);
900
901 return pvlan;
902}
903
240ea3ef 904static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 905{
906 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 907
908 /* prevent frames from going back out of the port they came in on */
909 output_ports &= ~BIT(port);
facd95b2 910
5a7921f4 911 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 912}
913
f81ec90f
VD		 914static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
915 u8 state)
facd95b2 916{
04bed143 917 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 918 int err;
facd95b2 919
fad09c73 920 mutex_lock(&chip->reg_lock);
f894c29c 921 err = mv88e6xxx_port_set_state(chip, port, state);
fad09c73 922 mutex_unlock(&chip->reg_lock);
553eb544
VD		 923
924 if (err)
774439e5 925 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 926}
927
a2ac29d2
VD		 928static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
929{
c3a7d4ad
VD		 930 int err;
931
daefc943
VD		 932 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
933 if (err)
934 return err;
935
c3a7d4ad
VD		 936 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
937 if (err)
938 return err;
939
a2ac29d2
VD		 940 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
941}
942
17a1594e
VD		 943static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
944{
945 u16 pvlan = 0;
946
947 if (!mv88e6xxx_has_pvt(chip))
948 return -EOPNOTSUPP;
949
950 /* Skip the local source device, which uses in-chip port VLAN */
951 if (dev != chip->ds->index)
aec5ac88 952 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 953
954 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
955}
956
81228996
VD		 957static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
958{
17a1594e
VD		 959 int dev, port;
960 int err;
961
81228996
VD		 962 if (!mv88e6xxx_has_pvt(chip))
963 return 0;
964
965 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
966 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
967 */
17a1594e
VD		 968 err = mv88e6xxx_g2_misc_4_bit_port(chip);
969 if (err)
970 return err;
971
972 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
973 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
974 err = mv88e6xxx_pvt_map(chip, dev, port);
975 if (err)
976 return err;
977 }
978 }
979
980 return 0;
81228996
VD		 981}
982
749efcb8
VD		 983static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
984{
985 struct mv88e6xxx_chip *chip = ds->priv;
986 int err;
987
988 mutex_lock(&chip->reg_lock);
e606ca36 989 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 990 mutex_unlock(&chip->reg_lock);
991
992 if (err)
774439e5 993 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 994}
995
b486d7c9
VD		 996static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
997{
998 if (!chip->info->max_vid)
999 return 0;
1000
1001 return mv88e6xxx_g1_vtu_flush(chip);
1002}
1003
f1394b78
VD		 1004static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1005 struct mv88e6xxx_vtu_entry *entry)
1006{
1007 if (!chip->info->ops->vtu_getnext)
1008 return -EOPNOTSUPP;
1009
1010 return chip->info->ops->vtu_getnext(chip, entry);
1011}
1012
0ad5daf6
VD		 1013static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1014 struct mv88e6xxx_vtu_entry *entry)
1015{
1016 if (!chip->info->ops->vtu_loadpurge)
1017 return -EOPNOTSUPP;
1018
1019 return chip->info->ops->vtu_loadpurge(chip, entry);
1020}
1021
f81ec90f
VD		 1022static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1023 struct switchdev_obj_port_vlan *vlan,
438ff537 1024 switchdev_obj_dump_cb_t *cb)
ceff5eff 1025{
04bed143 1026 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1027 struct mv88e6xxx_vtu_entry next = {
1028 .vid = chip->info->max_vid,
1029 };
ceff5eff
VD		 1030 u16 pvid;
1031 int err;
1032
3cf3c846 1033 if (!chip->info->max_vid)
54d77b5b
VD		 1034 return -EOPNOTSUPP;
1035
fad09c73 1036 mutex_lock(&chip->reg_lock);
ceff5eff 1037
77064f37 1038 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1039 if (err)
1040 goto unlock;
1041
ceff5eff 1042 do {
f1394b78 1043 err = mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1044 if (err)
1045 break;
1046
1047 if (!next.valid)
1048 break;
1049
bd00e053 1050 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
ceff5eff
VD		 1051 continue;
1052
1053 /* reinit and dump this VLAN obj */
57d32310
VD		 1054 vlan->vid_begin = next.vid;
1055 vlan->vid_end = next.vid;
ceff5eff
VD		 1056 vlan->flags = 0;
1057
bd00e053 1058 if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
ceff5eff
VD		 1059 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1060
1061 if (next.vid == pvid)
1062 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1063
1064 err = cb(&vlan->obj);
1065 if (err)
1066 break;
3cf3c846 1067 } while (next.vid < chip->info->max_vid);
ceff5eff
VD		 1068
1069unlock:
fad09c73 1070 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1071
1072 return err;
1073}
1074
d7f435f9 1075static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1076{
1077 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
3afb4bde
VD		 1078 struct mv88e6xxx_vtu_entry vlan = {
1079 .vid = chip->info->max_vid,
1080 };
2db9ce1f 1081 int i, err;
3285f9e8
VD		 1082
1083 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1084
2db9ce1f 1085 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1086 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1087 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1088 if (err)
1089 return err;
1090
1091 set_bit(*fid, fid_bitmap);
1092 }
1093
3285f9e8 1094 /* Set every FID bit used by the VLAN entries */
3285f9e8 1095 do {
f1394b78 1096 err = mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1097 if (err)
1098 return err;
1099
1100 if (!vlan.valid)
1101 break;
1102
1103 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1104 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1105
1106 /* The reset value 0x000 is used to indicate that multiple address
1107 * databases are not needed. Return the next positive available.
1108 */
1109 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1110 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1111 return -ENOSPC;
1112
1113 /* Clear the database */
daefc943 1114 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1115}
1116
567aa59a
VD		 1117static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1118 struct mv88e6xxx_vtu_entry *entry, bool new)
2fb5ef09
VD		 1119{
1120 int err;
1121
1122 if (!vid)
1123 return -EINVAL;
1124
3afb4bde
VD		 1125 entry->vid = vid - 1;
1126 entry->valid = false;
2fb5ef09 1127
f1394b78 1128 err = mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1129 if (err)
1130 return err;
1131
567aa59a
VD		 1132 if (entry->vid == vid && entry->valid)
1133 return 0;
2fb5ef09 1134
567aa59a
VD		 1135 if (new) {
1136 int i;
1137
1138 /* Initialize a fresh VLAN entry */
1139 memset(entry, 0, sizeof(*entry));
1140 entry->valid = true;
1141 entry->vid = vid;
1142
553a768d 1143 /* Exclude all ports */
567aa59a 1144 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
553a768d
VD		 1145 entry->member[i] =
1146 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
567aa59a
VD		 1147
1148 return mv88e6xxx_atu_new(chip, &entry->fid);
2fb5ef09
VD		 1149 }
1150
567aa59a
VD		 1151 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1152 return -EOPNOTSUPP;
2fb5ef09
VD		 1153}
1154
da9c359e
VD		 1155static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1156 u16 vid_begin, u16 vid_end)
1157{
04bed143 1158 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1159 struct mv88e6xxx_vtu_entry vlan = {
1160 .vid = vid_begin - 1,
1161 };
da9c359e
VD		 1162 int i, err;
1163
1164 if (!vid_begin)
1165 return -EOPNOTSUPP;
1166
fad09c73 1167 mutex_lock(&chip->reg_lock);
da9c359e 1168
da9c359e 1169 do {
f1394b78 1170 err = mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1171 if (err)
1172 goto unlock;
1173
1174 if (!vlan.valid)
1175 break;
1176
1177 if (vlan.vid > vid_end)
1178 break;
1179
370b4ffb 1180 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1181 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1182 continue;
1183
66e2809d
AL		 1184 if (!ds->ports[port].netdev)
1185 continue;
1186
bd00e053 1187 if (vlan.member[i] ==
da9c359e
VD		 1188 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1189 continue;
1190
fae8a25e
VD		 1191 if (ds->ports[i].bridge_dev ==
1192 ds->ports[port].bridge_dev)
da9c359e
VD		 1193 break; /* same bridge, check next VLAN */
1194
fae8a25e 1195 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1196 continue;
1197
774439e5
VD		 1198 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1199 port, vlan.vid,
1200 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1201 err = -EOPNOTSUPP;
1202 goto unlock;
1203 }
1204 } while (vlan.vid < vid_end);
1205
1206unlock:
fad09c73 1207 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1208
1209 return err;
1210}
1211
f81ec90f
VD		 1212static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1213 bool vlan_filtering)
214cdb99 1214{
04bed143 1215 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1216 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1217 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1218 int err;
214cdb99 1219
3cf3c846 1220 if (!chip->info->max_vid)
54d77b5b
VD		 1221 return -EOPNOTSUPP;
1222
fad09c73 1223 mutex_lock(&chip->reg_lock);
385a0995 1224 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1225 mutex_unlock(&chip->reg_lock);
214cdb99 1226
0e7b9925 1227 return err;
214cdb99
VD		 1228}
1229
57d32310
VD		 1230static int
1231mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1232 const struct switchdev_obj_port_vlan *vlan,
1233 struct switchdev_trans *trans)
76e398a6 1234{
04bed143 1235 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1236 int err;
1237
3cf3c846 1238 if (!chip->info->max_vid)
54d77b5b
VD		 1239 return -EOPNOTSUPP;
1240
da9c359e
VD		 1241 /* If the requested port doesn't belong to the same bridge as the VLAN
1242 * members, do not support it (yet) and fallback to software VLAN.
1243 */
1244 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1245 vlan->vid_end);
1246 if (err)
1247 return err;
1248
76e398a6
VD		 1249 /* We don't need any dynamic resource from the kernel (yet),
1250 * so skip the prepare phase.
1251 */
1252 return 0;
1253}
1254
fad09c73 1255static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
c91498e1 1256 u16 vid, u8 member)
0d3b33e6 1257{
b4e47c0f 1258 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1259 int err;
1260
567aa59a 1261 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1262 if (err)
76e398a6 1263 return err;
0d3b33e6 1264
c91498e1 1265 vlan.member[port] = member;
0d3b33e6 1266
0ad5daf6 1267 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1268}
1269
f81ec90f
VD		 1270static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1271 const struct switchdev_obj_port_vlan *vlan,
1272 struct switchdev_trans *trans)
76e398a6 1273{
04bed143 1274 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1275 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1276 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
c91498e1 1277 u8 member;
76e398a6 1278 u16 vid;
76e398a6 1279
3cf3c846 1280 if (!chip->info->max_vid)
54d77b5b
VD		 1281 return;
1282
c91498e1
VD		 1283 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1284 member = GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1285 else if (untagged)
1286 member = GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED;
1287 else
1288 member = GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1289
fad09c73 1290 mutex_lock(&chip->reg_lock);
76e398a6 1291
4d5770b3 1292 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
c91498e1 1293 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
774439e5
VD		 1294 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1295 vid, untagged ? 'u' : 't');
76e398a6 1296
77064f37 1297 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
774439e5
VD		 1298 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1299 vlan->vid_end);
0d3b33e6 1300
fad09c73 1301 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1302}
1303
fad09c73 1304static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1305 int port, u16 vid)
7dad08d7 1306{
b4e47c0f 1307 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1308 int i, err;
1309
567aa59a 1310 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1311 if (err)
76e398a6 1312 return err;
7dad08d7 1313
2fb5ef09 1314 /* Tell switchdev if this VLAN is handled in software */
bd00e053 1315 if (vlan.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1316 return -EOPNOTSUPP;
7dad08d7 1317
bd00e053 1318 vlan.member[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1319
1320 /* keep the VLAN unless all ports are excluded */
f02bdffc 1321 vlan.valid = false;
370b4ffb 1322 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
bd00e053 1323 if (vlan.member[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1324 vlan.valid = true;
7dad08d7
VD		 1325 break;
1326 }
1327 }
1328
0ad5daf6 1329 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1330 if (err)
1331 return err;
1332
e606ca36 1333 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1334}
1335
f81ec90f
VD		 1336static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1337 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1338{
04bed143 1339 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1340 u16 pvid, vid;
1341 int err = 0;
1342
3cf3c846 1343 if (!chip->info->max_vid)
54d77b5b
VD		 1344 return -EOPNOTSUPP;
1345
fad09c73 1346 mutex_lock(&chip->reg_lock);
76e398a6 1347
77064f37 1348 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1349 if (err)
1350 goto unlock;
1351
76e398a6 1352 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1353 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1354 if (err)
1355 goto unlock;
1356
1357 if (vid == pvid) {
77064f37 1358 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1359 if (err)
1360 goto unlock;
1361 }
1362 }
1363
7dad08d7 1364unlock:
fad09c73 1365 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1366
1367 return err;
1368}
1369
83dabd1f
VD		 1370static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1371 const unsigned char *addr, u16 vid,
1372 u8 state)
fd231c82 1373{
b4e47c0f 1374 struct mv88e6xxx_vtu_entry vlan;
88472939 1375 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1376 int err;
1377
2db9ce1f
VD		 1378 /* Null VLAN ID corresponds to the port private database */
1379 if (vid == 0)
b4e48c50 1380 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1381 else
567aa59a 1382 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1383 if (err)
1384 return err;
fd231c82 1385
dabc1a96
VD		 1386 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1387 ether_addr_copy(entry.mac, addr);
1388 eth_addr_dec(entry.mac);
1389
1390 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1391 if (err)
1392 return err;
1393
dabc1a96
VD		 1394 /* Initialize a fresh ATU entry if it isn't found */
1395 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1396 !ether_addr_equal(entry.mac, addr)) {
1397 memset(&entry, 0, sizeof(entry));
1398 ether_addr_copy(entry.mac, addr);
1399 }
1400
88472939
VD		 1401 /* Purge the ATU entry only if no port is using it anymore */
1402 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1403 entry.portvec &= ~BIT(port);
1404 if (!entry.portvec)
88472939
VD		 1405 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1406 } else {
01bd96c8 1407 entry.portvec |= BIT(port);
88472939 1408 entry.state = state;
fd231c82
VD		 1409 }
1410
9c13c026 1411 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1412}
1413
f81ec90f
VD		 1414static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1415 const struct switchdev_obj_port_fdb *fdb,
1416 struct switchdev_trans *trans)
146a3206
VD		 1417{
1418 /* We don't need any dynamic resource from the kernel (yet),
1419 * so skip the prepare phase.
1420 */
1421 return 0;
1422}
1423
f81ec90f
VD		 1424static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1425 const struct switchdev_obj_port_fdb *fdb,
1426 struct switchdev_trans *trans)
87820510 1427{
04bed143 1428 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1429
fad09c73 1430 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1431 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1432 GLOBAL_ATU_DATA_STATE_UC_STATIC))
774439e5
VD		 1433 dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
1434 port);
fad09c73 1435 mutex_unlock(&chip->reg_lock);
87820510
VD		 1436}
1437
f81ec90f
VD		 1438static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1439 const struct switchdev_obj_port_fdb *fdb)
87820510 1440{
04bed143 1441 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1442 int err;
87820510 1443
fad09c73 1444 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 1445 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
1446 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 1447 mutex_unlock(&chip->reg_lock);
87820510 1448
83dabd1f 1449 return err;
87820510
VD		 1450}
1451
83dabd1f
VD		 1452static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1453 u16 fid, u16 vid, int port,
1454 struct switchdev_obj *obj,
438ff537 1455 switchdev_obj_dump_cb_t *cb)
74b6ba0d 1456{
dabc1a96 1457 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 1458 int err;
1459
dabc1a96
VD		 1460 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1461 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1462
1463 do {
dabc1a96 1464 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1465 if (err)
83dabd1f 1466 return err;
74b6ba0d
VD		 1467
1468 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1469 break;
1470
01bd96c8 1471 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1472 continue;
1473
1474 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1475 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 1476
83dabd1f
VD		 1477 if (!is_unicast_ether_addr(addr.mac))
1478 continue;
1479
1480 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 1481 fdb->vid = vid;
1482 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 1483 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
1484 fdb->ndm_state = NUD_NOARP;
1485 else
1486 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 1487 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1488 struct switchdev_obj_port_mdb *mdb;
1489
1490 if (!is_multicast_ether_addr(addr.mac))
1491 continue;
1492
1493 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1494 mdb->vid = vid;
1495 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 1496 } else {
1497 return -EOPNOTSUPP;
74b6ba0d 1498 }
83dabd1f
VD		 1499
1500 err = cb(obj);
1501 if (err)
1502 return err;
74b6ba0d
VD		 1503 } while (!is_broadcast_ether_addr(addr.mac));
1504
1505 return err;
1506}
1507
83dabd1f
VD		 1508static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1509 struct switchdev_obj *obj,
438ff537 1510 switchdev_obj_dump_cb_t *cb)
f33475bd 1511{
b4e47c0f 1512 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 1513 .vid = chip->info->max_vid,
f33475bd 1514 };
2db9ce1f 1515 u16 fid;
f33475bd
VD		 1516 int err;
1517
2db9ce1f 1518 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 1519 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 1520 if (err)
83dabd1f 1521 return err;
2db9ce1f 1522
83dabd1f 1523 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 1524 if (err)
83dabd1f 1525 return err;
2db9ce1f 1526
74b6ba0d 1527 /* Dump VLANs' Filtering Information Databases */
f33475bd 1528 do {
f1394b78 1529 err = mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 1530 if (err)
83dabd1f 1531 return err;
f33475bd
VD		 1532
1533 if (!vlan.valid)
1534 break;
1535
83dabd1f
VD		 1536 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1537 obj, cb);
f33475bd 1538 if (err)
83dabd1f 1539 return err;
3cf3c846 1540 } while (vlan.vid < chip->info->max_vid);
f33475bd 1541
83dabd1f
VD		 1542 return err;
1543}
1544
1545static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1546 struct switchdev_obj_port_fdb *fdb,
438ff537 1547 switchdev_obj_dump_cb_t *cb)
83dabd1f 1548{
04bed143 1549 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 1550 int err;
1551
1552 mutex_lock(&chip->reg_lock);
1553 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 1554 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 1555
1556 return err;
1557}
1558
240ea3ef
VD		 1559static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1560 struct net_device *br)
e79a8bcb 1561{
e96a6e02 1562 struct dsa_switch *ds;
240ea3ef 1563 int port;
e96a6e02 1564 int dev;
240ea3ef 1565 int err;
466dfa07 1566
240ea3ef
VD		 1567 /* Remap the Port VLAN of each local bridge group member */
1568 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1569 if (chip->ds->ports[port].bridge_dev == br) {
1570 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 1571 if (err)
240ea3ef 1572 return err;
b7666efe
VD		 1573 }
1574 }
1575
e96a6e02
VD		 1576 if (!mv88e6xxx_has_pvt(chip))
1577 return 0;
1578
1579 /* Remap the Port VLAN of each cross-chip bridge group member */
1580 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1581 ds = chip->ds->dst->ds[dev];
1582 if (!ds)
1583 break;
1584
1585 for (port = 0; port < ds->num_ports; ++port) {
1586 if (ds->ports[port].bridge_dev == br) {
1587 err = mv88e6xxx_pvt_map(chip, dev, port);
1588 if (err)
1589 return err;
1590 }
1591 }
1592 }
1593
240ea3ef
VD		 1594 return 0;
1595}
1596
1597static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1598 struct net_device *br)
1599{
1600 struct mv88e6xxx_chip *chip = ds->priv;
1601 int err;
1602
1603 mutex_lock(&chip->reg_lock);
1604 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 1605 mutex_unlock(&chip->reg_lock);
a6692754 1606
466dfa07 1607 return err;
e79a8bcb
VD		 1608}
1609
f123f2fb
VD		 1610static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1611 struct net_device *br)
66d9cd0f 1612{
04bed143 1613 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 1614
fad09c73 1615 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 1616 if (mv88e6xxx_bridge_map(chip, br) ||
1617 mv88e6xxx_port_vlan_map(chip, port))
1618 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 1619 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 1620}
1621
aec5ac88
VD		 1622static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1623 int port, struct net_device *br)
1624{
1625 struct mv88e6xxx_chip *chip = ds->priv;
1626 int err;
1627
1628 if (!mv88e6xxx_has_pvt(chip))
1629 return 0;
1630
1631 mutex_lock(&chip->reg_lock);
1632 err = mv88e6xxx_pvt_map(chip, dev, port);
1633 mutex_unlock(&chip->reg_lock);
1634
1635 return err;
1636}
1637
1638static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1639 int port, struct net_device *br)
1640{
1641 struct mv88e6xxx_chip *chip = ds->priv;
1642
1643 if (!mv88e6xxx_has_pvt(chip))
1644 return;
1645
1646 mutex_lock(&chip->reg_lock);
1647 if (mv88e6xxx_pvt_map(chip, dev, port))
1648 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1649 mutex_unlock(&chip->reg_lock);
1650}
1651
17e708ba
VD		 1652static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1653{
1654 if (chip->info->ops->reset)
1655 return chip->info->ops->reset(chip);
1656
1657 return 0;
1658}
1659
309eca6d
VD		 1660static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1661{
1662 struct gpio_desc *gpiod = chip->reset;
1663
1664 /* If there is a GPIO connected to the reset pin, toggle it */
1665 if (gpiod) {
1666 gpiod_set_value_cansleep(gpiod, 1);
1667 usleep_range(10000, 20000);
1668 gpiod_set_value_cansleep(gpiod, 0);
1669 usleep_range(10000, 20000);
1670 }
1671}
1672
4ac4b5a6 1673static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 1674{
4ac4b5a6 1675 int i, err;
552238b5 1676
4ac4b5a6 1677 /* Set all ports to the Disabled state */
370b4ffb 1678 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 1679 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 1680 if (err)
1681 return err;
552238b5
VD		 1682 }
1683
4ac4b5a6
VD		 1684 /* Wait for transmit queues to drain,
1685 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1686 */
552238b5
VD		 1687 usleep_range(2000, 4000);
1688
4ac4b5a6
VD		 1689 return 0;
1690}
1691
1692static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1693{
4ac4b5a6
VD		 1694 int err;
1695
1696 err = mv88e6xxx_disable_ports(chip);
1697 if (err)
1698 return err;
1699
309eca6d 1700 mv88e6xxx_hardware_reset(chip);
552238b5 1701
17e708ba 1702 return mv88e6xxx_software_reset(chip);
552238b5
VD		 1703}
1704
4314557c 1705static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 1706 enum mv88e6xxx_frame_mode frame,
1707 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 1708{
1709 int err;
1710
4314557c
VD		 1711 if (!chip->info->ops->port_set_frame_mode)
1712 return -EOPNOTSUPP;
1713
1714 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 1715 if (err)
1716 return err;
1717
4314557c
VD		 1718 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1719 if (err)
1720 return err;
1721
1722 if (chip->info->ops->port_set_ether_type)
1723 return chip->info->ops->port_set_ether_type(chip, port, etype);
1724
1725 return 0;
56995cbc
AL		 1726}
1727
4314557c 1728static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 1729{
4314557c 1730 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 1731 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
4314557c
VD		 1732 PORT_ETH_TYPE_DEFAULT);
1733}
56995cbc 1734
4314557c
VD		 1735static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1736{
1737 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 1738 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
4314557c
VD		 1739 PORT_ETH_TYPE_DEFAULT);
1740}
56995cbc 1741
4314557c
VD		 1742static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1743{
1744 return mv88e6xxx_set_port_mode(chip, port,
1745 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 1746 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1747 ETH_P_EDSA);
4314557c 1748}
56995cbc 1749
4314557c
VD		 1750static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1751{
1752 if (dsa_is_dsa_port(chip->ds, port))
1753 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1754
4314557c
VD		 1755 if (dsa_is_normal_port(chip->ds, port))
1756 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 1757
4314557c
VD		 1758 /* Setup CPU port mode depending on its supported tag format */
1759 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1760 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1761
4314557c
VD		 1762 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1763 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 1764
4314557c 1765 return -EINVAL;
56995cbc
AL		 1766}
1767
601aeed3 1768static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 1769{
601aeed3 1770 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 1771
601aeed3 1772 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 1773}
56995cbc 1774
601aeed3 1775static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 1776{
601aeed3 1777 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 1778
601aeed3
VD		 1779 /* Upstream ports flood frames with unknown unicast or multicast DA */
1780 if (chip->info->ops->port_set_egress_floods)
1781 return chip->info->ops->port_set_egress_floods(chip, port,
1782 flood, flood);
ea698f4f 1783
601aeed3 1784 return 0;
ea698f4f
VD		 1785}
1786
6d91782f
AL		 1787static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1788 bool on)
1789{
523a8904
VD		 1790 if (chip->info->ops->serdes_power)
1791 return chip->info->ops->serdes_power(chip, port, on);
04aca993 1792
523a8904 1793 return 0;
6d91782f
AL		 1794}
1795
fad09c73 1796static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 1797{
fad09c73 1798 struct dsa_switch *ds = chip->ds;
0e7b9925 1799 int err;
54d792f2 1800 u16 reg;
d827e88a 1801
d78343d2
VD		 1802 /* MAC Forcing register: don't force link, speed, duplex or flow control
1803 * state to any particular values on physical ports, but force the CPU
1804 * port and all DSA ports to their maximum bandwidth and full duplex.
1805 */
1806 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1807 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1808 SPEED_MAX, DUPLEX_FULL,
1809 PHY_INTERFACE_MODE_NA);
1810 else
1811 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1812 SPEED_UNFORCED, DUPLEX_UNFORCED,
1813 PHY_INTERFACE_MODE_NA);
1814 if (err)
1815 return err;
54d792f2
AL		 1816
1817 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1818 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1819 * tunneling, determine priority by looking at 802.1p and IP
1820 * priority fields (IP prio has precedence), and set STP state
1821 * to Forwarding.
1822 *
1823 * If this is the CPU link, use DSA or EDSA tagging depending
1824 * on which tagging mode was configured.
1825 *
1826 * If this is a link to another switch, use DSA tagging mode.
1827 *
1828 * If this is the upstream port for this switch, enable
1829 * forwarding of unknown unicasts and multicasts.
1830 */
a89b433b
VD		 1831 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1832 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1833 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1834 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 1835 if (err)
1836 return err;
6083ce71 1837
601aeed3 1838 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 1839 if (err)
1840 return err;
54d792f2 1841
601aeed3 1842 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 1843 if (err)
1844 return err;
1845
04aca993
AL		 1846 /* Enable the SERDES interface for DSA and CPU ports. Normal
1847 * ports SERDES are enabled when the port is enabled, thus
1848 * saving a bit of power.
13a7ebb3 1849 */
04aca993
AL		 1850 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1851 err = mv88e6xxx_serdes_power(chip, port, true);
1852 if (err)
1853 return err;
1854 }
13a7ebb3 1855
8efdda4a 1856 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 1857 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 1858 * untagged frames on this port, do a destination address lookup on all
1859 * received packets as usual, disable ARP mirroring and don't send a
1860 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 1861 */
a23b2961
AL		 1862 err = mv88e6xxx_port_set_map_da(chip, port);
1863 if (err)
1864 return err;
8efdda4a 1865
a23b2961
AL		 1866 reg = 0;
1867 if (chip->info->ops->port_set_upstream_port) {
1868 err = chip->info->ops->port_set_upstream_port(
1869 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 1870 if (err)
1871 return err;
54d792f2
AL		 1872 }
1873
a23b2961
AL		 1874 err = mv88e6xxx_port_set_8021q_mode(chip, port,
1875 PORT_CONTROL_2_8021Q_DISABLED);
1876 if (err)
1877 return err;
1878
cd782656
VD		 1879 if (chip->info->ops->port_set_jumbo_size) {
1880 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 1881 if (err)
1882 return err;
1883 }
1884
54d792f2
AL		 1885 /* Port Association Vector: when learning source addresses
1886 * of packets, add the address to the address database using
1887 * a port bitmap that has only the bit for this port set and
1888 * the other bits clear.
1889 */
4c7ea3c0 1890 reg = 1 << port;
996ecb82
VD		 1891 /* Disable learning for CPU port */
1892 if (dsa_is_cpu_port(ds, port))
65fa4027 1893 reg = 0;
4c7ea3c0 1894
0e7b9925
AL		 1895 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
1896 if (err)
1897 return err;
54d792f2
AL		 1898
1899 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 1900 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
1901 if (err)
1902 return err;
54d792f2 1903
0898432c
VD		 1904 if (chip->info->ops->port_pause_limit) {
1905 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 1906 if (err)
1907 return err;
b35d322a 1908 }
54d792f2 1909
c8c94891
VD		 1910 if (chip->info->ops->port_disable_learn_limit) {
1911 err = chip->info->ops->port_disable_learn_limit(chip, port);
1912 if (err)
1913 return err;
1914 }
1915
9dbfb4e1
VD		 1916 if (chip->info->ops->port_disable_pri_override) {
1917 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 1918 if (err)
1919 return err;
ef0a7318 1920 }
2bbb33be 1921
ef0a7318
AL		 1922 if (chip->info->ops->port_tag_remap) {
1923 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 1924 if (err)
1925 return err;
54d792f2
AL		 1926 }
1927
ef70b111
AL		 1928 if (chip->info->ops->port_egress_rate_limiting) {
1929 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 1930 if (err)
1931 return err;
54d792f2
AL		 1932 }
1933
ea698f4f 1934 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 1935 if (err)
1936 return err;
d827e88a 1937
207afda1 1938 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 1939 * database, and allow bidirectional communication between the
1940 * CPU and DSA port(s), and the other ports.
d827e88a 1941 */
b4e48c50 1942 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 1943 if (err)
1944 return err;
2db9ce1f 1945
240ea3ef 1946 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 1947 if (err)
1948 return err;
d827e88a
GR		 1949
1950 /* Default VLAN ID and priority: don't set a default VLAN
1951 * ID, and set the default packet priority to zero.
1952 */
b7929fb3 1953 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 1954}
1955
04aca993
AL		 1956static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1957 struct phy_device *phydev)
1958{
1959 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 1960 int err;
04aca993
AL		 1961
1962 mutex_lock(&chip->reg_lock);
523a8904 1963 err = mv88e6xxx_serdes_power(chip, port, true);
04aca993
AL		 1964 mutex_unlock(&chip->reg_lock);
1965
1966 return err;
1967}
1968
1969static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1970 struct phy_device *phydev)
1971{
1972 struct mv88e6xxx_chip *chip = ds->priv;
1973
1974 mutex_lock(&chip->reg_lock);
523a8904
VD		 1975 if (mv88e6xxx_serdes_power(chip, port, false))
1976 dev_err(chip->dev, "failed to power off SERDES\n");
04aca993
AL		 1977 mutex_unlock(&chip->reg_lock);
1978}
1979
aa0938c6 1980static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 1981{
1982 int err;
1983
a935c052 1984 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 1985 if (err)
1986 return err;
1987
a935c052 1988 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 1989 if (err)
1990 return err;
1991
a935c052
VD		 1992 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
1993 if (err)
1994 return err;
1995
1996 return 0;
3b4caa1b
VD		 1997}
1998
2cfcd964
VD		 1999static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2000 unsigned int ageing_time)
2001{
04bed143 2002 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2003 int err;
2004
2005 mutex_lock(&chip->reg_lock);
720c6343 2006 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2007 mutex_unlock(&chip->reg_lock);
2008
2009 return err;
2010}
2011
9729934c 2012static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2013{
fad09c73 2014 struct dsa_switch *ds = chip->ds;
b0745e87 2015 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2016 int err;
54d792f2 2017
fa8d1179
VD		 2018 if (chip->info->ops->set_cpu_port) {
2019 err = chip->info->ops->set_cpu_port(chip, upstream_port);
33641994
AL		 2020 if (err)
2021 return err;
2022 }
2023
fa8d1179
VD		 2024 if (chip->info->ops->set_egress_port) {
2025 err = chip->info->ops->set_egress_port(chip, upstream_port);
33641994
AL		 2026 if (err)
2027 return err;
2028 }
b0745e87 2029
50484ff4 2030 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2031 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2032 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2033 (ds->index & 0x1f));
50484ff4
VD		 2034 if (err)
2035 return err;
2036
54d792f2 2037 /* Configure the IP ToS mapping registers. */
a935c052 2038 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2039 if (err)
08a01261 2040 return err;
a935c052 2041 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2042 if (err)
08a01261 2043 return err;
a935c052 2044 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2045 if (err)
08a01261 2046 return err;
a935c052 2047 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2048 if (err)
08a01261 2049 return err;
a935c052 2050 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2051 if (err)
08a01261 2052 return err;
a935c052 2053 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2054 if (err)
08a01261 2055 return err;
a935c052 2056 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2057 if (err)
08a01261 2058 return err;
a935c052 2059 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2060 if (err)
08a01261 2061 return err;
54d792f2
AL		 2062
2063 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2064 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2065 if (err)
08a01261 2066 return err;
54d792f2 2067
de227387
AL		 2068 /* Initialize the statistics unit */
2069 err = mv88e6xxx_stats_set_histogram(chip);
2070 if (err)
2071 return err;
2072
9729934c 2073 /* Clear the statistics counters for all ports */
a935c052
VD		 2074 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2075 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2076 if (err)
2077 return err;
2078
2079 /* Wait for the flush to complete. */
7f9ef3af 2080 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2081 if (err)
2082 return err;
2083
2084 return 0;
2085}
2086
f81ec90f 2087static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2088{
04bed143 2089 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2090 int err;
a1a6a4d1
VD		 2091 int i;
2092
fad09c73 2093 chip->ds = ds;
a3c53be5 2094 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2095
fad09c73 2096 mutex_lock(&chip->reg_lock);
08a01261 2097
9729934c 2098 /* Setup Switch Port Registers */
370b4ffb 2099 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2100 err = mv88e6xxx_setup_port(chip, i);
2101 if (err)
2102 goto unlock;
2103 }
2104
2105 /* Setup Switch Global 1 Registers */
2106 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2107 if (err)
2108 goto unlock;
2109
9729934c
VD		 2110 /* Setup Switch Global 2 Registers */
2111 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2112 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2113 if (err)
2114 goto unlock;
2115 }
08a01261 2116
1b17aedf
VD		 2117 err = mv88e6xxx_phy_setup(chip);
2118 if (err)
2119 goto unlock;
2120
b486d7c9
VD		 2121 err = mv88e6xxx_vtu_setup(chip);
2122 if (err)
2123 goto unlock;
2124
81228996
VD		 2125 err = mv88e6xxx_pvt_setup(chip);
2126 if (err)
2127 goto unlock;
2128
a2ac29d2
VD		 2129 err = mv88e6xxx_atu_setup(chip);
2130 if (err)
2131 goto unlock;
2132
6e55f698
AL		 2133 /* Some generations have the configuration of sending reserved
2134 * management frames to the CPU in global2, others in
2135 * global1. Hence it does not fit the two setup functions
2136 * above.
2137 */
2138 if (chip->info->ops->mgmt_rsvd2cpu) {
2139 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2140 if (err)
2141 goto unlock;
2142 }
2143
6b17e864 2144unlock:
fad09c73 2145 mutex_unlock(&chip->reg_lock);
db687a56 2146
48ace4ef 2147 return err;
54d792f2
AL		 2148}
2149
3b4caa1b
VD		 2150static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2151{
04bed143 2152 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2153 int err;
2154
b073d4e2
VD		 2155 if (!chip->info->ops->set_switch_mac)
2156 return -EOPNOTSUPP;
3b4caa1b 2157
b073d4e2
VD		 2158 mutex_lock(&chip->reg_lock);
2159 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2160 mutex_unlock(&chip->reg_lock);
2161
2162 return err;
2163}
2164
e57e5e77 2165static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2166{
0dd12d54
AL		 2167 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2168 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2169 u16 val;
2170 int err;
fd3a0ee4 2171
ee26a228
AL		 2172 if (!chip->info->ops->phy_read)
2173 return -EOPNOTSUPP;
2174
fad09c73 2175 mutex_lock(&chip->reg_lock);
ee26a228 2176 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2177 mutex_unlock(&chip->reg_lock);
e57e5e77 2178
da9f3301
AL		 2179 if (reg == MII_PHYSID2) {
2180 /* Some internal PHYS don't have a model number. Use
2181 * the mv88e6390 family model number instead.
2182 */
2183 if (!(val & 0x3f0))
107fcc10 2184 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
da9f3301
AL		 2185 }
2186
e57e5e77 2187 return err ? err : val;
fd3a0ee4
AL		 2188}
2189
e57e5e77 2190static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2191{
0dd12d54
AL		 2192 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2193 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2194 int err;
fd3a0ee4 2195
ee26a228
AL		 2196 if (!chip->info->ops->phy_write)
2197 return -EOPNOTSUPP;
2198
fad09c73 2199 mutex_lock(&chip->reg_lock);
ee26a228 2200 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2201 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2202
2203 return err;
fd3a0ee4
AL		 2204}
2205
fad09c73 2206static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2207 struct device_node *np,
2208 bool external)
b516d453
AL		 2209{
2210 static int index;
0dd12d54 2211 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2212 struct mii_bus *bus;
2213 int err;
2214
0dd12d54 2215 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2216 if (!bus)
2217 return -ENOMEM;
2218
0dd12d54 2219 mdio_bus = bus->priv;
a3c53be5 2220 mdio_bus->bus = bus;
0dd12d54 2221 mdio_bus->chip = chip;
a3c53be5
AL		 2222 INIT_LIST_HEAD(&mdio_bus->list);
2223 mdio_bus->external = external;
0dd12d54 2224
b516d453
AL		 2225 if (np) {
2226 bus->name = np->full_name;
2227 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2228 } else {
2229 bus->name = "mv88e6xxx SMI";
2230 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2231 }
2232
2233 bus->read = mv88e6xxx_mdio_read;
2234 bus->write = mv88e6xxx_mdio_write;
fad09c73 2235 bus->parent = chip->dev;
b516d453 2236
a3c53be5
AL		 2237 if (np)
2238 err = of_mdiobus_register(bus, np);
b516d453
AL		 2239 else
2240 err = mdiobus_register(bus);
2241 if (err) {
fad09c73 2242 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2243 return err;
b516d453 2244 }
a3c53be5
AL		 2245
2246 if (external)
2247 list_add_tail(&mdio_bus->list, &chip->mdios);
2248 else
2249 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2250
2251 return 0;
a3c53be5 2252}
b516d453 2253
a3c53be5
AL		 2254static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2255 { .compatible = "marvell,mv88e6xxx-mdio-external",
2256 .data = (void *)true },
2257 { },
2258};
b516d453 2259
a3c53be5
AL		 2260static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2261 struct device_node *np)
2262{
2263 const struct of_device_id *match;
2264 struct device_node *child;
2265 int err;
2266
2267 /* Always register one mdio bus for the internal/default mdio
2268 * bus. This maybe represented in the device tree, but is
2269 * optional.
2270 */
2271 child = of_get_child_by_name(np, "mdio");
2272 err = mv88e6xxx_mdio_register(chip, child, false);
2273 if (err)
2274 return err;
2275
2276 /* Walk the device tree, and see if there are any other nodes
2277 * which say they are compatible with the external mdio
2278 * bus.
2279 */
2280 for_each_available_child_of_node(np, child) {
2281 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2282 if (match) {
2283 err = mv88e6xxx_mdio_register(chip, child, true);
2284 if (err)
2285 return err;
2286 }
2287 }
2288
2289 return 0;
b516d453
AL		 2290}
2291
a3c53be5 2292static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2293
2294{
a3c53be5
AL		 2295 struct mv88e6xxx_mdio_bus *mdio_bus;
2296 struct mii_bus *bus;
b516d453 2297
a3c53be5
AL		 2298 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2299 bus = mdio_bus->bus;
b516d453 2300
a3c53be5
AL		 2301 mdiobus_unregister(bus);
2302 }
b516d453
AL		 2303}
2304
855b1932
VD		 2305static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2306{
04bed143 2307 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2308
2309 return chip->eeprom_len;
2310}
2311
855b1932
VD		 2312static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2313 struct ethtool_eeprom *eeprom, u8 *data)
2314{
04bed143 2315 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2316 int err;
2317
ee4dc2e7
VD		 2318 if (!chip->info->ops->get_eeprom)
2319 return -EOPNOTSUPP;
855b1932 2320
ee4dc2e7
VD		 2321 mutex_lock(&chip->reg_lock);
2322 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2323 mutex_unlock(&chip->reg_lock);
2324
2325 if (err)
2326 return err;
2327
2328 eeprom->magic = 0xc3ec4951;
2329
2330 return 0;
2331}
2332
855b1932
VD		 2333static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2334 struct ethtool_eeprom *eeprom, u8 *data)
2335{
04bed143 2336 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2337 int err;
2338
ee4dc2e7
VD		 2339 if (!chip->info->ops->set_eeprom)
2340 return -EOPNOTSUPP;
2341
855b1932
VD		 2342 if (eeprom->magic != 0xc3ec4951)
2343 return -EINVAL;
2344
2345 mutex_lock(&chip->reg_lock);
ee4dc2e7 2346 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2347 mutex_unlock(&chip->reg_lock);
2348
2349 return err;
2350}
2351
b3469dd8 2352static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2353 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 2354 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2355 .phy_read = mv88e6185_phy_ppu_read,
2356 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2357 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2358 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2359 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2360 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2361 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2362 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2363 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2364 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2365 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2366 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2367 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2368 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2369 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2370 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2371 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2372 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2373 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2374 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2375 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2376 .ppu_enable = mv88e6185_g1_ppu_enable,
2377 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2378 .reset = mv88e6185_g1_reset,
f1394b78 2379 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2380 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2381};
2382
2383static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2384 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2385 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2386 .phy_read = mv88e6185_phy_ppu_read,
2387 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2388 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2389 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2390 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2391 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2392 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2393 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2394 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2395 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2396 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2397 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 2398 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2399 .ppu_enable = mv88e6185_g1_ppu_enable,
2400 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2401 .reset = mv88e6185_g1_reset,
f1394b78 2402 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2403 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2404};
2405
7d381a02 2406static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2407 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 2408 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2409 .phy_read = mv88e6xxx_g2_smi_phy_read,
2410 .phy_write = mv88e6xxx_g2_smi_phy_write,
2411 .port_set_link = mv88e6xxx_port_set_link,
2412 .port_set_duplex = mv88e6xxx_port_set_duplex,
2413 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2414 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2415 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2416 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2417 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2418 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2419 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 2420 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2421 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2422 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2423 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2424 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2425 .stats_get_strings = mv88e6095_stats_get_strings,
2426 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2427 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2428 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2429 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2430 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2431 .reset = mv88e6352_g1_reset,
f1394b78 2432 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2433 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
7d381a02
SE		 2434};
2435
b3469dd8 2436static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2437 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2438 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2439 .phy_read = mv88e6xxx_g2_smi_phy_read,
2440 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2441 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2442 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2443 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2444 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2445 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2446 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2447 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2448 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2449 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2450 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2451 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2452 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2453 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2454 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2455 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2456 .reset = mv88e6352_g1_reset,
f1394b78 2457 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2458 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2459};
2460
2461static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2462 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2463 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2464 .phy_read = mv88e6185_phy_ppu_read,
2465 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2466 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2467 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2468 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2469 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2470 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2471 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2472 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2473 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 2474 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2475 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2476 .port_pause_limit = mv88e6097_port_pause_limit,
a605a0fe 2477 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2478 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2479 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2480 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2481 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2482 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2483 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2484 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2485 .ppu_enable = mv88e6185_g1_ppu_enable,
2486 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2487 .reset = mv88e6185_g1_reset,
f1394b78 2488 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2489 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2490};
2491
990e27b0
VD		 2492static const struct mv88e6xxx_ops mv88e6141_ops = {
2493 /* MV88E6XXX_FAMILY_6341 */
2494 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2495 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2496 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2497 .phy_read = mv88e6xxx_g2_smi_phy_read,
2498 .phy_write = mv88e6xxx_g2_smi_phy_write,
2499 .port_set_link = mv88e6xxx_port_set_link,
2500 .port_set_duplex = mv88e6xxx_port_set_duplex,
2501 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2502 .port_set_speed = mv88e6390_port_set_speed,
2503 .port_tag_remap = mv88e6095_port_tag_remap,
2504 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2505 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2506 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2507 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 2508 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2509 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 2510 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2511 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2512 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2513 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2514 .stats_get_strings = mv88e6320_stats_get_strings,
2515 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2516 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2517 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 2518 .watchdog_ops = &mv88e6390_watchdog_ops,
2519 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2520 .reset = mv88e6352_g1_reset,
f1394b78 2521 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2522 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
990e27b0
VD		 2523};
2524
b3469dd8 2525static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2526 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2527 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2528 .phy_read = mv88e6xxx_g2_smi_phy_read,
2529 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2530 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2531 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2532 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2533 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2534 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2535 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2536 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2537 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2538 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2539 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2540 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2541 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2542 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2543 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2544 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2545 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2546 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2547 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2548 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2549 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2550 .reset = mv88e6352_g1_reset,
f1394b78 2551 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2552 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2553};
2554
2555static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2556 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2557 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2558 .phy_read = mv88e6165_phy_read,
2559 .phy_write = mv88e6165_phy_write,
08ef7f10 2560 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2561 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2562 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 2563 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2564 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2565 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2566 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2567 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2568 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2569 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2570 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2571 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2572 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2573 .reset = mv88e6352_g1_reset,
f1394b78 2574 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2575 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2576};
2577
2578static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2579 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 2580 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2581 .phy_read = mv88e6xxx_g2_smi_phy_read,
2582 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2583 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2584 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2585 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2586 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2587 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2588 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2589 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2590 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2591 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2592 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2593 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2594 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2595 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2596 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2597 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2598 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2599 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2600 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2601 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2602 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2603 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2604 .reset = mv88e6352_g1_reset,
f1394b78 2605 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2606 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2607};
2608
2609static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 2610 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 2611 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2612 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2613 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2614 .phy_read = mv88e6xxx_g2_smi_phy_read,
2615 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2616 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2617 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2618 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2619 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2620 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2621 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2622 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2623 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2624 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2625 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2626 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2627 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2628 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2629 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2630 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2631 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2632 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2633 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2634 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2635 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2636 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2637 .reset = mv88e6352_g1_reset,
f1394b78 2638 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2639 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2640 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2641};
2642
2643static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 2644 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 2645 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2646 .phy_read = mv88e6xxx_g2_smi_phy_read,
2647 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2648 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2649 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2650 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2651 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2652 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2653 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2654 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2655 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2656 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2657 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2658 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2659 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2660 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2661 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2662 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2663 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2664 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2665 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2666 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2667 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2668 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2669 .reset = mv88e6352_g1_reset,
f1394b78 2670 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2671 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2672};
2673
2674static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 2675 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 2676 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2677 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2678 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2679 .phy_read = mv88e6xxx_g2_smi_phy_read,
2680 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2681 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2682 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2683 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2684 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2685 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2686 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2687 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2688 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2689 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2690 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2691 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2692 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2693 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2694 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2695 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2696 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2697 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2698 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2699 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2700 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2701 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2702 .reset = mv88e6352_g1_reset,
f1394b78 2703 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2704 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2705 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2706};
2707
2708static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 2709 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2710 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2711 .phy_read = mv88e6185_phy_ppu_read,
2712 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2713 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2714 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2715 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2716 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2717 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 2718 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 2719 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2720 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2721 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2722 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2723 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2724 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2725 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2726 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2727 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2728 .ppu_enable = mv88e6185_g1_ppu_enable,
2729 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2730 .reset = mv88e6185_g1_reset,
f1394b78 2731 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2732 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2733};
2734
1a3b39ec 2735static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 2736 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2737 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2738 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2739 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2740 .phy_read = mv88e6xxx_g2_smi_phy_read,
2741 .phy_write = mv88e6xxx_g2_smi_phy_write,
2742 .port_set_link = mv88e6xxx_port_set_link,
2743 .port_set_duplex = mv88e6xxx_port_set_duplex,
2744 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2745 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2746 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2747 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2748 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2749 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2750 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2751 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2752 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2753 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2754 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2755 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2756 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2757 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2758 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2759 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2760 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2761 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2762 .reset = mv88e6352_g1_reset,
931d1822
VD		 2763 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2764 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2765 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2766};
2767
2768static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 2769 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2770 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2771 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2772 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2773 .phy_read = mv88e6xxx_g2_smi_phy_read,
2774 .phy_write = mv88e6xxx_g2_smi_phy_write,
2775 .port_set_link = mv88e6xxx_port_set_link,
2776 .port_set_duplex = mv88e6xxx_port_set_duplex,
2777 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2778 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 2779 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2780 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2781 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2782 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2783 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2784 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2785 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2786 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2787 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2788 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2789 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2790 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2791 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2792 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2793 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2794 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2795 .reset = mv88e6352_g1_reset,
931d1822
VD		 2796 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2797 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2798 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2799};
2800
2801static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 2802 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2803 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2804 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2805 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2806 .phy_read = mv88e6xxx_g2_smi_phy_read,
2807 .phy_write = mv88e6xxx_g2_smi_phy_write,
2808 .port_set_link = mv88e6xxx_port_set_link,
2809 .port_set_duplex = mv88e6xxx_port_set_duplex,
2810 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2811 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2812 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2813 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2814 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2815 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2816 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2817 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2818 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2819 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2820 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2821 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2822 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2823 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2824 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2825 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2826 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2827 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2828 .reset = mv88e6352_g1_reset,
931d1822
VD		 2829 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2830 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2831 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2832};
2833
b3469dd8 2834static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 2835 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 2836 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2837 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2838 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2839 .phy_read = mv88e6xxx_g2_smi_phy_read,
2840 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2841 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2842 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2843 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2844 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2845 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2846 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2847 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2848 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2849 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2850 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2851 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2852 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2853 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2854 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2855 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2856 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2857 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2858 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2859 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2860 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2861 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2862 .reset = mv88e6352_g1_reset,
f1394b78 2863 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2864 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2865 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2866};
2867
1a3b39ec 2868static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 2869 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2870 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2871 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2872 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2873 .phy_read = mv88e6xxx_g2_smi_phy_read,
2874 .phy_write = mv88e6xxx_g2_smi_phy_write,
2875 .port_set_link = mv88e6xxx_port_set_link,
2876 .port_set_duplex = mv88e6xxx_port_set_duplex,
2877 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2878 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2879 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2880 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2881 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2882 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2883 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 2884 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 2885 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2886 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2887 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2888 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2889 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2890 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2891 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2892 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2893 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2894 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2895 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2896 .reset = mv88e6352_g1_reset,
931d1822
VD		 2897 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2898 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2899 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2900};
2901
b3469dd8 2902static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 2903 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 2904 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2905 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2906 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2907 .phy_read = mv88e6xxx_g2_smi_phy_read,
2908 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2909 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2910 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2911 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2912 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2913 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2914 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2915 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2916 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2917 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2918 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2919 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2920 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2921 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2922 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2923 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2924 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2925 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2926 .set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 2927 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2928 .reset = mv88e6352_g1_reset,
f1394b78 2929 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2930 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2931};
2932
2933static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 2934 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 2935 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2936 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2937 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2938 .phy_read = mv88e6xxx_g2_smi_phy_read,
2939 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2940 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2941 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2942 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2943 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2944 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2945 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2946 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2947 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2948 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2949 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2950 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2951 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2952 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2953 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2954 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2955 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2956 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2957 .set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 2958 .reset = mv88e6352_g1_reset,
f1394b78 2959 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2960 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2961};
2962
16e329ae
VD		 2963static const struct mv88e6xxx_ops mv88e6341_ops = {
2964 /* MV88E6XXX_FAMILY_6341 */
2965 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2966 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2967 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2968 .phy_read = mv88e6xxx_g2_smi_phy_read,
2969 .phy_write = mv88e6xxx_g2_smi_phy_write,
2970 .port_set_link = mv88e6xxx_port_set_link,
2971 .port_set_duplex = mv88e6xxx_port_set_duplex,
2972 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2973 .port_set_speed = mv88e6390_port_set_speed,
2974 .port_tag_remap = mv88e6095_port_tag_remap,
2975 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2976 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2977 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2978 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 2979 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2980 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 2981 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2982 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2983 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2984 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2985 .stats_get_strings = mv88e6320_stats_get_strings,
2986 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2987 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2988 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 2989 .watchdog_ops = &mv88e6390_watchdog_ops,
2990 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2991 .reset = mv88e6352_g1_reset,
f1394b78 2992 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2993 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
16e329ae
VD		 2994};
2995
b3469dd8 2996static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 2997 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 2998 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2999 .phy_read = mv88e6xxx_g2_smi_phy_read,
3000 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3001 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3002 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3003 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3004 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3005 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3006 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3007 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3008 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3009 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3010 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3011 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3012 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3013 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3014 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3015 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3016 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3017 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3018 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3019 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3020 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3021 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3022 .reset = mv88e6352_g1_reset,
f1394b78 3023 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3024 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3025};
3026
3027static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3028 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3030 .phy_read = mv88e6xxx_g2_smi_phy_read,
3031 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3032 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3033 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3034 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3035 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3036 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3037 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3038 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3039 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3040 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3041 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3042 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3043 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3044 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3045 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3046 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3047 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3048 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3049 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3050 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3051 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3052 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3053 .reset = mv88e6352_g1_reset,
f1394b78 3054 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3055 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3056};
3057
3058static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3059 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3060 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3061 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3062 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3063 .phy_read = mv88e6xxx_g2_smi_phy_read,
3064 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3065 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3066 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3067 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3068 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3069 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3070 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3071 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3072 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3073 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3074 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3075 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3076 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3077 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3078 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3079 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3080 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3081 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3082 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3083 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3084 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3085 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3086 .reset = mv88e6352_g1_reset,
f1394b78 3087 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3088 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 3089 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 3090};
3091
1a3b39ec 3092static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3093 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3094 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3095 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3096 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3097 .phy_read = mv88e6xxx_g2_smi_phy_read,
3098 .phy_write = mv88e6xxx_g2_smi_phy_write,
3099 .port_set_link = mv88e6xxx_port_set_link,
3100 .port_set_duplex = mv88e6xxx_port_set_duplex,
3101 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3102 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3103 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3104 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3105 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3106 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3107 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3108 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3109 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 3110 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3111 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3112 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3113 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3114 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3115 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3116 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3117 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3118 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3119 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3120 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3121 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3122 .reset = mv88e6352_g1_reset,
931d1822
VD		 3123 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3124 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3125 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3126};
3127
3128static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3129 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3130 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3131 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3132 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3133 .phy_read = mv88e6xxx_g2_smi_phy_read,
3134 .phy_write = mv88e6xxx_g2_smi_phy_write,
3135 .port_set_link = mv88e6xxx_port_set_link,
3136 .port_set_duplex = mv88e6xxx_port_set_duplex,
3137 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3138 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3139 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3140 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3141 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3142 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3143 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3144 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3145 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 3146 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3147 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3148 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3149 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3150 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3151 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3152 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3153 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3154 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3155 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3156 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3157 .reset = mv88e6352_g1_reset,
931d1822
VD		 3158 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3159 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3160 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3161};
3162
f81ec90f
VD		 3163static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3164 [MV88E6085] = {
107fcc10 3165 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 3166 .family = MV88E6XXX_FAMILY_6097,
3167 .name = "Marvell 88E6085",
3168 .num_databases = 4096,
3169 .num_ports = 10,
3cf3c846 3170 .max_vid = 4095,
9dddd478 3171 .port_base_addr = 0x10,
a935c052 3172 .global1_addr = 0x1b,
acddbd21 3173 .age_time_coeff = 15000,
dc30c35b 3174 .g1_irqs = 8,
e606ca36 3175 .atu_move_port_mask = 0xf,
f3645652 3176 .pvt = true,
443d5a1b 3177 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3178 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3179 .ops = &mv88e6085_ops,
f81ec90f
VD		 3180 },
3181
3182 [MV88E6095] = {
107fcc10 3183 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 3184 .family = MV88E6XXX_FAMILY_6095,
3185 .name = "Marvell 88E6095/88E6095F",
3186 .num_databases = 256,
3187 .num_ports = 11,
3cf3c846 3188 .max_vid = 4095,
9dddd478 3189 .port_base_addr = 0x10,
a935c052 3190 .global1_addr = 0x1b,
acddbd21 3191 .age_time_coeff = 15000,
dc30c35b 3192 .g1_irqs = 8,
e606ca36 3193 .atu_move_port_mask = 0xf,
443d5a1b 3194 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3195 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3196 .ops = &mv88e6095_ops,
f81ec90f
VD		 3197 },
3198
7d381a02 3199 [MV88E6097] = {
107fcc10 3200 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 3201 .family = MV88E6XXX_FAMILY_6097,
3202 .name = "Marvell 88E6097/88E6097F",
3203 .num_databases = 4096,
3204 .num_ports = 11,
3cf3c846 3205 .max_vid = 4095,
7d381a02
SE		 3206 .port_base_addr = 0x10,
3207 .global1_addr = 0x1b,
3208 .age_time_coeff = 15000,
c534178b 3209 .g1_irqs = 8,
e606ca36 3210 .atu_move_port_mask = 0xf,
f3645652 3211 .pvt = true,
2bfcfcd3 3212 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3213 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3214 .ops = &mv88e6097_ops,
3215 },
3216
f81ec90f 3217 [MV88E6123] = {
107fcc10 3218 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 3219 .family = MV88E6XXX_FAMILY_6165,
3220 .name = "Marvell 88E6123",
3221 .num_databases = 4096,
3222 .num_ports = 3,
3cf3c846 3223 .max_vid = 4095,
9dddd478 3224 .port_base_addr = 0x10,
a935c052 3225 .global1_addr = 0x1b,
acddbd21 3226 .age_time_coeff = 15000,
dc30c35b 3227 .g1_irqs = 9,
e606ca36 3228 .atu_move_port_mask = 0xf,
f3645652 3229 .pvt = true,
5ebe31d7 3230 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3231 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3232 .ops = &mv88e6123_ops,
f81ec90f
VD		 3233 },
3234
3235 [MV88E6131] = {
107fcc10 3236 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 3237 .family = MV88E6XXX_FAMILY_6185,
3238 .name = "Marvell 88E6131",
3239 .num_databases = 256,
3240 .num_ports = 8,
3cf3c846 3241 .max_vid = 4095,
9dddd478 3242 .port_base_addr = 0x10,
a935c052 3243 .global1_addr = 0x1b,
acddbd21 3244 .age_time_coeff = 15000,
dc30c35b 3245 .g1_irqs = 9,
e606ca36 3246 .atu_move_port_mask = 0xf,
443d5a1b 3247 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3248 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3249 .ops = &mv88e6131_ops,
f81ec90f
VD		 3250 },
3251
990e27b0 3252 [MV88E6141] = {
107fcc10 3253 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0
VD		 3254 .family = MV88E6XXX_FAMILY_6341,
3255 .name = "Marvell 88E6341",
3256 .num_databases = 4096,
3257 .num_ports = 6,
3cf3c846 3258 .max_vid = 4095,
990e27b0
VD		 3259 .port_base_addr = 0x10,
3260 .global1_addr = 0x1b,
3261 .age_time_coeff = 3750,
3262 .atu_move_port_mask = 0x1f,
f3645652 3263 .pvt = true,
990e27b0
VD		 3264 .tag_protocol = DSA_TAG_PROTO_EDSA,
3265 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3266 .ops = &mv88e6141_ops,
3267 },
3268
f81ec90f 3269 [MV88E6161] = {
107fcc10 3270 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 3271 .family = MV88E6XXX_FAMILY_6165,
3272 .name = "Marvell 88E6161",
3273 .num_databases = 4096,
3274 .num_ports = 6,
3cf3c846 3275 .max_vid = 4095,
9dddd478 3276 .port_base_addr = 0x10,
a935c052 3277 .global1_addr = 0x1b,
acddbd21 3278 .age_time_coeff = 15000,
dc30c35b 3279 .g1_irqs = 9,
e606ca36 3280 .atu_move_port_mask = 0xf,
f3645652 3281 .pvt = true,
5ebe31d7 3282 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3283 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3284 .ops = &mv88e6161_ops,
f81ec90f
VD		 3285 },
3286
3287 [MV88E6165] = {
107fcc10 3288 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 3289 .family = MV88E6XXX_FAMILY_6165,
3290 .name = "Marvell 88E6165",
3291 .num_databases = 4096,
3292 .num_ports = 6,
3cf3c846 3293 .max_vid = 4095,
9dddd478 3294 .port_base_addr = 0x10,
a935c052 3295 .global1_addr = 0x1b,
acddbd21 3296 .age_time_coeff = 15000,
dc30c35b 3297 .g1_irqs = 9,
e606ca36 3298 .atu_move_port_mask = 0xf,
f3645652 3299 .pvt = true,
443d5a1b 3300 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3301 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3302 .ops = &mv88e6165_ops,
f81ec90f
VD		 3303 },
3304
3305 [MV88E6171] = {
107fcc10 3306 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 3307 .family = MV88E6XXX_FAMILY_6351,
3308 .name = "Marvell 88E6171",
3309 .num_databases = 4096,
3310 .num_ports = 7,
3cf3c846 3311 .max_vid = 4095,
9dddd478 3312 .port_base_addr = 0x10,
a935c052 3313 .global1_addr = 0x1b,
acddbd21 3314 .age_time_coeff = 15000,
dc30c35b 3315 .g1_irqs = 9,
e606ca36 3316 .atu_move_port_mask = 0xf,
f3645652 3317 .pvt = true,
443d5a1b 3318 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3319 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3320 .ops = &mv88e6171_ops,
f81ec90f
VD		 3321 },
3322
3323 [MV88E6172] = {
107fcc10 3324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 3325 .family = MV88E6XXX_FAMILY_6352,
3326 .name = "Marvell 88E6172",
3327 .num_databases = 4096,
3328 .num_ports = 7,
3cf3c846 3329 .max_vid = 4095,
9dddd478 3330 .port_base_addr = 0x10,
a935c052 3331 .global1_addr = 0x1b,
acddbd21 3332 .age_time_coeff = 15000,
dc30c35b 3333 .g1_irqs = 9,
e606ca36 3334 .atu_move_port_mask = 0xf,
f3645652 3335 .pvt = true,
443d5a1b 3336 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3337 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3338 .ops = &mv88e6172_ops,
f81ec90f
VD		 3339 },
3340
3341 [MV88E6175] = {
107fcc10 3342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 3343 .family = MV88E6XXX_FAMILY_6351,
3344 .name = "Marvell 88E6175",
3345 .num_databases = 4096,
3346 .num_ports = 7,
3cf3c846 3347 .max_vid = 4095,
9dddd478 3348 .port_base_addr = 0x10,
a935c052 3349 .global1_addr = 0x1b,
acddbd21 3350 .age_time_coeff = 15000,
dc30c35b 3351 .g1_irqs = 9,
e606ca36 3352 .atu_move_port_mask = 0xf,
f3645652 3353 .pvt = true,
443d5a1b 3354 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3355 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3356 .ops = &mv88e6175_ops,
f81ec90f
VD		 3357 },
3358
3359 [MV88E6176] = {
107fcc10 3360 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 3361 .family = MV88E6XXX_FAMILY_6352,
3362 .name = "Marvell 88E6176",
3363 .num_databases = 4096,
3364 .num_ports = 7,
3cf3c846 3365 .max_vid = 4095,
9dddd478 3366 .port_base_addr = 0x10,
a935c052 3367 .global1_addr = 0x1b,
acddbd21 3368 .age_time_coeff = 15000,
dc30c35b 3369 .g1_irqs = 9,
e606ca36 3370 .atu_move_port_mask = 0xf,
f3645652 3371 .pvt = true,
443d5a1b 3372 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3373 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3374 .ops = &mv88e6176_ops,
f81ec90f
VD		 3375 },
3376
3377 [MV88E6185] = {
107fcc10 3378 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 3379 .family = MV88E6XXX_FAMILY_6185,
3380 .name = "Marvell 88E6185",
3381 .num_databases = 256,
3382 .num_ports = 10,
3cf3c846 3383 .max_vid = 4095,
9dddd478 3384 .port_base_addr = 0x10,
a935c052 3385 .global1_addr = 0x1b,
acddbd21 3386 .age_time_coeff = 15000,
dc30c35b 3387 .g1_irqs = 8,
e606ca36 3388 .atu_move_port_mask = 0xf,
443d5a1b 3389 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3390 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3391 .ops = &mv88e6185_ops,
f81ec90f
VD		 3392 },
3393
1a3b39ec 3394 [MV88E6190] = {
107fcc10 3395 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 3396 .family = MV88E6XXX_FAMILY_6390,
3397 .name = "Marvell 88E6190",
3398 .num_databases = 4096,
3399 .num_ports = 11, /* 10 + Z80 */
931d1822 3400 .max_vid = 8191,
1a3b39ec
AL		 3401 .port_base_addr = 0x0,
3402 .global1_addr = 0x1b,
443d5a1b 3403 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3404 .age_time_coeff = 3750,
1a3b39ec 3405 .g1_irqs = 9,
f3645652 3406 .pvt = true,
e606ca36 3407 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3408 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3409 .ops = &mv88e6190_ops,
3410 },
3411
3412 [MV88E6190X] = {
107fcc10 3413 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 3414 .family = MV88E6XXX_FAMILY_6390,
3415 .name = "Marvell 88E6190X",
3416 .num_databases = 4096,
3417 .num_ports = 11, /* 10 + Z80 */
931d1822 3418 .max_vid = 8191,
1a3b39ec
AL		 3419 .port_base_addr = 0x0,
3420 .global1_addr = 0x1b,
b91e055c 3421 .age_time_coeff = 3750,
1a3b39ec 3422 .g1_irqs = 9,
e606ca36 3423 .atu_move_port_mask = 0x1f,
f3645652 3424 .pvt = true,
443d5a1b 3425 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3426 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3427 .ops = &mv88e6190x_ops,
3428 },
3429
3430 [MV88E6191] = {
107fcc10 3431 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 3432 .family = MV88E6XXX_FAMILY_6390,
3433 .name = "Marvell 88E6191",
3434 .num_databases = 4096,
3435 .num_ports = 11, /* 10 + Z80 */
931d1822 3436 .max_vid = 8191,
1a3b39ec
AL		 3437 .port_base_addr = 0x0,
3438 .global1_addr = 0x1b,
b91e055c 3439 .age_time_coeff = 3750,
443d5a1b 3440 .g1_irqs = 9,
e606ca36 3441 .atu_move_port_mask = 0x1f,
f3645652 3442 .pvt = true,
443d5a1b 3443 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec 3444 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
2cf4cefb 3445 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3446 },
3447
f81ec90f 3448 [MV88E6240] = {
107fcc10 3449 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 3450 .family = MV88E6XXX_FAMILY_6352,
3451 .name = "Marvell 88E6240",
3452 .num_databases = 4096,
3453 .num_ports = 7,
3cf3c846 3454 .max_vid = 4095,
9dddd478 3455 .port_base_addr = 0x10,
a935c052 3456 .global1_addr = 0x1b,
acddbd21 3457 .age_time_coeff = 15000,
dc30c35b 3458 .g1_irqs = 9,
e606ca36 3459 .atu_move_port_mask = 0xf,
f3645652 3460 .pvt = true,
443d5a1b 3461 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3462 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3463 .ops = &mv88e6240_ops,
f81ec90f
VD		 3464 },
3465
1a3b39ec 3466 [MV88E6290] = {
107fcc10 3467 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 3468 .family = MV88E6XXX_FAMILY_6390,
3469 .name = "Marvell 88E6290",
3470 .num_databases = 4096,
3471 .num_ports = 11, /* 10 + Z80 */
931d1822 3472 .max_vid = 8191,
1a3b39ec
AL		 3473 .port_base_addr = 0x0,
3474 .global1_addr = 0x1b,
b91e055c 3475 .age_time_coeff = 3750,
1a3b39ec 3476 .g1_irqs = 9,
e606ca36 3477 .atu_move_port_mask = 0x1f,
f3645652 3478 .pvt = true,
443d5a1b 3479 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3480 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3481 .ops = &mv88e6290_ops,
3482 },
3483
f81ec90f 3484 [MV88E6320] = {
107fcc10 3485 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 3486 .family = MV88E6XXX_FAMILY_6320,
3487 .name = "Marvell 88E6320",
3488 .num_databases = 4096,
3489 .num_ports = 7,
3cf3c846 3490 .max_vid = 4095,
9dddd478 3491 .port_base_addr = 0x10,
a935c052 3492 .global1_addr = 0x1b,
acddbd21 3493 .age_time_coeff = 15000,
dc30c35b 3494 .g1_irqs = 8,
e606ca36 3495 .atu_move_port_mask = 0xf,
f3645652 3496 .pvt = true,
443d5a1b 3497 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3498 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3499 .ops = &mv88e6320_ops,
f81ec90f
VD		 3500 },
3501
3502 [MV88E6321] = {
107fcc10 3503 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 3504 .family = MV88E6XXX_FAMILY_6320,
3505 .name = "Marvell 88E6321",
3506 .num_databases = 4096,
3507 .num_ports = 7,
3cf3c846 3508 .max_vid = 4095,
9dddd478 3509 .port_base_addr = 0x10,
a935c052 3510 .global1_addr = 0x1b,
acddbd21 3511 .age_time_coeff = 15000,
dc30c35b 3512 .g1_irqs = 8,
e606ca36 3513 .atu_move_port_mask = 0xf,
443d5a1b 3514 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3515 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3516 .ops = &mv88e6321_ops,
f81ec90f
VD		 3517 },
3518
a75961d0 3519 [MV88E6341] = {
107fcc10 3520 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 3521 .family = MV88E6XXX_FAMILY_6341,
3522 .name = "Marvell 88E6341",
3523 .num_databases = 4096,
3524 .num_ports = 6,
3cf3c846 3525 .max_vid = 4095,
a75961d0
GC		 3526 .port_base_addr = 0x10,
3527 .global1_addr = 0x1b,
3528 .age_time_coeff = 3750,
e606ca36 3529 .atu_move_port_mask = 0x1f,
f3645652 3530 .pvt = true,
a75961d0
GC		 3531 .tag_protocol = DSA_TAG_PROTO_EDSA,
3532 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3533 .ops = &mv88e6341_ops,
3534 },
3535
f81ec90f 3536 [MV88E6350] = {
107fcc10 3537 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 3538 .family = MV88E6XXX_FAMILY_6351,
3539 .name = "Marvell 88E6350",
3540 .num_databases = 4096,
3541 .num_ports = 7,
3cf3c846 3542 .max_vid = 4095,
9dddd478 3543 .port_base_addr = 0x10,
a935c052 3544 .global1_addr = 0x1b,
acddbd21 3545 .age_time_coeff = 15000,
dc30c35b 3546 .g1_irqs = 9,
e606ca36 3547 .atu_move_port_mask = 0xf,
f3645652 3548 .pvt = true,
443d5a1b 3549 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3550 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3551 .ops = &mv88e6350_ops,
f81ec90f
VD		 3552 },
3553
3554 [MV88E6351] = {
107fcc10 3555 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 3556 .family = MV88E6XXX_FAMILY_6351,
3557 .name = "Marvell 88E6351",
3558 .num_databases = 4096,
3559 .num_ports = 7,
3cf3c846 3560 .max_vid = 4095,
9dddd478 3561 .port_base_addr = 0x10,
a935c052 3562 .global1_addr = 0x1b,
acddbd21 3563 .age_time_coeff = 15000,
dc30c35b 3564 .g1_irqs = 9,
e606ca36 3565 .atu_move_port_mask = 0xf,
f3645652 3566 .pvt = true,
443d5a1b 3567 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3568 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3569 .ops = &mv88e6351_ops,
f81ec90f
VD		 3570 },
3571
3572 [MV88E6352] = {
107fcc10 3573 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 3574 .family = MV88E6XXX_FAMILY_6352,
3575 .name = "Marvell 88E6352",
3576 .num_databases = 4096,
3577 .num_ports = 7,
3cf3c846 3578 .max_vid = 4095,
9dddd478 3579 .port_base_addr = 0x10,
a935c052 3580 .global1_addr = 0x1b,
acddbd21 3581 .age_time_coeff = 15000,
dc30c35b 3582 .g1_irqs = 9,
e606ca36 3583 .atu_move_port_mask = 0xf,
f3645652 3584 .pvt = true,
443d5a1b 3585 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3586 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3587 .ops = &mv88e6352_ops,
f81ec90f 3588 },
1a3b39ec 3589 [MV88E6390] = {
107fcc10 3590 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 3591 .family = MV88E6XXX_FAMILY_6390,
3592 .name = "Marvell 88E6390",
3593 .num_databases = 4096,
3594 .num_ports = 11, /* 10 + Z80 */
931d1822 3595 .max_vid = 8191,
1a3b39ec
AL		 3596 .port_base_addr = 0x0,
3597 .global1_addr = 0x1b,
b91e055c 3598 .age_time_coeff = 3750,
1a3b39ec 3599 .g1_irqs = 9,
e606ca36 3600 .atu_move_port_mask = 0x1f,
f3645652 3601 .pvt = true,
443d5a1b 3602 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3603 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3604 .ops = &mv88e6390_ops,
3605 },
3606 [MV88E6390X] = {
107fcc10 3607 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 3608 .family = MV88E6XXX_FAMILY_6390,
3609 .name = "Marvell 88E6390X",
3610 .num_databases = 4096,
3611 .num_ports = 11, /* 10 + Z80 */
931d1822 3612 .max_vid = 8191,
1a3b39ec
AL		 3613 .port_base_addr = 0x0,
3614 .global1_addr = 0x1b,
b91e055c 3615 .age_time_coeff = 3750,
1a3b39ec 3616 .g1_irqs = 9,
e606ca36 3617 .atu_move_port_mask = 0x1f,
f3645652 3618 .pvt = true,
443d5a1b 3619 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3620 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3621 .ops = &mv88e6390x_ops,
3622 },
f81ec90f
VD		 3623};
3624
5f7c0367 3625static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3626{
a439c061 3627 int i;
b9b37713 3628
5f7c0367
VD		 3629 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3630 if (mv88e6xxx_table[i].prod_num == prod_num)
3631 return &mv88e6xxx_table[i];
b9b37713 3632
b9b37713
VD		 3633 return NULL;
3634}
3635
fad09c73 3636static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3637{
3638 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3639 unsigned int prod_num, rev;
3640 u16 id;
3641 int err;
bc46a3d5 3642
8f6345b2 3643 mutex_lock(&chip->reg_lock);
107fcc10 3644 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
8f6345b2
VD		 3645 mutex_unlock(&chip->reg_lock);
3646 if (err)
3647 return err;
bc46a3d5 3648
107fcc10
VD		 3649 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3650 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 3651
3652 info = mv88e6xxx_lookup_info(prod_num);
3653 if (!info)
3654 return -ENODEV;
3655
caac8545 3656 /* Update the compatible info with the probed one */
fad09c73 3657 chip->info = info;
bc46a3d5 3658
ca070c10
VD		 3659 err = mv88e6xxx_g2_require(chip);
3660 if (err)
3661 return err;
3662
fad09c73
VD		 3663 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3664 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3665
3666 return 0;
3667}
3668
fad09c73 3669static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3670{
fad09c73 3671 struct mv88e6xxx_chip *chip;
469d729f 3672
fad09c73
VD		 3673 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3674 if (!chip)
469d729f
VD		 3675 return NULL;
3676
fad09c73 3677 chip->dev = dev;
469d729f 3678
fad09c73 3679 mutex_init(&chip->reg_lock);
a3c53be5 3680 INIT_LIST_HEAD(&chip->mdios);
469d729f 3681
fad09c73 3682 return chip;
469d729f
VD		 3683}
3684
fad09c73 3685static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3686 struct mii_bus *bus, int sw_addr)
3687{
914b32f6 3688 if (sw_addr == 0)
fad09c73 3689 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3690 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3691 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3692 else
3693 return -EINVAL;
3694
fad09c73
VD		 3695 chip->bus = bus;
3696 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3697
3698 return 0;
3699}
3700
7b314362
AL		 3701static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3702{
04bed143 3703 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 3704
443d5a1b 3705 return chip->info->tag_protocol;
7b314362
AL		 3706}
3707
fcdce7d0
AL		 3708static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3709 struct device *host_dev, int sw_addr,
3710 void **priv)
a77d43f1 3711{
fad09c73 3712 struct mv88e6xxx_chip *chip;
a439c061 3713 struct mii_bus *bus;
b516d453 3714 int err;
a77d43f1 3715
a439c061 3716 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3717 if (!bus)
3718 return NULL;
3719
fad09c73
VD		 3720 chip = mv88e6xxx_alloc_chip(dsa_dev);
3721 if (!chip)
469d729f
VD		 3722 return NULL;
3723
caac8545 3724 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3725 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3726
fad09c73 3727 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3728 if (err)
3729 goto free;
3730
fad09c73 3731 err = mv88e6xxx_detect(chip);
bc46a3d5 3732 if (err)
469d729f 3733 goto free;
a439c061 3734
dc30c35b
AL		 3735 mutex_lock(&chip->reg_lock);
3736 err = mv88e6xxx_switch_reset(chip);
3737 mutex_unlock(&chip->reg_lock);
3738 if (err)
3739 goto free;
3740
e57e5e77
VD		 3741 mv88e6xxx_phy_init(chip);
3742
a3c53be5 3743 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 3744 if (err)
469d729f 3745 goto free;
b516d453 3746
fad09c73 3747 *priv = chip;
a439c061 3748
fad09c73 3749 return chip->info->name;
469d729f 3750free:
fad09c73 3751 devm_kfree(dsa_dev, chip);
469d729f
VD		 3752
3753 return NULL;
a77d43f1
AL		 3754}
3755
7df8fbdd
VD		 3756static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3757 const struct switchdev_obj_port_mdb *mdb,
3758 struct switchdev_trans *trans)
3759{
3760 /* We don't need any dynamic resource from the kernel (yet),
3761 * so skip the prepare phase.
3762 */
3763
3764 return 0;
3765}
3766
3767static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3768 const struct switchdev_obj_port_mdb *mdb,
3769 struct switchdev_trans *trans)
3770{
04bed143 3771 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3772
3773 mutex_lock(&chip->reg_lock);
3774 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3775 GLOBAL_ATU_DATA_STATE_MC_STATIC))
774439e5
VD		 3776 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3777 port);
7df8fbdd
VD		 3778 mutex_unlock(&chip->reg_lock);
3779}
3780
3781static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3782 const struct switchdev_obj_port_mdb *mdb)
3783{
04bed143 3784 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3785 int err;
3786
3787 mutex_lock(&chip->reg_lock);
3788 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3789 GLOBAL_ATU_DATA_STATE_UNUSED);
3790 mutex_unlock(&chip->reg_lock);
3791
3792 return err;
3793}
3794
3795static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3796 struct switchdev_obj_port_mdb *mdb,
438ff537 3797 switchdev_obj_dump_cb_t *cb)
7df8fbdd 3798{
04bed143 3799 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3800 int err;
3801
3802 mutex_lock(&chip->reg_lock);
3803 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3804 mutex_unlock(&chip->reg_lock);
3805
3806 return err;
3807}
3808
a82f67af 3809static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3810 .probe = mv88e6xxx_drv_probe,
7b314362 3811 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3812 .setup = mv88e6xxx_setup,
3813 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3814 .adjust_link = mv88e6xxx_adjust_link,
3815 .get_strings = mv88e6xxx_get_strings,
3816 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3817 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 3818 .port_enable = mv88e6xxx_port_enable,
3819 .port_disable = mv88e6xxx_port_disable,
f81ec90f
VD		 3820 .set_eee = mv88e6xxx_set_eee,
3821 .get_eee = mv88e6xxx_get_eee,
f8cd8753 3822 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3823 .get_eeprom = mv88e6xxx_get_eeprom,
3824 .set_eeprom = mv88e6xxx_set_eeprom,
3825 .get_regs_len = mv88e6xxx_get_regs_len,
3826 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3827 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3828 .port_bridge_join = mv88e6xxx_port_bridge_join,
3829 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3830 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3831 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3832 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3833 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3834 .port_vlan_add = mv88e6xxx_port_vlan_add,
3835 .port_vlan_del = mv88e6xxx_port_vlan_del,
3836 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3837 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3838 .port_fdb_add = mv88e6xxx_port_fdb_add,
3839 .port_fdb_del = mv88e6xxx_port_fdb_del,
3840 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3841 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3842 .port_mdb_add = mv88e6xxx_port_mdb_add,
3843 .port_mdb_del = mv88e6xxx_port_mdb_del,
3844 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
aec5ac88
VD		 3845 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3846 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 3847};
3848
ab3d408d
FF		 3849static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3850 .ops = &mv88e6xxx_switch_ops,
3851};
3852
55ed0ce0 3853static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3854{
fad09c73 3855 struct device *dev = chip->dev;
b7e66a5f
VD		 3856 struct dsa_switch *ds;
3857
73b1204d 3858 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 3859 if (!ds)
3860 return -ENOMEM;
3861
fad09c73 3862 ds->priv = chip;
9d490b4e 3863 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 3864 ds->ageing_time_min = chip->info->age_time_coeff;
3865 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 3866
3867 dev_set_drvdata(dev, ds);
3868
23c9ee49 3869 return dsa_register_switch(ds);
b7e66a5f
VD		 3870}
3871
fad09c73 3872static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3873{
fad09c73 3874 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3875}
3876
57d32310 3877static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3878{
14c7b3c3 3879 struct device *dev = &mdiodev->dev;
f8cd8753 3880 struct device_node *np = dev->of_node;
caac8545 3881 const struct mv88e6xxx_info *compat_info;
fad09c73 3882 struct mv88e6xxx_chip *chip;
f8cd8753 3883 u32 eeprom_len;
52638f71 3884 int err;
14c7b3c3 3885
caac8545
VD		 3886 compat_info = of_device_get_match_data(dev);
3887 if (!compat_info)
3888 return -EINVAL;
3889
fad09c73
VD		 3890 chip = mv88e6xxx_alloc_chip(dev);
3891 if (!chip)
14c7b3c3
AL		 3892 return -ENOMEM;
3893
fad09c73 3894 chip->info = compat_info;
caac8545 3895
fad09c73 3896 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3897 if (err)
3898 return err;
14c7b3c3 3899
b4308f04
AL		 3900 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
3901 if (IS_ERR(chip->reset))
3902 return PTR_ERR(chip->reset);
3903
fad09c73 3904 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3905 if (err)
3906 return err;
14c7b3c3 3907
e57e5e77
VD		 3908 mv88e6xxx_phy_init(chip);
3909
ee4dc2e7 3910 if (chip->info->ops->get_eeprom &&
f8cd8753 3911 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3912 chip->eeprom_len = eeprom_len;
f8cd8753 3913
dc30c35b
AL		 3914 mutex_lock(&chip->reg_lock);
3915 err = mv88e6xxx_switch_reset(chip);
3916 mutex_unlock(&chip->reg_lock);
3917 if (err)
3918 goto out;
3919
3920 chip->irq = of_irq_get(np, 0);
3921 if (chip->irq == -EPROBE_DEFER) {
3922 err = chip->irq;
3923 goto out;
3924 }
3925
3926 if (chip->irq > 0) {
3927 /* Has to be performed before the MDIO bus is created,
3928 * because the PHYs will link there interrupts to these
3929 * interrupt controllers
3930 */
3931 mutex_lock(&chip->reg_lock);
3932 err = mv88e6xxx_g1_irq_setup(chip);
3933 mutex_unlock(&chip->reg_lock);
3934
3935 if (err)
3936 goto out;
3937
3938 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
3939 err = mv88e6xxx_g2_irq_setup(chip);
3940 if (err)
3941 goto out_g1_irq;
3942 }
3943 }
3944
a3c53be5 3945 err = mv88e6xxx_mdios_register(chip, np);
b516d453 3946 if (err)
dc30c35b 3947 goto out_g2_irq;
b516d453 3948
55ed0ce0 3949 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 3950 if (err)
3951 goto out_mdio;
83c0afae 3952
98e67308 3953 return 0;
dc30c35b
AL		 3954
3955out_mdio:
a3c53be5 3956 mv88e6xxx_mdios_unregister(chip);
dc30c35b 3957out_g2_irq:
46712644 3958 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 3959 mv88e6xxx_g2_irq_free(chip);
3960out_g1_irq:
61f7c3f8
AL		 3961 if (chip->irq > 0) {
3962 mutex_lock(&chip->reg_lock);
46712644 3963 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 3964 mutex_unlock(&chip->reg_lock);
3965 }
dc30c35b
AL		 3966out:
3967 return err;
98e67308 3968}
14c7b3c3
AL		 3969
3970static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3971{
3972 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 3973 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 3974
930188ce 3975 mv88e6xxx_phy_destroy(chip);
fad09c73 3976 mv88e6xxx_unregister_switch(chip);
a3c53be5 3977 mv88e6xxx_mdios_unregister(chip);
dc30c35b 3978
46712644
AL		 3979 if (chip->irq > 0) {
3980 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
3981 mv88e6xxx_g2_irq_free(chip);
3982 mv88e6xxx_g1_irq_free(chip);
3983 }
14c7b3c3
AL		 3984}
3985
3986static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 3987 {
3988 .compatible = "marvell,mv88e6085",
3989 .data = &mv88e6xxx_table[MV88E6085],
3990 },
1a3b39ec
AL		 3991 {
3992 .compatible = "marvell,mv88e6190",
3993 .data = &mv88e6xxx_table[MV88E6190],
3994 },
14c7b3c3
AL		 3995 { /* sentinel */ },
3996};
3997
3998MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3999
4000static struct mdio_driver mv88e6xxx_driver = {
4001 .probe = mv88e6xxx_probe,
4002 .remove = mv88e6xxx_remove,
4003 .mdiodrv.driver = {
4004 .name = "mv88e6085",
4005 .of_match_table = mv88e6xxx_of_match,
4006 },
4007};
4008
4009static int __init mv88e6xxx_init(void)
4010{
ab3d408d 4011 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4012 return mdio_driver_register(&mv88e6xxx_driver);
4013}
98e67308
BH		 4014module_init(mv88e6xxx_init);
4015
4016static void __exit mv88e6xxx_cleanup(void)
4017{
14c7b3c3 4018 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4019 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4020}
4021module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4022
4023MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4024MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4025MODULE_LICENSE("GPL");
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