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net: dsa: mv88e6xxx: enable ATU Learn2All
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
ee26a228
AL		 225static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
226 struct mii_bus *bus,
227 int addr, int reg, u16 *val)
efb3e74d
AL		 228{
229 return mv88e6xxx_read(chip, addr, reg, val);
230}
231
ee26a228
AL		 232static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
233 struct mii_bus *bus,
234 int addr, int reg, u16 val)
efb3e74d
AL		 235{
236 return mv88e6xxx_write(chip, addr, reg, val);
237}
238
a3c53be5
AL		 239static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
240{
241 struct mv88e6xxx_mdio_bus *mdio_bus;
242
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
244 list);
245 if (!mdio_bus)
246 return NULL;
247
248 return mdio_bus->bus;
249}
250
e57e5e77
VD		 251static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
252 int reg, u16 *val)
253{
254 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 255 struct mii_bus *bus;
e57e5e77 256
a3c53be5
AL		 257 bus = mv88e6xxx_default_mdio_bus(chip);
258 if (!bus)
e57e5e77
VD		 259 return -EOPNOTSUPP;
260
a3c53be5 261 if (!chip->info->ops->phy_read)
ee26a228
AL		 262 return -EOPNOTSUPP;
263
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
e57e5e77
VD		 265}
266
267static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
268 int reg, u16 val)
269{
270 int addr = phy; /* PHY devices addresses start at 0x0 */
a3c53be5 271 struct mii_bus *bus;
e57e5e77 272
a3c53be5
AL		 273 bus = mv88e6xxx_default_mdio_bus(chip);
274 if (!bus)
e57e5e77
VD		 275 return -EOPNOTSUPP;
276
a3c53be5 277 if (!chip->info->ops->phy_write)
ee26a228
AL		 278 return -EOPNOTSUPP;
279
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
e57e5e77
VD		 281}
282
09cb7dfd
VD		 283static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
284{
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
286 return -EOPNOTSUPP;
287
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
289}
290
291static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
292{
293 int err;
294
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
297 if (unlikely(err)) {
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
299 phy, err);
300 }
301}
302
303static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
305{
306 int err;
307
308 /* There is no paging for registers 22 */
309 if (reg == PHY_PAGE)
310 return -EINVAL;
311
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
313 if (!err) {
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
316 }
317
318 return err;
319}
320
321static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
323{
324 int err;
325
326 /* There is no paging for registers 22 */
327 if (reg == PHY_PAGE)
328 return -EINVAL;
329
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
331 if (!err) {
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
334 }
335
336 return err;
337}
338
339static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
340{
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
342 reg, val);
343}
344
345static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
346{
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 reg, val);
349}
350
dc30c35b
AL		 351static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
352{
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
355
356 chip->g1_irq.masked |= (1 << n);
357}
358
359static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
360{
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
363
364 chip->g1_irq.masked &= ~(1 << n);
365}
366
367static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
368{
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
372 unsigned int n;
373 u16 reg;
374 int err;
375
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
378 mutex_unlock(&chip->reg_lock);
379
380 if (err)
381 goto out;
382
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
387 ++nhandled;
388 }
389 }
390out:
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
392}
393
394static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
395{
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
397
398 mutex_lock(&chip->reg_lock);
399}
400
401static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
402{
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
405 u16 reg;
406 int err;
407
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
409 if (err)
410 goto out;
411
412 reg &= ~mask;
413 reg |= (~chip->g1_irq.masked & mask);
414
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
416 if (err)
417 goto out;
418
419out:
420 mutex_unlock(&chip->reg_lock);
421}
422
423static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
429};
430
431static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
432 unsigned int irq,
433 irq_hw_number_t hwirq)
434{
435 struct mv88e6xxx_chip *chip = d->host_data;
436
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
440
441 return 0;
442}
443
444static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
447};
448
449static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
450{
451 int irq, virq;
3460a577
AL		 452 u16 mask;
453
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457
458 free_irq(chip->irq, chip);
dc30c35b 459
5edef2f2 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 462 irq_dispose_mapping(virq);
463 }
464
a3db3d3a 465 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 466}
467
468static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
469{
3dd0ef05
AL		 470 int err, irq, virq;
471 u16 reg, mask;
dc30c35b
AL		 472
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
478 return -ENOMEM;
479
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
482
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
485
3dd0ef05 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
dc30c35b 487 if (err)
3dd0ef05 488 goto out_mapping;
dc30c35b 489
3dd0ef05 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 491
3dd0ef05 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
dc30c35b 493 if (err)
3dd0ef05 494 goto out_disable;
dc30c35b
AL		 495
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
498 if (err)
3dd0ef05 499 goto out_disable;
dc30c35b
AL		 500
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
505 if (err)
3dd0ef05 506 goto out_disable;
dc30c35b
AL		 507
508 return 0;
509
3dd0ef05
AL		 510out_disable:
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
513
514out_mapping:
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
518 }
519
520 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 521
522 return err;
523}
524
ec561276 525int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 526{
6441e669 527 int i;
2d79af6e 528
6441e669 529 for (i = 0; i < 16; i++) {
2d79af6e
VD		 530 u16 val;
531 int err;
532
533 err = mv88e6xxx_read(chip, addr, reg, &val);
534 if (err)
535 return err;
536
537 if (!(val & mask))
538 return 0;
539
540 usleep_range(1000, 2000);
541 }
542
30853553 543 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 544 return -ETIMEDOUT;
545}
546
f22ab641 547/* Indirect write to single pointer-data register with an Update bit */
ec561276 548int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 549{
550 u16 val;
0f02b4f7 551 int err;
f22ab641
VD		 552
553 /* Wait until the previous operation is completed */
0f02b4f7
AL		 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
555 if (err)
556 return err;
f22ab641
VD		 557
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
560
561 return mv88e6xxx_write(chip, addr, reg, val);
562}
563
a935c052 564static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6 565{
a199d8b6
VD		 566 if (!chip->info->ops->ppu_disable)
567 return 0;
2e5f0320 568
a199d8b6 569 return chip->info->ops->ppu_disable(chip);
2e5f0320
LB		 570}
571
fad09c73 572static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 573{
a199d8b6
VD		 574 if (!chip->info->ops->ppu_enable)
575 return 0;
2e5f0320 576
a199d8b6 577 return chip->info->ops->ppu_enable(chip);
2e5f0320
LB		 578}
579
580static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
581{
fad09c73 582 struct mv88e6xxx_chip *chip;
2e5f0320 583
fad09c73 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 585
fad09c73 586 mutex_lock(&chip->reg_lock);
762eb67b 587
fad09c73
VD		 588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
2e5f0320 592 }
762eb67b 593
fad09c73 594 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 595}
596
597static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
598{
fad09c73 599 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 600
fad09c73 601 schedule_work(&chip->ppu_work);
2e5f0320
LB		 602}
603
fad09c73 604static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 605{
2e5f0320
LB		 606 int ret;
607
fad09c73 608 mutex_lock(&chip->ppu_mutex);
2e5f0320 609
3675c8d7 610 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
613 * it.
614 */
fad09c73
VD		 615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
85686581 617 if (ret < 0) {
fad09c73 618 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 619 return ret;
620 }
fad09c73 621 chip->ppu_disabled = 1;
2e5f0320 622 } else {
fad09c73 623 del_timer(&chip->ppu_timer);
85686581 624 ret = 0;
2e5f0320
LB		 625 }
626
627 return ret;
628}
629
fad09c73 630static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 631{
3675c8d7 632 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 635}
636
fad09c73 637static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 638{
fad09c73
VD		 639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
2e5f0320
LB		 643}
644
930188ce
AL		 645static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
646{
647 del_timer_sync(&chip->ppu_timer);
648}
649
ee26a228
AL		 650static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
651 struct mii_bus *bus,
652 int addr, int reg, u16 *val)
2e5f0320 653{
e57e5e77 654 int err;
2e5f0320 655
e57e5e77
VD		 656 err = mv88e6xxx_ppu_access_get(chip);
657 if (!err) {
658 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 659 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 660 }
661
e57e5e77 662 return err;
2e5f0320
LB		 663}
664
ee26a228
AL		 665static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
666 struct mii_bus *bus,
667 int addr, int reg, u16 val)
2e5f0320 668{
e57e5e77 669 int err;
2e5f0320 670
e57e5e77
VD		 671 err = mv88e6xxx_ppu_access_get(chip);
672 if (!err) {
673 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 674 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 675 }
676
e57e5e77 677 return err;
2e5f0320 678}
2e5f0320 679
fad09c73 680static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 681{
fad09c73 682 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 683}
684
fad09c73 685static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 686{
fad09c73 687 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 688}
689
fad09c73 690static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 691{
fad09c73 692 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 693}
694
a75961d0
GC		 695static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
696{
697 return chip->info->family == MV88E6XXX_FAMILY_6341;
698}
699
fad09c73 700static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 701{
fad09c73 702 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 703}
704
fad09c73 705static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 706{
fad09c73 707 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 708}
709
d78343d2
VD		 710static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
711 int link, int speed, int duplex,
712 phy_interface_t mode)
713{
714 int err;
715
716 if (!chip->info->ops->port_set_link)
717 return 0;
718
719 /* Port's MAC control must not be changed unless the link is down */
720 err = chip->info->ops->port_set_link(chip, port, 0);
721 if (err)
722 return err;
723
724 if (chip->info->ops->port_set_speed) {
725 err = chip->info->ops->port_set_speed(chip, port, speed);
726 if (err && err != -EOPNOTSUPP)
727 goto restore_link;
728 }
729
730 if (chip->info->ops->port_set_duplex) {
731 err = chip->info->ops->port_set_duplex(chip, port, duplex);
732 if (err && err != -EOPNOTSUPP)
733 goto restore_link;
734 }
735
736 if (chip->info->ops->port_set_rgmii_delay) {
737 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
738 if (err && err != -EOPNOTSUPP)
739 goto restore_link;
740 }
741
f39908d3
AL		 742 if (chip->info->ops->port_set_cmode) {
743 err = chip->info->ops->port_set_cmode(chip, port, mode);
744 if (err && err != -EOPNOTSUPP)
745 goto restore_link;
746 }
747
d78343d2
VD		 748 err = 0;
749restore_link:
750 if (chip->info->ops->port_set_link(chip, port, link))
751 netdev_err(chip->ds->ports[port].netdev,
752 "failed to restore MAC's link\n");
753
754 return err;
755}
756
dea87024
AL		 757/* We expect the switch to perform auto negotiation if there is a real
758 * phy. However, in the case of a fixed link phy, we force the port
759 * settings from the fixed link settings.
760 */
f81ec90f
VD		 761static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
762 struct phy_device *phydev)
dea87024 763{
04bed143 764 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 765 int err;
dea87024
AL		 766
767 if (!phy_is_pseudo_fixed_link(phydev))
768 return;
769
fad09c73 770 mutex_lock(&chip->reg_lock);
d78343d2
VD		 771 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
772 phydev->duplex, phydev->interface);
fad09c73 773 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 774
775 if (err && err != -EOPNOTSUPP)
776 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 777}
778
a605a0fe 779static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 780{
a605a0fe
AL		 781 if (!chip->info->ops->stats_snapshot)
782 return -EOPNOTSUPP;
91da11f8 783
a605a0fe 784 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 785}
786
e413e7e1 787static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 788 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
789 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
790 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
791 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
792 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
793 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
794 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
795 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
796 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
797 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
798 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
799 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
800 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
801 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
802 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
803 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
804 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
805 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
806 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
807 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
808 { "single", 4, 0x14, STATS_TYPE_BANK0, },
809 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
810 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
811 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
812 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
813 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
814 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
815 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
816 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
817 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
818 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
819 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
820 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
821 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
822 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
823 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
824 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
826 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
828 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
829 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
830 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
831 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
832 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
833 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
834 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
835 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
836 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
837 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
838 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
839 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
840 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
841 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
842 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
843 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
844 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
845 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
846 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 847};
848
fad09c73 849static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 850 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 851 int port, u16 bank1_select,
852 u16 histogram)
80c4627b 853{
80c4627b
AL		 854 u32 low;
855 u32 high = 0;
dfafe449 856 u16 reg = 0;
0e7b9925 857 int err;
80c4627b
AL		 858 u64 value;
859
f5e2ed02 860 switch (s->type) {
dfafe449 861 case STATS_TYPE_PORT:
0e7b9925
AL		 862 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
863 if (err)
80c4627b
AL		 864 return UINT64_MAX;
865
0e7b9925 866 low = reg;
80c4627b 867 if (s->sizeof_stat == 4) {
0e7b9925
AL		 868 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
869 if (err)
80c4627b 870 return UINT64_MAX;
0e7b9925 871 high = reg;
80c4627b 872 }
f5e2ed02 873 break;
dfafe449 874 case STATS_TYPE_BANK1:
e0d8b615 875 reg = bank1_select;
dfafe449
AL		 876 /* fall through */
877 case STATS_TYPE_BANK0:
e0d8b615 878 reg |= s->reg | histogram;
7f9ef3af 879 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 880 if (s->sizeof_stat == 8)
7f9ef3af 881 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
80c4627b
AL		 882 }
883 value = (((u64)high) << 16) | low;
884 return value;
885}
886
dfafe449
AL		 887static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
888 uint8_t *data, int types)
91da11f8 889{
f5e2ed02
AL		 890 struct mv88e6xxx_hw_stat *stat;
891 int i, j;
91da11f8 892
f5e2ed02
AL		 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 stat = &mv88e6xxx_hw_stats[i];
dfafe449 895 if (stat->type & types) {
f5e2ed02
AL		 896 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
897 ETH_GSTRING_LEN);
898 j++;
899 }
91da11f8 900 }
e413e7e1
AL		 901}
902
dfafe449
AL		 903static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
904 uint8_t *data)
905{
906 mv88e6xxx_stats_get_strings(chip, data,
907 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
908}
909
910static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
911 uint8_t *data)
912{
913 mv88e6xxx_stats_get_strings(chip, data,
914 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
915}
916
917static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
918 uint8_t *data)
e413e7e1 919{
04bed143 920 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 921
922 if (chip->info->ops->stats_get_strings)
923 chip->info->ops->stats_get_strings(chip, data);
924}
925
926static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
927 int types)
928{
f5e2ed02
AL		 929 struct mv88e6xxx_hw_stat *stat;
930 int i, j;
931
932 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
933 stat = &mv88e6xxx_hw_stats[i];
dfafe449 934 if (stat->type & types)
f5e2ed02
AL		 935 j++;
936 }
937 return j;
e413e7e1
AL		 938}
939
dfafe449
AL		 940static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
941{
942 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
943 STATS_TYPE_PORT);
944}
945
946static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
947{
948 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
949 STATS_TYPE_BANK1);
950}
951
952static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
953{
954 struct mv88e6xxx_chip *chip = ds->priv;
955
956 if (chip->info->ops->stats_get_sset_count)
957 return chip->info->ops->stats_get_sset_count(chip);
958
959 return 0;
960}
961
052f947f 962static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 963 uint64_t *data, int types,
964 u16 bank1_select, u16 histogram)
052f947f
AL		 965{
966 struct mv88e6xxx_hw_stat *stat;
967 int i, j;
968
969 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
970 stat = &mv88e6xxx_hw_stats[i];
971 if (stat->type & types) {
e0d8b615
AL		 972 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
973 bank1_select,
974 histogram);
052f947f
AL		 975 j++;
976 }
977 }
978}
979
980static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
981 uint64_t *data)
982{
983 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 984 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
985 0, GLOBAL_STATS_OP_HIST_RX_TX);
052f947f
AL		 986}
987
988static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
989 uint64_t *data)
990{
991 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615
AL		 992 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
993 GLOBAL_STATS_OP_BANK_1_BIT_9,
994 GLOBAL_STATS_OP_HIST_RX_TX);
995}
996
997static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
998 uint64_t *data)
999{
1000 return mv88e6xxx_stats_get_stats(chip, port, data,
1001 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1002 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
052f947f
AL		 1003}
1004
1005static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1006 uint64_t *data)
1007{
1008 if (chip->info->ops->stats_get_stats)
1009 chip->info->ops->stats_get_stats(chip, port, data);
1010}
1011
f81ec90f
VD		 1012static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1013 uint64_t *data)
e413e7e1 1014{
04bed143 1015 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1016 int ret;
f5e2ed02 1017
fad09c73 1018 mutex_lock(&chip->reg_lock);
f5e2ed02 1019
a605a0fe 1020 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 1021 if (ret < 0) {
fad09c73 1022 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 1023 return;
1024 }
052f947f
AL		 1025
1026 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1027
fad09c73 1028 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1029}
1030
de227387
AL		 1031static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1032{
1033 if (chip->info->ops->stats_set_histogram)
1034 return chip->info->ops->stats_set_histogram(chip);
1035
1036 return 0;
1037}
1038
f81ec90f 1039static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1040{
1041 return 32 * sizeof(u16);
1042}
1043
f81ec90f
VD		 1044static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1045 struct ethtool_regs *regs, void *_p)
a1ab91f3 1046{
04bed143 1047 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1048 int err;
1049 u16 reg;
a1ab91f3
GR		 1050 u16 *p = _p;
1051 int i;
1052
1053 regs->version = 0;
1054
1055 memset(p, 0xff, 32 * sizeof(u16));
1056
fad09c73 1057 mutex_lock(&chip->reg_lock);
23062513 1058
a1ab91f3 1059 for (i = 0; i < 32; i++) {
a1ab91f3 1060
0e7b9925
AL		 1061 err = mv88e6xxx_port_read(chip, port, i, &reg);
1062 if (!err)
1063 p[i] = reg;
a1ab91f3 1064 }
23062513 1065
fad09c73 1066 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1067}
1068
fad09c73 1069static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1070{
a935c052 1071 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1072}
1073
f81ec90f
VD		 1074static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1075 struct ethtool_eee *e)
11b3b45d 1076{
04bed143 1077 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1078 u16 reg;
1079 int err;
11b3b45d 1080
fad09c73 1081 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1082 return -EOPNOTSUPP;
1083
fad09c73 1084 mutex_lock(&chip->reg_lock);
2f40c698 1085
9c93829c
VD		 1086 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1087 if (err)
2f40c698 1088 goto out;
11b3b45d
GR		 1089
1090 e->eee_enabled = !!(reg & 0x0200);
1091 e->tx_lpi_enabled = !!(reg & 0x0100);
1092
0e7b9925 1093 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1094 if (err)
2f40c698 1095 goto out;
11b3b45d 1096
cca8b133 1097 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1098out:
fad09c73 1099 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1100
1101 return err;
11b3b45d
GR		 1102}
1103
f81ec90f
VD		 1104static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1105 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1106{
04bed143 1107 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1108 u16 reg;
1109 int err;
11b3b45d 1110
fad09c73 1111 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1112 return -EOPNOTSUPP;
1113
fad09c73 1114 mutex_lock(&chip->reg_lock);
11b3b45d 1115
9c93829c
VD		 1116 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1117 if (err)
2f40c698
AL		 1118 goto out;
1119
9c93829c 1120 reg &= ~0x0300;
2f40c698
AL		 1121 if (e->eee_enabled)
1122 reg |= 0x0200;
1123 if (e->tx_lpi_enabled)
1124 reg |= 0x0100;
1125
9c93829c 1126 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1127out:
fad09c73 1128 mutex_unlock(&chip->reg_lock);
2f40c698 1129
9c93829c 1130 return err;
11b3b45d
GR		 1131}
1132
fad09c73 1133static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1134{
a935c052
VD		 1135 u16 val;
1136 int err;
facd95b2 1137
6dc10bbc 1138 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1139 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1140 if (err)
1141 return err;
fad09c73 1142 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1143 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1144 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1145 if (err)
1146 return err;
11ea809f 1147
a935c052
VD		 1148 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1149 (val & 0xfff) | ((fid << 8) & 0xf000));
1150 if (err)
1151 return err;
11ea809f
VD		 1152
1153 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1154 cmd |= fid & 0xf;
b426e5f7
VD		 1155 }
1156
a935c052
VD		 1157 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1158 if (err)
1159 return err;
facd95b2 1160
fad09c73 1161 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1162}
1163
fad09c73 1164static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1165 struct mv88e6xxx_atu_entry *entry)
1166{
1167 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1168
1169 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1170 unsigned int mask, shift;
1171
1172 if (entry->trunk) {
1173 data |= GLOBAL_ATU_DATA_TRUNK;
1174 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1175 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1176 } else {
1177 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1178 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1179 }
1180
1181 data |= (entry->portv_trunkid << shift) & mask;
1182 }
1183
a935c052 1184 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1185}
1186
fad09c73 1187static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1188 struct mv88e6xxx_atu_entry *entry,
1189 bool static_too)
facd95b2 1190{
7fb5e755
VD		 1191 int op;
1192 int err;
facd95b2 1193
fad09c73 1194 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1195 if (err)
1196 return err;
facd95b2 1197
fad09c73 1198 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1199 if (err)
1200 return err;
1201
1202 if (entry->fid) {
7fb5e755
VD		 1203 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1204 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1205 } else {
1206 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1207 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1208 }
1209
fad09c73 1210 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1211}
1212
fad09c73 1213static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1214 u16 fid, bool static_too)
7fb5e755
VD		 1215{
1216 struct mv88e6xxx_atu_entry entry = {
1217 .fid = fid,
1218 .state = 0, /* EntryState bits must be 0 */
1219 };
70cc99d1 1220
fad09c73 1221 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1222}
1223
fad09c73 1224static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1225 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1226{
1227 struct mv88e6xxx_atu_entry entry = {
1228 .trunk = false,
1229 .fid = fid,
1230 };
1231
1232 /* EntryState bits must be 0xF */
1233 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1234
1235 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1236 entry.portv_trunkid = (to_port & 0x0f) << 4;
1237 entry.portv_trunkid |= from_port & 0x0f;
1238
fad09c73 1239 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1240}
1241
fad09c73 1242static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1243 int port, bool static_too)
9f4d55d2
VD		 1244{
1245 /* Destination port 0xF means remove the entries */
fad09c73 1246 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1247}
1248
fad09c73 1249static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1250{
fad09c73 1251 struct dsa_switch *ds = chip->ds;
fae8a25e 1252 struct net_device *bridge = ds->ports[port].bridge_dev;
b7666efe 1253 u16 output_ports = 0;
b7666efe
VD		 1254 int i;
1255
1256 /* allow CPU port or DSA link(s) to send frames to every port */
1257 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1258 output_ports = ~0;
b7666efe 1259 } else {
370b4ffb 1260 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1261 /* allow sending frames to every group member */
fae8a25e 1262 if (bridge && ds->ports[i].bridge_dev == bridge)
b7666efe
VD		 1263 output_ports |= BIT(i);
1264
1265 /* allow sending frames to CPU port and DSA link(s) */
1266 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1267 output_ports |= BIT(i);
1268 }
1269 }
1270
1271 /* prevent frames from going back out of the port they came in on */
1272 output_ports &= ~BIT(port);
facd95b2 1273
5a7921f4 1274 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1275}
1276
f81ec90f
VD		 1277static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1278 u8 state)
facd95b2 1279{
04bed143 1280 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1281 int stp_state;
553eb544 1282 int err;
facd95b2
GR		 1283
1284 switch (state) {
1285 case BR_STATE_DISABLED:
cca8b133 1286 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1287 break;
1288 case BR_STATE_BLOCKING:
1289 case BR_STATE_LISTENING:
cca8b133 1290 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1291 break;
1292 case BR_STATE_LEARNING:
cca8b133 1293 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1294 break;
1295 case BR_STATE_FORWARDING:
1296 default:
cca8b133 1297 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1298 break;
1299 }
1300
fad09c73 1301 mutex_lock(&chip->reg_lock);
e28def33 1302 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1303 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1304
1305 if (err)
e28def33 1306 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1307}
1308
a2ac29d2
VD		 1309static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1310{
c3a7d4ad
VD		 1311 int err;
1312
1313 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1314 if (err)
1315 return err;
1316
a2ac29d2
VD		 1317 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1318}
1319
749efcb8
VD		 1320static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1321{
1322 struct mv88e6xxx_chip *chip = ds->priv;
1323 int err;
1324
1325 mutex_lock(&chip->reg_lock);
1326 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1327 mutex_unlock(&chip->reg_lock);
1328
1329 if (err)
1330 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1331}
1332
fad09c73 1333static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1334{
a935c052 1335 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1336}
1337
fad09c73 1338static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1339{
a935c052 1340 int err;
6b17e864 1341
a935c052
VD		 1342 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1343 if (err)
1344 return err;
6b17e864 1345
fad09c73 1346 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1347}
1348
fad09c73 1349static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1350{
1351 int ret;
1352
fad09c73 1353 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1354 if (ret < 0)
1355 return ret;
1356
fad09c73 1357 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1358}
1359
fad09c73 1360static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1361 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1362 unsigned int nibble_offset)
1363{
b8fee957 1364 u16 regs[3];
a935c052 1365 int i, err;
b8fee957
VD		 1366
1367 for (i = 0; i < 3; ++i) {
a935c052 1368 u16 *reg = &regs[i];
b8fee957 1369
a935c052
VD		 1370 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1371 if (err)
1372 return err;
b8fee957
VD		 1373 }
1374
370b4ffb 1375 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1376 unsigned int shift = (i % 4) * 4 + nibble_offset;
1377 u16 reg = regs[i / 4];
1378
1379 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1380 }
1381
1382 return 0;
1383}
1384
fad09c73 1385static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1386 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1387{
fad09c73 1388 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1389}
1390
fad09c73 1391static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1392 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1393{
fad09c73 1394 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1395}
1396
fad09c73 1397static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1398 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1399 unsigned int nibble_offset)
1400{
7dad08d7 1401 u16 regs[3] = { 0 };
a935c052 1402 int i, err;
7dad08d7 1403
370b4ffb 1404 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1405 unsigned int shift = (i % 4) * 4 + nibble_offset;
1406 u8 data = entry->data[i];
1407
1408 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1409 }
1410
1411 for (i = 0; i < 3; ++i) {
a935c052
VD		 1412 u16 reg = regs[i];
1413
1414 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1415 if (err)
1416 return err;
7dad08d7
VD		 1417 }
1418
1419 return 0;
1420}
1421
fad09c73 1422static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1423 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1424{
fad09c73 1425 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1426}
1427
fad09c73 1428static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1429 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1430{
fad09c73 1431 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1432}
1433
fad09c73 1434static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1435{
a935c052
VD		 1436 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1437 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1438}
1439
fad09c73 1440static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1441 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1442{
b4e47c0f 1443 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1444 u16 val;
1445 int err;
b8fee957 1446
a935c052
VD		 1447 err = _mv88e6xxx_vtu_wait(chip);
1448 if (err)
1449 return err;
b8fee957 1450
a935c052
VD		 1451 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1452 if (err)
1453 return err;
b8fee957 1454
a935c052
VD		 1455 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1456 if (err)
1457 return err;
b8fee957 1458
a935c052
VD		 1459 next.vid = val & GLOBAL_VTU_VID_MASK;
1460 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1461
1462 if (next.valid) {
a935c052
VD		 1463 err = mv88e6xxx_vtu_data_read(chip, &next);
1464 if (err)
1465 return err;
b8fee957 1466
6dc10bbc 1467 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1468 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1469 if (err)
1470 return err;
b8fee957 1471
a935c052 1472 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1473 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1474 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1475 * VTU DBNum[3:0] are located in VTU Operation 3:0
1476 */
a935c052
VD		 1477 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1478 if (err)
1479 return err;
11ea809f 1480
a935c052
VD		 1481 next.fid = (val & 0xf00) >> 4;
1482 next.fid |= val & 0xf;
2e7bd5ef 1483 }
b8fee957 1484
fad09c73 1485 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1486 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1487 if (err)
1488 return err;
b8fee957 1489
a935c052 1490 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1491 }
1492 }
1493
1494 *entry = next;
1495 return 0;
1496}
1497
f81ec90f
VD		 1498static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1499 struct switchdev_obj_port_vlan *vlan,
1500 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1501{
04bed143 1502 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1503 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1504 u16 pvid;
1505 int err;
1506
fad09c73 1507 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1508 return -EOPNOTSUPP;
1509
fad09c73 1510 mutex_lock(&chip->reg_lock);
ceff5eff 1511
77064f37 1512 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1513 if (err)
1514 goto unlock;
1515
fad09c73 1516 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1517 if (err)
1518 goto unlock;
1519
1520 do {
fad09c73 1521 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1522 if (err)
1523 break;
1524
1525 if (!next.valid)
1526 break;
1527
1528 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1529 continue;
1530
1531 /* reinit and dump this VLAN obj */
57d32310
VD		 1532 vlan->vid_begin = next.vid;
1533 vlan->vid_end = next.vid;
ceff5eff
VD		 1534 vlan->flags = 0;
1535
1536 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1537 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1538
1539 if (next.vid == pvid)
1540 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1541
1542 err = cb(&vlan->obj);
1543 if (err)
1544 break;
1545 } while (next.vid < GLOBAL_VTU_VID_MASK);
1546
1547unlock:
fad09c73 1548 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1549
1550 return err;
1551}
1552
fad09c73 1553static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1554 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1555{
11ea809f 1556 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1557 u16 reg = 0;
a935c052 1558 int err;
7dad08d7 1559
a935c052
VD		 1560 err = _mv88e6xxx_vtu_wait(chip);
1561 if (err)
1562 return err;
7dad08d7
VD		 1563
1564 if (!entry->valid)
1565 goto loadpurge;
1566
1567 /* Write port member tags */
a935c052
VD		 1568 err = mv88e6xxx_vtu_data_write(chip, entry);
1569 if (err)
1570 return err;
7dad08d7 1571
fad09c73 1572 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1573 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1574 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1575 if (err)
1576 return err;
b426e5f7 1577 }
7dad08d7 1578
6dc10bbc 1579 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1580 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1581 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1582 if (err)
1583 return err;
fad09c73 1584 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1585 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1586 * VTU DBNum[3:0] are located in VTU Operation 3:0
1587 */
1588 op |= (entry->fid & 0xf0) << 8;
1589 op |= entry->fid & 0xf;
7dad08d7
VD		 1590 }
1591
1592 reg = GLOBAL_VTU_VID_VALID;
1593loadpurge:
1594 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1595 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1596 if (err)
1597 return err;
7dad08d7 1598
fad09c73 1599 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1600}
1601
fad09c73 1602static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1603 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1604{
b4e47c0f 1605 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1606 u16 val;
1607 int err;
0d3b33e6 1608
a935c052
VD		 1609 err = _mv88e6xxx_vtu_wait(chip);
1610 if (err)
1611 return err;
0d3b33e6 1612
a935c052
VD		 1613 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1614 sid & GLOBAL_VTU_SID_MASK);
1615 if (err)
1616 return err;
0d3b33e6 1617
a935c052
VD		 1618 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1619 if (err)
1620 return err;
0d3b33e6 1621
a935c052
VD		 1622 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1623 if (err)
1624 return err;
0d3b33e6 1625
a935c052 1626 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1627
a935c052
VD		 1628 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1629 if (err)
1630 return err;
0d3b33e6 1631
a935c052 1632 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1633
1634 if (next.valid) {
a935c052
VD		 1635 err = mv88e6xxx_stu_data_read(chip, &next);
1636 if (err)
1637 return err;
0d3b33e6
VD		 1638 }
1639
1640 *entry = next;
1641 return 0;
1642}
1643
fad09c73 1644static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1645 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1646{
1647 u16 reg = 0;
a935c052 1648 int err;
0d3b33e6 1649
a935c052
VD		 1650 err = _mv88e6xxx_vtu_wait(chip);
1651 if (err)
1652 return err;
0d3b33e6
VD		 1653
1654 if (!entry->valid)
1655 goto loadpurge;
1656
1657 /* Write port states */
a935c052
VD		 1658 err = mv88e6xxx_stu_data_write(chip, entry);
1659 if (err)
1660 return err;
0d3b33e6
VD		 1661
1662 reg = GLOBAL_VTU_VID_VALID;
1663loadpurge:
a935c052
VD		 1664 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1665 if (err)
1666 return err;
0d3b33e6
VD		 1667
1668 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1669 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1670 if (err)
1671 return err;
0d3b33e6 1672
fad09c73 1673 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1674}
1675
fad09c73 1676static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1677{
1678 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1679 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1680 int i, err;
3285f9e8
VD		 1681
1682 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1683
2db9ce1f 1684 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1685 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1686 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1687 if (err)
1688 return err;
1689
1690 set_bit(*fid, fid_bitmap);
1691 }
1692
3285f9e8 1693 /* Set every FID bit used by the VLAN entries */
fad09c73 1694 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1695 if (err)
1696 return err;
1697
1698 do {
fad09c73 1699 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1700 if (err)
1701 return err;
1702
1703 if (!vlan.valid)
1704 break;
1705
1706 set_bit(vlan.fid, fid_bitmap);
1707 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1708
1709 /* The reset value 0x000 is used to indicate that multiple address
1710 * databases are not needed. Return the next positive available.
1711 */
1712 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1713 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1714 return -ENOSPC;
1715
1716 /* Clear the database */
fad09c73 1717 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1718}
1719
fad09c73 1720static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1721 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1722{
fad09c73 1723 struct dsa_switch *ds = chip->ds;
b4e47c0f 1724 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1725 .valid = true,
1726 .vid = vid,
1727 };
3285f9e8
VD		 1728 int i, err;
1729
fad09c73 1730 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1731 if (err)
1732 return err;
0d3b33e6 1733
3d131f07 1734 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1735 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1736 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1737 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1738 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1739
fad09c73 1740 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
a75961d0
GC		 1741 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1742 mv88e6xxx_6341_family(chip)) {
b4e47c0f 1743 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1744
1745 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1746 * implemented, only one STU entry is needed to cover all VTU
1747 * entries. Thus, validate the SID 0.
1748 */
1749 vlan.sid = 0;
fad09c73 1750 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1751 if (err)
1752 return err;
1753
1754 if (vstp.sid != vlan.sid || !vstp.valid) {
1755 memset(&vstp, 0, sizeof(vstp));
1756 vstp.valid = true;
1757 vstp.sid = vlan.sid;
1758
fad09c73 1759 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1760 if (err)
1761 return err;
1762 }
0d3b33e6
VD		 1763 }
1764
1765 *entry = vlan;
1766 return 0;
1767}
1768
fad09c73 1769static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1770 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1771{
1772 int err;
1773
1774 if (!vid)
1775 return -EINVAL;
1776
fad09c73 1777 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1778 if (err)
1779 return err;
1780
fad09c73 1781 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1782 if (err)
1783 return err;
1784
1785 if (entry->vid != vid || !entry->valid) {
1786 if (!creat)
1787 return -EOPNOTSUPP;
1788 /* -ENOENT would've been more appropriate, but switchdev expects
1789 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1790 */
1791
fad09c73 1792 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1793 }
1794
1795 return err;
1796}
1797
da9c359e
VD		 1798static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1799 u16 vid_begin, u16 vid_end)
1800{
04bed143 1801 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1802 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1803 int i, err;
1804
1805 if (!vid_begin)
1806 return -EOPNOTSUPP;
1807
fad09c73 1808 mutex_lock(&chip->reg_lock);
da9c359e 1809
fad09c73 1810 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1811 if (err)
1812 goto unlock;
1813
1814 do {
fad09c73 1815 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1816 if (err)
1817 goto unlock;
1818
1819 if (!vlan.valid)
1820 break;
1821
1822 if (vlan.vid > vid_end)
1823 break;
1824
370b4ffb 1825 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1826 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1827 continue;
1828
66e2809d
AL		 1829 if (!ds->ports[port].netdev)
1830 continue;
1831
da9c359e
VD		 1832 if (vlan.data[i] ==
1833 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1834 continue;
1835
fae8a25e
VD		 1836 if (ds->ports[i].bridge_dev ==
1837 ds->ports[port].bridge_dev)
da9c359e
VD		 1838 break; /* same bridge, check next VLAN */
1839
fae8a25e 1840 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1841 continue;
1842
c8b09808 1843 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1844 "hardware VLAN %d already used by %s\n",
1845 vlan.vid,
fae8a25e 1846 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1847 err = -EOPNOTSUPP;
1848 goto unlock;
1849 }
1850 } while (vlan.vid < vid_end);
1851
1852unlock:
fad09c73 1853 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1854
1855 return err;
1856}
1857
f81ec90f
VD		 1858static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1859 bool vlan_filtering)
214cdb99 1860{
04bed143 1861 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1862 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1863 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1864 int err;
214cdb99 1865
fad09c73 1866 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1867 return -EOPNOTSUPP;
1868
fad09c73 1869 mutex_lock(&chip->reg_lock);
385a0995 1870 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1871 mutex_unlock(&chip->reg_lock);
214cdb99 1872
0e7b9925 1873 return err;
214cdb99
VD		 1874}
1875
57d32310
VD		 1876static int
1877mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1878 const struct switchdev_obj_port_vlan *vlan,
1879 struct switchdev_trans *trans)
76e398a6 1880{
04bed143 1881 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1882 int err;
1883
fad09c73 1884 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1885 return -EOPNOTSUPP;
1886
da9c359e
VD		 1887 /* If the requested port doesn't belong to the same bridge as the VLAN
1888 * members, do not support it (yet) and fallback to software VLAN.
1889 */
1890 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1891 vlan->vid_end);
1892 if (err)
1893 return err;
1894
76e398a6
VD		 1895 /* We don't need any dynamic resource from the kernel (yet),
1896 * so skip the prepare phase.
1897 */
1898 return 0;
1899}
1900
fad09c73 1901static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1902 u16 vid, bool untagged)
0d3b33e6 1903{
b4e47c0f 1904 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1905 int err;
1906
fad09c73 1907 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1908 if (err)
76e398a6 1909 return err;
0d3b33e6 1910
0d3b33e6
VD		 1911 vlan.data[port] = untagged ?
1912 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1913 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1914
fad09c73 1915 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1916}
1917
f81ec90f
VD		 1918static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1919 const struct switchdev_obj_port_vlan *vlan,
1920 struct switchdev_trans *trans)
76e398a6 1921{
04bed143 1922 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1923 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1924 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1925 u16 vid;
76e398a6 1926
fad09c73 1927 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1928 return;
1929
fad09c73 1930 mutex_lock(&chip->reg_lock);
76e398a6 1931
4d5770b3 1932 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1933 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1934 netdev_err(ds->ports[port].netdev,
1935 "failed to add VLAN %d%c\n",
4d5770b3 1936 vid, untagged ? 'u' : 't');
76e398a6 1937
77064f37 1938 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1939 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1940 vlan->vid_end);
0d3b33e6 1941
fad09c73 1942 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1943}
1944
fad09c73 1945static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1946 int port, u16 vid)
7dad08d7 1947{
fad09c73 1948 struct dsa_switch *ds = chip->ds;
b4e47c0f 1949 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1950 int i, err;
1951
fad09c73 1952 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1953 if (err)
76e398a6 1954 return err;
7dad08d7 1955
2fb5ef09
VD		 1956 /* Tell switchdev if this VLAN is handled in software */
1957 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1958 return -EOPNOTSUPP;
7dad08d7
VD		 1959
1960 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1961
1962 /* keep the VLAN unless all ports are excluded */
f02bdffc 1963 vlan.valid = false;
370b4ffb 1964 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1965 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1966 continue;
1967
1968 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1969 vlan.valid = true;
7dad08d7
VD		 1970 break;
1971 }
1972 }
1973
fad09c73 1974 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1975 if (err)
1976 return err;
1977
fad09c73 1978 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1979}
1980
f81ec90f
VD		 1981static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1982 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1983{
04bed143 1984 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1985 u16 pvid, vid;
1986 int err = 0;
1987
fad09c73 1988 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1989 return -EOPNOTSUPP;
1990
fad09c73 1991 mutex_lock(&chip->reg_lock);
76e398a6 1992
77064f37 1993 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1994 if (err)
1995 goto unlock;
1996
76e398a6 1997 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1998 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1999 if (err)
2000 goto unlock;
2001
2002 if (vid == pvid) {
77064f37 2003 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 2004 if (err)
2005 goto unlock;
2006 }
2007 }
2008
7dad08d7 2009unlock:
fad09c73 2010 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2011
2012 return err;
2013}
2014
fad09c73 2015static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2016 const unsigned char *addr)
defb05b9 2017{
a935c052 2018 int i, err;
defb05b9
GR		 2019
2020 for (i = 0; i < 3; i++) {
a935c052
VD		 2021 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2022 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2023 if (err)
2024 return err;
defb05b9
GR		 2025 }
2026
2027 return 0;
2028}
2029
fad09c73 2030static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2031 unsigned char *addr)
defb05b9 2032{
a935c052
VD		 2033 u16 val;
2034 int i, err;
defb05b9
GR		 2035
2036 for (i = 0; i < 3; i++) {
a935c052
VD		 2037 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2038 if (err)
2039 return err;
2040
2041 addr[i * 2] = val >> 8;
2042 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2043 }
2044
2045 return 0;
2046}
2047
fad09c73 2048static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2049 struct mv88e6xxx_atu_entry *entry)
defb05b9 2050{
6630e236
VD		 2051 int ret;
2052
fad09c73 2053 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2054 if (ret < 0)
2055 return ret;
2056
fad09c73 2057 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2058 if (ret < 0)
2059 return ret;
2060
fad09c73 2061 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2062 if (ret < 0)
87820510
VD		 2063 return ret;
2064
fad09c73 2065 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2066}
87820510 2067
88472939
VD		 2068static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2069 struct mv88e6xxx_atu_entry *entry);
2070
2071static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2072 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2073{
2074 struct mv88e6xxx_atu_entry next;
2075 int err;
2076
59527581
AL		 2077 memcpy(next.mac, addr, ETH_ALEN);
2078 eth_addr_dec(next.mac);
88472939
VD		 2079
2080 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2081 if (err)
2082 return err;
2083
2084 do {
2085 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2086 if (err)
2087 return err;
2088
2089 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2090 break;
2091
2092 if (ether_addr_equal(next.mac, addr)) {
2093 *entry = next;
2094 return 0;
2095 }
59527581 2096 } while (ether_addr_greater(addr, next.mac));
88472939
VD		 2097
2098 memset(entry, 0, sizeof(*entry));
2099 entry->fid = fid;
2100 ether_addr_copy(entry->mac, addr);
2101
2102 return 0;
2103}
2104
83dabd1f
VD		 2105static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2106 const unsigned char *addr, u16 vid,
2107 u8 state)
fd231c82 2108{
b4e47c0f 2109 struct mv88e6xxx_vtu_entry vlan;
88472939 2110 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2111 int err;
2112
2db9ce1f
VD		 2113 /* Null VLAN ID corresponds to the port private database */
2114 if (vid == 0)
b4e48c50 2115 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2116 else
fad09c73 2117 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2118 if (err)
2119 return err;
fd231c82 2120
88472939
VD		 2121 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2122 if (err)
2123 return err;
2124
2125 /* Purge the ATU entry only if no port is using it anymore */
2126 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2127 entry.portv_trunkid &= ~BIT(port);
2128 if (!entry.portv_trunkid)
2129 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2130 } else {
2131 entry.portv_trunkid |= BIT(port);
2132 entry.state = state;
fd231c82
VD		 2133 }
2134
fad09c73 2135 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2136}
2137
f81ec90f
VD		 2138static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2139 const struct switchdev_obj_port_fdb *fdb,
2140 struct switchdev_trans *trans)
146a3206
VD		 2141{
2142 /* We don't need any dynamic resource from the kernel (yet),
2143 * so skip the prepare phase.
2144 */
2145 return 0;
2146}
2147
f81ec90f
VD		 2148static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2149 const struct switchdev_obj_port_fdb *fdb,
2150 struct switchdev_trans *trans)
87820510 2151{
04bed143 2152 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2153
fad09c73 2154 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2155 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2156 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2157 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2158 mutex_unlock(&chip->reg_lock);
87820510
VD		 2159}
2160
f81ec90f
VD		 2161static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2162 const struct switchdev_obj_port_fdb *fdb)
87820510 2163{
04bed143 2164 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2165 int err;
87820510 2166
fad09c73 2167 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2168 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2169 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2170 mutex_unlock(&chip->reg_lock);
87820510 2171
83dabd1f 2172 return err;
87820510
VD		 2173}
2174
fad09c73 2175static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2176 struct mv88e6xxx_atu_entry *entry)
6630e236 2177{
1d194046 2178 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2179 u16 val;
2180 int err;
1d194046
VD		 2181
2182 next.fid = fid;
defb05b9 2183
a935c052
VD		 2184 err = _mv88e6xxx_atu_wait(chip);
2185 if (err)
2186 return err;
6630e236 2187
a935c052
VD		 2188 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2189 if (err)
2190 return err;
6630e236 2191
a935c052
VD		 2192 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2193 if (err)
2194 return err;
6630e236 2195
a935c052
VD		 2196 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2197 if (err)
2198 return err;
6630e236 2199
a935c052 2200 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2201 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2202 unsigned int mask, shift;
2203
a935c052 2204 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2205 next.trunk = true;
2206 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2207 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2208 } else {
2209 next.trunk = false;
2210 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2211 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2212 }
2213
a935c052 2214 next.portv_trunkid = (val & mask) >> shift;
1d194046 2215 }
cdf09697 2216
1d194046 2217 *entry = next;
cdf09697
DM		 2218 return 0;
2219}
2220
83dabd1f
VD		 2221static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2222 u16 fid, u16 vid, int port,
2223 struct switchdev_obj *obj,
2224 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2225{
2226 struct mv88e6xxx_atu_entry addr = {
2227 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2228 };
2229 int err;
2230
fad09c73 2231 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2232 if (err)
2233 return err;
2234
2235 do {
fad09c73 2236 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2237 if (err)
83dabd1f 2238 return err;
74b6ba0d
VD		 2239
2240 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2241 break;
2242
83dabd1f
VD		 2243 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2244 continue;
2245
2246 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2247 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2248
83dabd1f
VD		 2249 if (!is_unicast_ether_addr(addr.mac))
2250 continue;
2251
2252 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2253 fdb->vid = vid;
2254 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2255 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2256 fdb->ndm_state = NUD_NOARP;
2257 else
2258 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2259 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2260 struct switchdev_obj_port_mdb *mdb;
2261
2262 if (!is_multicast_ether_addr(addr.mac))
2263 continue;
2264
2265 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2266 mdb->vid = vid;
2267 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2268 } else {
2269 return -EOPNOTSUPP;
74b6ba0d 2270 }
83dabd1f
VD		 2271
2272 err = cb(obj);
2273 if (err)
2274 return err;
74b6ba0d
VD		 2275 } while (!is_broadcast_ether_addr(addr.mac));
2276
2277 return err;
2278}
2279
83dabd1f
VD		 2280static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2281 struct switchdev_obj *obj,
2282 int (*cb)(struct switchdev_obj *obj))
f33475bd 2283{
b4e47c0f 2284 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2285 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2286 };
2db9ce1f 2287 u16 fid;
f33475bd
VD		 2288 int err;
2289
2db9ce1f 2290 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2291 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2292 if (err)
83dabd1f 2293 return err;
2db9ce1f 2294
83dabd1f 2295 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2296 if (err)
83dabd1f 2297 return err;
2db9ce1f 2298
74b6ba0d 2299 /* Dump VLANs' Filtering Information Databases */
fad09c73 2300 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2301 if (err)
83dabd1f 2302 return err;
f33475bd
VD		 2303
2304 do {
fad09c73 2305 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2306 if (err)
83dabd1f 2307 return err;
f33475bd
VD		 2308
2309 if (!vlan.valid)
2310 break;
2311
83dabd1f
VD		 2312 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2313 obj, cb);
f33475bd 2314 if (err)
83dabd1f 2315 return err;
f33475bd
VD		 2316 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2317
83dabd1f
VD		 2318 return err;
2319}
2320
2321static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2322 struct switchdev_obj_port_fdb *fdb,
2323 int (*cb)(struct switchdev_obj *obj))
2324{
04bed143 2325 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2326 int err;
2327
2328 mutex_lock(&chip->reg_lock);
2329 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2330 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2331
2332 return err;
2333}
2334
f81ec90f 2335static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
fae8a25e 2336 struct net_device *br)
e79a8bcb 2337{
04bed143 2338 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2339 int i, err = 0;
466dfa07 2340
fad09c73 2341 mutex_lock(&chip->reg_lock);
466dfa07 2342
fae8a25e 2343 /* Remap each port's VLANTable */
370b4ffb 2344 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fae8a25e 2345 if (ds->ports[i].bridge_dev == br) {
fad09c73 2346 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2347 if (err)
2348 break;
2349 }
2350 }
2351
fad09c73 2352 mutex_unlock(&chip->reg_lock);
a6692754 2353
466dfa07 2354 return err;
e79a8bcb
VD		 2355}
2356
f123f2fb
VD		 2357static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2358 struct net_device *br)
66d9cd0f 2359{
04bed143 2360 struct mv88e6xxx_chip *chip = ds->priv;
16bfa702 2361 int i;
466dfa07 2362
fad09c73 2363 mutex_lock(&chip->reg_lock);
466dfa07 2364
fae8a25e 2365 /* Remap each port's VLANTable */
370b4ffb 2366 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fae8a25e 2367 if (i == port || ds->ports[i].bridge_dev == br)
fad09c73 2368 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2369 netdev_warn(ds->ports[i].netdev,
2370 "failed to remap\n");
b7666efe 2371
fad09c73 2372 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2373}
2374
17e708ba
VD		 2375static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2376{
2377 if (chip->info->ops->reset)
2378 return chip->info->ops->reset(chip);
2379
2380 return 0;
2381}
2382
309eca6d
VD		 2383static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2384{
2385 struct gpio_desc *gpiod = chip->reset;
2386
2387 /* If there is a GPIO connected to the reset pin, toggle it */
2388 if (gpiod) {
2389 gpiod_set_value_cansleep(gpiod, 1);
2390 usleep_range(10000, 20000);
2391 gpiod_set_value_cansleep(gpiod, 0);
2392 usleep_range(10000, 20000);
2393 }
2394}
2395
4ac4b5a6 2396static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2397{
4ac4b5a6 2398 int i, err;
552238b5 2399
4ac4b5a6 2400 /* Set all ports to the Disabled state */
370b4ffb 2401 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2402 err = mv88e6xxx_port_set_state(chip, i,
2403 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2404 if (err)
2405 return err;
552238b5
VD		 2406 }
2407
4ac4b5a6
VD		 2408 /* Wait for transmit queues to drain,
2409 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2410 */
552238b5
VD		 2411 usleep_range(2000, 4000);
2412
4ac4b5a6
VD		 2413 return 0;
2414}
2415
2416static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2417{
4ac4b5a6
VD		 2418 int err;
2419
2420 err = mv88e6xxx_disable_ports(chip);
2421 if (err)
2422 return err;
2423
309eca6d 2424 mv88e6xxx_hardware_reset(chip);
552238b5 2425
17e708ba 2426 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2427}
2428
09cb7dfd 2429static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2430{
09cb7dfd
VD		 2431 u16 val;
2432 int err;
13a7ebb3 2433
09cb7dfd
VD		 2434 /* Clear Power Down bit */
2435 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2436 if (err)
2437 return err;
13a7ebb3 2438
09cb7dfd
VD		 2439 if (val & BMCR_PDOWN) {
2440 val &= ~BMCR_PDOWN;
2441 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2442 }
2443
09cb7dfd 2444 return err;
13a7ebb3
PU		 2445}
2446
56995cbc
AL		 2447static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2448 int upstream_port)
2449{
2450 int err;
2451
2452 err = chip->info->ops->port_set_frame_mode(
2453 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2454 if (err)
2455 return err;
2456
2457 return chip->info->ops->port_set_egress_unknowns(
2458 chip, port, port == upstream_port);
2459}
2460
2461static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2462{
2463 int err;
2464
2465 switch (chip->info->tag_protocol) {
2466 case DSA_TAG_PROTO_EDSA:
2467 err = chip->info->ops->port_set_frame_mode(
2468 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2469 if (err)
2470 return err;
2471
2472 err = mv88e6xxx_port_set_egress_mode(
2473 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2474 if (err)
2475 return err;
2476
2477 if (chip->info->ops->port_set_ether_type)
2478 err = chip->info->ops->port_set_ether_type(
2479 chip, port, ETH_P_EDSA);
2480 break;
2481
2482 case DSA_TAG_PROTO_DSA:
2483 err = chip->info->ops->port_set_frame_mode(
2484 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2485 if (err)
2486 return err;
2487
2488 err = mv88e6xxx_port_set_egress_mode(
2489 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2490 break;
2491 default:
2492 err = -EINVAL;
2493 }
2494
2495 if (err)
2496 return err;
2497
2498 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2499}
2500
2501static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2502{
2503 int err;
2504
2505 err = chip->info->ops->port_set_frame_mode(
2506 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2507 if (err)
2508 return err;
2509
2510 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2511}
2512
ea698f4f
VD		 2513static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2514{
2515 bool message = dsa_is_dsa_port(chip->ds, port);
2516
2517 return mv88e6xxx_port_set_message_port(chip, port, message);
2518}
2519
fad09c73 2520static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2521{
fad09c73 2522 struct dsa_switch *ds = chip->ds;
0e7b9925 2523 int err;
54d792f2 2524 u16 reg;
d827e88a 2525
d78343d2
VD		 2526 /* MAC Forcing register: don't force link, speed, duplex or flow control
2527 * state to any particular values on physical ports, but force the CPU
2528 * port and all DSA ports to their maximum bandwidth and full duplex.
2529 */
2530 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2531 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2532 SPEED_MAX, DUPLEX_FULL,
2533 PHY_INTERFACE_MODE_NA);
2534 else
2535 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2536 SPEED_UNFORCED, DUPLEX_UNFORCED,
2537 PHY_INTERFACE_MODE_NA);
2538 if (err)
2539 return err;
54d792f2
AL		 2540
2541 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2542 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2543 * tunneling, determine priority by looking at 802.1p and IP
2544 * priority fields (IP prio has precedence), and set STP state
2545 * to Forwarding.
2546 *
2547 * If this is the CPU link, use DSA or EDSA tagging depending
2548 * on which tagging mode was configured.
2549 *
2550 * If this is a link to another switch, use DSA tagging mode.
2551 *
2552 * If this is the upstream port for this switch, enable
2553 * forwarding of unknown unicasts and multicasts.
2554 */
56995cbc 2555 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
54d792f2
AL		 2556 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2557 PORT_CONTROL_STATE_FORWARDING;
56995cbc
AL		 2558 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2559 if (err)
2560 return err;
6083ce71 2561
56995cbc
AL		 2562 if (dsa_is_cpu_port(ds, port)) {
2563 err = mv88e6xxx_setup_port_cpu(chip, port);
2564 } else if (dsa_is_dsa_port(ds, port)) {
2565 err = mv88e6xxx_setup_port_dsa(chip, port,
2566 dsa_upstream_port(ds));
2567 } else {
2568 err = mv88e6xxx_setup_port_normal(chip, port);
54d792f2 2569 }
56995cbc
AL		 2570 if (err)
2571 return err;
54d792f2 2572
13a7ebb3
PU		 2573 /* If this port is connected to a SerDes, make sure the SerDes is not
2574 * powered down.
2575 */
09cb7dfd 2576 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2577 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2578 if (err)
2579 return err;
2580 reg &= PORT_STATUS_CMODE_MASK;
2581 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2582 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2583 (reg == PORT_STATUS_CMODE_SGMII)) {
2584 err = mv88e6xxx_serdes_power_on(chip);
2585 if (err < 0)
2586 return err;
13a7ebb3
PU		 2587 }
2588 }
2589
8efdda4a 2590 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2591 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2592 * untagged frames on this port, do a destination address lookup on all
2593 * received packets as usual, disable ARP mirroring and don't send a
2594 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2595 */
a23b2961
AL		 2596 err = mv88e6xxx_port_set_map_da(chip, port);
2597 if (err)
2598 return err;
8efdda4a 2599
a23b2961
AL		 2600 reg = 0;
2601 if (chip->info->ops->port_set_upstream_port) {
2602 err = chip->info->ops->port_set_upstream_port(
2603 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 2604 if (err)
2605 return err;
54d792f2
AL		 2606 }
2607
a23b2961
AL		 2608 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2609 PORT_CONTROL_2_8021Q_DISABLED);
2610 if (err)
2611 return err;
2612
5f436666
AL		 2613 if (chip->info->ops->port_jumbo_config) {
2614 err = chip->info->ops->port_jumbo_config(chip, port);
2615 if (err)
2616 return err;
2617 }
2618
54d792f2
AL		 2619 /* Port Association Vector: when learning source addresses
2620 * of packets, add the address to the address database using
2621 * a port bitmap that has only the bit for this port set and
2622 * the other bits clear.
2623 */
4c7ea3c0 2624 reg = 1 << port;
996ecb82
VD		 2625 /* Disable learning for CPU port */
2626 if (dsa_is_cpu_port(ds, port))
65fa4027 2627 reg = 0;
4c7ea3c0 2628
0e7b9925
AL		 2629 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2630 if (err)
2631 return err;
54d792f2
AL		 2632
2633 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2634 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2635 if (err)
2636 return err;
54d792f2 2637
b35d322a
AL		 2638 if (chip->info->ops->port_pause_config) {
2639 err = chip->info->ops->port_pause_config(chip, port);
0e7b9925
AL		 2640 if (err)
2641 return err;
b35d322a 2642 }
54d792f2 2643
b35d322a
AL		 2644 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2645 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
a75961d0 2646 mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) {
54d792f2
AL		 2647 /* Port ATU control: disable limiting the number of
2648 * address database entries that this port is allowed
2649 * to use.
2650 */
0e7b9925
AL		 2651 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2652 0x0000);
54d792f2
AL		 2653 /* Priority Override: disable DA, SA and VTU priority
2654 * override.
2655 */
0e7b9925
AL		 2656 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2657 0x0000);
2658 if (err)
2659 return err;
ef0a7318 2660 }
2bbb33be 2661
ef0a7318
AL		 2662 if (chip->info->ops->port_tag_remap) {
2663 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2664 if (err)
2665 return err;
54d792f2
AL		 2666 }
2667
ef70b111
AL		 2668 if (chip->info->ops->port_egress_rate_limiting) {
2669 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2670 if (err)
2671 return err;
54d792f2
AL		 2672 }
2673
ea698f4f 2674 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 2675 if (err)
2676 return err;
d827e88a 2677
207afda1 2678 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2679 * database, and allow bidirectional communication between the
2680 * CPU and DSA port(s), and the other ports.
d827e88a 2681 */
b4e48c50 2682 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2683 if (err)
2684 return err;
2db9ce1f 2685
0e7b9925
AL		 2686 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2687 if (err)
2688 return err;
d827e88a
GR		 2689
2690 /* Default VLAN ID and priority: don't set a default VLAN
2691 * ID, and set the default packet priority to zero.
2692 */
0e7b9925 2693 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2694}
2695
aa0938c6 2696static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2697{
2698 int err;
2699
a935c052 2700 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2701 if (err)
2702 return err;
2703
a935c052 2704 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2705 if (err)
2706 return err;
2707
a935c052
VD		 2708 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2709 if (err)
2710 return err;
2711
2712 return 0;
3b4caa1b
VD		 2713}
2714
2cfcd964
VD		 2715static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2716 unsigned int ageing_time)
2717{
04bed143 2718 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2719 int err;
2720
2721 mutex_lock(&chip->reg_lock);
720c6343 2722 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2723 mutex_unlock(&chip->reg_lock);
2724
2725 return err;
2726}
2727
9729934c 2728static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2729{
fad09c73 2730 struct dsa_switch *ds = chip->ds;
b0745e87 2731 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2732 int err;
54d792f2 2733
119477bd
VD		 2734 /* Enable the PHY Polling Unit if present, don't discard any packets,
2735 * and mask all interrupt sources.
2736 */
a199d8b6 2737 err = mv88e6xxx_ppu_enable(chip);
119477bd
VD		 2738 if (err)
2739 return err;
2740
33641994
AL		 2741 if (chip->info->ops->g1_set_cpu_port) {
2742 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2743 if (err)
2744 return err;
2745 }
2746
2747 if (chip->info->ops->g1_set_egress_port) {
2748 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2749 if (err)
2750 return err;
2751 }
b0745e87 2752
50484ff4 2753 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2754 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2755 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2756 (ds->index & 0x1f));
50484ff4
VD		 2757 if (err)
2758 return err;
2759
acddbd21
VD		 2760 /* Clear all the VTU and STU entries */
2761 err = _mv88e6xxx_vtu_stu_flush(chip);
2762 if (err < 0)
2763 return err;
2764
9729934c
VD		 2765 /* Clear all ATU entries */
2766 err = _mv88e6xxx_atu_flush(chip, 0, true);
2767 if (err)
2768 return err;
2769
54d792f2 2770 /* Configure the IP ToS mapping registers. */
a935c052 2771 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2772 if (err)
08a01261 2773 return err;
a935c052 2774 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2775 if (err)
08a01261 2776 return err;
a935c052 2777 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2778 if (err)
08a01261 2779 return err;
a935c052 2780 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2781 if (err)
08a01261 2782 return err;
a935c052 2783 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2784 if (err)
08a01261 2785 return err;
a935c052 2786 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2787 if (err)
08a01261 2788 return err;
a935c052 2789 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2790 if (err)
08a01261 2791 return err;
a935c052 2792 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2793 if (err)
08a01261 2794 return err;
54d792f2
AL		 2795
2796 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2797 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2798 if (err)
08a01261 2799 return err;
54d792f2 2800
de227387
AL		 2801 /* Initialize the statistics unit */
2802 err = mv88e6xxx_stats_set_histogram(chip);
2803 if (err)
2804 return err;
2805
9729934c 2806 /* Clear the statistics counters for all ports */
a935c052
VD		 2807 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2808 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2809 if (err)
2810 return err;
2811
2812 /* Wait for the flush to complete. */
7f9ef3af 2813 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2814 if (err)
2815 return err;
2816
2817 return 0;
2818}
2819
f81ec90f 2820static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2821{
04bed143 2822 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2823 int err;
a1a6a4d1
VD		 2824 int i;
2825
fad09c73 2826 chip->ds = ds;
a3c53be5 2827 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2828
fad09c73 2829 mutex_lock(&chip->reg_lock);
08a01261 2830
9729934c 2831 /* Setup Switch Port Registers */
370b4ffb 2832 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2833 err = mv88e6xxx_setup_port(chip, i);
2834 if (err)
2835 goto unlock;
2836 }
2837
2838 /* Setup Switch Global 1 Registers */
2839 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2840 if (err)
2841 goto unlock;
2842
9729934c
VD		 2843 /* Setup Switch Global 2 Registers */
2844 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2845 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2846 if (err)
2847 goto unlock;
2848 }
08a01261 2849
a2ac29d2
VD		 2850 err = mv88e6xxx_atu_setup(chip);
2851 if (err)
2852 goto unlock;
2853
6e55f698
AL		 2854 /* Some generations have the configuration of sending reserved
2855 * management frames to the CPU in global2, others in
2856 * global1. Hence it does not fit the two setup functions
2857 * above.
2858 */
2859 if (chip->info->ops->mgmt_rsvd2cpu) {
2860 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2861 if (err)
2862 goto unlock;
2863 }
2864
6b17e864 2865unlock:
fad09c73 2866 mutex_unlock(&chip->reg_lock);
db687a56 2867
48ace4ef 2868 return err;
54d792f2
AL		 2869}
2870
3b4caa1b
VD		 2871static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2872{
04bed143 2873 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2874 int err;
2875
b073d4e2
VD		 2876 if (!chip->info->ops->set_switch_mac)
2877 return -EOPNOTSUPP;
3b4caa1b 2878
b073d4e2
VD		 2879 mutex_lock(&chip->reg_lock);
2880 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2881 mutex_unlock(&chip->reg_lock);
2882
2883 return err;
2884}
2885
e57e5e77 2886static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2887{
0dd12d54
AL		 2888 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2889 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2890 u16 val;
2891 int err;
fd3a0ee4 2892
ee26a228
AL		 2893 if (!chip->info->ops->phy_read)
2894 return -EOPNOTSUPP;
2895
fad09c73 2896 mutex_lock(&chip->reg_lock);
ee26a228 2897 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2898 mutex_unlock(&chip->reg_lock);
e57e5e77 2899
da9f3301
AL		 2900 if (reg == MII_PHYSID2) {
2901 /* Some internal PHYS don't have a model number. Use
2902 * the mv88e6390 family model number instead.
2903 */
2904 if (!(val & 0x3f0))
2905 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2906 }
2907
e57e5e77 2908 return err ? err : val;
fd3a0ee4
AL		 2909}
2910
e57e5e77 2911static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2912{
0dd12d54
AL		 2913 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2914 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2915 int err;
fd3a0ee4 2916
ee26a228
AL		 2917 if (!chip->info->ops->phy_write)
2918 return -EOPNOTSUPP;
2919
fad09c73 2920 mutex_lock(&chip->reg_lock);
ee26a228 2921 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2922 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2923
2924 return err;
fd3a0ee4
AL		 2925}
2926
fad09c73 2927static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2928 struct device_node *np,
2929 bool external)
b516d453
AL		 2930{
2931 static int index;
0dd12d54 2932 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2933 struct mii_bus *bus;
2934 int err;
2935
0dd12d54 2936 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2937 if (!bus)
2938 return -ENOMEM;
2939
0dd12d54 2940 mdio_bus = bus->priv;
a3c53be5 2941 mdio_bus->bus = bus;
0dd12d54 2942 mdio_bus->chip = chip;
a3c53be5
AL		 2943 INIT_LIST_HEAD(&mdio_bus->list);
2944 mdio_bus->external = external;
0dd12d54 2945
b516d453
AL		 2946 if (np) {
2947 bus->name = np->full_name;
2948 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2949 } else {
2950 bus->name = "mv88e6xxx SMI";
2951 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2952 }
2953
2954 bus->read = mv88e6xxx_mdio_read;
2955 bus->write = mv88e6xxx_mdio_write;
fad09c73 2956 bus->parent = chip->dev;
b516d453 2957
a3c53be5
AL		 2958 if (np)
2959 err = of_mdiobus_register(bus, np);
b516d453
AL		 2960 else
2961 err = mdiobus_register(bus);
2962 if (err) {
fad09c73 2963 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2964 return err;
b516d453 2965 }
a3c53be5
AL		 2966
2967 if (external)
2968 list_add_tail(&mdio_bus->list, &chip->mdios);
2969 else
2970 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2971
2972 return 0;
a3c53be5 2973}
b516d453 2974
a3c53be5
AL		 2975static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2976 { .compatible = "marvell,mv88e6xxx-mdio-external",
2977 .data = (void *)true },
2978 { },
2979};
b516d453 2980
a3c53be5
AL		 2981static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2982 struct device_node *np)
2983{
2984 const struct of_device_id *match;
2985 struct device_node *child;
2986 int err;
2987
2988 /* Always register one mdio bus for the internal/default mdio
2989 * bus. This maybe represented in the device tree, but is
2990 * optional.
2991 */
2992 child = of_get_child_by_name(np, "mdio");
2993 err = mv88e6xxx_mdio_register(chip, child, false);
2994 if (err)
2995 return err;
2996
2997 /* Walk the device tree, and see if there are any other nodes
2998 * which say they are compatible with the external mdio
2999 * bus.
3000 */
3001 for_each_available_child_of_node(np, child) {
3002 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3003 if (match) {
3004 err = mv88e6xxx_mdio_register(chip, child, true);
3005 if (err)
3006 return err;
3007 }
3008 }
3009
3010 return 0;
b516d453
AL		 3011}
3012
a3c53be5 3013static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3014
3015{
a3c53be5
AL		 3016 struct mv88e6xxx_mdio_bus *mdio_bus;
3017 struct mii_bus *bus;
b516d453 3018
a3c53be5
AL		 3019 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3020 bus = mdio_bus->bus;
b516d453 3021
a3c53be5
AL		 3022 mdiobus_unregister(bus);
3023 }
b516d453
AL		 3024}
3025
855b1932
VD		 3026static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3027{
04bed143 3028 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3029
3030 return chip->eeprom_len;
3031}
3032
855b1932
VD		 3033static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3034 struct ethtool_eeprom *eeprom, u8 *data)
3035{
04bed143 3036 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3037 int err;
3038
ee4dc2e7
VD		 3039 if (!chip->info->ops->get_eeprom)
3040 return -EOPNOTSUPP;
855b1932 3041
ee4dc2e7
VD		 3042 mutex_lock(&chip->reg_lock);
3043 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3044 mutex_unlock(&chip->reg_lock);
3045
3046 if (err)
3047 return err;
3048
3049 eeprom->magic = 0xc3ec4951;
3050
3051 return 0;
3052}
3053
855b1932
VD		 3054static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3055 struct ethtool_eeprom *eeprom, u8 *data)
3056{
04bed143 3057 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3058 int err;
3059
ee4dc2e7
VD		 3060 if (!chip->info->ops->set_eeprom)
3061 return -EOPNOTSUPP;
3062
855b1932
VD		 3063 if (eeprom->magic != 0xc3ec4951)
3064 return -EINVAL;
3065
3066 mutex_lock(&chip->reg_lock);
ee4dc2e7 3067 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3068 mutex_unlock(&chip->reg_lock);
3069
3070 return err;
3071}
3072
b3469dd8 3073static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3074 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 3075 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3076 .phy_read = mv88e6xxx_phy_ppu_read,
3077 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3078 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3079 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3080 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3081 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3082 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3083 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3084 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3085 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3086 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3087 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3088 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3089 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3090 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3091 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3092 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3093 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3094 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3095 .ppu_enable = mv88e6185_g1_ppu_enable,
3096 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3097 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3098};
3099
3100static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3101 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 3102 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3103 .phy_read = mv88e6xxx_phy_ppu_read,
3104 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3105 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3106 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3107 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3108 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a23b2961
AL		 3109 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
3110 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3111 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3112 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3113 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3114 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 3115 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3116 .ppu_enable = mv88e6185_g1_ppu_enable,
3117 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3118 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3119};
3120
7d381a02 3121static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3122 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 3123 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3124 .phy_read = mv88e6xxx_g2_smi_phy_read,
3125 .phy_write = mv88e6xxx_g2_smi_phy_write,
3126 .port_set_link = mv88e6xxx_port_set_link,
3127 .port_set_duplex = mv88e6xxx_port_set_duplex,
3128 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3129 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3130 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3131 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3132 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3133 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3134 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
b35d322a 3135 .port_pause_config = mv88e6097_port_pause_config,
7d381a02
SE		 3136 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3137 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3138 .stats_get_strings = mv88e6095_stats_get_strings,
3139 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3140 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3141 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 3142 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3143 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3144 .reset = mv88e6352_g1_reset,
7d381a02
SE		 3145};
3146
b3469dd8 3147static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3148 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3149 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3150 .phy_read = mv88e6165_phy_read,
3151 .phy_write = mv88e6165_phy_write,
08ef7f10 3152 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3153 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3154 .port_set_speed = mv88e6185_port_set_speed,
56995cbc
AL		 3155 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3156 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
a605a0fe 3157 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3158 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3159 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3160 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3161 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3162 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3163 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3164 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3165 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3166};
3167
3168static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3169 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3170 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3171 .phy_read = mv88e6xxx_phy_ppu_read,
3172 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3173 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3174 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3175 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3176 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3177 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a23b2961 3178 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
56995cbc 3179 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 3180 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
5f436666 3181 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3182 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3183 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3184 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3185 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3186 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3187 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3188 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3189 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3190 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3191 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3192 .ppu_enable = mv88e6185_g1_ppu_enable,
3193 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3194 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3195};
3196
3197static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3198 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3199 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3200 .phy_read = mv88e6165_phy_read,
3201 .phy_write = mv88e6165_phy_write,
08ef7f10 3202 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3203 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3204 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3205 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3206 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3207 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3208 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3209 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3210 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3211 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3212 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3213 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3214 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3215 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3216 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3217 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3218 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3219 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3220 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3221};
3222
3223static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3224 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 3225 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3226 .phy_read = mv88e6165_phy_read,
3227 .phy_write = mv88e6165_phy_write,
08ef7f10 3228 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3229 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3230 .port_set_speed = mv88e6185_port_set_speed,
a605a0fe 3231 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3232 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3233 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3234 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3235 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3236 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3237 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3238 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3239 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3240};
3241
3242static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3243 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3244 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3245 .phy_read = mv88e6xxx_g2_smi_phy_read,
3246 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3247 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3248 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3249 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3250 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3251 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3252 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3253 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3254 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3255 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3256 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3257 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3258 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3259 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3260 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3261 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3262 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3263 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3264 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3265 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3266 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3267};
3268
3269static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3270 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3271 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3272 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3273 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3274 .phy_read = mv88e6xxx_g2_smi_phy_read,
3275 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3276 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3277 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3278 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3279 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3280 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3281 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3282 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3283 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3284 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3285 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3286 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3287 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3288 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3289 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3290 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3291 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3292 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3293 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3294 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3295 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3296};
3297
3298static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3299 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3301 .phy_read = mv88e6xxx_g2_smi_phy_read,
3302 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3303 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3304 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3305 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3306 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3307 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3308 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3309 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3310 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3311 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3312 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3313 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3314 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3315 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3316 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3317 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3318 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3319 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3320 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3321 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3322 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3323};
3324
3325static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3326 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3327 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3328 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3329 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3330 .phy_read = mv88e6xxx_g2_smi_phy_read,
3331 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3332 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3333 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3334 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3335 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3336 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3337 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3338 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3339 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3340 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3341 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3342 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3343 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3344 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3345 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3346 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3347 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3348 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3349 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3350 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3351 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3352};
3353
3354static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3355 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 3356 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3357 .phy_read = mv88e6xxx_phy_ppu_read,
3358 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3359 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3360 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3361 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 3362 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a23b2961 3363 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns,
ef70b111 3364 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 3365 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 3366 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 3367 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3368 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3369 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3370 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3371 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3372 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3373 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 3374 .ppu_enable = mv88e6185_g1_ppu_enable,
3375 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3376 .reset = mv88e6185_g1_reset,
b3469dd8
VD		 3377};
3378
1a3b39ec 3379static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 3380 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3381 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3382 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3383 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3384 .phy_read = mv88e6xxx_g2_smi_phy_read,
3385 .phy_write = mv88e6xxx_g2_smi_phy_write,
3386 .port_set_link = mv88e6xxx_port_set_link,
3387 .port_set_duplex = mv88e6xxx_port_set_duplex,
3388 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3389 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3390 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3391 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3392 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3393 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3394 .port_pause_config = mv88e6390_port_pause_config,
79523473 3395 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3396 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3397 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3398 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3399 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3400 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3401 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3402 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3403 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3404 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3405};
3406
3407static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 3408 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3409 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3410 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3411 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3412 .phy_read = mv88e6xxx_g2_smi_phy_read,
3413 .phy_write = mv88e6xxx_g2_smi_phy_write,
3414 .port_set_link = mv88e6xxx_port_set_link,
3415 .port_set_duplex = mv88e6xxx_port_set_duplex,
3416 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3417 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3418 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3419 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3420 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3421 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3422 .port_pause_config = mv88e6390_port_pause_config,
79523473 3423 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3424 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3425 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3426 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3427 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3428 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3429 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3430 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3431 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3432 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3433};
3434
3435static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 3436 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3437 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3438 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3439 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3440 .phy_read = mv88e6xxx_g2_smi_phy_read,
3441 .phy_write = mv88e6xxx_g2_smi_phy_write,
3442 .port_set_link = mv88e6xxx_port_set_link,
3443 .port_set_duplex = mv88e6xxx_port_set_duplex,
3444 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3445 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3446 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3447 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3448 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3449 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3450 .port_pause_config = mv88e6390_port_pause_config,
79523473 3451 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3452 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3453 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3454 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3455 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3456 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3457 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3458 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3459 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3460 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3461};
3462
b3469dd8 3463static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 3464 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3465 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3466 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3467 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3468 .phy_read = mv88e6xxx_g2_smi_phy_read,
3469 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3470 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3471 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3472 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3473 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3474 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3475 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3476 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3477 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3478 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3479 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3480 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3481 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3482 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3483 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3484 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3485 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3486 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3487 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3488 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3489 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3490};
3491
1a3b39ec 3492static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 3493 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3494 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3495 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3496 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3497 .phy_read = mv88e6xxx_g2_smi_phy_read,
3498 .phy_write = mv88e6xxx_g2_smi_phy_write,
3499 .port_set_link = mv88e6xxx_port_set_link,
3500 .port_set_duplex = mv88e6xxx_port_set_duplex,
3501 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3502 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3503 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3504 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3505 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3506 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3507 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3508 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3509 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3510 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3511 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3512 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3513 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3514 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3515 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3516 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3517 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3518 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3519};
3520
b3469dd8 3521static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 3522 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 3523 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3524 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3525 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3526 .phy_read = mv88e6xxx_g2_smi_phy_read,
3527 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3528 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3529 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3530 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3531 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3532 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3533 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3534 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3535 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3536 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3537 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3538 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3539 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3540 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3541 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3542 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3543 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 3544 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3545 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3546};
3547
3548static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 3549 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 3550 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3551 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3552 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3553 .phy_read = mv88e6xxx_g2_smi_phy_read,
3554 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3555 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3556 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3557 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3558 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3559 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3560 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3561 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3562 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3563 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3564 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3565 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3566 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3567 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3568 .stats_get_stats = mv88e6320_stats_get_stats,
33641994
AL		 3569 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3570 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3571 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3572};
3573
3574static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3575 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3576 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3577 .phy_read = mv88e6xxx_g2_smi_phy_read,
3578 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3579 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3580 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3581 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3582 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3583 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3584 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3585 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3586 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3587 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3588 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3589 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3590 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3591 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3592 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3593 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3594 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3595 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3596 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3597 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3598 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3599};
3600
3601static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3602 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3603 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3604 .phy_read = mv88e6xxx_g2_smi_phy_read,
3605 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3606 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3607 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3608 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3609 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3610 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3611 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3612 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3613 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3614 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3615 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3616 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3617 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3618 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3619 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3620 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3621 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3622 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3623 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3624 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3625 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3626};
3627
3628static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3629 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3630 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3631 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3632 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3633 .phy_read = mv88e6xxx_g2_smi_phy_read,
3634 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3635 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3636 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3637 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3638 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3639 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc
AL		 3640 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3641 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3642 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3643 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3644 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
b35d322a 3645 .port_pause_config = mv88e6097_port_pause_config,
a605a0fe 3646 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3647 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3648 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3649 .stats_get_stats = mv88e6095_stats_get_stats,
33641994
AL		 3650 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3651 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3652 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3653 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3654 .reset = mv88e6352_g1_reset,
b3469dd8
VD		 3655};
3656
1558727a
GC		 3657static const struct mv88e6xxx_ops mv88e6141_ops = {
3658 /* MV88E6XXX_FAMILY_6341 */
3659 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3660 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3661 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3662 .phy_read = mv88e6xxx_g2_smi_phy_read,
3663 .phy_write = mv88e6xxx_g2_smi_phy_write,
3664 .port_set_link = mv88e6xxx_port_set_link,
3665 .port_set_duplex = mv88e6xxx_port_set_duplex,
3666 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3667 .port_set_speed = mv88e6390_port_set_speed,
3668 .port_tag_remap = mv88e6095_port_tag_remap,
3669 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3670 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3671 .port_set_ether_type = mv88e6351_port_set_ether_type,
3672 .port_jumbo_config = mv88e6165_port_jumbo_config,
3673 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3674 .port_pause_config = mv88e6097_port_pause_config,
3675 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3676 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3677 .stats_get_strings = mv88e6320_stats_get_strings,
3678 .stats_get_stats = mv88e6390_stats_get_stats,
3679 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3680 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3681 .watchdog_ops = &mv88e6390_watchdog_ops,
1558727a
GC		 3682 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3683 .reset = mv88e6352_g1_reset,
3684};
3685
a75961d0
GC		 3686static const struct mv88e6xxx_ops mv88e6341_ops = {
3687 /* MV88E6XXX_FAMILY_6341 */
3688 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3689 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3690 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3691 .phy_read = mv88e6xxx_g2_smi_phy_read,
3692 .phy_write = mv88e6xxx_g2_smi_phy_write,
3693 .port_set_link = mv88e6xxx_port_set_link,
3694 .port_set_duplex = mv88e6xxx_port_set_duplex,
3695 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3696 .port_set_speed = mv88e6390_port_set_speed,
3697 .port_tag_remap = mv88e6095_port_tag_remap,
3698 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3699 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3700 .port_set_ether_type = mv88e6351_port_set_ether_type,
3701 .port_jumbo_config = mv88e6165_port_jumbo_config,
3702 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3703 .port_pause_config = mv88e6097_port_pause_config,
3704 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3705 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3706 .stats_get_strings = mv88e6320_stats_get_strings,
3707 .stats_get_stats = mv88e6390_stats_get_stats,
3708 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3709 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3710 .watchdog_ops = &mv88e6390_watchdog_ops,
a75961d0
GC		 3711 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3712 .reset = mv88e6352_g1_reset,
3713};
3714
1a3b39ec 3715static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3716 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3717 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3718 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3719 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3720 .phy_read = mv88e6xxx_g2_smi_phy_read,
3721 .phy_write = mv88e6xxx_g2_smi_phy_write,
3722 .port_set_link = mv88e6xxx_port_set_link,
3723 .port_set_duplex = mv88e6xxx_port_set_duplex,
3724 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3725 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3726 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3727 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3728 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3729 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3730 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3731 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3732 .port_pause_config = mv88e6390_port_pause_config,
f39908d3 3733 .port_set_cmode = mv88e6390x_port_set_cmode,
79523473 3734 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3735 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3736 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3737 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3738 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3739 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3740 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3741 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3742 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3743 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3744};
3745
3746static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3747 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3748 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3749 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3750 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3751 .phy_read = mv88e6xxx_g2_smi_phy_read,
3752 .phy_write = mv88e6xxx_g2_smi_phy_write,
3753 .port_set_link = mv88e6xxx_port_set_link,
3754 .port_set_duplex = mv88e6xxx_port_set_duplex,
3755 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3756 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3757 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3758 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3759 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3760 .port_set_ether_type = mv88e6351_port_set_ether_type,
5f436666 3761 .port_jumbo_config = mv88e6165_port_jumbo_config,
ef70b111 3762 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3ce0e65e 3763 .port_pause_config = mv88e6390_port_pause_config,
79523473 3764 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3765 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3766 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3767 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3768 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3769 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3770 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3771 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3772 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3773 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3774};
3775
3776static const struct mv88e6xxx_ops mv88e6391_ops = {
4b325d8c 3777 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3778 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3779 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3780 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3781 .phy_read = mv88e6xxx_g2_smi_phy_read,
3782 .phy_write = mv88e6xxx_g2_smi_phy_write,
3783 .port_set_link = mv88e6xxx_port_set_link,
3784 .port_set_duplex = mv88e6xxx_port_set_duplex,
3785 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3786 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3787 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc
AL		 3788 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3789 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3790 .port_set_ether_type = mv88e6351_port_set_ether_type,
3ce0e65e 3791 .port_pause_config = mv88e6390_port_pause_config,
79523473 3792 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3793 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3794 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3795 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3796 .stats_get_stats = mv88e6390_stats_get_stats,
33641994
AL		 3797 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3798 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3799 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3800 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3801 .reset = mv88e6352_g1_reset,
1a3b39ec
AL		 3802};
3803
56995cbc
AL		 3804static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3805 const struct mv88e6xxx_ops *ops)
3806{
3807 if (!ops->port_set_frame_mode) {
3808 dev_err(chip->dev, "Missing port_set_frame_mode");
3809 return -EINVAL;
3810 }
3811
3812 if (!ops->port_set_egress_unknowns) {
3813 dev_err(chip->dev, "Missing port_set_egress_mode");
3814 return -EINVAL;
3815 }
3816
3817 return 0;
3818}
3819
f81ec90f
VD		 3820static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3821 [MV88E6085] = {
3822 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3823 .family = MV88E6XXX_FAMILY_6097,
3824 .name = "Marvell 88E6085",
3825 .num_databases = 4096,
3826 .num_ports = 10,
9dddd478 3827 .port_base_addr = 0x10,
a935c052 3828 .global1_addr = 0x1b,
acddbd21 3829 .age_time_coeff = 15000,
dc30c35b 3830 .g1_irqs = 8,
443d5a1b 3831 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3832 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3833 .ops = &mv88e6085_ops,
f81ec90f
VD		 3834 },
3835
3836 [MV88E6095] = {
3837 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3838 .family = MV88E6XXX_FAMILY_6095,
3839 .name = "Marvell 88E6095/88E6095F",
3840 .num_databases = 256,
3841 .num_ports = 11,
9dddd478 3842 .port_base_addr = 0x10,
a935c052 3843 .global1_addr = 0x1b,
acddbd21 3844 .age_time_coeff = 15000,
dc30c35b 3845 .g1_irqs = 8,
443d5a1b 3846 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3847 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3848 .ops = &mv88e6095_ops,
f81ec90f
VD		 3849 },
3850
7d381a02
SE		 3851 [MV88E6097] = {
3852 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3853 .family = MV88E6XXX_FAMILY_6097,
3854 .name = "Marvell 88E6097/88E6097F",
3855 .num_databases = 4096,
3856 .num_ports = 11,
3857 .port_base_addr = 0x10,
3858 .global1_addr = 0x1b,
3859 .age_time_coeff = 15000,
c534178b 3860 .g1_irqs = 8,
2bfcfcd3 3861 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3862 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3863 .ops = &mv88e6097_ops,
3864 },
3865
f81ec90f
VD		 3866 [MV88E6123] = {
3867 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3868 .family = MV88E6XXX_FAMILY_6165,
3869 .name = "Marvell 88E6123",
3870 .num_databases = 4096,
3871 .num_ports = 3,
9dddd478 3872 .port_base_addr = 0x10,
a935c052 3873 .global1_addr = 0x1b,
acddbd21 3874 .age_time_coeff = 15000,
dc30c35b 3875 .g1_irqs = 9,
443d5a1b 3876 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3877 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3878 .ops = &mv88e6123_ops,
f81ec90f
VD		 3879 },
3880
3881 [MV88E6131] = {
3882 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3883 .family = MV88E6XXX_FAMILY_6185,
3884 .name = "Marvell 88E6131",
3885 .num_databases = 256,
3886 .num_ports = 8,
9dddd478 3887 .port_base_addr = 0x10,
a935c052 3888 .global1_addr = 0x1b,
acddbd21 3889 .age_time_coeff = 15000,
dc30c35b 3890 .g1_irqs = 9,
443d5a1b 3891 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3892 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3893 .ops = &mv88e6131_ops,
f81ec90f
VD		 3894 },
3895
3896 [MV88E6161] = {
3897 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3898 .family = MV88E6XXX_FAMILY_6165,
3899 .name = "Marvell 88E6161",
3900 .num_databases = 4096,
3901 .num_ports = 6,
9dddd478 3902 .port_base_addr = 0x10,
a935c052 3903 .global1_addr = 0x1b,
acddbd21 3904 .age_time_coeff = 15000,
dc30c35b 3905 .g1_irqs = 9,
443d5a1b 3906 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3907 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3908 .ops = &mv88e6161_ops,
f81ec90f
VD		 3909 },
3910
3911 [MV88E6165] = {
3912 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3913 .family = MV88E6XXX_FAMILY_6165,
3914 .name = "Marvell 88E6165",
3915 .num_databases = 4096,
3916 .num_ports = 6,
9dddd478 3917 .port_base_addr = 0x10,
a935c052 3918 .global1_addr = 0x1b,
acddbd21 3919 .age_time_coeff = 15000,
dc30c35b 3920 .g1_irqs = 9,
443d5a1b 3921 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3922 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3923 .ops = &mv88e6165_ops,
f81ec90f
VD		 3924 },
3925
3926 [MV88E6171] = {
3927 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3928 .family = MV88E6XXX_FAMILY_6351,
3929 .name = "Marvell 88E6171",
3930 .num_databases = 4096,
3931 .num_ports = 7,
9dddd478 3932 .port_base_addr = 0x10,
a935c052 3933 .global1_addr = 0x1b,
acddbd21 3934 .age_time_coeff = 15000,
dc30c35b 3935 .g1_irqs = 9,
443d5a1b 3936 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3937 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3938 .ops = &mv88e6171_ops,
f81ec90f
VD		 3939 },
3940
3941 [MV88E6172] = {
3942 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3943 .family = MV88E6XXX_FAMILY_6352,
3944 .name = "Marvell 88E6172",
3945 .num_databases = 4096,
3946 .num_ports = 7,
9dddd478 3947 .port_base_addr = 0x10,
a935c052 3948 .global1_addr = 0x1b,
acddbd21 3949 .age_time_coeff = 15000,
dc30c35b 3950 .g1_irqs = 9,
443d5a1b 3951 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3952 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3953 .ops = &mv88e6172_ops,
f81ec90f
VD		 3954 },
3955
3956 [MV88E6175] = {
3957 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3958 .family = MV88E6XXX_FAMILY_6351,
3959 .name = "Marvell 88E6175",
3960 .num_databases = 4096,
3961 .num_ports = 7,
9dddd478 3962 .port_base_addr = 0x10,
a935c052 3963 .global1_addr = 0x1b,
acddbd21 3964 .age_time_coeff = 15000,
dc30c35b 3965 .g1_irqs = 9,
443d5a1b 3966 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3967 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3968 .ops = &mv88e6175_ops,
f81ec90f
VD		 3969 },
3970
3971 [MV88E6176] = {
3972 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3973 .family = MV88E6XXX_FAMILY_6352,
3974 .name = "Marvell 88E6176",
3975 .num_databases = 4096,
3976 .num_ports = 7,
9dddd478 3977 .port_base_addr = 0x10,
a935c052 3978 .global1_addr = 0x1b,
acddbd21 3979 .age_time_coeff = 15000,
dc30c35b 3980 .g1_irqs = 9,
443d5a1b 3981 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3982 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3983 .ops = &mv88e6176_ops,
f81ec90f
VD		 3984 },
3985
3986 [MV88E6185] = {
3987 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3988 .family = MV88E6XXX_FAMILY_6185,
3989 .name = "Marvell 88E6185",
3990 .num_databases = 256,
3991 .num_ports = 10,
9dddd478 3992 .port_base_addr = 0x10,
a935c052 3993 .global1_addr = 0x1b,
acddbd21 3994 .age_time_coeff = 15000,
dc30c35b 3995 .g1_irqs = 8,
443d5a1b 3996 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3997 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3998 .ops = &mv88e6185_ops,
f81ec90f
VD		 3999 },
4000
1a3b39ec
AL		 4001 [MV88E6190] = {
4002 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
4003 .family = MV88E6XXX_FAMILY_6390,
4004 .name = "Marvell 88E6190",
4005 .num_databases = 4096,
4006 .num_ports = 11, /* 10 + Z80 */
4007 .port_base_addr = 0x0,
4008 .global1_addr = 0x1b,
443d5a1b 4009 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 4010 .age_time_coeff = 3750,
1a3b39ec
AL		 4011 .g1_irqs = 9,
4012 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4013 .ops = &mv88e6190_ops,
4014 },
4015
4016 [MV88E6190X] = {
4017 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
4018 .family = MV88E6XXX_FAMILY_6390,
4019 .name = "Marvell 88E6190X",
4020 .num_databases = 4096,
4021 .num_ports = 11, /* 10 + Z80 */
4022 .port_base_addr = 0x0,
4023 .global1_addr = 0x1b,
b91e055c 4024 .age_time_coeff = 3750,
1a3b39ec 4025 .g1_irqs = 9,
443d5a1b 4026 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4027 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4028 .ops = &mv88e6190x_ops,
4029 },
4030
4031 [MV88E6191] = {
4032 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
4033 .family = MV88E6XXX_FAMILY_6390,
4034 .name = "Marvell 88E6191",
4035 .num_databases = 4096,
4036 .num_ports = 11, /* 10 + Z80 */
4037 .port_base_addr = 0x0,
4038 .global1_addr = 0x1b,
b91e055c 4039 .age_time_coeff = 3750,
443d5a1b
AL		 4040 .g1_irqs = 9,
4041 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4042 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4043 .ops = &mv88e6391_ops,
4044 },
4045
f81ec90f
VD		 4046 [MV88E6240] = {
4047 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
4048 .family = MV88E6XXX_FAMILY_6352,
4049 .name = "Marvell 88E6240",
4050 .num_databases = 4096,
4051 .num_ports = 7,
9dddd478 4052 .port_base_addr = 0x10,
a935c052 4053 .global1_addr = 0x1b,
acddbd21 4054 .age_time_coeff = 15000,
dc30c35b 4055 .g1_irqs = 9,
443d5a1b 4056 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4057 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4058 .ops = &mv88e6240_ops,
f81ec90f
VD		 4059 },
4060
1a3b39ec
AL		 4061 [MV88E6290] = {
4062 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4063 .family = MV88E6XXX_FAMILY_6390,
4064 .name = "Marvell 88E6290",
4065 .num_databases = 4096,
4066 .num_ports = 11, /* 10 + Z80 */
4067 .port_base_addr = 0x0,
4068 .global1_addr = 0x1b,
b91e055c 4069 .age_time_coeff = 3750,
1a3b39ec 4070 .g1_irqs = 9,
443d5a1b 4071 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4072 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4073 .ops = &mv88e6290_ops,
4074 },
4075
f81ec90f
VD		 4076 [MV88E6320] = {
4077 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4078 .family = MV88E6XXX_FAMILY_6320,
4079 .name = "Marvell 88E6320",
4080 .num_databases = 4096,
4081 .num_ports = 7,
9dddd478 4082 .port_base_addr = 0x10,
a935c052 4083 .global1_addr = 0x1b,
acddbd21 4084 .age_time_coeff = 15000,
dc30c35b 4085 .g1_irqs = 8,
443d5a1b 4086 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4087 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4088 .ops = &mv88e6320_ops,
f81ec90f
VD		 4089 },
4090
4091 [MV88E6321] = {
4092 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4093 .family = MV88E6XXX_FAMILY_6320,
4094 .name = "Marvell 88E6321",
4095 .num_databases = 4096,
4096 .num_ports = 7,
9dddd478 4097 .port_base_addr = 0x10,
a935c052 4098 .global1_addr = 0x1b,
acddbd21 4099 .age_time_coeff = 15000,
dc30c35b 4100 .g1_irqs = 8,
443d5a1b 4101 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4102 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 4103 .ops = &mv88e6321_ops,
f81ec90f
VD		 4104 },
4105
1558727a
GC		 4106 [MV88E6141] = {
4107 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
4108 .family = MV88E6XXX_FAMILY_6341,
4109 .name = "Marvell 88E6341",
4110 .num_databases = 4096,
4111 .num_ports = 6,
4112 .port_base_addr = 0x10,
4113 .global1_addr = 0x1b,
4114 .age_time_coeff = 3750,
4115 .tag_protocol = DSA_TAG_PROTO_EDSA,
4116 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4117 .ops = &mv88e6141_ops,
4118 },
4119
a75961d0
GC		 4120 [MV88E6341] = {
4121 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
4122 .family = MV88E6XXX_FAMILY_6341,
4123 .name = "Marvell 88E6341",
4124 .num_databases = 4096,
4125 .num_ports = 6,
4126 .port_base_addr = 0x10,
4127 .global1_addr = 0x1b,
4128 .age_time_coeff = 3750,
4129 .tag_protocol = DSA_TAG_PROTO_EDSA,
4130 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4131 .ops = &mv88e6341_ops,
4132 },
4133
f81ec90f
VD		 4134 [MV88E6350] = {
4135 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4136 .family = MV88E6XXX_FAMILY_6351,
4137 .name = "Marvell 88E6350",
4138 .num_databases = 4096,
4139 .num_ports = 7,
9dddd478 4140 .port_base_addr = 0x10,
a935c052 4141 .global1_addr = 0x1b,
acddbd21 4142 .age_time_coeff = 15000,
dc30c35b 4143 .g1_irqs = 9,
443d5a1b 4144 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4145 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4146 .ops = &mv88e6350_ops,
f81ec90f
VD		 4147 },
4148
4149 [MV88E6351] = {
4150 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4151 .family = MV88E6XXX_FAMILY_6351,
4152 .name = "Marvell 88E6351",
4153 .num_databases = 4096,
4154 .num_ports = 7,
9dddd478 4155 .port_base_addr = 0x10,
a935c052 4156 .global1_addr = 0x1b,
acddbd21 4157 .age_time_coeff = 15000,
dc30c35b 4158 .g1_irqs = 9,
443d5a1b 4159 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4160 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 4161 .ops = &mv88e6351_ops,
f81ec90f
VD		 4162 },
4163
4164 [MV88E6352] = {
4165 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4166 .family = MV88E6XXX_FAMILY_6352,
4167 .name = "Marvell 88E6352",
4168 .num_databases = 4096,
4169 .num_ports = 7,
9dddd478 4170 .port_base_addr = 0x10,
a935c052 4171 .global1_addr = 0x1b,
acddbd21 4172 .age_time_coeff = 15000,
dc30c35b 4173 .g1_irqs = 9,
443d5a1b 4174 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 4175 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 4176 .ops = &mv88e6352_ops,
f81ec90f 4177 },
1a3b39ec
AL		 4178 [MV88E6390] = {
4179 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4180 .family = MV88E6XXX_FAMILY_6390,
4181 .name = "Marvell 88E6390",
4182 .num_databases = 4096,
4183 .num_ports = 11, /* 10 + Z80 */
4184 .port_base_addr = 0x0,
4185 .global1_addr = 0x1b,
b91e055c 4186 .age_time_coeff = 3750,
1a3b39ec 4187 .g1_irqs = 9,
443d5a1b 4188 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4189 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4190 .ops = &mv88e6390_ops,
4191 },
4192 [MV88E6390X] = {
4193 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4194 .family = MV88E6XXX_FAMILY_6390,
4195 .name = "Marvell 88E6390X",
4196 .num_databases = 4096,
4197 .num_ports = 11, /* 10 + Z80 */
4198 .port_base_addr = 0x0,
4199 .global1_addr = 0x1b,
b91e055c 4200 .age_time_coeff = 3750,
1a3b39ec 4201 .g1_irqs = 9,
443d5a1b 4202 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 4203 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4204 .ops = &mv88e6390x_ops,
4205 },
f81ec90f
VD		 4206};
4207
5f7c0367 4208static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 4209{
a439c061 4210 int i;
b9b37713 4211
5f7c0367
VD		 4212 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4213 if (mv88e6xxx_table[i].prod_num == prod_num)
4214 return &mv88e6xxx_table[i];
b9b37713 4215
b9b37713
VD		 4216 return NULL;
4217}
4218
fad09c73 4219static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 4220{
4221 const struct mv88e6xxx_info *info;
8f6345b2
VD		 4222 unsigned int prod_num, rev;
4223 u16 id;
4224 int err;
bc46a3d5 4225
8f6345b2
VD		 4226 mutex_lock(&chip->reg_lock);
4227 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4228 mutex_unlock(&chip->reg_lock);
4229 if (err)
4230 return err;
bc46a3d5
VD		 4231
4232 prod_num = (id & 0xfff0) >> 4;
4233 rev = id & 0x000f;
4234
4235 info = mv88e6xxx_lookup_info(prod_num);
4236 if (!info)
4237 return -ENODEV;
4238
caac8545 4239 /* Update the compatible info with the probed one */
fad09c73 4240 chip->info = info;
bc46a3d5 4241
ca070c10
VD		 4242 err = mv88e6xxx_g2_require(chip);
4243 if (err)
4244 return err;
4245
fad09c73
VD		 4246 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4247 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 4248
4249 return 0;
4250}
4251
fad09c73 4252static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 4253{
fad09c73 4254 struct mv88e6xxx_chip *chip;
469d729f 4255
fad09c73
VD		 4256 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4257 if (!chip)
469d729f
VD		 4258 return NULL;
4259
fad09c73 4260 chip->dev = dev;
469d729f 4261
fad09c73 4262 mutex_init(&chip->reg_lock);
a3c53be5 4263 INIT_LIST_HEAD(&chip->mdios);
469d729f 4264
fad09c73 4265 return chip;
469d729f
VD		 4266}
4267
e57e5e77
VD		 4268static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4269{
a199d8b6 4270 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
e57e5e77 4271 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 4272}
4273
930188ce
AL		 4274static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4275{
a199d8b6 4276 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
930188ce 4277 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 4278}
4279
fad09c73 4280static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 4281 struct mii_bus *bus, int sw_addr)
4282{
914b32f6 4283 if (sw_addr == 0)
fad09c73 4284 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 4285 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 4286 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 4287 else
4288 return -EINVAL;
4289
fad09c73
VD		 4290 chip->bus = bus;
4291 chip->sw_addr = sw_addr;
4a70c4ab
VD		 4292
4293 return 0;
4294}
4295
7b314362
AL		 4296static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4297{
04bed143 4298 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 4299
443d5a1b 4300 return chip->info->tag_protocol;
7b314362
AL		 4301}
4302
fcdce7d0
AL		 4303static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4304 struct device *host_dev, int sw_addr,
4305 void **priv)
a77d43f1 4306{
fad09c73 4307 struct mv88e6xxx_chip *chip;
a439c061 4308 struct mii_bus *bus;
b516d453 4309 int err;
a77d43f1 4310
a439c061 4311 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 4312 if (!bus)
4313 return NULL;
4314
fad09c73
VD		 4315 chip = mv88e6xxx_alloc_chip(dsa_dev);
4316 if (!chip)
469d729f
VD		 4317 return NULL;
4318
caac8545 4319 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 4320 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 4321
fad09c73 4322 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 4323 if (err)
4324 goto free;
4325
fad09c73 4326 err = mv88e6xxx_detect(chip);
bc46a3d5 4327 if (err)
469d729f 4328 goto free;
a439c061 4329
dc30c35b
AL		 4330 mutex_lock(&chip->reg_lock);
4331 err = mv88e6xxx_switch_reset(chip);
4332 mutex_unlock(&chip->reg_lock);
4333 if (err)
4334 goto free;
4335
e57e5e77
VD		 4336 mv88e6xxx_phy_init(chip);
4337
a3c53be5 4338 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 4339 if (err)
469d729f 4340 goto free;
b516d453 4341
fad09c73 4342 *priv = chip;
a439c061 4343
fad09c73 4344 return chip->info->name;
469d729f 4345free:
fad09c73 4346 devm_kfree(dsa_dev, chip);
469d729f
VD		 4347
4348 return NULL;
a77d43f1
AL		 4349}
4350
7df8fbdd
VD		 4351static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4352 const struct switchdev_obj_port_mdb *mdb,
4353 struct switchdev_trans *trans)
4354{
4355 /* We don't need any dynamic resource from the kernel (yet),
4356 * so skip the prepare phase.
4357 */
4358
4359 return 0;
4360}
4361
4362static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4363 const struct switchdev_obj_port_mdb *mdb,
4364 struct switchdev_trans *trans)
4365{
04bed143 4366 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4367
4368 mutex_lock(&chip->reg_lock);
4369 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4370 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4371 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4372 mutex_unlock(&chip->reg_lock);
4373}
4374
4375static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4376 const struct switchdev_obj_port_mdb *mdb)
4377{
04bed143 4378 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4379 int err;
4380
4381 mutex_lock(&chip->reg_lock);
4382 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4383 GLOBAL_ATU_DATA_STATE_UNUSED);
4384 mutex_unlock(&chip->reg_lock);
4385
4386 return err;
4387}
4388
4389static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4390 struct switchdev_obj_port_mdb *mdb,
4391 int (*cb)(struct switchdev_obj *obj))
4392{
04bed143 4393 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 4394 int err;
4395
4396 mutex_lock(&chip->reg_lock);
4397 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4398 mutex_unlock(&chip->reg_lock);
4399
4400 return err;
4401}
4402
a82f67af 4403static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 4404 .probe = mv88e6xxx_drv_probe,
7b314362 4405 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 4406 .setup = mv88e6xxx_setup,
4407 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 4408 .adjust_link = mv88e6xxx_adjust_link,
4409 .get_strings = mv88e6xxx_get_strings,
4410 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4411 .get_sset_count = mv88e6xxx_get_sset_count,
4412 .set_eee = mv88e6xxx_set_eee,
4413 .get_eee = mv88e6xxx_get_eee,
f8cd8753 4414 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 4415 .get_eeprom = mv88e6xxx_get_eeprom,
4416 .set_eeprom = mv88e6xxx_set_eeprom,
4417 .get_regs_len = mv88e6xxx_get_regs_len,
4418 .get_regs = mv88e6xxx_get_regs,
2cfcd964 4419 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 4420 .port_bridge_join = mv88e6xxx_port_bridge_join,
4421 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4422 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 4423 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 4424 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4425 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4426 .port_vlan_add = mv88e6xxx_port_vlan_add,
4427 .port_vlan_del = mv88e6xxx_port_vlan_del,
4428 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4429 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4430 .port_fdb_add = mv88e6xxx_port_fdb_add,
4431 .port_fdb_del = mv88e6xxx_port_fdb_del,
4432 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 4433 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4434 .port_mdb_add = mv88e6xxx_port_mdb_add,
4435 .port_mdb_del = mv88e6xxx_port_mdb_del,
4436 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 4437};
4438
ab3d408d
FF		 4439static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4440 .ops = &mv88e6xxx_switch_ops,
4441};
4442
55ed0ce0 4443static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4444{
fad09c73 4445 struct device *dev = chip->dev;
b7e66a5f
VD		 4446 struct dsa_switch *ds;
4447
a0c02161 4448 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
b7e66a5f
VD		 4449 if (!ds)
4450 return -ENOMEM;
4451
fad09c73 4452 ds->priv = chip;
9d490b4e 4453 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 4454
4455 dev_set_drvdata(dev, ds);
4456
55ed0ce0 4457 return dsa_register_switch(ds, dev);
b7e66a5f
VD		 4458}
4459
fad09c73 4460static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4461{
fad09c73 4462 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4463}
4464
57d32310 4465static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4466{
14c7b3c3 4467 struct device *dev = &mdiodev->dev;
f8cd8753 4468 struct device_node *np = dev->of_node;
caac8545 4469 const struct mv88e6xxx_info *compat_info;
fad09c73 4470 struct mv88e6xxx_chip *chip;
f8cd8753 4471 u32 eeprom_len;
52638f71 4472 int err;
14c7b3c3 4473
caac8545
VD		 4474 compat_info = of_device_get_match_data(dev);
4475 if (!compat_info)
4476 return -EINVAL;
4477
fad09c73
VD		 4478 chip = mv88e6xxx_alloc_chip(dev);
4479 if (!chip)
14c7b3c3
AL		 4480 return -ENOMEM;
4481
fad09c73 4482 chip->info = compat_info;
caac8545 4483
56995cbc
AL		 4484 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4485 if (err)
4486 return err;
4487
fad09c73 4488 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4489 if (err)
4490 return err;
14c7b3c3 4491
b4308f04
AL		 4492 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4493 if (IS_ERR(chip->reset))
4494 return PTR_ERR(chip->reset);
4495
fad09c73 4496 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4497 if (err)
4498 return err;
14c7b3c3 4499
e57e5e77
VD		 4500 mv88e6xxx_phy_init(chip);
4501
ee4dc2e7 4502 if (chip->info->ops->get_eeprom &&
f8cd8753 4503 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4504 chip->eeprom_len = eeprom_len;
f8cd8753 4505
dc30c35b
AL		 4506 mutex_lock(&chip->reg_lock);
4507 err = mv88e6xxx_switch_reset(chip);
4508 mutex_unlock(&chip->reg_lock);
4509 if (err)
4510 goto out;
4511
4512 chip->irq = of_irq_get(np, 0);
4513 if (chip->irq == -EPROBE_DEFER) {
4514 err = chip->irq;
4515 goto out;
4516 }
4517
4518 if (chip->irq > 0) {
4519 /* Has to be performed before the MDIO bus is created,
4520 * because the PHYs will link there interrupts to these
4521 * interrupt controllers
4522 */
4523 mutex_lock(&chip->reg_lock);
4524 err = mv88e6xxx_g1_irq_setup(chip);
4525 mutex_unlock(&chip->reg_lock);
4526
4527 if (err)
4528 goto out;
4529
4530 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4531 err = mv88e6xxx_g2_irq_setup(chip);
4532 if (err)
4533 goto out_g1_irq;
4534 }
4535 }
4536
a3c53be5 4537 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4538 if (err)
dc30c35b 4539 goto out_g2_irq;
b516d453 4540
55ed0ce0 4541 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4542 if (err)
4543 goto out_mdio;
83c0afae 4544
98e67308 4545 return 0;
dc30c35b
AL		 4546
4547out_mdio:
a3c53be5 4548 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4549out_g2_irq:
46712644 4550 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 4551 mv88e6xxx_g2_irq_free(chip);
4552out_g1_irq:
61f7c3f8
AL		 4553 if (chip->irq > 0) {
4554 mutex_lock(&chip->reg_lock);
46712644 4555 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4556 mutex_unlock(&chip->reg_lock);
4557 }
dc30c35b
AL		 4558out:
4559 return err;
98e67308 4560}
14c7b3c3
AL		 4561
4562static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4563{
4564 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4565 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4566
930188ce 4567 mv88e6xxx_phy_destroy(chip);
fad09c73 4568 mv88e6xxx_unregister_switch(chip);
a3c53be5 4569 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4570
46712644
AL		 4571 if (chip->irq > 0) {
4572 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4573 mv88e6xxx_g2_irq_free(chip);
4574 mv88e6xxx_g1_irq_free(chip);
4575 }
14c7b3c3
AL		 4576}
4577
4578static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4579 {
4580 .compatible = "marvell,mv88e6085",
4581 .data = &mv88e6xxx_table[MV88E6085],
4582 },
1a3b39ec
AL		 4583 {
4584 .compatible = "marvell,mv88e6190",
4585 .data = &mv88e6xxx_table[MV88E6190],
4586 },
14c7b3c3
AL		 4587 { /* sentinel */ },
4588};
4589
4590MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4591
4592static struct mdio_driver mv88e6xxx_driver = {
4593 .probe = mv88e6xxx_probe,
4594 .remove = mv88e6xxx_remove,
4595 .mdiodrv.driver = {
4596 .name = "mv88e6085",
4597 .of_match_table = mv88e6xxx_of_match,
4598 },
4599};
4600
4601static int __init mv88e6xxx_init(void)
4602{
ab3d408d 4603 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4604 return mdio_driver_register(&mv88e6xxx_driver);
4605}
98e67308
BH		 4606module_init(mv88e6xxx_init);
4607
4608static void __exit mv88e6xxx_cleanup(void)
4609{
14c7b3c3 4610 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4611 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4612}
4613module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4614
4615MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4616MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4617MODULE_LICENSE("GPL");
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