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Merge branch 'net-next-stmmac-dwmac-sun8i-add-support-for-V3s'
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
ec561276 35
4d5f2ba7 36#include "chip.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
6d91782f 41#include "serdes.h"
91da11f8 42
fad09c73 43static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 44{
fad09c73
VD		 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 47 dump_stack();
48 }
49}
50
914b32f6
VD		 51/* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 *
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 *
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 61 */
914b32f6 62
fad09c73 63static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 *val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 val)
74{
fad09c73 75 if (!chip->smi_ops)
914b32f6
VD		 76 return -EOPNOTSUPP;
77
fad09c73 78 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 79}
80
fad09c73 81static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 82 int addr, int reg, u16 *val)
83{
84 int ret;
85
fad09c73 86 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 87 if (ret < 0)
88 return ret;
89
90 *val = ret & 0xffff;
91
92 return 0;
93}
94
fad09c73 95static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 96 int addr, int reg, u16 val)
97{
98 int ret;
99
fad09c73 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 101 if (ret < 0)
102 return ret;
103
104 return 0;
105}
106
c08026ab 107static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
110};
111
fad09c73 112static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 113{
114 int ret;
115 int i;
116
117 for (i = 0; i < 16; i++) {
fad09c73 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 119 if (ret < 0)
120 return ret;
121
cca8b133 122 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 123 return 0;
124 }
125
126 return -ETIMEDOUT;
127}
128
fad09c73 129static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 130 int addr, int reg, u16 *val)
91da11f8
LB		 131{
132 int ret;
133
3675c8d7 134 /* Wait for the bus to become free. */
fad09c73 135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the read command. */
fad09c73 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the read command to complete. */
fad09c73 146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 147 if (ret < 0)
148 return ret;
149
3675c8d7 150 /* Read the data. */
fad09c73 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 152 if (ret < 0)
153 return ret;
154
914b32f6 155 *val = ret & 0xffff;
91da11f8 156
914b32f6 157 return 0;
8d6d09e7
GR		 158}
159
fad09c73 160static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 161 int addr, int reg, u16 val)
91da11f8
LB		 162{
163 int ret;
164
3675c8d7 165 /* Wait for the bus to become free. */
fad09c73 166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 167 if (ret < 0)
168 return ret;
169
3675c8d7 170 /* Transmit the data to write. */
fad09c73 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Transmit the write command. */
fad09c73 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 178 if (ret < 0)
179 return ret;
180
3675c8d7 181 /* Wait for the write command to complete. */
fad09c73 182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 183 if (ret < 0)
184 return ret;
185
186 return 0;
187}
188
c08026ab 189static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
192};
193
ec561276 194int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 195{
196 int err;
197
fad09c73 198 assert_reg_lock(chip);
914b32f6 199
fad09c73 200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 201 if (err)
202 return err;
203
fad09c73 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 205 addr, reg, *val);
206
207 return 0;
208}
209
ec561276 210int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 211{
914b32f6
VD		 212 int err;
213
fad09c73 214 assert_reg_lock(chip);
91da11f8 215
fad09c73 216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 217 if (err)
218 return err;
219
fad09c73 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 221 addr, reg, val);
222
914b32f6
VD		 223 return 0;
224}
225
10fa5bfc 226struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 227{
228 struct mv88e6xxx_mdio_bus *mdio_bus;
229
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
231 list);
232 if (!mdio_bus)
233 return NULL;
234
235 return mdio_bus->bus;
236}
237
dc30c35b
AL		 238static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
239{
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
242
243 chip->g1_irq.masked |= (1 << n);
244}
245
246static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
247{
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
250
251 chip->g1_irq.masked &= ~(1 << n);
252}
253
254static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
255{
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
259 unsigned int n;
260 u16 reg;
261 int err;
262
263 mutex_lock(&chip->reg_lock);
82466921 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b
AL		 265 mutex_unlock(&chip->reg_lock);
266
267 if (err)
268 goto out;
269
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
274 ++nhandled;
275 }
276 }
277out:
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
279}
280
281static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
282{
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
284
285 mutex_lock(&chip->reg_lock);
286}
287
288static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
289{
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
292 u16 reg;
293 int err;
294
d77f4321 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 296 if (err)
297 goto out;
298
299 reg &= ~mask;
300 reg |= (~chip->g1_irq.masked & mask);
301
d77f4321 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 303 if (err)
304 goto out;
305
306out:
307 mutex_unlock(&chip->reg_lock);
308}
309
310static struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
316};
317
318static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
319 unsigned int irq,
320 irq_hw_number_t hwirq)
321{
322 struct mv88e6xxx_chip *chip = d->host_data;
323
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
327
328 return 0;
329}
330
331static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
334};
335
336static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
337{
338 int irq, virq;
3460a577
AL		 339 u16 mask;
340
d77f4321 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3460a577 342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577
AL		 344
345 free_irq(chip->irq, chip);
dc30c35b 346
5edef2f2 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 349 irq_dispose_mapping(virq);
350 }
351
a3db3d3a 352 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 353}
354
355static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
356{
3dd0ef05
AL		 357 int err, irq, virq;
358 u16 reg, mask;
dc30c35b
AL		 359
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
365 return -ENOMEM;
366
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
369
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
372
d77f4321 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 374 if (err)
3dd0ef05 375 goto out_mapping;
dc30c35b 376
3dd0ef05 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 378
d77f4321 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 380 if (err)
3dd0ef05 381 goto out_disable;
dc30c35b
AL		 382
383 /* Reading the interrupt status clears (most of) them */
82466921 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 385 if (err)
3dd0ef05 386 goto out_disable;
dc30c35b
AL		 387
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
392 if (err)
3dd0ef05 393 goto out_disable;
dc30c35b
AL		 394
395 return 0;
396
3dd0ef05
AL		 397out_disable:
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 400
401out_mapping:
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
405 }
406
407 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 408
409 return err;
410}
411
ec561276 412int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 413{
6441e669 414 int i;
2d79af6e 415
6441e669 416 for (i = 0; i < 16; i++) {
2d79af6e
VD		 417 u16 val;
418 int err;
419
420 err = mv88e6xxx_read(chip, addr, reg, &val);
421 if (err)
422 return err;
423
424 if (!(val & mask))
425 return 0;
426
427 usleep_range(1000, 2000);
428 }
429
30853553 430 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 431 return -ETIMEDOUT;
432}
433
f22ab641 434/* Indirect write to single pointer-data register with an Update bit */
ec561276 435int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 436{
437 u16 val;
0f02b4f7 438 int err;
f22ab641
VD		 439
440 /* Wait until the previous operation is completed */
0f02b4f7
AL		 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
442 if (err)
443 return err;
f22ab641
VD		 444
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
447
448 return mv88e6xxx_write(chip, addr, reg, val);
449}
450
d78343d2
VD		 451static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
454{
455 int err;
456
457 if (!chip->info->ops->port_set_link)
458 return 0;
459
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
462 if (err)
463 return err;
464
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
468 goto restore_link;
469 }
470
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
474 goto restore_link;
475 }
476
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
480 goto restore_link;
481 }
482
f39908d3
AL		 483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
486 goto restore_link;
487 }
488
d78343d2
VD		 489 err = 0;
490restore_link:
491 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 493
494 return err;
495}
496
dea87024
AL		 497/* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
500 */
f81ec90f
VD		 501static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
dea87024 503{
04bed143 504 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 505 int err;
dea87024
AL		 506
507 if (!phy_is_pseudo_fixed_link(phydev))
508 return;
509
fad09c73 510 mutex_lock(&chip->reg_lock);
d78343d2
VD		 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
fad09c73 513 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 514
515 if (err && err != -EOPNOTSUPP)
774439e5 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
dea87024
AL		 517}
518
a605a0fe 519static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 520{
a605a0fe
AL		 521 if (!chip->info->ops->stats_snapshot)
522 return -EOPNOTSUPP;
91da11f8 523
a605a0fe 524 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 525}
526
e413e7e1 527static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 587};
588
fad09c73 589static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 590 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 591 int port, u16 bank1_select,
592 u16 histogram)
80c4627b 593{
80c4627b
AL		 594 u32 low;
595 u32 high = 0;
dfafe449 596 u16 reg = 0;
0e7b9925 597 int err;
80c4627b
AL		 598 u64 value;
599
f5e2ed02 600 switch (s->type) {
dfafe449 601 case STATS_TYPE_PORT:
0e7b9925
AL		 602 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
603 if (err)
80c4627b
AL		 604 return UINT64_MAX;
605
0e7b9925 606 low = reg;
80c4627b 607 if (s->sizeof_stat == 4) {
0e7b9925
AL		 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
609 if (err)
80c4627b 610 return UINT64_MAX;
0e7b9925 611 high = reg;
80c4627b 612 }
f5e2ed02 613 break;
dfafe449 614 case STATS_TYPE_BANK1:
e0d8b615 615 reg = bank1_select;
dfafe449
AL		 616 /* fall through */
617 case STATS_TYPE_BANK0:
e0d8b615 618 reg |= s->reg | histogram;
7f9ef3af 619 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 620 if (s->sizeof_stat == 8)
7f9ef3af 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 622 break;
623 default:
624 return UINT64_MAX;
80c4627b
AL		 625 }
626 value = (((u64)high) << 16) | low;
627 return value;
628}
629
dfafe449
AL		 630static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
91da11f8 632{
f5e2ed02
AL		 633 struct mv88e6xxx_hw_stat *stat;
634 int i, j;
91da11f8 635
f5e2ed02
AL		 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
dfafe449 638 if (stat->type & types) {
f5e2ed02
AL		 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
640 ETH_GSTRING_LEN);
641 j++;
642 }
91da11f8 643 }
e413e7e1
AL		 644}
645
dfafe449
AL		 646static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
647 uint8_t *data)
648{
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
651}
652
653static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
654 uint8_t *data)
655{
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
658}
659
660static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
661 uint8_t *data)
e413e7e1 662{
04bed143 663 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 664
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
667}
668
669static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
670 int types)
671{
f5e2ed02
AL		 672 struct mv88e6xxx_hw_stat *stat;
673 int i, j;
674
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
dfafe449 677 if (stat->type & types)
f5e2ed02
AL		 678 j++;
679 }
680 return j;
e413e7e1
AL		 681}
682
dfafe449
AL		 683static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
684{
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
686 STATS_TYPE_PORT);
687}
688
689static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
690{
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
692 STATS_TYPE_BANK1);
693}
694
695static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
696{
697 struct mv88e6xxx_chip *chip = ds->priv;
698
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
701
702 return 0;
703}
704
052f947f 705static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
052f947f
AL		 708{
709 struct mv88e6xxx_hw_stat *stat;
710 int i, j;
711
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
e0d8b615
AL		 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
716 bank1_select,
717 histogram);
052f947f
AL		 718 j++;
719 }
720 }
721}
722
723static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
724 uint64_t *data)
725{
726 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 729}
730
731static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
732 uint64_t *data)
733{
734 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 738}
739
740static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
741 uint64_t *data)
742{
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
746 0);
052f947f
AL		 747}
748
749static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
750 uint64_t *data)
751{
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
754}
755
f81ec90f
VD		 756static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
757 uint64_t *data)
e413e7e1 758{
04bed143 759 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 760 int ret;
f5e2ed02 761
fad09c73 762 mutex_lock(&chip->reg_lock);
f5e2ed02 763
a605a0fe 764 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 765 if (ret < 0) {
fad09c73 766 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 767 return;
768 }
052f947f
AL		 769
770 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 771
fad09c73 772 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 773}
774
de227387
AL		 775static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
776{
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
779
780 return 0;
781}
782
f81ec90f 783static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 784{
785 return 32 * sizeof(u16);
786}
787
f81ec90f
VD		 788static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
a1ab91f3 790{
04bed143 791 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 792 int err;
793 u16 reg;
a1ab91f3
GR		 794 u16 *p = _p;
795 int i;
796
797 regs->version = 0;
798
799 memset(p, 0xff, 32 * sizeof(u16));
800
fad09c73 801 mutex_lock(&chip->reg_lock);
23062513 802
a1ab91f3 803 for (i = 0; i < 32; i++) {
a1ab91f3 804
0e7b9925
AL		 805 err = mv88e6xxx_port_read(chip, port, i, &reg);
806 if (!err)
807 p[i] = reg;
a1ab91f3 808 }
23062513 809
fad09c73 810 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 811}
812
f81ec90f
VD		 813static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
814 struct ethtool_eee *e)
11b3b45d 815{
04bed143 816 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 817 u16 reg;
818 int err;
11b3b45d 819
fad09c73 820 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 821 return -EOPNOTSUPP;
822
fad09c73 823 mutex_lock(&chip->reg_lock);
2f40c698 824
9c93829c
VD		 825 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
826 if (err)
2f40c698 827 goto out;
11b3b45d
GR		 828
829 e->eee_enabled = !!(reg & 0x0200);
830 e->tx_lpi_enabled = !!(reg & 0x0100);
831
5f83dc93 832 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
9c93829c 833 if (err)
2f40c698 834 goto out;
11b3b45d 835
5f83dc93 836 e->eee_active = !!(reg & MV88E6352_PORT_STS_EEE);
2f40c698 837out:
fad09c73 838 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 839
840 return err;
11b3b45d
GR		 841}
842
f81ec90f
VD		 843static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
844 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 845{
04bed143 846 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 847 u16 reg;
848 int err;
11b3b45d 849
fad09c73 850 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 851 return -EOPNOTSUPP;
852
fad09c73 853 mutex_lock(&chip->reg_lock);
11b3b45d 854
9c93829c
VD		 855 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
856 if (err)
2f40c698
AL		 857 goto out;
858
9c93829c 859 reg &= ~0x0300;
2f40c698
AL		 860 if (e->eee_enabled)
861 reg |= 0x0200;
862 if (e->tx_lpi_enabled)
863 reg |= 0x0100;
864
9c93829c 865 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 866out:
fad09c73 867 mutex_unlock(&chip->reg_lock);
2f40c698 868
9c93829c 869 return err;
11b3b45d
GR		 870}
871
e5887a2a 872static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 873{
e5887a2a
VD		 874 struct dsa_switch *ds = NULL;
875 struct net_device *br;
876 u16 pvlan;
b7666efe
VD		 877 int i;
878
e5887a2a
VD		 879 if (dev < DSA_MAX_SWITCHES)
880 ds = chip->ds->dst->ds[dev];
881
882 /* Prevent frames from unknown switch or port */
883 if (!ds || port >= ds->num_ports)
884 return 0;
885
886 /* Frames from DSA links and CPU ports can egress any local port */
887 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
888 return mv88e6xxx_port_mask(chip);
889
890 br = ds->ports[port].bridge_dev;
891 pvlan = 0;
892
893 /* Frames from user ports can egress any local DSA links and CPU ports,
894 * as well as any local member of their bridge group.
895 */
896 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
897 if (dsa_is_cpu_port(chip->ds, i) ||
898 dsa_is_dsa_port(chip->ds, i) ||
899 (br && chip->ds->ports[i].bridge_dev == br))
900 pvlan |= BIT(i);
901
902 return pvlan;
903}
904
240ea3ef 905static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 906{
907 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 908
909 /* prevent frames from going back out of the port they came in on */
910 output_ports &= ~BIT(port);
facd95b2 911
5a7921f4 912 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 913}
914
f81ec90f
VD		 915static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
916 u8 state)
facd95b2 917{
04bed143 918 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 919 int err;
facd95b2 920
fad09c73 921 mutex_lock(&chip->reg_lock);
f894c29c 922 err = mv88e6xxx_port_set_state(chip, port, state);
fad09c73 923 mutex_unlock(&chip->reg_lock);
553eb544
VD		 924
925 if (err)
774439e5 926 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 927}
928
a2ac29d2
VD		 929static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
930{
c3a7d4ad
VD		 931 int err;
932
daefc943
VD		 933 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
934 if (err)
935 return err;
936
c3a7d4ad
VD		 937 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
938 if (err)
939 return err;
940
a2ac29d2
VD		 941 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
942}
943
17a1594e
VD		 944static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
945{
946 u16 pvlan = 0;
947
948 if (!mv88e6xxx_has_pvt(chip))
949 return -EOPNOTSUPP;
950
951 /* Skip the local source device, which uses in-chip port VLAN */
952 if (dev != chip->ds->index)
aec5ac88 953 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 954
955 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
956}
957
81228996
VD		 958static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
959{
17a1594e
VD		 960 int dev, port;
961 int err;
962
81228996
VD		 963 if (!mv88e6xxx_has_pvt(chip))
964 return 0;
965
966 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
967 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
968 */
17a1594e
VD		 969 err = mv88e6xxx_g2_misc_4_bit_port(chip);
970 if (err)
971 return err;
972
973 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
974 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
975 err = mv88e6xxx_pvt_map(chip, dev, port);
976 if (err)
977 return err;
978 }
979 }
980
981 return 0;
81228996
VD		 982}
983
749efcb8
VD		 984static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
985{
986 struct mv88e6xxx_chip *chip = ds->priv;
987 int err;
988
989 mutex_lock(&chip->reg_lock);
e606ca36 990 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 991 mutex_unlock(&chip->reg_lock);
992
993 if (err)
774439e5 994 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 995}
996
b486d7c9
VD		 997static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
998{
999 if (!chip->info->max_vid)
1000 return 0;
1001
1002 return mv88e6xxx_g1_vtu_flush(chip);
1003}
1004
f1394b78
VD		 1005static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1006 struct mv88e6xxx_vtu_entry *entry)
1007{
1008 if (!chip->info->ops->vtu_getnext)
1009 return -EOPNOTSUPP;
1010
1011 return chip->info->ops->vtu_getnext(chip, entry);
1012}
1013
0ad5daf6
VD		 1014static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1015 struct mv88e6xxx_vtu_entry *entry)
1016{
1017 if (!chip->info->ops->vtu_loadpurge)
1018 return -EOPNOTSUPP;
1019
1020 return chip->info->ops->vtu_loadpurge(chip, entry);
1021}
1022
f81ec90f
VD		 1023static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1024 struct switchdev_obj_port_vlan *vlan,
438ff537 1025 switchdev_obj_dump_cb_t *cb)
ceff5eff 1026{
04bed143 1027 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1028 struct mv88e6xxx_vtu_entry next = {
1029 .vid = chip->info->max_vid,
1030 };
ceff5eff
VD		 1031 u16 pvid;
1032 int err;
1033
3cf3c846 1034 if (!chip->info->max_vid)
54d77b5b
VD		 1035 return -EOPNOTSUPP;
1036
fad09c73 1037 mutex_lock(&chip->reg_lock);
ceff5eff 1038
77064f37 1039 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1040 if (err)
1041 goto unlock;
1042
ceff5eff 1043 do {
f1394b78 1044 err = mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1045 if (err)
1046 break;
1047
1048 if (!next.valid)
1049 break;
1050
7ec60d6e
VD		 1051 if (next.member[port] ==
1052 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
ceff5eff
VD		 1053 continue;
1054
1055 /* reinit and dump this VLAN obj */
57d32310
VD		 1056 vlan->vid_begin = next.vid;
1057 vlan->vid_end = next.vid;
ceff5eff
VD		 1058 vlan->flags = 0;
1059
7ec60d6e
VD		 1060 if (next.member[port] ==
1061 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED)
ceff5eff
VD		 1062 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1063
1064 if (next.vid == pvid)
1065 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1066
1067 err = cb(&vlan->obj);
1068 if (err)
1069 break;
3cf3c846 1070 } while (next.vid < chip->info->max_vid);
ceff5eff
VD		 1071
1072unlock:
fad09c73 1073 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1074
1075 return err;
1076}
1077
d7f435f9 1078static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1079{
1080 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
3afb4bde
VD		 1081 struct mv88e6xxx_vtu_entry vlan = {
1082 .vid = chip->info->max_vid,
1083 };
2db9ce1f 1084 int i, err;
3285f9e8
VD		 1085
1086 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1087
2db9ce1f 1088 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1089 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1090 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1091 if (err)
1092 return err;
1093
1094 set_bit(*fid, fid_bitmap);
1095 }
1096
3285f9e8 1097 /* Set every FID bit used by the VLAN entries */
3285f9e8 1098 do {
f1394b78 1099 err = mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1100 if (err)
1101 return err;
1102
1103 if (!vlan.valid)
1104 break;
1105
1106 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1107 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1108
1109 /* The reset value 0x000 is used to indicate that multiple address
1110 * databases are not needed. Return the next positive available.
1111 */
1112 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1113 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1114 return -ENOSPC;
1115
1116 /* Clear the database */
daefc943 1117 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1118}
1119
567aa59a
VD		 1120static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1121 struct mv88e6xxx_vtu_entry *entry, bool new)
2fb5ef09
VD		 1122{
1123 int err;
1124
1125 if (!vid)
1126 return -EINVAL;
1127
3afb4bde
VD		 1128 entry->vid = vid - 1;
1129 entry->valid = false;
2fb5ef09 1130
f1394b78 1131 err = mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1132 if (err)
1133 return err;
1134
567aa59a
VD		 1135 if (entry->vid == vid && entry->valid)
1136 return 0;
2fb5ef09 1137
567aa59a
VD		 1138 if (new) {
1139 int i;
1140
1141 /* Initialize a fresh VLAN entry */
1142 memset(entry, 0, sizeof(*entry));
1143 entry->valid = true;
1144 entry->vid = vid;
1145
553a768d 1146 /* Exclude all ports */
567aa59a 1147 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
553a768d 1148 entry->member[i] =
7ec60d6e 1149 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
567aa59a
VD		 1150
1151 return mv88e6xxx_atu_new(chip, &entry->fid);
2fb5ef09
VD		 1152 }
1153
567aa59a
VD		 1154 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1155 return -EOPNOTSUPP;
2fb5ef09
VD		 1156}
1157
da9c359e
VD		 1158static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1159 u16 vid_begin, u16 vid_end)
1160{
04bed143 1161 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1162 struct mv88e6xxx_vtu_entry vlan = {
1163 .vid = vid_begin - 1,
1164 };
da9c359e
VD		 1165 int i, err;
1166
1167 if (!vid_begin)
1168 return -EOPNOTSUPP;
1169
fad09c73 1170 mutex_lock(&chip->reg_lock);
da9c359e 1171
da9c359e 1172 do {
f1394b78 1173 err = mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1174 if (err)
1175 goto unlock;
1176
1177 if (!vlan.valid)
1178 break;
1179
1180 if (vlan.vid > vid_end)
1181 break;
1182
370b4ffb 1183 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1184 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1185 continue;
1186
66e2809d
AL		 1187 if (!ds->ports[port].netdev)
1188 continue;
1189
bd00e053 1190 if (vlan.member[i] ==
7ec60d6e 1191 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
da9c359e
VD		 1192 continue;
1193
fae8a25e
VD		 1194 if (ds->ports[i].bridge_dev ==
1195 ds->ports[port].bridge_dev)
da9c359e
VD		 1196 break; /* same bridge, check next VLAN */
1197
fae8a25e 1198 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1199 continue;
1200
774439e5
VD		 1201 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1202 port, vlan.vid,
1203 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1204 err = -EOPNOTSUPP;
1205 goto unlock;
1206 }
1207 } while (vlan.vid < vid_end);
1208
1209unlock:
fad09c73 1210 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1211
1212 return err;
1213}
1214
f81ec90f
VD		 1215static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1216 bool vlan_filtering)
214cdb99 1217{
04bed143 1218 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1219 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1220 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1221 int err;
214cdb99 1222
3cf3c846 1223 if (!chip->info->max_vid)
54d77b5b
VD		 1224 return -EOPNOTSUPP;
1225
fad09c73 1226 mutex_lock(&chip->reg_lock);
385a0995 1227 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1228 mutex_unlock(&chip->reg_lock);
214cdb99 1229
0e7b9925 1230 return err;
214cdb99
VD		 1231}
1232
57d32310
VD		 1233static int
1234mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1235 const struct switchdev_obj_port_vlan *vlan,
1236 struct switchdev_trans *trans)
76e398a6 1237{
04bed143 1238 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1239 int err;
1240
3cf3c846 1241 if (!chip->info->max_vid)
54d77b5b
VD		 1242 return -EOPNOTSUPP;
1243
da9c359e
VD		 1244 /* If the requested port doesn't belong to the same bridge as the VLAN
1245 * members, do not support it (yet) and fallback to software VLAN.
1246 */
1247 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1248 vlan->vid_end);
1249 if (err)
1250 return err;
1251
76e398a6
VD		 1252 /* We don't need any dynamic resource from the kernel (yet),
1253 * so skip the prepare phase.
1254 */
1255 return 0;
1256}
1257
fad09c73 1258static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
c91498e1 1259 u16 vid, u8 member)
0d3b33e6 1260{
b4e47c0f 1261 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1262 int err;
1263
567aa59a 1264 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1265 if (err)
76e398a6 1266 return err;
0d3b33e6 1267
c91498e1 1268 vlan.member[port] = member;
0d3b33e6 1269
0ad5daf6 1270 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1271}
1272
f81ec90f
VD		 1273static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1274 const struct switchdev_obj_port_vlan *vlan,
1275 struct switchdev_trans *trans)
76e398a6 1276{
04bed143 1277 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1278 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1279 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
c91498e1 1280 u8 member;
76e398a6 1281 u16 vid;
76e398a6 1282
3cf3c846 1283 if (!chip->info->max_vid)
54d77b5b
VD		 1284 return;
1285
c91498e1 1286 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 1287 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 1288 else if (untagged)
7ec60d6e 1289 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 1290 else
7ec60d6e 1291 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 1292
fad09c73 1293 mutex_lock(&chip->reg_lock);
76e398a6 1294
4d5770b3 1295 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
c91498e1 1296 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
774439e5
VD		 1297 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1298 vid, untagged ? 'u' : 't');
76e398a6 1299
77064f37 1300 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
774439e5
VD		 1301 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1302 vlan->vid_end);
0d3b33e6 1303
fad09c73 1304 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1305}
1306
fad09c73 1307static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1308 int port, u16 vid)
7dad08d7 1309{
b4e47c0f 1310 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1311 int i, err;
1312
567aa59a 1313 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1314 if (err)
76e398a6 1315 return err;
7dad08d7 1316
2fb5ef09 1317 /* Tell switchdev if this VLAN is handled in software */
7ec60d6e 1318 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1319 return -EOPNOTSUPP;
7dad08d7 1320
7ec60d6e 1321 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1322
1323 /* keep the VLAN unless all ports are excluded */
f02bdffc 1324 vlan.valid = false;
370b4ffb 1325 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 1326 if (vlan.member[i] !=
1327 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1328 vlan.valid = true;
7dad08d7
VD		 1329 break;
1330 }
1331 }
1332
0ad5daf6 1333 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1334 if (err)
1335 return err;
1336
e606ca36 1337 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1338}
1339
f81ec90f
VD		 1340static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1341 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1342{
04bed143 1343 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1344 u16 pvid, vid;
1345 int err = 0;
1346
3cf3c846 1347 if (!chip->info->max_vid)
54d77b5b
VD		 1348 return -EOPNOTSUPP;
1349
fad09c73 1350 mutex_lock(&chip->reg_lock);
76e398a6 1351
77064f37 1352 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1353 if (err)
1354 goto unlock;
1355
76e398a6 1356 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1357 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1358 if (err)
1359 goto unlock;
1360
1361 if (vid == pvid) {
77064f37 1362 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1363 if (err)
1364 goto unlock;
1365 }
1366 }
1367
7dad08d7 1368unlock:
fad09c73 1369 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1370
1371 return err;
1372}
1373
83dabd1f
VD		 1374static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1375 const unsigned char *addr, u16 vid,
1376 u8 state)
fd231c82 1377{
b4e47c0f 1378 struct mv88e6xxx_vtu_entry vlan;
88472939 1379 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1380 int err;
1381
2db9ce1f
VD		 1382 /* Null VLAN ID corresponds to the port private database */
1383 if (vid == 0)
b4e48c50 1384 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1385 else
567aa59a 1386 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1387 if (err)
1388 return err;
fd231c82 1389
27c0e600 1390 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96
VD		 1391 ether_addr_copy(entry.mac, addr);
1392 eth_addr_dec(entry.mac);
1393
1394 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1395 if (err)
1396 return err;
1397
dabc1a96 1398 /* Initialize a fresh ATU entry if it isn't found */
27c0e600 1399 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
dabc1a96
VD		 1400 !ether_addr_equal(entry.mac, addr)) {
1401 memset(&entry, 0, sizeof(entry));
1402 ether_addr_copy(entry.mac, addr);
1403 }
1404
88472939 1405 /* Purge the ATU entry only if no port is using it anymore */
27c0e600 1406 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1407 entry.portvec &= ~BIT(port);
1408 if (!entry.portvec)
27c0e600 1409 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
88472939 1410 } else {
01bd96c8 1411 entry.portvec |= BIT(port);
88472939 1412 entry.state = state;
fd231c82
VD		 1413 }
1414
9c13c026 1415 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1416}
1417
f81ec90f
VD		 1418static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1419 const struct switchdev_obj_port_fdb *fdb,
1420 struct switchdev_trans *trans)
146a3206
VD		 1421{
1422 /* We don't need any dynamic resource from the kernel (yet),
1423 * so skip the prepare phase.
1424 */
1425 return 0;
1426}
1427
f81ec90f
VD		 1428static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1429 const struct switchdev_obj_port_fdb *fdb,
1430 struct switchdev_trans *trans)
87820510 1431{
04bed143 1432 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1433
fad09c73 1434 mutex_lock(&chip->reg_lock);
83dabd1f 1435 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
27c0e600 1436 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC))
774439e5
VD		 1437 dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
1438 port);
fad09c73 1439 mutex_unlock(&chip->reg_lock);
87820510
VD		 1440}
1441
f81ec90f
VD		 1442static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1443 const struct switchdev_obj_port_fdb *fdb)
87820510 1444{
04bed143 1445 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1446 int err;
87820510 1447
fad09c73 1448 mutex_lock(&chip->reg_lock);
83dabd1f 1449 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
27c0e600 1450 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
fad09c73 1451 mutex_unlock(&chip->reg_lock);
87820510 1452
83dabd1f 1453 return err;
87820510
VD		 1454}
1455
83dabd1f
VD		 1456static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1457 u16 fid, u16 vid, int port,
1458 struct switchdev_obj *obj,
438ff537 1459 switchdev_obj_dump_cb_t *cb)
74b6ba0d 1460{
dabc1a96 1461 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 1462 int err;
1463
27c0e600 1464 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96 1465 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1466
1467 do {
dabc1a96 1468 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1469 if (err)
83dabd1f 1470 return err;
74b6ba0d 1471
27c0e600 1472 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
74b6ba0d
VD		 1473 break;
1474
01bd96c8 1475 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1476 continue;
1477
1478 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1479 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 1480
83dabd1f
VD		 1481 if (!is_unicast_ether_addr(addr.mac))
1482 continue;
1483
1484 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 1485 fdb->vid = vid;
1486 ether_addr_copy(fdb->addr, addr.mac);
27c0e600 1487 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
83dabd1f
VD		 1488 fdb->ndm_state = NUD_NOARP;
1489 else
1490 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 1491 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1492 struct switchdev_obj_port_mdb *mdb;
1493
1494 if (!is_multicast_ether_addr(addr.mac))
1495 continue;
1496
1497 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1498 mdb->vid = vid;
1499 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 1500 } else {
1501 return -EOPNOTSUPP;
74b6ba0d 1502 }
83dabd1f
VD		 1503
1504 err = cb(obj);
1505 if (err)
1506 return err;
74b6ba0d
VD		 1507 } while (!is_broadcast_ether_addr(addr.mac));
1508
1509 return err;
1510}
1511
83dabd1f
VD		 1512static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1513 struct switchdev_obj *obj,
438ff537 1514 switchdev_obj_dump_cb_t *cb)
f33475bd 1515{
b4e47c0f 1516 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 1517 .vid = chip->info->max_vid,
f33475bd 1518 };
2db9ce1f 1519 u16 fid;
f33475bd
VD		 1520 int err;
1521
2db9ce1f 1522 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 1523 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 1524 if (err)
83dabd1f 1525 return err;
2db9ce1f 1526
83dabd1f 1527 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 1528 if (err)
83dabd1f 1529 return err;
2db9ce1f 1530
74b6ba0d 1531 /* Dump VLANs' Filtering Information Databases */
f33475bd 1532 do {
f1394b78 1533 err = mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 1534 if (err)
83dabd1f 1535 return err;
f33475bd
VD		 1536
1537 if (!vlan.valid)
1538 break;
1539
83dabd1f
VD		 1540 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1541 obj, cb);
f33475bd 1542 if (err)
83dabd1f 1543 return err;
3cf3c846 1544 } while (vlan.vid < chip->info->max_vid);
f33475bd 1545
83dabd1f
VD		 1546 return err;
1547}
1548
1549static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1550 struct switchdev_obj_port_fdb *fdb,
438ff537 1551 switchdev_obj_dump_cb_t *cb)
83dabd1f 1552{
04bed143 1553 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 1554 int err;
1555
1556 mutex_lock(&chip->reg_lock);
1557 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 1558 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 1559
1560 return err;
1561}
1562
240ea3ef
VD		 1563static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1564 struct net_device *br)
e79a8bcb 1565{
e96a6e02 1566 struct dsa_switch *ds;
240ea3ef 1567 int port;
e96a6e02 1568 int dev;
240ea3ef 1569 int err;
466dfa07 1570
240ea3ef
VD		 1571 /* Remap the Port VLAN of each local bridge group member */
1572 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1573 if (chip->ds->ports[port].bridge_dev == br) {
1574 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 1575 if (err)
240ea3ef 1576 return err;
b7666efe
VD		 1577 }
1578 }
1579
e96a6e02
VD		 1580 if (!mv88e6xxx_has_pvt(chip))
1581 return 0;
1582
1583 /* Remap the Port VLAN of each cross-chip bridge group member */
1584 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1585 ds = chip->ds->dst->ds[dev];
1586 if (!ds)
1587 break;
1588
1589 for (port = 0; port < ds->num_ports; ++port) {
1590 if (ds->ports[port].bridge_dev == br) {
1591 err = mv88e6xxx_pvt_map(chip, dev, port);
1592 if (err)
1593 return err;
1594 }
1595 }
1596 }
1597
240ea3ef
VD		 1598 return 0;
1599}
1600
1601static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1602 struct net_device *br)
1603{
1604 struct mv88e6xxx_chip *chip = ds->priv;
1605 int err;
1606
1607 mutex_lock(&chip->reg_lock);
1608 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 1609 mutex_unlock(&chip->reg_lock);
a6692754 1610
466dfa07 1611 return err;
e79a8bcb
VD		 1612}
1613
f123f2fb
VD		 1614static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1615 struct net_device *br)
66d9cd0f 1616{
04bed143 1617 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 1618
fad09c73 1619 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 1620 if (mv88e6xxx_bridge_map(chip, br) ||
1621 mv88e6xxx_port_vlan_map(chip, port))
1622 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 1623 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 1624}
1625
aec5ac88
VD		 1626static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1627 int port, struct net_device *br)
1628{
1629 struct mv88e6xxx_chip *chip = ds->priv;
1630 int err;
1631
1632 if (!mv88e6xxx_has_pvt(chip))
1633 return 0;
1634
1635 mutex_lock(&chip->reg_lock);
1636 err = mv88e6xxx_pvt_map(chip, dev, port);
1637 mutex_unlock(&chip->reg_lock);
1638
1639 return err;
1640}
1641
1642static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1643 int port, struct net_device *br)
1644{
1645 struct mv88e6xxx_chip *chip = ds->priv;
1646
1647 if (!mv88e6xxx_has_pvt(chip))
1648 return;
1649
1650 mutex_lock(&chip->reg_lock);
1651 if (mv88e6xxx_pvt_map(chip, dev, port))
1652 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1653 mutex_unlock(&chip->reg_lock);
1654}
1655
17e708ba
VD		 1656static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1657{
1658 if (chip->info->ops->reset)
1659 return chip->info->ops->reset(chip);
1660
1661 return 0;
1662}
1663
309eca6d
VD		 1664static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1665{
1666 struct gpio_desc *gpiod = chip->reset;
1667
1668 /* If there is a GPIO connected to the reset pin, toggle it */
1669 if (gpiod) {
1670 gpiod_set_value_cansleep(gpiod, 1);
1671 usleep_range(10000, 20000);
1672 gpiod_set_value_cansleep(gpiod, 0);
1673 usleep_range(10000, 20000);
1674 }
1675}
1676
4ac4b5a6 1677static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 1678{
4ac4b5a6 1679 int i, err;
552238b5 1680
4ac4b5a6 1681 /* Set all ports to the Disabled state */
370b4ffb 1682 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 1683 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 1684 if (err)
1685 return err;
552238b5
VD		 1686 }
1687
4ac4b5a6
VD		 1688 /* Wait for transmit queues to drain,
1689 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1690 */
552238b5
VD		 1691 usleep_range(2000, 4000);
1692
4ac4b5a6
VD		 1693 return 0;
1694}
1695
1696static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1697{
4ac4b5a6
VD		 1698 int err;
1699
1700 err = mv88e6xxx_disable_ports(chip);
1701 if (err)
1702 return err;
1703
309eca6d 1704 mv88e6xxx_hardware_reset(chip);
552238b5 1705
17e708ba 1706 return mv88e6xxx_software_reset(chip);
552238b5
VD		 1707}
1708
4314557c 1709static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 1710 enum mv88e6xxx_frame_mode frame,
1711 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 1712{
1713 int err;
1714
4314557c
VD		 1715 if (!chip->info->ops->port_set_frame_mode)
1716 return -EOPNOTSUPP;
1717
1718 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 1719 if (err)
1720 return err;
1721
4314557c
VD		 1722 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1723 if (err)
1724 return err;
1725
1726 if (chip->info->ops->port_set_ether_type)
1727 return chip->info->ops->port_set_ether_type(chip, port, etype);
1728
1729 return 0;
56995cbc
AL		 1730}
1731
4314557c 1732static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 1733{
4314557c 1734 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 1735 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1736 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1737}
56995cbc 1738
4314557c
VD		 1739static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1740{
1741 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 1742 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1743 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1744}
56995cbc 1745
4314557c
VD		 1746static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1747{
1748 return mv88e6xxx_set_port_mode(chip, port,
1749 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 1750 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1751 ETH_P_EDSA);
4314557c 1752}
56995cbc 1753
4314557c
VD		 1754static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1755{
1756 if (dsa_is_dsa_port(chip->ds, port))
1757 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1758
4314557c
VD		 1759 if (dsa_is_normal_port(chip->ds, port))
1760 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 1761
4314557c
VD		 1762 /* Setup CPU port mode depending on its supported tag format */
1763 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1764 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1765
4314557c
VD		 1766 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1767 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 1768
4314557c 1769 return -EINVAL;
56995cbc
AL		 1770}
1771
601aeed3 1772static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 1773{
601aeed3 1774 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 1775
601aeed3 1776 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 1777}
56995cbc 1778
601aeed3 1779static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 1780{
601aeed3 1781 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 1782
601aeed3
VD		 1783 /* Upstream ports flood frames with unknown unicast or multicast DA */
1784 if (chip->info->ops->port_set_egress_floods)
1785 return chip->info->ops->port_set_egress_floods(chip, port,
1786 flood, flood);
ea698f4f 1787
601aeed3 1788 return 0;
ea698f4f
VD		 1789}
1790
6d91782f
AL		 1791static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1792 bool on)
1793{
523a8904
VD		 1794 if (chip->info->ops->serdes_power)
1795 return chip->info->ops->serdes_power(chip, port, on);
04aca993 1796
523a8904 1797 return 0;
6d91782f
AL		 1798}
1799
fad09c73 1800static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 1801{
fad09c73 1802 struct dsa_switch *ds = chip->ds;
0e7b9925 1803 int err;
54d792f2 1804 u16 reg;
d827e88a 1805
d78343d2
VD		 1806 /* MAC Forcing register: don't force link, speed, duplex or flow control
1807 * state to any particular values on physical ports, but force the CPU
1808 * port and all DSA ports to their maximum bandwidth and full duplex.
1809 */
1810 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1811 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1812 SPEED_MAX, DUPLEX_FULL,
1813 PHY_INTERFACE_MODE_NA);
1814 else
1815 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1816 SPEED_UNFORCED, DUPLEX_UNFORCED,
1817 PHY_INTERFACE_MODE_NA);
1818 if (err)
1819 return err;
54d792f2
AL		 1820
1821 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1822 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1823 * tunneling, determine priority by looking at 802.1p and IP
1824 * priority fields (IP prio has precedence), and set STP state
1825 * to Forwarding.
1826 *
1827 * If this is the CPU link, use DSA or EDSA tagging depending
1828 * on which tagging mode was configured.
1829 *
1830 * If this is a link to another switch, use DSA tagging mode.
1831 *
1832 * If this is the upstream port for this switch, enable
1833 * forwarding of unknown unicasts and multicasts.
1834 */
a89b433b
VD		 1835 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1836 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1837 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1838 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 1839 if (err)
1840 return err;
6083ce71 1841
601aeed3 1842 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 1843 if (err)
1844 return err;
54d792f2 1845
601aeed3 1846 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 1847 if (err)
1848 return err;
1849
04aca993
AL		 1850 /* Enable the SERDES interface for DSA and CPU ports. Normal
1851 * ports SERDES are enabled when the port is enabled, thus
1852 * saving a bit of power.
13a7ebb3 1853 */
04aca993
AL		 1854 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1855 err = mv88e6xxx_serdes_power(chip, port, true);
1856 if (err)
1857 return err;
1858 }
13a7ebb3 1859
8efdda4a 1860 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 1861 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 1862 * untagged frames on this port, do a destination address lookup on all
1863 * received packets as usual, disable ARP mirroring and don't send a
1864 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 1865 */
a23b2961
AL		 1866 err = mv88e6xxx_port_set_map_da(chip, port);
1867 if (err)
1868 return err;
8efdda4a 1869
a23b2961
AL		 1870 reg = 0;
1871 if (chip->info->ops->port_set_upstream_port) {
1872 err = chip->info->ops->port_set_upstream_port(
1873 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 1874 if (err)
1875 return err;
54d792f2
AL		 1876 }
1877
a23b2961 1878 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 1879 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 1880 if (err)
1881 return err;
1882
cd782656
VD		 1883 if (chip->info->ops->port_set_jumbo_size) {
1884 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 1885 if (err)
1886 return err;
1887 }
1888
54d792f2
AL		 1889 /* Port Association Vector: when learning source addresses
1890 * of packets, add the address to the address database using
1891 * a port bitmap that has only the bit for this port set and
1892 * the other bits clear.
1893 */
4c7ea3c0 1894 reg = 1 << port;
996ecb82
VD		 1895 /* Disable learning for CPU port */
1896 if (dsa_is_cpu_port(ds, port))
65fa4027 1897 reg = 0;
4c7ea3c0 1898
2a4614e4
VD		 1899 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1900 reg);
0e7b9925
AL		 1901 if (err)
1902 return err;
54d792f2
AL		 1903
1904 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 1905 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1906 0x0000);
0e7b9925
AL		 1907 if (err)
1908 return err;
54d792f2 1909
0898432c
VD		 1910 if (chip->info->ops->port_pause_limit) {
1911 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 1912 if (err)
1913 return err;
b35d322a 1914 }
54d792f2 1915
c8c94891
VD		 1916 if (chip->info->ops->port_disable_learn_limit) {
1917 err = chip->info->ops->port_disable_learn_limit(chip, port);
1918 if (err)
1919 return err;
1920 }
1921
9dbfb4e1
VD		 1922 if (chip->info->ops->port_disable_pri_override) {
1923 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 1924 if (err)
1925 return err;
ef0a7318 1926 }
2bbb33be 1927
ef0a7318
AL		 1928 if (chip->info->ops->port_tag_remap) {
1929 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 1930 if (err)
1931 return err;
54d792f2
AL		 1932 }
1933
ef70b111
AL		 1934 if (chip->info->ops->port_egress_rate_limiting) {
1935 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 1936 if (err)
1937 return err;
54d792f2
AL		 1938 }
1939
ea698f4f 1940 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 1941 if (err)
1942 return err;
d827e88a 1943
207afda1 1944 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 1945 * database, and allow bidirectional communication between the
1946 * CPU and DSA port(s), and the other ports.
d827e88a 1947 */
b4e48c50 1948 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 1949 if (err)
1950 return err;
2db9ce1f 1951
240ea3ef 1952 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 1953 if (err)
1954 return err;
d827e88a
GR		 1955
1956 /* Default VLAN ID and priority: don't set a default VLAN
1957 * ID, and set the default packet priority to zero.
1958 */
b7929fb3 1959 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 1960}
1961
04aca993
AL		 1962static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1963 struct phy_device *phydev)
1964{
1965 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 1966 int err;
04aca993
AL		 1967
1968 mutex_lock(&chip->reg_lock);
523a8904 1969 err = mv88e6xxx_serdes_power(chip, port, true);
04aca993
AL		 1970 mutex_unlock(&chip->reg_lock);
1971
1972 return err;
1973}
1974
1975static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1976 struct phy_device *phydev)
1977{
1978 struct mv88e6xxx_chip *chip = ds->priv;
1979
1980 mutex_lock(&chip->reg_lock);
523a8904
VD		 1981 if (mv88e6xxx_serdes_power(chip, port, false))
1982 dev_err(chip->dev, "failed to power off SERDES\n");
04aca993
AL		 1983 mutex_unlock(&chip->reg_lock);
1984}
1985
2cfcd964
VD		 1986static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
1987 unsigned int ageing_time)
1988{
04bed143 1989 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 1990 int err;
1991
1992 mutex_lock(&chip->reg_lock);
720c6343 1993 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 1994 mutex_unlock(&chip->reg_lock);
1995
1996 return err;
1997}
1998
9729934c 1999static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2000{
fad09c73 2001 struct dsa_switch *ds = chip->ds;
b0745e87 2002 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2003 int err;
54d792f2 2004
fa8d1179
VD		 2005 if (chip->info->ops->set_cpu_port) {
2006 err = chip->info->ops->set_cpu_port(chip, upstream_port);
33641994
AL		 2007 if (err)
2008 return err;
2009 }
2010
fa8d1179
VD		 2011 if (chip->info->ops->set_egress_port) {
2012 err = chip->info->ops->set_egress_port(chip, upstream_port);
33641994
AL		 2013 if (err)
2014 return err;
2015 }
b0745e87 2016
50484ff4 2017 /* Disable remote management, and set the switch's DSA device number. */
d77f4321
VD		 2018 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2019 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
a935c052 2020 (ds->index & 0x1f));
50484ff4
VD		 2021 if (err)
2022 return err;
2023
54d792f2 2024 /* Configure the IP ToS mapping registers. */
ccba8f3a 2025 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
48ace4ef 2026 if (err)
08a01261 2027 return err;
ccba8f3a 2028 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
48ace4ef 2029 if (err)
08a01261 2030 return err;
ccba8f3a 2031 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
48ace4ef 2032 if (err)
08a01261 2033 return err;
ccba8f3a 2034 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
48ace4ef 2035 if (err)
08a01261 2036 return err;
ccba8f3a 2037 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
48ace4ef 2038 if (err)
08a01261 2039 return err;
ccba8f3a 2040 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
48ace4ef 2041 if (err)
08a01261 2042 return err;
ccba8f3a 2043 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
48ace4ef 2044 if (err)
08a01261 2045 return err;
ccba8f3a 2046 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
48ace4ef 2047 if (err)
08a01261 2048 return err;
54d792f2
AL		 2049
2050 /* Configure the IEEE 802.1p priority mapping register. */
ccba8f3a 2051 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
48ace4ef 2052 if (err)
08a01261 2053 return err;
54d792f2 2054
de227387
AL		 2055 /* Initialize the statistics unit */
2056 err = mv88e6xxx_stats_set_histogram(chip);
2057 if (err)
2058 return err;
2059
9729934c 2060 /* Clear the statistics counters for all ports */
57d1ef38
VD		 2061 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
2062 MV88E6XXX_G1_STATS_OP_BUSY |
2063 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
9729934c
VD		 2064 if (err)
2065 return err;
2066
2067 /* Wait for the flush to complete. */
7f9ef3af 2068 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2069 if (err)
2070 return err;
2071
2072 return 0;
2073}
2074
f81ec90f 2075static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2076{
04bed143 2077 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2078 int err;
a1a6a4d1
VD		 2079 int i;
2080
fad09c73 2081 chip->ds = ds;
a3c53be5 2082 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2083
fad09c73 2084 mutex_lock(&chip->reg_lock);
08a01261 2085
9729934c 2086 /* Setup Switch Port Registers */
370b4ffb 2087 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2088 err = mv88e6xxx_setup_port(chip, i);
2089 if (err)
2090 goto unlock;
2091 }
2092
2093 /* Setup Switch Global 1 Registers */
2094 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2095 if (err)
2096 goto unlock;
2097
9729934c
VD		 2098 /* Setup Switch Global 2 Registers */
2099 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2100 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2101 if (err)
2102 goto unlock;
2103 }
08a01261 2104
1b17aedf
VD		 2105 err = mv88e6xxx_phy_setup(chip);
2106 if (err)
2107 goto unlock;
2108
b486d7c9
VD		 2109 err = mv88e6xxx_vtu_setup(chip);
2110 if (err)
2111 goto unlock;
2112
81228996
VD		 2113 err = mv88e6xxx_pvt_setup(chip);
2114 if (err)
2115 goto unlock;
2116
a2ac29d2
VD		 2117 err = mv88e6xxx_atu_setup(chip);
2118 if (err)
2119 goto unlock;
2120
6e55f698
AL		 2121 /* Some generations have the configuration of sending reserved
2122 * management frames to the CPU in global2, others in
2123 * global1. Hence it does not fit the two setup functions
2124 * above.
2125 */
2126 if (chip->info->ops->mgmt_rsvd2cpu) {
2127 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2128 if (err)
2129 goto unlock;
2130 }
2131
6b17e864 2132unlock:
fad09c73 2133 mutex_unlock(&chip->reg_lock);
db687a56 2134
48ace4ef 2135 return err;
54d792f2
AL		 2136}
2137
3b4caa1b
VD		 2138static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2139{
04bed143 2140 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2141 int err;
2142
b073d4e2
VD		 2143 if (!chip->info->ops->set_switch_mac)
2144 return -EOPNOTSUPP;
3b4caa1b 2145
b073d4e2
VD		 2146 mutex_lock(&chip->reg_lock);
2147 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2148 mutex_unlock(&chip->reg_lock);
2149
2150 return err;
2151}
2152
e57e5e77 2153static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2154{
0dd12d54
AL		 2155 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2156 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2157 u16 val;
2158 int err;
fd3a0ee4 2159
ee26a228
AL		 2160 if (!chip->info->ops->phy_read)
2161 return -EOPNOTSUPP;
2162
fad09c73 2163 mutex_lock(&chip->reg_lock);
ee26a228 2164 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2165 mutex_unlock(&chip->reg_lock);
e57e5e77 2166
da9f3301
AL		 2167 if (reg == MII_PHYSID2) {
2168 /* Some internal PHYS don't have a model number. Use
2169 * the mv88e6390 family model number instead.
2170 */
2171 if (!(val & 0x3f0))
107fcc10 2172 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
da9f3301
AL		 2173 }
2174
e57e5e77 2175 return err ? err : val;
fd3a0ee4
AL		 2176}
2177
e57e5e77 2178static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2179{
0dd12d54
AL		 2180 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2181 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2182 int err;
fd3a0ee4 2183
ee26a228
AL		 2184 if (!chip->info->ops->phy_write)
2185 return -EOPNOTSUPP;
2186
fad09c73 2187 mutex_lock(&chip->reg_lock);
ee26a228 2188 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2189 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2190
2191 return err;
fd3a0ee4
AL		 2192}
2193
fad09c73 2194static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2195 struct device_node *np,
2196 bool external)
b516d453
AL		 2197{
2198 static int index;
0dd12d54 2199 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2200 struct mii_bus *bus;
2201 int err;
2202
0dd12d54 2203 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2204 if (!bus)
2205 return -ENOMEM;
2206
0dd12d54 2207 mdio_bus = bus->priv;
a3c53be5 2208 mdio_bus->bus = bus;
0dd12d54 2209 mdio_bus->chip = chip;
a3c53be5
AL		 2210 INIT_LIST_HEAD(&mdio_bus->list);
2211 mdio_bus->external = external;
0dd12d54 2212
b516d453
AL		 2213 if (np) {
2214 bus->name = np->full_name;
2215 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2216 } else {
2217 bus->name = "mv88e6xxx SMI";
2218 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2219 }
2220
2221 bus->read = mv88e6xxx_mdio_read;
2222 bus->write = mv88e6xxx_mdio_write;
fad09c73 2223 bus->parent = chip->dev;
b516d453 2224
a3c53be5
AL		 2225 if (np)
2226 err = of_mdiobus_register(bus, np);
b516d453
AL		 2227 else
2228 err = mdiobus_register(bus);
2229 if (err) {
fad09c73 2230 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2231 return err;
b516d453 2232 }
a3c53be5
AL		 2233
2234 if (external)
2235 list_add_tail(&mdio_bus->list, &chip->mdios);
2236 else
2237 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2238
2239 return 0;
a3c53be5 2240}
b516d453 2241
a3c53be5
AL		 2242static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2243 { .compatible = "marvell,mv88e6xxx-mdio-external",
2244 .data = (void *)true },
2245 { },
2246};
b516d453 2247
a3c53be5
AL		 2248static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2249 struct device_node *np)
2250{
2251 const struct of_device_id *match;
2252 struct device_node *child;
2253 int err;
2254
2255 /* Always register one mdio bus for the internal/default mdio
2256 * bus. This maybe represented in the device tree, but is
2257 * optional.
2258 */
2259 child = of_get_child_by_name(np, "mdio");
2260 err = mv88e6xxx_mdio_register(chip, child, false);
2261 if (err)
2262 return err;
2263
2264 /* Walk the device tree, and see if there are any other nodes
2265 * which say they are compatible with the external mdio
2266 * bus.
2267 */
2268 for_each_available_child_of_node(np, child) {
2269 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2270 if (match) {
2271 err = mv88e6xxx_mdio_register(chip, child, true);
2272 if (err)
2273 return err;
2274 }
2275 }
2276
2277 return 0;
b516d453
AL		 2278}
2279
a3c53be5 2280static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2281
2282{
a3c53be5
AL		 2283 struct mv88e6xxx_mdio_bus *mdio_bus;
2284 struct mii_bus *bus;
b516d453 2285
a3c53be5
AL		 2286 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2287 bus = mdio_bus->bus;
b516d453 2288
a3c53be5
AL		 2289 mdiobus_unregister(bus);
2290 }
b516d453
AL		 2291}
2292
855b1932
VD		 2293static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2294{
04bed143 2295 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2296
2297 return chip->eeprom_len;
2298}
2299
855b1932
VD		 2300static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2301 struct ethtool_eeprom *eeprom, u8 *data)
2302{
04bed143 2303 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2304 int err;
2305
ee4dc2e7
VD		 2306 if (!chip->info->ops->get_eeprom)
2307 return -EOPNOTSUPP;
855b1932 2308
ee4dc2e7
VD		 2309 mutex_lock(&chip->reg_lock);
2310 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2311 mutex_unlock(&chip->reg_lock);
2312
2313 if (err)
2314 return err;
2315
2316 eeprom->magic = 0xc3ec4951;
2317
2318 return 0;
2319}
2320
855b1932
VD		 2321static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2322 struct ethtool_eeprom *eeprom, u8 *data)
2323{
04bed143 2324 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2325 int err;
2326
ee4dc2e7
VD		 2327 if (!chip->info->ops->set_eeprom)
2328 return -EOPNOTSUPP;
2329
855b1932
VD		 2330 if (eeprom->magic != 0xc3ec4951)
2331 return -EINVAL;
2332
2333 mutex_lock(&chip->reg_lock);
ee4dc2e7 2334 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2335 mutex_unlock(&chip->reg_lock);
2336
2337 return err;
2338}
2339
b3469dd8 2340static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2341 /* MV88E6XXX_FAMILY_6097 */
b073d4e2 2342 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2343 .phy_read = mv88e6185_phy_ppu_read,
2344 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2345 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2346 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2347 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2348 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2349 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2350 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2351 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2352 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2353 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2354 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2355 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2356 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2357 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2358 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2359 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2360 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2361 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2362 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2363 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2364 .ppu_enable = mv88e6185_g1_ppu_enable,
2365 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2366 .reset = mv88e6185_g1_reset,
f1394b78 2367 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2368 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2369};
2370
2371static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2372 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2373 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2374 .phy_read = mv88e6185_phy_ppu_read,
2375 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2376 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2377 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2378 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2379 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2380 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2381 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2382 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2383 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2384 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2385 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 2386 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2387 .ppu_enable = mv88e6185_g1_ppu_enable,
2388 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2389 .reset = mv88e6185_g1_reset,
f1394b78 2390 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2391 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2392};
2393
7d381a02 2394static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2395 /* MV88E6XXX_FAMILY_6097 */
7d381a02
SE		 2396 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2397 .phy_read = mv88e6xxx_g2_smi_phy_read,
2398 .phy_write = mv88e6xxx_g2_smi_phy_write,
2399 .port_set_link = mv88e6xxx_port_set_link,
2400 .port_set_duplex = mv88e6xxx_port_set_duplex,
2401 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2402 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2403 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2404 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2405 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2406 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2407 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 2408 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2409 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2410 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2411 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2412 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2413 .stats_get_strings = mv88e6095_stats_get_strings,
2414 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2415 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2416 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2417 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2418 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2419 .reset = mv88e6352_g1_reset,
f1394b78 2420 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2421 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
7d381a02
SE		 2422};
2423
b3469dd8 2424static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2425 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2426 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2427 .phy_read = mv88e6xxx_g2_smi_phy_read,
2428 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2429 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2430 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2431 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2432 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2433 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2434 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2435 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2436 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2437 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2438 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2439 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2440 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2441 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2442 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2443 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2444 .reset = mv88e6352_g1_reset,
f1394b78 2445 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2446 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2447};
2448
2449static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2450 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2451 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2452 .phy_read = mv88e6185_phy_ppu_read,
2453 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2454 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2455 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2456 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2457 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2458 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2459 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2460 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2461 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 2462 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2463 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2464 .port_pause_limit = mv88e6097_port_pause_limit,
a605a0fe 2465 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2466 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2467 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2468 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2469 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2470 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2471 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2472 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2473 .ppu_enable = mv88e6185_g1_ppu_enable,
2474 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2475 .reset = mv88e6185_g1_reset,
f1394b78 2476 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2477 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2478};
2479
990e27b0
VD		 2480static const struct mv88e6xxx_ops mv88e6141_ops = {
2481 /* MV88E6XXX_FAMILY_6341 */
2482 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2483 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2484 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2485 .phy_read = mv88e6xxx_g2_smi_phy_read,
2486 .phy_write = mv88e6xxx_g2_smi_phy_write,
2487 .port_set_link = mv88e6xxx_port_set_link,
2488 .port_set_duplex = mv88e6xxx_port_set_duplex,
2489 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2490 .port_set_speed = mv88e6390_port_set_speed,
2491 .port_tag_remap = mv88e6095_port_tag_remap,
2492 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2493 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2494 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2495 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 2496 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2497 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 2498 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2499 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2500 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2501 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2502 .stats_get_strings = mv88e6320_stats_get_strings,
2503 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2504 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2505 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 2506 .watchdog_ops = &mv88e6390_watchdog_ops,
2507 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2508 .reset = mv88e6352_g1_reset,
f1394b78 2509 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2510 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
990e27b0
VD		 2511};
2512
b3469dd8 2513static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2514 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2516 .phy_read = mv88e6xxx_g2_smi_phy_read,
2517 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2518 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2519 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2520 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2521 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2522 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2523 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2524 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2525 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2526 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2527 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2528 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2529 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2530 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2531 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2532 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2533 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2534 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2535 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2536 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2537 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2538 .reset = mv88e6352_g1_reset,
f1394b78 2539 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2540 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2541};
2542
2543static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2544 /* MV88E6XXX_FAMILY_6165 */
b073d4e2 2545 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2546 .phy_read = mv88e6165_phy_read,
2547 .phy_write = mv88e6165_phy_write,
08ef7f10 2548 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2549 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2550 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 2551 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2552 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2553 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2554 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2555 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2556 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2557 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2558 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2559 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2560 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2561 .reset = mv88e6352_g1_reset,
f1394b78 2562 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2563 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2564};
2565
2566static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2567 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 2568 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2569 .phy_read = mv88e6xxx_g2_smi_phy_read,
2570 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2571 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2572 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2573 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2574 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2575 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2576 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2577 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2578 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2579 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2580 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2581 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2582 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2583 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2584 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2585 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2586 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2587 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2588 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2589 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2590 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2591 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2592 .reset = mv88e6352_g1_reset,
f1394b78 2593 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2594 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2595};
2596
2597static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 2598 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 2599 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2600 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2601 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2602 .phy_read = mv88e6xxx_g2_smi_phy_read,
2603 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2604 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2605 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2606 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2607 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2608 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2609 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2610 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2611 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2612 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2613 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2614 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2615 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2616 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2617 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2618 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2619 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2620 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2621 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2622 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2623 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2624 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2625 .reset = mv88e6352_g1_reset,
f1394b78 2626 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2627 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2628 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2629};
2630
2631static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 2632 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 2633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2634 .phy_read = mv88e6xxx_g2_smi_phy_read,
2635 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2636 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2637 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2638 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2639 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2640 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2641 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2642 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2643 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2644 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2645 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2646 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2647 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2648 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2649 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2650 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2651 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2652 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2653 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2654 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2655 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2656 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2657 .reset = mv88e6352_g1_reset,
f1394b78 2658 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2660};
2661
2662static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 2663 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 2664 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2665 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2666 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2667 .phy_read = mv88e6xxx_g2_smi_phy_read,
2668 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2669 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2670 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2671 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2672 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2673 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2674 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2675 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2676 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2677 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2678 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2679 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2680 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2681 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2682 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2683 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2684 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2685 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2686 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2687 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2688 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2689 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2690 .reset = mv88e6352_g1_reset,
f1394b78 2691 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2693 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2694};
2695
2696static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 2697 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2698 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2699 .phy_read = mv88e6185_phy_ppu_read,
2700 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2701 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2702 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2703 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2704 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2705 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 2706 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 2707 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2708 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2709 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2710 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2711 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2712 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2713 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2714 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2715 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2716 .ppu_enable = mv88e6185_g1_ppu_enable,
2717 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2718 .reset = mv88e6185_g1_reset,
f1394b78 2719 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2720 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2721};
2722
1a3b39ec 2723static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 2724 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2725 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2726 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2727 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2728 .phy_read = mv88e6xxx_g2_smi_phy_read,
2729 .phy_write = mv88e6xxx_g2_smi_phy_write,
2730 .port_set_link = mv88e6xxx_port_set_link,
2731 .port_set_duplex = mv88e6xxx_port_set_duplex,
2732 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2733 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2734 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2735 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2736 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2737 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2738 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2739 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2740 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2741 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2742 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2743 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2744 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2745 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2746 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2747 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2748 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2749 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2750 .reset = mv88e6352_g1_reset,
931d1822
VD		 2751 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2752 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2753 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2754};
2755
2756static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 2757 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2758 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2759 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2760 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2761 .phy_read = mv88e6xxx_g2_smi_phy_read,
2762 .phy_write = mv88e6xxx_g2_smi_phy_write,
2763 .port_set_link = mv88e6xxx_port_set_link,
2764 .port_set_duplex = mv88e6xxx_port_set_duplex,
2765 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2766 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 2767 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2768 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2769 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2770 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2771 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2772 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2773 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2774 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2775 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2776 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2777 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2778 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2779 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2780 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2781 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2782 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2783 .reset = mv88e6352_g1_reset,
931d1822
VD		 2784 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2785 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2786 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2787};
2788
2789static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 2790 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2791 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2792 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2793 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2794 .phy_read = mv88e6xxx_g2_smi_phy_read,
2795 .phy_write = mv88e6xxx_g2_smi_phy_write,
2796 .port_set_link = mv88e6xxx_port_set_link,
2797 .port_set_duplex = mv88e6xxx_port_set_duplex,
2798 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2799 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2800 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2801 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2802 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2803 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2804 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2805 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2806 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2807 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2808 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2809 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2810 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2811 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2812 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2813 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2814 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2815 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2816 .reset = mv88e6352_g1_reset,
931d1822
VD		 2817 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2818 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2819 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2820};
2821
b3469dd8 2822static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 2823 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 2824 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2825 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2826 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2827 .phy_read = mv88e6xxx_g2_smi_phy_read,
2828 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2829 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2830 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2831 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2832 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2833 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2834 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2835 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2836 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2837 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2838 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2839 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2840 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2841 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2842 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2843 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2844 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2845 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2846 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2847 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2848 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2849 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2850 .reset = mv88e6352_g1_reset,
f1394b78 2851 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2852 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2853 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2854};
2855
1a3b39ec 2856static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 2857 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 2858 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2859 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2860 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2861 .phy_read = mv88e6xxx_g2_smi_phy_read,
2862 .phy_write = mv88e6xxx_g2_smi_phy_write,
2863 .port_set_link = mv88e6xxx_port_set_link,
2864 .port_set_duplex = mv88e6xxx_port_set_duplex,
2865 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2866 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2867 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2868 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2869 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2870 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2871 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 2872 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 2873 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2874 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2875 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2876 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2877 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2878 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2879 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2880 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2881 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2882 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2883 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2884 .reset = mv88e6352_g1_reset,
931d1822
VD		 2885 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2886 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2887 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2888};
2889
b3469dd8 2890static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 2891 /* MV88E6XXX_FAMILY_6320 */
ee4dc2e7
VD		 2892 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2893 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2894 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2895 .phy_read = mv88e6xxx_g2_smi_phy_read,
2896 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2897 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2898 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2899 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2900 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2901 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2902 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2903 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2904 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2905 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2906 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2907 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2908 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2909 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2910 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2911 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2912 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2913 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2914 .set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 2915 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2916 .reset = mv88e6352_g1_reset,
f1394b78 2917 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2918 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2919};
2920
2921static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 2922 /* MV88E6XXX_FAMILY_6321 */
ee4dc2e7
VD		 2923 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2924 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2925 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2926 .phy_read = mv88e6xxx_g2_smi_phy_read,
2927 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2928 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2929 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2930 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2931 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2932 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2933 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2934 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2935 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2936 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2937 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2938 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2939 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2940 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2941 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2942 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2943 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2944 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2945 .set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 2946 .reset = mv88e6352_g1_reset,
f1394b78 2947 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2948 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2949};
2950
16e329ae
VD		 2951static const struct mv88e6xxx_ops mv88e6341_ops = {
2952 /* MV88E6XXX_FAMILY_6341 */
2953 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2954 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2955 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2956 .phy_read = mv88e6xxx_g2_smi_phy_read,
2957 .phy_write = mv88e6xxx_g2_smi_phy_write,
2958 .port_set_link = mv88e6xxx_port_set_link,
2959 .port_set_duplex = mv88e6xxx_port_set_duplex,
2960 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2961 .port_set_speed = mv88e6390_port_set_speed,
2962 .port_tag_remap = mv88e6095_port_tag_remap,
2963 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2964 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2965 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2966 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 2967 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2968 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 2969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2971 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2972 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2973 .stats_get_strings = mv88e6320_stats_get_strings,
2974 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2975 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2976 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 2977 .watchdog_ops = &mv88e6390_watchdog_ops,
2978 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2979 .reset = mv88e6352_g1_reset,
f1394b78 2980 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2981 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
16e329ae
VD		 2982};
2983
b3469dd8 2984static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 2985 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 2986 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2987 .phy_read = mv88e6xxx_g2_smi_phy_read,
2988 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2989 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2990 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2991 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2992 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2993 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2994 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2995 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2996 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2997 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2998 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2999 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3000 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3001 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3002 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3003 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3004 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3005 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3006 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3007 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3008 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3009 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3010 .reset = mv88e6352_g1_reset,
f1394b78 3011 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3012 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3013};
3014
3015static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3016 /* MV88E6XXX_FAMILY_6351 */
b073d4e2 3017 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3018 .phy_read = mv88e6xxx_g2_smi_phy_read,
3019 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3020 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3021 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3022 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3023 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3024 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3025 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3026 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3027 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3028 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3029 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3030 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3031 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3032 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3033 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3034 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3035 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3036 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3037 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3038 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3039 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3040 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3041 .reset = mv88e6352_g1_reset,
f1394b78 3042 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3043 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3044};
3045
3046static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3047 /* MV88E6XXX_FAMILY_6352 */
ee4dc2e7
VD		 3048 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3049 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3050 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3051 .phy_read = mv88e6xxx_g2_smi_phy_read,
3052 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3053 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3054 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3055 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3056 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3057 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3058 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3059 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3060 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3061 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3062 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3063 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3064 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3065 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3066 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3067 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3068 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3069 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3070 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3071 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3072 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3073 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3074 .reset = mv88e6352_g1_reset,
f1394b78 3075 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3076 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 3077 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 3078};
3079
1a3b39ec 3080static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3081 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3082 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3083 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3084 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3085 .phy_read = mv88e6xxx_g2_smi_phy_read,
3086 .phy_write = mv88e6xxx_g2_smi_phy_write,
3087 .port_set_link = mv88e6xxx_port_set_link,
3088 .port_set_duplex = mv88e6xxx_port_set_duplex,
3089 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3090 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3091 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3092 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3093 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3094 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3095 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3096 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3097 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 3098 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3099 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3100 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3101 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3102 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3103 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3104 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3105 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3106 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3107 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3108 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3109 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3110 .reset = mv88e6352_g1_reset,
931d1822
VD		 3111 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3112 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3113 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3114};
3115
3116static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3117 /* MV88E6XXX_FAMILY_6390 */
98fc3c6f
VD		 3118 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3119 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3120 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3121 .phy_read = mv88e6xxx_g2_smi_phy_read,
3122 .phy_write = mv88e6xxx_g2_smi_phy_write,
3123 .port_set_link = mv88e6xxx_port_set_link,
3124 .port_set_duplex = mv88e6xxx_port_set_duplex,
3125 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3126 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3127 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3128 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3129 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3130 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3131 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3132 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3133 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 3134 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3135 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3136 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3137 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3138 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3139 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3140 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3141 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3142 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3143 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3144 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3145 .reset = mv88e6352_g1_reset,
931d1822
VD		 3146 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3147 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3148 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3149};
3150
f81ec90f
VD		 3151static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3152 [MV88E6085] = {
107fcc10 3153 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 3154 .family = MV88E6XXX_FAMILY_6097,
3155 .name = "Marvell 88E6085",
3156 .num_databases = 4096,
3157 .num_ports = 10,
3cf3c846 3158 .max_vid = 4095,
9dddd478 3159 .port_base_addr = 0x10,
a935c052 3160 .global1_addr = 0x1b,
acddbd21 3161 .age_time_coeff = 15000,
dc30c35b 3162 .g1_irqs = 8,
e606ca36 3163 .atu_move_port_mask = 0xf,
f3645652 3164 .pvt = true,
443d5a1b 3165 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3166 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3167 .ops = &mv88e6085_ops,
f81ec90f
VD		 3168 },
3169
3170 [MV88E6095] = {
107fcc10 3171 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 3172 .family = MV88E6XXX_FAMILY_6095,
3173 .name = "Marvell 88E6095/88E6095F",
3174 .num_databases = 256,
3175 .num_ports = 11,
3cf3c846 3176 .max_vid = 4095,
9dddd478 3177 .port_base_addr = 0x10,
a935c052 3178 .global1_addr = 0x1b,
acddbd21 3179 .age_time_coeff = 15000,
dc30c35b 3180 .g1_irqs = 8,
e606ca36 3181 .atu_move_port_mask = 0xf,
443d5a1b 3182 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3183 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3184 .ops = &mv88e6095_ops,
f81ec90f
VD		 3185 },
3186
7d381a02 3187 [MV88E6097] = {
107fcc10 3188 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 3189 .family = MV88E6XXX_FAMILY_6097,
3190 .name = "Marvell 88E6097/88E6097F",
3191 .num_databases = 4096,
3192 .num_ports = 11,
3cf3c846 3193 .max_vid = 4095,
7d381a02
SE		 3194 .port_base_addr = 0x10,
3195 .global1_addr = 0x1b,
3196 .age_time_coeff = 15000,
c534178b 3197 .g1_irqs = 8,
e606ca36 3198 .atu_move_port_mask = 0xf,
f3645652 3199 .pvt = true,
2bfcfcd3 3200 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3201 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3202 .ops = &mv88e6097_ops,
3203 },
3204
f81ec90f 3205 [MV88E6123] = {
107fcc10 3206 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 3207 .family = MV88E6XXX_FAMILY_6165,
3208 .name = "Marvell 88E6123",
3209 .num_databases = 4096,
3210 .num_ports = 3,
3cf3c846 3211 .max_vid = 4095,
9dddd478 3212 .port_base_addr = 0x10,
a935c052 3213 .global1_addr = 0x1b,
acddbd21 3214 .age_time_coeff = 15000,
dc30c35b 3215 .g1_irqs = 9,
e606ca36 3216 .atu_move_port_mask = 0xf,
f3645652 3217 .pvt = true,
5ebe31d7 3218 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3219 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3220 .ops = &mv88e6123_ops,
f81ec90f
VD		 3221 },
3222
3223 [MV88E6131] = {
107fcc10 3224 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 3225 .family = MV88E6XXX_FAMILY_6185,
3226 .name = "Marvell 88E6131",
3227 .num_databases = 256,
3228 .num_ports = 8,
3cf3c846 3229 .max_vid = 4095,
9dddd478 3230 .port_base_addr = 0x10,
a935c052 3231 .global1_addr = 0x1b,
acddbd21 3232 .age_time_coeff = 15000,
dc30c35b 3233 .g1_irqs = 9,
e606ca36 3234 .atu_move_port_mask = 0xf,
443d5a1b 3235 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3236 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3237 .ops = &mv88e6131_ops,
f81ec90f
VD		 3238 },
3239
990e27b0 3240 [MV88E6141] = {
107fcc10 3241 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0
VD		 3242 .family = MV88E6XXX_FAMILY_6341,
3243 .name = "Marvell 88E6341",
3244 .num_databases = 4096,
3245 .num_ports = 6,
3cf3c846 3246 .max_vid = 4095,
990e27b0
VD		 3247 .port_base_addr = 0x10,
3248 .global1_addr = 0x1b,
3249 .age_time_coeff = 3750,
3250 .atu_move_port_mask = 0x1f,
f3645652 3251 .pvt = true,
990e27b0
VD		 3252 .tag_protocol = DSA_TAG_PROTO_EDSA,
3253 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3254 .ops = &mv88e6141_ops,
3255 },
3256
f81ec90f 3257 [MV88E6161] = {
107fcc10 3258 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 3259 .family = MV88E6XXX_FAMILY_6165,
3260 .name = "Marvell 88E6161",
3261 .num_databases = 4096,
3262 .num_ports = 6,
3cf3c846 3263 .max_vid = 4095,
9dddd478 3264 .port_base_addr = 0x10,
a935c052 3265 .global1_addr = 0x1b,
acddbd21 3266 .age_time_coeff = 15000,
dc30c35b 3267 .g1_irqs = 9,
e606ca36 3268 .atu_move_port_mask = 0xf,
f3645652 3269 .pvt = true,
5ebe31d7 3270 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3271 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3272 .ops = &mv88e6161_ops,
f81ec90f
VD		 3273 },
3274
3275 [MV88E6165] = {
107fcc10 3276 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 3277 .family = MV88E6XXX_FAMILY_6165,
3278 .name = "Marvell 88E6165",
3279 .num_databases = 4096,
3280 .num_ports = 6,
3cf3c846 3281 .max_vid = 4095,
9dddd478 3282 .port_base_addr = 0x10,
a935c052 3283 .global1_addr = 0x1b,
acddbd21 3284 .age_time_coeff = 15000,
dc30c35b 3285 .g1_irqs = 9,
e606ca36 3286 .atu_move_port_mask = 0xf,
f3645652 3287 .pvt = true,
443d5a1b 3288 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3289 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3290 .ops = &mv88e6165_ops,
f81ec90f
VD		 3291 },
3292
3293 [MV88E6171] = {
107fcc10 3294 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 3295 .family = MV88E6XXX_FAMILY_6351,
3296 .name = "Marvell 88E6171",
3297 .num_databases = 4096,
3298 .num_ports = 7,
3cf3c846 3299 .max_vid = 4095,
9dddd478 3300 .port_base_addr = 0x10,
a935c052 3301 .global1_addr = 0x1b,
acddbd21 3302 .age_time_coeff = 15000,
dc30c35b 3303 .g1_irqs = 9,
e606ca36 3304 .atu_move_port_mask = 0xf,
f3645652 3305 .pvt = true,
443d5a1b 3306 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3307 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3308 .ops = &mv88e6171_ops,
f81ec90f
VD		 3309 },
3310
3311 [MV88E6172] = {
107fcc10 3312 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 3313 .family = MV88E6XXX_FAMILY_6352,
3314 .name = "Marvell 88E6172",
3315 .num_databases = 4096,
3316 .num_ports = 7,
3cf3c846 3317 .max_vid = 4095,
9dddd478 3318 .port_base_addr = 0x10,
a935c052 3319 .global1_addr = 0x1b,
acddbd21 3320 .age_time_coeff = 15000,
dc30c35b 3321 .g1_irqs = 9,
e606ca36 3322 .atu_move_port_mask = 0xf,
f3645652 3323 .pvt = true,
443d5a1b 3324 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3325 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3326 .ops = &mv88e6172_ops,
f81ec90f
VD		 3327 },
3328
3329 [MV88E6175] = {
107fcc10 3330 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 3331 .family = MV88E6XXX_FAMILY_6351,
3332 .name = "Marvell 88E6175",
3333 .num_databases = 4096,
3334 .num_ports = 7,
3cf3c846 3335 .max_vid = 4095,
9dddd478 3336 .port_base_addr = 0x10,
a935c052 3337 .global1_addr = 0x1b,
acddbd21 3338 .age_time_coeff = 15000,
dc30c35b 3339 .g1_irqs = 9,
e606ca36 3340 .atu_move_port_mask = 0xf,
f3645652 3341 .pvt = true,
443d5a1b 3342 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3343 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3344 .ops = &mv88e6175_ops,
f81ec90f
VD		 3345 },
3346
3347 [MV88E6176] = {
107fcc10 3348 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 3349 .family = MV88E6XXX_FAMILY_6352,
3350 .name = "Marvell 88E6176",
3351 .num_databases = 4096,
3352 .num_ports = 7,
3cf3c846 3353 .max_vid = 4095,
9dddd478 3354 .port_base_addr = 0x10,
a935c052 3355 .global1_addr = 0x1b,
acddbd21 3356 .age_time_coeff = 15000,
dc30c35b 3357 .g1_irqs = 9,
e606ca36 3358 .atu_move_port_mask = 0xf,
f3645652 3359 .pvt = true,
443d5a1b 3360 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3361 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3362 .ops = &mv88e6176_ops,
f81ec90f
VD		 3363 },
3364
3365 [MV88E6185] = {
107fcc10 3366 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 3367 .family = MV88E6XXX_FAMILY_6185,
3368 .name = "Marvell 88E6185",
3369 .num_databases = 256,
3370 .num_ports = 10,
3cf3c846 3371 .max_vid = 4095,
9dddd478 3372 .port_base_addr = 0x10,
a935c052 3373 .global1_addr = 0x1b,
acddbd21 3374 .age_time_coeff = 15000,
dc30c35b 3375 .g1_irqs = 8,
e606ca36 3376 .atu_move_port_mask = 0xf,
443d5a1b 3377 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3378 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3379 .ops = &mv88e6185_ops,
f81ec90f
VD		 3380 },
3381
1a3b39ec 3382 [MV88E6190] = {
107fcc10 3383 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 3384 .family = MV88E6XXX_FAMILY_6390,
3385 .name = "Marvell 88E6190",
3386 .num_databases = 4096,
3387 .num_ports = 11, /* 10 + Z80 */
931d1822 3388 .max_vid = 8191,
1a3b39ec
AL		 3389 .port_base_addr = 0x0,
3390 .global1_addr = 0x1b,
443d5a1b 3391 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3392 .age_time_coeff = 3750,
1a3b39ec 3393 .g1_irqs = 9,
f3645652 3394 .pvt = true,
e606ca36 3395 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3396 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3397 .ops = &mv88e6190_ops,
3398 },
3399
3400 [MV88E6190X] = {
107fcc10 3401 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 3402 .family = MV88E6XXX_FAMILY_6390,
3403 .name = "Marvell 88E6190X",
3404 .num_databases = 4096,
3405 .num_ports = 11, /* 10 + Z80 */
931d1822 3406 .max_vid = 8191,
1a3b39ec
AL		 3407 .port_base_addr = 0x0,
3408 .global1_addr = 0x1b,
b91e055c 3409 .age_time_coeff = 3750,
1a3b39ec 3410 .g1_irqs = 9,
e606ca36 3411 .atu_move_port_mask = 0x1f,
f3645652 3412 .pvt = true,
443d5a1b 3413 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3414 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3415 .ops = &mv88e6190x_ops,
3416 },
3417
3418 [MV88E6191] = {
107fcc10 3419 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 3420 .family = MV88E6XXX_FAMILY_6390,
3421 .name = "Marvell 88E6191",
3422 .num_databases = 4096,
3423 .num_ports = 11, /* 10 + Z80 */
931d1822 3424 .max_vid = 8191,
1a3b39ec
AL		 3425 .port_base_addr = 0x0,
3426 .global1_addr = 0x1b,
b91e055c 3427 .age_time_coeff = 3750,
443d5a1b 3428 .g1_irqs = 9,
e606ca36 3429 .atu_move_port_mask = 0x1f,
f3645652 3430 .pvt = true,
443d5a1b 3431 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec 3432 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
2cf4cefb 3433 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3434 },
3435
f81ec90f 3436 [MV88E6240] = {
107fcc10 3437 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 3438 .family = MV88E6XXX_FAMILY_6352,
3439 .name = "Marvell 88E6240",
3440 .num_databases = 4096,
3441 .num_ports = 7,
3cf3c846 3442 .max_vid = 4095,
9dddd478 3443 .port_base_addr = 0x10,
a935c052 3444 .global1_addr = 0x1b,
acddbd21 3445 .age_time_coeff = 15000,
dc30c35b 3446 .g1_irqs = 9,
e606ca36 3447 .atu_move_port_mask = 0xf,
f3645652 3448 .pvt = true,
443d5a1b 3449 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3450 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3451 .ops = &mv88e6240_ops,
f81ec90f
VD		 3452 },
3453
1a3b39ec 3454 [MV88E6290] = {
107fcc10 3455 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 3456 .family = MV88E6XXX_FAMILY_6390,
3457 .name = "Marvell 88E6290",
3458 .num_databases = 4096,
3459 .num_ports = 11, /* 10 + Z80 */
931d1822 3460 .max_vid = 8191,
1a3b39ec
AL		 3461 .port_base_addr = 0x0,
3462 .global1_addr = 0x1b,
b91e055c 3463 .age_time_coeff = 3750,
1a3b39ec 3464 .g1_irqs = 9,
e606ca36 3465 .atu_move_port_mask = 0x1f,
f3645652 3466 .pvt = true,
443d5a1b 3467 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3468 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3469 .ops = &mv88e6290_ops,
3470 },
3471
f81ec90f 3472 [MV88E6320] = {
107fcc10 3473 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 3474 .family = MV88E6XXX_FAMILY_6320,
3475 .name = "Marvell 88E6320",
3476 .num_databases = 4096,
3477 .num_ports = 7,
3cf3c846 3478 .max_vid = 4095,
9dddd478 3479 .port_base_addr = 0x10,
a935c052 3480 .global1_addr = 0x1b,
acddbd21 3481 .age_time_coeff = 15000,
dc30c35b 3482 .g1_irqs = 8,
e606ca36 3483 .atu_move_port_mask = 0xf,
f3645652 3484 .pvt = true,
443d5a1b 3485 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3486 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3487 .ops = &mv88e6320_ops,
f81ec90f
VD		 3488 },
3489
3490 [MV88E6321] = {
107fcc10 3491 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 3492 .family = MV88E6XXX_FAMILY_6320,
3493 .name = "Marvell 88E6321",
3494 .num_databases = 4096,
3495 .num_ports = 7,
3cf3c846 3496 .max_vid = 4095,
9dddd478 3497 .port_base_addr = 0x10,
a935c052 3498 .global1_addr = 0x1b,
acddbd21 3499 .age_time_coeff = 15000,
dc30c35b 3500 .g1_irqs = 8,
e606ca36 3501 .atu_move_port_mask = 0xf,
443d5a1b 3502 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3503 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3504 .ops = &mv88e6321_ops,
f81ec90f
VD		 3505 },
3506
a75961d0 3507 [MV88E6341] = {
107fcc10 3508 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 3509 .family = MV88E6XXX_FAMILY_6341,
3510 .name = "Marvell 88E6341",
3511 .num_databases = 4096,
3512 .num_ports = 6,
3cf3c846 3513 .max_vid = 4095,
a75961d0
GC		 3514 .port_base_addr = 0x10,
3515 .global1_addr = 0x1b,
3516 .age_time_coeff = 3750,
e606ca36 3517 .atu_move_port_mask = 0x1f,
f3645652 3518 .pvt = true,
a75961d0
GC		 3519 .tag_protocol = DSA_TAG_PROTO_EDSA,
3520 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3521 .ops = &mv88e6341_ops,
3522 },
3523
f81ec90f 3524 [MV88E6350] = {
107fcc10 3525 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 3526 .family = MV88E6XXX_FAMILY_6351,
3527 .name = "Marvell 88E6350",
3528 .num_databases = 4096,
3529 .num_ports = 7,
3cf3c846 3530 .max_vid = 4095,
9dddd478 3531 .port_base_addr = 0x10,
a935c052 3532 .global1_addr = 0x1b,
acddbd21 3533 .age_time_coeff = 15000,
dc30c35b 3534 .g1_irqs = 9,
e606ca36 3535 .atu_move_port_mask = 0xf,
f3645652 3536 .pvt = true,
443d5a1b 3537 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3538 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3539 .ops = &mv88e6350_ops,
f81ec90f
VD		 3540 },
3541
3542 [MV88E6351] = {
107fcc10 3543 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 3544 .family = MV88E6XXX_FAMILY_6351,
3545 .name = "Marvell 88E6351",
3546 .num_databases = 4096,
3547 .num_ports = 7,
3cf3c846 3548 .max_vid = 4095,
9dddd478 3549 .port_base_addr = 0x10,
a935c052 3550 .global1_addr = 0x1b,
acddbd21 3551 .age_time_coeff = 15000,
dc30c35b 3552 .g1_irqs = 9,
e606ca36 3553 .atu_move_port_mask = 0xf,
f3645652 3554 .pvt = true,
443d5a1b 3555 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3556 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3557 .ops = &mv88e6351_ops,
f81ec90f
VD		 3558 },
3559
3560 [MV88E6352] = {
107fcc10 3561 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 3562 .family = MV88E6XXX_FAMILY_6352,
3563 .name = "Marvell 88E6352",
3564 .num_databases = 4096,
3565 .num_ports = 7,
3cf3c846 3566 .max_vid = 4095,
9dddd478 3567 .port_base_addr = 0x10,
a935c052 3568 .global1_addr = 0x1b,
acddbd21 3569 .age_time_coeff = 15000,
dc30c35b 3570 .g1_irqs = 9,
e606ca36 3571 .atu_move_port_mask = 0xf,
f3645652 3572 .pvt = true,
443d5a1b 3573 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3574 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3575 .ops = &mv88e6352_ops,
f81ec90f 3576 },
1a3b39ec 3577 [MV88E6390] = {
107fcc10 3578 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 3579 .family = MV88E6XXX_FAMILY_6390,
3580 .name = "Marvell 88E6390",
3581 .num_databases = 4096,
3582 .num_ports = 11, /* 10 + Z80 */
931d1822 3583 .max_vid = 8191,
1a3b39ec
AL		 3584 .port_base_addr = 0x0,
3585 .global1_addr = 0x1b,
b91e055c 3586 .age_time_coeff = 3750,
1a3b39ec 3587 .g1_irqs = 9,
e606ca36 3588 .atu_move_port_mask = 0x1f,
f3645652 3589 .pvt = true,
443d5a1b 3590 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3591 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3592 .ops = &mv88e6390_ops,
3593 },
3594 [MV88E6390X] = {
107fcc10 3595 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 3596 .family = MV88E6XXX_FAMILY_6390,
3597 .name = "Marvell 88E6390X",
3598 .num_databases = 4096,
3599 .num_ports = 11, /* 10 + Z80 */
931d1822 3600 .max_vid = 8191,
1a3b39ec
AL		 3601 .port_base_addr = 0x0,
3602 .global1_addr = 0x1b,
b91e055c 3603 .age_time_coeff = 3750,
1a3b39ec 3604 .g1_irqs = 9,
e606ca36 3605 .atu_move_port_mask = 0x1f,
f3645652 3606 .pvt = true,
443d5a1b 3607 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3608 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3609 .ops = &mv88e6390x_ops,
3610 },
f81ec90f
VD		 3611};
3612
5f7c0367 3613static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3614{
a439c061 3615 int i;
b9b37713 3616
5f7c0367
VD		 3617 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3618 if (mv88e6xxx_table[i].prod_num == prod_num)
3619 return &mv88e6xxx_table[i];
b9b37713 3620
b9b37713
VD		 3621 return NULL;
3622}
3623
fad09c73 3624static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3625{
3626 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3627 unsigned int prod_num, rev;
3628 u16 id;
3629 int err;
bc46a3d5 3630
8f6345b2 3631 mutex_lock(&chip->reg_lock);
107fcc10 3632 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
8f6345b2
VD		 3633 mutex_unlock(&chip->reg_lock);
3634 if (err)
3635 return err;
bc46a3d5 3636
107fcc10
VD		 3637 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3638 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 3639
3640 info = mv88e6xxx_lookup_info(prod_num);
3641 if (!info)
3642 return -ENODEV;
3643
caac8545 3644 /* Update the compatible info with the probed one */
fad09c73 3645 chip->info = info;
bc46a3d5 3646
ca070c10
VD		 3647 err = mv88e6xxx_g2_require(chip);
3648 if (err)
3649 return err;
3650
fad09c73
VD		 3651 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3652 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3653
3654 return 0;
3655}
3656
fad09c73 3657static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3658{
fad09c73 3659 struct mv88e6xxx_chip *chip;
469d729f 3660
fad09c73
VD		 3661 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3662 if (!chip)
469d729f
VD		 3663 return NULL;
3664
fad09c73 3665 chip->dev = dev;
469d729f 3666
fad09c73 3667 mutex_init(&chip->reg_lock);
a3c53be5 3668 INIT_LIST_HEAD(&chip->mdios);
469d729f 3669
fad09c73 3670 return chip;
469d729f
VD		 3671}
3672
fad09c73 3673static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3674 struct mii_bus *bus, int sw_addr)
3675{
914b32f6 3676 if (sw_addr == 0)
fad09c73 3677 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3678 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3679 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3680 else
3681 return -EINVAL;
3682
fad09c73
VD		 3683 chip->bus = bus;
3684 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3685
3686 return 0;
3687}
3688
7b314362
AL		 3689static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3690{
04bed143 3691 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 3692
443d5a1b 3693 return chip->info->tag_protocol;
7b314362
AL		 3694}
3695
fcdce7d0
AL		 3696static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3697 struct device *host_dev, int sw_addr,
3698 void **priv)
a77d43f1 3699{
fad09c73 3700 struct mv88e6xxx_chip *chip;
a439c061 3701 struct mii_bus *bus;
b516d453 3702 int err;
a77d43f1 3703
a439c061 3704 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3705 if (!bus)
3706 return NULL;
3707
fad09c73
VD		 3708 chip = mv88e6xxx_alloc_chip(dsa_dev);
3709 if (!chip)
469d729f
VD		 3710 return NULL;
3711
caac8545 3712 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3713 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3714
fad09c73 3715 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3716 if (err)
3717 goto free;
3718
fad09c73 3719 err = mv88e6xxx_detect(chip);
bc46a3d5 3720 if (err)
469d729f 3721 goto free;
a439c061 3722
dc30c35b
AL		 3723 mutex_lock(&chip->reg_lock);
3724 err = mv88e6xxx_switch_reset(chip);
3725 mutex_unlock(&chip->reg_lock);
3726 if (err)
3727 goto free;
3728
e57e5e77
VD		 3729 mv88e6xxx_phy_init(chip);
3730
a3c53be5 3731 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 3732 if (err)
469d729f 3733 goto free;
b516d453 3734
fad09c73 3735 *priv = chip;
a439c061 3736
fad09c73 3737 return chip->info->name;
469d729f 3738free:
fad09c73 3739 devm_kfree(dsa_dev, chip);
469d729f
VD		 3740
3741 return NULL;
a77d43f1
AL		 3742}
3743
7df8fbdd
VD		 3744static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3745 const struct switchdev_obj_port_mdb *mdb,
3746 struct switchdev_trans *trans)
3747{
3748 /* We don't need any dynamic resource from the kernel (yet),
3749 * so skip the prepare phase.
3750 */
3751
3752 return 0;
3753}
3754
3755static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3756 const struct switchdev_obj_port_mdb *mdb,
3757 struct switchdev_trans *trans)
3758{
04bed143 3759 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3760
3761 mutex_lock(&chip->reg_lock);
3762 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3763 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
774439e5
VD		 3764 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3765 port);
7df8fbdd
VD		 3766 mutex_unlock(&chip->reg_lock);
3767}
3768
3769static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3770 const struct switchdev_obj_port_mdb *mdb)
3771{
04bed143 3772 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3773 int err;
3774
3775 mutex_lock(&chip->reg_lock);
3776 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3777 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
7df8fbdd
VD		 3778 mutex_unlock(&chip->reg_lock);
3779
3780 return err;
3781}
3782
3783static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3784 struct switchdev_obj_port_mdb *mdb,
438ff537 3785 switchdev_obj_dump_cb_t *cb)
7df8fbdd 3786{
04bed143 3787 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3788 int err;
3789
3790 mutex_lock(&chip->reg_lock);
3791 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3792 mutex_unlock(&chip->reg_lock);
3793
3794 return err;
3795}
3796
a82f67af 3797static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3798 .probe = mv88e6xxx_drv_probe,
7b314362 3799 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3800 .setup = mv88e6xxx_setup,
3801 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3802 .adjust_link = mv88e6xxx_adjust_link,
3803 .get_strings = mv88e6xxx_get_strings,
3804 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3805 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 3806 .port_enable = mv88e6xxx_port_enable,
3807 .port_disable = mv88e6xxx_port_disable,
f81ec90f
VD		 3808 .set_eee = mv88e6xxx_set_eee,
3809 .get_eee = mv88e6xxx_get_eee,
f8cd8753 3810 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3811 .get_eeprom = mv88e6xxx_get_eeprom,
3812 .set_eeprom = mv88e6xxx_set_eeprom,
3813 .get_regs_len = mv88e6xxx_get_regs_len,
3814 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3815 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3816 .port_bridge_join = mv88e6xxx_port_bridge_join,
3817 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3818 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3819 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3820 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3821 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3822 .port_vlan_add = mv88e6xxx_port_vlan_add,
3823 .port_vlan_del = mv88e6xxx_port_vlan_del,
3824 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3825 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3826 .port_fdb_add = mv88e6xxx_port_fdb_add,
3827 .port_fdb_del = mv88e6xxx_port_fdb_del,
3828 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3829 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3830 .port_mdb_add = mv88e6xxx_port_mdb_add,
3831 .port_mdb_del = mv88e6xxx_port_mdb_del,
3832 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
aec5ac88
VD		 3833 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3834 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 3835};
3836
ab3d408d
FF		 3837static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3838 .ops = &mv88e6xxx_switch_ops,
3839};
3840
55ed0ce0 3841static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3842{
fad09c73 3843 struct device *dev = chip->dev;
b7e66a5f
VD		 3844 struct dsa_switch *ds;
3845
73b1204d 3846 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 3847 if (!ds)
3848 return -ENOMEM;
3849
fad09c73 3850 ds->priv = chip;
9d490b4e 3851 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 3852 ds->ageing_time_min = chip->info->age_time_coeff;
3853 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 3854
3855 dev_set_drvdata(dev, ds);
3856
23c9ee49 3857 return dsa_register_switch(ds);
b7e66a5f
VD		 3858}
3859
fad09c73 3860static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3861{
fad09c73 3862 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3863}
3864
57d32310 3865static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3866{
14c7b3c3 3867 struct device *dev = &mdiodev->dev;
f8cd8753 3868 struct device_node *np = dev->of_node;
caac8545 3869 const struct mv88e6xxx_info *compat_info;
fad09c73 3870 struct mv88e6xxx_chip *chip;
f8cd8753 3871 u32 eeprom_len;
52638f71 3872 int err;
14c7b3c3 3873
caac8545
VD		 3874 compat_info = of_device_get_match_data(dev);
3875 if (!compat_info)
3876 return -EINVAL;
3877
fad09c73
VD		 3878 chip = mv88e6xxx_alloc_chip(dev);
3879 if (!chip)
14c7b3c3
AL		 3880 return -ENOMEM;
3881
fad09c73 3882 chip->info = compat_info;
caac8545 3883
fad09c73 3884 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3885 if (err)
3886 return err;
14c7b3c3 3887
b4308f04
AL		 3888 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
3889 if (IS_ERR(chip->reset))
3890 return PTR_ERR(chip->reset);
3891
fad09c73 3892 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3893 if (err)
3894 return err;
14c7b3c3 3895
e57e5e77
VD		 3896 mv88e6xxx_phy_init(chip);
3897
ee4dc2e7 3898 if (chip->info->ops->get_eeprom &&
f8cd8753 3899 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3900 chip->eeprom_len = eeprom_len;
f8cd8753 3901
dc30c35b
AL		 3902 mutex_lock(&chip->reg_lock);
3903 err = mv88e6xxx_switch_reset(chip);
3904 mutex_unlock(&chip->reg_lock);
3905 if (err)
3906 goto out;
3907
3908 chip->irq = of_irq_get(np, 0);
3909 if (chip->irq == -EPROBE_DEFER) {
3910 err = chip->irq;
3911 goto out;
3912 }
3913
3914 if (chip->irq > 0) {
3915 /* Has to be performed before the MDIO bus is created,
3916 * because the PHYs will link there interrupts to these
3917 * interrupt controllers
3918 */
3919 mutex_lock(&chip->reg_lock);
3920 err = mv88e6xxx_g1_irq_setup(chip);
3921 mutex_unlock(&chip->reg_lock);
3922
3923 if (err)
3924 goto out;
3925
3926 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
3927 err = mv88e6xxx_g2_irq_setup(chip);
3928 if (err)
3929 goto out_g1_irq;
3930 }
3931 }
3932
a3c53be5 3933 err = mv88e6xxx_mdios_register(chip, np);
b516d453 3934 if (err)
dc30c35b 3935 goto out_g2_irq;
b516d453 3936
55ed0ce0 3937 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 3938 if (err)
3939 goto out_mdio;
83c0afae 3940
98e67308 3941 return 0;
dc30c35b
AL		 3942
3943out_mdio:
a3c53be5 3944 mv88e6xxx_mdios_unregister(chip);
dc30c35b 3945out_g2_irq:
46712644 3946 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 3947 mv88e6xxx_g2_irq_free(chip);
3948out_g1_irq:
61f7c3f8
AL		 3949 if (chip->irq > 0) {
3950 mutex_lock(&chip->reg_lock);
46712644 3951 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 3952 mutex_unlock(&chip->reg_lock);
3953 }
dc30c35b
AL		 3954out:
3955 return err;
98e67308 3956}
14c7b3c3
AL		 3957
3958static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3959{
3960 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 3961 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 3962
930188ce 3963 mv88e6xxx_phy_destroy(chip);
fad09c73 3964 mv88e6xxx_unregister_switch(chip);
a3c53be5 3965 mv88e6xxx_mdios_unregister(chip);
dc30c35b 3966
46712644
AL		 3967 if (chip->irq > 0) {
3968 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
3969 mv88e6xxx_g2_irq_free(chip);
3970 mv88e6xxx_g1_irq_free(chip);
3971 }
14c7b3c3
AL		 3972}
3973
3974static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 3975 {
3976 .compatible = "marvell,mv88e6085",
3977 .data = &mv88e6xxx_table[MV88E6085],
3978 },
1a3b39ec
AL		 3979 {
3980 .compatible = "marvell,mv88e6190",
3981 .data = &mv88e6xxx_table[MV88E6190],
3982 },
14c7b3c3
AL		 3983 { /* sentinel */ },
3984};
3985
3986MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3987
3988static struct mdio_driver mv88e6xxx_driver = {
3989 .probe = mv88e6xxx_probe,
3990 .remove = mv88e6xxx_remove,
3991 .mdiodrv.driver = {
3992 .name = "mv88e6085",
3993 .of_match_table = mv88e6xxx_of_match,
3994 },
3995};
3996
3997static int __init mv88e6xxx_init(void)
3998{
ab3d408d 3999 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4000 return mdio_driver_register(&mv88e6xxx_driver);
4001}
98e67308
BH		 4002module_init(mv88e6xxx_init);
4003
4004static void __exit mv88e6xxx_cleanup(void)
4005{
14c7b3c3 4006 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4007 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4008}
4009module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4010
4011MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4012MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4013MODULE_LICENSE("GPL");
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