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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
ec561276 35
4d5f2ba7 36#include "chip.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
6d91782f 41#include "serdes.h"
91da11f8 42
fad09c73 43static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 44{
fad09c73
VD		 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 47 dump_stack();
48 }
49}
50
914b32f6
VD		 51/* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 *
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 *
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 61 */
914b32f6 62
fad09c73 63static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 *val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 val)
74{
fad09c73 75 if (!chip->smi_ops)
914b32f6
VD		 76 return -EOPNOTSUPP;
77
fad09c73 78 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 79}
80
fad09c73 81static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 82 int addr, int reg, u16 *val)
83{
84 int ret;
85
fad09c73 86 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 87 if (ret < 0)
88 return ret;
89
90 *val = ret & 0xffff;
91
92 return 0;
93}
94
fad09c73 95static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 96 int addr, int reg, u16 val)
97{
98 int ret;
99
fad09c73 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 101 if (ret < 0)
102 return ret;
103
104 return 0;
105}
106
c08026ab 107static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
110};
111
fad09c73 112static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 113{
114 int ret;
115 int i;
116
117 for (i = 0; i < 16; i++) {
fad09c73 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 119 if (ret < 0)
120 return ret;
121
cca8b133 122 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 123 return 0;
124 }
125
126 return -ETIMEDOUT;
127}
128
fad09c73 129static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 130 int addr, int reg, u16 *val)
91da11f8
LB		 131{
132 int ret;
133
3675c8d7 134 /* Wait for the bus to become free. */
fad09c73 135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the read command. */
fad09c73 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the read command to complete. */
fad09c73 146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 147 if (ret < 0)
148 return ret;
149
3675c8d7 150 /* Read the data. */
fad09c73 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 152 if (ret < 0)
153 return ret;
154
914b32f6 155 *val = ret & 0xffff;
91da11f8 156
914b32f6 157 return 0;
8d6d09e7
GR		 158}
159
fad09c73 160static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 161 int addr, int reg, u16 val)
91da11f8
LB		 162{
163 int ret;
164
3675c8d7 165 /* Wait for the bus to become free. */
fad09c73 166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 167 if (ret < 0)
168 return ret;
169
3675c8d7 170 /* Transmit the data to write. */
fad09c73 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Transmit the write command. */
fad09c73 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 178 if (ret < 0)
179 return ret;
180
3675c8d7 181 /* Wait for the write command to complete. */
fad09c73 182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 183 if (ret < 0)
184 return ret;
185
186 return 0;
187}
188
c08026ab 189static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
192};
193
ec561276 194int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 195{
196 int err;
197
fad09c73 198 assert_reg_lock(chip);
914b32f6 199
fad09c73 200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 201 if (err)
202 return err;
203
fad09c73 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 205 addr, reg, *val);
206
207 return 0;
208}
209
ec561276 210int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 211{
914b32f6
VD		 212 int err;
213
fad09c73 214 assert_reg_lock(chip);
91da11f8 215
fad09c73 216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 217 if (err)
218 return err;
219
fad09c73 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 221 addr, reg, val);
222
914b32f6
VD		 223 return 0;
224}
225
10fa5bfc 226struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 227{
228 struct mv88e6xxx_mdio_bus *mdio_bus;
229
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
231 list);
232 if (!mdio_bus)
233 return NULL;
234
235 return mdio_bus->bus;
236}
237
dc30c35b
AL		 238static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
239{
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
242
243 chip->g1_irq.masked |= (1 << n);
244}
245
246static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
247{
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
250
251 chip->g1_irq.masked &= ~(1 << n);
252}
253
254static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
255{
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
259 unsigned int n;
260 u16 reg;
261 int err;
262
263 mutex_lock(&chip->reg_lock);
82466921 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b
AL		 265 mutex_unlock(&chip->reg_lock);
266
267 if (err)
268 goto out;
269
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
274 ++nhandled;
275 }
276 }
277out:
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
279}
280
281static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
282{
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
284
285 mutex_lock(&chip->reg_lock);
286}
287
288static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
289{
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
292 u16 reg;
293 int err;
294
d77f4321 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 296 if (err)
297 goto out;
298
299 reg &= ~mask;
300 reg |= (~chip->g1_irq.masked & mask);
301
d77f4321 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 303 if (err)
304 goto out;
305
306out:
307 mutex_unlock(&chip->reg_lock);
308}
309
310static struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
316};
317
318static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
319 unsigned int irq,
320 irq_hw_number_t hwirq)
321{
322 struct mv88e6xxx_chip *chip = d->host_data;
323
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
327
328 return 0;
329}
330
331static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
334};
335
336static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
337{
338 int irq, virq;
3460a577
AL		 339 u16 mask;
340
d77f4321 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3460a577 342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577
AL		 344
345 free_irq(chip->irq, chip);
dc30c35b 346
5edef2f2 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 349 irq_dispose_mapping(virq);
350 }
351
a3db3d3a 352 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 353}
354
355static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
356{
3dd0ef05
AL		 357 int err, irq, virq;
358 u16 reg, mask;
dc30c35b
AL		 359
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
365 return -ENOMEM;
366
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
369
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
372
d77f4321 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 374 if (err)
3dd0ef05 375 goto out_mapping;
dc30c35b 376
3dd0ef05 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 378
d77f4321 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 380 if (err)
3dd0ef05 381 goto out_disable;
dc30c35b
AL		 382
383 /* Reading the interrupt status clears (most of) them */
82466921 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 385 if (err)
3dd0ef05 386 goto out_disable;
dc30c35b
AL		 387
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
392 if (err)
3dd0ef05 393 goto out_disable;
dc30c35b
AL		 394
395 return 0;
396
3dd0ef05
AL		 397out_disable:
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 400
401out_mapping:
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
405 }
406
407 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 408
409 return err;
410}
411
ec561276 412int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 413{
6441e669 414 int i;
2d79af6e 415
6441e669 416 for (i = 0; i < 16; i++) {
2d79af6e
VD		 417 u16 val;
418 int err;
419
420 err = mv88e6xxx_read(chip, addr, reg, &val);
421 if (err)
422 return err;
423
424 if (!(val & mask))
425 return 0;
426
427 usleep_range(1000, 2000);
428 }
429
30853553 430 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 431 return -ETIMEDOUT;
432}
433
f22ab641 434/* Indirect write to single pointer-data register with an Update bit */
ec561276 435int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 436{
437 u16 val;
0f02b4f7 438 int err;
f22ab641
VD		 439
440 /* Wait until the previous operation is completed */
0f02b4f7
AL		 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
442 if (err)
443 return err;
f22ab641
VD		 444
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
447
448 return mv88e6xxx_write(chip, addr, reg, val);
449}
450
d78343d2
VD		 451static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
454{
455 int err;
456
457 if (!chip->info->ops->port_set_link)
458 return 0;
459
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
462 if (err)
463 return err;
464
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
468 goto restore_link;
469 }
470
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
474 goto restore_link;
475 }
476
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
480 goto restore_link;
481 }
482
f39908d3
AL		 483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
486 goto restore_link;
487 }
488
d78343d2
VD		 489 err = 0;
490restore_link:
491 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 493
494 return err;
495}
496
dea87024
AL		 497/* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
500 */
f81ec90f
VD		 501static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
dea87024 503{
04bed143 504 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 505 int err;
dea87024
AL		 506
507 if (!phy_is_pseudo_fixed_link(phydev))
508 return;
509
fad09c73 510 mutex_lock(&chip->reg_lock);
d78343d2
VD		 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
fad09c73 513 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 514
515 if (err && err != -EOPNOTSUPP)
774439e5 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
dea87024
AL		 517}
518
a605a0fe 519static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 520{
a605a0fe
AL		 521 if (!chip->info->ops->stats_snapshot)
522 return -EOPNOTSUPP;
91da11f8 523
a605a0fe 524 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 525}
526
e413e7e1 527static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 587};
588
fad09c73 589static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 590 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 591 int port, u16 bank1_select,
592 u16 histogram)
80c4627b 593{
80c4627b
AL		 594 u32 low;
595 u32 high = 0;
dfafe449 596 u16 reg = 0;
0e7b9925 597 int err;
80c4627b
AL		 598 u64 value;
599
f5e2ed02 600 switch (s->type) {
dfafe449 601 case STATS_TYPE_PORT:
0e7b9925
AL		 602 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
603 if (err)
80c4627b
AL		 604 return UINT64_MAX;
605
0e7b9925 606 low = reg;
80c4627b 607 if (s->sizeof_stat == 4) {
0e7b9925
AL		 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
609 if (err)
80c4627b 610 return UINT64_MAX;
0e7b9925 611 high = reg;
80c4627b 612 }
f5e2ed02 613 break;
dfafe449 614 case STATS_TYPE_BANK1:
e0d8b615 615 reg = bank1_select;
dfafe449
AL		 616 /* fall through */
617 case STATS_TYPE_BANK0:
e0d8b615 618 reg |= s->reg | histogram;
7f9ef3af 619 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 620 if (s->sizeof_stat == 8)
7f9ef3af 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 622 break;
623 default:
624 return UINT64_MAX;
80c4627b
AL		 625 }
626 value = (((u64)high) << 16) | low;
627 return value;
628}
629
dfafe449
AL		 630static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
91da11f8 632{
f5e2ed02
AL		 633 struct mv88e6xxx_hw_stat *stat;
634 int i, j;
91da11f8 635
f5e2ed02
AL		 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
dfafe449 638 if (stat->type & types) {
f5e2ed02
AL		 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
640 ETH_GSTRING_LEN);
641 j++;
642 }
91da11f8 643 }
e413e7e1
AL		 644}
645
dfafe449
AL		 646static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
647 uint8_t *data)
648{
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
651}
652
653static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
654 uint8_t *data)
655{
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
658}
659
660static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
661 uint8_t *data)
e413e7e1 662{
04bed143 663 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 664
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
667}
668
669static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
670 int types)
671{
f5e2ed02
AL		 672 struct mv88e6xxx_hw_stat *stat;
673 int i, j;
674
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
dfafe449 677 if (stat->type & types)
f5e2ed02
AL		 678 j++;
679 }
680 return j;
e413e7e1
AL		 681}
682
dfafe449
AL		 683static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
684{
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
686 STATS_TYPE_PORT);
687}
688
689static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
690{
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
692 STATS_TYPE_BANK1);
693}
694
695static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
696{
697 struct mv88e6xxx_chip *chip = ds->priv;
698
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
701
702 return 0;
703}
704
052f947f 705static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
052f947f
AL		 708{
709 struct mv88e6xxx_hw_stat *stat;
710 int i, j;
711
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
e0d8b615
AL		 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
716 bank1_select,
717 histogram);
052f947f
AL		 718 j++;
719 }
720 }
721}
722
723static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
724 uint64_t *data)
725{
726 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 729}
730
731static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
732 uint64_t *data)
733{
734 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 738}
739
740static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
741 uint64_t *data)
742{
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
746 0);
052f947f
AL		 747}
748
749static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
750 uint64_t *data)
751{
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
754}
755
f81ec90f
VD		 756static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
757 uint64_t *data)
e413e7e1 758{
04bed143 759 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 760 int ret;
f5e2ed02 761
fad09c73 762 mutex_lock(&chip->reg_lock);
f5e2ed02 763
a605a0fe 764 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 765 if (ret < 0) {
fad09c73 766 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 767 return;
768 }
052f947f
AL		 769
770 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 771
fad09c73 772 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 773}
774
de227387
AL		 775static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
776{
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
779
780 return 0;
781}
782
f81ec90f 783static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 784{
785 return 32 * sizeof(u16);
786}
787
f81ec90f
VD		 788static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
a1ab91f3 790{
04bed143 791 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 792 int err;
793 u16 reg;
a1ab91f3
GR		 794 u16 *p = _p;
795 int i;
796
797 regs->version = 0;
798
799 memset(p, 0xff, 32 * sizeof(u16));
800
fad09c73 801 mutex_lock(&chip->reg_lock);
23062513 802
a1ab91f3 803 for (i = 0; i < 32; i++) {
a1ab91f3 804
0e7b9925
AL		 805 err = mv88e6xxx_port_read(chip, port, i, &reg);
806 if (!err)
807 p[i] = reg;
a1ab91f3 808 }
23062513 809
fad09c73 810 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 811}
812
f81ec90f
VD		 813static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
814 struct ethtool_eee *e)
11b3b45d 815{
04bed143 816 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 817 u16 reg;
818 int err;
11b3b45d 819
fad09c73 820 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 821 return -EOPNOTSUPP;
822
fad09c73 823 mutex_lock(&chip->reg_lock);
2f40c698 824
9c93829c
VD		 825 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
826 if (err)
2f40c698 827 goto out;
11b3b45d
GR		 828
829 e->eee_enabled = !!(reg & 0x0200);
830 e->tx_lpi_enabled = !!(reg & 0x0100);
831
5f83dc93 832 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
9c93829c 833 if (err)
2f40c698 834 goto out;
11b3b45d 835
5f83dc93 836 e->eee_active = !!(reg & MV88E6352_PORT_STS_EEE);
2f40c698 837out:
fad09c73 838 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 839
840 return err;
11b3b45d
GR		 841}
842
f81ec90f
VD		 843static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
844 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 845{
04bed143 846 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 847 u16 reg;
848 int err;
11b3b45d 849
fad09c73 850 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 851 return -EOPNOTSUPP;
852
fad09c73 853 mutex_lock(&chip->reg_lock);
11b3b45d 854
9c93829c
VD		 855 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
856 if (err)
2f40c698
AL		 857 goto out;
858
9c93829c 859 reg &= ~0x0300;
2f40c698
AL		 860 if (e->eee_enabled)
861 reg |= 0x0200;
862 if (e->tx_lpi_enabled)
863 reg |= 0x0100;
864
9c93829c 865 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 866out:
fad09c73 867 mutex_unlock(&chip->reg_lock);
2f40c698 868
9c93829c 869 return err;
11b3b45d
GR		 870}
871
e5887a2a 872static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 873{
e5887a2a
VD		 874 struct dsa_switch *ds = NULL;
875 struct net_device *br;
876 u16 pvlan;
b7666efe
VD		 877 int i;
878
e5887a2a
VD		 879 if (dev < DSA_MAX_SWITCHES)
880 ds = chip->ds->dst->ds[dev];
881
882 /* Prevent frames from unknown switch or port */
883 if (!ds || port >= ds->num_ports)
884 return 0;
885
886 /* Frames from DSA links and CPU ports can egress any local port */
887 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
888 return mv88e6xxx_port_mask(chip);
889
890 br = ds->ports[port].bridge_dev;
891 pvlan = 0;
892
893 /* Frames from user ports can egress any local DSA links and CPU ports,
894 * as well as any local member of their bridge group.
895 */
896 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
897 if (dsa_is_cpu_port(chip->ds, i) ||
898 dsa_is_dsa_port(chip->ds, i) ||
899 (br && chip->ds->ports[i].bridge_dev == br))
900 pvlan |= BIT(i);
901
902 return pvlan;
903}
904
240ea3ef 905static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 906{
907 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 908
909 /* prevent frames from going back out of the port they came in on */
910 output_ports &= ~BIT(port);
facd95b2 911
5a7921f4 912 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 913}
914
f81ec90f
VD		 915static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
916 u8 state)
facd95b2 917{
04bed143 918 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 919 int err;
facd95b2 920
fad09c73 921 mutex_lock(&chip->reg_lock);
f894c29c 922 err = mv88e6xxx_port_set_state(chip, port, state);
fad09c73 923 mutex_unlock(&chip->reg_lock);
553eb544
VD		 924
925 if (err)
774439e5 926 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 927}
928
a2ac29d2
VD		 929static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
930{
c3a7d4ad
VD		 931 int err;
932
daefc943
VD		 933 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
934 if (err)
935 return err;
936
c3a7d4ad
VD		 937 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
938 if (err)
939 return err;
940
a2ac29d2
VD		 941 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
942}
943
cd8da8bb
VD		 944static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
945{
946 int port;
947 int err;
948
949 if (!chip->info->ops->irl_init_all)
950 return 0;
951
952 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
953 /* Disable ingress rate limiting by resetting all per port
954 * ingress rate limit resources to their initial state.
955 */
956 err = chip->info->ops->irl_init_all(chip, port);
957 if (err)
958 return err;
959 }
960
961 return 0;
962}
963
17a1594e
VD		 964static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
965{
966 u16 pvlan = 0;
967
968 if (!mv88e6xxx_has_pvt(chip))
969 return -EOPNOTSUPP;
970
971 /* Skip the local source device, which uses in-chip port VLAN */
972 if (dev != chip->ds->index)
aec5ac88 973 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 974
975 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
976}
977
81228996
VD		 978static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
979{
17a1594e
VD		 980 int dev, port;
981 int err;
982
81228996
VD		 983 if (!mv88e6xxx_has_pvt(chip))
984 return 0;
985
986 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
987 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
988 */
17a1594e
VD		 989 err = mv88e6xxx_g2_misc_4_bit_port(chip);
990 if (err)
991 return err;
992
993 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
994 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
995 err = mv88e6xxx_pvt_map(chip, dev, port);
996 if (err)
997 return err;
998 }
999 }
1000
1001 return 0;
81228996
VD		 1002}
1003
749efcb8
VD		 1004static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1005{
1006 struct mv88e6xxx_chip *chip = ds->priv;
1007 int err;
1008
1009 mutex_lock(&chip->reg_lock);
e606ca36 1010 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1011 mutex_unlock(&chip->reg_lock);
1012
1013 if (err)
774439e5 1014 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 1015}
1016
b486d7c9
VD		 1017static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1018{
1019 if (!chip->info->max_vid)
1020 return 0;
1021
1022 return mv88e6xxx_g1_vtu_flush(chip);
1023}
1024
f1394b78
VD		 1025static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1026 struct mv88e6xxx_vtu_entry *entry)
1027{
1028 if (!chip->info->ops->vtu_getnext)
1029 return -EOPNOTSUPP;
1030
1031 return chip->info->ops->vtu_getnext(chip, entry);
1032}
1033
0ad5daf6
VD		 1034static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1035 struct mv88e6xxx_vtu_entry *entry)
1036{
1037 if (!chip->info->ops->vtu_loadpurge)
1038 return -EOPNOTSUPP;
1039
1040 return chip->info->ops->vtu_loadpurge(chip, entry);
1041}
1042
f81ec90f
VD		 1043static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1044 struct switchdev_obj_port_vlan *vlan,
438ff537 1045 switchdev_obj_dump_cb_t *cb)
ceff5eff 1046{
04bed143 1047 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1048 struct mv88e6xxx_vtu_entry next = {
1049 .vid = chip->info->max_vid,
1050 };
ceff5eff
VD		 1051 u16 pvid;
1052 int err;
1053
3cf3c846 1054 if (!chip->info->max_vid)
54d77b5b
VD		 1055 return -EOPNOTSUPP;
1056
fad09c73 1057 mutex_lock(&chip->reg_lock);
ceff5eff 1058
77064f37 1059 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1060 if (err)
1061 goto unlock;
1062
ceff5eff 1063 do {
f1394b78 1064 err = mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1065 if (err)
1066 break;
1067
1068 if (!next.valid)
1069 break;
1070
7ec60d6e
VD		 1071 if (next.member[port] ==
1072 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
ceff5eff
VD		 1073 continue;
1074
1075 /* reinit and dump this VLAN obj */
57d32310
VD		 1076 vlan->vid_begin = next.vid;
1077 vlan->vid_end = next.vid;
ceff5eff
VD		 1078 vlan->flags = 0;
1079
7ec60d6e
VD		 1080 if (next.member[port] ==
1081 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED)
ceff5eff
VD		 1082 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1083
1084 if (next.vid == pvid)
1085 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1086
1087 err = cb(&vlan->obj);
1088 if (err)
1089 break;
3cf3c846 1090 } while (next.vid < chip->info->max_vid);
ceff5eff
VD		 1091
1092unlock:
fad09c73 1093 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1094
1095 return err;
1096}
1097
d7f435f9 1098static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1099{
1100 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
3afb4bde
VD		 1101 struct mv88e6xxx_vtu_entry vlan = {
1102 .vid = chip->info->max_vid,
1103 };
2db9ce1f 1104 int i, err;
3285f9e8
VD		 1105
1106 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1107
2db9ce1f 1108 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1109 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1110 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1111 if (err)
1112 return err;
1113
1114 set_bit(*fid, fid_bitmap);
1115 }
1116
3285f9e8 1117 /* Set every FID bit used by the VLAN entries */
3285f9e8 1118 do {
f1394b78 1119 err = mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1120 if (err)
1121 return err;
1122
1123 if (!vlan.valid)
1124 break;
1125
1126 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1127 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1128
1129 /* The reset value 0x000 is used to indicate that multiple address
1130 * databases are not needed. Return the next positive available.
1131 */
1132 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1133 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1134 return -ENOSPC;
1135
1136 /* Clear the database */
daefc943 1137 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1138}
1139
567aa59a
VD		 1140static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1141 struct mv88e6xxx_vtu_entry *entry, bool new)
2fb5ef09
VD		 1142{
1143 int err;
1144
1145 if (!vid)
1146 return -EINVAL;
1147
3afb4bde
VD		 1148 entry->vid = vid - 1;
1149 entry->valid = false;
2fb5ef09 1150
f1394b78 1151 err = mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1152 if (err)
1153 return err;
1154
567aa59a
VD		 1155 if (entry->vid == vid && entry->valid)
1156 return 0;
2fb5ef09 1157
567aa59a
VD		 1158 if (new) {
1159 int i;
1160
1161 /* Initialize a fresh VLAN entry */
1162 memset(entry, 0, sizeof(*entry));
1163 entry->valid = true;
1164 entry->vid = vid;
1165
553a768d 1166 /* Exclude all ports */
567aa59a 1167 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
553a768d 1168 entry->member[i] =
7ec60d6e 1169 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
567aa59a
VD		 1170
1171 return mv88e6xxx_atu_new(chip, &entry->fid);
2fb5ef09
VD		 1172 }
1173
567aa59a
VD		 1174 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1175 return -EOPNOTSUPP;
2fb5ef09
VD		 1176}
1177
da9c359e
VD		 1178static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1179 u16 vid_begin, u16 vid_end)
1180{
04bed143 1181 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1182 struct mv88e6xxx_vtu_entry vlan = {
1183 .vid = vid_begin - 1,
1184 };
da9c359e
VD		 1185 int i, err;
1186
1187 if (!vid_begin)
1188 return -EOPNOTSUPP;
1189
fad09c73 1190 mutex_lock(&chip->reg_lock);
da9c359e 1191
da9c359e 1192 do {
f1394b78 1193 err = mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1194 if (err)
1195 goto unlock;
1196
1197 if (!vlan.valid)
1198 break;
1199
1200 if (vlan.vid > vid_end)
1201 break;
1202
370b4ffb 1203 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1204 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1205 continue;
1206
66e2809d
AL		 1207 if (!ds->ports[port].netdev)
1208 continue;
1209
bd00e053 1210 if (vlan.member[i] ==
7ec60d6e 1211 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
da9c359e
VD		 1212 continue;
1213
fae8a25e
VD		 1214 if (ds->ports[i].bridge_dev ==
1215 ds->ports[port].bridge_dev)
da9c359e
VD		 1216 break; /* same bridge, check next VLAN */
1217
fae8a25e 1218 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1219 continue;
1220
774439e5
VD		 1221 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1222 port, vlan.vid,
1223 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1224 err = -EOPNOTSUPP;
1225 goto unlock;
1226 }
1227 } while (vlan.vid < vid_end);
1228
1229unlock:
fad09c73 1230 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1231
1232 return err;
1233}
1234
f81ec90f
VD		 1235static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1236 bool vlan_filtering)
214cdb99 1237{
04bed143 1238 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1239 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1240 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1241 int err;
214cdb99 1242
3cf3c846 1243 if (!chip->info->max_vid)
54d77b5b
VD		 1244 return -EOPNOTSUPP;
1245
fad09c73 1246 mutex_lock(&chip->reg_lock);
385a0995 1247 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1248 mutex_unlock(&chip->reg_lock);
214cdb99 1249
0e7b9925 1250 return err;
214cdb99
VD		 1251}
1252
57d32310
VD		 1253static int
1254mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1255 const struct switchdev_obj_port_vlan *vlan,
1256 struct switchdev_trans *trans)
76e398a6 1257{
04bed143 1258 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1259 int err;
1260
3cf3c846 1261 if (!chip->info->max_vid)
54d77b5b
VD		 1262 return -EOPNOTSUPP;
1263
da9c359e
VD		 1264 /* If the requested port doesn't belong to the same bridge as the VLAN
1265 * members, do not support it (yet) and fallback to software VLAN.
1266 */
1267 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1268 vlan->vid_end);
1269 if (err)
1270 return err;
1271
76e398a6
VD		 1272 /* We don't need any dynamic resource from the kernel (yet),
1273 * so skip the prepare phase.
1274 */
1275 return 0;
1276}
1277
fad09c73 1278static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
c91498e1 1279 u16 vid, u8 member)
0d3b33e6 1280{
b4e47c0f 1281 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1282 int err;
1283
567aa59a 1284 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1285 if (err)
76e398a6 1286 return err;
0d3b33e6 1287
c91498e1 1288 vlan.member[port] = member;
0d3b33e6 1289
0ad5daf6 1290 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1291}
1292
f81ec90f
VD		 1293static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1294 const struct switchdev_obj_port_vlan *vlan,
1295 struct switchdev_trans *trans)
76e398a6 1296{
04bed143 1297 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1298 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1299 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
c91498e1 1300 u8 member;
76e398a6 1301 u16 vid;
76e398a6 1302
3cf3c846 1303 if (!chip->info->max_vid)
54d77b5b
VD		 1304 return;
1305
c91498e1 1306 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 1307 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 1308 else if (untagged)
7ec60d6e 1309 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 1310 else
7ec60d6e 1311 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 1312
fad09c73 1313 mutex_lock(&chip->reg_lock);
76e398a6 1314
4d5770b3 1315 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
c91498e1 1316 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
774439e5
VD		 1317 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1318 vid, untagged ? 'u' : 't');
76e398a6 1319
77064f37 1320 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
774439e5
VD		 1321 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1322 vlan->vid_end);
0d3b33e6 1323
fad09c73 1324 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1325}
1326
fad09c73 1327static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1328 int port, u16 vid)
7dad08d7 1329{
b4e47c0f 1330 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1331 int i, err;
1332
567aa59a 1333 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1334 if (err)
76e398a6 1335 return err;
7dad08d7 1336
2fb5ef09 1337 /* Tell switchdev if this VLAN is handled in software */
7ec60d6e 1338 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1339 return -EOPNOTSUPP;
7dad08d7 1340
7ec60d6e 1341 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1342
1343 /* keep the VLAN unless all ports are excluded */
f02bdffc 1344 vlan.valid = false;
370b4ffb 1345 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 1346 if (vlan.member[i] !=
1347 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1348 vlan.valid = true;
7dad08d7
VD		 1349 break;
1350 }
1351 }
1352
0ad5daf6 1353 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1354 if (err)
1355 return err;
1356
e606ca36 1357 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1358}
1359
f81ec90f
VD		 1360static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1361 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1362{
04bed143 1363 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1364 u16 pvid, vid;
1365 int err = 0;
1366
3cf3c846 1367 if (!chip->info->max_vid)
54d77b5b
VD		 1368 return -EOPNOTSUPP;
1369
fad09c73 1370 mutex_lock(&chip->reg_lock);
76e398a6 1371
77064f37 1372 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1373 if (err)
1374 goto unlock;
1375
76e398a6 1376 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1377 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1378 if (err)
1379 goto unlock;
1380
1381 if (vid == pvid) {
77064f37 1382 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1383 if (err)
1384 goto unlock;
1385 }
1386 }
1387
7dad08d7 1388unlock:
fad09c73 1389 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1390
1391 return err;
1392}
1393
83dabd1f
VD		 1394static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1395 const unsigned char *addr, u16 vid,
1396 u8 state)
fd231c82 1397{
b4e47c0f 1398 struct mv88e6xxx_vtu_entry vlan;
88472939 1399 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1400 int err;
1401
2db9ce1f
VD		 1402 /* Null VLAN ID corresponds to the port private database */
1403 if (vid == 0)
b4e48c50 1404 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1405 else
567aa59a 1406 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1407 if (err)
1408 return err;
fd231c82 1409
27c0e600 1410 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96
VD		 1411 ether_addr_copy(entry.mac, addr);
1412 eth_addr_dec(entry.mac);
1413
1414 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1415 if (err)
1416 return err;
1417
dabc1a96 1418 /* Initialize a fresh ATU entry if it isn't found */
27c0e600 1419 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
dabc1a96
VD		 1420 !ether_addr_equal(entry.mac, addr)) {
1421 memset(&entry, 0, sizeof(entry));
1422 ether_addr_copy(entry.mac, addr);
1423 }
1424
88472939 1425 /* Purge the ATU entry only if no port is using it anymore */
27c0e600 1426 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1427 entry.portvec &= ~BIT(port);
1428 if (!entry.portvec)
27c0e600 1429 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
88472939 1430 } else {
01bd96c8 1431 entry.portvec |= BIT(port);
88472939 1432 entry.state = state;
fd231c82
VD		 1433 }
1434
9c13c026 1435 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1436}
1437
f81ec90f
VD		 1438static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1439 const struct switchdev_obj_port_fdb *fdb,
1440 struct switchdev_trans *trans)
146a3206
VD		 1441{
1442 /* We don't need any dynamic resource from the kernel (yet),
1443 * so skip the prepare phase.
1444 */
1445 return 0;
1446}
1447
f81ec90f
VD		 1448static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1449 const struct switchdev_obj_port_fdb *fdb,
1450 struct switchdev_trans *trans)
87820510 1451{
04bed143 1452 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1453
fad09c73 1454 mutex_lock(&chip->reg_lock);
83dabd1f 1455 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
27c0e600 1456 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC))
774439e5
VD		 1457 dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
1458 port);
fad09c73 1459 mutex_unlock(&chip->reg_lock);
87820510
VD		 1460}
1461
f81ec90f
VD		 1462static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1463 const struct switchdev_obj_port_fdb *fdb)
87820510 1464{
04bed143 1465 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1466 int err;
87820510 1467
fad09c73 1468 mutex_lock(&chip->reg_lock);
83dabd1f 1469 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
27c0e600 1470 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
fad09c73 1471 mutex_unlock(&chip->reg_lock);
87820510 1472
83dabd1f 1473 return err;
87820510
VD		 1474}
1475
83dabd1f
VD		 1476static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1477 u16 fid, u16 vid, int port,
1478 struct switchdev_obj *obj,
438ff537 1479 switchdev_obj_dump_cb_t *cb)
74b6ba0d 1480{
dabc1a96 1481 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 1482 int err;
1483
27c0e600 1484 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96 1485 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1486
1487 do {
dabc1a96 1488 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1489 if (err)
83dabd1f 1490 return err;
74b6ba0d 1491
27c0e600 1492 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
74b6ba0d
VD		 1493 break;
1494
01bd96c8 1495 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1496 continue;
1497
1498 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1499 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 1500
83dabd1f
VD		 1501 if (!is_unicast_ether_addr(addr.mac))
1502 continue;
1503
1504 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 1505 fdb->vid = vid;
1506 ether_addr_copy(fdb->addr, addr.mac);
27c0e600 1507 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
83dabd1f
VD		 1508 fdb->ndm_state = NUD_NOARP;
1509 else
1510 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 1511 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1512 struct switchdev_obj_port_mdb *mdb;
1513
1514 if (!is_multicast_ether_addr(addr.mac))
1515 continue;
1516
1517 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1518 mdb->vid = vid;
1519 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 1520 } else {
1521 return -EOPNOTSUPP;
74b6ba0d 1522 }
83dabd1f
VD		 1523
1524 err = cb(obj);
1525 if (err)
1526 return err;
74b6ba0d
VD		 1527 } while (!is_broadcast_ether_addr(addr.mac));
1528
1529 return err;
1530}
1531
83dabd1f
VD		 1532static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1533 struct switchdev_obj *obj,
438ff537 1534 switchdev_obj_dump_cb_t *cb)
f33475bd 1535{
b4e47c0f 1536 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 1537 .vid = chip->info->max_vid,
f33475bd 1538 };
2db9ce1f 1539 u16 fid;
f33475bd
VD		 1540 int err;
1541
2db9ce1f 1542 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 1543 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 1544 if (err)
83dabd1f 1545 return err;
2db9ce1f 1546
83dabd1f 1547 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 1548 if (err)
83dabd1f 1549 return err;
2db9ce1f 1550
74b6ba0d 1551 /* Dump VLANs' Filtering Information Databases */
f33475bd 1552 do {
f1394b78 1553 err = mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 1554 if (err)
83dabd1f 1555 return err;
f33475bd
VD		 1556
1557 if (!vlan.valid)
1558 break;
1559
83dabd1f
VD		 1560 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1561 obj, cb);
f33475bd 1562 if (err)
83dabd1f 1563 return err;
3cf3c846 1564 } while (vlan.vid < chip->info->max_vid);
f33475bd 1565
83dabd1f
VD		 1566 return err;
1567}
1568
1569static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1570 struct switchdev_obj_port_fdb *fdb,
438ff537 1571 switchdev_obj_dump_cb_t *cb)
83dabd1f 1572{
04bed143 1573 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 1574 int err;
1575
1576 mutex_lock(&chip->reg_lock);
1577 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 1578 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 1579
1580 return err;
1581}
1582
240ea3ef
VD		 1583static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1584 struct net_device *br)
e79a8bcb 1585{
e96a6e02 1586 struct dsa_switch *ds;
240ea3ef 1587 int port;
e96a6e02 1588 int dev;
240ea3ef 1589 int err;
466dfa07 1590
240ea3ef
VD		 1591 /* Remap the Port VLAN of each local bridge group member */
1592 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1593 if (chip->ds->ports[port].bridge_dev == br) {
1594 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 1595 if (err)
240ea3ef 1596 return err;
b7666efe
VD		 1597 }
1598 }
1599
e96a6e02
VD		 1600 if (!mv88e6xxx_has_pvt(chip))
1601 return 0;
1602
1603 /* Remap the Port VLAN of each cross-chip bridge group member */
1604 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1605 ds = chip->ds->dst->ds[dev];
1606 if (!ds)
1607 break;
1608
1609 for (port = 0; port < ds->num_ports; ++port) {
1610 if (ds->ports[port].bridge_dev == br) {
1611 err = mv88e6xxx_pvt_map(chip, dev, port);
1612 if (err)
1613 return err;
1614 }
1615 }
1616 }
1617
240ea3ef
VD		 1618 return 0;
1619}
1620
1621static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1622 struct net_device *br)
1623{
1624 struct mv88e6xxx_chip *chip = ds->priv;
1625 int err;
1626
1627 mutex_lock(&chip->reg_lock);
1628 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 1629 mutex_unlock(&chip->reg_lock);
a6692754 1630
466dfa07 1631 return err;
e79a8bcb
VD		 1632}
1633
f123f2fb
VD		 1634static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1635 struct net_device *br)
66d9cd0f 1636{
04bed143 1637 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 1638
fad09c73 1639 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 1640 if (mv88e6xxx_bridge_map(chip, br) ||
1641 mv88e6xxx_port_vlan_map(chip, port))
1642 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 1643 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 1644}
1645
aec5ac88
VD		 1646static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1647 int port, struct net_device *br)
1648{
1649 struct mv88e6xxx_chip *chip = ds->priv;
1650 int err;
1651
1652 if (!mv88e6xxx_has_pvt(chip))
1653 return 0;
1654
1655 mutex_lock(&chip->reg_lock);
1656 err = mv88e6xxx_pvt_map(chip, dev, port);
1657 mutex_unlock(&chip->reg_lock);
1658
1659 return err;
1660}
1661
1662static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1663 int port, struct net_device *br)
1664{
1665 struct mv88e6xxx_chip *chip = ds->priv;
1666
1667 if (!mv88e6xxx_has_pvt(chip))
1668 return;
1669
1670 mutex_lock(&chip->reg_lock);
1671 if (mv88e6xxx_pvt_map(chip, dev, port))
1672 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1673 mutex_unlock(&chip->reg_lock);
1674}
1675
17e708ba
VD		 1676static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1677{
1678 if (chip->info->ops->reset)
1679 return chip->info->ops->reset(chip);
1680
1681 return 0;
1682}
1683
309eca6d
VD		 1684static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1685{
1686 struct gpio_desc *gpiod = chip->reset;
1687
1688 /* If there is a GPIO connected to the reset pin, toggle it */
1689 if (gpiod) {
1690 gpiod_set_value_cansleep(gpiod, 1);
1691 usleep_range(10000, 20000);
1692 gpiod_set_value_cansleep(gpiod, 0);
1693 usleep_range(10000, 20000);
1694 }
1695}
1696
4ac4b5a6 1697static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 1698{
4ac4b5a6 1699 int i, err;
552238b5 1700
4ac4b5a6 1701 /* Set all ports to the Disabled state */
370b4ffb 1702 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 1703 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 1704 if (err)
1705 return err;
552238b5
VD		 1706 }
1707
4ac4b5a6
VD		 1708 /* Wait for transmit queues to drain,
1709 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1710 */
552238b5
VD		 1711 usleep_range(2000, 4000);
1712
4ac4b5a6
VD		 1713 return 0;
1714}
1715
1716static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1717{
4ac4b5a6
VD		 1718 int err;
1719
1720 err = mv88e6xxx_disable_ports(chip);
1721 if (err)
1722 return err;
1723
309eca6d 1724 mv88e6xxx_hardware_reset(chip);
552238b5 1725
17e708ba 1726 return mv88e6xxx_software_reset(chip);
552238b5
VD		 1727}
1728
4314557c 1729static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 1730 enum mv88e6xxx_frame_mode frame,
1731 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 1732{
1733 int err;
1734
4314557c
VD		 1735 if (!chip->info->ops->port_set_frame_mode)
1736 return -EOPNOTSUPP;
1737
1738 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 1739 if (err)
1740 return err;
1741
4314557c
VD		 1742 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1743 if (err)
1744 return err;
1745
1746 if (chip->info->ops->port_set_ether_type)
1747 return chip->info->ops->port_set_ether_type(chip, port, etype);
1748
1749 return 0;
56995cbc
AL		 1750}
1751
4314557c 1752static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 1753{
4314557c 1754 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 1755 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1756 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1757}
56995cbc 1758
4314557c
VD		 1759static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1760{
1761 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 1762 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1763 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1764}
56995cbc 1765
4314557c
VD		 1766static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1767{
1768 return mv88e6xxx_set_port_mode(chip, port,
1769 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 1770 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1771 ETH_P_EDSA);
4314557c 1772}
56995cbc 1773
4314557c
VD		 1774static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1775{
1776 if (dsa_is_dsa_port(chip->ds, port))
1777 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1778
4314557c
VD		 1779 if (dsa_is_normal_port(chip->ds, port))
1780 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 1781
4314557c
VD		 1782 /* Setup CPU port mode depending on its supported tag format */
1783 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1784 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1785
4314557c
VD		 1786 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1787 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 1788
4314557c 1789 return -EINVAL;
56995cbc
AL		 1790}
1791
601aeed3 1792static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 1793{
601aeed3 1794 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 1795
601aeed3 1796 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 1797}
56995cbc 1798
601aeed3 1799static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 1800{
601aeed3 1801 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 1802
601aeed3
VD		 1803 /* Upstream ports flood frames with unknown unicast or multicast DA */
1804 if (chip->info->ops->port_set_egress_floods)
1805 return chip->info->ops->port_set_egress_floods(chip, port,
1806 flood, flood);
ea698f4f 1807
601aeed3 1808 return 0;
ea698f4f
VD		 1809}
1810
6d91782f
AL		 1811static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1812 bool on)
1813{
523a8904
VD		 1814 if (chip->info->ops->serdes_power)
1815 return chip->info->ops->serdes_power(chip, port, on);
04aca993 1816
523a8904 1817 return 0;
6d91782f
AL		 1818}
1819
fad09c73 1820static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 1821{
fad09c73 1822 struct dsa_switch *ds = chip->ds;
0e7b9925 1823 int err;
54d792f2 1824 u16 reg;
d827e88a 1825
d78343d2
VD		 1826 /* MAC Forcing register: don't force link, speed, duplex or flow control
1827 * state to any particular values on physical ports, but force the CPU
1828 * port and all DSA ports to their maximum bandwidth and full duplex.
1829 */
1830 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1831 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1832 SPEED_MAX, DUPLEX_FULL,
1833 PHY_INTERFACE_MODE_NA);
1834 else
1835 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1836 SPEED_UNFORCED, DUPLEX_UNFORCED,
1837 PHY_INTERFACE_MODE_NA);
1838 if (err)
1839 return err;
54d792f2
AL		 1840
1841 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1842 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1843 * tunneling, determine priority by looking at 802.1p and IP
1844 * priority fields (IP prio has precedence), and set STP state
1845 * to Forwarding.
1846 *
1847 * If this is the CPU link, use DSA or EDSA tagging depending
1848 * on which tagging mode was configured.
1849 *
1850 * If this is a link to another switch, use DSA tagging mode.
1851 *
1852 * If this is the upstream port for this switch, enable
1853 * forwarding of unknown unicasts and multicasts.
1854 */
a89b433b
VD		 1855 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1856 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1857 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1858 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 1859 if (err)
1860 return err;
6083ce71 1861
601aeed3 1862 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 1863 if (err)
1864 return err;
54d792f2 1865
601aeed3 1866 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 1867 if (err)
1868 return err;
1869
04aca993
AL		 1870 /* Enable the SERDES interface for DSA and CPU ports. Normal
1871 * ports SERDES are enabled when the port is enabled, thus
1872 * saving a bit of power.
13a7ebb3 1873 */
04aca993
AL		 1874 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1875 err = mv88e6xxx_serdes_power(chip, port, true);
1876 if (err)
1877 return err;
1878 }
13a7ebb3 1879
8efdda4a 1880 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 1881 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 1882 * untagged frames on this port, do a destination address lookup on all
1883 * received packets as usual, disable ARP mirroring and don't send a
1884 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 1885 */
a23b2961
AL		 1886 err = mv88e6xxx_port_set_map_da(chip, port);
1887 if (err)
1888 return err;
8efdda4a 1889
a23b2961
AL		 1890 reg = 0;
1891 if (chip->info->ops->port_set_upstream_port) {
1892 err = chip->info->ops->port_set_upstream_port(
1893 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 1894 if (err)
1895 return err;
54d792f2
AL		 1896 }
1897
a23b2961 1898 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 1899 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 1900 if (err)
1901 return err;
1902
cd782656
VD		 1903 if (chip->info->ops->port_set_jumbo_size) {
1904 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 1905 if (err)
1906 return err;
1907 }
1908
54d792f2
AL		 1909 /* Port Association Vector: when learning source addresses
1910 * of packets, add the address to the address database using
1911 * a port bitmap that has only the bit for this port set and
1912 * the other bits clear.
1913 */
4c7ea3c0 1914 reg = 1 << port;
996ecb82
VD		 1915 /* Disable learning for CPU port */
1916 if (dsa_is_cpu_port(ds, port))
65fa4027 1917 reg = 0;
4c7ea3c0 1918
2a4614e4
VD		 1919 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1920 reg);
0e7b9925
AL		 1921 if (err)
1922 return err;
54d792f2
AL		 1923
1924 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 1925 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1926 0x0000);
0e7b9925
AL		 1927 if (err)
1928 return err;
54d792f2 1929
0898432c
VD		 1930 if (chip->info->ops->port_pause_limit) {
1931 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 1932 if (err)
1933 return err;
b35d322a 1934 }
54d792f2 1935
c8c94891
VD		 1936 if (chip->info->ops->port_disable_learn_limit) {
1937 err = chip->info->ops->port_disable_learn_limit(chip, port);
1938 if (err)
1939 return err;
1940 }
1941
9dbfb4e1
VD		 1942 if (chip->info->ops->port_disable_pri_override) {
1943 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 1944 if (err)
1945 return err;
ef0a7318 1946 }
2bbb33be 1947
ef0a7318
AL		 1948 if (chip->info->ops->port_tag_remap) {
1949 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 1950 if (err)
1951 return err;
54d792f2
AL		 1952 }
1953
ef70b111
AL		 1954 if (chip->info->ops->port_egress_rate_limiting) {
1955 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 1956 if (err)
1957 return err;
54d792f2
AL		 1958 }
1959
ea698f4f 1960 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 1961 if (err)
1962 return err;
d827e88a 1963
207afda1 1964 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 1965 * database, and allow bidirectional communication between the
1966 * CPU and DSA port(s), and the other ports.
d827e88a 1967 */
b4e48c50 1968 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 1969 if (err)
1970 return err;
2db9ce1f 1971
240ea3ef 1972 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 1973 if (err)
1974 return err;
d827e88a
GR		 1975
1976 /* Default VLAN ID and priority: don't set a default VLAN
1977 * ID, and set the default packet priority to zero.
1978 */
b7929fb3 1979 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 1980}
1981
04aca993
AL		 1982static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1983 struct phy_device *phydev)
1984{
1985 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 1986 int err;
04aca993
AL		 1987
1988 mutex_lock(&chip->reg_lock);
523a8904 1989 err = mv88e6xxx_serdes_power(chip, port, true);
04aca993
AL		 1990 mutex_unlock(&chip->reg_lock);
1991
1992 return err;
1993}
1994
1995static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1996 struct phy_device *phydev)
1997{
1998 struct mv88e6xxx_chip *chip = ds->priv;
1999
2000 mutex_lock(&chip->reg_lock);
523a8904
VD		 2001 if (mv88e6xxx_serdes_power(chip, port, false))
2002 dev_err(chip->dev, "failed to power off SERDES\n");
04aca993
AL		 2003 mutex_unlock(&chip->reg_lock);
2004}
2005
2cfcd964
VD		 2006static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2007 unsigned int ageing_time)
2008{
04bed143 2009 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2010 int err;
2011
2012 mutex_lock(&chip->reg_lock);
720c6343 2013 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2014 mutex_unlock(&chip->reg_lock);
2015
2016 return err;
2017}
2018
9729934c 2019static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2020{
fad09c73 2021 struct dsa_switch *ds = chip->ds;
b0745e87 2022 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2023 int err;
54d792f2 2024
fa8d1179
VD		 2025 if (chip->info->ops->set_cpu_port) {
2026 err = chip->info->ops->set_cpu_port(chip, upstream_port);
33641994
AL		 2027 if (err)
2028 return err;
2029 }
2030
fa8d1179
VD		 2031 if (chip->info->ops->set_egress_port) {
2032 err = chip->info->ops->set_egress_port(chip, upstream_port);
33641994
AL		 2033 if (err)
2034 return err;
2035 }
b0745e87 2036
50484ff4 2037 /* Disable remote management, and set the switch's DSA device number. */
d77f4321
VD		 2038 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2039 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
a935c052 2040 (ds->index & 0x1f));
50484ff4
VD		 2041 if (err)
2042 return err;
2043
54d792f2 2044 /* Configure the IP ToS mapping registers. */
ccba8f3a 2045 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
48ace4ef 2046 if (err)
08a01261 2047 return err;
ccba8f3a 2048 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
48ace4ef 2049 if (err)
08a01261 2050 return err;
ccba8f3a 2051 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
48ace4ef 2052 if (err)
08a01261 2053 return err;
ccba8f3a 2054 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
48ace4ef 2055 if (err)
08a01261 2056 return err;
ccba8f3a 2057 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
48ace4ef 2058 if (err)
08a01261 2059 return err;
ccba8f3a 2060 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
48ace4ef 2061 if (err)
08a01261 2062 return err;
ccba8f3a 2063 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
48ace4ef 2064 if (err)
08a01261 2065 return err;
ccba8f3a 2066 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
48ace4ef 2067 if (err)
08a01261 2068 return err;
54d792f2
AL		 2069
2070 /* Configure the IEEE 802.1p priority mapping register. */
ccba8f3a 2071 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
48ace4ef 2072 if (err)
08a01261 2073 return err;
54d792f2 2074
de227387
AL		 2075 /* Initialize the statistics unit */
2076 err = mv88e6xxx_stats_set_histogram(chip);
2077 if (err)
2078 return err;
2079
9729934c 2080 /* Clear the statistics counters for all ports */
57d1ef38
VD		 2081 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
2082 MV88E6XXX_G1_STATS_OP_BUSY |
2083 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
9729934c
VD		 2084 if (err)
2085 return err;
2086
2087 /* Wait for the flush to complete. */
7f9ef3af 2088 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2089 if (err)
2090 return err;
2091
2092 return 0;
2093}
2094
f81ec90f 2095static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2096{
04bed143 2097 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2098 int err;
a1a6a4d1
VD		 2099 int i;
2100
fad09c73 2101 chip->ds = ds;
a3c53be5 2102 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2103
fad09c73 2104 mutex_lock(&chip->reg_lock);
08a01261 2105
9729934c 2106 /* Setup Switch Port Registers */
370b4ffb 2107 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2108 err = mv88e6xxx_setup_port(chip, i);
2109 if (err)
2110 goto unlock;
2111 }
2112
2113 /* Setup Switch Global 1 Registers */
2114 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2115 if (err)
2116 goto unlock;
2117
9729934c
VD		 2118 /* Setup Switch Global 2 Registers */
2119 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2120 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2121 if (err)
2122 goto unlock;
2123 }
08a01261 2124
cd8da8bb
VD		 2125 err = mv88e6xxx_irl_setup(chip);
2126 if (err)
2127 goto unlock;
2128
1b17aedf
VD		 2129 err = mv88e6xxx_phy_setup(chip);
2130 if (err)
2131 goto unlock;
2132
b486d7c9
VD		 2133 err = mv88e6xxx_vtu_setup(chip);
2134 if (err)
2135 goto unlock;
2136
81228996
VD		 2137 err = mv88e6xxx_pvt_setup(chip);
2138 if (err)
2139 goto unlock;
2140
a2ac29d2
VD		 2141 err = mv88e6xxx_atu_setup(chip);
2142 if (err)
2143 goto unlock;
2144
6e55f698
AL		 2145 /* Some generations have the configuration of sending reserved
2146 * management frames to the CPU in global2, others in
2147 * global1. Hence it does not fit the two setup functions
2148 * above.
2149 */
2150 if (chip->info->ops->mgmt_rsvd2cpu) {
2151 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2152 if (err)
2153 goto unlock;
2154 }
2155
6b17e864 2156unlock:
fad09c73 2157 mutex_unlock(&chip->reg_lock);
db687a56 2158
48ace4ef 2159 return err;
54d792f2
AL		 2160}
2161
3b4caa1b
VD		 2162static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2163{
04bed143 2164 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2165 int err;
2166
b073d4e2
VD		 2167 if (!chip->info->ops->set_switch_mac)
2168 return -EOPNOTSUPP;
3b4caa1b 2169
b073d4e2
VD		 2170 mutex_lock(&chip->reg_lock);
2171 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2172 mutex_unlock(&chip->reg_lock);
2173
2174 return err;
2175}
2176
e57e5e77 2177static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2178{
0dd12d54
AL		 2179 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2180 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2181 u16 val;
2182 int err;
fd3a0ee4 2183
ee26a228
AL		 2184 if (!chip->info->ops->phy_read)
2185 return -EOPNOTSUPP;
2186
fad09c73 2187 mutex_lock(&chip->reg_lock);
ee26a228 2188 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2189 mutex_unlock(&chip->reg_lock);
e57e5e77 2190
da9f3301
AL		 2191 if (reg == MII_PHYSID2) {
2192 /* Some internal PHYS don't have a model number. Use
2193 * the mv88e6390 family model number instead.
2194 */
2195 if (!(val & 0x3f0))
107fcc10 2196 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
da9f3301
AL		 2197 }
2198
e57e5e77 2199 return err ? err : val;
fd3a0ee4
AL		 2200}
2201
e57e5e77 2202static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2203{
0dd12d54
AL		 2204 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2205 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2206 int err;
fd3a0ee4 2207
ee26a228
AL		 2208 if (!chip->info->ops->phy_write)
2209 return -EOPNOTSUPP;
2210
fad09c73 2211 mutex_lock(&chip->reg_lock);
ee26a228 2212 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2213 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2214
2215 return err;
fd3a0ee4
AL		 2216}
2217
fad09c73 2218static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2219 struct device_node *np,
2220 bool external)
b516d453
AL		 2221{
2222 static int index;
0dd12d54 2223 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2224 struct mii_bus *bus;
2225 int err;
2226
0dd12d54 2227 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2228 if (!bus)
2229 return -ENOMEM;
2230
0dd12d54 2231 mdio_bus = bus->priv;
a3c53be5 2232 mdio_bus->bus = bus;
0dd12d54 2233 mdio_bus->chip = chip;
a3c53be5
AL		 2234 INIT_LIST_HEAD(&mdio_bus->list);
2235 mdio_bus->external = external;
0dd12d54 2236
b516d453
AL		 2237 if (np) {
2238 bus->name = np->full_name;
2239 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2240 } else {
2241 bus->name = "mv88e6xxx SMI";
2242 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2243 }
2244
2245 bus->read = mv88e6xxx_mdio_read;
2246 bus->write = mv88e6xxx_mdio_write;
fad09c73 2247 bus->parent = chip->dev;
b516d453 2248
a3c53be5
AL		 2249 if (np)
2250 err = of_mdiobus_register(bus, np);
b516d453
AL		 2251 else
2252 err = mdiobus_register(bus);
2253 if (err) {
fad09c73 2254 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2255 return err;
b516d453 2256 }
a3c53be5
AL		 2257
2258 if (external)
2259 list_add_tail(&mdio_bus->list, &chip->mdios);
2260 else
2261 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2262
2263 return 0;
a3c53be5 2264}
b516d453 2265
a3c53be5
AL		 2266static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2267 { .compatible = "marvell,mv88e6xxx-mdio-external",
2268 .data = (void *)true },
2269 { },
2270};
b516d453 2271
a3c53be5
AL		 2272static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2273 struct device_node *np)
2274{
2275 const struct of_device_id *match;
2276 struct device_node *child;
2277 int err;
2278
2279 /* Always register one mdio bus for the internal/default mdio
2280 * bus. This maybe represented in the device tree, but is
2281 * optional.
2282 */
2283 child = of_get_child_by_name(np, "mdio");
2284 err = mv88e6xxx_mdio_register(chip, child, false);
2285 if (err)
2286 return err;
2287
2288 /* Walk the device tree, and see if there are any other nodes
2289 * which say they are compatible with the external mdio
2290 * bus.
2291 */
2292 for_each_available_child_of_node(np, child) {
2293 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2294 if (match) {
2295 err = mv88e6xxx_mdio_register(chip, child, true);
2296 if (err)
2297 return err;
2298 }
2299 }
2300
2301 return 0;
b516d453
AL		 2302}
2303
a3c53be5 2304static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2305
2306{
a3c53be5
AL		 2307 struct mv88e6xxx_mdio_bus *mdio_bus;
2308 struct mii_bus *bus;
b516d453 2309
a3c53be5
AL		 2310 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2311 bus = mdio_bus->bus;
b516d453 2312
a3c53be5
AL		 2313 mdiobus_unregister(bus);
2314 }
b516d453
AL		 2315}
2316
855b1932
VD		 2317static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2318{
04bed143 2319 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2320
2321 return chip->eeprom_len;
2322}
2323
855b1932
VD		 2324static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2325 struct ethtool_eeprom *eeprom, u8 *data)
2326{
04bed143 2327 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2328 int err;
2329
ee4dc2e7
VD		 2330 if (!chip->info->ops->get_eeprom)
2331 return -EOPNOTSUPP;
855b1932 2332
ee4dc2e7
VD		 2333 mutex_lock(&chip->reg_lock);
2334 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2335 mutex_unlock(&chip->reg_lock);
2336
2337 if (err)
2338 return err;
2339
2340 eeprom->magic = 0xc3ec4951;
2341
2342 return 0;
2343}
2344
855b1932
VD		 2345static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2346 struct ethtool_eeprom *eeprom, u8 *data)
2347{
04bed143 2348 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2349 int err;
2350
ee4dc2e7
VD		 2351 if (!chip->info->ops->set_eeprom)
2352 return -EOPNOTSUPP;
2353
855b1932
VD		 2354 if (eeprom->magic != 0xc3ec4951)
2355 return -EINVAL;
2356
2357 mutex_lock(&chip->reg_lock);
ee4dc2e7 2358 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2359 mutex_unlock(&chip->reg_lock);
2360
2361 return err;
2362}
2363
b3469dd8 2364static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2365 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2366 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2367 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2368 .phy_read = mv88e6185_phy_ppu_read,
2369 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2370 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2371 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2372 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2373 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2374 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2375 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2376 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2377 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2378 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2379 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2380 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2381 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2382 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2383 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2384 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2385 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2386 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2387 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2388 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2389 .ppu_enable = mv88e6185_g1_ppu_enable,
2390 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2391 .reset = mv88e6185_g1_reset,
f1394b78 2392 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2393 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2394};
2395
2396static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2397 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2398 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2399 .phy_read = mv88e6185_phy_ppu_read,
2400 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2401 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2402 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2403 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2404 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2405 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2406 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2407 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2408 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2409 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2410 .stats_get_stats = mv88e6095_stats_get_stats,
6e55f698 2411 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2412 .ppu_enable = mv88e6185_g1_ppu_enable,
2413 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2414 .reset = mv88e6185_g1_reset,
f1394b78 2415 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2416 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2417};
2418
7d381a02 2419static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2420 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2421 .irl_init_all = mv88e6352_g2_irl_init_all,
7d381a02
SE		 2422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2423 .phy_read = mv88e6xxx_g2_smi_phy_read,
2424 .phy_write = mv88e6xxx_g2_smi_phy_write,
2425 .port_set_link = mv88e6xxx_port_set_link,
2426 .port_set_duplex = mv88e6xxx_port_set_duplex,
2427 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2428 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2429 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2430 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2431 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2432 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2433 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 2434 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2435 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2436 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2437 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2438 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2439 .stats_get_strings = mv88e6095_stats_get_strings,
2440 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2441 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2442 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2443 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2444 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2445 .reset = mv88e6352_g1_reset,
f1394b78 2446 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2447 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
7d381a02
SE		 2448};
2449
b3469dd8 2450static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2451 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2452 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2453 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2454 .phy_read = mv88e6xxx_g2_smi_phy_read,
2455 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2456 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2457 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2458 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2459 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2460 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2463 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2464 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2465 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2466 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2467 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2468 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2469 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2470 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2471 .reset = mv88e6352_g1_reset,
f1394b78 2472 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2473 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2474};
2475
2476static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2477 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2478 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2479 .phy_read = mv88e6185_phy_ppu_read,
2480 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2481 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2482 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2483 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2484 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2485 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2486 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2487 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2488 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 2489 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2490 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2491 .port_pause_limit = mv88e6097_port_pause_limit,
a605a0fe 2492 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2493 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2494 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2495 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2496 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2497 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2498 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2499 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2500 .ppu_enable = mv88e6185_g1_ppu_enable,
2501 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2502 .reset = mv88e6185_g1_reset,
f1394b78 2503 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2504 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2505};
2506
990e27b0
VD		 2507static const struct mv88e6xxx_ops mv88e6141_ops = {
2508 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 2509 .irl_init_all = mv88e6352_g2_irl_init_all,
990e27b0
VD		 2510 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2511 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2512 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2513 .phy_read = mv88e6xxx_g2_smi_phy_read,
2514 .phy_write = mv88e6xxx_g2_smi_phy_write,
2515 .port_set_link = mv88e6xxx_port_set_link,
2516 .port_set_duplex = mv88e6xxx_port_set_duplex,
2517 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2518 .port_set_speed = mv88e6390_port_set_speed,
2519 .port_tag_remap = mv88e6095_port_tag_remap,
2520 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2521 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2522 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2523 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 2524 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2525 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 2526 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2527 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2528 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2529 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2530 .stats_get_strings = mv88e6320_stats_get_strings,
2531 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2532 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2533 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 2534 .watchdog_ops = &mv88e6390_watchdog_ops,
2535 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2536 .reset = mv88e6352_g1_reset,
f1394b78 2537 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2538 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
990e27b0
VD		 2539};
2540
b3469dd8 2541static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2542 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2543 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2544 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2545 .phy_read = mv88e6xxx_g2_smi_phy_read,
2546 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2547 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2548 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2549 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2550 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2551 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2552 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2553 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2554 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2555 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2556 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2557 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2558 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2559 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2560 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2561 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2562 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2563 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2564 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2565 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2566 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2567 .reset = mv88e6352_g1_reset,
f1394b78 2568 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2569 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2570};
2571
2572static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2573 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2574 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2576 .phy_read = mv88e6165_phy_read,
2577 .phy_write = mv88e6165_phy_write,
08ef7f10 2578 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2579 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2580 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 2581 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2582 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2583 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2584 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2585 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2586 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2587 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2588 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2589 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2590 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2591 .reset = mv88e6352_g1_reset,
f1394b78 2592 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2593 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2594};
2595
2596static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2597 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2598 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2599 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2600 .phy_read = mv88e6xxx_g2_smi_phy_read,
2601 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2602 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2603 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2604 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2605 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2606 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2607 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2608 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2609 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2610 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2611 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2612 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2613 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2614 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2615 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2616 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2617 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2618 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2619 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2620 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2621 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2622 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2623 .reset = mv88e6352_g1_reset,
f1394b78 2624 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2625 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2626};
2627
2628static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 2629 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2630 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2631 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2632 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2634 .phy_read = mv88e6xxx_g2_smi_phy_read,
2635 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2636 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2637 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2638 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2639 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2640 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2641 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2642 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2643 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2644 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2645 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2646 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2647 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2648 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2649 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2650 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2651 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2652 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2653 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2654 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2655 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2656 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2657 .reset = mv88e6352_g1_reset,
f1394b78 2658 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2660 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2661};
2662
2663static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 2664 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2665 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2666 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2667 .phy_read = mv88e6xxx_g2_smi_phy_read,
2668 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2669 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2670 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2671 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2672 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2673 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2674 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2675 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2676 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2677 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2678 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2679 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2680 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2681 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2682 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2683 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2684 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2685 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2686 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2687 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2688 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2689 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2690 .reset = mv88e6352_g1_reset,
f1394b78 2691 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2693};
2694
2695static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 2696 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2697 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2698 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2699 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2700 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2701 .phy_read = mv88e6xxx_g2_smi_phy_read,
2702 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2703 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2704 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2705 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2706 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2707 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2708 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2709 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2710 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2711 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2712 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2713 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2714 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2715 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2716 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2717 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2718 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2719 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2720 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2721 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2722 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2723 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2724 .reset = mv88e6352_g1_reset,
f1394b78 2725 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2726 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2727 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2728};
2729
2730static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 2731 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2732 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2733 .phy_read = mv88e6185_phy_ppu_read,
2734 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2735 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2736 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2737 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2738 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2739 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 2740 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 2741 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2742 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2743 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2744 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2745 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2746 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2747 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2748 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2749 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2750 .ppu_enable = mv88e6185_g1_ppu_enable,
2751 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2752 .reset = mv88e6185_g1_reset,
f1394b78 2753 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2754 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2755};
2756
1a3b39ec 2757static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 2758 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2759 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2760 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2761 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2762 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2763 .phy_read = mv88e6xxx_g2_smi_phy_read,
2764 .phy_write = mv88e6xxx_g2_smi_phy_write,
2765 .port_set_link = mv88e6xxx_port_set_link,
2766 .port_set_duplex = mv88e6xxx_port_set_duplex,
2767 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2768 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2769 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2770 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2771 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2772 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2773 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2774 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2775 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2776 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2777 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2778 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2779 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2780 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2781 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2782 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2783 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2784 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2785 .reset = mv88e6352_g1_reset,
931d1822
VD		 2786 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2787 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2788 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2789};
2790
2791static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 2792 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2793 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2794 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2795 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2796 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2797 .phy_read = mv88e6xxx_g2_smi_phy_read,
2798 .phy_write = mv88e6xxx_g2_smi_phy_write,
2799 .port_set_link = mv88e6xxx_port_set_link,
2800 .port_set_duplex = mv88e6xxx_port_set_duplex,
2801 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2802 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 2803 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2804 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2805 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2806 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2807 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2808 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2809 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2810 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2811 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2812 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2813 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2814 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2815 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2816 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2817 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2818 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2819 .reset = mv88e6352_g1_reset,
931d1822
VD		 2820 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2821 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2822 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2823};
2824
2825static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 2826 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2827 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2828 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2829 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2830 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2831 .phy_read = mv88e6xxx_g2_smi_phy_read,
2832 .phy_write = mv88e6xxx_g2_smi_phy_write,
2833 .port_set_link = mv88e6xxx_port_set_link,
2834 .port_set_duplex = mv88e6xxx_port_set_duplex,
2835 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2836 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2837 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2838 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2839 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2840 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2841 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2842 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2843 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2844 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2845 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2846 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2847 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2848 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2849 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2850 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2851 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2852 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2853 .reset = mv88e6352_g1_reset,
931d1822
VD		 2854 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2855 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2856 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2857};
2858
b3469dd8 2859static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 2860 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2861 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2862 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2863 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2864 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2865 .phy_read = mv88e6xxx_g2_smi_phy_read,
2866 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2867 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2868 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2869 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2870 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2871 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2872 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2873 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2874 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2875 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2876 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2877 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2878 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2879 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2880 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2881 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2882 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2883 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2884 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2885 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2886 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 2887 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2888 .reset = mv88e6352_g1_reset,
f1394b78 2889 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2890 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2891 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2892};
2893
1a3b39ec 2894static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 2895 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2896 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2897 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2898 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2899 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2900 .phy_read = mv88e6xxx_g2_smi_phy_read,
2901 .phy_write = mv88e6xxx_g2_smi_phy_write,
2902 .port_set_link = mv88e6xxx_port_set_link,
2903 .port_set_duplex = mv88e6xxx_port_set_duplex,
2904 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2905 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2906 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2907 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2908 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2909 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2910 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 2911 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 2912 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2913 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2914 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2915 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2916 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2917 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2918 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2919 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2920 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2921 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2922 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 2923 .reset = mv88e6352_g1_reset,
931d1822
VD		 2924 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2925 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2926 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2927};
2928
b3469dd8 2929static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 2930 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 2931 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2932 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2933 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2934 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2935 .phy_read = mv88e6xxx_g2_smi_phy_read,
2936 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2937 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2938 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2939 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2940 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2941 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2942 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2943 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2944 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2945 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2946 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2947 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2948 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2949 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2950 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2951 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2952 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2953 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2954 .set_egress_port = mv88e6095_g1_set_egress_port,
6e55f698 2955 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 2956 .reset = mv88e6352_g1_reset,
f1394b78 2957 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2958 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2959};
2960
2961static const struct mv88e6xxx_ops mv88e6321_ops = {
4b325d8c 2962 /* MV88E6XXX_FAMILY_6321 */
cd8da8bb 2963 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2964 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2965 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2966 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2967 .phy_read = mv88e6xxx_g2_smi_phy_read,
2968 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2969 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2970 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2971 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2972 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2973 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2974 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2975 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2976 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2977 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2978 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2979 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2980 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2981 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2982 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2983 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2984 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2985 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2986 .set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 2987 .reset = mv88e6352_g1_reset,
f1394b78 2988 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2989 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2990};
2991
16e329ae
VD		 2992static const struct mv88e6xxx_ops mv88e6341_ops = {
2993 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 2994 .irl_init_all = mv88e6352_g2_irl_init_all,
16e329ae
VD		 2995 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2996 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2997 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2998 .phy_read = mv88e6xxx_g2_smi_phy_read,
2999 .phy_write = mv88e6xxx_g2_smi_phy_write,
3000 .port_set_link = mv88e6xxx_port_set_link,
3001 .port_set_duplex = mv88e6xxx_port_set_duplex,
3002 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3003 .port_set_speed = mv88e6390_port_set_speed,
3004 .port_tag_remap = mv88e6095_port_tag_remap,
3005 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3006 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3007 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3008 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 3009 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3010 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 3011 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3012 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3013 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3014 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3015 .stats_get_strings = mv88e6320_stats_get_strings,
3016 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3017 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3018 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 3019 .watchdog_ops = &mv88e6390_watchdog_ops,
3020 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3021 .reset = mv88e6352_g1_reset,
f1394b78 3022 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3023 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
16e329ae
VD		 3024};
3025
b3469dd8 3026static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3027 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3028 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3030 .phy_read = mv88e6xxx_g2_smi_phy_read,
3031 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3032 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3033 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3034 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3035 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3036 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3037 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3038 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3039 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3040 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3041 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3042 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3043 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3044 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3045 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3046 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3047 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3048 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3049 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3050 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3051 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3052 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3053 .reset = mv88e6352_g1_reset,
f1394b78 3054 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3055 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3056};
3057
3058static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3059 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3060 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3061 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3062 .phy_read = mv88e6xxx_g2_smi_phy_read,
3063 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3064 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3065 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3066 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3067 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3068 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3069 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3070 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3071 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3072 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3073 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3074 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3075 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3076 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3077 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3078 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3079 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3080 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3081 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3082 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3083 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3084 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3085 .reset = mv88e6352_g1_reset,
f1394b78 3086 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3087 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3088};
3089
3090static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3091 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 3092 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3093 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3094 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3095 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3096 .phy_read = mv88e6xxx_g2_smi_phy_read,
3097 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3098 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3099 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3100 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3101 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3102 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3103 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3104 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3105 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3106 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3107 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3108 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3109 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3110 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3111 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3112 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3113 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3114 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3115 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3116 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3117 .watchdog_ops = &mv88e6097_watchdog_ops,
6e55f698 3118 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
17e708ba 3119 .reset = mv88e6352_g1_reset,
f1394b78 3120 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3121 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 3122 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 3123};
3124
1a3b39ec 3125static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3126 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 3127 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3128 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3129 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3130 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3131 .phy_read = mv88e6xxx_g2_smi_phy_read,
3132 .phy_write = mv88e6xxx_g2_smi_phy_write,
3133 .port_set_link = mv88e6xxx_port_set_link,
3134 .port_set_duplex = mv88e6xxx_port_set_duplex,
3135 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3136 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3137 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3138 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3139 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3140 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3141 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3142 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3143 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 3144 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3145 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3146 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3147 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3148 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3149 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3150 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3151 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3152 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3153 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3154 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3155 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3156 .reset = mv88e6352_g1_reset,
931d1822
VD		 3157 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3158 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3159 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3160};
3161
3162static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3163 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 3164 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3165 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3166 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3167 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3168 .phy_read = mv88e6xxx_g2_smi_phy_read,
3169 .phy_write = mv88e6xxx_g2_smi_phy_write,
3170 .port_set_link = mv88e6xxx_port_set_link,
3171 .port_set_duplex = mv88e6xxx_port_set_duplex,
3172 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3173 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3174 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3175 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3176 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3177 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3178 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3179 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3180 .port_pause_limit = mv88e6390_port_pause_limit,
bb0a2675 3181 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3182 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3183 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3184 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3185 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3186 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3187 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3188 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3189 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3190 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3191 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3192 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
17e708ba 3193 .reset = mv88e6352_g1_reset,
931d1822
VD		 3194 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3195 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3196 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3197};
3198
f81ec90f
VD		 3199static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3200 [MV88E6085] = {
107fcc10 3201 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 3202 .family = MV88E6XXX_FAMILY_6097,
3203 .name = "Marvell 88E6085",
3204 .num_databases = 4096,
3205 .num_ports = 10,
3cf3c846 3206 .max_vid = 4095,
9dddd478 3207 .port_base_addr = 0x10,
a935c052 3208 .global1_addr = 0x1b,
acddbd21 3209 .age_time_coeff = 15000,
dc30c35b 3210 .g1_irqs = 8,
e606ca36 3211 .atu_move_port_mask = 0xf,
f3645652 3212 .pvt = true,
443d5a1b 3213 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3214 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3215 .ops = &mv88e6085_ops,
f81ec90f
VD		 3216 },
3217
3218 [MV88E6095] = {
107fcc10 3219 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 3220 .family = MV88E6XXX_FAMILY_6095,
3221 .name = "Marvell 88E6095/88E6095F",
3222 .num_databases = 256,
3223 .num_ports = 11,
3cf3c846 3224 .max_vid = 4095,
9dddd478 3225 .port_base_addr = 0x10,
a935c052 3226 .global1_addr = 0x1b,
acddbd21 3227 .age_time_coeff = 15000,
dc30c35b 3228 .g1_irqs = 8,
e606ca36 3229 .atu_move_port_mask = 0xf,
443d5a1b 3230 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3231 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3232 .ops = &mv88e6095_ops,
f81ec90f
VD		 3233 },
3234
7d381a02 3235 [MV88E6097] = {
107fcc10 3236 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 3237 .family = MV88E6XXX_FAMILY_6097,
3238 .name = "Marvell 88E6097/88E6097F",
3239 .num_databases = 4096,
3240 .num_ports = 11,
3cf3c846 3241 .max_vid = 4095,
7d381a02
SE		 3242 .port_base_addr = 0x10,
3243 .global1_addr = 0x1b,
3244 .age_time_coeff = 15000,
c534178b 3245 .g1_irqs = 8,
e606ca36 3246 .atu_move_port_mask = 0xf,
f3645652 3247 .pvt = true,
2bfcfcd3 3248 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3249 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3250 .ops = &mv88e6097_ops,
3251 },
3252
f81ec90f 3253 [MV88E6123] = {
107fcc10 3254 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 3255 .family = MV88E6XXX_FAMILY_6165,
3256 .name = "Marvell 88E6123",
3257 .num_databases = 4096,
3258 .num_ports = 3,
3cf3c846 3259 .max_vid = 4095,
9dddd478 3260 .port_base_addr = 0x10,
a935c052 3261 .global1_addr = 0x1b,
acddbd21 3262 .age_time_coeff = 15000,
dc30c35b 3263 .g1_irqs = 9,
e606ca36 3264 .atu_move_port_mask = 0xf,
f3645652 3265 .pvt = true,
5ebe31d7 3266 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3267 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3268 .ops = &mv88e6123_ops,
f81ec90f
VD		 3269 },
3270
3271 [MV88E6131] = {
107fcc10 3272 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 3273 .family = MV88E6XXX_FAMILY_6185,
3274 .name = "Marvell 88E6131",
3275 .num_databases = 256,
3276 .num_ports = 8,
3cf3c846 3277 .max_vid = 4095,
9dddd478 3278 .port_base_addr = 0x10,
a935c052 3279 .global1_addr = 0x1b,
acddbd21 3280 .age_time_coeff = 15000,
dc30c35b 3281 .g1_irqs = 9,
e606ca36 3282 .atu_move_port_mask = 0xf,
443d5a1b 3283 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3284 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3285 .ops = &mv88e6131_ops,
f81ec90f
VD		 3286 },
3287
990e27b0 3288 [MV88E6141] = {
107fcc10 3289 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0
VD		 3290 .family = MV88E6XXX_FAMILY_6341,
3291 .name = "Marvell 88E6341",
3292 .num_databases = 4096,
3293 .num_ports = 6,
3cf3c846 3294 .max_vid = 4095,
990e27b0
VD		 3295 .port_base_addr = 0x10,
3296 .global1_addr = 0x1b,
3297 .age_time_coeff = 3750,
3298 .atu_move_port_mask = 0x1f,
f3645652 3299 .pvt = true,
990e27b0
VD		 3300 .tag_protocol = DSA_TAG_PROTO_EDSA,
3301 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3302 .ops = &mv88e6141_ops,
3303 },
3304
f81ec90f 3305 [MV88E6161] = {
107fcc10 3306 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 3307 .family = MV88E6XXX_FAMILY_6165,
3308 .name = "Marvell 88E6161",
3309 .num_databases = 4096,
3310 .num_ports = 6,
3cf3c846 3311 .max_vid = 4095,
9dddd478 3312 .port_base_addr = 0x10,
a935c052 3313 .global1_addr = 0x1b,
acddbd21 3314 .age_time_coeff = 15000,
dc30c35b 3315 .g1_irqs = 9,
e606ca36 3316 .atu_move_port_mask = 0xf,
f3645652 3317 .pvt = true,
5ebe31d7 3318 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3319 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3320 .ops = &mv88e6161_ops,
f81ec90f
VD		 3321 },
3322
3323 [MV88E6165] = {
107fcc10 3324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 3325 .family = MV88E6XXX_FAMILY_6165,
3326 .name = "Marvell 88E6165",
3327 .num_databases = 4096,
3328 .num_ports = 6,
3cf3c846 3329 .max_vid = 4095,
9dddd478 3330 .port_base_addr = 0x10,
a935c052 3331 .global1_addr = 0x1b,
acddbd21 3332 .age_time_coeff = 15000,
dc30c35b 3333 .g1_irqs = 9,
e606ca36 3334 .atu_move_port_mask = 0xf,
f3645652 3335 .pvt = true,
443d5a1b 3336 .tag_protocol = DSA_TAG_PROTO_DSA,
f81ec90f 3337 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3338 .ops = &mv88e6165_ops,
f81ec90f
VD		 3339 },
3340
3341 [MV88E6171] = {
107fcc10 3342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 3343 .family = MV88E6XXX_FAMILY_6351,
3344 .name = "Marvell 88E6171",
3345 .num_databases = 4096,
3346 .num_ports = 7,
3cf3c846 3347 .max_vid = 4095,
9dddd478 3348 .port_base_addr = 0x10,
a935c052 3349 .global1_addr = 0x1b,
acddbd21 3350 .age_time_coeff = 15000,
dc30c35b 3351 .g1_irqs = 9,
e606ca36 3352 .atu_move_port_mask = 0xf,
f3645652 3353 .pvt = true,
443d5a1b 3354 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3355 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3356 .ops = &mv88e6171_ops,
f81ec90f
VD		 3357 },
3358
3359 [MV88E6172] = {
107fcc10 3360 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 3361 .family = MV88E6XXX_FAMILY_6352,
3362 .name = "Marvell 88E6172",
3363 .num_databases = 4096,
3364 .num_ports = 7,
3cf3c846 3365 .max_vid = 4095,
9dddd478 3366 .port_base_addr = 0x10,
a935c052 3367 .global1_addr = 0x1b,
acddbd21 3368 .age_time_coeff = 15000,
dc30c35b 3369 .g1_irqs = 9,
e606ca36 3370 .atu_move_port_mask = 0xf,
f3645652 3371 .pvt = true,
443d5a1b 3372 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3373 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3374 .ops = &mv88e6172_ops,
f81ec90f
VD		 3375 },
3376
3377 [MV88E6175] = {
107fcc10 3378 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 3379 .family = MV88E6XXX_FAMILY_6351,
3380 .name = "Marvell 88E6175",
3381 .num_databases = 4096,
3382 .num_ports = 7,
3cf3c846 3383 .max_vid = 4095,
9dddd478 3384 .port_base_addr = 0x10,
a935c052 3385 .global1_addr = 0x1b,
acddbd21 3386 .age_time_coeff = 15000,
dc30c35b 3387 .g1_irqs = 9,
e606ca36 3388 .atu_move_port_mask = 0xf,
f3645652 3389 .pvt = true,
443d5a1b 3390 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3391 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3392 .ops = &mv88e6175_ops,
f81ec90f
VD		 3393 },
3394
3395 [MV88E6176] = {
107fcc10 3396 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 3397 .family = MV88E6XXX_FAMILY_6352,
3398 .name = "Marvell 88E6176",
3399 .num_databases = 4096,
3400 .num_ports = 7,
3cf3c846 3401 .max_vid = 4095,
9dddd478 3402 .port_base_addr = 0x10,
a935c052 3403 .global1_addr = 0x1b,
acddbd21 3404 .age_time_coeff = 15000,
dc30c35b 3405 .g1_irqs = 9,
e606ca36 3406 .atu_move_port_mask = 0xf,
f3645652 3407 .pvt = true,
443d5a1b 3408 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3409 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3410 .ops = &mv88e6176_ops,
f81ec90f
VD		 3411 },
3412
3413 [MV88E6185] = {
107fcc10 3414 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 3415 .family = MV88E6XXX_FAMILY_6185,
3416 .name = "Marvell 88E6185",
3417 .num_databases = 256,
3418 .num_ports = 10,
3cf3c846 3419 .max_vid = 4095,
9dddd478 3420 .port_base_addr = 0x10,
a935c052 3421 .global1_addr = 0x1b,
acddbd21 3422 .age_time_coeff = 15000,
dc30c35b 3423 .g1_irqs = 8,
e606ca36 3424 .atu_move_port_mask = 0xf,
443d5a1b 3425 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3426 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3427 .ops = &mv88e6185_ops,
f81ec90f
VD		 3428 },
3429
1a3b39ec 3430 [MV88E6190] = {
107fcc10 3431 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 3432 .family = MV88E6XXX_FAMILY_6390,
3433 .name = "Marvell 88E6190",
3434 .num_databases = 4096,
3435 .num_ports = 11, /* 10 + Z80 */
931d1822 3436 .max_vid = 8191,
1a3b39ec
AL		 3437 .port_base_addr = 0x0,
3438 .global1_addr = 0x1b,
443d5a1b 3439 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3440 .age_time_coeff = 3750,
1a3b39ec 3441 .g1_irqs = 9,
f3645652 3442 .pvt = true,
e606ca36 3443 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3444 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3445 .ops = &mv88e6190_ops,
3446 },
3447
3448 [MV88E6190X] = {
107fcc10 3449 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 3450 .family = MV88E6XXX_FAMILY_6390,
3451 .name = "Marvell 88E6190X",
3452 .num_databases = 4096,
3453 .num_ports = 11, /* 10 + Z80 */
931d1822 3454 .max_vid = 8191,
1a3b39ec
AL		 3455 .port_base_addr = 0x0,
3456 .global1_addr = 0x1b,
b91e055c 3457 .age_time_coeff = 3750,
1a3b39ec 3458 .g1_irqs = 9,
e606ca36 3459 .atu_move_port_mask = 0x1f,
f3645652 3460 .pvt = true,
443d5a1b 3461 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3462 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3463 .ops = &mv88e6190x_ops,
3464 },
3465
3466 [MV88E6191] = {
107fcc10 3467 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 3468 .family = MV88E6XXX_FAMILY_6390,
3469 .name = "Marvell 88E6191",
3470 .num_databases = 4096,
3471 .num_ports = 11, /* 10 + Z80 */
931d1822 3472 .max_vid = 8191,
1a3b39ec
AL		 3473 .port_base_addr = 0x0,
3474 .global1_addr = 0x1b,
b91e055c 3475 .age_time_coeff = 3750,
443d5a1b 3476 .g1_irqs = 9,
e606ca36 3477 .atu_move_port_mask = 0x1f,
f3645652 3478 .pvt = true,
443d5a1b 3479 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec 3480 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
2cf4cefb 3481 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3482 },
3483
f81ec90f 3484 [MV88E6240] = {
107fcc10 3485 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 3486 .family = MV88E6XXX_FAMILY_6352,
3487 .name = "Marvell 88E6240",
3488 .num_databases = 4096,
3489 .num_ports = 7,
3cf3c846 3490 .max_vid = 4095,
9dddd478 3491 .port_base_addr = 0x10,
a935c052 3492 .global1_addr = 0x1b,
acddbd21 3493 .age_time_coeff = 15000,
dc30c35b 3494 .g1_irqs = 9,
e606ca36 3495 .atu_move_port_mask = 0xf,
f3645652 3496 .pvt = true,
443d5a1b 3497 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3498 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3499 .ops = &mv88e6240_ops,
f81ec90f
VD		 3500 },
3501
1a3b39ec 3502 [MV88E6290] = {
107fcc10 3503 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 3504 .family = MV88E6XXX_FAMILY_6390,
3505 .name = "Marvell 88E6290",
3506 .num_databases = 4096,
3507 .num_ports = 11, /* 10 + Z80 */
931d1822 3508 .max_vid = 8191,
1a3b39ec
AL		 3509 .port_base_addr = 0x0,
3510 .global1_addr = 0x1b,
b91e055c 3511 .age_time_coeff = 3750,
1a3b39ec 3512 .g1_irqs = 9,
e606ca36 3513 .atu_move_port_mask = 0x1f,
f3645652 3514 .pvt = true,
443d5a1b 3515 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3516 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3517 .ops = &mv88e6290_ops,
3518 },
3519
f81ec90f 3520 [MV88E6320] = {
107fcc10 3521 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 3522 .family = MV88E6XXX_FAMILY_6320,
3523 .name = "Marvell 88E6320",
3524 .num_databases = 4096,
3525 .num_ports = 7,
3cf3c846 3526 .max_vid = 4095,
9dddd478 3527 .port_base_addr = 0x10,
a935c052 3528 .global1_addr = 0x1b,
acddbd21 3529 .age_time_coeff = 15000,
dc30c35b 3530 .g1_irqs = 8,
e606ca36 3531 .atu_move_port_mask = 0xf,
f3645652 3532 .pvt = true,
443d5a1b 3533 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3534 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3535 .ops = &mv88e6320_ops,
f81ec90f
VD		 3536 },
3537
3538 [MV88E6321] = {
107fcc10 3539 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 3540 .family = MV88E6XXX_FAMILY_6320,
3541 .name = "Marvell 88E6321",
3542 .num_databases = 4096,
3543 .num_ports = 7,
3cf3c846 3544 .max_vid = 4095,
9dddd478 3545 .port_base_addr = 0x10,
a935c052 3546 .global1_addr = 0x1b,
acddbd21 3547 .age_time_coeff = 15000,
dc30c35b 3548 .g1_irqs = 8,
e606ca36 3549 .atu_move_port_mask = 0xf,
443d5a1b 3550 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3551 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3552 .ops = &mv88e6321_ops,
f81ec90f
VD		 3553 },
3554
a75961d0 3555 [MV88E6341] = {
107fcc10 3556 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 3557 .family = MV88E6XXX_FAMILY_6341,
3558 .name = "Marvell 88E6341",
3559 .num_databases = 4096,
3560 .num_ports = 6,
3cf3c846 3561 .max_vid = 4095,
a75961d0
GC		 3562 .port_base_addr = 0x10,
3563 .global1_addr = 0x1b,
3564 .age_time_coeff = 3750,
e606ca36 3565 .atu_move_port_mask = 0x1f,
f3645652 3566 .pvt = true,
a75961d0
GC		 3567 .tag_protocol = DSA_TAG_PROTO_EDSA,
3568 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3569 .ops = &mv88e6341_ops,
3570 },
3571
f81ec90f 3572 [MV88E6350] = {
107fcc10 3573 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 3574 .family = MV88E6XXX_FAMILY_6351,
3575 .name = "Marvell 88E6350",
3576 .num_databases = 4096,
3577 .num_ports = 7,
3cf3c846 3578 .max_vid = 4095,
9dddd478 3579 .port_base_addr = 0x10,
a935c052 3580 .global1_addr = 0x1b,
acddbd21 3581 .age_time_coeff = 15000,
dc30c35b 3582 .g1_irqs = 9,
e606ca36 3583 .atu_move_port_mask = 0xf,
f3645652 3584 .pvt = true,
443d5a1b 3585 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3586 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3587 .ops = &mv88e6350_ops,
f81ec90f
VD		 3588 },
3589
3590 [MV88E6351] = {
107fcc10 3591 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 3592 .family = MV88E6XXX_FAMILY_6351,
3593 .name = "Marvell 88E6351",
3594 .num_databases = 4096,
3595 .num_ports = 7,
3cf3c846 3596 .max_vid = 4095,
9dddd478 3597 .port_base_addr = 0x10,
a935c052 3598 .global1_addr = 0x1b,
acddbd21 3599 .age_time_coeff = 15000,
dc30c35b 3600 .g1_irqs = 9,
e606ca36 3601 .atu_move_port_mask = 0xf,
f3645652 3602 .pvt = true,
443d5a1b 3603 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3604 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3605 .ops = &mv88e6351_ops,
f81ec90f
VD		 3606 },
3607
3608 [MV88E6352] = {
107fcc10 3609 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 3610 .family = MV88E6XXX_FAMILY_6352,
3611 .name = "Marvell 88E6352",
3612 .num_databases = 4096,
3613 .num_ports = 7,
3cf3c846 3614 .max_vid = 4095,
9dddd478 3615 .port_base_addr = 0x10,
a935c052 3616 .global1_addr = 0x1b,
acddbd21 3617 .age_time_coeff = 15000,
dc30c35b 3618 .g1_irqs = 9,
e606ca36 3619 .atu_move_port_mask = 0xf,
f3645652 3620 .pvt = true,
443d5a1b 3621 .tag_protocol = DSA_TAG_PROTO_EDSA,
f81ec90f 3622 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3623 .ops = &mv88e6352_ops,
f81ec90f 3624 },
1a3b39ec 3625 [MV88E6390] = {
107fcc10 3626 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 3627 .family = MV88E6XXX_FAMILY_6390,
3628 .name = "Marvell 88E6390",
3629 .num_databases = 4096,
3630 .num_ports = 11, /* 10 + Z80 */
931d1822 3631 .max_vid = 8191,
1a3b39ec
AL		 3632 .port_base_addr = 0x0,
3633 .global1_addr = 0x1b,
b91e055c 3634 .age_time_coeff = 3750,
1a3b39ec 3635 .g1_irqs = 9,
e606ca36 3636 .atu_move_port_mask = 0x1f,
f3645652 3637 .pvt = true,
443d5a1b 3638 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3639 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3640 .ops = &mv88e6390_ops,
3641 },
3642 [MV88E6390X] = {
107fcc10 3643 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 3644 .family = MV88E6XXX_FAMILY_6390,
3645 .name = "Marvell 88E6390X",
3646 .num_databases = 4096,
3647 .num_ports = 11, /* 10 + Z80 */
931d1822 3648 .max_vid = 8191,
1a3b39ec
AL		 3649 .port_base_addr = 0x0,
3650 .global1_addr = 0x1b,
b91e055c 3651 .age_time_coeff = 3750,
1a3b39ec 3652 .g1_irqs = 9,
e606ca36 3653 .atu_move_port_mask = 0x1f,
f3645652 3654 .pvt = true,
443d5a1b 3655 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3656 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3657 .ops = &mv88e6390x_ops,
3658 },
f81ec90f
VD		 3659};
3660
5f7c0367 3661static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3662{
a439c061 3663 int i;
b9b37713 3664
5f7c0367
VD		 3665 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3666 if (mv88e6xxx_table[i].prod_num == prod_num)
3667 return &mv88e6xxx_table[i];
b9b37713 3668
b9b37713
VD		 3669 return NULL;
3670}
3671
fad09c73 3672static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3673{
3674 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3675 unsigned int prod_num, rev;
3676 u16 id;
3677 int err;
bc46a3d5 3678
8f6345b2 3679 mutex_lock(&chip->reg_lock);
107fcc10 3680 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
8f6345b2
VD		 3681 mutex_unlock(&chip->reg_lock);
3682 if (err)
3683 return err;
bc46a3d5 3684
107fcc10
VD		 3685 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3686 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 3687
3688 info = mv88e6xxx_lookup_info(prod_num);
3689 if (!info)
3690 return -ENODEV;
3691
caac8545 3692 /* Update the compatible info with the probed one */
fad09c73 3693 chip->info = info;
bc46a3d5 3694
ca070c10
VD		 3695 err = mv88e6xxx_g2_require(chip);
3696 if (err)
3697 return err;
3698
fad09c73
VD		 3699 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3700 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3701
3702 return 0;
3703}
3704
fad09c73 3705static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3706{
fad09c73 3707 struct mv88e6xxx_chip *chip;
469d729f 3708
fad09c73
VD		 3709 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3710 if (!chip)
469d729f
VD		 3711 return NULL;
3712
fad09c73 3713 chip->dev = dev;
469d729f 3714
fad09c73 3715 mutex_init(&chip->reg_lock);
a3c53be5 3716 INIT_LIST_HEAD(&chip->mdios);
469d729f 3717
fad09c73 3718 return chip;
469d729f
VD		 3719}
3720
fad09c73 3721static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3722 struct mii_bus *bus, int sw_addr)
3723{
914b32f6 3724 if (sw_addr == 0)
fad09c73 3725 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3726 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3727 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3728 else
3729 return -EINVAL;
3730
fad09c73
VD		 3731 chip->bus = bus;
3732 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3733
3734 return 0;
3735}
3736
7b314362
AL		 3737static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3738{
04bed143 3739 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 3740
443d5a1b 3741 return chip->info->tag_protocol;
7b314362
AL		 3742}
3743
fcdce7d0
AL		 3744static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3745 struct device *host_dev, int sw_addr,
3746 void **priv)
a77d43f1 3747{
fad09c73 3748 struct mv88e6xxx_chip *chip;
a439c061 3749 struct mii_bus *bus;
b516d453 3750 int err;
a77d43f1 3751
a439c061 3752 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3753 if (!bus)
3754 return NULL;
3755
fad09c73
VD		 3756 chip = mv88e6xxx_alloc_chip(dsa_dev);
3757 if (!chip)
469d729f
VD		 3758 return NULL;
3759
caac8545 3760 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3761 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3762
fad09c73 3763 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3764 if (err)
3765 goto free;
3766
fad09c73 3767 err = mv88e6xxx_detect(chip);
bc46a3d5 3768 if (err)
469d729f 3769 goto free;
a439c061 3770
dc30c35b
AL		 3771 mutex_lock(&chip->reg_lock);
3772 err = mv88e6xxx_switch_reset(chip);
3773 mutex_unlock(&chip->reg_lock);
3774 if (err)
3775 goto free;
3776
e57e5e77
VD		 3777 mv88e6xxx_phy_init(chip);
3778
a3c53be5 3779 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 3780 if (err)
469d729f 3781 goto free;
b516d453 3782
fad09c73 3783 *priv = chip;
a439c061 3784
fad09c73 3785 return chip->info->name;
469d729f 3786free:
fad09c73 3787 devm_kfree(dsa_dev, chip);
469d729f
VD		 3788
3789 return NULL;
a77d43f1
AL		 3790}
3791
7df8fbdd
VD		 3792static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3793 const struct switchdev_obj_port_mdb *mdb,
3794 struct switchdev_trans *trans)
3795{
3796 /* We don't need any dynamic resource from the kernel (yet),
3797 * so skip the prepare phase.
3798 */
3799
3800 return 0;
3801}
3802
3803static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3804 const struct switchdev_obj_port_mdb *mdb,
3805 struct switchdev_trans *trans)
3806{
04bed143 3807 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3808
3809 mutex_lock(&chip->reg_lock);
3810 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3811 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
774439e5
VD		 3812 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3813 port);
7df8fbdd
VD		 3814 mutex_unlock(&chip->reg_lock);
3815}
3816
3817static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3818 const struct switchdev_obj_port_mdb *mdb)
3819{
04bed143 3820 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3821 int err;
3822
3823 mutex_lock(&chip->reg_lock);
3824 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3825 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
7df8fbdd
VD		 3826 mutex_unlock(&chip->reg_lock);
3827
3828 return err;
3829}
3830
3831static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3832 struct switchdev_obj_port_mdb *mdb,
438ff537 3833 switchdev_obj_dump_cb_t *cb)
7df8fbdd 3834{
04bed143 3835 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3836 int err;
3837
3838 mutex_lock(&chip->reg_lock);
3839 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3840 mutex_unlock(&chip->reg_lock);
3841
3842 return err;
3843}
3844
a82f67af 3845static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3846 .probe = mv88e6xxx_drv_probe,
7b314362 3847 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3848 .setup = mv88e6xxx_setup,
3849 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3850 .adjust_link = mv88e6xxx_adjust_link,
3851 .get_strings = mv88e6xxx_get_strings,
3852 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3853 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 3854 .port_enable = mv88e6xxx_port_enable,
3855 .port_disable = mv88e6xxx_port_disable,
f81ec90f
VD		 3856 .set_eee = mv88e6xxx_set_eee,
3857 .get_eee = mv88e6xxx_get_eee,
f8cd8753 3858 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3859 .get_eeprom = mv88e6xxx_get_eeprom,
3860 .set_eeprom = mv88e6xxx_set_eeprom,
3861 .get_regs_len = mv88e6xxx_get_regs_len,
3862 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3863 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3864 .port_bridge_join = mv88e6xxx_port_bridge_join,
3865 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3866 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3867 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3868 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3869 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3870 .port_vlan_add = mv88e6xxx_port_vlan_add,
3871 .port_vlan_del = mv88e6xxx_port_vlan_del,
3872 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3873 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3874 .port_fdb_add = mv88e6xxx_port_fdb_add,
3875 .port_fdb_del = mv88e6xxx_port_fdb_del,
3876 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3877 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3878 .port_mdb_add = mv88e6xxx_port_mdb_add,
3879 .port_mdb_del = mv88e6xxx_port_mdb_del,
3880 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
aec5ac88
VD		 3881 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3882 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 3883};
3884
ab3d408d
FF		 3885static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3886 .ops = &mv88e6xxx_switch_ops,
3887};
3888
55ed0ce0 3889static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3890{
fad09c73 3891 struct device *dev = chip->dev;
b7e66a5f
VD		 3892 struct dsa_switch *ds;
3893
73b1204d 3894 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 3895 if (!ds)
3896 return -ENOMEM;
3897
fad09c73 3898 ds->priv = chip;
9d490b4e 3899 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 3900 ds->ageing_time_min = chip->info->age_time_coeff;
3901 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 3902
3903 dev_set_drvdata(dev, ds);
3904
23c9ee49 3905 return dsa_register_switch(ds);
b7e66a5f
VD		 3906}
3907
fad09c73 3908static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3909{
fad09c73 3910 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3911}
3912
57d32310 3913static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3914{
14c7b3c3 3915 struct device *dev = &mdiodev->dev;
f8cd8753 3916 struct device_node *np = dev->of_node;
caac8545 3917 const struct mv88e6xxx_info *compat_info;
fad09c73 3918 struct mv88e6xxx_chip *chip;
f8cd8753 3919 u32 eeprom_len;
52638f71 3920 int err;
14c7b3c3 3921
caac8545
VD		 3922 compat_info = of_device_get_match_data(dev);
3923 if (!compat_info)
3924 return -EINVAL;
3925
fad09c73
VD		 3926 chip = mv88e6xxx_alloc_chip(dev);
3927 if (!chip)
14c7b3c3
AL		 3928 return -ENOMEM;
3929
fad09c73 3930 chip->info = compat_info;
caac8545 3931
fad09c73 3932 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3933 if (err)
3934 return err;
14c7b3c3 3935
b4308f04
AL		 3936 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
3937 if (IS_ERR(chip->reset))
3938 return PTR_ERR(chip->reset);
3939
fad09c73 3940 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3941 if (err)
3942 return err;
14c7b3c3 3943
e57e5e77
VD		 3944 mv88e6xxx_phy_init(chip);
3945
ee4dc2e7 3946 if (chip->info->ops->get_eeprom &&
f8cd8753 3947 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3948 chip->eeprom_len = eeprom_len;
f8cd8753 3949
dc30c35b
AL		 3950 mutex_lock(&chip->reg_lock);
3951 err = mv88e6xxx_switch_reset(chip);
3952 mutex_unlock(&chip->reg_lock);
3953 if (err)
3954 goto out;
3955
3956 chip->irq = of_irq_get(np, 0);
3957 if (chip->irq == -EPROBE_DEFER) {
3958 err = chip->irq;
3959 goto out;
3960 }
3961
3962 if (chip->irq > 0) {
3963 /* Has to be performed before the MDIO bus is created,
3964 * because the PHYs will link there interrupts to these
3965 * interrupt controllers
3966 */
3967 mutex_lock(&chip->reg_lock);
3968 err = mv88e6xxx_g1_irq_setup(chip);
3969 mutex_unlock(&chip->reg_lock);
3970
3971 if (err)
3972 goto out;
3973
3974 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
3975 err = mv88e6xxx_g2_irq_setup(chip);
3976 if (err)
3977 goto out_g1_irq;
3978 }
3979 }
3980
a3c53be5 3981 err = mv88e6xxx_mdios_register(chip, np);
b516d453 3982 if (err)
dc30c35b 3983 goto out_g2_irq;
b516d453 3984
55ed0ce0 3985 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 3986 if (err)
3987 goto out_mdio;
83c0afae 3988
98e67308 3989 return 0;
dc30c35b
AL		 3990
3991out_mdio:
a3c53be5 3992 mv88e6xxx_mdios_unregister(chip);
dc30c35b 3993out_g2_irq:
46712644 3994 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
dc30c35b
AL		 3995 mv88e6xxx_g2_irq_free(chip);
3996out_g1_irq:
61f7c3f8
AL		 3997 if (chip->irq > 0) {
3998 mutex_lock(&chip->reg_lock);
46712644 3999 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4000 mutex_unlock(&chip->reg_lock);
4001 }
dc30c35b
AL		 4002out:
4003 return err;
98e67308 4004}
14c7b3c3
AL		 4005
4006static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4007{
4008 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4009 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4010
930188ce 4011 mv88e6xxx_phy_destroy(chip);
fad09c73 4012 mv88e6xxx_unregister_switch(chip);
a3c53be5 4013 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4014
46712644
AL		 4015 if (chip->irq > 0) {
4016 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4017 mv88e6xxx_g2_irq_free(chip);
4018 mv88e6xxx_g1_irq_free(chip);
4019 }
14c7b3c3
AL		 4020}
4021
4022static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4023 {
4024 .compatible = "marvell,mv88e6085",
4025 .data = &mv88e6xxx_table[MV88E6085],
4026 },
1a3b39ec
AL		 4027 {
4028 .compatible = "marvell,mv88e6190",
4029 .data = &mv88e6xxx_table[MV88E6190],
4030 },
14c7b3c3
AL		 4031 { /* sentinel */ },
4032};
4033
4034MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4035
4036static struct mdio_driver mv88e6xxx_driver = {
4037 .probe = mv88e6xxx_probe,
4038 .remove = mv88e6xxx_remove,
4039 .mdiodrv.driver = {
4040 .name = "mv88e6085",
4041 .of_match_table = mv88e6xxx_of_match,
4042 },
4043};
4044
4045static int __init mv88e6xxx_init(void)
4046{
ab3d408d 4047 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4048 return mdio_driver_register(&mv88e6xxx_driver);
4049}
98e67308
BH		 4050module_init(mv88e6xxx_init);
4051
4052static void __exit mv88e6xxx_cleanup(void)
4053{
14c7b3c3 4054 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4055 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4056}
4057module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4058
4059MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4060MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4061MODULE_LICENSE("GPL");
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