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net: dsa: mv88e6xxx: expose mv88e6xxx_num_databases
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
b516d453 26#include <linux/of_mdio.h>
91da11f8 27#include <linux/netdevice.h>
c8c1b39a 28#include <linux/gpio/consumer.h>
91da11f8 29#include <linux/phy.h>
c8f0b869 30#include <net/dsa.h>
1f36faf2 31#include <net/switchdev.h>
ec561276 32
91da11f8 33#include "mv88e6xxx.h"
a935c052 34#include "global1.h"
ec561276 35#include "global2.h"
91da11f8 36
fad09c73 37static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 38{
fad09c73
VD		 39 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
40 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 41 dump_stack();
42 }
43}
44
914b32f6
VD		 45/* The switch ADDR[4:1] configuration pins define the chip SMI device address
46 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
47 *
48 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
49 * is the only device connected to the SMI master. In this mode it responds to
50 * all 32 possible SMI addresses, and thus maps directly the internal devices.
51 *
52 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
53 * multiple devices to share the SMI interface. In this mode it responds to only
54 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 55 */
914b32f6 56
fad09c73 57static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 58 int addr, int reg, u16 *val)
59{
fad09c73 60 if (!chip->smi_ops)
914b32f6
VD		 61 return -EOPNOTSUPP;
62
fad09c73 63 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 64}
65
fad09c73 66static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 67 int addr, int reg, u16 val)
68{
fad09c73 69 if (!chip->smi_ops)
914b32f6
VD		 70 return -EOPNOTSUPP;
71
fad09c73 72 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 73}
74
fad09c73 75static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 76 int addr, int reg, u16 *val)
77{
78 int ret;
79
fad09c73 80 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 81 if (ret < 0)
82 return ret;
83
84 *val = ret & 0xffff;
85
86 return 0;
87}
88
fad09c73 89static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 90 int addr, int reg, u16 val)
91{
92 int ret;
93
fad09c73 94 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 95 if (ret < 0)
96 return ret;
97
98 return 0;
99}
100
101static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
102 .read = mv88e6xxx_smi_single_chip_read,
103 .write = mv88e6xxx_smi_single_chip_write,
104};
105
fad09c73 106static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 107{
108 int ret;
109 int i;
110
111 for (i = 0; i < 16; i++) {
fad09c73 112 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 113 if (ret < 0)
114 return ret;
115
cca8b133 116 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 117 return 0;
118 }
119
120 return -ETIMEDOUT;
121}
122
fad09c73 123static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 124 int addr, int reg, u16 *val)
91da11f8
LB		 125{
126 int ret;
127
3675c8d7 128 /* Wait for the bus to become free. */
fad09c73 129 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 130 if (ret < 0)
131 return ret;
132
3675c8d7 133 /* Transmit the read command. */
fad09c73 134 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 135 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Wait for the read command to complete. */
fad09c73 140 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Read the data. */
fad09c73 145 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 146 if (ret < 0)
147 return ret;
148
914b32f6 149 *val = ret & 0xffff;
91da11f8 150
914b32f6 151 return 0;
8d6d09e7
GR		 152}
153
fad09c73 154static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 155 int addr, int reg, u16 val)
91da11f8
LB		 156{
157 int ret;
158
3675c8d7 159 /* Wait for the bus to become free. */
fad09c73 160 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 161 if (ret < 0)
162 return ret;
163
3675c8d7 164 /* Transmit the data to write. */
fad09c73 165 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the write command. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 171 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Wait for the write command to complete. */
fad09c73 176 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
180 return 0;
181}
182
914b32f6
VD		 183static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
184 .read = mv88e6xxx_smi_multi_chip_read,
185 .write = mv88e6xxx_smi_multi_chip_write,
186};
187
ec561276 188int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 189{
190 int err;
191
fad09c73 192 assert_reg_lock(chip);
914b32f6 193
fad09c73 194 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 195 if (err)
196 return err;
197
fad09c73 198 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 199 addr, reg, *val);
200
201 return 0;
202}
203
ec561276 204int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 205{
914b32f6
VD		 206 int err;
207
fad09c73 208 assert_reg_lock(chip);
91da11f8 209
fad09c73 210 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 211 if (err)
212 return err;
213
fad09c73 214 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 215 addr, reg, val);
216
914b32f6
VD		 217 return 0;
218}
219
b3f5bf64
WY		 220static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
221 u16 *val)
0e7b9925
AL		 222{
223 int addr = chip->info->port_base_addr + port;
224
225 return mv88e6xxx_read(chip, addr, reg, val);
226}
227
b3f5bf64
WY		 228static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
229 u16 val)
0e7b9925
AL		 230{
231 int addr = chip->info->port_base_addr + port;
232
233 return mv88e6xxx_write(chip, addr, reg, val);
234}
235
e57e5e77
VD		 236static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 *val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
241 if (!chip->phy_ops)
242 return -EOPNOTSUPP;
243
244 return chip->phy_ops->read(chip, addr, reg, val);
245}
246
247static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
248 int reg, u16 val)
249{
250 int addr = phy; /* PHY devices addresses start at 0x0 */
251
252 if (!chip->phy_ops)
253 return -EOPNOTSUPP;
254
255 return chip->phy_ops->write(chip, addr, reg, val);
256}
257
09cb7dfd
VD		 258static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
259{
260 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
261 return -EOPNOTSUPP;
262
263 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
264}
265
266static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
267{
268 int err;
269
270 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
271 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
272 if (unlikely(err)) {
273 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
274 phy, err);
275 }
276}
277
278static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
279 u8 page, int reg, u16 *val)
280{
281 int err;
282
283 /* There is no paging for registers 22 */
284 if (reg == PHY_PAGE)
285 return -EINVAL;
286
287 err = mv88e6xxx_phy_page_get(chip, phy, page);
288 if (!err) {
289 err = mv88e6xxx_phy_read(chip, phy, reg, val);
290 mv88e6xxx_phy_page_put(chip, phy);
291 }
292
293 return err;
294}
295
296static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
297 u8 page, int reg, u16 val)
298{
299 int err;
300
301 /* There is no paging for registers 22 */
302 if (reg == PHY_PAGE)
303 return -EINVAL;
304
305 err = mv88e6xxx_phy_page_get(chip, phy, page);
306 if (!err) {
307 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
308 mv88e6xxx_phy_page_put(chip, phy);
309 }
310
311 return err;
312}
313
314static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
315{
316 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
317 reg, val);
318}
319
320static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
321{
322 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
323 reg, val);
324}
325
ec561276 326int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 327{
6441e669 328 int i;
2d79af6e 329
6441e669 330 for (i = 0; i < 16; i++) {
2d79af6e
VD		 331 u16 val;
332 int err;
333
334 err = mv88e6xxx_read(chip, addr, reg, &val);
335 if (err)
336 return err;
337
338 if (!(val & mask))
339 return 0;
340
341 usleep_range(1000, 2000);
342 }
343
30853553 344 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 345 return -ETIMEDOUT;
346}
347
f22ab641 348/* Indirect write to single pointer-data register with an Update bit */
ec561276 349int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 350{
351 u16 val;
0f02b4f7 352 int err;
f22ab641
VD		 353
354 /* Wait until the previous operation is completed */
0f02b4f7
AL		 355 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
356 if (err)
357 return err;
f22ab641
VD		 358
359 /* Set the Update bit to trigger a write operation */
360 val = BIT(15) | update;
361
362 return mv88e6xxx_write(chip, addr, reg, val);
363}
364
a935c052 365static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6
VD		 366{
367 u16 val;
a935c052 368 int i, err;
914b32f6 369
a935c052 370 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
914b32f6
VD		 371 if (err)
372 return err;
373
a935c052
VD		 374 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
375 val & ~GLOBAL_CONTROL_PPU_ENABLE);
376 if (err)
377 return err;
2e5f0320 378
6441e669 379 for (i = 0; i < 16; i++) {
a935c052
VD		 380 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
381 if (err)
382 return err;
48ace4ef 383
19b2f97e 384 usleep_range(1000, 2000);
a935c052 385 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
85686581 386 return 0;
2e5f0320
LB		 387 }
388
389 return -ETIMEDOUT;
390}
391
fad09c73 392static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 393{
a935c052
VD		 394 u16 val;
395 int i, err;
2e5f0320 396
a935c052
VD		 397 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
398 if (err)
399 return err;
48ace4ef 400
a935c052
VD		 401 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
402 val | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 403 if (err)
404 return err;
2e5f0320 405
6441e669 406 for (i = 0; i < 16; i++) {
a935c052
VD		 407 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
408 if (err)
409 return err;
48ace4ef 410
19b2f97e 411 usleep_range(1000, 2000);
a935c052 412 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
85686581 413 return 0;
2e5f0320
LB		 414 }
415
416 return -ETIMEDOUT;
417}
418
419static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
420{
fad09c73 421 struct mv88e6xxx_chip *chip;
2e5f0320 422
fad09c73 423 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 424
fad09c73 425 mutex_lock(&chip->reg_lock);
762eb67b 426
fad09c73
VD		 427 if (mutex_trylock(&chip->ppu_mutex)) {
428 if (mv88e6xxx_ppu_enable(chip) == 0)
429 chip->ppu_disabled = 0;
430 mutex_unlock(&chip->ppu_mutex);
2e5f0320 431 }
762eb67b 432
fad09c73 433 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 434}
435
436static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
437{
fad09c73 438 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 439
fad09c73 440 schedule_work(&chip->ppu_work);
2e5f0320
LB		 441}
442
fad09c73 443static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 444{
2e5f0320
LB		 445 int ret;
446
fad09c73 447 mutex_lock(&chip->ppu_mutex);
2e5f0320 448
3675c8d7 449 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 450 * we can access the PHY registers. If it was already
451 * disabled, cancel the timer that is going to re-enable
452 * it.
453 */
fad09c73
VD		 454 if (!chip->ppu_disabled) {
455 ret = mv88e6xxx_ppu_disable(chip);
85686581 456 if (ret < 0) {
fad09c73 457 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 458 return ret;
459 }
fad09c73 460 chip->ppu_disabled = 1;
2e5f0320 461 } else {
fad09c73 462 del_timer(&chip->ppu_timer);
85686581 463 ret = 0;
2e5f0320
LB		 464 }
465
466 return ret;
467}
468
fad09c73 469static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 470{
3675c8d7 471 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 472 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
473 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 474}
475
fad09c73 476static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 477{
fad09c73
VD		 478 mutex_init(&chip->ppu_mutex);
479 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
480 init_timer(&chip->ppu_timer);
481 chip->ppu_timer.data = (unsigned long)chip;
482 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 483}
484
930188ce
AL		 485static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
486{
487 del_timer_sync(&chip->ppu_timer);
488}
489
e57e5e77
VD		 490static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
491 int reg, u16 *val)
2e5f0320 492{
e57e5e77 493 int err;
2e5f0320 494
e57e5e77
VD		 495 err = mv88e6xxx_ppu_access_get(chip);
496 if (!err) {
497 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 498 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 499 }
500
e57e5e77 501 return err;
2e5f0320
LB		 502}
503
e57e5e77
VD		 504static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
505 int reg, u16 val)
2e5f0320 506{
e57e5e77 507 int err;
2e5f0320 508
e57e5e77
VD		 509 err = mv88e6xxx_ppu_access_get(chip);
510 if (!err) {
511 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 512 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 513 }
514
e57e5e77 515 return err;
2e5f0320 516}
2e5f0320 517
e57e5e77
VD		 518static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
519 .read = mv88e6xxx_phy_ppu_read,
520 .write = mv88e6xxx_phy_ppu_write,
521};
522
fad09c73 523static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 524{
fad09c73 525 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 526}
527
fad09c73 528static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 529{
fad09c73 530 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 531}
532
fad09c73 533static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 534{
fad09c73 535 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 536}
537
fad09c73 538static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 539{
fad09c73 540 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 541}
542
fad09c73 543static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 544{
fad09c73 545 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 546}
547
fad09c73 548static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 549{
fad09c73 550 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 551}
552
fad09c73 553static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 554{
fad09c73 555 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 556}
557
fad09c73 558static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 559{
fad09c73 560 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 561}
562
dea87024
AL		 563/* We expect the switch to perform auto negotiation if there is a real
564 * phy. However, in the case of a fixed link phy, we force the port
565 * settings from the fixed link settings.
566 */
f81ec90f
VD		 567static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
568 struct phy_device *phydev)
dea87024 569{
04bed143 570 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 571 u16 reg;
572 int err;
dea87024
AL		 573
574 if (!phy_is_pseudo_fixed_link(phydev))
575 return;
576
fad09c73 577 mutex_lock(&chip->reg_lock);
dea87024 578
0e7b9925
AL		 579 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
580 if (err)
dea87024
AL		 581 goto out;
582
0e7b9925
AL		 583 reg &= ~(PORT_PCS_CTRL_LINK_UP |
584 PORT_PCS_CTRL_FORCE_LINK |
585 PORT_PCS_CTRL_DUPLEX_FULL |
586 PORT_PCS_CTRL_FORCE_DUPLEX |
587 PORT_PCS_CTRL_UNFORCED);
dea87024
AL		 588
589 reg |= PORT_PCS_CTRL_FORCE_LINK;
590 if (phydev->link)
57d32310 591 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 592
fad09c73 593 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 594 goto out;
595
596 switch (phydev->speed) {
597 case SPEED_1000:
598 reg |= PORT_PCS_CTRL_1000;
599 break;
600 case SPEED_100:
601 reg |= PORT_PCS_CTRL_100;
602 break;
603 case SPEED_10:
604 reg |= PORT_PCS_CTRL_10;
605 break;
606 default:
607 pr_info("Unknown speed");
608 goto out;
609 }
610
611 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
612 if (phydev->duplex == DUPLEX_FULL)
613 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
614
fad09c73
VD		 615 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
616 (port >= chip->info->num_ports - 2)) {
e7e72ac0
AL		 617 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
618 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
619 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
620 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
621 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
622 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
623 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
624 }
0e7b9925 625 mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
dea87024
AL		 626
627out:
fad09c73 628 mutex_unlock(&chip->reg_lock);
dea87024
AL		 629}
630
fad09c73 631static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8 632{
a935c052
VD		 633 u16 val;
634 int i, err;
91da11f8
LB		 635
636 for (i = 0; i < 10; i++) {
a935c052
VD		 637 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
638 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 639 return 0;
640 }
641
642 return -ETIMEDOUT;
643}
644
fad09c73 645static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 646{
a935c052 647 int err;
91da11f8 648
fad09c73 649 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 650 port = (port + 1) << 5;
651
3675c8d7 652 /* Snapshot the hardware statistics counters for this port. */
a935c052
VD		 653 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
654 GLOBAL_STATS_OP_CAPTURE_PORT |
655 GLOBAL_STATS_OP_HIST_RX_TX | port);
656 if (err)
657 return err;
91da11f8 658
3675c8d7 659 /* Wait for the snapshotting to complete. */
a935c052 660 return _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 661}
662
fad09c73 663static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 664 int stat, u32 *val)
91da11f8 665{
a935c052
VD		 666 u32 value;
667 u16 reg;
668 int err;
91da11f8
LB		 669
670 *val = 0;
671
a935c052
VD		 672 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
673 GLOBAL_STATS_OP_READ_CAPTURED |
674 GLOBAL_STATS_OP_HIST_RX_TX | stat);
675 if (err)
91da11f8
LB		 676 return;
677
a935c052
VD		 678 err = _mv88e6xxx_stats_wait(chip);
679 if (err)
91da11f8
LB		 680 return;
681
a935c052
VD		 682 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
683 if (err)
91da11f8
LB		 684 return;
685
a935c052 686 value = reg << 16;
91da11f8 687
a935c052
VD		 688 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
689 if (err)
91da11f8
LB		 690 return;
691
a935c052 692 *val = value | reg;
91da11f8
LB		 693}
694
e413e7e1 695static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 696 { "in_good_octets", 8, 0x00, BANK0, },
697 { "in_bad_octets", 4, 0x02, BANK0, },
698 { "in_unicast", 4, 0x04, BANK0, },
699 { "in_broadcasts", 4, 0x06, BANK0, },
700 { "in_multicasts", 4, 0x07, BANK0, },
701 { "in_pause", 4, 0x16, BANK0, },
702 { "in_undersize", 4, 0x18, BANK0, },
703 { "in_fragments", 4, 0x19, BANK0, },
704 { "in_oversize", 4, 0x1a, BANK0, },
705 { "in_jabber", 4, 0x1b, BANK0, },
706 { "in_rx_error", 4, 0x1c, BANK0, },
707 { "in_fcs_error", 4, 0x1d, BANK0, },
708 { "out_octets", 8, 0x0e, BANK0, },
709 { "out_unicast", 4, 0x10, BANK0, },
710 { "out_broadcasts", 4, 0x13, BANK0, },
711 { "out_multicasts", 4, 0x12, BANK0, },
712 { "out_pause", 4, 0x15, BANK0, },
713 { "excessive", 4, 0x11, BANK0, },
714 { "collisions", 4, 0x1e, BANK0, },
715 { "deferred", 4, 0x05, BANK0, },
716 { "single", 4, 0x14, BANK0, },
717 { "multiple", 4, 0x17, BANK0, },
718 { "out_fcs_error", 4, 0x03, BANK0, },
719 { "late", 4, 0x1f, BANK0, },
720 { "hist_64bytes", 4, 0x08, BANK0, },
721 { "hist_65_127bytes", 4, 0x09, BANK0, },
722 { "hist_128_255bytes", 4, 0x0a, BANK0, },
723 { "hist_256_511bytes", 4, 0x0b, BANK0, },
724 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
725 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
726 { "sw_in_discards", 4, 0x10, PORT, },
727 { "sw_in_filtered", 2, 0x12, PORT, },
728 { "sw_out_filtered", 2, 0x13, PORT, },
729 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
730 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
731 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
732 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
733 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
734 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
735 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
736 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
737 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
738 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
739 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
740 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
741 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
742 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
743 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
744 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
745 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
746 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
747 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
748 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
749 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
750 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
751 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
752 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
753 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
754 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 755};
756
fad09c73 757static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 758 struct mv88e6xxx_hw_stat *stat)
e413e7e1 759{
f5e2ed02
AL		 760 switch (stat->type) {
761 case BANK0:
e413e7e1 762 return true;
f5e2ed02 763 case BANK1:
fad09c73 764 return mv88e6xxx_6320_family(chip);
f5e2ed02 765 case PORT:
fad09c73
VD		 766 return mv88e6xxx_6095_family(chip) ||
767 mv88e6xxx_6185_family(chip) ||
768 mv88e6xxx_6097_family(chip) ||
769 mv88e6xxx_6165_family(chip) ||
770 mv88e6xxx_6351_family(chip) ||
771 mv88e6xxx_6352_family(chip);
91da11f8 772 }
f5e2ed02 773 return false;
91da11f8
LB		 774}
775
fad09c73 776static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 777 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 778 int port)
779{
80c4627b
AL		 780 u32 low;
781 u32 high = 0;
0e7b9925
AL		 782 int err;
783 u16 reg;
80c4627b
AL		 784 u64 value;
785
f5e2ed02
AL		 786 switch (s->type) {
787 case PORT:
0e7b9925
AL		 788 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
789 if (err)
80c4627b
AL		 790 return UINT64_MAX;
791
0e7b9925 792 low = reg;
80c4627b 793 if (s->sizeof_stat == 4) {
0e7b9925
AL		 794 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
795 if (err)
80c4627b 796 return UINT64_MAX;
0e7b9925 797 high = reg;
80c4627b 798 }
f5e2ed02
AL		 799 break;
800 case BANK0:
801 case BANK1:
fad09c73 802 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 803 if (s->sizeof_stat == 8)
fad09c73 804 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 805 }
806 value = (((u64)high) << 16) | low;
807 return value;
808}
809
f81ec90f
VD		 810static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
811 uint8_t *data)
91da11f8 812{
04bed143 813 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 814 struct mv88e6xxx_hw_stat *stat;
815 int i, j;
91da11f8 816
f5e2ed02
AL		 817 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
818 stat = &mv88e6xxx_hw_stats[i];
fad09c73 819 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 820 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
821 ETH_GSTRING_LEN);
822 j++;
823 }
91da11f8 824 }
e413e7e1
AL		 825}
826
f81ec90f 827static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 828{
04bed143 829 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 830 struct mv88e6xxx_hw_stat *stat;
831 int i, j;
832
833 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
834 stat = &mv88e6xxx_hw_stats[i];
fad09c73 835 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 836 j++;
837 }
838 return j;
e413e7e1
AL		 839}
840
f81ec90f
VD		 841static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
842 uint64_t *data)
e413e7e1 843{
04bed143 844 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 845 struct mv88e6xxx_hw_stat *stat;
846 int ret;
847 int i, j;
848
fad09c73 849 mutex_lock(&chip->reg_lock);
f5e2ed02 850
fad09c73 851 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 852 if (ret < 0) {
fad09c73 853 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 854 return;
855 }
856 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
857 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 858 if (mv88e6xxx_has_stat(chip, stat)) {
859 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 860 j++;
861 }
862 }
863
fad09c73 864 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 865}
866
f81ec90f 867static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 868{
869 return 32 * sizeof(u16);
870}
871
f81ec90f
VD		 872static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
873 struct ethtool_regs *regs, void *_p)
a1ab91f3 874{
04bed143 875 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 876 int err;
877 u16 reg;
a1ab91f3
GR		 878 u16 *p = _p;
879 int i;
880
881 regs->version = 0;
882
883 memset(p, 0xff, 32 * sizeof(u16));
884
fad09c73 885 mutex_lock(&chip->reg_lock);
23062513 886
a1ab91f3 887 for (i = 0; i < 32; i++) {
a1ab91f3 888
0e7b9925
AL		 889 err = mv88e6xxx_port_read(chip, port, i, &reg);
890 if (!err)
891 p[i] = reg;
a1ab91f3 892 }
23062513 893
fad09c73 894 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 895}
896
fad09c73 897static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 898{
a935c052 899 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 900}
901
f81ec90f
VD		 902static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
903 struct ethtool_eee *e)
11b3b45d 904{
04bed143 905 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 906 u16 reg;
907 int err;
11b3b45d 908
fad09c73 909 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 910 return -EOPNOTSUPP;
911
fad09c73 912 mutex_lock(&chip->reg_lock);
2f40c698 913
9c93829c
VD		 914 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
915 if (err)
2f40c698 916 goto out;
11b3b45d
GR		 917
918 e->eee_enabled = !!(reg & 0x0200);
919 e->tx_lpi_enabled = !!(reg & 0x0100);
920
0e7b9925 921 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 922 if (err)
2f40c698 923 goto out;
11b3b45d 924
cca8b133 925 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 926out:
fad09c73 927 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 928
929 return err;
11b3b45d
GR		 930}
931
f81ec90f
VD		 932static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
933 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 934{
04bed143 935 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 936 u16 reg;
937 int err;
11b3b45d 938
fad09c73 939 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 940 return -EOPNOTSUPP;
941
fad09c73 942 mutex_lock(&chip->reg_lock);
11b3b45d 943
9c93829c
VD		 944 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
945 if (err)
2f40c698
AL		 946 goto out;
947
9c93829c 948 reg &= ~0x0300;
2f40c698
AL		 949 if (e->eee_enabled)
950 reg |= 0x0200;
951 if (e->tx_lpi_enabled)
952 reg |= 0x0100;
953
9c93829c 954 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 955out:
fad09c73 956 mutex_unlock(&chip->reg_lock);
2f40c698 957
9c93829c 958 return err;
11b3b45d
GR		 959}
960
fad09c73 961static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 962{
a935c052
VD		 963 u16 val;
964 int err;
facd95b2 965
6dc10bbc 966 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 967 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
968 if (err)
969 return err;
fad09c73 970 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 971 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 972 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
973 if (err)
974 return err;
11ea809f 975
a935c052
VD		 976 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
977 (val & 0xfff) | ((fid << 8) & 0xf000));
978 if (err)
979 return err;
11ea809f
VD		 980
981 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
982 cmd |= fid & 0xf;
b426e5f7
VD		 983 }
984
a935c052
VD		 985 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
986 if (err)
987 return err;
facd95b2 988
fad09c73 989 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 990}
991
fad09c73 992static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 993 struct mv88e6xxx_atu_entry *entry)
994{
995 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
996
997 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
998 unsigned int mask, shift;
999
1000 if (entry->trunk) {
1001 data |= GLOBAL_ATU_DATA_TRUNK;
1002 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1003 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1004 } else {
1005 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1006 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1007 }
1008
1009 data |= (entry->portv_trunkid << shift) & mask;
1010 }
1011
a935c052 1012 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1013}
1014
fad09c73 1015static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1016 struct mv88e6xxx_atu_entry *entry,
1017 bool static_too)
facd95b2 1018{
7fb5e755
VD		 1019 int op;
1020 int err;
facd95b2 1021
fad09c73 1022 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1023 if (err)
1024 return err;
facd95b2 1025
fad09c73 1026 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1027 if (err)
1028 return err;
1029
1030 if (entry->fid) {
7fb5e755
VD		 1031 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1032 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1033 } else {
1034 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1035 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1036 }
1037
fad09c73 1038 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1039}
1040
fad09c73 1041static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1042 u16 fid, bool static_too)
7fb5e755
VD		 1043{
1044 struct mv88e6xxx_atu_entry entry = {
1045 .fid = fid,
1046 .state = 0, /* EntryState bits must be 0 */
1047 };
70cc99d1 1048
fad09c73 1049 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1050}
1051
fad09c73 1052static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1053 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1054{
1055 struct mv88e6xxx_atu_entry entry = {
1056 .trunk = false,
1057 .fid = fid,
1058 };
1059
1060 /* EntryState bits must be 0xF */
1061 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1062
1063 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1064 entry.portv_trunkid = (to_port & 0x0f) << 4;
1065 entry.portv_trunkid |= from_port & 0x0f;
1066
fad09c73 1067 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1068}
1069
fad09c73 1070static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1071 int port, bool static_too)
9f4d55d2
VD		 1072{
1073 /* Destination port 0xF means remove the entries */
fad09c73 1074 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1075}
1076
2d9deae4
VD		 1077static const char * const mv88e6xxx_port_state_names[] = {
1078 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1079 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1080 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1081 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1082};
1083
fad09c73 1084static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1085 u8 state)
facd95b2 1086{
fad09c73 1087 struct dsa_switch *ds = chip->ds;
0e7b9925
AL		 1088 u16 reg;
1089 int err;
facd95b2
GR		 1090 u8 oldstate;
1091
0e7b9925
AL		 1092 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
1093 if (err)
1094 return err;
facd95b2 1095
cca8b133 1096 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1097
749efcb8
VD		 1098 reg &= ~PORT_CONTROL_STATE_MASK;
1099 reg |= state;
2d9deae4 1100
749efcb8
VD		 1101 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
1102 if (err)
1103 return err;
2d9deae4 1104
749efcb8
VD		 1105 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1106 mv88e6xxx_port_state_names[state],
1107 mv88e6xxx_port_state_names[oldstate]);
facd95b2 1108
749efcb8 1109 return 0;
facd95b2
GR		 1110}
1111
fad09c73 1112static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1113{
fad09c73
VD		 1114 struct net_device *bridge = chip->ports[port].bridge_dev;
1115 const u16 mask = (1 << chip->info->num_ports) - 1;
1116 struct dsa_switch *ds = chip->ds;
b7666efe 1117 u16 output_ports = 0;
0e7b9925
AL		 1118 u16 reg;
1119 int err;
b7666efe
VD		 1120 int i;
1121
1122 /* allow CPU port or DSA link(s) to send frames to every port */
1123 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1124 output_ports = mask;
1125 } else {
fad09c73 1126 for (i = 0; i < chip->info->num_ports; ++i) {
b7666efe 1127 /* allow sending frames to every group member */
fad09c73 1128 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1129 output_ports |= BIT(i);
1130
1131 /* allow sending frames to CPU port and DSA link(s) */
1132 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1133 output_ports |= BIT(i);
1134 }
1135 }
1136
1137 /* prevent frames from going back out of the port they came in on */
1138 output_ports &= ~BIT(port);
facd95b2 1139
0e7b9925
AL		 1140 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1141 if (err)
1142 return err;
facd95b2 1143
ede8098d
VD		 1144 reg &= ~mask;
1145 reg |= output_ports & mask;
facd95b2 1146
0e7b9925 1147 return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
facd95b2
GR		 1148}
1149
f81ec90f
VD		 1150static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1151 u8 state)
facd95b2 1152{
04bed143 1153 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1154 int stp_state;
553eb544 1155 int err;
facd95b2
GR		 1156
1157 switch (state) {
1158 case BR_STATE_DISABLED:
cca8b133 1159 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1160 break;
1161 case BR_STATE_BLOCKING:
1162 case BR_STATE_LISTENING:
cca8b133 1163 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1164 break;
1165 case BR_STATE_LEARNING:
cca8b133 1166 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1167 break;
1168 case BR_STATE_FORWARDING:
1169 default:
cca8b133 1170 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1171 break;
1172 }
1173
fad09c73
VD		 1174 mutex_lock(&chip->reg_lock);
1175 err = _mv88e6xxx_port_state(chip, port, stp_state);
1176 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1177
1178 if (err)
c8b09808
AL		 1179 netdev_err(ds->ports[port].netdev,
1180 "failed to update state to %s\n",
553eb544 1181 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1182}
1183
749efcb8
VD		 1184static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1185{
1186 struct mv88e6xxx_chip *chip = ds->priv;
1187 int err;
1188
1189 mutex_lock(&chip->reg_lock);
1190 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1191 mutex_unlock(&chip->reg_lock);
1192
1193 if (err)
1194 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1195}
1196
fad09c73 1197static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1198 u16 *new, u16 *old)
76e398a6 1199{
fad09c73 1200 struct dsa_switch *ds = chip->ds;
0e7b9925
AL		 1201 u16 pvid, reg;
1202 int err;
76e398a6 1203
0e7b9925
AL		 1204 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
1205 if (err)
1206 return err;
76e398a6 1207
0e7b9925 1208 pvid = reg & PORT_DEFAULT_VLAN_MASK;
5da96031
VD		 1209
1210 if (new) {
0e7b9925
AL		 1211 reg &= ~PORT_DEFAULT_VLAN_MASK;
1212 reg |= *new & PORT_DEFAULT_VLAN_MASK;
5da96031 1213
0e7b9925
AL		 1214 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
1215 if (err)
1216 return err;
5da96031 1217
c8b09808
AL		 1218 netdev_dbg(ds->ports[port].netdev,
1219 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1220 }
1221
1222 if (old)
1223 *old = pvid;
76e398a6
VD		 1224
1225 return 0;
1226}
1227
fad09c73 1228static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1229 int port, u16 *pvid)
5da96031 1230{
fad09c73 1231 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1232}
1233
fad09c73 1234static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1235 int port, u16 pvid)
0d3b33e6 1236{
fad09c73 1237 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1238}
1239
fad09c73 1240static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1241{
a935c052 1242 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1243}
1244
fad09c73 1245static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1246{
a935c052 1247 int err;
6b17e864 1248
a935c052
VD		 1249 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1250 if (err)
1251 return err;
6b17e864 1252
fad09c73 1253 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1254}
1255
fad09c73 1256static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1257{
1258 int ret;
1259
fad09c73 1260 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1261 if (ret < 0)
1262 return ret;
1263
fad09c73 1264 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1265}
1266
fad09c73 1267static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1268 struct mv88e6xxx_vtu_stu_entry *entry,
1269 unsigned int nibble_offset)
1270{
b8fee957 1271 u16 regs[3];
a935c052 1272 int i, err;
b8fee957
VD		 1273
1274 for (i = 0; i < 3; ++i) {
a935c052 1275 u16 *reg = &regs[i];
b8fee957 1276
a935c052
VD		 1277 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1278 if (err)
1279 return err;
b8fee957
VD		 1280 }
1281
fad09c73 1282 for (i = 0; i < chip->info->num_ports; ++i) {
b8fee957
VD		 1283 unsigned int shift = (i % 4) * 4 + nibble_offset;
1284 u16 reg = regs[i / 4];
1285
1286 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1287 }
1288
1289 return 0;
1290}
1291
fad09c73 1292static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1293 struct mv88e6xxx_vtu_stu_entry *entry)
1294{
fad09c73 1295 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1296}
1297
fad09c73 1298static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1299 struct mv88e6xxx_vtu_stu_entry *entry)
1300{
fad09c73 1301 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1302}
1303
fad09c73 1304static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1305 struct mv88e6xxx_vtu_stu_entry *entry,
1306 unsigned int nibble_offset)
1307{
7dad08d7 1308 u16 regs[3] = { 0 };
a935c052 1309 int i, err;
7dad08d7 1310
fad09c73 1311 for (i = 0; i < chip->info->num_ports; ++i) {
7dad08d7
VD		 1312 unsigned int shift = (i % 4) * 4 + nibble_offset;
1313 u8 data = entry->data[i];
1314
1315 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1316 }
1317
1318 for (i = 0; i < 3; ++i) {
a935c052
VD		 1319 u16 reg = regs[i];
1320
1321 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1322 if (err)
1323 return err;
7dad08d7
VD		 1324 }
1325
1326 return 0;
1327}
1328
fad09c73 1329static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1330 struct mv88e6xxx_vtu_stu_entry *entry)
1331{
fad09c73 1332 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1333}
1334
fad09c73 1335static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1336 struct mv88e6xxx_vtu_stu_entry *entry)
1337{
fad09c73 1338 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1339}
1340
fad09c73 1341static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1342{
a935c052
VD		 1343 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1344 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1345}
1346
fad09c73 1347static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1348 struct mv88e6xxx_vtu_stu_entry *entry)
1349{
1350 struct mv88e6xxx_vtu_stu_entry next = { 0 };
a935c052
VD		 1351 u16 val;
1352 int err;
b8fee957 1353
a935c052
VD		 1354 err = _mv88e6xxx_vtu_wait(chip);
1355 if (err)
1356 return err;
b8fee957 1357
a935c052
VD		 1358 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1359 if (err)
1360 return err;
b8fee957 1361
a935c052
VD		 1362 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1363 if (err)
1364 return err;
b8fee957 1365
a935c052
VD		 1366 next.vid = val & GLOBAL_VTU_VID_MASK;
1367 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1368
1369 if (next.valid) {
a935c052
VD		 1370 err = mv88e6xxx_vtu_data_read(chip, &next);
1371 if (err)
1372 return err;
b8fee957 1373
6dc10bbc 1374 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1375 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1376 if (err)
1377 return err;
b8fee957 1378
a935c052 1379 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1380 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1381 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1382 * VTU DBNum[3:0] are located in VTU Operation 3:0
1383 */
a935c052
VD		 1384 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1385 if (err)
1386 return err;
11ea809f 1387
a935c052
VD		 1388 next.fid = (val & 0xf00) >> 4;
1389 next.fid |= val & 0xf;
2e7bd5ef 1390 }
b8fee957 1391
fad09c73 1392 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1393 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1394 if (err)
1395 return err;
b8fee957 1396
a935c052 1397 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1398 }
1399 }
1400
1401 *entry = next;
1402 return 0;
1403}
1404
f81ec90f
VD		 1405static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1406 struct switchdev_obj_port_vlan *vlan,
1407 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1408{
04bed143 1409 struct mv88e6xxx_chip *chip = ds->priv;
ceff5eff
VD		 1410 struct mv88e6xxx_vtu_stu_entry next;
1411 u16 pvid;
1412 int err;
1413
fad09c73 1414 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1415 return -EOPNOTSUPP;
1416
fad09c73 1417 mutex_lock(&chip->reg_lock);
ceff5eff 1418
fad09c73 1419 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1420 if (err)
1421 goto unlock;
1422
fad09c73 1423 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1424 if (err)
1425 goto unlock;
1426
1427 do {
fad09c73 1428 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1429 if (err)
1430 break;
1431
1432 if (!next.valid)
1433 break;
1434
1435 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1436 continue;
1437
1438 /* reinit and dump this VLAN obj */
57d32310
VD		 1439 vlan->vid_begin = next.vid;
1440 vlan->vid_end = next.vid;
ceff5eff
VD		 1441 vlan->flags = 0;
1442
1443 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1444 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1445
1446 if (next.vid == pvid)
1447 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1448
1449 err = cb(&vlan->obj);
1450 if (err)
1451 break;
1452 } while (next.vid < GLOBAL_VTU_VID_MASK);
1453
1454unlock:
fad09c73 1455 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1456
1457 return err;
1458}
1459
fad09c73 1460static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1461 struct mv88e6xxx_vtu_stu_entry *entry)
1462{
11ea809f 1463 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1464 u16 reg = 0;
a935c052 1465 int err;
7dad08d7 1466
a935c052
VD		 1467 err = _mv88e6xxx_vtu_wait(chip);
1468 if (err)
1469 return err;
7dad08d7
VD		 1470
1471 if (!entry->valid)
1472 goto loadpurge;
1473
1474 /* Write port member tags */
a935c052
VD		 1475 err = mv88e6xxx_vtu_data_write(chip, entry);
1476 if (err)
1477 return err;
7dad08d7 1478
fad09c73 1479 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1480 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1481 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1482 if (err)
1483 return err;
b426e5f7 1484 }
7dad08d7 1485
6dc10bbc 1486 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1487 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1488 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1489 if (err)
1490 return err;
fad09c73 1491 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1492 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1493 * VTU DBNum[3:0] are located in VTU Operation 3:0
1494 */
1495 op |= (entry->fid & 0xf0) << 8;
1496 op |= entry->fid & 0xf;
7dad08d7
VD		 1497 }
1498
1499 reg = GLOBAL_VTU_VID_VALID;
1500loadpurge:
1501 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1502 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1503 if (err)
1504 return err;
7dad08d7 1505
fad09c73 1506 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1507}
1508
fad09c73 1509static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
0d3b33e6
VD		 1510 struct mv88e6xxx_vtu_stu_entry *entry)
1511{
1512 struct mv88e6xxx_vtu_stu_entry next = { 0 };
a935c052
VD		 1513 u16 val;
1514 int err;
0d3b33e6 1515
a935c052
VD		 1516 err = _mv88e6xxx_vtu_wait(chip);
1517 if (err)
1518 return err;
0d3b33e6 1519
a935c052
VD		 1520 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1521 sid & GLOBAL_VTU_SID_MASK);
1522 if (err)
1523 return err;
0d3b33e6 1524
a935c052
VD		 1525 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1526 if (err)
1527 return err;
0d3b33e6 1528
a935c052
VD		 1529 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1530 if (err)
1531 return err;
0d3b33e6 1532
a935c052 1533 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1534
a935c052
VD		 1535 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1536 if (err)
1537 return err;
0d3b33e6 1538
a935c052 1539 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1540
1541 if (next.valid) {
a935c052
VD		 1542 err = mv88e6xxx_stu_data_read(chip, &next);
1543 if (err)
1544 return err;
0d3b33e6
VD		 1545 }
1546
1547 *entry = next;
1548 return 0;
1549}
1550
fad09c73 1551static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
0d3b33e6
VD		 1552 struct mv88e6xxx_vtu_stu_entry *entry)
1553{
1554 u16 reg = 0;
a935c052 1555 int err;
0d3b33e6 1556
a935c052
VD		 1557 err = _mv88e6xxx_vtu_wait(chip);
1558 if (err)
1559 return err;
0d3b33e6
VD		 1560
1561 if (!entry->valid)
1562 goto loadpurge;
1563
1564 /* Write port states */
a935c052
VD		 1565 err = mv88e6xxx_stu_data_write(chip, entry);
1566 if (err)
1567 return err;
0d3b33e6
VD		 1568
1569 reg = GLOBAL_VTU_VID_VALID;
1570loadpurge:
a935c052
VD		 1571 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1572 if (err)
1573 return err;
0d3b33e6
VD		 1574
1575 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1576 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1577 if (err)
1578 return err;
0d3b33e6 1579
fad09c73 1580 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1581}
1582
fad09c73 1583static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1584 u16 *new, u16 *old)
2db9ce1f 1585{
fad09c73 1586 struct dsa_switch *ds = chip->ds;
f74df0be 1587 u16 upper_mask;
2db9ce1f 1588 u16 fid;
0e7b9925
AL		 1589 u16 reg;
1590 int err;
2db9ce1f 1591
fad09c73 1592 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1593 upper_mask = 0xff;
fad09c73 1594 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1595 upper_mask = 0xf;
f74df0be
VD		 1596 else
1597 return -EOPNOTSUPP;
1598
2db9ce1f 1599 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
0e7b9925
AL		 1600 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1601 if (err)
1602 return err;
2db9ce1f 1603
0e7b9925 1604 fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
2db9ce1f
VD		 1605
1606 if (new) {
0e7b9925
AL		 1607 reg &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1608 reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
2db9ce1f 1609
0e7b9925
AL		 1610 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1611 if (err)
1612 return err;
2db9ce1f
VD		 1613 }
1614
1615 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
0e7b9925
AL		 1616 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
1617 if (err)
1618 return err;
2db9ce1f 1619
0e7b9925 1620 fid |= (reg & upper_mask) << 4;
2db9ce1f
VD		 1621
1622 if (new) {
0e7b9925
AL		 1623 reg &= ~upper_mask;
1624 reg |= (*new >> 4) & upper_mask;
2db9ce1f 1625
0e7b9925
AL		 1626 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
1627 if (err)
1628 return err;
2db9ce1f 1629
c8b09808
AL		 1630 netdev_dbg(ds->ports[port].netdev,
1631 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1632 }
1633
1634 if (old)
1635 *old = fid;
1636
1637 return 0;
1638}
1639
fad09c73 1640static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1641 int port, u16 *fid)
2db9ce1f 1642{
fad09c73 1643 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1644}
1645
fad09c73 1646static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1647 int port, u16 fid)
2db9ce1f 1648{
fad09c73 1649 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1650}
1651
fad09c73 1652static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1653{
1654 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1655 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1656 int i, err;
3285f9e8
VD		 1657
1658 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1659
2db9ce1f 1660 /* Set every FID bit used by the (un)bridged ports */
fad09c73
VD		 1661 for (i = 0; i < chip->info->num_ports; ++i) {
1662 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1663 if (err)
1664 return err;
1665
1666 set_bit(*fid, fid_bitmap);
1667 }
1668
3285f9e8 1669 /* Set every FID bit used by the VLAN entries */
fad09c73 1670 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1671 if (err)
1672 return err;
1673
1674 do {
fad09c73 1675 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1676 if (err)
1677 return err;
1678
1679 if (!vlan.valid)
1680 break;
1681
1682 set_bit(vlan.fid, fid_bitmap);
1683 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1684
1685 /* The reset value 0x000 is used to indicate that multiple address
1686 * databases are not needed. Return the next positive available.
1687 */
1688 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1689 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1690 return -ENOSPC;
1691
1692 /* Clear the database */
fad09c73 1693 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1694}
1695
fad09c73 1696static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09 1697 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1698{
fad09c73 1699 struct dsa_switch *ds = chip->ds;
0d3b33e6
VD		 1700 struct mv88e6xxx_vtu_stu_entry vlan = {
1701 .valid = true,
1702 .vid = vid,
1703 };
3285f9e8
VD		 1704 int i, err;
1705
fad09c73 1706 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1707 if (err)
1708 return err;
0d3b33e6 1709
3d131f07 1710 /* exclude all ports except the CPU and DSA ports */
fad09c73 1711 for (i = 0; i < chip->info->num_ports; ++i)
3d131f07
VD		 1712 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1713 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1714 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1715
fad09c73
VD		 1716 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1717 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
0d3b33e6 1718 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1719
1720 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1721 * implemented, only one STU entry is needed to cover all VTU
1722 * entries. Thus, validate the SID 0.
1723 */
1724 vlan.sid = 0;
fad09c73 1725 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1726 if (err)
1727 return err;
1728
1729 if (vstp.sid != vlan.sid || !vstp.valid) {
1730 memset(&vstp, 0, sizeof(vstp));
1731 vstp.valid = true;
1732 vstp.sid = vlan.sid;
1733
fad09c73 1734 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1735 if (err)
1736 return err;
1737 }
0d3b33e6
VD		 1738 }
1739
1740 *entry = vlan;
1741 return 0;
1742}
1743
fad09c73 1744static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09
VD		 1745 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1746{
1747 int err;
1748
1749 if (!vid)
1750 return -EINVAL;
1751
fad09c73 1752 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1753 if (err)
1754 return err;
1755
fad09c73 1756 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1757 if (err)
1758 return err;
1759
1760 if (entry->vid != vid || !entry->valid) {
1761 if (!creat)
1762 return -EOPNOTSUPP;
1763 /* -ENOENT would've been more appropriate, but switchdev expects
1764 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1765 */
1766
fad09c73 1767 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1768 }
1769
1770 return err;
1771}
1772
da9c359e
VD		 1773static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1774 u16 vid_begin, u16 vid_end)
1775{
04bed143 1776 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1777 struct mv88e6xxx_vtu_stu_entry vlan;
1778 int i, err;
1779
1780 if (!vid_begin)
1781 return -EOPNOTSUPP;
1782
fad09c73 1783 mutex_lock(&chip->reg_lock);
da9c359e 1784
fad09c73 1785 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1786 if (err)
1787 goto unlock;
1788
1789 do {
fad09c73 1790 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1791 if (err)
1792 goto unlock;
1793
1794 if (!vlan.valid)
1795 break;
1796
1797 if (vlan.vid > vid_end)
1798 break;
1799
fad09c73 1800 for (i = 0; i < chip->info->num_ports; ++i) {
da9c359e
VD		 1801 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1802 continue;
1803
1804 if (vlan.data[i] ==
1805 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1806 continue;
1807
fad09c73
VD		 1808 if (chip->ports[i].bridge_dev ==
1809 chip->ports[port].bridge_dev)
da9c359e
VD		 1810 break; /* same bridge, check next VLAN */
1811
c8b09808 1812 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1813 "hardware VLAN %d already used by %s\n",
1814 vlan.vid,
fad09c73 1815 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1816 err = -EOPNOTSUPP;
1817 goto unlock;
1818 }
1819 } while (vlan.vid < vid_end);
1820
1821unlock:
fad09c73 1822 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1823
1824 return err;
1825}
1826
214cdb99
VD		 1827static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1828 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1829 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1830 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1831 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1832};
1833
f81ec90f
VD		 1834static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1835 bool vlan_filtering)
214cdb99 1836{
04bed143 1837 struct mv88e6xxx_chip *chip = ds->priv;
214cdb99
VD		 1838 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1839 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925
AL		 1840 u16 reg;
1841 int err;
214cdb99 1842
fad09c73 1843 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1844 return -EOPNOTSUPP;
1845
fad09c73 1846 mutex_lock(&chip->reg_lock);
214cdb99 1847
0e7b9925
AL		 1848 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
1849 if (err)
214cdb99
VD		 1850 goto unlock;
1851
0e7b9925 1852 old = reg & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1853
5220ef1e 1854 if (new != old) {
0e7b9925
AL		 1855 reg &= ~PORT_CONTROL_2_8021Q_MASK;
1856 reg |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1857
0e7b9925
AL		 1858 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
1859 if (err)
5220ef1e
VD		 1860 goto unlock;
1861
c8b09808 1862 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 1863 mv88e6xxx_port_8021q_mode_names[new],
1864 mv88e6xxx_port_8021q_mode_names[old]);
1865 }
214cdb99 1866
0e7b9925 1867 err = 0;
214cdb99 1868unlock:
fad09c73 1869 mutex_unlock(&chip->reg_lock);
214cdb99 1870
0e7b9925 1871 return err;
214cdb99
VD		 1872}
1873
57d32310
VD		 1874static int
1875mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1876 const struct switchdev_obj_port_vlan *vlan,
1877 struct switchdev_trans *trans)
76e398a6 1878{
04bed143 1879 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1880 int err;
1881
fad09c73 1882 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1883 return -EOPNOTSUPP;
1884
da9c359e
VD		 1885 /* If the requested port doesn't belong to the same bridge as the VLAN
1886 * members, do not support it (yet) and fallback to software VLAN.
1887 */
1888 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1889 vlan->vid_end);
1890 if (err)
1891 return err;
1892
76e398a6
VD		 1893 /* We don't need any dynamic resource from the kernel (yet),
1894 * so skip the prepare phase.
1895 */
1896 return 0;
1897}
1898
fad09c73 1899static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1900 u16 vid, bool untagged)
0d3b33e6 1901{
0d3b33e6
VD		 1902 struct mv88e6xxx_vtu_stu_entry vlan;
1903 int err;
1904
fad09c73 1905 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1906 if (err)
76e398a6 1907 return err;
0d3b33e6 1908
0d3b33e6
VD		 1909 vlan.data[port] = untagged ?
1910 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1911 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1912
fad09c73 1913 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1914}
1915
f81ec90f
VD		 1916static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1917 const struct switchdev_obj_port_vlan *vlan,
1918 struct switchdev_trans *trans)
76e398a6 1919{
04bed143 1920 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1921 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1922 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1923 u16 vid;
76e398a6 1924
fad09c73 1925 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1926 return;
1927
fad09c73 1928 mutex_lock(&chip->reg_lock);
76e398a6 1929
4d5770b3 1930 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1931 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1932 netdev_err(ds->ports[port].netdev,
1933 "failed to add VLAN %d%c\n",
4d5770b3 1934 vid, untagged ? 'u' : 't');
76e398a6 1935
fad09c73 1936 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 1937 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1938 vlan->vid_end);
0d3b33e6 1939
fad09c73 1940 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1941}
1942
fad09c73 1943static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1944 int port, u16 vid)
7dad08d7 1945{
fad09c73 1946 struct dsa_switch *ds = chip->ds;
7dad08d7 1947 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1948 int i, err;
1949
fad09c73 1950 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1951 if (err)
76e398a6 1952 return err;
7dad08d7 1953
2fb5ef09
VD		 1954 /* Tell switchdev if this VLAN is handled in software */
1955 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1956 return -EOPNOTSUPP;
7dad08d7
VD		 1957
1958 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1959
1960 /* keep the VLAN unless all ports are excluded */
f02bdffc 1961 vlan.valid = false;
fad09c73 1962 for (i = 0; i < chip->info->num_ports; ++i) {
3d131f07 1963 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1964 continue;
1965
1966 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1967 vlan.valid = true;
7dad08d7
VD		 1968 break;
1969 }
1970 }
1971
fad09c73 1972 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1973 if (err)
1974 return err;
1975
fad09c73 1976 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1977}
1978
f81ec90f
VD		 1979static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1980 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1981{
04bed143 1982 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1983 u16 pvid, vid;
1984 int err = 0;
1985
fad09c73 1986 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1987 return -EOPNOTSUPP;
1988
fad09c73 1989 mutex_lock(&chip->reg_lock);
76e398a6 1990
fad09c73 1991 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 1992 if (err)
1993 goto unlock;
1994
76e398a6 1995 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1996 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1997 if (err)
1998 goto unlock;
1999
2000 if (vid == pvid) {
fad09c73 2001 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 2002 if (err)
2003 goto unlock;
2004 }
2005 }
2006
7dad08d7 2007unlock:
fad09c73 2008 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2009
2010 return err;
2011}
2012
fad09c73 2013static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2014 const unsigned char *addr)
defb05b9 2015{
a935c052 2016 int i, err;
defb05b9
GR		 2017
2018 for (i = 0; i < 3; i++) {
a935c052
VD		 2019 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2020 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2021 if (err)
2022 return err;
defb05b9
GR		 2023 }
2024
2025 return 0;
2026}
2027
fad09c73 2028static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2029 unsigned char *addr)
defb05b9 2030{
a935c052
VD		 2031 u16 val;
2032 int i, err;
defb05b9
GR		 2033
2034 for (i = 0; i < 3; i++) {
a935c052
VD		 2035 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2036 if (err)
2037 return err;
2038
2039 addr[i * 2] = val >> 8;
2040 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 2041 }
2042
2043 return 0;
2044}
2045
fad09c73 2046static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2047 struct mv88e6xxx_atu_entry *entry)
defb05b9 2048{
6630e236
VD		 2049 int ret;
2050
fad09c73 2051 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2052 if (ret < 0)
2053 return ret;
2054
fad09c73 2055 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2056 if (ret < 0)
2057 return ret;
2058
fad09c73 2059 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2060 if (ret < 0)
87820510
VD		 2061 return ret;
2062
fad09c73 2063 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2064}
87820510 2065
88472939
VD		 2066static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2067 struct mv88e6xxx_atu_entry *entry);
2068
2069static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2070 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2071{
2072 struct mv88e6xxx_atu_entry next;
2073 int err;
2074
2075 eth_broadcast_addr(next.mac);
2076
2077 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2078 if (err)
2079 return err;
2080
2081 do {
2082 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2083 if (err)
2084 return err;
2085
2086 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2087 break;
2088
2089 if (ether_addr_equal(next.mac, addr)) {
2090 *entry = next;
2091 return 0;
2092 }
2093 } while (!is_broadcast_ether_addr(next.mac));
2094
2095 memset(entry, 0, sizeof(*entry));
2096 entry->fid = fid;
2097 ether_addr_copy(entry->mac, addr);
2098
2099 return 0;
2100}
2101
83dabd1f
VD		 2102static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2103 const unsigned char *addr, u16 vid,
2104 u8 state)
fd231c82 2105{
3285f9e8 2106 struct mv88e6xxx_vtu_stu_entry vlan;
88472939 2107 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2108 int err;
2109
2db9ce1f
VD		 2110 /* Null VLAN ID corresponds to the port private database */
2111 if (vid == 0)
fad09c73 2112 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2113 else
fad09c73 2114 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2115 if (err)
2116 return err;
fd231c82 2117
88472939
VD		 2118 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2119 if (err)
2120 return err;
2121
2122 /* Purge the ATU entry only if no port is using it anymore */
2123 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2124 entry.portv_trunkid &= ~BIT(port);
2125 if (!entry.portv_trunkid)
2126 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2127 } else {
2128 entry.portv_trunkid |= BIT(port);
2129 entry.state = state;
fd231c82
VD		 2130 }
2131
fad09c73 2132 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2133}
2134
f81ec90f
VD		 2135static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2136 const struct switchdev_obj_port_fdb *fdb,
2137 struct switchdev_trans *trans)
146a3206
VD		 2138{
2139 /* We don't need any dynamic resource from the kernel (yet),
2140 * so skip the prepare phase.
2141 */
2142 return 0;
2143}
2144
f81ec90f
VD		 2145static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2146 const struct switchdev_obj_port_fdb *fdb,
2147 struct switchdev_trans *trans)
87820510 2148{
04bed143 2149 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2150
fad09c73 2151 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2152 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2153 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2154 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2155 mutex_unlock(&chip->reg_lock);
87820510
VD		 2156}
2157
f81ec90f
VD		 2158static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2159 const struct switchdev_obj_port_fdb *fdb)
87820510 2160{
04bed143 2161 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2162 int err;
87820510 2163
fad09c73 2164 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2165 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2166 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2167 mutex_unlock(&chip->reg_lock);
87820510 2168
83dabd1f 2169 return err;
87820510
VD		 2170}
2171
fad09c73 2172static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2173 struct mv88e6xxx_atu_entry *entry)
6630e236 2174{
1d194046 2175 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2176 u16 val;
2177 int err;
1d194046
VD		 2178
2179 next.fid = fid;
defb05b9 2180
a935c052
VD		 2181 err = _mv88e6xxx_atu_wait(chip);
2182 if (err)
2183 return err;
6630e236 2184
a935c052
VD		 2185 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2186 if (err)
2187 return err;
6630e236 2188
a935c052
VD		 2189 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2190 if (err)
2191 return err;
6630e236 2192
a935c052
VD		 2193 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2194 if (err)
2195 return err;
6630e236 2196
a935c052 2197 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2198 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2199 unsigned int mask, shift;
2200
a935c052 2201 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2202 next.trunk = true;
2203 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2204 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2205 } else {
2206 next.trunk = false;
2207 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2208 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2209 }
2210
a935c052 2211 next.portv_trunkid = (val & mask) >> shift;
1d194046 2212 }
cdf09697 2213
1d194046 2214 *entry = next;
cdf09697
DM		 2215 return 0;
2216}
2217
83dabd1f
VD		 2218static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2219 u16 fid, u16 vid, int port,
2220 struct switchdev_obj *obj,
2221 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2222{
2223 struct mv88e6xxx_atu_entry addr = {
2224 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2225 };
2226 int err;
2227
fad09c73 2228 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2229 if (err)
2230 return err;
2231
2232 do {
fad09c73 2233 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2234 if (err)
83dabd1f 2235 return err;
74b6ba0d
VD		 2236
2237 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2238 break;
2239
83dabd1f
VD		 2240 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2241 continue;
2242
2243 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2244 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2245
83dabd1f
VD		 2246 if (!is_unicast_ether_addr(addr.mac))
2247 continue;
2248
2249 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2250 fdb->vid = vid;
2251 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2252 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2253 fdb->ndm_state = NUD_NOARP;
2254 else
2255 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2256 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2257 struct switchdev_obj_port_mdb *mdb;
2258
2259 if (!is_multicast_ether_addr(addr.mac))
2260 continue;
2261
2262 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2263 mdb->vid = vid;
2264 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2265 } else {
2266 return -EOPNOTSUPP;
74b6ba0d 2267 }
83dabd1f
VD		 2268
2269 err = cb(obj);
2270 if (err)
2271 return err;
74b6ba0d
VD		 2272 } while (!is_broadcast_ether_addr(addr.mac));
2273
2274 return err;
2275}
2276
83dabd1f
VD		 2277static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2278 struct switchdev_obj *obj,
2279 int (*cb)(struct switchdev_obj *obj))
f33475bd 2280{
f33475bd
VD		 2281 struct mv88e6xxx_vtu_stu_entry vlan = {
2282 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2283 };
2db9ce1f 2284 u16 fid;
f33475bd
VD		 2285 int err;
2286
2db9ce1f 2287 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2288 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f 2289 if (err)
83dabd1f 2290 return err;
2db9ce1f 2291
83dabd1f 2292 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2293 if (err)
83dabd1f 2294 return err;
2db9ce1f 2295
74b6ba0d 2296 /* Dump VLANs' Filtering Information Databases */
fad09c73 2297 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2298 if (err)
83dabd1f 2299 return err;
f33475bd
VD		 2300
2301 do {
fad09c73 2302 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2303 if (err)
83dabd1f 2304 return err;
f33475bd
VD		 2305
2306 if (!vlan.valid)
2307 break;
2308
83dabd1f
VD		 2309 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2310 obj, cb);
f33475bd 2311 if (err)
83dabd1f 2312 return err;
f33475bd
VD		 2313 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2314
83dabd1f
VD		 2315 return err;
2316}
2317
2318static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2319 struct switchdev_obj_port_fdb *fdb,
2320 int (*cb)(struct switchdev_obj *obj))
2321{
04bed143 2322 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2323 int err;
2324
2325 mutex_lock(&chip->reg_lock);
2326 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2327 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2328
2329 return err;
2330}
2331
f81ec90f
VD		 2332static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2333 struct net_device *bridge)
e79a8bcb 2334{
04bed143 2335 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2336 int i, err = 0;
466dfa07 2337
fad09c73 2338 mutex_lock(&chip->reg_lock);
466dfa07 2339
b7666efe 2340 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2341 chip->ports[port].bridge_dev = bridge;
b7666efe 2342
fad09c73
VD		 2343 for (i = 0; i < chip->info->num_ports; ++i) {
2344 if (chip->ports[i].bridge_dev == bridge) {
2345 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2346 if (err)
2347 break;
2348 }
2349 }
2350
fad09c73 2351 mutex_unlock(&chip->reg_lock);
a6692754 2352
466dfa07 2353 return err;
e79a8bcb
VD		 2354}
2355
f81ec90f 2356static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2357{
04bed143 2358 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2359 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2360 int i;
466dfa07 2361
fad09c73 2362 mutex_lock(&chip->reg_lock);
466dfa07 2363
b7666efe 2364 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2365 chip->ports[port].bridge_dev = NULL;
b7666efe 2366
fad09c73
VD		 2367 for (i = 0; i < chip->info->num_ports; ++i)
2368 if (i == port || chip->ports[i].bridge_dev == bridge)
2369 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2370 netdev_warn(ds->ports[i].netdev,
2371 "failed to remap\n");
b7666efe 2372
fad09c73 2373 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2374}
2375
fad09c73 2376static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2377{
fad09c73 2378 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2379 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2380 struct gpio_desc *gpiod = chip->reset;
552238b5 2381 unsigned long timeout;
0e7b9925 2382 u16 reg;
a935c052 2383 int err;
552238b5
VD		 2384 int i;
2385
2386 /* Set all ports to the disabled state. */
fad09c73 2387 for (i = 0; i < chip->info->num_ports; i++) {
0e7b9925
AL		 2388 err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, &reg);
2389 if (err)
2390 return err;
552238b5 2391
0e7b9925
AL		 2392 err = mv88e6xxx_port_write(chip, i, PORT_CONTROL,
2393 reg & 0xfffc);
2394 if (err)
2395 return err;
552238b5
VD		 2396 }
2397
2398 /* Wait for transmit queues to drain. */
2399 usleep_range(2000, 4000);
2400
2401 /* If there is a gpio connected to the reset pin, toggle it */
2402 if (gpiod) {
2403 gpiod_set_value_cansleep(gpiod, 1);
2404 usleep_range(10000, 20000);
2405 gpiod_set_value_cansleep(gpiod, 0);
2406 usleep_range(10000, 20000);
2407 }
2408
2409 /* Reset the switch. Keep the PPU active if requested. The PPU
2410 * needs to be active to support indirect phy register access
2411 * through global registers 0x18 and 0x19.
2412 */
2413 if (ppu_active)
a935c052 2414 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
552238b5 2415 else
a935c052 2416 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
0e7b9925
AL		 2417 if (err)
2418 return err;
552238b5
VD		 2419
2420 /* Wait up to one second for reset to complete. */
2421 timeout = jiffies + 1 * HZ;
2422 while (time_before(jiffies, timeout)) {
a935c052
VD		 2423 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2424 if (err)
2425 return err;
552238b5 2426
a935c052 2427 if ((reg & is_reset) == is_reset)
552238b5
VD		 2428 break;
2429 usleep_range(1000, 2000);
2430 }
2431 if (time_after(jiffies, timeout))
0e7b9925 2432 err = -ETIMEDOUT;
552238b5 2433 else
0e7b9925 2434 err = 0;
552238b5 2435
0e7b9925 2436 return err;
552238b5
VD		 2437}
2438
09cb7dfd 2439static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2440{
09cb7dfd
VD		 2441 u16 val;
2442 int err;
13a7ebb3 2443
09cb7dfd
VD		 2444 /* Clear Power Down bit */
2445 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2446 if (err)
2447 return err;
13a7ebb3 2448
09cb7dfd
VD		 2449 if (val & BMCR_PDOWN) {
2450 val &= ~BMCR_PDOWN;
2451 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2452 }
2453
09cb7dfd 2454 return err;
13a7ebb3
PU		 2455}
2456
fad09c73 2457static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2458{
fad09c73 2459 struct dsa_switch *ds = chip->ds;
0e7b9925 2460 int err;
54d792f2 2461 u16 reg;
d827e88a 2462
fad09c73
VD		 2463 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2464 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2465 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2466 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2467 /* MAC Forcing register: don't force link, speed,
2468 * duplex or flow control state to any particular
2469 * values on physical ports, but force the CPU port
2470 * and all DSA ports to their maximum bandwidth and
2471 * full duplex.
2472 */
0e7b9925 2473 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
60045cbf 2474 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2475 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2476 reg |= PORT_PCS_CTRL_FORCE_LINK |
2477 PORT_PCS_CTRL_LINK_UP |
2478 PORT_PCS_CTRL_DUPLEX_FULL |
2479 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2480 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2481 reg |= PORT_PCS_CTRL_100;
2482 else
2483 reg |= PORT_PCS_CTRL_1000;
2484 } else {
2485 reg |= PORT_PCS_CTRL_UNFORCED;
2486 }
2487
0e7b9925
AL		 2488 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
2489 if (err)
2490 return err;
54d792f2
AL		 2491 }
2492
2493 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2494 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2495 * tunneling, determine priority by looking at 802.1p and IP
2496 * priority fields (IP prio has precedence), and set STP state
2497 * to Forwarding.
2498 *
2499 * If this is the CPU link, use DSA or EDSA tagging depending
2500 * on which tagging mode was configured.
2501 *
2502 * If this is a link to another switch, use DSA tagging mode.
2503 *
2504 * If this is the upstream port for this switch, enable
2505 * forwarding of unknown unicasts and multicasts.
2506 */
2507 reg = 0;
fad09c73
VD		 2508 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2509 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2510 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2511 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2512 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2513 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2514 PORT_CONTROL_STATE_FORWARDING;
2515 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2516 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2517 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2518 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2519 else
2520 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2521 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2522 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2523 }
6083ce71 2524 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2525 if (mv88e6xxx_6095_family(chip) ||
2526 mv88e6xxx_6185_family(chip))
6083ce71 2527 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2528 if (mv88e6xxx_6352_family(chip) ||
2529 mv88e6xxx_6351_family(chip) ||
2530 mv88e6xxx_6165_family(chip) ||
2531 mv88e6xxx_6097_family(chip) ||
2532 mv88e6xxx_6320_family(chip)) {
54d792f2 2533 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2534 }
2535
54d792f2
AL		 2536 if (port == dsa_upstream_port(ds))
2537 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2538 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2539 }
2540 if (reg) {
0e7b9925
AL		 2541 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2542 if (err)
2543 return err;
54d792f2
AL		 2544 }
2545
13a7ebb3
PU		 2546 /* If this port is connected to a SerDes, make sure the SerDes is not
2547 * powered down.
2548 */
09cb7dfd 2549 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2550 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2551 if (err)
2552 return err;
2553 reg &= PORT_STATUS_CMODE_MASK;
2554 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2555 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2556 (reg == PORT_STATUS_CMODE_SGMII)) {
2557 err = mv88e6xxx_serdes_power_on(chip);
2558 if (err < 0)
2559 return err;
13a7ebb3
PU		 2560 }
2561 }
2562
8efdda4a 2563 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2564 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2565 * untagged frames on this port, do a destination address lookup on all
2566 * received packets as usual, disable ARP mirroring and don't send a
2567 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2568 */
2569 reg = 0;
fad09c73
VD		 2570 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2571 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2572 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2573 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2574 reg = PORT_CONTROL_2_MAP_DA;
2575
fad09c73
VD		 2576 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2577 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2578 reg |= PORT_CONTROL_2_JUMBO_10240;
2579
fad09c73 2580 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2581 /* Set the upstream port this port should use */
2582 reg |= dsa_upstream_port(ds);
2583 /* enable forwarding of unknown multicast addresses to
2584 * the upstream port
2585 */
2586 if (port == dsa_upstream_port(ds))
2587 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2588 }
2589
46fbe5e5 2590 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2591
54d792f2 2592 if (reg) {
0e7b9925
AL		 2593 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2594 if (err)
2595 return err;
54d792f2
AL		 2596 }
2597
2598 /* Port Association Vector: when learning source addresses
2599 * of packets, add the address to the address database using
2600 * a port bitmap that has only the bit for this port set and
2601 * the other bits clear.
2602 */
4c7ea3c0 2603 reg = 1 << port;
996ecb82
VD		 2604 /* Disable learning for CPU port */
2605 if (dsa_is_cpu_port(ds, port))
65fa4027 2606 reg = 0;
4c7ea3c0 2607
0e7b9925
AL		 2608 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2609 if (err)
2610 return err;
54d792f2
AL		 2611
2612 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2613 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2614 if (err)
2615 return err;
54d792f2 2616
fad09c73
VD		 2617 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2618 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2619 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2620 /* Do not limit the period of time that this port can
2621 * be paused for by the remote end or the period of
2622 * time that this port can pause the remote end.
2623 */
0e7b9925
AL		 2624 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2625 if (err)
2626 return err;
54d792f2
AL		 2627
2628 /* Port ATU control: disable limiting the number of
2629 * address database entries that this port is allowed
2630 * to use.
2631 */
0e7b9925
AL		 2632 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2633 0x0000);
54d792f2
AL		 2634 /* Priority Override: disable DA, SA and VTU priority
2635 * override.
2636 */
0e7b9925
AL		 2637 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2638 0x0000);
2639 if (err)
2640 return err;
54d792f2
AL		 2641
2642 /* Port Ethertype: use the Ethertype DSA Ethertype
2643 * value.
2644 */
2bbb33be 2645 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
0e7b9925
AL		 2646 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2647 ETH_P_EDSA);
2648 if (err)
2649 return err;
2bbb33be
AL		 2650 }
2651
54d792f2
AL		 2652 /* Tag Remap: use an identity 802.1p prio -> switch
2653 * prio mapping.
2654 */
0e7b9925
AL		 2655 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2656 0x3210);
2657 if (err)
2658 return err;
54d792f2
AL		 2659
2660 /* Tag Remap 2: use an identity 802.1p prio -> switch
2661 * prio mapping.
2662 */
0e7b9925
AL		 2663 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2664 0x7654);
2665 if (err)
2666 return err;
54d792f2
AL		 2667 }
2668
1bc261fa 2669 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2670 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2671 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2672 mv88e6xxx_6320_family(chip)) {
0e7b9925
AL		 2673 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2674 0x0001);
2675 if (err)
2676 return err;
1bc261fa 2677 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
0e7b9925
AL		 2678 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2679 0x0000);
2680 if (err)
2681 return err;
54d792f2
AL		 2682 }
2683
366f0a0f
GR		 2684 /* Port Control 1: disable trunking, disable sending
2685 * learning messages to this port.
d827e88a 2686 */
0e7b9925
AL		 2687 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2688 if (err)
2689 return err;
d827e88a 2690
207afda1 2691 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2692 * database, and allow bidirectional communication between the
2693 * CPU and DSA port(s), and the other ports.
d827e88a 2694 */
0e7b9925
AL		 2695 err = _mv88e6xxx_port_fid_set(chip, port, 0);
2696 if (err)
2697 return err;
2db9ce1f 2698
0e7b9925
AL		 2699 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2700 if (err)
2701 return err;
d827e88a
GR		 2702
2703 /* Default VLAN ID and priority: don't set a default VLAN
2704 * ID, and set the default packet priority to zero.
2705 */
0e7b9925 2706 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2707}
2708
a935c052 2709int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2710{
2711 int err;
2712
a935c052 2713 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2714 if (err)
2715 return err;
2716
a935c052 2717 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2718 if (err)
2719 return err;
2720
a935c052
VD		 2721 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2722 if (err)
2723 return err;
2724
2725 return 0;
3b4caa1b
VD		 2726}
2727
acddbd21
VD		 2728static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2729 unsigned int msecs)
2730{
2731 const unsigned int coeff = chip->info->age_time_coeff;
2732 const unsigned int min = 0x01 * coeff;
2733 const unsigned int max = 0xff * coeff;
2734 u8 age_time;
2735 u16 val;
2736 int err;
2737
2738 if (msecs < min || msecs > max)
2739 return -ERANGE;
2740
2741 /* Round to nearest multiple of coeff */
2742 age_time = (msecs + coeff / 2) / coeff;
2743
a935c052 2744 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2745 if (err)
2746 return err;
2747
2748 /* AgeTime is 11:4 bits */
2749 val &= ~0xff0;
2750 val |= age_time << 4;
2751
a935c052 2752 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2753}
2754
2cfcd964
VD		 2755static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2756 unsigned int ageing_time)
2757{
04bed143 2758 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2759 int err;
2760
2761 mutex_lock(&chip->reg_lock);
2762 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2763 mutex_unlock(&chip->reg_lock);
2764
2765 return err;
2766}
2767
9729934c 2768static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2769{
fad09c73 2770 struct dsa_switch *ds = chip->ds;
b0745e87 2771 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2772 u16 reg;
552238b5 2773 int err;
54d792f2 2774
119477bd
VD		 2775 /* Enable the PHY Polling Unit if present, don't discard any packets,
2776 * and mask all interrupt sources.
2777 */
2778 reg = 0;
fad09c73
VD		 2779 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2780 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2781 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2782
a935c052 2783 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
119477bd
VD		 2784 if (err)
2785 return err;
2786
b0745e87
VD		 2787 /* Configure the upstream port, and configure it as the port to which
2788 * ingress and egress and ARP monitor frames are to be sent.
2789 */
2790 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2791 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2792 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
a935c052 2793 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
b0745e87
VD		 2794 if (err)
2795 return err;
2796
50484ff4 2797 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2798 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2799 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2800 (ds->index & 0x1f));
50484ff4
VD		 2801 if (err)
2802 return err;
2803
acddbd21
VD		 2804 /* Clear all the VTU and STU entries */
2805 err = _mv88e6xxx_vtu_stu_flush(chip);
2806 if (err < 0)
2807 return err;
2808
54d792f2
AL		 2809 /* Set the default address aging time to 5 minutes, and
2810 * enable address learn messages to be sent to all message
2811 * ports.
2812 */
a935c052
VD		 2813 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2814 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2815 if (err)
08a01261 2816 return err;
54d792f2 2817
acddbd21
VD		 2818 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2819 if (err)
9729934c
VD		 2820 return err;
2821
2822 /* Clear all ATU entries */
2823 err = _mv88e6xxx_atu_flush(chip, 0, true);
2824 if (err)
2825 return err;
2826
54d792f2 2827 /* Configure the IP ToS mapping registers. */
a935c052 2828 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2829 if (err)
08a01261 2830 return err;
a935c052 2831 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2832 if (err)
08a01261 2833 return err;
a935c052 2834 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2835 if (err)
08a01261 2836 return err;
a935c052 2837 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2838 if (err)
08a01261 2839 return err;
a935c052 2840 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2841 if (err)
08a01261 2842 return err;
a935c052 2843 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2844 if (err)
08a01261 2845 return err;
a935c052 2846 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2847 if (err)
08a01261 2848 return err;
a935c052 2849 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2850 if (err)
08a01261 2851 return err;
54d792f2
AL		 2852
2853 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2854 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2855 if (err)
08a01261 2856 return err;
54d792f2 2857
9729934c 2858 /* Clear the statistics counters for all ports */
a935c052
VD		 2859 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2860 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2861 if (err)
2862 return err;
2863
2864 /* Wait for the flush to complete. */
2865 err = _mv88e6xxx_stats_wait(chip);
2866 if (err)
2867 return err;
2868
2869 return 0;
2870}
2871
f81ec90f 2872static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2873{
04bed143 2874 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2875 int err;
a1a6a4d1
VD		 2876 int i;
2877
fad09c73
VD		 2878 chip->ds = ds;
2879 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2880
fad09c73 2881 mutex_lock(&chip->reg_lock);
08a01261 2882
fad09c73 2883 err = mv88e6xxx_switch_reset(chip);
08a01261
VD		 2884 if (err)
2885 goto unlock;
2886
9729934c
VD		 2887 /* Setup Switch Port Registers */
2888 for (i = 0; i < chip->info->num_ports; i++) {
2889 err = mv88e6xxx_setup_port(chip, i);
2890 if (err)
2891 goto unlock;
2892 }
2893
2894 /* Setup Switch Global 1 Registers */
2895 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2896 if (err)
2897 goto unlock;
2898
9729934c
VD		 2899 /* Setup Switch Global 2 Registers */
2900 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2901 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2902 if (err)
2903 goto unlock;
2904 }
08a01261 2905
6b17e864 2906unlock:
fad09c73 2907 mutex_unlock(&chip->reg_lock);
db687a56 2908
48ace4ef 2909 return err;
54d792f2
AL		 2910}
2911
3b4caa1b
VD		 2912static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2913{
04bed143 2914 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2915 int err;
2916
2917 mutex_lock(&chip->reg_lock);
2918
2919 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
2920 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
2921 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
2922 else
2923 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
2924
2925 mutex_unlock(&chip->reg_lock);
2926
2927 return err;
2928}
2929
e57e5e77 2930static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2931{
fad09c73 2932 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2933 u16 val;
2934 int err;
fd3a0ee4 2935
e57e5e77 2936 if (phy >= chip->info->num_ports)
158bc065 2937 return 0xffff;
fd3a0ee4 2938
fad09c73 2939 mutex_lock(&chip->reg_lock);
e57e5e77 2940 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2941 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2942
2943 return err ? err : val;
fd3a0ee4
AL		 2944}
2945
e57e5e77 2946static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2947{
fad09c73 2948 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2949 int err;
fd3a0ee4 2950
e57e5e77 2951 if (phy >= chip->info->num_ports)
158bc065 2952 return 0xffff;
fd3a0ee4 2953
fad09c73 2954 mutex_lock(&chip->reg_lock);
e57e5e77 2955 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2956 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2957
2958 return err;
fd3a0ee4
AL		 2959}
2960
fad09c73 2961static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2962 struct device_node *np)
2963{
2964 static int index;
2965 struct mii_bus *bus;
2966 int err;
2967
b516d453 2968 if (np)
fad09c73 2969 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2970
fad09c73 2971 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2972 if (!bus)
2973 return -ENOMEM;
2974
fad09c73 2975 bus->priv = (void *)chip;
b516d453
AL		 2976 if (np) {
2977 bus->name = np->full_name;
2978 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2979 } else {
2980 bus->name = "mv88e6xxx SMI";
2981 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2982 }
2983
2984 bus->read = mv88e6xxx_mdio_read;
2985 bus->write = mv88e6xxx_mdio_write;
fad09c73 2986 bus->parent = chip->dev;
b516d453 2987
fad09c73
VD		 2988 if (chip->mdio_np)
2989 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2990 else
2991 err = mdiobus_register(bus);
2992 if (err) {
fad09c73 2993 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 2994 goto out;
2995 }
fad09c73 2996 chip->mdio_bus = bus;
b516d453
AL		 2997
2998 return 0;
2999
3000out:
fad09c73
VD		 3001 if (chip->mdio_np)
3002 of_node_put(chip->mdio_np);
b516d453
AL		 3003
3004 return err;
3005}
3006
fad09c73 3007static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3008
3009{
fad09c73 3010 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3011
3012 mdiobus_unregister(bus);
3013
fad09c73
VD		 3014 if (chip->mdio_np)
3015 of_node_put(chip->mdio_np);
b516d453
AL		 3016}
3017
c22995c5
GR		 3018#ifdef CONFIG_NET_DSA_HWMON
3019
3020static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3021{
04bed143 3022 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 3023 u16 val;
c22995c5 3024 int ret;
c22995c5
GR		 3025
3026 *temp = 0;
3027
fad09c73 3028 mutex_lock(&chip->reg_lock);
c22995c5 3029
9c93829c 3030 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3031 if (ret < 0)
3032 goto error;
3033
3034 /* Enable temperature sensor */
9c93829c 3035 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3036 if (ret < 0)
3037 goto error;
3038
9c93829c 3039 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3040 if (ret < 0)
3041 goto error;
3042
3043 /* Wait for temperature to stabilize */
3044 usleep_range(10000, 12000);
3045
9c93829c
VD		 3046 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3047 if (ret < 0)
c22995c5 3048 goto error;
c22995c5
GR		 3049
3050 /* Disable temperature sensor */
9c93829c 3051 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3052 if (ret < 0)
3053 goto error;
3054
3055 *temp = ((val & 0x1f) - 5) * 5;
3056
3057error:
9c93829c 3058 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3059 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3060 return ret;
3061}
3062
3063static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3064{
04bed143 3065 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3066 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3067 u16 val;
c22995c5
GR		 3068 int ret;
3069
3070 *temp = 0;
3071
9c93829c
VD		 3072 mutex_lock(&chip->reg_lock);
3073 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3074 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3075 if (ret < 0)
3076 return ret;
3077
9c93829c 3078 *temp = (val & 0xff) - 25;
c22995c5
GR		 3079
3080 return 0;
3081}
3082
f81ec90f 3083static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3084{
04bed143 3085 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3086
fad09c73 3087 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3088 return -EOPNOTSUPP;
3089
fad09c73 3090 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3091 return mv88e63xx_get_temp(ds, temp);
3092
3093 return mv88e61xx_get_temp(ds, temp);
3094}
3095
f81ec90f 3096static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3097{
04bed143 3098 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3099 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3100 u16 val;
c22995c5
GR		 3101 int ret;
3102
fad09c73 3103 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3104 return -EOPNOTSUPP;
3105
3106 *temp = 0;
3107
9c93829c
VD		 3108 mutex_lock(&chip->reg_lock);
3109 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3110 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3111 if (ret < 0)
3112 return ret;
3113
9c93829c 3114 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3115
3116 return 0;
3117}
3118
f81ec90f 3119static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3120{
04bed143 3121 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3122 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3123 u16 val;
3124 int err;
c22995c5 3125
fad09c73 3126 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3127 return -EOPNOTSUPP;
3128
9c93829c
VD		 3129 mutex_lock(&chip->reg_lock);
3130 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3131 if (err)
3132 goto unlock;
c22995c5 3133 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3134 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3135 (val & 0xe0ff) | (temp << 8));
3136unlock:
3137 mutex_unlock(&chip->reg_lock);
3138
3139 return err;
c22995c5
GR		 3140}
3141
f81ec90f 3142static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3143{
04bed143 3144 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3145 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3146 u16 val;
c22995c5
GR		 3147 int ret;
3148
fad09c73 3149 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3150 return -EOPNOTSUPP;
3151
3152 *alarm = false;
3153
9c93829c
VD		 3154 mutex_lock(&chip->reg_lock);
3155 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3156 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3157 if (ret < 0)
3158 return ret;
3159
9c93829c 3160 *alarm = !!(val & 0x40);
c22995c5
GR		 3161
3162 return 0;
3163}
3164#endif /* CONFIG_NET_DSA_HWMON */
3165
855b1932
VD		 3166static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3167{
04bed143 3168 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3169
3170 return chip->eeprom_len;
3171}
3172
855b1932
VD		 3173static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3174 struct ethtool_eeprom *eeprom, u8 *data)
3175{
04bed143 3176 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3177 int err;
3178
3179 mutex_lock(&chip->reg_lock);
3180
3181 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
ec561276 3182 err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data);
855b1932
VD		 3183 else
3184 err = -EOPNOTSUPP;
3185
3186 mutex_unlock(&chip->reg_lock);
3187
3188 if (err)
3189 return err;
3190
3191 eeprom->magic = 0xc3ec4951;
3192
3193 return 0;
3194}
3195
855b1932
VD		 3196static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3197 struct ethtool_eeprom *eeprom, u8 *data)
3198{
04bed143 3199 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3200 int err;
3201
3202 if (eeprom->magic != 0xc3ec4951)
3203 return -EINVAL;
3204
3205 mutex_lock(&chip->reg_lock);
3206
3207 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
ec561276 3208 err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data);
855b1932
VD		 3209 else
3210 err = -EOPNOTSUPP;
3211
3212 mutex_unlock(&chip->reg_lock);
3213
3214 return err;
3215}
3216
f81ec90f
VD		 3217static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3218 [MV88E6085] = {
3219 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3220 .family = MV88E6XXX_FAMILY_6097,
3221 .name = "Marvell 88E6085",
3222 .num_databases = 4096,
3223 .num_ports = 10,
9dddd478 3224 .port_base_addr = 0x10,
a935c052 3225 .global1_addr = 0x1b,
acddbd21 3226 .age_time_coeff = 15000,
f81ec90f
VD		 3227 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3228 },
3229
3230 [MV88E6095] = {
3231 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3232 .family = MV88E6XXX_FAMILY_6095,
3233 .name = "Marvell 88E6095/88E6095F",
3234 .num_databases = 256,
3235 .num_ports = 11,
9dddd478 3236 .port_base_addr = 0x10,
a935c052 3237 .global1_addr = 0x1b,
acddbd21 3238 .age_time_coeff = 15000,
f81ec90f
VD		 3239 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3240 },
3241
3242 [MV88E6123] = {
3243 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3244 .family = MV88E6XXX_FAMILY_6165,
3245 .name = "Marvell 88E6123",
3246 .num_databases = 4096,
3247 .num_ports = 3,
9dddd478 3248 .port_base_addr = 0x10,
a935c052 3249 .global1_addr = 0x1b,
acddbd21 3250 .age_time_coeff = 15000,
f81ec90f
VD		 3251 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3252 },
3253
3254 [MV88E6131] = {
3255 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3256 .family = MV88E6XXX_FAMILY_6185,
3257 .name = "Marvell 88E6131",
3258 .num_databases = 256,
3259 .num_ports = 8,
9dddd478 3260 .port_base_addr = 0x10,
a935c052 3261 .global1_addr = 0x1b,
acddbd21 3262 .age_time_coeff = 15000,
f81ec90f
VD		 3263 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3264 },
3265
3266 [MV88E6161] = {
3267 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3268 .family = MV88E6XXX_FAMILY_6165,
3269 .name = "Marvell 88E6161",
3270 .num_databases = 4096,
3271 .num_ports = 6,
9dddd478 3272 .port_base_addr = 0x10,
a935c052 3273 .global1_addr = 0x1b,
acddbd21 3274 .age_time_coeff = 15000,
f81ec90f
VD		 3275 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3276 },
3277
3278 [MV88E6165] = {
3279 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3280 .family = MV88E6XXX_FAMILY_6165,
3281 .name = "Marvell 88E6165",
3282 .num_databases = 4096,
3283 .num_ports = 6,
9dddd478 3284 .port_base_addr = 0x10,
a935c052 3285 .global1_addr = 0x1b,
acddbd21 3286 .age_time_coeff = 15000,
f81ec90f
VD		 3287 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3288 },
3289
3290 [MV88E6171] = {
3291 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3292 .family = MV88E6XXX_FAMILY_6351,
3293 .name = "Marvell 88E6171",
3294 .num_databases = 4096,
3295 .num_ports = 7,
9dddd478 3296 .port_base_addr = 0x10,
a935c052 3297 .global1_addr = 0x1b,
acddbd21 3298 .age_time_coeff = 15000,
f81ec90f
VD		 3299 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3300 },
3301
3302 [MV88E6172] = {
3303 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3304 .family = MV88E6XXX_FAMILY_6352,
3305 .name = "Marvell 88E6172",
3306 .num_databases = 4096,
3307 .num_ports = 7,
9dddd478 3308 .port_base_addr = 0x10,
a935c052 3309 .global1_addr = 0x1b,
acddbd21 3310 .age_time_coeff = 15000,
f81ec90f
VD		 3311 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3312 },
3313
3314 [MV88E6175] = {
3315 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3316 .family = MV88E6XXX_FAMILY_6351,
3317 .name = "Marvell 88E6175",
3318 .num_databases = 4096,
3319 .num_ports = 7,
9dddd478 3320 .port_base_addr = 0x10,
a935c052 3321 .global1_addr = 0x1b,
acddbd21 3322 .age_time_coeff = 15000,
f81ec90f
VD		 3323 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3324 },
3325
3326 [MV88E6176] = {
3327 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3328 .family = MV88E6XXX_FAMILY_6352,
3329 .name = "Marvell 88E6176",
3330 .num_databases = 4096,
3331 .num_ports = 7,
9dddd478 3332 .port_base_addr = 0x10,
a935c052 3333 .global1_addr = 0x1b,
acddbd21 3334 .age_time_coeff = 15000,
f81ec90f
VD		 3335 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3336 },
3337
3338 [MV88E6185] = {
3339 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3340 .family = MV88E6XXX_FAMILY_6185,
3341 .name = "Marvell 88E6185",
3342 .num_databases = 256,
3343 .num_ports = 10,
9dddd478 3344 .port_base_addr = 0x10,
a935c052 3345 .global1_addr = 0x1b,
acddbd21 3346 .age_time_coeff = 15000,
f81ec90f
VD		 3347 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3348 },
3349
3350 [MV88E6240] = {
3351 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3352 .family = MV88E6XXX_FAMILY_6352,
3353 .name = "Marvell 88E6240",
3354 .num_databases = 4096,
3355 .num_ports = 7,
9dddd478 3356 .port_base_addr = 0x10,
a935c052 3357 .global1_addr = 0x1b,
acddbd21 3358 .age_time_coeff = 15000,
f81ec90f
VD		 3359 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3360 },
3361
3362 [MV88E6320] = {
3363 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3364 .family = MV88E6XXX_FAMILY_6320,
3365 .name = "Marvell 88E6320",
3366 .num_databases = 4096,
3367 .num_ports = 7,
9dddd478 3368 .port_base_addr = 0x10,
a935c052 3369 .global1_addr = 0x1b,
acddbd21 3370 .age_time_coeff = 15000,
f81ec90f
VD		 3371 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3372 },
3373
3374 [MV88E6321] = {
3375 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3376 .family = MV88E6XXX_FAMILY_6320,
3377 .name = "Marvell 88E6321",
3378 .num_databases = 4096,
3379 .num_ports = 7,
9dddd478 3380 .port_base_addr = 0x10,
a935c052 3381 .global1_addr = 0x1b,
acddbd21 3382 .age_time_coeff = 15000,
f81ec90f
VD		 3383 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3384 },
3385
3386 [MV88E6350] = {
3387 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3388 .family = MV88E6XXX_FAMILY_6351,
3389 .name = "Marvell 88E6350",
3390 .num_databases = 4096,
3391 .num_ports = 7,
9dddd478 3392 .port_base_addr = 0x10,
a935c052 3393 .global1_addr = 0x1b,
acddbd21 3394 .age_time_coeff = 15000,
f81ec90f
VD		 3395 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3396 },
3397
3398 [MV88E6351] = {
3399 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3400 .family = MV88E6XXX_FAMILY_6351,
3401 .name = "Marvell 88E6351",
3402 .num_databases = 4096,
3403 .num_ports = 7,
9dddd478 3404 .port_base_addr = 0x10,
a935c052 3405 .global1_addr = 0x1b,
acddbd21 3406 .age_time_coeff = 15000,
f81ec90f
VD		 3407 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3408 },
3409
3410 [MV88E6352] = {
3411 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3412 .family = MV88E6XXX_FAMILY_6352,
3413 .name = "Marvell 88E6352",
3414 .num_databases = 4096,
3415 .num_ports = 7,
9dddd478 3416 .port_base_addr = 0x10,
a935c052 3417 .global1_addr = 0x1b,
acddbd21 3418 .age_time_coeff = 15000,
f81ec90f
VD		 3419 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3420 },
3421};
3422
5f7c0367 3423static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3424{
a439c061 3425 int i;
b9b37713 3426
5f7c0367
VD		 3427 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3428 if (mv88e6xxx_table[i].prod_num == prod_num)
3429 return &mv88e6xxx_table[i];
b9b37713 3430
b9b37713
VD		 3431 return NULL;
3432}
3433
fad09c73 3434static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3435{
3436 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3437 unsigned int prod_num, rev;
3438 u16 id;
3439 int err;
bc46a3d5 3440
8f6345b2
VD		 3441 mutex_lock(&chip->reg_lock);
3442 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3443 mutex_unlock(&chip->reg_lock);
3444 if (err)
3445 return err;
bc46a3d5
VD		 3446
3447 prod_num = (id & 0xfff0) >> 4;
3448 rev = id & 0x000f;
3449
3450 info = mv88e6xxx_lookup_info(prod_num);
3451 if (!info)
3452 return -ENODEV;
3453
caac8545 3454 /* Update the compatible info with the probed one */
fad09c73 3455 chip->info = info;
bc46a3d5 3456
ca070c10
VD		 3457 err = mv88e6xxx_g2_require(chip);
3458 if (err)
3459 return err;
3460
fad09c73
VD		 3461 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3462 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3463
3464 return 0;
3465}
3466
fad09c73 3467static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3468{
fad09c73 3469 struct mv88e6xxx_chip *chip;
469d729f 3470
fad09c73
VD		 3471 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3472 if (!chip)
469d729f
VD		 3473 return NULL;
3474
fad09c73 3475 chip->dev = dev;
469d729f 3476
fad09c73 3477 mutex_init(&chip->reg_lock);
469d729f 3478
fad09c73 3479 return chip;
469d729f
VD		 3480}
3481
ec561276
VD		 3482static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3483 .read = mv88e6xxx_g2_smi_phy_read,
3484 .write = mv88e6xxx_g2_smi_phy_write,
3485};
3486
e57e5e77
VD		 3487static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3488 .read = mv88e6xxx_read,
3489 .write = mv88e6xxx_write,
3490};
3491
3492static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3493{
3494 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3495 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3496 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3497 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3498 mv88e6xxx_ppu_state_init(chip);
3499 } else {
3500 chip->phy_ops = &mv88e6xxx_phy_ops;
3501 }
3502}
3503
930188ce
AL		 3504static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3505{
3506 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3507 mv88e6xxx_ppu_state_destroy(chip);
3508 }
3509}
3510
fad09c73 3511static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3512 struct mii_bus *bus, int sw_addr)
3513{
3514 /* ADDR[0] pin is unavailable externally and considered zero */
3515 if (sw_addr & 0x1)
3516 return -EINVAL;
3517
914b32f6 3518 if (sw_addr == 0)
fad09c73 3519 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3520 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3521 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3522 else
3523 return -EINVAL;
3524
fad09c73
VD		 3525 chip->bus = bus;
3526 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3527
3528 return 0;
3529}
3530
7b314362
AL		 3531static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3532{
04bed143 3533 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be
AL		 3534
3535 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3536 return DSA_TAG_PROTO_EDSA;
3537
3538 return DSA_TAG_PROTO_DSA;
7b314362
AL		 3539}
3540
fcdce7d0
AL		 3541static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3542 struct device *host_dev, int sw_addr,
3543 void **priv)
a77d43f1 3544{
fad09c73 3545 struct mv88e6xxx_chip *chip;
a439c061 3546 struct mii_bus *bus;
b516d453 3547 int err;
a77d43f1 3548
a439c061 3549 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3550 if (!bus)
3551 return NULL;
3552
fad09c73
VD		 3553 chip = mv88e6xxx_alloc_chip(dsa_dev);
3554 if (!chip)
469d729f
VD		 3555 return NULL;
3556
caac8545 3557 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3558 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3559
fad09c73 3560 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3561 if (err)
3562 goto free;
3563
fad09c73 3564 err = mv88e6xxx_detect(chip);
bc46a3d5 3565 if (err)
469d729f 3566 goto free;
a439c061 3567
e57e5e77
VD		 3568 mv88e6xxx_phy_init(chip);
3569
fad09c73 3570 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3571 if (err)
469d729f 3572 goto free;
b516d453 3573
fad09c73 3574 *priv = chip;
a439c061 3575
fad09c73 3576 return chip->info->name;
469d729f 3577free:
fad09c73 3578 devm_kfree(dsa_dev, chip);
469d729f
VD		 3579
3580 return NULL;
a77d43f1
AL		 3581}
3582
7df8fbdd
VD		 3583static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3584 const struct switchdev_obj_port_mdb *mdb,
3585 struct switchdev_trans *trans)
3586{
3587 /* We don't need any dynamic resource from the kernel (yet),
3588 * so skip the prepare phase.
3589 */
3590
3591 return 0;
3592}
3593
3594static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3595 const struct switchdev_obj_port_mdb *mdb,
3596 struct switchdev_trans *trans)
3597{
04bed143 3598 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3599
3600 mutex_lock(&chip->reg_lock);
3601 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3602 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3603 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3604 mutex_unlock(&chip->reg_lock);
3605}
3606
3607static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3608 const struct switchdev_obj_port_mdb *mdb)
3609{
04bed143 3610 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3611 int err;
3612
3613 mutex_lock(&chip->reg_lock);
3614 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3615 GLOBAL_ATU_DATA_STATE_UNUSED);
3616 mutex_unlock(&chip->reg_lock);
3617
3618 return err;
3619}
3620
3621static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3622 struct switchdev_obj_port_mdb *mdb,
3623 int (*cb)(struct switchdev_obj *obj))
3624{
04bed143 3625 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3626 int err;
3627
3628 mutex_lock(&chip->reg_lock);
3629 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3630 mutex_unlock(&chip->reg_lock);
3631
3632 return err;
3633}
3634
9d490b4e 3635static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3636 .probe = mv88e6xxx_drv_probe,
7b314362 3637 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3638 .setup = mv88e6xxx_setup,
3639 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3640 .adjust_link = mv88e6xxx_adjust_link,
3641 .get_strings = mv88e6xxx_get_strings,
3642 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3643 .get_sset_count = mv88e6xxx_get_sset_count,
3644 .set_eee = mv88e6xxx_set_eee,
3645 .get_eee = mv88e6xxx_get_eee,
3646#ifdef CONFIG_NET_DSA_HWMON
3647 .get_temp = mv88e6xxx_get_temp,
3648 .get_temp_limit = mv88e6xxx_get_temp_limit,
3649 .set_temp_limit = mv88e6xxx_set_temp_limit,
3650 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3651#endif
f8cd8753 3652 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3653 .get_eeprom = mv88e6xxx_get_eeprom,
3654 .set_eeprom = mv88e6xxx_set_eeprom,
3655 .get_regs_len = mv88e6xxx_get_regs_len,
3656 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3657 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3658 .port_bridge_join = mv88e6xxx_port_bridge_join,
3659 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3660 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3661 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3662 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3663 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3664 .port_vlan_add = mv88e6xxx_port_vlan_add,
3665 .port_vlan_del = mv88e6xxx_port_vlan_del,
3666 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3667 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3668 .port_fdb_add = mv88e6xxx_port_fdb_add,
3669 .port_fdb_del = mv88e6xxx_port_fdb_del,
3670 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3671 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3672 .port_mdb_add = mv88e6xxx_port_mdb_add,
3673 .port_mdb_del = mv88e6xxx_port_mdb_del,
3674 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 3675};
3676
fad09c73 3677static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3678 struct device_node *np)
3679{
fad09c73 3680 struct device *dev = chip->dev;
b7e66a5f
VD		 3681 struct dsa_switch *ds;
3682
3683 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3684 if (!ds)
3685 return -ENOMEM;
3686
3687 ds->dev = dev;
fad09c73 3688 ds->priv = chip;
9d490b4e 3689 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 3690
3691 dev_set_drvdata(dev, ds);
3692
3693 return dsa_register_switch(ds, np);
3694}
3695
fad09c73 3696static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3697{
fad09c73 3698 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3699}
3700
57d32310 3701static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3702{
14c7b3c3 3703 struct device *dev = &mdiodev->dev;
f8cd8753 3704 struct device_node *np = dev->of_node;
caac8545 3705 const struct mv88e6xxx_info *compat_info;
fad09c73 3706 struct mv88e6xxx_chip *chip;
f8cd8753 3707 u32 eeprom_len;
52638f71 3708 int err;
14c7b3c3 3709
caac8545
VD		 3710 compat_info = of_device_get_match_data(dev);
3711 if (!compat_info)
3712 return -EINVAL;
3713
fad09c73
VD		 3714 chip = mv88e6xxx_alloc_chip(dev);
3715 if (!chip)
14c7b3c3
AL		 3716 return -ENOMEM;
3717
fad09c73 3718 chip->info = compat_info;
caac8545 3719
fad09c73 3720 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3721 if (err)
3722 return err;
14c7b3c3 3723
fad09c73 3724 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3725 if (err)
3726 return err;
14c7b3c3 3727
e57e5e77
VD		 3728 mv88e6xxx_phy_init(chip);
3729
fad09c73
VD		 3730 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3731 if (IS_ERR(chip->reset))
3732 return PTR_ERR(chip->reset);
52638f71 3733
855b1932 3734 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
f8cd8753 3735 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3736 chip->eeprom_len = eeprom_len;
f8cd8753 3737
fad09c73 3738 err = mv88e6xxx_mdio_register(chip, np);
b516d453
AL		 3739 if (err)
3740 return err;
3741
fad09c73 3742 err = mv88e6xxx_register_switch(chip, np);
83c0afae 3743 if (err) {
fad09c73 3744 mv88e6xxx_mdio_unregister(chip);
83c0afae
AL		 3745 return err;
3746 }
3747
98e67308
BH		 3748 return 0;
3749}
14c7b3c3
AL		 3750
3751static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3752{
3753 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 3754 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 3755
930188ce 3756 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 3757 mv88e6xxx_unregister_switch(chip);
3758 mv88e6xxx_mdio_unregister(chip);
14c7b3c3
AL		 3759}
3760
3761static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 3762 {
3763 .compatible = "marvell,mv88e6085",
3764 .data = &mv88e6xxx_table[MV88E6085],
3765 },
14c7b3c3
AL		 3766 { /* sentinel */ },
3767};
3768
3769MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3770
3771static struct mdio_driver mv88e6xxx_driver = {
3772 .probe = mv88e6xxx_probe,
3773 .remove = mv88e6xxx_remove,
3774 .mdiodrv.driver = {
3775 .name = "mv88e6085",
3776 .of_match_table = mv88e6xxx_of_match,
3777 },
3778};
3779
3780static int __init mv88e6xxx_init(void)
3781{
9d490b4e 3782 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 3783 return mdio_driver_register(&mv88e6xxx_driver);
3784}
98e67308
BH		 3785module_init(mv88e6xxx_init);
3786
3787static void __exit mv88e6xxx_cleanup(void)
3788{
14c7b3c3 3789 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 3790 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 3791}
3792module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3793
3794MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3795MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3796MODULE_LICENSE("GPL");
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