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dsa: mv88e6xxx: Ensure all pending interrupts are handled prior to exit
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
ec561276 35
4d5f2ba7 36#include "chip.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
6d91782f 41#include "serdes.h"
91da11f8 42
fad09c73 43static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 44{
fad09c73
VD		 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 47 dump_stack();
48 }
49}
50
914b32f6
VD		 51/* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 *
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 *
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 61 */
914b32f6 62
fad09c73 63static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 *val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 val)
74{
fad09c73 75 if (!chip->smi_ops)
914b32f6
VD		 76 return -EOPNOTSUPP;
77
fad09c73 78 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 79}
80
fad09c73 81static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 82 int addr, int reg, u16 *val)
83{
84 int ret;
85
fad09c73 86 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 87 if (ret < 0)
88 return ret;
89
90 *val = ret & 0xffff;
91
92 return 0;
93}
94
fad09c73 95static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 96 int addr, int reg, u16 val)
97{
98 int ret;
99
fad09c73 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 101 if (ret < 0)
102 return ret;
103
104 return 0;
105}
106
c08026ab 107static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
110};
111
fad09c73 112static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 113{
114 int ret;
115 int i;
116
117 for (i = 0; i < 16; i++) {
fad09c73 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 119 if (ret < 0)
120 return ret;
121
cca8b133 122 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 123 return 0;
124 }
125
126 return -ETIMEDOUT;
127}
128
fad09c73 129static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 130 int addr, int reg, u16 *val)
91da11f8
LB		 131{
132 int ret;
133
3675c8d7 134 /* Wait for the bus to become free. */
fad09c73 135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the read command. */
fad09c73 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the read command to complete. */
fad09c73 146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 147 if (ret < 0)
148 return ret;
149
3675c8d7 150 /* Read the data. */
fad09c73 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 152 if (ret < 0)
153 return ret;
154
914b32f6 155 *val = ret & 0xffff;
91da11f8 156
914b32f6 157 return 0;
8d6d09e7
GR		 158}
159
fad09c73 160static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 161 int addr, int reg, u16 val)
91da11f8
LB		 162{
163 int ret;
164
3675c8d7 165 /* Wait for the bus to become free. */
fad09c73 166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 167 if (ret < 0)
168 return ret;
169
3675c8d7 170 /* Transmit the data to write. */
fad09c73 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Transmit the write command. */
fad09c73 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 178 if (ret < 0)
179 return ret;
180
3675c8d7 181 /* Wait for the write command to complete. */
fad09c73 182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 183 if (ret < 0)
184 return ret;
185
186 return 0;
187}
188
c08026ab 189static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
192};
193
ec561276 194int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 195{
196 int err;
197
fad09c73 198 assert_reg_lock(chip);
914b32f6 199
fad09c73 200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 201 if (err)
202 return err;
203
fad09c73 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 205 addr, reg, *val);
206
207 return 0;
208}
209
ec561276 210int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 211{
914b32f6
VD		 212 int err;
213
fad09c73 214 assert_reg_lock(chip);
91da11f8 215
fad09c73 216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 217 if (err)
218 return err;
219
fad09c73 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 221 addr, reg, val);
222
914b32f6
VD		 223 return 0;
224}
225
10fa5bfc 226struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 227{
228 struct mv88e6xxx_mdio_bus *mdio_bus;
229
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
231 list);
232 if (!mdio_bus)
233 return NULL;
234
235 return mdio_bus->bus;
236}
237
dc30c35b
AL		 238static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
239{
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
242
243 chip->g1_irq.masked |= (1 << n);
244}
245
246static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
247{
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
250
251 chip->g1_irq.masked &= ~(1 << n);
252}
253
254static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
255{
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
259 unsigned int n;
260 u16 reg;
f0b95e6b 261 u16 ctl1;
dc30c35b
AL		 262 int err;
263
264 mutex_lock(&chip->reg_lock);
82466921 265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b
AL		 266 mutex_unlock(&chip->reg_lock);
267
268 if (err)
269 goto out;
270
f0b95e6b
JDA		 271 do {
272 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
273 if (reg & (1 << n)) {
274 sub_irq = irq_find_mapping(chip->g1_irq.domain,
275 n);
276 handle_nested_irq(sub_irq);
277 ++nhandled;
278 }
dc30c35b 279 }
f0b95e6b
JDA		 280
281 mutex_lock(&chip->reg_lock);
282 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
283 if (err)
284 goto unlock;
285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
286unlock:
287 mutex_unlock(&chip->reg_lock);
288 if (err)
289 goto out;
290 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
291 } while (reg & ctl1);
292
dc30c35b
AL		 293out:
294 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
295}
296
297static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
298{
299 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
300
301 mutex_lock(&chip->reg_lock);
302}
303
304static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
305{
306 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
307 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
308 u16 reg;
309 int err;
310
d77f4321 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 312 if (err)
313 goto out;
314
315 reg &= ~mask;
316 reg |= (~chip->g1_irq.masked & mask);
317
d77f4321 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 319 if (err)
320 goto out;
321
322out:
323 mutex_unlock(&chip->reg_lock);
324}
325
6eb15e21 326static const struct irq_chip mv88e6xxx_g1_irq_chip = {
dc30c35b
AL		 327 .name = "mv88e6xxx-g1",
328 .irq_mask = mv88e6xxx_g1_irq_mask,
329 .irq_unmask = mv88e6xxx_g1_irq_unmask,
330 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
331 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
332};
333
334static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
335 unsigned int irq,
336 irq_hw_number_t hwirq)
337{
338 struct mv88e6xxx_chip *chip = d->host_data;
339
340 irq_set_chip_data(irq, d->host_data);
341 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
342 irq_set_noprobe(irq);
343
344 return 0;
345}
346
347static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
348 .map = mv88e6xxx_g1_irq_domain_map,
349 .xlate = irq_domain_xlate_twocell,
350};
351
352static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
353{
354 int irq, virq;
3460a577
AL		 355 u16 mask;
356
d77f4321 357 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3d5fdba1 358 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 359 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577
AL		 360
361 free_irq(chip->irq, chip);
dc30c35b 362
5edef2f2 363 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 364 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 365 irq_dispose_mapping(virq);
366 }
367
a3db3d3a 368 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 369}
370
371static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
372{
3dd0ef05
AL		 373 int err, irq, virq;
374 u16 reg, mask;
dc30c35b
AL		 375
376 chip->g1_irq.nirqs = chip->info->g1_irqs;
377 chip->g1_irq.domain = irq_domain_add_simple(
378 NULL, chip->g1_irq.nirqs, 0,
379 &mv88e6xxx_g1_irq_domain_ops, chip);
380 if (!chip->g1_irq.domain)
381 return -ENOMEM;
382
383 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
384 irq_create_mapping(chip->g1_irq.domain, irq);
385
386 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
387 chip->g1_irq.masked = ~0;
388
d77f4321 389 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 390 if (err)
3dd0ef05 391 goto out_mapping;
dc30c35b 392
3dd0ef05 393 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 394
d77f4321 395 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 396 if (err)
3dd0ef05 397 goto out_disable;
dc30c35b
AL		 398
399 /* Reading the interrupt status clears (most of) them */
82466921 400 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 401 if (err)
3dd0ef05 402 goto out_disable;
dc30c35b
AL		 403
404 err = request_threaded_irq(chip->irq, NULL,
405 mv88e6xxx_g1_irq_thread_fn,
406 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
407 dev_name(chip->dev), chip);
408 if (err)
3dd0ef05 409 goto out_disable;
dc30c35b
AL		 410
411 return 0;
412
3dd0ef05 413out_disable:
3d5fdba1 414 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 415 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 416
417out_mapping:
418 for (irq = 0; irq < 16; irq++) {
419 virq = irq_find_mapping(chip->g1_irq.domain, irq);
420 irq_dispose_mapping(virq);
421 }
422
423 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 424
425 return err;
426}
427
ec561276 428int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 429{
6441e669 430 int i;
2d79af6e 431
6441e669 432 for (i = 0; i < 16; i++) {
2d79af6e
VD		 433 u16 val;
434 int err;
435
436 err = mv88e6xxx_read(chip, addr, reg, &val);
437 if (err)
438 return err;
439
440 if (!(val & mask))
441 return 0;
442
443 usleep_range(1000, 2000);
444 }
445
30853553 446 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 447 return -ETIMEDOUT;
448}
449
f22ab641 450/* Indirect write to single pointer-data register with an Update bit */
ec561276 451int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 452{
453 u16 val;
0f02b4f7 454 int err;
f22ab641
VD		 455
456 /* Wait until the previous operation is completed */
0f02b4f7
AL		 457 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
458 if (err)
459 return err;
f22ab641
VD		 460
461 /* Set the Update bit to trigger a write operation */
462 val = BIT(15) | update;
463
464 return mv88e6xxx_write(chip, addr, reg, val);
465}
466
d78343d2
VD		 467static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
468 int link, int speed, int duplex,
469 phy_interface_t mode)
470{
471 int err;
472
473 if (!chip->info->ops->port_set_link)
474 return 0;
475
476 /* Port's MAC control must not be changed unless the link is down */
477 err = chip->info->ops->port_set_link(chip, port, 0);
478 if (err)
479 return err;
480
481 if (chip->info->ops->port_set_speed) {
482 err = chip->info->ops->port_set_speed(chip, port, speed);
483 if (err && err != -EOPNOTSUPP)
484 goto restore_link;
485 }
486
487 if (chip->info->ops->port_set_duplex) {
488 err = chip->info->ops->port_set_duplex(chip, port, duplex);
489 if (err && err != -EOPNOTSUPP)
490 goto restore_link;
491 }
492
493 if (chip->info->ops->port_set_rgmii_delay) {
494 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
495 if (err && err != -EOPNOTSUPP)
496 goto restore_link;
497 }
498
f39908d3
AL		 499 if (chip->info->ops->port_set_cmode) {
500 err = chip->info->ops->port_set_cmode(chip, port, mode);
501 if (err && err != -EOPNOTSUPP)
502 goto restore_link;
503 }
504
d78343d2
VD		 505 err = 0;
506restore_link:
507 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 508 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 509
510 return err;
511}
512
dea87024
AL		 513/* We expect the switch to perform auto negotiation if there is a real
514 * phy. However, in the case of a fixed link phy, we force the port
515 * settings from the fixed link settings.
516 */
f81ec90f
VD		 517static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
518 struct phy_device *phydev)
dea87024 519{
04bed143 520 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 521 int err;
dea87024
AL		 522
523 if (!phy_is_pseudo_fixed_link(phydev))
524 return;
525
fad09c73 526 mutex_lock(&chip->reg_lock);
d78343d2
VD		 527 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
528 phydev->duplex, phydev->interface);
fad09c73 529 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 530
531 if (err && err != -EOPNOTSUPP)
774439e5 532 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
dea87024
AL		 533}
534
a605a0fe 535static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 536{
a605a0fe
AL		 537 if (!chip->info->ops->stats_snapshot)
538 return -EOPNOTSUPP;
91da11f8 539
a605a0fe 540 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 541}
542
e413e7e1 543static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 544 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
545 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
546 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
547 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
548 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
549 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
550 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
551 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
552 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
553 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
554 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
555 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
556 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
557 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
558 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
559 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
560 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
561 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
562 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
563 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
564 { "single", 4, 0x14, STATS_TYPE_BANK0, },
565 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
566 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
567 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
568 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
569 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
570 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
571 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
572 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
573 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
574 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
575 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
576 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
577 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
578 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
579 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
580 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
581 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
582 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
583 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
584 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
585 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
586 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
587 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
588 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
589 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
590 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
591 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
592 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
593 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
594 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
595 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
596 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
597 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
598 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
599 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
600 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
601 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
602 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 603};
604
fad09c73 605static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 606 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 607 int port, u16 bank1_select,
608 u16 histogram)
80c4627b 609{
80c4627b
AL		 610 u32 low;
611 u32 high = 0;
dfafe449 612 u16 reg = 0;
0e7b9925 613 int err;
80c4627b
AL		 614 u64 value;
615
f5e2ed02 616 switch (s->type) {
dfafe449 617 case STATS_TYPE_PORT:
0e7b9925
AL		 618 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
619 if (err)
80c4627b
AL		 620 return UINT64_MAX;
621
0e7b9925 622 low = reg;
80c4627b 623 if (s->sizeof_stat == 4) {
0e7b9925
AL		 624 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
625 if (err)
80c4627b 626 return UINT64_MAX;
0e7b9925 627 high = reg;
80c4627b 628 }
f5e2ed02 629 break;
dfafe449 630 case STATS_TYPE_BANK1:
e0d8b615 631 reg = bank1_select;
dfafe449
AL		 632 /* fall through */
633 case STATS_TYPE_BANK0:
e0d8b615 634 reg |= s->reg | histogram;
7f9ef3af 635 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 636 if (s->sizeof_stat == 8)
7f9ef3af 637 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 638 break;
639 default:
640 return UINT64_MAX;
80c4627b
AL		 641 }
642 value = (((u64)high) << 16) | low;
643 return value;
644}
645
dfafe449
AL		 646static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
647 uint8_t *data, int types)
91da11f8 648{
f5e2ed02
AL		 649 struct mv88e6xxx_hw_stat *stat;
650 int i, j;
91da11f8 651
f5e2ed02
AL		 652 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
653 stat = &mv88e6xxx_hw_stats[i];
dfafe449 654 if (stat->type & types) {
f5e2ed02
AL		 655 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
656 ETH_GSTRING_LEN);
657 j++;
658 }
91da11f8 659 }
e413e7e1
AL		 660}
661
dfafe449
AL		 662static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
663 uint8_t *data)
664{
665 mv88e6xxx_stats_get_strings(chip, data,
666 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
667}
668
669static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
670 uint8_t *data)
671{
672 mv88e6xxx_stats_get_strings(chip, data,
673 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
674}
675
676static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
677 uint8_t *data)
e413e7e1 678{
04bed143 679 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 680
681 if (chip->info->ops->stats_get_strings)
682 chip->info->ops->stats_get_strings(chip, data);
683}
684
685static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
686 int types)
687{
f5e2ed02
AL		 688 struct mv88e6xxx_hw_stat *stat;
689 int i, j;
690
691 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
692 stat = &mv88e6xxx_hw_stats[i];
dfafe449 693 if (stat->type & types)
f5e2ed02
AL		 694 j++;
695 }
696 return j;
e413e7e1
AL		 697}
698
dfafe449
AL		 699static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
700{
701 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
702 STATS_TYPE_PORT);
703}
704
705static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
706{
707 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
708 STATS_TYPE_BANK1);
709}
710
711static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
712{
713 struct mv88e6xxx_chip *chip = ds->priv;
714
715 if (chip->info->ops->stats_get_sset_count)
716 return chip->info->ops->stats_get_sset_count(chip);
717
718 return 0;
719}
720
052f947f 721static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 722 uint64_t *data, int types,
723 u16 bank1_select, u16 histogram)
052f947f
AL		 724{
725 struct mv88e6xxx_hw_stat *stat;
726 int i, j;
727
728 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
729 stat = &mv88e6xxx_hw_stats[i];
730 if (stat->type & types) {
e0d8b615
AL		 731 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
732 bank1_select,
733 histogram);
052f947f
AL		 734 j++;
735 }
736 }
737}
738
739static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
740 uint64_t *data)
741{
742 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 743 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 744 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 745}
746
747static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
748 uint64_t *data)
749{
750 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 751 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 752 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
753 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 754}
755
756static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
757 uint64_t *data)
758{
759 return mv88e6xxx_stats_get_stats(chip, port, data,
760 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 761 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
762 0);
052f947f
AL		 763}
764
765static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
766 uint64_t *data)
767{
768 if (chip->info->ops->stats_get_stats)
769 chip->info->ops->stats_get_stats(chip, port, data);
770}
771
f81ec90f
VD		 772static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
773 uint64_t *data)
e413e7e1 774{
04bed143 775 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 776 int ret;
f5e2ed02 777
fad09c73 778 mutex_lock(&chip->reg_lock);
f5e2ed02 779
a605a0fe 780 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 781 if (ret < 0) {
fad09c73 782 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 783 return;
784 }
052f947f
AL		 785
786 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 787
fad09c73 788 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 789}
790
de227387
AL		 791static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
792{
793 if (chip->info->ops->stats_set_histogram)
794 return chip->info->ops->stats_set_histogram(chip);
795
796 return 0;
797}
798
f81ec90f 799static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 800{
801 return 32 * sizeof(u16);
802}
803
f81ec90f
VD		 804static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
805 struct ethtool_regs *regs, void *_p)
a1ab91f3 806{
04bed143 807 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 808 int err;
809 u16 reg;
a1ab91f3
GR		 810 u16 *p = _p;
811 int i;
812
813 regs->version = 0;
814
815 memset(p, 0xff, 32 * sizeof(u16));
816
fad09c73 817 mutex_lock(&chip->reg_lock);
23062513 818
a1ab91f3 819 for (i = 0; i < 32; i++) {
a1ab91f3 820
0e7b9925
AL		 821 err = mv88e6xxx_port_read(chip, port, i, &reg);
822 if (!err)
823 p[i] = reg;
a1ab91f3 824 }
23062513 825
fad09c73 826 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 827}
828
08f50061
VD		 829static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
830 struct ethtool_eee *e)
68b8f60c 831{
5480db69
VD		 832 /* Nothing to do on the port's MAC */
833 return 0;
11b3b45d
GR		 834}
835
08f50061
VD		 836static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
837 struct ethtool_eee *e)
11b3b45d 838{
5480db69
VD		 839 /* Nothing to do on the port's MAC */
840 return 0;
11b3b45d
GR		 841}
842
e5887a2a 843static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 844{
e5887a2a
VD		 845 struct dsa_switch *ds = NULL;
846 struct net_device *br;
847 u16 pvlan;
b7666efe
VD		 848 int i;
849
e5887a2a
VD		 850 if (dev < DSA_MAX_SWITCHES)
851 ds = chip->ds->dst->ds[dev];
852
853 /* Prevent frames from unknown switch or port */
854 if (!ds || port >= ds->num_ports)
855 return 0;
856
857 /* Frames from DSA links and CPU ports can egress any local port */
858 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
859 return mv88e6xxx_port_mask(chip);
860
861 br = ds->ports[port].bridge_dev;
862 pvlan = 0;
863
864 /* Frames from user ports can egress any local DSA links and CPU ports,
865 * as well as any local member of their bridge group.
866 */
867 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
868 if (dsa_is_cpu_port(chip->ds, i) ||
869 dsa_is_dsa_port(chip->ds, i) ||
c8652c83 870 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
e5887a2a
VD		 871 pvlan |= BIT(i);
872
873 return pvlan;
874}
875
240ea3ef 876static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 877{
878 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 879
880 /* prevent frames from going back out of the port they came in on */
881 output_ports &= ~BIT(port);
facd95b2 882
5a7921f4 883 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 884}
885
f81ec90f
VD		 886static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
887 u8 state)
facd95b2 888{
04bed143 889 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 890 int err;
facd95b2 891
fad09c73 892 mutex_lock(&chip->reg_lock);
f894c29c 893 err = mv88e6xxx_port_set_state(chip, port, state);
fad09c73 894 mutex_unlock(&chip->reg_lock);
553eb544
VD		 895
896 if (err)
774439e5 897 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 898}
899
9e907d73
VD		 900static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
901{
902 if (chip->info->ops->pot_clear)
903 return chip->info->ops->pot_clear(chip);
904
905 return 0;
906}
907
51c901a7
VD		 908static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
909{
910 if (chip->info->ops->mgmt_rsvd2cpu)
911 return chip->info->ops->mgmt_rsvd2cpu(chip);
912
913 return 0;
914}
915
a2ac29d2
VD		 916static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
917{
c3a7d4ad
VD		 918 int err;
919
daefc943
VD		 920 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
921 if (err)
922 return err;
923
c3a7d4ad
VD		 924 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
925 if (err)
926 return err;
927
a2ac29d2
VD		 928 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
929}
930
cd8da8bb
VD		 931static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
932{
933 int port;
934 int err;
935
936 if (!chip->info->ops->irl_init_all)
937 return 0;
938
939 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
940 /* Disable ingress rate limiting by resetting all per port
941 * ingress rate limit resources to their initial state.
942 */
943 err = chip->info->ops->irl_init_all(chip, port);
944 if (err)
945 return err;
946 }
947
948 return 0;
949}
950
04a69a17
VD		 951static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
952{
953 if (chip->info->ops->set_switch_mac) {
954 u8 addr[ETH_ALEN];
955
956 eth_random_addr(addr);
957
958 return chip->info->ops->set_switch_mac(chip, addr);
959 }
960
961 return 0;
962}
963
17a1594e
VD		 964static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
965{
966 u16 pvlan = 0;
967
968 if (!mv88e6xxx_has_pvt(chip))
969 return -EOPNOTSUPP;
970
971 /* Skip the local source device, which uses in-chip port VLAN */
972 if (dev != chip->ds->index)
aec5ac88 973 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 974
975 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
976}
977
81228996
VD		 978static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
979{
17a1594e
VD		 980 int dev, port;
981 int err;
982
81228996
VD		 983 if (!mv88e6xxx_has_pvt(chip))
984 return 0;
985
986 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
987 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
988 */
17a1594e
VD		 989 err = mv88e6xxx_g2_misc_4_bit_port(chip);
990 if (err)
991 return err;
992
993 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
994 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
995 err = mv88e6xxx_pvt_map(chip, dev, port);
996 if (err)
997 return err;
998 }
999 }
1000
1001 return 0;
81228996
VD		 1002}
1003
749efcb8
VD		 1004static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1005{
1006 struct mv88e6xxx_chip *chip = ds->priv;
1007 int err;
1008
1009 mutex_lock(&chip->reg_lock);
e606ca36 1010 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1011 mutex_unlock(&chip->reg_lock);
1012
1013 if (err)
774439e5 1014 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 1015}
1016
b486d7c9
VD		 1017static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1018{
1019 if (!chip->info->max_vid)
1020 return 0;
1021
1022 return mv88e6xxx_g1_vtu_flush(chip);
1023}
1024
f1394b78
VD		 1025static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1026 struct mv88e6xxx_vtu_entry *entry)
1027{
1028 if (!chip->info->ops->vtu_getnext)
1029 return -EOPNOTSUPP;
1030
1031 return chip->info->ops->vtu_getnext(chip, entry);
1032}
1033
0ad5daf6
VD		 1034static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1035 struct mv88e6xxx_vtu_entry *entry)
1036{
1037 if (!chip->info->ops->vtu_loadpurge)
1038 return -EOPNOTSUPP;
1039
1040 return chip->info->ops->vtu_loadpurge(chip, entry);
1041}
1042
d7f435f9 1043static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1044{
1045 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
3afb4bde
VD		 1046 struct mv88e6xxx_vtu_entry vlan = {
1047 .vid = chip->info->max_vid,
1048 };
2db9ce1f 1049 int i, err;
3285f9e8
VD		 1050
1051 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1052
2db9ce1f 1053 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1054 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1055 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1056 if (err)
1057 return err;
1058
1059 set_bit(*fid, fid_bitmap);
1060 }
1061
3285f9e8 1062 /* Set every FID bit used by the VLAN entries */
3285f9e8 1063 do {
f1394b78 1064 err = mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1065 if (err)
1066 return err;
1067
1068 if (!vlan.valid)
1069 break;
1070
1071 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1072 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1073
1074 /* The reset value 0x000 is used to indicate that multiple address
1075 * databases are not needed. Return the next positive available.
1076 */
1077 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1078 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1079 return -ENOSPC;
1080
1081 /* Clear the database */
daefc943 1082 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1083}
1084
567aa59a
VD		 1085static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1086 struct mv88e6xxx_vtu_entry *entry, bool new)
2fb5ef09
VD		 1087{
1088 int err;
1089
1090 if (!vid)
1091 return -EINVAL;
1092
3afb4bde
VD		 1093 entry->vid = vid - 1;
1094 entry->valid = false;
2fb5ef09 1095
f1394b78 1096 err = mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1097 if (err)
1098 return err;
1099
567aa59a
VD		 1100 if (entry->vid == vid && entry->valid)
1101 return 0;
2fb5ef09 1102
567aa59a
VD		 1103 if (new) {
1104 int i;
1105
1106 /* Initialize a fresh VLAN entry */
1107 memset(entry, 0, sizeof(*entry));
1108 entry->valid = true;
1109 entry->vid = vid;
1110
553a768d 1111 /* Exclude all ports */
567aa59a 1112 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
553a768d 1113 entry->member[i] =
7ec60d6e 1114 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
567aa59a
VD		 1115
1116 return mv88e6xxx_atu_new(chip, &entry->fid);
2fb5ef09
VD		 1117 }
1118
567aa59a
VD		 1119 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1120 return -EOPNOTSUPP;
2fb5ef09
VD		 1121}
1122
da9c359e
VD		 1123static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1124 u16 vid_begin, u16 vid_end)
1125{
04bed143 1126 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1127 struct mv88e6xxx_vtu_entry vlan = {
1128 .vid = vid_begin - 1,
1129 };
da9c359e
VD		 1130 int i, err;
1131
db06ae41
AL		 1132 /* DSA and CPU ports have to be members of multiple vlans */
1133 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1134 return 0;
1135
da9c359e
VD		 1136 if (!vid_begin)
1137 return -EOPNOTSUPP;
1138
fad09c73 1139 mutex_lock(&chip->reg_lock);
da9c359e 1140
da9c359e 1141 do {
f1394b78 1142 err = mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1143 if (err)
1144 goto unlock;
1145
1146 if (!vlan.valid)
1147 break;
1148
1149 if (vlan.vid > vid_end)
1150 break;
1151
370b4ffb 1152 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1153 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1154 continue;
1155
cd886469 1156 if (!ds->ports[i].slave)
66e2809d
AL		 1157 continue;
1158
bd00e053 1159 if (vlan.member[i] ==
7ec60d6e 1160 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
da9c359e
VD		 1161 continue;
1162
c8652c83 1163 if (dsa_to_port(ds, i)->bridge_dev ==
fae8a25e 1164 ds->ports[port].bridge_dev)
da9c359e
VD		 1165 break; /* same bridge, check next VLAN */
1166
c8652c83 1167 if (!dsa_to_port(ds, i)->bridge_dev)
66e2809d
AL		 1168 continue;
1169
743fcc28
AL		 1170 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1171 port, vlan.vid, i,
c8652c83 1172 netdev_name(dsa_to_port(ds, i)->bridge_dev));
da9c359e
VD		 1173 err = -EOPNOTSUPP;
1174 goto unlock;
1175 }
1176 } while (vlan.vid < vid_end);
1177
1178unlock:
fad09c73 1179 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1180
1181 return err;
1182}
1183
f81ec90f
VD		 1184static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1185 bool vlan_filtering)
214cdb99 1186{
04bed143 1187 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1188 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1189 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1190 int err;
214cdb99 1191
3cf3c846 1192 if (!chip->info->max_vid)
54d77b5b
VD		 1193 return -EOPNOTSUPP;
1194
fad09c73 1195 mutex_lock(&chip->reg_lock);
385a0995 1196 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1197 mutex_unlock(&chip->reg_lock);
214cdb99 1198
0e7b9925 1199 return err;
214cdb99
VD		 1200}
1201
57d32310
VD		 1202static int
1203mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1204 const struct switchdev_obj_port_vlan *vlan,
1205 struct switchdev_trans *trans)
76e398a6 1206{
04bed143 1207 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1208 int err;
1209
3cf3c846 1210 if (!chip->info->max_vid)
54d77b5b
VD		 1211 return -EOPNOTSUPP;
1212
da9c359e
VD		 1213 /* If the requested port doesn't belong to the same bridge as the VLAN
1214 * members, do not support it (yet) and fallback to software VLAN.
1215 */
1216 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1217 vlan->vid_end);
1218 if (err)
1219 return err;
1220
76e398a6
VD		 1221 /* We don't need any dynamic resource from the kernel (yet),
1222 * so skip the prepare phase.
1223 */
1224 return 0;
1225}
1226
a4c93ae1
AL		 1227static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1228 const unsigned char *addr, u16 vid,
1229 u8 state)
1230{
1231 struct mv88e6xxx_vtu_entry vlan;
1232 struct mv88e6xxx_atu_entry entry;
1233 int err;
1234
1235 /* Null VLAN ID corresponds to the port private database */
1236 if (vid == 0)
1237 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1238 else
1239 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1240 if (err)
1241 return err;
1242
1243 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1244 ether_addr_copy(entry.mac, addr);
1245 eth_addr_dec(entry.mac);
1246
1247 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1248 if (err)
1249 return err;
1250
1251 /* Initialize a fresh ATU entry if it isn't found */
1252 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1253 !ether_addr_equal(entry.mac, addr)) {
1254 memset(&entry, 0, sizeof(entry));
1255 ether_addr_copy(entry.mac, addr);
1256 }
1257
1258 /* Purge the ATU entry only if no port is using it anymore */
1259 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1260 entry.portvec &= ~BIT(port);
1261 if (!entry.portvec)
1262 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1263 } else {
1264 entry.portvec |= BIT(port);
1265 entry.state = state;
1266 }
1267
1268 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1269}
1270
87fa886e
AL		 1271static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1272 u16 vid)
1273{
1274 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1275 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1276
1277 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1278}
1279
1280static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1281{
1282 int port;
1283 int err;
1284
1285 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1286 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1287 if (err)
1288 return err;
1289 }
1290
1291 return 0;
1292}
1293
fad09c73 1294static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
c91498e1 1295 u16 vid, u8 member)
0d3b33e6 1296{
b4e47c0f 1297 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1298 int err;
1299
567aa59a 1300 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1301 if (err)
76e398a6 1302 return err;
0d3b33e6 1303
c91498e1 1304 vlan.member[port] = member;
0d3b33e6 1305
87fa886e
AL		 1306 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1307 if (err)
1308 return err;
1309
1310 return mv88e6xxx_broadcast_setup(chip, vid);
76e398a6
VD		 1311}
1312
f81ec90f
VD		 1313static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1314 const struct switchdev_obj_port_vlan *vlan,
1315 struct switchdev_trans *trans)
76e398a6 1316{
04bed143 1317 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1318 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1319 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
c91498e1 1320 u8 member;
76e398a6 1321 u16 vid;
76e398a6 1322
3cf3c846 1323 if (!chip->info->max_vid)
54d77b5b
VD		 1324 return;
1325
c91498e1 1326 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 1327 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 1328 else if (untagged)
7ec60d6e 1329 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 1330 else
7ec60d6e 1331 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 1332
fad09c73 1333 mutex_lock(&chip->reg_lock);
76e398a6 1334
4d5770b3 1335 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
c91498e1 1336 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
774439e5
VD		 1337 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1338 vid, untagged ? 'u' : 't');
76e398a6 1339
77064f37 1340 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
774439e5
VD		 1341 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1342 vlan->vid_end);
0d3b33e6 1343
fad09c73 1344 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1345}
1346
fad09c73 1347static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1348 int port, u16 vid)
7dad08d7 1349{
b4e47c0f 1350 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1351 int i, err;
1352
567aa59a 1353 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1354 if (err)
76e398a6 1355 return err;
7dad08d7 1356
2fb5ef09 1357 /* Tell switchdev if this VLAN is handled in software */
7ec60d6e 1358 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1359 return -EOPNOTSUPP;
7dad08d7 1360
7ec60d6e 1361 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1362
1363 /* keep the VLAN unless all ports are excluded */
f02bdffc 1364 vlan.valid = false;
370b4ffb 1365 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 1366 if (vlan.member[i] !=
1367 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1368 vlan.valid = true;
7dad08d7
VD		 1369 break;
1370 }
1371 }
1372
0ad5daf6 1373 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1374 if (err)
1375 return err;
1376
e606ca36 1377 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1378}
1379
f81ec90f
VD		 1380static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1381 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1382{
04bed143 1383 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1384 u16 pvid, vid;
1385 int err = 0;
1386
3cf3c846 1387 if (!chip->info->max_vid)
54d77b5b
VD		 1388 return -EOPNOTSUPP;
1389
fad09c73 1390 mutex_lock(&chip->reg_lock);
76e398a6 1391
77064f37 1392 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1393 if (err)
1394 goto unlock;
1395
76e398a6 1396 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1397 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1398 if (err)
1399 goto unlock;
1400
1401 if (vid == pvid) {
77064f37 1402 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1403 if (err)
1404 goto unlock;
1405 }
1406 }
1407
7dad08d7 1408unlock:
fad09c73 1409 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1410
1411 return err;
1412}
1413
1b6dd556
AS		 1414static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1415 const unsigned char *addr, u16 vid)
87820510 1416{
04bed143 1417 struct mv88e6xxx_chip *chip = ds->priv;
1b6dd556 1418 int err;
87820510 1419
fad09c73 1420 mutex_lock(&chip->reg_lock);
1b6dd556
AS		 1421 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1422 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
fad09c73 1423 mutex_unlock(&chip->reg_lock);
1b6dd556
AS		 1424
1425 return err;
87820510
VD		 1426}
1427
f81ec90f 1428static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1429 const unsigned char *addr, u16 vid)
87820510 1430{
04bed143 1431 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1432 int err;
87820510 1433
fad09c73 1434 mutex_lock(&chip->reg_lock);
6c2c1dcb 1435 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
27c0e600 1436 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
fad09c73 1437 mutex_unlock(&chip->reg_lock);
87820510 1438
83dabd1f 1439 return err;
87820510
VD		 1440}
1441
83dabd1f
VD		 1442static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1443 u16 fid, u16 vid, int port,
2bedde1a 1444 dsa_fdb_dump_cb_t *cb, void *data)
74b6ba0d 1445{
dabc1a96 1446 struct mv88e6xxx_atu_entry addr;
2bedde1a 1447 bool is_static;
74b6ba0d
VD		 1448 int err;
1449
27c0e600 1450 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96 1451 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1452
1453 do {
dabc1a96 1454 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1455 if (err)
83dabd1f 1456 return err;
74b6ba0d 1457
27c0e600 1458 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
74b6ba0d
VD		 1459 break;
1460
01bd96c8 1461 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1462 continue;
1463
2bedde1a
AS		 1464 if (!is_unicast_ether_addr(addr.mac))
1465 continue;
83dabd1f 1466
2bedde1a
AS		 1467 is_static = (addr.state ==
1468 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1469 err = cb(addr.mac, vid, is_static, data);
83dabd1f
VD		 1470 if (err)
1471 return err;
74b6ba0d
VD		 1472 } while (!is_broadcast_ether_addr(addr.mac));
1473
1474 return err;
1475}
1476
83dabd1f 1477static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2bedde1a 1478 dsa_fdb_dump_cb_t *cb, void *data)
f33475bd 1479{
b4e47c0f 1480 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 1481 .vid = chip->info->max_vid,
f33475bd 1482 };
2db9ce1f 1483 u16 fid;
f33475bd
VD		 1484 int err;
1485
2db9ce1f 1486 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 1487 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 1488 if (err)
83dabd1f 1489 return err;
2db9ce1f 1490
2bedde1a 1491 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2db9ce1f 1492 if (err)
83dabd1f 1493 return err;
2db9ce1f 1494
74b6ba0d 1495 /* Dump VLANs' Filtering Information Databases */
f33475bd 1496 do {
f1394b78 1497 err = mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 1498 if (err)
83dabd1f 1499 return err;
f33475bd
VD		 1500
1501 if (!vlan.valid)
1502 break;
1503
83dabd1f 1504 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2bedde1a 1505 cb, data);
f33475bd 1506 if (err)
83dabd1f 1507 return err;
3cf3c846 1508 } while (vlan.vid < chip->info->max_vid);
f33475bd 1509
83dabd1f
VD		 1510 return err;
1511}
1512
1513static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1514 dsa_fdb_dump_cb_t *cb, void *data)
83dabd1f 1515{
04bed143 1516 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 1517 int err;
1518
1519 mutex_lock(&chip->reg_lock);
2bedde1a 1520 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
fad09c73 1521 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 1522
1523 return err;
1524}
1525
240ea3ef
VD		 1526static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1527 struct net_device *br)
e79a8bcb 1528{
e96a6e02 1529 struct dsa_switch *ds;
240ea3ef 1530 int port;
e96a6e02 1531 int dev;
240ea3ef 1532 int err;
466dfa07 1533
240ea3ef
VD		 1534 /* Remap the Port VLAN of each local bridge group member */
1535 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1536 if (chip->ds->ports[port].bridge_dev == br) {
1537 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 1538 if (err)
240ea3ef 1539 return err;
b7666efe
VD		 1540 }
1541 }
1542
e96a6e02
VD		 1543 if (!mv88e6xxx_has_pvt(chip))
1544 return 0;
1545
1546 /* Remap the Port VLAN of each cross-chip bridge group member */
1547 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1548 ds = chip->ds->dst->ds[dev];
1549 if (!ds)
1550 break;
1551
1552 for (port = 0; port < ds->num_ports; ++port) {
1553 if (ds->ports[port].bridge_dev == br) {
1554 err = mv88e6xxx_pvt_map(chip, dev, port);
1555 if (err)
1556 return err;
1557 }
1558 }
1559 }
1560
240ea3ef
VD		 1561 return 0;
1562}
1563
1564static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1565 struct net_device *br)
1566{
1567 struct mv88e6xxx_chip *chip = ds->priv;
1568 int err;
1569
1570 mutex_lock(&chip->reg_lock);
1571 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 1572 mutex_unlock(&chip->reg_lock);
a6692754 1573
466dfa07 1574 return err;
e79a8bcb
VD		 1575}
1576
f123f2fb
VD		 1577static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1578 struct net_device *br)
66d9cd0f 1579{
04bed143 1580 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 1581
fad09c73 1582 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 1583 if (mv88e6xxx_bridge_map(chip, br) ||
1584 mv88e6xxx_port_vlan_map(chip, port))
1585 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 1586 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 1587}
1588
aec5ac88
VD		 1589static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1590 int port, struct net_device *br)
1591{
1592 struct mv88e6xxx_chip *chip = ds->priv;
1593 int err;
1594
1595 if (!mv88e6xxx_has_pvt(chip))
1596 return 0;
1597
1598 mutex_lock(&chip->reg_lock);
1599 err = mv88e6xxx_pvt_map(chip, dev, port);
1600 mutex_unlock(&chip->reg_lock);
1601
1602 return err;
1603}
1604
1605static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1606 int port, struct net_device *br)
1607{
1608 struct mv88e6xxx_chip *chip = ds->priv;
1609
1610 if (!mv88e6xxx_has_pvt(chip))
1611 return;
1612
1613 mutex_lock(&chip->reg_lock);
1614 if (mv88e6xxx_pvt_map(chip, dev, port))
1615 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1616 mutex_unlock(&chip->reg_lock);
1617}
1618
17e708ba
VD		 1619static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1620{
1621 if (chip->info->ops->reset)
1622 return chip->info->ops->reset(chip);
1623
1624 return 0;
1625}
1626
309eca6d
VD		 1627static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1628{
1629 struct gpio_desc *gpiod = chip->reset;
1630
1631 /* If there is a GPIO connected to the reset pin, toggle it */
1632 if (gpiod) {
1633 gpiod_set_value_cansleep(gpiod, 1);
1634 usleep_range(10000, 20000);
1635 gpiod_set_value_cansleep(gpiod, 0);
1636 usleep_range(10000, 20000);
1637 }
1638}
1639
4ac4b5a6 1640static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 1641{
4ac4b5a6 1642 int i, err;
552238b5 1643
4ac4b5a6 1644 /* Set all ports to the Disabled state */
370b4ffb 1645 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 1646 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 1647 if (err)
1648 return err;
552238b5
VD		 1649 }
1650
4ac4b5a6
VD		 1651 /* Wait for transmit queues to drain,
1652 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1653 */
552238b5
VD		 1654 usleep_range(2000, 4000);
1655
4ac4b5a6
VD		 1656 return 0;
1657}
1658
1659static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1660{
4ac4b5a6
VD		 1661 int err;
1662
1663 err = mv88e6xxx_disable_ports(chip);
1664 if (err)
1665 return err;
1666
309eca6d 1667 mv88e6xxx_hardware_reset(chip);
552238b5 1668
17e708ba 1669 return mv88e6xxx_software_reset(chip);
552238b5
VD		 1670}
1671
4314557c 1672static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 1673 enum mv88e6xxx_frame_mode frame,
1674 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 1675{
1676 int err;
1677
4314557c
VD		 1678 if (!chip->info->ops->port_set_frame_mode)
1679 return -EOPNOTSUPP;
1680
1681 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 1682 if (err)
1683 return err;
1684
4314557c
VD		 1685 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1686 if (err)
1687 return err;
1688
1689 if (chip->info->ops->port_set_ether_type)
1690 return chip->info->ops->port_set_ether_type(chip, port, etype);
1691
1692 return 0;
56995cbc
AL		 1693}
1694
4314557c 1695static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 1696{
4314557c 1697 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 1698 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1699 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1700}
56995cbc 1701
4314557c
VD		 1702static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1703{
1704 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 1705 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1706 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1707}
56995cbc 1708
4314557c
VD		 1709static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1710{
1711 return mv88e6xxx_set_port_mode(chip, port,
1712 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 1713 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1714 ETH_P_EDSA);
4314557c 1715}
56995cbc 1716
4314557c
VD		 1717static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1718{
1719 if (dsa_is_dsa_port(chip->ds, port))
1720 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1721
2b3e9891 1722 if (dsa_is_user_port(chip->ds, port))
4314557c 1723 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 1724
4314557c
VD		 1725 /* Setup CPU port mode depending on its supported tag format */
1726 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1727 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1728
4314557c
VD		 1729 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1730 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 1731
4314557c 1732 return -EINVAL;
56995cbc
AL		 1733}
1734
601aeed3 1735static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 1736{
601aeed3 1737 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 1738
601aeed3 1739 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 1740}
56995cbc 1741
601aeed3 1742static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 1743{
601aeed3 1744 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 1745
601aeed3
VD		 1746 /* Upstream ports flood frames with unknown unicast or multicast DA */
1747 if (chip->info->ops->port_set_egress_floods)
1748 return chip->info->ops->port_set_egress_floods(chip, port,
1749 flood, flood);
ea698f4f 1750
601aeed3 1751 return 0;
ea698f4f
VD		 1752}
1753
6d91782f
AL		 1754static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1755 bool on)
1756{
523a8904
VD		 1757 if (chip->info->ops->serdes_power)
1758 return chip->info->ops->serdes_power(chip, port, on);
04aca993 1759
523a8904 1760 return 0;
6d91782f
AL		 1761}
1762
fad09c73 1763static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 1764{
fad09c73 1765 struct dsa_switch *ds = chip->ds;
0e7b9925 1766 int err;
54d792f2 1767 u16 reg;
d827e88a 1768
d78343d2
VD		 1769 /* MAC Forcing register: don't force link, speed, duplex or flow control
1770 * state to any particular values on physical ports, but force the CPU
1771 * port and all DSA ports to their maximum bandwidth and full duplex.
1772 */
1773 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1774 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1775 SPEED_MAX, DUPLEX_FULL,
1776 PHY_INTERFACE_MODE_NA);
1777 else
1778 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1779 SPEED_UNFORCED, DUPLEX_UNFORCED,
1780 PHY_INTERFACE_MODE_NA);
1781 if (err)
1782 return err;
54d792f2
AL		 1783
1784 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1785 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1786 * tunneling, determine priority by looking at 802.1p and IP
1787 * priority fields (IP prio has precedence), and set STP state
1788 * to Forwarding.
1789 *
1790 * If this is the CPU link, use DSA or EDSA tagging depending
1791 * on which tagging mode was configured.
1792 *
1793 * If this is a link to another switch, use DSA tagging mode.
1794 *
1795 * If this is the upstream port for this switch, enable
1796 * forwarding of unknown unicasts and multicasts.
1797 */
a89b433b
VD		 1798 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1799 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1800 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1801 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 1802 if (err)
1803 return err;
6083ce71 1804
601aeed3 1805 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 1806 if (err)
1807 return err;
54d792f2 1808
601aeed3 1809 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 1810 if (err)
1811 return err;
1812
04aca993
AL		 1813 /* Enable the SERDES interface for DSA and CPU ports. Normal
1814 * ports SERDES are enabled when the port is enabled, thus
1815 * saving a bit of power.
13a7ebb3 1816 */
04aca993
AL		 1817 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1818 err = mv88e6xxx_serdes_power(chip, port, true);
1819 if (err)
1820 return err;
1821 }
13a7ebb3 1822
8efdda4a 1823 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 1824 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 1825 * untagged frames on this port, do a destination address lookup on all
1826 * received packets as usual, disable ARP mirroring and don't send a
1827 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 1828 */
a23b2961
AL		 1829 err = mv88e6xxx_port_set_map_da(chip, port);
1830 if (err)
1831 return err;
8efdda4a 1832
a23b2961
AL		 1833 reg = 0;
1834 if (chip->info->ops->port_set_upstream_port) {
1835 err = chip->info->ops->port_set_upstream_port(
1836 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 1837 if (err)
1838 return err;
54d792f2
AL		 1839 }
1840
a23b2961 1841 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 1842 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 1843 if (err)
1844 return err;
1845
cd782656
VD		 1846 if (chip->info->ops->port_set_jumbo_size) {
1847 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 1848 if (err)
1849 return err;
1850 }
1851
54d792f2
AL		 1852 /* Port Association Vector: when learning source addresses
1853 * of packets, add the address to the address database using
1854 * a port bitmap that has only the bit for this port set and
1855 * the other bits clear.
1856 */
4c7ea3c0 1857 reg = 1 << port;
996ecb82
VD		 1858 /* Disable learning for CPU port */
1859 if (dsa_is_cpu_port(ds, port))
65fa4027 1860 reg = 0;
4c7ea3c0 1861
2a4614e4
VD		 1862 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1863 reg);
0e7b9925
AL		 1864 if (err)
1865 return err;
54d792f2
AL		 1866
1867 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 1868 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1869 0x0000);
0e7b9925
AL		 1870 if (err)
1871 return err;
54d792f2 1872
0898432c
VD		 1873 if (chip->info->ops->port_pause_limit) {
1874 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 1875 if (err)
1876 return err;
b35d322a 1877 }
54d792f2 1878
c8c94891
VD		 1879 if (chip->info->ops->port_disable_learn_limit) {
1880 err = chip->info->ops->port_disable_learn_limit(chip, port);
1881 if (err)
1882 return err;
1883 }
1884
9dbfb4e1
VD		 1885 if (chip->info->ops->port_disable_pri_override) {
1886 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 1887 if (err)
1888 return err;
ef0a7318 1889 }
2bbb33be 1890
ef0a7318
AL		 1891 if (chip->info->ops->port_tag_remap) {
1892 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 1893 if (err)
1894 return err;
54d792f2
AL		 1895 }
1896
ef70b111
AL		 1897 if (chip->info->ops->port_egress_rate_limiting) {
1898 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 1899 if (err)
1900 return err;
54d792f2
AL		 1901 }
1902
ea698f4f 1903 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 1904 if (err)
1905 return err;
d827e88a 1906
207afda1 1907 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 1908 * database, and allow bidirectional communication between the
1909 * CPU and DSA port(s), and the other ports.
d827e88a 1910 */
b4e48c50 1911 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 1912 if (err)
1913 return err;
2db9ce1f 1914
240ea3ef 1915 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 1916 if (err)
1917 return err;
d827e88a
GR		 1918
1919 /* Default VLAN ID and priority: don't set a default VLAN
1920 * ID, and set the default packet priority to zero.
1921 */
b7929fb3 1922 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 1923}
1924
04aca993
AL		 1925static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1926 struct phy_device *phydev)
1927{
1928 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 1929 int err;
04aca993
AL		 1930
1931 mutex_lock(&chip->reg_lock);
523a8904 1932 err = mv88e6xxx_serdes_power(chip, port, true);
04aca993
AL		 1933 mutex_unlock(&chip->reg_lock);
1934
1935 return err;
1936}
1937
1938static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
1939 struct phy_device *phydev)
1940{
1941 struct mv88e6xxx_chip *chip = ds->priv;
1942
1943 mutex_lock(&chip->reg_lock);
523a8904
VD		 1944 if (mv88e6xxx_serdes_power(chip, port, false))
1945 dev_err(chip->dev, "failed to power off SERDES\n");
04aca993
AL		 1946 mutex_unlock(&chip->reg_lock);
1947}
1948
2cfcd964
VD		 1949static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
1950 unsigned int ageing_time)
1951{
04bed143 1952 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 1953 int err;
1954
1955 mutex_lock(&chip->reg_lock);
720c6343 1956 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 1957 mutex_unlock(&chip->reg_lock);
1958
1959 return err;
1960}
1961
9729934c 1962static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 1963{
fad09c73 1964 struct dsa_switch *ds = chip->ds;
b0745e87 1965 u32 upstream_port = dsa_upstream_port(ds);
552238b5 1966 int err;
54d792f2 1967
fa8d1179
VD		 1968 if (chip->info->ops->set_cpu_port) {
1969 err = chip->info->ops->set_cpu_port(chip, upstream_port);
33641994
AL		 1970 if (err)
1971 return err;
1972 }
1973
fa8d1179
VD		 1974 if (chip->info->ops->set_egress_port) {
1975 err = chip->info->ops->set_egress_port(chip, upstream_port);
33641994
AL		 1976 if (err)
1977 return err;
1978 }
b0745e87 1979
50484ff4 1980 /* Disable remote management, and set the switch's DSA device number. */
d77f4321
VD		 1981 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
1982 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
a935c052 1983 (ds->index & 0x1f));
50484ff4
VD		 1984 if (err)
1985 return err;
1986
54d792f2 1987 /* Configure the IP ToS mapping registers. */
ccba8f3a 1988 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
48ace4ef 1989 if (err)
08a01261 1990 return err;
ccba8f3a 1991 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
48ace4ef 1992 if (err)
08a01261 1993 return err;
ccba8f3a 1994 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
48ace4ef 1995 if (err)
08a01261 1996 return err;
ccba8f3a 1997 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
48ace4ef 1998 if (err)
08a01261 1999 return err;
ccba8f3a 2000 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
48ace4ef 2001 if (err)
08a01261 2002 return err;
ccba8f3a 2003 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
48ace4ef 2004 if (err)
08a01261 2005 return err;
ccba8f3a 2006 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
48ace4ef 2007 if (err)
08a01261 2008 return err;
ccba8f3a 2009 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
48ace4ef 2010 if (err)
08a01261 2011 return err;
54d792f2
AL		 2012
2013 /* Configure the IEEE 802.1p priority mapping register. */
ccba8f3a 2014 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
48ace4ef 2015 if (err)
08a01261 2016 return err;
54d792f2 2017
de227387
AL		 2018 /* Initialize the statistics unit */
2019 err = mv88e6xxx_stats_set_histogram(chip);
2020 if (err)
2021 return err;
2022
40cff8fc 2023 return mv88e6xxx_g1_stats_clear(chip);
9729934c
VD		 2024}
2025
f843abe0
AL		 2026/* The mv88e6390 has some hidden registers used for debug and
2027 * development. The errata also makes use of them.
2028 */
2029static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2030 int reg, u16 val)
2031{
2032 u16 ctrl;
2033 int err;
2034
2035 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2036 PORT_RESERVED_1A, val);
2037 if (err)
2038 return err;
2039
2040 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2041 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2042 reg;
2043
2044 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2045 PORT_RESERVED_1A, ctrl);
2046}
2047
2048static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2049{
2050 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2051 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2052}
2053
2054
2055static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2056 int reg, u16 *val)
2057{
2058 u16 ctrl;
2059 int err;
2060
2061 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2062 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2063 reg;
2064
2065 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2066 PORT_RESERVED_1A, ctrl);
2067 if (err)
2068 return err;
2069
2070 err = mv88e6390_hidden_wait(chip);
2071 if (err)
2072 return err;
2073
2074 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2075 PORT_RESERVED_1A, val);
2076}
2077
2078/* Check if the errata has already been applied. */
2079static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2080{
2081 int port;
2082 int err;
2083 u16 val;
2084
2085 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2086 err = mv88e6390_hidden_read(chip, port, 0, &val);
2087 if (err) {
2088 dev_err(chip->dev,
2089 "Error reading hidden register: %d\n", err);
2090 return false;
2091 }
2092 if (val != 0x01c0)
2093 return false;
2094 }
2095
2096 return true;
2097}
2098
2099/* The 6390 copper ports have an errata which require poking magic
2100 * values into undocumented hidden registers and then performing a
2101 * software reset.
2102 */
2103static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2104{
2105 int port;
2106 int err;
2107
2108 if (mv88e6390_setup_errata_applied(chip))
2109 return 0;
2110
2111 /* Set the ports into blocking mode */
2112 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2113 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2114 if (err)
2115 return err;
2116 }
2117
2118 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2119 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2120 if (err)
2121 return err;
2122 }
2123
2124 return mv88e6xxx_software_reset(chip);
2125}
2126
f81ec90f 2127static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2128{
04bed143 2129 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2130 int err;
a1a6a4d1
VD		 2131 int i;
2132
fad09c73 2133 chip->ds = ds;
a3c53be5 2134 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2135
fad09c73 2136 mutex_lock(&chip->reg_lock);
08a01261 2137
f843abe0
AL		 2138 if (chip->info->ops->setup_errata) {
2139 err = chip->info->ops->setup_errata(chip);
2140 if (err)
2141 goto unlock;
2142 }
2143
9729934c 2144 /* Setup Switch Port Registers */
370b4ffb 2145 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
91dee144
VD		 2146 if (dsa_is_unused_port(ds, i))
2147 continue;
2148
9729934c
VD		 2149 err = mv88e6xxx_setup_port(chip, i);
2150 if (err)
2151 goto unlock;
2152 }
2153
2154 /* Setup Switch Global 1 Registers */
2155 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2156 if (err)
2157 goto unlock;
2158
9729934c 2159 /* Setup Switch Global 2 Registers */
9069c13a 2160 if (chip->info->global2_addr) {
9729934c 2161 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2162 if (err)
2163 goto unlock;
2164 }
08a01261 2165
cd8da8bb
VD		 2166 err = mv88e6xxx_irl_setup(chip);
2167 if (err)
2168 goto unlock;
2169
04a69a17
VD		 2170 err = mv88e6xxx_mac_setup(chip);
2171 if (err)
2172 goto unlock;
2173
1b17aedf
VD		 2174 err = mv88e6xxx_phy_setup(chip);
2175 if (err)
2176 goto unlock;
2177
b486d7c9
VD		 2178 err = mv88e6xxx_vtu_setup(chip);
2179 if (err)
2180 goto unlock;
2181
81228996
VD		 2182 err = mv88e6xxx_pvt_setup(chip);
2183 if (err)
2184 goto unlock;
2185
a2ac29d2
VD		 2186 err = mv88e6xxx_atu_setup(chip);
2187 if (err)
2188 goto unlock;
2189
87fa886e
AL		 2190 err = mv88e6xxx_broadcast_setup(chip, 0);
2191 if (err)
2192 goto unlock;
2193
9e907d73
VD		 2194 err = mv88e6xxx_pot_setup(chip);
2195 if (err)
2196 goto unlock;
2197
51c901a7
VD		 2198 err = mv88e6xxx_rsvd2cpu_setup(chip);
2199 if (err)
2200 goto unlock;
6e55f698 2201
6b17e864 2202unlock:
fad09c73 2203 mutex_unlock(&chip->reg_lock);
db687a56 2204
48ace4ef 2205 return err;
54d792f2
AL		 2206}
2207
e57e5e77 2208static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2209{
0dd12d54
AL		 2210 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2211 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2212 u16 val;
2213 int err;
fd3a0ee4 2214
ee26a228
AL		 2215 if (!chip->info->ops->phy_read)
2216 return -EOPNOTSUPP;
2217
fad09c73 2218 mutex_lock(&chip->reg_lock);
ee26a228 2219 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2220 mutex_unlock(&chip->reg_lock);
e57e5e77 2221
da9f3301
AL		 2222 if (reg == MII_PHYSID2) {
2223 /* Some internal PHYS don't have a model number. Use
2224 * the mv88e6390 family model number instead.
2225 */
2226 if (!(val & 0x3f0))
107fcc10 2227 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
da9f3301
AL		 2228 }
2229
e57e5e77 2230 return err ? err : val;
fd3a0ee4
AL		 2231}
2232
e57e5e77 2233static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2234{
0dd12d54
AL		 2235 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2236 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2237 int err;
fd3a0ee4 2238
ee26a228
AL		 2239 if (!chip->info->ops->phy_write)
2240 return -EOPNOTSUPP;
2241
fad09c73 2242 mutex_lock(&chip->reg_lock);
ee26a228 2243 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2244 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2245
2246 return err;
fd3a0ee4
AL		 2247}
2248
fad09c73 2249static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2250 struct device_node *np,
2251 bool external)
b516d453
AL		 2252{
2253 static int index;
0dd12d54 2254 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2255 struct mii_bus *bus;
2256 int err;
2257
0dd12d54 2258 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2259 if (!bus)
2260 return -ENOMEM;
2261
0dd12d54 2262 mdio_bus = bus->priv;
a3c53be5 2263 mdio_bus->bus = bus;
0dd12d54 2264 mdio_bus->chip = chip;
a3c53be5
AL		 2265 INIT_LIST_HEAD(&mdio_bus->list);
2266 mdio_bus->external = external;
0dd12d54 2267
b516d453
AL		 2268 if (np) {
2269 bus->name = np->full_name;
f7ce9103 2270 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
b516d453
AL		 2271 } else {
2272 bus->name = "mv88e6xxx SMI";
2273 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2274 }
2275
2276 bus->read = mv88e6xxx_mdio_read;
2277 bus->write = mv88e6xxx_mdio_write;
fad09c73 2278 bus->parent = chip->dev;
b516d453 2279
a3c53be5
AL		 2280 if (np)
2281 err = of_mdiobus_register(bus, np);
b516d453
AL		 2282 else
2283 err = mdiobus_register(bus);
2284 if (err) {
fad09c73 2285 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2286 return err;
b516d453 2287 }
a3c53be5
AL		 2288
2289 if (external)
2290 list_add_tail(&mdio_bus->list, &chip->mdios);
2291 else
2292 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2293
2294 return 0;
a3c53be5 2295}
b516d453 2296
a3c53be5
AL		 2297static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2298 { .compatible = "marvell,mv88e6xxx-mdio-external",
2299 .data = (void *)true },
2300 { },
2301};
b516d453 2302
3126aeec
AL		 2303static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2304
2305{
2306 struct mv88e6xxx_mdio_bus *mdio_bus;
2307 struct mii_bus *bus;
2308
2309 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2310 bus = mdio_bus->bus;
2311
2312 mdiobus_unregister(bus);
2313 }
2314}
2315
a3c53be5
AL		 2316static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2317 struct device_node *np)
2318{
2319 const struct of_device_id *match;
2320 struct device_node *child;
2321 int err;
2322
2323 /* Always register one mdio bus for the internal/default mdio
2324 * bus. This maybe represented in the device tree, but is
2325 * optional.
2326 */
2327 child = of_get_child_by_name(np, "mdio");
2328 err = mv88e6xxx_mdio_register(chip, child, false);
2329 if (err)
2330 return err;
2331
2332 /* Walk the device tree, and see if there are any other nodes
2333 * which say they are compatible with the external mdio
2334 * bus.
2335 */
2336 for_each_available_child_of_node(np, child) {
2337 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2338 if (match) {
2339 err = mv88e6xxx_mdio_register(chip, child, true);
3126aeec
AL		 2340 if (err) {
2341 mv88e6xxx_mdios_unregister(chip);
a3c53be5 2342 return err;
3126aeec 2343 }
a3c53be5
AL		 2344 }
2345 }
2346
2347 return 0;
b516d453
AL		 2348}
2349
855b1932
VD		 2350static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2351{
04bed143 2352 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2353
2354 return chip->eeprom_len;
2355}
2356
855b1932
VD		 2357static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2358 struct ethtool_eeprom *eeprom, u8 *data)
2359{
04bed143 2360 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2361 int err;
2362
ee4dc2e7
VD		 2363 if (!chip->info->ops->get_eeprom)
2364 return -EOPNOTSUPP;
855b1932 2365
ee4dc2e7
VD		 2366 mutex_lock(&chip->reg_lock);
2367 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2368 mutex_unlock(&chip->reg_lock);
2369
2370 if (err)
2371 return err;
2372
2373 eeprom->magic = 0xc3ec4951;
2374
2375 return 0;
2376}
2377
855b1932
VD		 2378static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2379 struct ethtool_eeprom *eeprom, u8 *data)
2380{
04bed143 2381 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2382 int err;
2383
ee4dc2e7
VD		 2384 if (!chip->info->ops->set_eeprom)
2385 return -EOPNOTSUPP;
2386
855b1932
VD		 2387 if (eeprom->magic != 0xc3ec4951)
2388 return -EINVAL;
2389
2390 mutex_lock(&chip->reg_lock);
ee4dc2e7 2391 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2392 mutex_unlock(&chip->reg_lock);
2393
2394 return err;
2395}
2396
b3469dd8 2397static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2398 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2399 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2400 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2401 .phy_read = mv88e6185_phy_ppu_read,
2402 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2403 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2404 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2405 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2406 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2407 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2408 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2409 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2410 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2411 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2412 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2413 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2414 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2415 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2416 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2417 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2418 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2419 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2420 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2421 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2422 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2423 .pot_clear = mv88e6xxx_g2_pot_clear,
a199d8b6
VD		 2424 .ppu_enable = mv88e6185_g1_ppu_enable,
2425 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2426 .reset = mv88e6185_g1_reset,
f1394b78 2427 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2428 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2429};
2430
2431static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2432 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2433 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2434 .phy_read = mv88e6185_phy_ppu_read,
2435 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2436 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2437 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2438 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2439 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2440 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2441 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2442 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2443 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2444 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2445 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2446 .stats_get_stats = mv88e6095_stats_get_stats,
51c901a7 2447 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2448 .ppu_enable = mv88e6185_g1_ppu_enable,
2449 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2450 .reset = mv88e6185_g1_reset,
f1394b78 2451 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2452 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2453};
2454
7d381a02 2455static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2456 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2457 .irl_init_all = mv88e6352_g2_irl_init_all,
7d381a02
SE		 2458 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2459 .phy_read = mv88e6xxx_g2_smi_phy_read,
2460 .phy_write = mv88e6xxx_g2_smi_phy_write,
2461 .port_set_link = mv88e6xxx_port_set_link,
2462 .port_set_duplex = mv88e6xxx_port_set_duplex,
2463 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2464 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2465 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2466 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2467 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2468 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2469 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 2470 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2471 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2472 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02 2473 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2474 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
7d381a02
SE		 2475 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2476 .stats_get_strings = mv88e6095_stats_get_strings,
2477 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2478 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2479 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2480 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2481 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2482 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2483 .reset = mv88e6352_g1_reset,
f1394b78 2484 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2485 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
7d381a02
SE		 2486};
2487
b3469dd8 2488static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2489 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2490 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2491 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2492 .phy_read = mv88e6xxx_g2_smi_phy_read,
2493 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2494 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2495 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2496 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2497 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2498 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2501 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2502 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2503 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2504 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2505 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2506 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2507 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2508 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2509 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2510 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2511 .reset = mv88e6352_g1_reset,
f1394b78 2512 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2513 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2514};
2515
2516static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2517 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2518 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2519 .phy_read = mv88e6185_phy_ppu_read,
2520 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2521 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2522 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2523 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2524 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2525 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2526 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2527 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2528 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 2529 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2530 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2531 .port_pause_limit = mv88e6097_port_pause_limit,
a605a0fe 2532 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2533 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2534 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2535 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2536 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2537 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2538 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2539 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2540 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2541 .ppu_enable = mv88e6185_g1_ppu_enable,
2542 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2543 .reset = mv88e6185_g1_reset,
f1394b78 2544 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2545 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2546};
2547
990e27b0
VD		 2548static const struct mv88e6xxx_ops mv88e6141_ops = {
2549 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 2550 .irl_init_all = mv88e6352_g2_irl_init_all,
990e27b0
VD		 2551 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2552 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2553 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2554 .phy_read = mv88e6xxx_g2_smi_phy_read,
2555 .phy_write = mv88e6xxx_g2_smi_phy_write,
2556 .port_set_link = mv88e6xxx_port_set_link,
2557 .port_set_duplex = mv88e6xxx_port_set_duplex,
2558 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2559 .port_set_speed = mv88e6390_port_set_speed,
2560 .port_tag_remap = mv88e6095_port_tag_remap,
2561 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2562 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2563 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2564 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 2565 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2566 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 2567 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2568 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2569 .stats_snapshot = mv88e6390_g1_stats_snapshot,
40cff8fc 2570 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
990e27b0
VD		 2571 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2572 .stats_get_strings = mv88e6320_stats_get_strings,
2573 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2574 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2575 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 2576 .watchdog_ops = &mv88e6390_watchdog_ops,
2577 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2578 .pot_clear = mv88e6xxx_g2_pot_clear,
990e27b0 2579 .reset = mv88e6352_g1_reset,
f1394b78 2580 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2581 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
990e27b0
VD		 2582};
2583
b3469dd8 2584static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2585 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2586 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2587 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2588 .phy_read = mv88e6xxx_g2_smi_phy_read,
2589 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2590 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2591 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2592 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2593 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2594 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2595 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2596 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2597 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2598 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2599 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2600 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2601 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2602 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2603 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2604 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2605 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2606 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2607 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2608 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2609 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2610 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2611 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2612 .reset = mv88e6352_g1_reset,
f1394b78 2613 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2614 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2615};
2616
2617static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2618 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2619 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2620 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2621 .phy_read = mv88e6165_phy_read,
2622 .phy_write = mv88e6165_phy_write,
08ef7f10 2623 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2624 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2625 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 2626 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2627 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2628 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2629 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2630 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2631 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2632 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2633 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2634 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2635 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2636 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2637 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2638 .reset = mv88e6352_g1_reset,
f1394b78 2639 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2640 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2641};
2642
2643static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2644 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2645 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2646 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2647 .phy_read = mv88e6xxx_g2_smi_phy_read,
2648 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2649 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2650 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2651 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2652 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2653 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2654 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2655 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2656 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2657 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2658 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2659 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2660 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2661 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2662 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2663 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2664 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2665 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2666 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2667 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2668 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2669 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2670 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2671 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2672 .reset = mv88e6352_g1_reset,
f1394b78 2673 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2674 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2675};
2676
2677static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 2678 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2679 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2680 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2681 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2682 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2683 .phy_read = mv88e6xxx_g2_smi_phy_read,
2684 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2685 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2686 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2687 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2688 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2689 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2690 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2691 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2692 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2693 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2694 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2695 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2696 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2697 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2698 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2699 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2700 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2701 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2702 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2703 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2704 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2705 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2706 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2707 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2708 .reset = mv88e6352_g1_reset,
f1394b78 2709 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2710 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2711 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2712};
2713
2714static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 2715 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2716 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2717 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2718 .phy_read = mv88e6xxx_g2_smi_phy_read,
2719 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2720 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2721 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2722 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2723 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2724 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2725 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2726 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2727 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2728 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2729 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2730 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2731 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2732 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2733 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2734 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2735 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2736 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2737 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2738 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2739 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2740 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2741 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2742 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2743 .reset = mv88e6352_g1_reset,
f1394b78 2744 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2745 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2746};
2747
2748static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 2749 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2750 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2751 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2752 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2753 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2754 .phy_read = mv88e6xxx_g2_smi_phy_read,
2755 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2756 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2757 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2758 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2759 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2760 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2761 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2762 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2763 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2764 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2765 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2766 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2767 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2768 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2769 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2770 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2771 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2772 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2773 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2774 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2775 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2776 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2777 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2778 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2779 .reset = mv88e6352_g1_reset,
f1394b78 2780 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2781 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2782 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2783};
2784
2785static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 2786 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2787 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2788 .phy_read = mv88e6185_phy_ppu_read,
2789 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2790 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2791 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2792 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2793 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2794 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 2795 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 2796 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2797 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 2798 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2799 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2800 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2801 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2802 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2803 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2804 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2805 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2806 .ppu_enable = mv88e6185_g1_ppu_enable,
2807 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2808 .reset = mv88e6185_g1_reset,
f1394b78 2809 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2810 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2811};
2812
1a3b39ec 2813static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 2814 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2815 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2816 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2817 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2818 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2819 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2820 .phy_read = mv88e6xxx_g2_smi_phy_read,
2821 .phy_write = mv88e6xxx_g2_smi_phy_write,
2822 .port_set_link = mv88e6xxx_port_set_link,
2823 .port_set_duplex = mv88e6xxx_port_set_duplex,
2824 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2825 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2826 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2827 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2828 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2829 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2830 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2831 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2832 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2833 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2834 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2835 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2836 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2837 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2838 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2839 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2840 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2841 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2842 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2843 .reset = mv88e6352_g1_reset,
931d1822
VD		 2844 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2845 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2846 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2847};
2848
2849static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 2850 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2851 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2852 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2853 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2854 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2855 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2856 .phy_read = mv88e6xxx_g2_smi_phy_read,
2857 .phy_write = mv88e6xxx_g2_smi_phy_write,
2858 .port_set_link = mv88e6xxx_port_set_link,
2859 .port_set_duplex = mv88e6xxx_port_set_duplex,
2860 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2861 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 2862 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2863 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2864 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2865 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2866 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2867 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2868 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2869 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2870 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2871 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2872 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2873 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2874 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2875 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2876 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2877 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2878 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2879 .reset = mv88e6352_g1_reset,
931d1822
VD		 2880 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2881 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2882 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2883};
2884
2885static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 2886 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2887 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2888 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2889 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2890 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2891 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2892 .phy_read = mv88e6xxx_g2_smi_phy_read,
2893 .phy_write = mv88e6xxx_g2_smi_phy_write,
2894 .port_set_link = mv88e6xxx_port_set_link,
2895 .port_set_duplex = mv88e6xxx_port_set_duplex,
2896 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2897 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2898 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2899 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2900 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2901 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2902 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2903 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2904 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2905 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2906 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2907 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2908 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2909 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2910 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2911 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2912 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2913 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2914 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2915 .reset = mv88e6352_g1_reset,
931d1822
VD		 2916 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2917 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2918 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2919};
2920
b3469dd8 2921static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 2922 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2923 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2924 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2925 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2926 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2927 .phy_read = mv88e6xxx_g2_smi_phy_read,
2928 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2929 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2930 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2931 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2932 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2933 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2934 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2935 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2936 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2937 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2938 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2939 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2940 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2941 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2942 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 2943 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 2944 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2945 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2946 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2947 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2948 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2949 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2950 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2951 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2952 .reset = mv88e6352_g1_reset,
f1394b78 2953 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2954 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2955 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2956};
2957
1a3b39ec 2958static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 2959 /* MV88E6XXX_FAMILY_6390 */
f843abe0 2960 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 2961 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2962 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2963 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2964 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2965 .phy_read = mv88e6xxx_g2_smi_phy_read,
2966 .phy_write = mv88e6xxx_g2_smi_phy_write,
2967 .port_set_link = mv88e6xxx_port_set_link,
2968 .port_set_duplex = mv88e6xxx_port_set_duplex,
2969 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2970 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2971 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2972 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2973 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2974 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2975 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 2976 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 2977 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2978 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2979 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2980 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2981 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2982 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2983 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2984 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2985 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2986 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2987 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2988 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2989 .reset = mv88e6352_g1_reset,
931d1822
VD		 2990 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2991 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2992 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2993};
2994
b3469dd8 2995static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 2996 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 2997 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2998 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2999 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3000 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3001 .phy_read = mv88e6xxx_g2_smi_phy_read,
3002 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3003 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3004 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3005 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3006 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3007 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3008 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3009 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3010 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3011 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3012 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3013 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3014 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3015 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3016 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3017 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3018 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3019 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 3020 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3021 .set_egress_port = mv88e6095_g1_set_egress_port,
51c901a7 3022 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3023 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3024 .reset = mv88e6352_g1_reset,
f1394b78 3025 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3026 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 3027};
3028
3029static const struct mv88e6xxx_ops mv88e6321_ops = {
bd807204 3030 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 3031 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3032 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3033 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3034 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3035 .phy_read = mv88e6xxx_g2_smi_phy_read,
3036 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3037 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3038 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3039 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3040 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3041 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3042 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3043 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3044 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3045 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3046 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3049 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3050 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3051 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3052 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3053 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 3054 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3055 .set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3056 .reset = mv88e6352_g1_reset,
f1394b78 3057 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3058 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 3059};
3060
16e329ae
VD		 3061static const struct mv88e6xxx_ops mv88e6341_ops = {
3062 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 3063 .irl_init_all = mv88e6352_g2_irl_init_all,
16e329ae
VD		 3064 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3065 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3066 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3067 .phy_read = mv88e6xxx_g2_smi_phy_read,
3068 .phy_write = mv88e6xxx_g2_smi_phy_write,
3069 .port_set_link = mv88e6xxx_port_set_link,
3070 .port_set_duplex = mv88e6xxx_port_set_duplex,
3071 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3072 .port_set_speed = mv88e6390_port_set_speed,
3073 .port_tag_remap = mv88e6095_port_tag_remap,
3074 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3075 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3076 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3077 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 3078 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3079 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 3080 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3081 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3082 .stats_snapshot = mv88e6390_g1_stats_snapshot,
40cff8fc 3083 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
16e329ae
VD		 3084 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3085 .stats_get_strings = mv88e6320_stats_get_strings,
3086 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3087 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3088 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 3089 .watchdog_ops = &mv88e6390_watchdog_ops,
3090 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3091 .pot_clear = mv88e6xxx_g2_pot_clear,
16e329ae 3092 .reset = mv88e6352_g1_reset,
f1394b78 3093 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3094 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
16e329ae
VD		 3095};
3096
b3469dd8 3097static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3098 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3099 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3100 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3101 .phy_read = mv88e6xxx_g2_smi_phy_read,
3102 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3103 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3104 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3105 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3106 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3107 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3108 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3109 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3110 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3111 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3112 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3113 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3114 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3115 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3116 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3117 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3118 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3119 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3120 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3121 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3122 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3123 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3124 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3125 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3126 .reset = mv88e6352_g1_reset,
f1394b78 3127 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3128 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3129};
3130
3131static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3132 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3133 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3134 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3135 .phy_read = mv88e6xxx_g2_smi_phy_read,
3136 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3137 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3138 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3139 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3140 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3141 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3142 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3143 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3144 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3145 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3146 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3147 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3148 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3149 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3150 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3151 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3152 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3153 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3154 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3155 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3156 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3157 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3158 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3159 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3160 .reset = mv88e6352_g1_reset,
f1394b78 3161 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3162 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3163};
3164
3165static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3166 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 3167 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3168 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3169 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3170 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3171 .phy_read = mv88e6xxx_g2_smi_phy_read,
3172 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3173 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3174 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3175 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3176 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3177 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3178 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3179 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3180 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3181 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3182 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3183 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3184 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3185 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3186 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3187 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3188 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3189 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3190 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3191 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3192 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3193 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3194 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3195 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3196 .reset = mv88e6352_g1_reset,
f1394b78 3197 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3198 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 3199 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 3200};
3201
1a3b39ec 3202static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3203 /* MV88E6XXX_FAMILY_6390 */
f843abe0 3204 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 3205 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3206 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3207 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3208 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3209 .phy_read = mv88e6xxx_g2_smi_phy_read,
3210 .phy_write = mv88e6xxx_g2_smi_phy_write,
3211 .port_set_link = mv88e6xxx_port_set_link,
3212 .port_set_duplex = mv88e6xxx_port_set_duplex,
3213 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3214 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3215 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3216 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3217 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3218 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3219 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3220 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3221 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 3222 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3223 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3224 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3225 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3226 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3227 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3228 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3229 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3230 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3231 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3232 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3233 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3234 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3235 .reset = mv88e6352_g1_reset,
931d1822
VD		 3236 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3237 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3238 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3239};
3240
3241static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3242 /* MV88E6XXX_FAMILY_6390 */
f843abe0 3243 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 3244 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3245 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3246 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3247 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3248 .phy_read = mv88e6xxx_g2_smi_phy_read,
3249 .phy_write = mv88e6xxx_g2_smi_phy_write,
3250 .port_set_link = mv88e6xxx_port_set_link,
3251 .port_set_duplex = mv88e6xxx_port_set_duplex,
3252 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3253 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3254 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3255 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3256 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3257 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3258 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3260 .port_pause_limit = mv88e6390_port_pause_limit,
bb0a2675 3261 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3262 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3263 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3264 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3265 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3266 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3267 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3268 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3269 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3270 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3271 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3272 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3273 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3274 .reset = mv88e6352_g1_reset,
931d1822
VD		 3275 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3276 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3277 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3278};
3279
f81ec90f
VD		 3280static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3281 [MV88E6085] = {
107fcc10 3282 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 3283 .family = MV88E6XXX_FAMILY_6097,
3284 .name = "Marvell 88E6085",
3285 .num_databases = 4096,
3286 .num_ports = 10,
3cf3c846 3287 .max_vid = 4095,
9dddd478 3288 .port_base_addr = 0x10,
a935c052 3289 .global1_addr = 0x1b,
9069c13a 3290 .global2_addr = 0x1c,
acddbd21 3291 .age_time_coeff = 15000,
dc30c35b 3292 .g1_irqs = 8,
d6c5e6af 3293 .g2_irqs = 10,
e606ca36 3294 .atu_move_port_mask = 0xf,
f3645652 3295 .pvt = true,
b3e05aa1 3296 .multi_chip = true,
443d5a1b 3297 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3298 .ops = &mv88e6085_ops,
f81ec90f
VD		 3299 },
3300
3301 [MV88E6095] = {
107fcc10 3302 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 3303 .family = MV88E6XXX_FAMILY_6095,
3304 .name = "Marvell 88E6095/88E6095F",
3305 .num_databases = 256,
3306 .num_ports = 11,
3cf3c846 3307 .max_vid = 4095,
9dddd478 3308 .port_base_addr = 0x10,
a935c052 3309 .global1_addr = 0x1b,
9069c13a 3310 .global2_addr = 0x1c,
acddbd21 3311 .age_time_coeff = 15000,
dc30c35b 3312 .g1_irqs = 8,
e606ca36 3313 .atu_move_port_mask = 0xf,
b3e05aa1 3314 .multi_chip = true,
443d5a1b 3315 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3316 .ops = &mv88e6095_ops,
f81ec90f
VD		 3317 },
3318
7d381a02 3319 [MV88E6097] = {
107fcc10 3320 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 3321 .family = MV88E6XXX_FAMILY_6097,
3322 .name = "Marvell 88E6097/88E6097F",
3323 .num_databases = 4096,
3324 .num_ports = 11,
3cf3c846 3325 .max_vid = 4095,
7d381a02
SE		 3326 .port_base_addr = 0x10,
3327 .global1_addr = 0x1b,
9069c13a 3328 .global2_addr = 0x1c,
7d381a02 3329 .age_time_coeff = 15000,
c534178b 3330 .g1_irqs = 8,
d6c5e6af 3331 .g2_irqs = 10,
e606ca36 3332 .atu_move_port_mask = 0xf,
f3645652 3333 .pvt = true,
b3e05aa1 3334 .multi_chip = true,
2bfcfcd3 3335 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3336 .ops = &mv88e6097_ops,
3337 },
3338
f81ec90f 3339 [MV88E6123] = {
107fcc10 3340 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 3341 .family = MV88E6XXX_FAMILY_6165,
3342 .name = "Marvell 88E6123",
3343 .num_databases = 4096,
3344 .num_ports = 3,
3cf3c846 3345 .max_vid = 4095,
9dddd478 3346 .port_base_addr = 0x10,
a935c052 3347 .global1_addr = 0x1b,
9069c13a 3348 .global2_addr = 0x1c,
acddbd21 3349 .age_time_coeff = 15000,
dc30c35b 3350 .g1_irqs = 9,
d6c5e6af 3351 .g2_irqs = 10,
e606ca36 3352 .atu_move_port_mask = 0xf,
f3645652 3353 .pvt = true,
b3e05aa1 3354 .multi_chip = true,
5ebe31d7 3355 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3356 .ops = &mv88e6123_ops,
f81ec90f
VD		 3357 },
3358
3359 [MV88E6131] = {
107fcc10 3360 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 3361 .family = MV88E6XXX_FAMILY_6185,
3362 .name = "Marvell 88E6131",
3363 .num_databases = 256,
3364 .num_ports = 8,
3cf3c846 3365 .max_vid = 4095,
9dddd478 3366 .port_base_addr = 0x10,
a935c052 3367 .global1_addr = 0x1b,
9069c13a 3368 .global2_addr = 0x1c,
acddbd21 3369 .age_time_coeff = 15000,
dc30c35b 3370 .g1_irqs = 9,
e606ca36 3371 .atu_move_port_mask = 0xf,
b3e05aa1 3372 .multi_chip = true,
443d5a1b 3373 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3374 .ops = &mv88e6131_ops,
f81ec90f
VD		 3375 },
3376
990e27b0 3377 [MV88E6141] = {
107fcc10 3378 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0
VD		 3379 .family = MV88E6XXX_FAMILY_6341,
3380 .name = "Marvell 88E6341",
3381 .num_databases = 4096,
3382 .num_ports = 6,
3cf3c846 3383 .max_vid = 4095,
990e27b0
VD		 3384 .port_base_addr = 0x10,
3385 .global1_addr = 0x1b,
9069c13a 3386 .global2_addr = 0x1c,
990e27b0
VD		 3387 .age_time_coeff = 3750,
3388 .atu_move_port_mask = 0x1f,
d6c5e6af 3389 .g2_irqs = 10,
f3645652 3390 .pvt = true,
b3e05aa1 3391 .multi_chip = true,
990e27b0 3392 .tag_protocol = DSA_TAG_PROTO_EDSA,
990e27b0
VD		 3393 .ops = &mv88e6141_ops,
3394 },
3395
f81ec90f 3396 [MV88E6161] = {
107fcc10 3397 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 3398 .family = MV88E6XXX_FAMILY_6165,
3399 .name = "Marvell 88E6161",
3400 .num_databases = 4096,
3401 .num_ports = 6,
3cf3c846 3402 .max_vid = 4095,
9dddd478 3403 .port_base_addr = 0x10,
a935c052 3404 .global1_addr = 0x1b,
9069c13a 3405 .global2_addr = 0x1c,
acddbd21 3406 .age_time_coeff = 15000,
dc30c35b 3407 .g1_irqs = 9,
d6c5e6af 3408 .g2_irqs = 10,
e606ca36 3409 .atu_move_port_mask = 0xf,
f3645652 3410 .pvt = true,
b3e05aa1 3411 .multi_chip = true,
5ebe31d7 3412 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3413 .ops = &mv88e6161_ops,
f81ec90f
VD		 3414 },
3415
3416 [MV88E6165] = {
107fcc10 3417 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 3418 .family = MV88E6XXX_FAMILY_6165,
3419 .name = "Marvell 88E6165",
3420 .num_databases = 4096,
3421 .num_ports = 6,
3cf3c846 3422 .max_vid = 4095,
9dddd478 3423 .port_base_addr = 0x10,
a935c052 3424 .global1_addr = 0x1b,
9069c13a 3425 .global2_addr = 0x1c,
acddbd21 3426 .age_time_coeff = 15000,
dc30c35b 3427 .g1_irqs = 9,
d6c5e6af 3428 .g2_irqs = 10,
e606ca36 3429 .atu_move_port_mask = 0xf,
f3645652 3430 .pvt = true,
b3e05aa1 3431 .multi_chip = true,
443d5a1b 3432 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3433 .ops = &mv88e6165_ops,
f81ec90f
VD		 3434 },
3435
3436 [MV88E6171] = {
107fcc10 3437 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 3438 .family = MV88E6XXX_FAMILY_6351,
3439 .name = "Marvell 88E6171",
3440 .num_databases = 4096,
3441 .num_ports = 7,
3cf3c846 3442 .max_vid = 4095,
9dddd478 3443 .port_base_addr = 0x10,
a935c052 3444 .global1_addr = 0x1b,
9069c13a 3445 .global2_addr = 0x1c,
acddbd21 3446 .age_time_coeff = 15000,
dc30c35b 3447 .g1_irqs = 9,
d6c5e6af 3448 .g2_irqs = 10,
e606ca36 3449 .atu_move_port_mask = 0xf,
f3645652 3450 .pvt = true,
b3e05aa1 3451 .multi_chip = true,
443d5a1b 3452 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3453 .ops = &mv88e6171_ops,
f81ec90f
VD		 3454 },
3455
3456 [MV88E6172] = {
107fcc10 3457 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 3458 .family = MV88E6XXX_FAMILY_6352,
3459 .name = "Marvell 88E6172",
3460 .num_databases = 4096,
3461 .num_ports = 7,
3cf3c846 3462 .max_vid = 4095,
9dddd478 3463 .port_base_addr = 0x10,
a935c052 3464 .global1_addr = 0x1b,
9069c13a 3465 .global2_addr = 0x1c,
acddbd21 3466 .age_time_coeff = 15000,
dc30c35b 3467 .g1_irqs = 9,
d6c5e6af 3468 .g2_irqs = 10,
e606ca36 3469 .atu_move_port_mask = 0xf,
f3645652 3470 .pvt = true,
b3e05aa1 3471 .multi_chip = true,
443d5a1b 3472 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3473 .ops = &mv88e6172_ops,
f81ec90f
VD		 3474 },
3475
3476 [MV88E6175] = {
107fcc10 3477 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 3478 .family = MV88E6XXX_FAMILY_6351,
3479 .name = "Marvell 88E6175",
3480 .num_databases = 4096,
3481 .num_ports = 7,
3cf3c846 3482 .max_vid = 4095,
9dddd478 3483 .port_base_addr = 0x10,
a935c052 3484 .global1_addr = 0x1b,
9069c13a 3485 .global2_addr = 0x1c,
acddbd21 3486 .age_time_coeff = 15000,
dc30c35b 3487 .g1_irqs = 9,
d6c5e6af 3488 .g2_irqs = 10,
e606ca36 3489 .atu_move_port_mask = 0xf,
f3645652 3490 .pvt = true,
b3e05aa1 3491 .multi_chip = true,
443d5a1b 3492 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3493 .ops = &mv88e6175_ops,
f81ec90f
VD		 3494 },
3495
3496 [MV88E6176] = {
107fcc10 3497 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 3498 .family = MV88E6XXX_FAMILY_6352,
3499 .name = "Marvell 88E6176",
3500 .num_databases = 4096,
3501 .num_ports = 7,
3cf3c846 3502 .max_vid = 4095,
9dddd478 3503 .port_base_addr = 0x10,
a935c052 3504 .global1_addr = 0x1b,
9069c13a 3505 .global2_addr = 0x1c,
acddbd21 3506 .age_time_coeff = 15000,
dc30c35b 3507 .g1_irqs = 9,
d6c5e6af 3508 .g2_irqs = 10,
e606ca36 3509 .atu_move_port_mask = 0xf,
f3645652 3510 .pvt = true,
b3e05aa1 3511 .multi_chip = true,
443d5a1b 3512 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3513 .ops = &mv88e6176_ops,
f81ec90f
VD		 3514 },
3515
3516 [MV88E6185] = {
107fcc10 3517 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 3518 .family = MV88E6XXX_FAMILY_6185,
3519 .name = "Marvell 88E6185",
3520 .num_databases = 256,
3521 .num_ports = 10,
3cf3c846 3522 .max_vid = 4095,
9dddd478 3523 .port_base_addr = 0x10,
a935c052 3524 .global1_addr = 0x1b,
9069c13a 3525 .global2_addr = 0x1c,
acddbd21 3526 .age_time_coeff = 15000,
dc30c35b 3527 .g1_irqs = 8,
e606ca36 3528 .atu_move_port_mask = 0xf,
b3e05aa1 3529 .multi_chip = true,
443d5a1b 3530 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3531 .ops = &mv88e6185_ops,
f81ec90f
VD		 3532 },
3533
1a3b39ec 3534 [MV88E6190] = {
107fcc10 3535 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 3536 .family = MV88E6XXX_FAMILY_6390,
3537 .name = "Marvell 88E6190",
3538 .num_databases = 4096,
3539 .num_ports = 11, /* 10 + Z80 */
931d1822 3540 .max_vid = 8191,
1a3b39ec
AL		 3541 .port_base_addr = 0x0,
3542 .global1_addr = 0x1b,
9069c13a 3543 .global2_addr = 0x1c,
443d5a1b 3544 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3545 .age_time_coeff = 3750,
1a3b39ec 3546 .g1_irqs = 9,
d6c5e6af 3547 .g2_irqs = 14,
f3645652 3548 .pvt = true,
b3e05aa1 3549 .multi_chip = true,
e606ca36 3550 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3551 .ops = &mv88e6190_ops,
3552 },
3553
3554 [MV88E6190X] = {
107fcc10 3555 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 3556 .family = MV88E6XXX_FAMILY_6390,
3557 .name = "Marvell 88E6190X",
3558 .num_databases = 4096,
3559 .num_ports = 11, /* 10 + Z80 */
931d1822 3560 .max_vid = 8191,
1a3b39ec
AL		 3561 .port_base_addr = 0x0,
3562 .global1_addr = 0x1b,
9069c13a 3563 .global2_addr = 0x1c,
b91e055c 3564 .age_time_coeff = 3750,
1a3b39ec 3565 .g1_irqs = 9,
d6c5e6af 3566 .g2_irqs = 14,
e606ca36 3567 .atu_move_port_mask = 0x1f,
f3645652 3568 .pvt = true,
b3e05aa1 3569 .multi_chip = true,
443d5a1b 3570 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3571 .ops = &mv88e6190x_ops,
3572 },
3573
3574 [MV88E6191] = {
107fcc10 3575 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 3576 .family = MV88E6XXX_FAMILY_6390,
3577 .name = "Marvell 88E6191",
3578 .num_databases = 4096,
3579 .num_ports = 11, /* 10 + Z80 */
931d1822 3580 .max_vid = 8191,
1a3b39ec
AL		 3581 .port_base_addr = 0x0,
3582 .global1_addr = 0x1b,
9069c13a 3583 .global2_addr = 0x1c,
b91e055c 3584 .age_time_coeff = 3750,
443d5a1b 3585 .g1_irqs = 9,
d6c5e6af 3586 .g2_irqs = 14,
e606ca36 3587 .atu_move_port_mask = 0x1f,
f3645652 3588 .pvt = true,
b3e05aa1 3589 .multi_chip = true,
443d5a1b 3590 .tag_protocol = DSA_TAG_PROTO_DSA,
2cf4cefb 3591 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3592 },
3593
f81ec90f 3594 [MV88E6240] = {
107fcc10 3595 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 3596 .family = MV88E6XXX_FAMILY_6352,
3597 .name = "Marvell 88E6240",
3598 .num_databases = 4096,
3599 .num_ports = 7,
3cf3c846 3600 .max_vid = 4095,
9dddd478 3601 .port_base_addr = 0x10,
a935c052 3602 .global1_addr = 0x1b,
9069c13a 3603 .global2_addr = 0x1c,
acddbd21 3604 .age_time_coeff = 15000,
dc30c35b 3605 .g1_irqs = 9,
d6c5e6af 3606 .g2_irqs = 10,
e606ca36 3607 .atu_move_port_mask = 0xf,
f3645652 3608 .pvt = true,
b3e05aa1 3609 .multi_chip = true,
443d5a1b 3610 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3611 .ops = &mv88e6240_ops,
f81ec90f
VD		 3612 },
3613
1a3b39ec 3614 [MV88E6290] = {
107fcc10 3615 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 3616 .family = MV88E6XXX_FAMILY_6390,
3617 .name = "Marvell 88E6290",
3618 .num_databases = 4096,
3619 .num_ports = 11, /* 10 + Z80 */
931d1822 3620 .max_vid = 8191,
1a3b39ec
AL		 3621 .port_base_addr = 0x0,
3622 .global1_addr = 0x1b,
9069c13a 3623 .global2_addr = 0x1c,
b91e055c 3624 .age_time_coeff = 3750,
1a3b39ec 3625 .g1_irqs = 9,
d6c5e6af 3626 .g2_irqs = 14,
e606ca36 3627 .atu_move_port_mask = 0x1f,
f3645652 3628 .pvt = true,
b3e05aa1 3629 .multi_chip = true,
443d5a1b 3630 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3631 .ops = &mv88e6290_ops,
3632 },
3633
f81ec90f 3634 [MV88E6320] = {
107fcc10 3635 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 3636 .family = MV88E6XXX_FAMILY_6320,
3637 .name = "Marvell 88E6320",
3638 .num_databases = 4096,
3639 .num_ports = 7,
3cf3c846 3640 .max_vid = 4095,
9dddd478 3641 .port_base_addr = 0x10,
a935c052 3642 .global1_addr = 0x1b,
9069c13a 3643 .global2_addr = 0x1c,
acddbd21 3644 .age_time_coeff = 15000,
dc30c35b 3645 .g1_irqs = 8,
e606ca36 3646 .atu_move_port_mask = 0xf,
f3645652 3647 .pvt = true,
b3e05aa1 3648 .multi_chip = true,
443d5a1b 3649 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3650 .ops = &mv88e6320_ops,
f81ec90f
VD		 3651 },
3652
3653 [MV88E6321] = {
107fcc10 3654 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 3655 .family = MV88E6XXX_FAMILY_6320,
3656 .name = "Marvell 88E6321",
3657 .num_databases = 4096,
3658 .num_ports = 7,
3cf3c846 3659 .max_vid = 4095,
9dddd478 3660 .port_base_addr = 0x10,
a935c052 3661 .global1_addr = 0x1b,
9069c13a 3662 .global2_addr = 0x1c,
acddbd21 3663 .age_time_coeff = 15000,
dc30c35b 3664 .g1_irqs = 8,
e606ca36 3665 .atu_move_port_mask = 0xf,
b3e05aa1 3666 .multi_chip = true,
443d5a1b 3667 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3668 .ops = &mv88e6321_ops,
f81ec90f
VD		 3669 },
3670
a75961d0 3671 [MV88E6341] = {
107fcc10 3672 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 3673 .family = MV88E6XXX_FAMILY_6341,
3674 .name = "Marvell 88E6341",
3675 .num_databases = 4096,
3676 .num_ports = 6,
3cf3c846 3677 .max_vid = 4095,
a75961d0
GC		 3678 .port_base_addr = 0x10,
3679 .global1_addr = 0x1b,
9069c13a 3680 .global2_addr = 0x1c,
a75961d0 3681 .age_time_coeff = 3750,
e606ca36 3682 .atu_move_port_mask = 0x1f,
d6c5e6af 3683 .g2_irqs = 10,
f3645652 3684 .pvt = true,
b3e05aa1 3685 .multi_chip = true,
a75961d0 3686 .tag_protocol = DSA_TAG_PROTO_EDSA,
a75961d0
GC		 3687 .ops = &mv88e6341_ops,
3688 },
3689
f81ec90f 3690 [MV88E6350] = {
107fcc10 3691 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 3692 .family = MV88E6XXX_FAMILY_6351,
3693 .name = "Marvell 88E6350",
3694 .num_databases = 4096,
3695 .num_ports = 7,
3cf3c846 3696 .max_vid = 4095,
9dddd478 3697 .port_base_addr = 0x10,
a935c052 3698 .global1_addr = 0x1b,
9069c13a 3699 .global2_addr = 0x1c,
acddbd21 3700 .age_time_coeff = 15000,
dc30c35b 3701 .g1_irqs = 9,
d6c5e6af 3702 .g2_irqs = 10,
e606ca36 3703 .atu_move_port_mask = 0xf,
f3645652 3704 .pvt = true,
b3e05aa1 3705 .multi_chip = true,
443d5a1b 3706 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3707 .ops = &mv88e6350_ops,
f81ec90f
VD		 3708 },
3709
3710 [MV88E6351] = {
107fcc10 3711 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 3712 .family = MV88E6XXX_FAMILY_6351,
3713 .name = "Marvell 88E6351",
3714 .num_databases = 4096,
3715 .num_ports = 7,
3cf3c846 3716 .max_vid = 4095,
9dddd478 3717 .port_base_addr = 0x10,
a935c052 3718 .global1_addr = 0x1b,
9069c13a 3719 .global2_addr = 0x1c,
acddbd21 3720 .age_time_coeff = 15000,
dc30c35b 3721 .g1_irqs = 9,
d6c5e6af 3722 .g2_irqs = 10,
e606ca36 3723 .atu_move_port_mask = 0xf,
f3645652 3724 .pvt = true,
b3e05aa1 3725 .multi_chip = true,
443d5a1b 3726 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3727 .ops = &mv88e6351_ops,
f81ec90f
VD		 3728 },
3729
3730 [MV88E6352] = {
107fcc10 3731 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 3732 .family = MV88E6XXX_FAMILY_6352,
3733 .name = "Marvell 88E6352",
3734 .num_databases = 4096,
3735 .num_ports = 7,
3cf3c846 3736 .max_vid = 4095,
9dddd478 3737 .port_base_addr = 0x10,
a935c052 3738 .global1_addr = 0x1b,
9069c13a 3739 .global2_addr = 0x1c,
acddbd21 3740 .age_time_coeff = 15000,
dc30c35b 3741 .g1_irqs = 9,
d6c5e6af 3742 .g2_irqs = 10,
e606ca36 3743 .atu_move_port_mask = 0xf,
f3645652 3744 .pvt = true,
b3e05aa1 3745 .multi_chip = true,
443d5a1b 3746 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3747 .ops = &mv88e6352_ops,
f81ec90f 3748 },
1a3b39ec 3749 [MV88E6390] = {
107fcc10 3750 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 3751 .family = MV88E6XXX_FAMILY_6390,
3752 .name = "Marvell 88E6390",
3753 .num_databases = 4096,
3754 .num_ports = 11, /* 10 + Z80 */
931d1822 3755 .max_vid = 8191,
1a3b39ec
AL		 3756 .port_base_addr = 0x0,
3757 .global1_addr = 0x1b,
9069c13a 3758 .global2_addr = 0x1c,
b91e055c 3759 .age_time_coeff = 3750,
1a3b39ec 3760 .g1_irqs = 9,
d6c5e6af 3761 .g2_irqs = 14,
e606ca36 3762 .atu_move_port_mask = 0x1f,
f3645652 3763 .pvt = true,
b3e05aa1 3764 .multi_chip = true,
443d5a1b 3765 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3766 .ops = &mv88e6390_ops,
3767 },
3768 [MV88E6390X] = {
107fcc10 3769 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 3770 .family = MV88E6XXX_FAMILY_6390,
3771 .name = "Marvell 88E6390X",
3772 .num_databases = 4096,
3773 .num_ports = 11, /* 10 + Z80 */
931d1822 3774 .max_vid = 8191,
1a3b39ec
AL		 3775 .port_base_addr = 0x0,
3776 .global1_addr = 0x1b,
9069c13a 3777 .global2_addr = 0x1c,
b91e055c 3778 .age_time_coeff = 3750,
1a3b39ec 3779 .g1_irqs = 9,
d6c5e6af 3780 .g2_irqs = 14,
e606ca36 3781 .atu_move_port_mask = 0x1f,
f3645652 3782 .pvt = true,
b3e05aa1 3783 .multi_chip = true,
443d5a1b 3784 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3785 .ops = &mv88e6390x_ops,
3786 },
f81ec90f
VD		 3787};
3788
5f7c0367 3789static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3790{
a439c061 3791 int i;
b9b37713 3792
5f7c0367
VD		 3793 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3794 if (mv88e6xxx_table[i].prod_num == prod_num)
3795 return &mv88e6xxx_table[i];
b9b37713 3796
b9b37713
VD		 3797 return NULL;
3798}
3799
fad09c73 3800static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3801{
3802 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3803 unsigned int prod_num, rev;
3804 u16 id;
3805 int err;
bc46a3d5 3806
8f6345b2 3807 mutex_lock(&chip->reg_lock);
107fcc10 3808 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
8f6345b2
VD		 3809 mutex_unlock(&chip->reg_lock);
3810 if (err)
3811 return err;
bc46a3d5 3812
107fcc10
VD		 3813 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3814 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 3815
3816 info = mv88e6xxx_lookup_info(prod_num);
3817 if (!info)
3818 return -ENODEV;
3819
caac8545 3820 /* Update the compatible info with the probed one */
fad09c73 3821 chip->info = info;
bc46a3d5 3822
ca070c10
VD		 3823 err = mv88e6xxx_g2_require(chip);
3824 if (err)
3825 return err;
3826
fad09c73
VD		 3827 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3828 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3829
3830 return 0;
3831}
3832
fad09c73 3833static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3834{
fad09c73 3835 struct mv88e6xxx_chip *chip;
469d729f 3836
fad09c73
VD		 3837 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3838 if (!chip)
469d729f
VD		 3839 return NULL;
3840
fad09c73 3841 chip->dev = dev;
469d729f 3842
fad09c73 3843 mutex_init(&chip->reg_lock);
a3c53be5 3844 INIT_LIST_HEAD(&chip->mdios);
469d729f 3845
fad09c73 3846 return chip;
469d729f
VD		 3847}
3848
fad09c73 3849static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3850 struct mii_bus *bus, int sw_addr)
3851{
914b32f6 3852 if (sw_addr == 0)
fad09c73 3853 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
b3e05aa1 3854 else if (chip->info->multi_chip)
fad09c73 3855 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3856 else
3857 return -EINVAL;
3858
fad09c73
VD		 3859 chip->bus = bus;
3860 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3861
3862 return 0;
3863}
3864
5ed4e3eb
FF		 3865static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
3866 int port)
7b314362 3867{
04bed143 3868 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 3869
443d5a1b 3870 return chip->info->tag_protocol;
7b314362
AL		 3871}
3872
fcdce7d0
AL		 3873static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3874 struct device *host_dev, int sw_addr,
3875 void **priv)
a77d43f1 3876{
fad09c73 3877 struct mv88e6xxx_chip *chip;
a439c061 3878 struct mii_bus *bus;
b516d453 3879 int err;
a77d43f1 3880
a439c061 3881 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3882 if (!bus)
3883 return NULL;
3884
fad09c73
VD		 3885 chip = mv88e6xxx_alloc_chip(dsa_dev);
3886 if (!chip)
469d729f
VD		 3887 return NULL;
3888
caac8545 3889 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3890 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3891
fad09c73 3892 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3893 if (err)
3894 goto free;
3895
fad09c73 3896 err = mv88e6xxx_detect(chip);
bc46a3d5 3897 if (err)
469d729f 3898 goto free;
a439c061 3899
dc30c35b
AL		 3900 mutex_lock(&chip->reg_lock);
3901 err = mv88e6xxx_switch_reset(chip);
3902 mutex_unlock(&chip->reg_lock);
3903 if (err)
3904 goto free;
3905
e57e5e77
VD		 3906 mv88e6xxx_phy_init(chip);
3907
a3c53be5 3908 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 3909 if (err)
469d729f 3910 goto free;
b516d453 3911
fad09c73 3912 *priv = chip;
a439c061 3913
fad09c73 3914 return chip->info->name;
469d729f 3915free:
fad09c73 3916 devm_kfree(dsa_dev, chip);
469d729f
VD		 3917
3918 return NULL;
a77d43f1
AL		 3919}
3920
7df8fbdd
VD		 3921static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3922 const struct switchdev_obj_port_mdb *mdb,
3923 struct switchdev_trans *trans)
3924{
3925 /* We don't need any dynamic resource from the kernel (yet),
3926 * so skip the prepare phase.
3927 */
3928
3929 return 0;
3930}
3931
3932static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3933 const struct switchdev_obj_port_mdb *mdb,
3934 struct switchdev_trans *trans)
3935{
04bed143 3936 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3937
3938 mutex_lock(&chip->reg_lock);
3939 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3940 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
774439e5
VD		 3941 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3942 port);
7df8fbdd
VD		 3943 mutex_unlock(&chip->reg_lock);
3944}
3945
3946static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3947 const struct switchdev_obj_port_mdb *mdb)
3948{
04bed143 3949 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3950 int err;
3951
3952 mutex_lock(&chip->reg_lock);
3953 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3954 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
7df8fbdd
VD		 3955 mutex_unlock(&chip->reg_lock);
3956
3957 return err;
3958}
3959
a82f67af 3960static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3961 .probe = mv88e6xxx_drv_probe,
7b314362 3962 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f 3963 .setup = mv88e6xxx_setup,
f81ec90f
VD		 3964 .adjust_link = mv88e6xxx_adjust_link,
3965 .get_strings = mv88e6xxx_get_strings,
3966 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3967 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 3968 .port_enable = mv88e6xxx_port_enable,
3969 .port_disable = mv88e6xxx_port_disable,
08f50061
VD		 3970 .get_mac_eee = mv88e6xxx_get_mac_eee,
3971 .set_mac_eee = mv88e6xxx_set_mac_eee,
f8cd8753 3972 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3973 .get_eeprom = mv88e6xxx_get_eeprom,
3974 .set_eeprom = mv88e6xxx_set_eeprom,
3975 .get_regs_len = mv88e6xxx_get_regs_len,
3976 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3977 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3978 .port_bridge_join = mv88e6xxx_port_bridge_join,
3979 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3980 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3981 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3982 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3983 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3984 .port_vlan_add = mv88e6xxx_port_vlan_add,
3985 .port_vlan_del = mv88e6xxx_port_vlan_del,
f81ec90f
VD		 3986 .port_fdb_add = mv88e6xxx_port_fdb_add,
3987 .port_fdb_del = mv88e6xxx_port_fdb_del,
3988 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3989 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3990 .port_mdb_add = mv88e6xxx_port_mdb_add,
3991 .port_mdb_del = mv88e6xxx_port_mdb_del,
aec5ac88
VD		 3992 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3993 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 3994};
3995
ab3d408d
FF		 3996static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3997 .ops = &mv88e6xxx_switch_ops,
3998};
3999
55ed0ce0 4000static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4001{
fad09c73 4002 struct device *dev = chip->dev;
b7e66a5f
VD		 4003 struct dsa_switch *ds;
4004
73b1204d 4005 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 4006 if (!ds)
4007 return -ENOMEM;
4008
fad09c73 4009 ds->priv = chip;
9d490b4e 4010 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 4011 ds->ageing_time_min = chip->info->age_time_coeff;
4012 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 4013
4014 dev_set_drvdata(dev, ds);
4015
23c9ee49 4016 return dsa_register_switch(ds);
b7e66a5f
VD		 4017}
4018
fad09c73 4019static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4020{
fad09c73 4021 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4022}
4023
57d32310 4024static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4025{
14c7b3c3 4026 struct device *dev = &mdiodev->dev;
f8cd8753 4027 struct device_node *np = dev->of_node;
caac8545 4028 const struct mv88e6xxx_info *compat_info;
fad09c73 4029 struct mv88e6xxx_chip *chip;
f8cd8753 4030 u32 eeprom_len;
52638f71 4031 int err;
14c7b3c3 4032
caac8545
VD		 4033 compat_info = of_device_get_match_data(dev);
4034 if (!compat_info)
4035 return -EINVAL;
4036
fad09c73
VD		 4037 chip = mv88e6xxx_alloc_chip(dev);
4038 if (!chip)
14c7b3c3
AL		 4039 return -ENOMEM;
4040
fad09c73 4041 chip->info = compat_info;
caac8545 4042
fad09c73 4043 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4044 if (err)
4045 return err;
14c7b3c3 4046
b4308f04
AL		 4047 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4048 if (IS_ERR(chip->reset))
4049 return PTR_ERR(chip->reset);
4050
fad09c73 4051 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4052 if (err)
4053 return err;
14c7b3c3 4054
e57e5e77
VD		 4055 mv88e6xxx_phy_init(chip);
4056
ee4dc2e7 4057 if (chip->info->ops->get_eeprom &&
f8cd8753 4058 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4059 chip->eeprom_len = eeprom_len;
f8cd8753 4060
dc30c35b
AL		 4061 mutex_lock(&chip->reg_lock);
4062 err = mv88e6xxx_switch_reset(chip);
4063 mutex_unlock(&chip->reg_lock);
4064 if (err)
4065 goto out;
4066
4067 chip->irq = of_irq_get(np, 0);
4068 if (chip->irq == -EPROBE_DEFER) {
4069 err = chip->irq;
4070 goto out;
4071 }
4072
4073 if (chip->irq > 0) {
4074 /* Has to be performed before the MDIO bus is created,
4075 * because the PHYs will link there interrupts to these
4076 * interrupt controllers
4077 */
4078 mutex_lock(&chip->reg_lock);
4079 err = mv88e6xxx_g1_irq_setup(chip);
4080 mutex_unlock(&chip->reg_lock);
4081
4082 if (err)
4083 goto out;
4084
d6c5e6af 4085 if (chip->info->g2_irqs > 0) {
dc30c35b
AL		 4086 err = mv88e6xxx_g2_irq_setup(chip);
4087 if (err)
4088 goto out_g1_irq;
4089 }
4090 }
4091
a3c53be5 4092 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4093 if (err)
dc30c35b 4094 goto out_g2_irq;
b516d453 4095
55ed0ce0 4096 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4097 if (err)
4098 goto out_mdio;
83c0afae 4099
98e67308 4100 return 0;
dc30c35b
AL		 4101
4102out_mdio:
a3c53be5 4103 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4104out_g2_irq:
d6c5e6af 4105 if (chip->info->g2_irqs > 0 && chip->irq > 0)
dc30c35b
AL		 4106 mv88e6xxx_g2_irq_free(chip);
4107out_g1_irq:
61f7c3f8
AL		 4108 if (chip->irq > 0) {
4109 mutex_lock(&chip->reg_lock);
46712644 4110 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4111 mutex_unlock(&chip->reg_lock);
4112 }
dc30c35b
AL		 4113out:
4114 return err;
98e67308 4115}
14c7b3c3
AL		 4116
4117static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4118{
4119 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4120 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4121
930188ce 4122 mv88e6xxx_phy_destroy(chip);
fad09c73 4123 mv88e6xxx_unregister_switch(chip);
a3c53be5 4124 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4125
46712644 4126 if (chip->irq > 0) {
d6c5e6af 4127 if (chip->info->g2_irqs > 0)
46712644 4128 mv88e6xxx_g2_irq_free(chip);
b32ca44a 4129 mutex_lock(&chip->reg_lock);
46712644 4130 mv88e6xxx_g1_irq_free(chip);
b32ca44a 4131 mutex_unlock(&chip->reg_lock);
46712644 4132 }
14c7b3c3
AL		 4133}
4134
4135static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4136 {
4137 .compatible = "marvell,mv88e6085",
4138 .data = &mv88e6xxx_table[MV88E6085],
4139 },
1a3b39ec
AL		 4140 {
4141 .compatible = "marvell,mv88e6190",
4142 .data = &mv88e6xxx_table[MV88E6190],
4143 },
14c7b3c3
AL		 4144 { /* sentinel */ },
4145};
4146
4147MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4148
4149static struct mdio_driver mv88e6xxx_driver = {
4150 .probe = mv88e6xxx_probe,
4151 .remove = mv88e6xxx_remove,
4152 .mdiodrv.driver = {
4153 .name = "mv88e6085",
4154 .of_match_table = mv88e6xxx_of_match,
4155 },
4156};
4157
4158static int __init mv88e6xxx_init(void)
4159{
ab3d408d 4160 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4161 return mdio_driver_register(&mv88e6xxx_driver);
4162}
98e67308
BH		 4163module_init(mv88e6xxx_init);
4164
4165static void __exit mv88e6xxx_cleanup(void)
4166{
14c7b3c3 4167 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4168 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4169}
4170module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4171
4172MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4173MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4174MODULE_LICENSE("GPL");
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