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[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
14c7b3c3
AL		 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7 *
4333d619
VD		 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
ec561276 35
4d5f2ba7 36#include "chip.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
6d91782f 41#include "serdes.h"
91da11f8 42
fad09c73 43static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 44{
fad09c73
VD		 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
46 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 47 dump_stack();
48 }
49}
50
914b32f6
VD		 51/* The switch ADDR[4:1] configuration pins define the chip SMI device address
52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 *
54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
55 * is the only device connected to the SMI master. In this mode it responds to
56 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 *
58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
59 * multiple devices to share the SMI interface. In this mode it responds to only
60 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 61 */
914b32f6 62
fad09c73 63static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 *val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 val)
74{
fad09c73 75 if (!chip->smi_ops)
914b32f6
VD		 76 return -EOPNOTSUPP;
77
fad09c73 78 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 79}
80
fad09c73 81static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 82 int addr, int reg, u16 *val)
83{
84 int ret;
85
fad09c73 86 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 87 if (ret < 0)
88 return ret;
89
90 *val = ret & 0xffff;
91
92 return 0;
93}
94
fad09c73 95static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 96 int addr, int reg, u16 val)
97{
98 int ret;
99
fad09c73 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 101 if (ret < 0)
102 return ret;
103
104 return 0;
105}
106
c08026ab 107static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 108 .read = mv88e6xxx_smi_single_chip_read,
109 .write = mv88e6xxx_smi_single_chip_write,
110};
111
fad09c73 112static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 113{
114 int ret;
115 int i;
116
117 for (i = 0; i < 16; i++) {
fad09c73 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 119 if (ret < 0)
120 return ret;
121
cca8b133 122 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 123 return 0;
124 }
125
126 return -ETIMEDOUT;
127}
128
fad09c73 129static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 130 int addr, int reg, u16 *val)
91da11f8
LB		 131{
132 int ret;
133
3675c8d7 134 /* Wait for the bus to become free. */
fad09c73 135 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the read command. */
fad09c73 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 141 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the read command to complete. */
fad09c73 146 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 147 if (ret < 0)
148 return ret;
149
3675c8d7 150 /* Read the data. */
fad09c73 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 152 if (ret < 0)
153 return ret;
154
914b32f6 155 *val = ret & 0xffff;
91da11f8 156
914b32f6 157 return 0;
8d6d09e7
GR		 158}
159
fad09c73 160static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 161 int addr, int reg, u16 val)
91da11f8
LB		 162{
163 int ret;
164
3675c8d7 165 /* Wait for the bus to become free. */
fad09c73 166 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 167 if (ret < 0)
168 return ret;
169
3675c8d7 170 /* Transmit the data to write. */
fad09c73 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 172 if (ret < 0)
173 return ret;
174
3675c8d7 175 /* Transmit the write command. */
fad09c73 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 178 if (ret < 0)
179 return ret;
180
3675c8d7 181 /* Wait for the write command to complete. */
fad09c73 182 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 183 if (ret < 0)
184 return ret;
185
186 return 0;
187}
188
c08026ab 189static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 190 .read = mv88e6xxx_smi_multi_chip_read,
191 .write = mv88e6xxx_smi_multi_chip_write,
192};
193
ec561276 194int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 195{
196 int err;
197
fad09c73 198 assert_reg_lock(chip);
914b32f6 199
fad09c73 200 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 201 if (err)
202 return err;
203
fad09c73 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 205 addr, reg, *val);
206
207 return 0;
208}
209
ec561276 210int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 211{
914b32f6
VD		 212 int err;
213
fad09c73 214 assert_reg_lock(chip);
91da11f8 215
fad09c73 216 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 217 if (err)
218 return err;
219
fad09c73 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 221 addr, reg, val);
222
914b32f6
VD		 223 return 0;
224}
225
10fa5bfc 226struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 227{
228 struct mv88e6xxx_mdio_bus *mdio_bus;
229
230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
231 list);
232 if (!mdio_bus)
233 return NULL;
234
235 return mdio_bus->bus;
236}
237
dc30c35b
AL		 238static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
239{
240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
241 unsigned int n = d->hwirq;
242
243 chip->g1_irq.masked |= (1 << n);
244}
245
246static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
247{
248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
249 unsigned int n = d->hwirq;
250
251 chip->g1_irq.masked &= ~(1 << n);
252}
253
254static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
255{
256 struct mv88e6xxx_chip *chip = dev_id;
257 unsigned int nhandled = 0;
258 unsigned int sub_irq;
259 unsigned int n;
260 u16 reg;
261 int err;
262
263 mutex_lock(&chip->reg_lock);
82466921 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b
AL		 265 mutex_unlock(&chip->reg_lock);
266
267 if (err)
268 goto out;
269
270 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
271 if (reg & (1 << n)) {
272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
273 handle_nested_irq(sub_irq);
274 ++nhandled;
275 }
276 }
277out:
278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
279}
280
281static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
282{
283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
284
285 mutex_lock(&chip->reg_lock);
286}
287
288static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
289{
290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
292 u16 reg;
293 int err;
294
d77f4321 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 296 if (err)
297 goto out;
298
299 reg &= ~mask;
300 reg |= (~chip->g1_irq.masked & mask);
301
d77f4321 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 303 if (err)
304 goto out;
305
306out:
307 mutex_unlock(&chip->reg_lock);
308}
309
310static struct irq_chip mv88e6xxx_g1_irq_chip = {
311 .name = "mv88e6xxx-g1",
312 .irq_mask = mv88e6xxx_g1_irq_mask,
313 .irq_unmask = mv88e6xxx_g1_irq_unmask,
314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
316};
317
318static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
319 unsigned int irq,
320 irq_hw_number_t hwirq)
321{
322 struct mv88e6xxx_chip *chip = d->host_data;
323
324 irq_set_chip_data(irq, d->host_data);
325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
326 irq_set_noprobe(irq);
327
328 return 0;
329}
330
331static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
332 .map = mv88e6xxx_g1_irq_domain_map,
333 .xlate = irq_domain_xlate_twocell,
334};
335
336static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
337{
338 int irq, virq;
3460a577
AL		 339 u16 mask;
340
d77f4321 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3460a577 342 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577
AL		 344
345 free_irq(chip->irq, chip);
dc30c35b 346
5edef2f2 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 348 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 349 irq_dispose_mapping(virq);
350 }
351
a3db3d3a 352 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 353}
354
355static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
356{
3dd0ef05
AL		 357 int err, irq, virq;
358 u16 reg, mask;
dc30c35b
AL		 359
360 chip->g1_irq.nirqs = chip->info->g1_irqs;
361 chip->g1_irq.domain = irq_domain_add_simple(
362 NULL, chip->g1_irq.nirqs, 0,
363 &mv88e6xxx_g1_irq_domain_ops, chip);
364 if (!chip->g1_irq.domain)
365 return -ENOMEM;
366
367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
368 irq_create_mapping(chip->g1_irq.domain, irq);
369
370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
371 chip->g1_irq.masked = ~0;
372
d77f4321 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 374 if (err)
3dd0ef05 375 goto out_mapping;
dc30c35b 376
3dd0ef05 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 378
d77f4321 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 380 if (err)
3dd0ef05 381 goto out_disable;
dc30c35b
AL		 382
383 /* Reading the interrupt status clears (most of) them */
82466921 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 385 if (err)
3dd0ef05 386 goto out_disable;
dc30c35b
AL		 387
388 err = request_threaded_irq(chip->irq, NULL,
389 mv88e6xxx_g1_irq_thread_fn,
390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
391 dev_name(chip->dev), chip);
392 if (err)
3dd0ef05 393 goto out_disable;
dc30c35b
AL		 394
395 return 0;
396
3dd0ef05
AL		 397out_disable:
398 mask |= GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 400
401out_mapping:
402 for (irq = 0; irq < 16; irq++) {
403 virq = irq_find_mapping(chip->g1_irq.domain, irq);
404 irq_dispose_mapping(virq);
405 }
406
407 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 408
409 return err;
410}
411
ec561276 412int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 413{
6441e669 414 int i;
2d79af6e 415
6441e669 416 for (i = 0; i < 16; i++) {
2d79af6e
VD		 417 u16 val;
418 int err;
419
420 err = mv88e6xxx_read(chip, addr, reg, &val);
421 if (err)
422 return err;
423
424 if (!(val & mask))
425 return 0;
426
427 usleep_range(1000, 2000);
428 }
429
30853553 430 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 431 return -ETIMEDOUT;
432}
433
f22ab641 434/* Indirect write to single pointer-data register with an Update bit */
ec561276 435int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 436{
437 u16 val;
0f02b4f7 438 int err;
f22ab641
VD		 439
440 /* Wait until the previous operation is completed */
0f02b4f7
AL		 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
442 if (err)
443 return err;
f22ab641
VD		 444
445 /* Set the Update bit to trigger a write operation */
446 val = BIT(15) | update;
447
448 return mv88e6xxx_write(chip, addr, reg, val);
449}
450
d78343d2
VD		 451static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
452 int link, int speed, int duplex,
453 phy_interface_t mode)
454{
455 int err;
456
457 if (!chip->info->ops->port_set_link)
458 return 0;
459
460 /* Port's MAC control must not be changed unless the link is down */
461 err = chip->info->ops->port_set_link(chip, port, 0);
462 if (err)
463 return err;
464
465 if (chip->info->ops->port_set_speed) {
466 err = chip->info->ops->port_set_speed(chip, port, speed);
467 if (err && err != -EOPNOTSUPP)
468 goto restore_link;
469 }
470
471 if (chip->info->ops->port_set_duplex) {
472 err = chip->info->ops->port_set_duplex(chip, port, duplex);
473 if (err && err != -EOPNOTSUPP)
474 goto restore_link;
475 }
476
477 if (chip->info->ops->port_set_rgmii_delay) {
478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
479 if (err && err != -EOPNOTSUPP)
480 goto restore_link;
481 }
482
f39908d3
AL		 483 if (chip->info->ops->port_set_cmode) {
484 err = chip->info->ops->port_set_cmode(chip, port, mode);
485 if (err && err != -EOPNOTSUPP)
486 goto restore_link;
487 }
488
d78343d2
VD		 489 err = 0;
490restore_link:
491 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 493
494 return err;
495}
496
dea87024
AL		 497/* We expect the switch to perform auto negotiation if there is a real
498 * phy. However, in the case of a fixed link phy, we force the port
499 * settings from the fixed link settings.
500 */
f81ec90f
VD		 501static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
502 struct phy_device *phydev)
dea87024 503{
04bed143 504 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 505 int err;
dea87024
AL		 506
507 if (!phy_is_pseudo_fixed_link(phydev))
508 return;
509
fad09c73 510 mutex_lock(&chip->reg_lock);
d78343d2
VD		 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
512 phydev->duplex, phydev->interface);
fad09c73 513 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 514
515 if (err && err != -EOPNOTSUPP)
774439e5 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
dea87024
AL		 517}
518
a605a0fe 519static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 520{
a605a0fe
AL		 521 if (!chip->info->ops->stats_snapshot)
522 return -EOPNOTSUPP;
91da11f8 523
a605a0fe 524 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 525}
526
e413e7e1 527static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
548 { "single", 4, 0x14, STATS_TYPE_BANK0, },
549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
551 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 587};
588
fad09c73 589static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 590 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 591 int port, u16 bank1_select,
592 u16 histogram)
80c4627b 593{
80c4627b
AL		 594 u32 low;
595 u32 high = 0;
dfafe449 596 u16 reg = 0;
0e7b9925 597 int err;
80c4627b
AL		 598 u64 value;
599
f5e2ed02 600 switch (s->type) {
dfafe449 601 case STATS_TYPE_PORT:
0e7b9925
AL		 602 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
603 if (err)
80c4627b
AL		 604 return UINT64_MAX;
605
0e7b9925 606 low = reg;
80c4627b 607 if (s->sizeof_stat == 4) {
0e7b9925
AL		 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
609 if (err)
80c4627b 610 return UINT64_MAX;
0e7b9925 611 high = reg;
80c4627b 612 }
f5e2ed02 613 break;
dfafe449 614 case STATS_TYPE_BANK1:
e0d8b615 615 reg = bank1_select;
dfafe449
AL		 616 /* fall through */
617 case STATS_TYPE_BANK0:
e0d8b615 618 reg |= s->reg | histogram;
7f9ef3af 619 mv88e6xxx_g1_stats_read(chip, reg, &low);
80c4627b 620 if (s->sizeof_stat == 8)
7f9ef3af 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 622 break;
623 default:
624 return UINT64_MAX;
80c4627b
AL		 625 }
626 value = (((u64)high) << 16) | low;
627 return value;
628}
629
dfafe449
AL		 630static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
631 uint8_t *data, int types)
91da11f8 632{
f5e2ed02
AL		 633 struct mv88e6xxx_hw_stat *stat;
634 int i, j;
91da11f8 635
f5e2ed02
AL		 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
637 stat = &mv88e6xxx_hw_stats[i];
dfafe449 638 if (stat->type & types) {
f5e2ed02
AL		 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
640 ETH_GSTRING_LEN);
641 j++;
642 }
91da11f8 643 }
e413e7e1
AL		 644}
645
dfafe449
AL		 646static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
647 uint8_t *data)
648{
649 mv88e6xxx_stats_get_strings(chip, data,
650 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
651}
652
653static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
654 uint8_t *data)
655{
656 mv88e6xxx_stats_get_strings(chip, data,
657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
658}
659
660static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
661 uint8_t *data)
e413e7e1 662{
04bed143 663 struct mv88e6xxx_chip *chip = ds->priv;
dfafe449
AL		 664
665 if (chip->info->ops->stats_get_strings)
666 chip->info->ops->stats_get_strings(chip, data);
667}
668
669static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
670 int types)
671{
f5e2ed02
AL		 672 struct mv88e6xxx_hw_stat *stat;
673 int i, j;
674
675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
676 stat = &mv88e6xxx_hw_stats[i];
dfafe449 677 if (stat->type & types)
f5e2ed02
AL		 678 j++;
679 }
680 return j;
e413e7e1
AL		 681}
682
dfafe449
AL		 683static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
684{
685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
686 STATS_TYPE_PORT);
687}
688
689static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
690{
691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
692 STATS_TYPE_BANK1);
693}
694
695static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
696{
697 struct mv88e6xxx_chip *chip = ds->priv;
698
699 if (chip->info->ops->stats_get_sset_count)
700 return chip->info->ops->stats_get_sset_count(chip);
701
702 return 0;
703}
704
052f947f 705static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
e0d8b615
AL		 706 uint64_t *data, int types,
707 u16 bank1_select, u16 histogram)
052f947f
AL		 708{
709 struct mv88e6xxx_hw_stat *stat;
710 int i, j;
711
712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
713 stat = &mv88e6xxx_hw_stats[i];
714 if (stat->type & types) {
e0d8b615
AL		 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
716 bank1_select,
717 histogram);
052f947f
AL		 718 j++;
719 }
720 }
721}
722
723static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
724 uint64_t *data)
725{
726 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 729}
730
731static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
732 uint64_t *data)
733{
734 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 738}
739
740static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
741 uint64_t *data)
742{
743 return mv88e6xxx_stats_get_stats(chip, port, data,
744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
746 0);
052f947f
AL		 747}
748
749static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
750 uint64_t *data)
751{
752 if (chip->info->ops->stats_get_stats)
753 chip->info->ops->stats_get_stats(chip, port, data);
754}
755
f81ec90f
VD		 756static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
757 uint64_t *data)
e413e7e1 758{
04bed143 759 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 760 int ret;
f5e2ed02 761
fad09c73 762 mutex_lock(&chip->reg_lock);
f5e2ed02 763
a605a0fe 764 ret = mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 765 if (ret < 0) {
fad09c73 766 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 767 return;
768 }
052f947f
AL		 769
770 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 771
fad09c73 772 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 773}
774
de227387
AL		 775static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
776{
777 if (chip->info->ops->stats_set_histogram)
778 return chip->info->ops->stats_set_histogram(chip);
779
780 return 0;
781}
782
f81ec90f 783static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 784{
785 return 32 * sizeof(u16);
786}
787
f81ec90f
VD		 788static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
789 struct ethtool_regs *regs, void *_p)
a1ab91f3 790{
04bed143 791 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 792 int err;
793 u16 reg;
a1ab91f3
GR		 794 u16 *p = _p;
795 int i;
796
797 regs->version = 0;
798
799 memset(p, 0xff, 32 * sizeof(u16));
800
fad09c73 801 mutex_lock(&chip->reg_lock);
23062513 802
a1ab91f3 803 for (i = 0; i < 32; i++) {
a1ab91f3 804
0e7b9925
AL		 805 err = mv88e6xxx_port_read(chip, port, i, &reg);
806 if (!err)
807 p[i] = reg;
a1ab91f3 808 }
23062513 809
fad09c73 810 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 811}
812
68b8f60c
VD		 813static int mv88e6xxx_energy_detect_read(struct mv88e6xxx_chip *chip, int port,
814 struct ethtool_eee *eee)
11b3b45d 815{
9c93829c 816 int err;
11b3b45d 817
68b8f60c 818 if (!chip->info->ops->phy_energy_detect_read)
aadbdb8a
VD		 819 return -EOPNOTSUPP;
820
68b8f60c
VD		 821 /* assign eee->eee_enabled and eee->tx_lpi_enabled */
822 err = chip->info->ops->phy_energy_detect_read(chip, port, eee);
9c93829c 823 if (err)
68b8f60c 824 return err;
11b3b45d 825
68b8f60c
VD		 826 /* assign eee->eee_active */
827 return mv88e6xxx_port_status_eee(chip, port, eee);
828}
11b3b45d 829
68b8f60c
VD		 830static int mv88e6xxx_energy_detect_write(struct mv88e6xxx_chip *chip, int port,
831 struct ethtool_eee *eee)
832{
833 if (!chip->info->ops->phy_energy_detect_write)
834 return -EOPNOTSUPP;
11b3b45d 835
68b8f60c
VD		 836 return chip->info->ops->phy_energy_detect_write(chip, port, eee);
837}
838
839static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
840 struct ethtool_eee *e)
841{
842 struct mv88e6xxx_chip *chip = ds->priv;
843 int err;
844
845 mutex_lock(&chip->reg_lock);
846 err = mv88e6xxx_energy_detect_read(chip, port, e);
fad09c73 847 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 848
849 return err;
11b3b45d
GR		 850}
851
f81ec90f
VD		 852static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
853 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 854{
04bed143 855 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 856 int err;
11b3b45d 857
fad09c73 858 mutex_lock(&chip->reg_lock);
68b8f60c 859 err = mv88e6xxx_energy_detect_write(chip, port, e);
fad09c73 860 mutex_unlock(&chip->reg_lock);
2f40c698 861
9c93829c 862 return err;
11b3b45d
GR		 863}
864
e5887a2a 865static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 866{
e5887a2a
VD		 867 struct dsa_switch *ds = NULL;
868 struct net_device *br;
869 u16 pvlan;
b7666efe
VD		 870 int i;
871
e5887a2a
VD		 872 if (dev < DSA_MAX_SWITCHES)
873 ds = chip->ds->dst->ds[dev];
874
875 /* Prevent frames from unknown switch or port */
876 if (!ds || port >= ds->num_ports)
877 return 0;
878
879 /* Frames from DSA links and CPU ports can egress any local port */
880 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
881 return mv88e6xxx_port_mask(chip);
882
883 br = ds->ports[port].bridge_dev;
884 pvlan = 0;
885
886 /* Frames from user ports can egress any local DSA links and CPU ports,
887 * as well as any local member of their bridge group.
888 */
889 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
890 if (dsa_is_cpu_port(chip->ds, i) ||
891 dsa_is_dsa_port(chip->ds, i) ||
892 (br && chip->ds->ports[i].bridge_dev == br))
893 pvlan |= BIT(i);
894
895 return pvlan;
896}
897
240ea3ef 898static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 899{
900 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 901
902 /* prevent frames from going back out of the port they came in on */
903 output_ports &= ~BIT(port);
facd95b2 904
5a7921f4 905 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 906}
907
f81ec90f
VD		 908static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
909 u8 state)
facd95b2 910{
04bed143 911 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 912 int err;
facd95b2 913
fad09c73 914 mutex_lock(&chip->reg_lock);
f894c29c 915 err = mv88e6xxx_port_set_state(chip, port, state);
fad09c73 916 mutex_unlock(&chip->reg_lock);
553eb544
VD		 917
918 if (err)
774439e5 919 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 920}
921
9e907d73
VD		 922static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
923{
924 if (chip->info->ops->pot_clear)
925 return chip->info->ops->pot_clear(chip);
926
927 return 0;
928}
929
51c901a7
VD		 930static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
931{
932 if (chip->info->ops->mgmt_rsvd2cpu)
933 return chip->info->ops->mgmt_rsvd2cpu(chip);
934
935 return 0;
936}
937
a2ac29d2
VD		 938static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
939{
c3a7d4ad
VD		 940 int err;
941
daefc943
VD		 942 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
943 if (err)
944 return err;
945
c3a7d4ad
VD		 946 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
947 if (err)
948 return err;
949
a2ac29d2
VD		 950 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
951}
952
cd8da8bb
VD		 953static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
954{
955 int port;
956 int err;
957
958 if (!chip->info->ops->irl_init_all)
959 return 0;
960
961 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
962 /* Disable ingress rate limiting by resetting all per port
963 * ingress rate limit resources to their initial state.
964 */
965 err = chip->info->ops->irl_init_all(chip, port);
966 if (err)
967 return err;
968 }
969
970 return 0;
971}
972
17a1594e
VD		 973static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
974{
975 u16 pvlan = 0;
976
977 if (!mv88e6xxx_has_pvt(chip))
978 return -EOPNOTSUPP;
979
980 /* Skip the local source device, which uses in-chip port VLAN */
981 if (dev != chip->ds->index)
aec5ac88 982 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e
VD		 983
984 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
985}
986
81228996
VD		 987static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
988{
17a1594e
VD		 989 int dev, port;
990 int err;
991
81228996
VD		 992 if (!mv88e6xxx_has_pvt(chip))
993 return 0;
994
995 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
996 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
997 */
17a1594e
VD		 998 err = mv88e6xxx_g2_misc_4_bit_port(chip);
999 if (err)
1000 return err;
1001
1002 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1003 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1004 err = mv88e6xxx_pvt_map(chip, dev, port);
1005 if (err)
1006 return err;
1007 }
1008 }
1009
1010 return 0;
81228996
VD		 1011}
1012
749efcb8
VD		 1013static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1014{
1015 struct mv88e6xxx_chip *chip = ds->priv;
1016 int err;
1017
1018 mutex_lock(&chip->reg_lock);
e606ca36 1019 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
749efcb8
VD		 1020 mutex_unlock(&chip->reg_lock);
1021
1022 if (err)
774439e5 1023 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 1024}
1025
b486d7c9
VD		 1026static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1027{
1028 if (!chip->info->max_vid)
1029 return 0;
1030
1031 return mv88e6xxx_g1_vtu_flush(chip);
1032}
1033
f1394b78
VD		 1034static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1035 struct mv88e6xxx_vtu_entry *entry)
1036{
1037 if (!chip->info->ops->vtu_getnext)
1038 return -EOPNOTSUPP;
1039
1040 return chip->info->ops->vtu_getnext(chip, entry);
1041}
1042
0ad5daf6
VD		 1043static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1044 struct mv88e6xxx_vtu_entry *entry)
1045{
1046 if (!chip->info->ops->vtu_loadpurge)
1047 return -EOPNOTSUPP;
1048
1049 return chip->info->ops->vtu_loadpurge(chip, entry);
1050}
1051
f81ec90f
VD		 1052static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1053 struct switchdev_obj_port_vlan *vlan,
438ff537 1054 switchdev_obj_dump_cb_t *cb)
ceff5eff 1055{
04bed143 1056 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1057 struct mv88e6xxx_vtu_entry next = {
1058 .vid = chip->info->max_vid,
1059 };
ceff5eff
VD		 1060 u16 pvid;
1061 int err;
1062
3cf3c846 1063 if (!chip->info->max_vid)
54d77b5b
VD		 1064 return -EOPNOTSUPP;
1065
fad09c73 1066 mutex_lock(&chip->reg_lock);
ceff5eff 1067
77064f37 1068 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1069 if (err)
1070 goto unlock;
1071
ceff5eff 1072 do {
f1394b78 1073 err = mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1074 if (err)
1075 break;
1076
1077 if (!next.valid)
1078 break;
1079
7ec60d6e
VD		 1080 if (next.member[port] ==
1081 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
ceff5eff
VD		 1082 continue;
1083
1084 /* reinit and dump this VLAN obj */
57d32310
VD		 1085 vlan->vid_begin = next.vid;
1086 vlan->vid_end = next.vid;
ceff5eff
VD		 1087 vlan->flags = 0;
1088
7ec60d6e
VD		 1089 if (next.member[port] ==
1090 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED)
ceff5eff
VD		 1091 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1092
1093 if (next.vid == pvid)
1094 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1095
1096 err = cb(&vlan->obj);
1097 if (err)
1098 break;
3cf3c846 1099 } while (next.vid < chip->info->max_vid);
ceff5eff
VD		 1100
1101unlock:
fad09c73 1102 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1103
1104 return err;
1105}
1106
d7f435f9 1107static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1108{
1109 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
3afb4bde
VD		 1110 struct mv88e6xxx_vtu_entry vlan = {
1111 .vid = chip->info->max_vid,
1112 };
2db9ce1f 1113 int i, err;
3285f9e8
VD		 1114
1115 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1116
2db9ce1f 1117 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1118 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1119 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1120 if (err)
1121 return err;
1122
1123 set_bit(*fid, fid_bitmap);
1124 }
1125
3285f9e8 1126 /* Set every FID bit used by the VLAN entries */
3285f9e8 1127 do {
f1394b78 1128 err = mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1129 if (err)
1130 return err;
1131
1132 if (!vlan.valid)
1133 break;
1134
1135 set_bit(vlan.fid, fid_bitmap);
3cf3c846 1136 } while (vlan.vid < chip->info->max_vid);
3285f9e8
VD		 1137
1138 /* The reset value 0x000 is used to indicate that multiple address
1139 * databases are not needed. Return the next positive available.
1140 */
1141 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1142 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1143 return -ENOSPC;
1144
1145 /* Clear the database */
daefc943 1146 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1147}
1148
567aa59a
VD		 1149static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1150 struct mv88e6xxx_vtu_entry *entry, bool new)
2fb5ef09
VD		 1151{
1152 int err;
1153
1154 if (!vid)
1155 return -EINVAL;
1156
3afb4bde
VD		 1157 entry->vid = vid - 1;
1158 entry->valid = false;
2fb5ef09 1159
f1394b78 1160 err = mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1161 if (err)
1162 return err;
1163
567aa59a
VD		 1164 if (entry->vid == vid && entry->valid)
1165 return 0;
2fb5ef09 1166
567aa59a
VD		 1167 if (new) {
1168 int i;
1169
1170 /* Initialize a fresh VLAN entry */
1171 memset(entry, 0, sizeof(*entry));
1172 entry->valid = true;
1173 entry->vid = vid;
1174
553a768d 1175 /* Exclude all ports */
567aa59a 1176 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
553a768d 1177 entry->member[i] =
7ec60d6e 1178 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
567aa59a
VD		 1179
1180 return mv88e6xxx_atu_new(chip, &entry->fid);
2fb5ef09
VD		 1181 }
1182
567aa59a
VD		 1183 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1184 return -EOPNOTSUPP;
2fb5ef09
VD		 1185}
1186
da9c359e
VD		 1187static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1188 u16 vid_begin, u16 vid_end)
1189{
04bed143 1190 struct mv88e6xxx_chip *chip = ds->priv;
3afb4bde
VD		 1191 struct mv88e6xxx_vtu_entry vlan = {
1192 .vid = vid_begin - 1,
1193 };
da9c359e
VD		 1194 int i, err;
1195
1196 if (!vid_begin)
1197 return -EOPNOTSUPP;
1198
fad09c73 1199 mutex_lock(&chip->reg_lock);
da9c359e 1200
da9c359e 1201 do {
f1394b78 1202 err = mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1203 if (err)
1204 goto unlock;
1205
1206 if (!vlan.valid)
1207 break;
1208
1209 if (vlan.vid > vid_end)
1210 break;
1211
370b4ffb 1212 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1213 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1214 continue;
1215
66e2809d
AL		 1216 if (!ds->ports[port].netdev)
1217 continue;
1218
bd00e053 1219 if (vlan.member[i] ==
7ec60d6e 1220 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
da9c359e
VD		 1221 continue;
1222
fae8a25e
VD		 1223 if (ds->ports[i].bridge_dev ==
1224 ds->ports[port].bridge_dev)
da9c359e
VD		 1225 break; /* same bridge, check next VLAN */
1226
fae8a25e 1227 if (!ds->ports[i].bridge_dev)
66e2809d
AL		 1228 continue;
1229
774439e5
VD		 1230 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
1231 port, vlan.vid,
1232 netdev_name(ds->ports[i].bridge_dev));
da9c359e
VD		 1233 err = -EOPNOTSUPP;
1234 goto unlock;
1235 }
1236 } while (vlan.vid < vid_end);
1237
1238unlock:
fad09c73 1239 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1240
1241 return err;
1242}
1243
f81ec90f
VD		 1244static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1245 bool vlan_filtering)
214cdb99 1246{
04bed143 1247 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1248 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1249 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1250 int err;
214cdb99 1251
3cf3c846 1252 if (!chip->info->max_vid)
54d77b5b
VD		 1253 return -EOPNOTSUPP;
1254
fad09c73 1255 mutex_lock(&chip->reg_lock);
385a0995 1256 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1257 mutex_unlock(&chip->reg_lock);
214cdb99 1258
0e7b9925 1259 return err;
214cdb99
VD		 1260}
1261
57d32310
VD		 1262static int
1263mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1264 const struct switchdev_obj_port_vlan *vlan,
1265 struct switchdev_trans *trans)
76e398a6 1266{
04bed143 1267 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1268 int err;
1269
3cf3c846 1270 if (!chip->info->max_vid)
54d77b5b
VD		 1271 return -EOPNOTSUPP;
1272
da9c359e
VD		 1273 /* If the requested port doesn't belong to the same bridge as the VLAN
1274 * members, do not support it (yet) and fallback to software VLAN.
1275 */
1276 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1277 vlan->vid_end);
1278 if (err)
1279 return err;
1280
76e398a6
VD		 1281 /* We don't need any dynamic resource from the kernel (yet),
1282 * so skip the prepare phase.
1283 */
1284 return 0;
1285}
1286
fad09c73 1287static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
c91498e1 1288 u16 vid, u8 member)
0d3b33e6 1289{
b4e47c0f 1290 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1291 int err;
1292
567aa59a 1293 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1294 if (err)
76e398a6 1295 return err;
0d3b33e6 1296
c91498e1 1297 vlan.member[port] = member;
0d3b33e6 1298
0ad5daf6 1299 return mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1300}
1301
f81ec90f
VD		 1302static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1303 const struct switchdev_obj_port_vlan *vlan,
1304 struct switchdev_trans *trans)
76e398a6 1305{
04bed143 1306 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1307 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1308 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
c91498e1 1309 u8 member;
76e398a6 1310 u16 vid;
76e398a6 1311
3cf3c846 1312 if (!chip->info->max_vid)
54d77b5b
VD		 1313 return;
1314
c91498e1 1315 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 1316 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 1317 else if (untagged)
7ec60d6e 1318 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 1319 else
7ec60d6e 1320 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 1321
fad09c73 1322 mutex_lock(&chip->reg_lock);
76e398a6 1323
4d5770b3 1324 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
c91498e1 1325 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
774439e5
VD		 1326 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1327 vid, untagged ? 'u' : 't');
76e398a6 1328
77064f37 1329 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
774439e5
VD		 1330 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1331 vlan->vid_end);
0d3b33e6 1332
fad09c73 1333 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1334}
1335
fad09c73 1336static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1337 int port, u16 vid)
7dad08d7 1338{
b4e47c0f 1339 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1340 int i, err;
1341
567aa59a 1342 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1343 if (err)
76e398a6 1344 return err;
7dad08d7 1345
2fb5ef09 1346 /* Tell switchdev if this VLAN is handled in software */
7ec60d6e 1347 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1348 return -EOPNOTSUPP;
7dad08d7 1349
7ec60d6e 1350 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 1351
1352 /* keep the VLAN unless all ports are excluded */
f02bdffc 1353 vlan.valid = false;
370b4ffb 1354 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 1355 if (vlan.member[i] !=
1356 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1357 vlan.valid = true;
7dad08d7
VD		 1358 break;
1359 }
1360 }
1361
0ad5daf6 1362 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1363 if (err)
1364 return err;
1365
e606ca36 1366 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1367}
1368
f81ec90f
VD		 1369static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1370 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1371{
04bed143 1372 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1373 u16 pvid, vid;
1374 int err = 0;
1375
3cf3c846 1376 if (!chip->info->max_vid)
54d77b5b
VD		 1377 return -EOPNOTSUPP;
1378
fad09c73 1379 mutex_lock(&chip->reg_lock);
76e398a6 1380
77064f37 1381 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1382 if (err)
1383 goto unlock;
1384
76e398a6 1385 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1386 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1387 if (err)
1388 goto unlock;
1389
1390 if (vid == pvid) {
77064f37 1391 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1392 if (err)
1393 goto unlock;
1394 }
1395 }
1396
7dad08d7 1397unlock:
fad09c73 1398 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1399
1400 return err;
1401}
1402
83dabd1f
VD		 1403static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1404 const unsigned char *addr, u16 vid,
1405 u8 state)
fd231c82 1406{
b4e47c0f 1407 struct mv88e6xxx_vtu_entry vlan;
88472939 1408 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 1409 int err;
1410
2db9ce1f
VD		 1411 /* Null VLAN ID corresponds to the port private database */
1412 if (vid == 0)
b4e48c50 1413 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 1414 else
567aa59a 1415 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 1416 if (err)
1417 return err;
fd231c82 1418
27c0e600 1419 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96
VD		 1420 ether_addr_copy(entry.mac, addr);
1421 eth_addr_dec(entry.mac);
1422
1423 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
88472939
VD		 1424 if (err)
1425 return err;
1426
dabc1a96 1427 /* Initialize a fresh ATU entry if it isn't found */
27c0e600 1428 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
dabc1a96
VD		 1429 !ether_addr_equal(entry.mac, addr)) {
1430 memset(&entry, 0, sizeof(entry));
1431 ether_addr_copy(entry.mac, addr);
1432 }
1433
88472939 1434 /* Purge the ATU entry only if no port is using it anymore */
27c0e600 1435 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
01bd96c8
VD		 1436 entry.portvec &= ~BIT(port);
1437 if (!entry.portvec)
27c0e600 1438 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
88472939 1439 } else {
01bd96c8 1440 entry.portvec |= BIT(port);
88472939 1441 entry.state = state;
fd231c82
VD		 1442 }
1443
9c13c026 1444 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
87820510
VD		 1445}
1446
f81ec90f
VD		 1447static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1448 const struct switchdev_obj_port_fdb *fdb,
1449 struct switchdev_trans *trans)
146a3206
VD		 1450{
1451 /* We don't need any dynamic resource from the kernel (yet),
1452 * so skip the prepare phase.
1453 */
1454 return 0;
1455}
1456
f81ec90f
VD		 1457static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1458 const struct switchdev_obj_port_fdb *fdb,
1459 struct switchdev_trans *trans)
87820510 1460{
04bed143 1461 struct mv88e6xxx_chip *chip = ds->priv;
87820510 1462
fad09c73 1463 mutex_lock(&chip->reg_lock);
83dabd1f 1464 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
27c0e600 1465 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC))
774439e5
VD		 1466 dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
1467 port);
fad09c73 1468 mutex_unlock(&chip->reg_lock);
87820510
VD		 1469}
1470
f81ec90f
VD		 1471static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1472 const struct switchdev_obj_port_fdb *fdb)
87820510 1473{
04bed143 1474 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 1475 int err;
87820510 1476
fad09c73 1477 mutex_lock(&chip->reg_lock);
83dabd1f 1478 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
27c0e600 1479 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
fad09c73 1480 mutex_unlock(&chip->reg_lock);
87820510 1481
83dabd1f 1482 return err;
87820510
VD		 1483}
1484
83dabd1f
VD		 1485static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1486 u16 fid, u16 vid, int port,
1487 struct switchdev_obj *obj,
438ff537 1488 switchdev_obj_dump_cb_t *cb)
74b6ba0d 1489{
dabc1a96 1490 struct mv88e6xxx_atu_entry addr;
74b6ba0d
VD		 1491 int err;
1492
27c0e600 1493 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
dabc1a96 1494 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 1495
1496 do {
dabc1a96 1497 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 1498 if (err)
83dabd1f 1499 return err;
74b6ba0d 1500
27c0e600 1501 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
74b6ba0d
VD		 1502 break;
1503
01bd96c8 1504 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 1505 continue;
1506
1507 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
1508 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 1509
83dabd1f
VD		 1510 if (!is_unicast_ether_addr(addr.mac))
1511 continue;
1512
1513 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 1514 fdb->vid = vid;
1515 ether_addr_copy(fdb->addr, addr.mac);
27c0e600 1516 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
83dabd1f
VD		 1517 fdb->ndm_state = NUD_NOARP;
1518 else
1519 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 1520 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
1521 struct switchdev_obj_port_mdb *mdb;
1522
1523 if (!is_multicast_ether_addr(addr.mac))
1524 continue;
1525
1526 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
1527 mdb->vid = vid;
1528 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 1529 } else {
1530 return -EOPNOTSUPP;
74b6ba0d 1531 }
83dabd1f
VD		 1532
1533 err = cb(obj);
1534 if (err)
1535 return err;
74b6ba0d
VD		 1536 } while (!is_broadcast_ether_addr(addr.mac));
1537
1538 return err;
1539}
1540
83dabd1f
VD		 1541static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1542 struct switchdev_obj *obj,
438ff537 1543 switchdev_obj_dump_cb_t *cb)
f33475bd 1544{
b4e47c0f 1545 struct mv88e6xxx_vtu_entry vlan = {
3cf3c846 1546 .vid = chip->info->max_vid,
f33475bd 1547 };
2db9ce1f 1548 u16 fid;
f33475bd
VD		 1549 int err;
1550
2db9ce1f 1551 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 1552 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 1553 if (err)
83dabd1f 1554 return err;
2db9ce1f 1555
83dabd1f 1556 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 1557 if (err)
83dabd1f 1558 return err;
2db9ce1f 1559
74b6ba0d 1560 /* Dump VLANs' Filtering Information Databases */
f33475bd 1561 do {
f1394b78 1562 err = mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 1563 if (err)
83dabd1f 1564 return err;
f33475bd
VD		 1565
1566 if (!vlan.valid)
1567 break;
1568
83dabd1f
VD		 1569 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1570 obj, cb);
f33475bd 1571 if (err)
83dabd1f 1572 return err;
3cf3c846 1573 } while (vlan.vid < chip->info->max_vid);
f33475bd 1574
83dabd1f
VD		 1575 return err;
1576}
1577
1578static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1579 struct switchdev_obj_port_fdb *fdb,
438ff537 1580 switchdev_obj_dump_cb_t *cb)
83dabd1f 1581{
04bed143 1582 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 1583 int err;
1584
1585 mutex_lock(&chip->reg_lock);
1586 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 1587 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 1588
1589 return err;
1590}
1591
240ea3ef
VD		 1592static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1593 struct net_device *br)
e79a8bcb 1594{
e96a6e02 1595 struct dsa_switch *ds;
240ea3ef 1596 int port;
e96a6e02 1597 int dev;
240ea3ef 1598 int err;
466dfa07 1599
240ea3ef
VD		 1600 /* Remap the Port VLAN of each local bridge group member */
1601 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1602 if (chip->ds->ports[port].bridge_dev == br) {
1603 err = mv88e6xxx_port_vlan_map(chip, port);
b7666efe 1604 if (err)
240ea3ef 1605 return err;
b7666efe
VD		 1606 }
1607 }
1608
e96a6e02
VD		 1609 if (!mv88e6xxx_has_pvt(chip))
1610 return 0;
1611
1612 /* Remap the Port VLAN of each cross-chip bridge group member */
1613 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1614 ds = chip->ds->dst->ds[dev];
1615 if (!ds)
1616 break;
1617
1618 for (port = 0; port < ds->num_ports; ++port) {
1619 if (ds->ports[port].bridge_dev == br) {
1620 err = mv88e6xxx_pvt_map(chip, dev, port);
1621 if (err)
1622 return err;
1623 }
1624 }
1625 }
1626
240ea3ef
VD		 1627 return 0;
1628}
1629
1630static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1631 struct net_device *br)
1632{
1633 struct mv88e6xxx_chip *chip = ds->priv;
1634 int err;
1635
1636 mutex_lock(&chip->reg_lock);
1637 err = mv88e6xxx_bridge_map(chip, br);
fad09c73 1638 mutex_unlock(&chip->reg_lock);
a6692754 1639
466dfa07 1640 return err;
e79a8bcb
VD		 1641}
1642
f123f2fb
VD		 1643static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1644 struct net_device *br)
66d9cd0f 1645{
04bed143 1646 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 1647
fad09c73 1648 mutex_lock(&chip->reg_lock);
240ea3ef
VD		 1649 if (mv88e6xxx_bridge_map(chip, br) ||
1650 mv88e6xxx_port_vlan_map(chip, port))
1651 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
fad09c73 1652 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 1653}
1654
aec5ac88
VD		 1655static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1656 int port, struct net_device *br)
1657{
1658 struct mv88e6xxx_chip *chip = ds->priv;
1659 int err;
1660
1661 if (!mv88e6xxx_has_pvt(chip))
1662 return 0;
1663
1664 mutex_lock(&chip->reg_lock);
1665 err = mv88e6xxx_pvt_map(chip, dev, port);
1666 mutex_unlock(&chip->reg_lock);
1667
1668 return err;
1669}
1670
1671static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1672 int port, struct net_device *br)
1673{
1674 struct mv88e6xxx_chip *chip = ds->priv;
1675
1676 if (!mv88e6xxx_has_pvt(chip))
1677 return;
1678
1679 mutex_lock(&chip->reg_lock);
1680 if (mv88e6xxx_pvt_map(chip, dev, port))
1681 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1682 mutex_unlock(&chip->reg_lock);
1683}
1684
17e708ba
VD		 1685static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1686{
1687 if (chip->info->ops->reset)
1688 return chip->info->ops->reset(chip);
1689
1690 return 0;
1691}
1692
309eca6d
VD		 1693static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1694{
1695 struct gpio_desc *gpiod = chip->reset;
1696
1697 /* If there is a GPIO connected to the reset pin, toggle it */
1698 if (gpiod) {
1699 gpiod_set_value_cansleep(gpiod, 1);
1700 usleep_range(10000, 20000);
1701 gpiod_set_value_cansleep(gpiod, 0);
1702 usleep_range(10000, 20000);
1703 }
1704}
1705
4ac4b5a6 1706static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 1707{
4ac4b5a6 1708 int i, err;
552238b5 1709
4ac4b5a6 1710 /* Set all ports to the Disabled state */
370b4ffb 1711 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 1712 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 1713 if (err)
1714 return err;
552238b5
VD		 1715 }
1716
4ac4b5a6
VD		 1717 /* Wait for transmit queues to drain,
1718 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1719 */
552238b5
VD		 1720 usleep_range(2000, 4000);
1721
4ac4b5a6
VD		 1722 return 0;
1723}
1724
1725static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1726{
4ac4b5a6
VD		 1727 int err;
1728
1729 err = mv88e6xxx_disable_ports(chip);
1730 if (err)
1731 return err;
1732
309eca6d 1733 mv88e6xxx_hardware_reset(chip);
552238b5 1734
17e708ba 1735 return mv88e6xxx_software_reset(chip);
552238b5
VD		 1736}
1737
4314557c 1738static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 1739 enum mv88e6xxx_frame_mode frame,
1740 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 1741{
1742 int err;
1743
4314557c
VD		 1744 if (!chip->info->ops->port_set_frame_mode)
1745 return -EOPNOTSUPP;
1746
1747 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 1748 if (err)
1749 return err;
1750
4314557c
VD		 1751 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1752 if (err)
1753 return err;
1754
1755 if (chip->info->ops->port_set_ether_type)
1756 return chip->info->ops->port_set_ether_type(chip, port, etype);
1757
1758 return 0;
56995cbc
AL		 1759}
1760
4314557c 1761static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 1762{
4314557c 1763 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 1764 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1765 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1766}
56995cbc 1767
4314557c
VD		 1768static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1769{
1770 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 1771 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 1772 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 1773}
56995cbc 1774
4314557c
VD		 1775static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1776{
1777 return mv88e6xxx_set_port_mode(chip, port,
1778 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 1779 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1780 ETH_P_EDSA);
4314557c 1781}
56995cbc 1782
4314557c
VD		 1783static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1784{
1785 if (dsa_is_dsa_port(chip->ds, port))
1786 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1787
4314557c
VD		 1788 if (dsa_is_normal_port(chip->ds, port))
1789 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 1790
4314557c
VD		 1791 /* Setup CPU port mode depending on its supported tag format */
1792 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1793 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 1794
4314557c
VD		 1795 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1796 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 1797
4314557c 1798 return -EINVAL;
56995cbc
AL		 1799}
1800
601aeed3 1801static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 1802{
601aeed3 1803 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 1804
601aeed3 1805 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 1806}
56995cbc 1807
601aeed3 1808static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 1809{
601aeed3 1810 bool flood = port == dsa_upstream_port(chip->ds);
56995cbc 1811
601aeed3
VD		 1812 /* Upstream ports flood frames with unknown unicast or multicast DA */
1813 if (chip->info->ops->port_set_egress_floods)
1814 return chip->info->ops->port_set_egress_floods(chip, port,
1815 flood, flood);
ea698f4f 1816
601aeed3 1817 return 0;
ea698f4f
VD		 1818}
1819
6d91782f
AL		 1820static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1821 bool on)
1822{
523a8904
VD		 1823 if (chip->info->ops->serdes_power)
1824 return chip->info->ops->serdes_power(chip, port, on);
04aca993 1825
523a8904 1826 return 0;
6d91782f
AL		 1827}
1828
fad09c73 1829static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 1830{
fad09c73 1831 struct dsa_switch *ds = chip->ds;
0e7b9925 1832 int err;
54d792f2 1833 u16 reg;
d827e88a 1834
d78343d2
VD		 1835 /* MAC Forcing register: don't force link, speed, duplex or flow control
1836 * state to any particular values on physical ports, but force the CPU
1837 * port and all DSA ports to their maximum bandwidth and full duplex.
1838 */
1839 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1840 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1841 SPEED_MAX, DUPLEX_FULL,
1842 PHY_INTERFACE_MODE_NA);
1843 else
1844 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1845 SPEED_UNFORCED, DUPLEX_UNFORCED,
1846 PHY_INTERFACE_MODE_NA);
1847 if (err)
1848 return err;
54d792f2
AL		 1849
1850 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1851 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1852 * tunneling, determine priority by looking at 802.1p and IP
1853 * priority fields (IP prio has precedence), and set STP state
1854 * to Forwarding.
1855 *
1856 * If this is the CPU link, use DSA or EDSA tagging depending
1857 * on which tagging mode was configured.
1858 *
1859 * If this is a link to another switch, use DSA tagging mode.
1860 *
1861 * If this is the upstream port for this switch, enable
1862 * forwarding of unknown unicasts and multicasts.
1863 */
a89b433b
VD		 1864 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1865 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1866 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1867 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 1868 if (err)
1869 return err;
6083ce71 1870
601aeed3 1871 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 1872 if (err)
1873 return err;
54d792f2 1874
601aeed3 1875 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 1876 if (err)
1877 return err;
1878
04aca993
AL		 1879 /* Enable the SERDES interface for DSA and CPU ports. Normal
1880 * ports SERDES are enabled when the port is enabled, thus
1881 * saving a bit of power.
13a7ebb3 1882 */
04aca993
AL		 1883 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1884 err = mv88e6xxx_serdes_power(chip, port, true);
1885 if (err)
1886 return err;
1887 }
13a7ebb3 1888
8efdda4a 1889 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 1890 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 1891 * untagged frames on this port, do a destination address lookup on all
1892 * received packets as usual, disable ARP mirroring and don't send a
1893 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 1894 */
a23b2961
AL		 1895 err = mv88e6xxx_port_set_map_da(chip, port);
1896 if (err)
1897 return err;
8efdda4a 1898
a23b2961
AL		 1899 reg = 0;
1900 if (chip->info->ops->port_set_upstream_port) {
1901 err = chip->info->ops->port_set_upstream_port(
1902 chip, port, dsa_upstream_port(ds));
0e7b9925
AL		 1903 if (err)
1904 return err;
54d792f2
AL		 1905 }
1906
a23b2961 1907 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 1908 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 1909 if (err)
1910 return err;
1911
cd782656
VD		 1912 if (chip->info->ops->port_set_jumbo_size) {
1913 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 1914 if (err)
1915 return err;
1916 }
1917
54d792f2
AL		 1918 /* Port Association Vector: when learning source addresses
1919 * of packets, add the address to the address database using
1920 * a port bitmap that has only the bit for this port set and
1921 * the other bits clear.
1922 */
4c7ea3c0 1923 reg = 1 << port;
996ecb82
VD		 1924 /* Disable learning for CPU port */
1925 if (dsa_is_cpu_port(ds, port))
65fa4027 1926 reg = 0;
4c7ea3c0 1927
2a4614e4
VD		 1928 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1929 reg);
0e7b9925
AL		 1930 if (err)
1931 return err;
54d792f2
AL		 1932
1933 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 1934 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
1935 0x0000);
0e7b9925
AL		 1936 if (err)
1937 return err;
54d792f2 1938
0898432c
VD		 1939 if (chip->info->ops->port_pause_limit) {
1940 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 1941 if (err)
1942 return err;
b35d322a 1943 }
54d792f2 1944
c8c94891
VD		 1945 if (chip->info->ops->port_disable_learn_limit) {
1946 err = chip->info->ops->port_disable_learn_limit(chip, port);
1947 if (err)
1948 return err;
1949 }
1950
9dbfb4e1
VD		 1951 if (chip->info->ops->port_disable_pri_override) {
1952 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 1953 if (err)
1954 return err;
ef0a7318 1955 }
2bbb33be 1956
ef0a7318
AL		 1957 if (chip->info->ops->port_tag_remap) {
1958 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 1959 if (err)
1960 return err;
54d792f2
AL		 1961 }
1962
ef70b111
AL		 1963 if (chip->info->ops->port_egress_rate_limiting) {
1964 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 1965 if (err)
1966 return err;
54d792f2
AL		 1967 }
1968
ea698f4f 1969 err = mv88e6xxx_setup_message_port(chip, port);
0e7b9925
AL		 1970 if (err)
1971 return err;
d827e88a 1972
207afda1 1973 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 1974 * database, and allow bidirectional communication between the
1975 * CPU and DSA port(s), and the other ports.
d827e88a 1976 */
b4e48c50 1977 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 1978 if (err)
1979 return err;
2db9ce1f 1980
240ea3ef 1981 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 1982 if (err)
1983 return err;
d827e88a
GR		 1984
1985 /* Default VLAN ID and priority: don't set a default VLAN
1986 * ID, and set the default packet priority to zero.
1987 */
b7929fb3 1988 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 1989}
1990
04aca993
AL		 1991static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
1992 struct phy_device *phydev)
1993{
1994 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 1995 int err;
04aca993
AL		 1996
1997 mutex_lock(&chip->reg_lock);
523a8904 1998 err = mv88e6xxx_serdes_power(chip, port, true);
04aca993
AL		 1999 mutex_unlock(&chip->reg_lock);
2000
2001 return err;
2002}
2003
2004static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2005 struct phy_device *phydev)
2006{
2007 struct mv88e6xxx_chip *chip = ds->priv;
2008
2009 mutex_lock(&chip->reg_lock);
523a8904
VD		 2010 if (mv88e6xxx_serdes_power(chip, port, false))
2011 dev_err(chip->dev, "failed to power off SERDES\n");
04aca993
AL		 2012 mutex_unlock(&chip->reg_lock);
2013}
2014
2cfcd964
VD		 2015static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2016 unsigned int ageing_time)
2017{
04bed143 2018 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2019 int err;
2020
2021 mutex_lock(&chip->reg_lock);
720c6343 2022 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2cfcd964
VD		 2023 mutex_unlock(&chip->reg_lock);
2024
2025 return err;
2026}
2027
9729934c 2028static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2029{
fad09c73 2030 struct dsa_switch *ds = chip->ds;
b0745e87 2031 u32 upstream_port = dsa_upstream_port(ds);
552238b5 2032 int err;
54d792f2 2033
fa8d1179
VD		 2034 if (chip->info->ops->set_cpu_port) {
2035 err = chip->info->ops->set_cpu_port(chip, upstream_port);
33641994
AL		 2036 if (err)
2037 return err;
2038 }
2039
fa8d1179
VD		 2040 if (chip->info->ops->set_egress_port) {
2041 err = chip->info->ops->set_egress_port(chip, upstream_port);
33641994
AL		 2042 if (err)
2043 return err;
2044 }
b0745e87 2045
50484ff4 2046 /* Disable remote management, and set the switch's DSA device number. */
d77f4321
VD		 2047 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2048 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
a935c052 2049 (ds->index & 0x1f));
50484ff4
VD		 2050 if (err)
2051 return err;
2052
54d792f2 2053 /* Configure the IP ToS mapping registers. */
ccba8f3a 2054 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
48ace4ef 2055 if (err)
08a01261 2056 return err;
ccba8f3a 2057 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
48ace4ef 2058 if (err)
08a01261 2059 return err;
ccba8f3a 2060 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
48ace4ef 2061 if (err)
08a01261 2062 return err;
ccba8f3a 2063 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
48ace4ef 2064 if (err)
08a01261 2065 return err;
ccba8f3a 2066 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
48ace4ef 2067 if (err)
08a01261 2068 return err;
ccba8f3a 2069 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
48ace4ef 2070 if (err)
08a01261 2071 return err;
ccba8f3a 2072 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
48ace4ef 2073 if (err)
08a01261 2074 return err;
ccba8f3a 2075 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
48ace4ef 2076 if (err)
08a01261 2077 return err;
54d792f2
AL		 2078
2079 /* Configure the IEEE 802.1p priority mapping register. */
ccba8f3a 2080 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
48ace4ef 2081 if (err)
08a01261 2082 return err;
54d792f2 2083
de227387
AL		 2084 /* Initialize the statistics unit */
2085 err = mv88e6xxx_stats_set_histogram(chip);
2086 if (err)
2087 return err;
2088
9729934c 2089 /* Clear the statistics counters for all ports */
57d1ef38
VD		 2090 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
2091 MV88E6XXX_G1_STATS_OP_BUSY |
2092 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
9729934c
VD		 2093 if (err)
2094 return err;
2095
2096 /* Wait for the flush to complete. */
7f9ef3af 2097 err = mv88e6xxx_g1_stats_wait(chip);
9729934c
VD		 2098 if (err)
2099 return err;
2100
2101 return 0;
2102}
2103
f81ec90f 2104static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2105{
04bed143 2106 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2107 int err;
a1a6a4d1
VD		 2108 int i;
2109
fad09c73 2110 chip->ds = ds;
a3c53be5 2111 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 2112
fad09c73 2113 mutex_lock(&chip->reg_lock);
08a01261 2114
9729934c 2115 /* Setup Switch Port Registers */
370b4ffb 2116 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2117 err = mv88e6xxx_setup_port(chip, i);
2118 if (err)
2119 goto unlock;
2120 }
2121
2122 /* Setup Switch Global 1 Registers */
2123 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2124 if (err)
2125 goto unlock;
2126
9729934c 2127 /* Setup Switch Global 2 Registers */
9069c13a 2128 if (chip->info->global2_addr) {
9729934c 2129 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2130 if (err)
2131 goto unlock;
2132 }
08a01261 2133
cd8da8bb
VD		 2134 err = mv88e6xxx_irl_setup(chip);
2135 if (err)
2136 goto unlock;
2137
1b17aedf
VD		 2138 err = mv88e6xxx_phy_setup(chip);
2139 if (err)
2140 goto unlock;
2141
b486d7c9
VD		 2142 err = mv88e6xxx_vtu_setup(chip);
2143 if (err)
2144 goto unlock;
2145
81228996
VD		 2146 err = mv88e6xxx_pvt_setup(chip);
2147 if (err)
2148 goto unlock;
2149
a2ac29d2
VD		 2150 err = mv88e6xxx_atu_setup(chip);
2151 if (err)
2152 goto unlock;
2153
9e907d73
VD		 2154 err = mv88e6xxx_pot_setup(chip);
2155 if (err)
2156 goto unlock;
2157
51c901a7
VD		 2158 err = mv88e6xxx_rsvd2cpu_setup(chip);
2159 if (err)
2160 goto unlock;
6e55f698 2161
6b17e864 2162unlock:
fad09c73 2163 mutex_unlock(&chip->reg_lock);
db687a56 2164
48ace4ef 2165 return err;
54d792f2
AL		 2166}
2167
3b4caa1b
VD		 2168static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2169{
04bed143 2170 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2171 int err;
2172
b073d4e2
VD		 2173 if (!chip->info->ops->set_switch_mac)
2174 return -EOPNOTSUPP;
3b4caa1b 2175
b073d4e2
VD		 2176 mutex_lock(&chip->reg_lock);
2177 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2178 mutex_unlock(&chip->reg_lock);
2179
2180 return err;
2181}
2182
e57e5e77 2183static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2184{
0dd12d54
AL		 2185 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2186 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77
VD		 2187 u16 val;
2188 int err;
fd3a0ee4 2189
ee26a228
AL		 2190 if (!chip->info->ops->phy_read)
2191 return -EOPNOTSUPP;
2192
fad09c73 2193 mutex_lock(&chip->reg_lock);
ee26a228 2194 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
fad09c73 2195 mutex_unlock(&chip->reg_lock);
e57e5e77 2196
da9f3301
AL		 2197 if (reg == MII_PHYSID2) {
2198 /* Some internal PHYS don't have a model number. Use
2199 * the mv88e6390 family model number instead.
2200 */
2201 if (!(val & 0x3f0))
107fcc10 2202 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
da9f3301
AL		 2203 }
2204
e57e5e77 2205 return err ? err : val;
fd3a0ee4
AL		 2206}
2207
e57e5e77 2208static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2209{
0dd12d54
AL		 2210 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2211 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 2212 int err;
fd3a0ee4 2213
ee26a228
AL		 2214 if (!chip->info->ops->phy_write)
2215 return -EOPNOTSUPP;
2216
fad09c73 2217 mutex_lock(&chip->reg_lock);
ee26a228 2218 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
fad09c73 2219 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2220
2221 return err;
fd3a0ee4
AL		 2222}
2223
fad09c73 2224static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 2225 struct device_node *np,
2226 bool external)
b516d453
AL		 2227{
2228 static int index;
0dd12d54 2229 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 2230 struct mii_bus *bus;
2231 int err;
2232
0dd12d54 2233 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 2234 if (!bus)
2235 return -ENOMEM;
2236
0dd12d54 2237 mdio_bus = bus->priv;
a3c53be5 2238 mdio_bus->bus = bus;
0dd12d54 2239 mdio_bus->chip = chip;
a3c53be5
AL		 2240 INIT_LIST_HEAD(&mdio_bus->list);
2241 mdio_bus->external = external;
0dd12d54 2242
b516d453
AL		 2243 if (np) {
2244 bus->name = np->full_name;
f7ce9103 2245 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
b516d453
AL		 2246 } else {
2247 bus->name = "mv88e6xxx SMI";
2248 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2249 }
2250
2251 bus->read = mv88e6xxx_mdio_read;
2252 bus->write = mv88e6xxx_mdio_write;
fad09c73 2253 bus->parent = chip->dev;
b516d453 2254
a3c53be5
AL		 2255 if (np)
2256 err = of_mdiobus_register(bus, np);
b516d453
AL		 2257 else
2258 err = mdiobus_register(bus);
2259 if (err) {
fad09c73 2260 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
a3c53be5 2261 return err;
b516d453 2262 }
a3c53be5
AL		 2263
2264 if (external)
2265 list_add_tail(&mdio_bus->list, &chip->mdios);
2266 else
2267 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 2268
2269 return 0;
a3c53be5 2270}
b516d453 2271
a3c53be5
AL		 2272static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2273 { .compatible = "marvell,mv88e6xxx-mdio-external",
2274 .data = (void *)true },
2275 { },
2276};
b516d453 2277
a3c53be5
AL		 2278static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2279 struct device_node *np)
2280{
2281 const struct of_device_id *match;
2282 struct device_node *child;
2283 int err;
2284
2285 /* Always register one mdio bus for the internal/default mdio
2286 * bus. This maybe represented in the device tree, but is
2287 * optional.
2288 */
2289 child = of_get_child_by_name(np, "mdio");
2290 err = mv88e6xxx_mdio_register(chip, child, false);
2291 if (err)
2292 return err;
2293
2294 /* Walk the device tree, and see if there are any other nodes
2295 * which say they are compatible with the external mdio
2296 * bus.
2297 */
2298 for_each_available_child_of_node(np, child) {
2299 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2300 if (match) {
2301 err = mv88e6xxx_mdio_register(chip, child, true);
2302 if (err)
2303 return err;
2304 }
2305 }
2306
2307 return 0;
b516d453
AL		 2308}
2309
a3c53be5 2310static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2311
2312{
a3c53be5
AL		 2313 struct mv88e6xxx_mdio_bus *mdio_bus;
2314 struct mii_bus *bus;
b516d453 2315
a3c53be5
AL		 2316 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2317 bus = mdio_bus->bus;
b516d453 2318
a3c53be5
AL		 2319 mdiobus_unregister(bus);
2320 }
b516d453
AL		 2321}
2322
855b1932
VD		 2323static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2324{
04bed143 2325 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2326
2327 return chip->eeprom_len;
2328}
2329
855b1932
VD		 2330static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2331 struct ethtool_eeprom *eeprom, u8 *data)
2332{
04bed143 2333 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2334 int err;
2335
ee4dc2e7
VD		 2336 if (!chip->info->ops->get_eeprom)
2337 return -EOPNOTSUPP;
855b1932 2338
ee4dc2e7
VD		 2339 mutex_lock(&chip->reg_lock);
2340 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 2341 mutex_unlock(&chip->reg_lock);
2342
2343 if (err)
2344 return err;
2345
2346 eeprom->magic = 0xc3ec4951;
2347
2348 return 0;
2349}
2350
855b1932
VD		 2351static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2352 struct ethtool_eeprom *eeprom, u8 *data)
2353{
04bed143 2354 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 2355 int err;
2356
ee4dc2e7
VD		 2357 if (!chip->info->ops->set_eeprom)
2358 return -EOPNOTSUPP;
2359
855b1932
VD		 2360 if (eeprom->magic != 0xc3ec4951)
2361 return -EINVAL;
2362
2363 mutex_lock(&chip->reg_lock);
ee4dc2e7 2364 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 2365 mutex_unlock(&chip->reg_lock);
2366
2367 return err;
2368}
2369
b3469dd8 2370static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 2371 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2372 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2373 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2374 .phy_read = mv88e6185_phy_ppu_read,
2375 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2376 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2377 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2378 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2379 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2380 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2381 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2382 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 2383 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2384 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2385 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2386 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2387 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2388 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2389 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2390 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2391 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2392 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2393 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2394 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2395 .pot_clear = mv88e6xxx_g2_pot_clear,
a199d8b6
VD		 2396 .ppu_enable = mv88e6185_g1_ppu_enable,
2397 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2398 .reset = mv88e6185_g1_reset,
f1394b78 2399 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2400 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2401};
2402
2403static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 2404 /* MV88E6XXX_FAMILY_6095 */
b073d4e2 2405 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2406 .phy_read = mv88e6185_phy_ppu_read,
2407 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2408 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2409 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2410 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2411 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2412 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
a23b2961 2413 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2414 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2415 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2416 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2417 .stats_get_stats = mv88e6095_stats_get_stats,
51c901a7 2418 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2419 .ppu_enable = mv88e6185_g1_ppu_enable,
2420 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2421 .reset = mv88e6185_g1_reset,
f1394b78 2422 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2423 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2424};
2425
7d381a02 2426static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 2427 /* MV88E6XXX_FAMILY_6097 */
cd8da8bb 2428 .irl_init_all = mv88e6352_g2_irl_init_all,
7d381a02
SE		 2429 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2430 .phy_read = mv88e6xxx_g2_smi_phy_read,
2431 .phy_write = mv88e6xxx_g2_smi_phy_write,
2432 .port_set_link = mv88e6xxx_port_set_link,
2433 .port_set_duplex = mv88e6xxx_port_set_duplex,
2434 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2435 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2436 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2437 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2438 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2439 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2440 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 2441 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2442 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2443 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
7d381a02
SE		 2444 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2445 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2446 .stats_get_strings = mv88e6095_stats_get_strings,
2447 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2448 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2449 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 2450 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2451 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2452 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2453 .reset = mv88e6352_g1_reset,
f1394b78 2454 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2455 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
7d381a02
SE		 2456};
2457
b3469dd8 2458static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 2459 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2460 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2461 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2462 .phy_read = mv88e6xxx_g2_smi_phy_read,
2463 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2464 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2465 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2466 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2467 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2468 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
c8c94891 2469 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2470 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2471 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2472 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2473 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2474 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2475 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2476 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2477 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2478 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2479 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2480 .reset = mv88e6352_g1_reset,
f1394b78 2481 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2482 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2483};
2484
2485static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 2486 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2487 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2488 .phy_read = mv88e6185_phy_ppu_read,
2489 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2490 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2491 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2492 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2493 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2494 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2495 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
56995cbc 2496 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 2497 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 2498 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2499 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2500 .port_pause_limit = mv88e6097_port_pause_limit,
a605a0fe 2501 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2502 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2503 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2504 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2505 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2506 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2507 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2508 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2509 .ppu_enable = mv88e6185_g1_ppu_enable,
2510 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2511 .reset = mv88e6185_g1_reset,
f1394b78 2512 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2513 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2514};
2515
990e27b0
VD		 2516static const struct mv88e6xxx_ops mv88e6141_ops = {
2517 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 2518 .irl_init_all = mv88e6352_g2_irl_init_all,
990e27b0
VD		 2519 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2520 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2522 .phy_read = mv88e6xxx_g2_smi_phy_read,
2523 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2524 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2525 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
990e27b0
VD		 2526 .port_set_link = mv88e6xxx_port_set_link,
2527 .port_set_duplex = mv88e6xxx_port_set_duplex,
2528 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2529 .port_set_speed = mv88e6390_port_set_speed,
2530 .port_tag_remap = mv88e6095_port_tag_remap,
2531 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2532 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2533 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2534 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 2535 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2536 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 2537 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2538 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2539 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2540 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2541 .stats_get_strings = mv88e6320_stats_get_strings,
2542 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2543 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2544 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 2545 .watchdog_ops = &mv88e6390_watchdog_ops,
2546 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2547 .pot_clear = mv88e6xxx_g2_pot_clear,
990e27b0 2548 .reset = mv88e6352_g1_reset,
f1394b78 2549 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2550 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
990e27b0
VD		 2551};
2552
b3469dd8 2553static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 2554 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2555 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 2557 .phy_read = mv88e6xxx_g2_smi_phy_read,
2558 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2559 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2560 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2561 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2562 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2563 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2564 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2565 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2566 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2567 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2568 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2569 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2570 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
0ac64c39 2571 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2572 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2573 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2574 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2575 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2576 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2577 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2578 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2579 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2580 .reset = mv88e6352_g1_reset,
f1394b78 2581 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2582 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2583};
2584
2585static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 2586 /* MV88E6XXX_FAMILY_6165 */
cd8da8bb 2587 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2588 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 2589 .phy_read = mv88e6165_phy_read,
2590 .phy_write = mv88e6165_phy_write,
08ef7f10 2591 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2592 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2593 .port_set_speed = mv88e6185_port_set_speed,
c8c94891 2594 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2595 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2596 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2597 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2598 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2599 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2600 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2601 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2602 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2604 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2605 .reset = mv88e6352_g1_reset,
f1394b78 2606 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2607 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2608};
2609
2610static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 2611 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2612 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2613 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2614 .phy_read = mv88e6xxx_g2_smi_phy_read,
2615 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2616 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2617 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2618 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2619 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2620 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2621 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2622 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2623 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2624 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2625 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2626 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2627 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2628 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2629 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2630 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2631 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2632 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2633 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2634 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2635 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2636 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2637 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2638 .reset = mv88e6352_g1_reset,
f1394b78 2639 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2640 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2641};
2642
2643static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 2644 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2645 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2646 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2647 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2648 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2649 .phy_read = mv88e6xxx_g2_smi_phy_read,
2650 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2651 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2652 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
08ef7f10 2653 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2654 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2655 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2656 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2657 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2658 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2659 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2660 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2661 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2662 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2663 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2666 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2667 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2668 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2669 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2670 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2671 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2672 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2673 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2674 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2675 .reset = mv88e6352_g1_reset,
f1394b78 2676 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2677 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2678 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2679};
2680
2681static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 2682 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 2683 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 2684 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2685 .phy_read = mv88e6xxx_g2_smi_phy_read,
2686 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 2687 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2688 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 2689 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2690 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2691 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2692 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2693 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2694 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2695 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2696 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2697 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2698 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2699 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2700 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2701 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2702 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2703 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2704 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2705 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2706 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2707 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2708 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2709 .reset = mv88e6352_g1_reset,
f1394b78 2710 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2711 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 2712};
2713
2714static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 2715 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2716 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2717 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2718 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2719 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2720 .phy_read = mv88e6xxx_g2_smi_phy_read,
2721 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2722 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2723 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
08ef7f10 2724 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2725 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2726 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2727 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2728 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2729 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2730 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2731 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2732 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2733 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2734 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2735 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2736 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2737 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2738 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2739 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2740 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2741 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2742 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2743 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2744 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2745 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2746 .reset = mv88e6352_g1_reset,
f1394b78 2747 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2748 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2749 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2750};
2751
2752static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 2753 /* MV88E6XXX_FAMILY_6185 */
b073d4e2 2754 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 2755 .phy_read = mv88e6185_phy_ppu_read,
2756 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 2757 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2758 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2759 .port_set_speed = mv88e6185_port_set_speed,
56995cbc 2760 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
601aeed3 2761 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
ef70b111 2762 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 2763 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
a605a0fe 2764 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
dfafe449
AL		 2765 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2766 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2767 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2768 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2769 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2770 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2771 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6
VD		 2772 .ppu_enable = mv88e6185_g1_ppu_enable,
2773 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 2774 .reset = mv88e6185_g1_reset,
f1394b78 2775 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2776 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2777};
2778
1a3b39ec 2779static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 2780 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2781 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2782 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2783 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2784 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2785 .phy_read = mv88e6xxx_g2_smi_phy_read,
2786 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2787 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2788 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
1a3b39ec
AL		 2789 .port_set_link = mv88e6xxx_port_set_link,
2790 .port_set_duplex = mv88e6xxx_port_set_duplex,
2791 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2792 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2793 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2794 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2795 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2796 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2797 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2800 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2801 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2802 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2803 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2804 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2805 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2806 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2807 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2808 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2809 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2810 .reset = mv88e6352_g1_reset,
931d1822
VD		 2811 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2812 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2813 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2814};
2815
2816static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 2817 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2818 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2819 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2820 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2821 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2822 .phy_read = mv88e6xxx_g2_smi_phy_read,
2823 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2824 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2825 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
1a3b39ec
AL		 2826 .port_set_link = mv88e6xxx_port_set_link,
2827 .port_set_duplex = mv88e6xxx_port_set_duplex,
2828 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2829 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 2830 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2831 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2832 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2833 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2834 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2835 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2836 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2837 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2838 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2839 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2840 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2841 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2842 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2843 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2844 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2845 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2846 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2847 .reset = mv88e6352_g1_reset,
931d1822
VD		 2848 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2849 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2850 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2851};
2852
2853static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 2854 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2855 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2856 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2857 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2858 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2859 .phy_read = mv88e6xxx_g2_smi_phy_read,
2860 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2861 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2862 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
1a3b39ec
AL		 2863 .port_set_link = mv88e6xxx_port_set_link,
2864 .port_set_duplex = mv88e6xxx_port_set_duplex,
2865 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2866 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2867 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2868 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2869 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2870 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2871 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 2872 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2873 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2874 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2875 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2876 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2877 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2878 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2879 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2880 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2881 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2882 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2883 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2884 .reset = mv88e6352_g1_reset,
931d1822
VD		 2885 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2886 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2887 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2888};
2889
b3469dd8 2890static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 2891 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 2892 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2893 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2894 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2895 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2896 .phy_read = mv88e6xxx_g2_smi_phy_read,
2897 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2898 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2899 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
08ef7f10 2900 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2901 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 2902 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 2903 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 2904 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2905 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2906 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2907 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2908 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2909 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2910 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2911 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2912 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2913 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2914 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2915 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 2916 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 2917 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2918 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 2919 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 2920 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2921 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2922 .reset = mv88e6352_g1_reset,
f1394b78 2923 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 2924 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 2925 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 2926};
2927
1a3b39ec 2928static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 2929 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 2930 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 2931 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2932 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 2933 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2934 .phy_read = mv88e6xxx_g2_smi_phy_read,
2935 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2936 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
2937 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
1a3b39ec
AL		 2938 .port_set_link = mv88e6xxx_port_set_link,
2939 .port_set_duplex = mv88e6xxx_port_set_duplex,
2940 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2941 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 2942 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 2943 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2944 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2945 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 2946 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 2947 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 2948 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2949 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 2950 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 2951 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 2952 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2953 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 2954 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 2955 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2956 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 2957 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 2958 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 2959 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2960 .reset = mv88e6352_g1_reset,
931d1822
VD		 2961 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2962 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 2963 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 2964};
2965
b3469dd8 2966static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 2967 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 2968 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 2969 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2970 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 2971 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 2972 .phy_read = mv88e6xxx_g2_smi_phy_read,
2973 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 2974 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
2975 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
08ef7f10 2976 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 2977 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 2978 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 2979 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 2980 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 2981 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 2982 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 2983 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 2984 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 2985 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 2986 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 2987 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 2988 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 2989 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2990 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 2991 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 2992 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2993 .set_egress_port = mv88e6095_g1_set_egress_port,
51c901a7 2994 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 2995 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 2996 .reset = mv88e6352_g1_reset,
f1394b78 2997 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 2998 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 2999};
3000
3001static const struct mv88e6xxx_ops mv88e6321_ops = {
bd807204 3002 /* MV88E6XXX_FAMILY_6320 */
cd8da8bb 3003 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3004 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3005 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3006 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3007 .phy_read = mv88e6xxx_g2_smi_phy_read,
3008 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 3009 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3010 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
08ef7f10 3011 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3012 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3013 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3014 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3015 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3016 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3017 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3018 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3019 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3020 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3021 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3022 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3023 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3024 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3025 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 3026 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 3027 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3028 .set_egress_port = mv88e6095_g1_set_egress_port,
17e708ba 3029 .reset = mv88e6352_g1_reset,
f1394b78 3030 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3031 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
b3469dd8
VD		 3032};
3033
16e329ae
VD		 3034static const struct mv88e6xxx_ops mv88e6341_ops = {
3035 /* MV88E6XXX_FAMILY_6341 */
cd8da8bb 3036 .irl_init_all = mv88e6352_g2_irl_init_all,
16e329ae
VD		 3037 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3038 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3039 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3040 .phy_read = mv88e6xxx_g2_smi_phy_read,
3041 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 3042 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3043 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
16e329ae
VD		 3044 .port_set_link = mv88e6xxx_port_set_link,
3045 .port_set_duplex = mv88e6xxx_port_set_duplex,
3046 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3047 .port_set_speed = mv88e6390_port_set_speed,
3048 .port_tag_remap = mv88e6095_port_tag_remap,
3049 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3050 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3051 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3052 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 3053 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3054 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 3055 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3056 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3057 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3058 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3059 .stats_get_strings = mv88e6320_stats_get_strings,
3060 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3061 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3062 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 3063 .watchdog_ops = &mv88e6390_watchdog_ops,
3064 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3065 .pot_clear = mv88e6xxx_g2_pot_clear,
16e329ae 3066 .reset = mv88e6352_g1_reset,
f1394b78 3067 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3068 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
16e329ae
VD		 3069};
3070
b3469dd8 3071static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 3072 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3073 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3074 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3075 .phy_read = mv88e6xxx_g2_smi_phy_read,
3076 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3077 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3078 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3079 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3080 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3081 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3082 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3083 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3084 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3085 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3086 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3087 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3088 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3089 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3090 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3091 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3092 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3093 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3094 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3095 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3096 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3097 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3098 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3099 .reset = mv88e6352_g1_reset,
f1394b78 3100 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3101 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3102};
3103
3104static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 3105 /* MV88E6XXX_FAMILY_6351 */
cd8da8bb 3106 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3107 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3108 .phy_read = mv88e6xxx_g2_smi_phy_read,
3109 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3110 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3111 .port_set_duplex = mv88e6xxx_port_set_duplex,
94d66ae6 3112 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3113 .port_set_speed = mv88e6185_port_set_speed,
ef0a7318 3114 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3115 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3116 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3117 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3118 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3119 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3120 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3121 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3122 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3123 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3124 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3125 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3126 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3127 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3128 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3129 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3130 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3131 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3132 .reset = mv88e6352_g1_reset,
f1394b78 3133 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3134 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
b3469dd8
VD		 3135};
3136
3137static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 3138 /* MV88E6XXX_FAMILY_6352 */
cd8da8bb 3139 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3140 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3141 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3142 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3143 .phy_read = mv88e6xxx_g2_smi_phy_read,
3144 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 3145 .phy_energy_detect_read = mv88e6352_phy_energy_detect_read,
3146 .phy_energy_detect_write = mv88e6352_phy_energy_detect_write,
08ef7f10 3147 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3148 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3149 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3150 .port_set_speed = mv88e6352_port_set_speed,
ef0a7318 3151 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3152 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3153 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3154 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3155 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3156 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3157 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3158 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3159 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
a605a0fe 3160 .stats_snapshot = mv88e6320_g1_stats_snapshot,
dfafe449
AL		 3161 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3162 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3163 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3164 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3165 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3166 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3167 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3168 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3169 .reset = mv88e6352_g1_reset,
f1394b78 3170 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3171 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6d91782f 3172 .serdes_power = mv88e6352_serdes_power,
b3469dd8
VD		 3173};
3174
1a3b39ec 3175static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 3176 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 3177 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3178 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3179 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3180 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3181 .phy_read = mv88e6xxx_g2_smi_phy_read,
3182 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 3183 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
3184 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
1a3b39ec
AL		 3185 .port_set_link = mv88e6xxx_port_set_link,
3186 .port_set_duplex = mv88e6xxx_port_set_duplex,
3187 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3188 .port_set_speed = mv88e6390_port_set_speed,
ef0a7318 3189 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3190 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3191 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3192 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3193 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3194 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3195 .port_pause_limit = mv88e6390_port_pause_limit,
f39908d3 3196 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3197 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3198 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3199 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3200 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3201 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3202 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3203 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3204 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3205 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3206 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3207 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3208 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3209 .reset = mv88e6352_g1_reset,
931d1822
VD		 3210 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3211 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3212 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3213};
3214
3215static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 3216 /* MV88E6XXX_FAMILY_6390 */
cd8da8bb 3217 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 3218 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3219 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 3220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3221 .phy_read = mv88e6xxx_g2_smi_phy_read,
3222 .phy_write = mv88e6xxx_g2_smi_phy_write,
68b8f60c
VD		 3223 .phy_energy_detect_read = mv88e6390_phy_energy_detect_read,
3224 .phy_energy_detect_write = mv88e6390_phy_energy_detect_write,
1a3b39ec
AL		 3225 .port_set_link = mv88e6xxx_port_set_link,
3226 .port_set_duplex = mv88e6xxx_port_set_duplex,
3227 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3228 .port_set_speed = mv88e6390x_port_set_speed,
ef0a7318 3229 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 3230 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
601aeed3 3231 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
56995cbc 3232 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3233 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3234 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3235 .port_pause_limit = mv88e6390_port_pause_limit,
bb0a2675 3236 .port_set_cmode = mv88e6390x_port_set_cmode,
c8c94891 3237 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3238 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
79523473 3239 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 3240 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 3241 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3242 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 3243 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3244 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3245 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 3246 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 3247 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3248 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3249 .reset = mv88e6352_g1_reset,
931d1822
VD		 3250 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3251 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 3252 .serdes_power = mv88e6390_serdes_power,
1a3b39ec
AL		 3253};
3254
f81ec90f
VD		 3255static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3256 [MV88E6085] = {
107fcc10 3257 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 3258 .family = MV88E6XXX_FAMILY_6097,
3259 .name = "Marvell 88E6085",
3260 .num_databases = 4096,
3261 .num_ports = 10,
3cf3c846 3262 .max_vid = 4095,
9dddd478 3263 .port_base_addr = 0x10,
a935c052 3264 .global1_addr = 0x1b,
9069c13a 3265 .global2_addr = 0x1c,
acddbd21 3266 .age_time_coeff = 15000,
dc30c35b 3267 .g1_irqs = 8,
d6c5e6af 3268 .g2_irqs = 10,
e606ca36 3269 .atu_move_port_mask = 0xf,
f3645652 3270 .pvt = true,
b3e05aa1 3271 .multi_chip = true,
443d5a1b 3272 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3273 .ops = &mv88e6085_ops,
f81ec90f
VD		 3274 },
3275
3276 [MV88E6095] = {
107fcc10 3277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 3278 .family = MV88E6XXX_FAMILY_6095,
3279 .name = "Marvell 88E6095/88E6095F",
3280 .num_databases = 256,
3281 .num_ports = 11,
3cf3c846 3282 .max_vid = 4095,
9dddd478 3283 .port_base_addr = 0x10,
a935c052 3284 .global1_addr = 0x1b,
9069c13a 3285 .global2_addr = 0x1c,
acddbd21 3286 .age_time_coeff = 15000,
dc30c35b 3287 .g1_irqs = 8,
e606ca36 3288 .atu_move_port_mask = 0xf,
b3e05aa1 3289 .multi_chip = true,
443d5a1b 3290 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3291 .ops = &mv88e6095_ops,
f81ec90f
VD		 3292 },
3293
7d381a02 3294 [MV88E6097] = {
107fcc10 3295 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 3296 .family = MV88E6XXX_FAMILY_6097,
3297 .name = "Marvell 88E6097/88E6097F",
3298 .num_databases = 4096,
3299 .num_ports = 11,
3cf3c846 3300 .max_vid = 4095,
7d381a02
SE		 3301 .port_base_addr = 0x10,
3302 .global1_addr = 0x1b,
9069c13a 3303 .global2_addr = 0x1c,
7d381a02 3304 .age_time_coeff = 15000,
c534178b 3305 .g1_irqs = 8,
d6c5e6af 3306 .g2_irqs = 10,
e606ca36 3307 .atu_move_port_mask = 0xf,
f3645652 3308 .pvt = true,
b3e05aa1 3309 .multi_chip = true,
2bfcfcd3 3310 .tag_protocol = DSA_TAG_PROTO_EDSA,
7d381a02
SE		 3311 .ops = &mv88e6097_ops,
3312 },
3313
f81ec90f 3314 [MV88E6123] = {
107fcc10 3315 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 3316 .family = MV88E6XXX_FAMILY_6165,
3317 .name = "Marvell 88E6123",
3318 .num_databases = 4096,
3319 .num_ports = 3,
3cf3c846 3320 .max_vid = 4095,
9dddd478 3321 .port_base_addr = 0x10,
a935c052 3322 .global1_addr = 0x1b,
9069c13a 3323 .global2_addr = 0x1c,
acddbd21 3324 .age_time_coeff = 15000,
dc30c35b 3325 .g1_irqs = 9,
d6c5e6af 3326 .g2_irqs = 10,
e606ca36 3327 .atu_move_port_mask = 0xf,
f3645652 3328 .pvt = true,
b3e05aa1 3329 .multi_chip = true,
5ebe31d7 3330 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3331 .ops = &mv88e6123_ops,
f81ec90f
VD		 3332 },
3333
3334 [MV88E6131] = {
107fcc10 3335 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 3336 .family = MV88E6XXX_FAMILY_6185,
3337 .name = "Marvell 88E6131",
3338 .num_databases = 256,
3339 .num_ports = 8,
3cf3c846 3340 .max_vid = 4095,
9dddd478 3341 .port_base_addr = 0x10,
a935c052 3342 .global1_addr = 0x1b,
9069c13a 3343 .global2_addr = 0x1c,
acddbd21 3344 .age_time_coeff = 15000,
dc30c35b 3345 .g1_irqs = 9,
e606ca36 3346 .atu_move_port_mask = 0xf,
b3e05aa1 3347 .multi_chip = true,
443d5a1b 3348 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3349 .ops = &mv88e6131_ops,
f81ec90f
VD		 3350 },
3351
990e27b0 3352 [MV88E6141] = {
107fcc10 3353 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0
VD		 3354 .family = MV88E6XXX_FAMILY_6341,
3355 .name = "Marvell 88E6341",
3356 .num_databases = 4096,
3357 .num_ports = 6,
3cf3c846 3358 .max_vid = 4095,
990e27b0
VD		 3359 .port_base_addr = 0x10,
3360 .global1_addr = 0x1b,
9069c13a 3361 .global2_addr = 0x1c,
990e27b0
VD		 3362 .age_time_coeff = 3750,
3363 .atu_move_port_mask = 0x1f,
d6c5e6af 3364 .g2_irqs = 10,
f3645652 3365 .pvt = true,
b3e05aa1 3366 .multi_chip = true,
990e27b0 3367 .tag_protocol = DSA_TAG_PROTO_EDSA,
990e27b0
VD		 3368 .ops = &mv88e6141_ops,
3369 },
3370
f81ec90f 3371 [MV88E6161] = {
107fcc10 3372 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 3373 .family = MV88E6XXX_FAMILY_6165,
3374 .name = "Marvell 88E6161",
3375 .num_databases = 4096,
3376 .num_ports = 6,
3cf3c846 3377 .max_vid = 4095,
9dddd478 3378 .port_base_addr = 0x10,
a935c052 3379 .global1_addr = 0x1b,
9069c13a 3380 .global2_addr = 0x1c,
acddbd21 3381 .age_time_coeff = 15000,
dc30c35b 3382 .g1_irqs = 9,
d6c5e6af 3383 .g2_irqs = 10,
e606ca36 3384 .atu_move_port_mask = 0xf,
f3645652 3385 .pvt = true,
b3e05aa1 3386 .multi_chip = true,
5ebe31d7 3387 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3388 .ops = &mv88e6161_ops,
f81ec90f
VD		 3389 },
3390
3391 [MV88E6165] = {
107fcc10 3392 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 3393 .family = MV88E6XXX_FAMILY_6165,
3394 .name = "Marvell 88E6165",
3395 .num_databases = 4096,
3396 .num_ports = 6,
3cf3c846 3397 .max_vid = 4095,
9dddd478 3398 .port_base_addr = 0x10,
a935c052 3399 .global1_addr = 0x1b,
9069c13a 3400 .global2_addr = 0x1c,
acddbd21 3401 .age_time_coeff = 15000,
dc30c35b 3402 .g1_irqs = 9,
d6c5e6af 3403 .g2_irqs = 10,
e606ca36 3404 .atu_move_port_mask = 0xf,
f3645652 3405 .pvt = true,
b3e05aa1 3406 .multi_chip = true,
443d5a1b 3407 .tag_protocol = DSA_TAG_PROTO_DSA,
b3469dd8 3408 .ops = &mv88e6165_ops,
f81ec90f
VD		 3409 },
3410
3411 [MV88E6171] = {
107fcc10 3412 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 3413 .family = MV88E6XXX_FAMILY_6351,
3414 .name = "Marvell 88E6171",
3415 .num_databases = 4096,
3416 .num_ports = 7,
3cf3c846 3417 .max_vid = 4095,
9dddd478 3418 .port_base_addr = 0x10,
a935c052 3419 .global1_addr = 0x1b,
9069c13a 3420 .global2_addr = 0x1c,
acddbd21 3421 .age_time_coeff = 15000,
dc30c35b 3422 .g1_irqs = 9,
d6c5e6af 3423 .g2_irqs = 10,
e606ca36 3424 .atu_move_port_mask = 0xf,
f3645652 3425 .pvt = true,
b3e05aa1 3426 .multi_chip = true,
443d5a1b 3427 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3428 .ops = &mv88e6171_ops,
f81ec90f
VD		 3429 },
3430
3431 [MV88E6172] = {
107fcc10 3432 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 3433 .family = MV88E6XXX_FAMILY_6352,
3434 .name = "Marvell 88E6172",
3435 .num_databases = 4096,
3436 .num_ports = 7,
3cf3c846 3437 .max_vid = 4095,
9dddd478 3438 .port_base_addr = 0x10,
a935c052 3439 .global1_addr = 0x1b,
9069c13a 3440 .global2_addr = 0x1c,
acddbd21 3441 .age_time_coeff = 15000,
dc30c35b 3442 .g1_irqs = 9,
d6c5e6af 3443 .g2_irqs = 10,
e606ca36 3444 .atu_move_port_mask = 0xf,
f3645652 3445 .pvt = true,
b3e05aa1 3446 .multi_chip = true,
443d5a1b 3447 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3448 .ops = &mv88e6172_ops,
f81ec90f
VD		 3449 },
3450
3451 [MV88E6175] = {
107fcc10 3452 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 3453 .family = MV88E6XXX_FAMILY_6351,
3454 .name = "Marvell 88E6175",
3455 .num_databases = 4096,
3456 .num_ports = 7,
3cf3c846 3457 .max_vid = 4095,
9dddd478 3458 .port_base_addr = 0x10,
a935c052 3459 .global1_addr = 0x1b,
9069c13a 3460 .global2_addr = 0x1c,
acddbd21 3461 .age_time_coeff = 15000,
dc30c35b 3462 .g1_irqs = 9,
d6c5e6af 3463 .g2_irqs = 10,
e606ca36 3464 .atu_move_port_mask = 0xf,
f3645652 3465 .pvt = true,
b3e05aa1 3466 .multi_chip = true,
443d5a1b 3467 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3468 .ops = &mv88e6175_ops,
f81ec90f
VD		 3469 },
3470
3471 [MV88E6176] = {
107fcc10 3472 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 3473 .family = MV88E6XXX_FAMILY_6352,
3474 .name = "Marvell 88E6176",
3475 .num_databases = 4096,
3476 .num_ports = 7,
3cf3c846 3477 .max_vid = 4095,
9dddd478 3478 .port_base_addr = 0x10,
a935c052 3479 .global1_addr = 0x1b,
9069c13a 3480 .global2_addr = 0x1c,
acddbd21 3481 .age_time_coeff = 15000,
dc30c35b 3482 .g1_irqs = 9,
d6c5e6af 3483 .g2_irqs = 10,
e606ca36 3484 .atu_move_port_mask = 0xf,
f3645652 3485 .pvt = true,
b3e05aa1 3486 .multi_chip = true,
443d5a1b 3487 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3488 .ops = &mv88e6176_ops,
f81ec90f
VD		 3489 },
3490
3491 [MV88E6185] = {
107fcc10 3492 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 3493 .family = MV88E6XXX_FAMILY_6185,
3494 .name = "Marvell 88E6185",
3495 .num_databases = 256,
3496 .num_ports = 10,
3cf3c846 3497 .max_vid = 4095,
9dddd478 3498 .port_base_addr = 0x10,
a935c052 3499 .global1_addr = 0x1b,
9069c13a 3500 .global2_addr = 0x1c,
acddbd21 3501 .age_time_coeff = 15000,
dc30c35b 3502 .g1_irqs = 8,
e606ca36 3503 .atu_move_port_mask = 0xf,
b3e05aa1 3504 .multi_chip = true,
443d5a1b 3505 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3506 .ops = &mv88e6185_ops,
f81ec90f
VD		 3507 },
3508
1a3b39ec 3509 [MV88E6190] = {
107fcc10 3510 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 3511 .family = MV88E6XXX_FAMILY_6390,
3512 .name = "Marvell 88E6190",
3513 .num_databases = 4096,
3514 .num_ports = 11, /* 10 + Z80 */
931d1822 3515 .max_vid = 8191,
1a3b39ec
AL		 3516 .port_base_addr = 0x0,
3517 .global1_addr = 0x1b,
9069c13a 3518 .global2_addr = 0x1c,
443d5a1b 3519 .tag_protocol = DSA_TAG_PROTO_DSA,
b91e055c 3520 .age_time_coeff = 3750,
1a3b39ec 3521 .g1_irqs = 9,
d6c5e6af 3522 .g2_irqs = 14,
f3645652 3523 .pvt = true,
b3e05aa1 3524 .multi_chip = true,
e606ca36 3525 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 3526 .ops = &mv88e6190_ops,
3527 },
3528
3529 [MV88E6190X] = {
107fcc10 3530 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 3531 .family = MV88E6XXX_FAMILY_6390,
3532 .name = "Marvell 88E6190X",
3533 .num_databases = 4096,
3534 .num_ports = 11, /* 10 + Z80 */
931d1822 3535 .max_vid = 8191,
1a3b39ec
AL		 3536 .port_base_addr = 0x0,
3537 .global1_addr = 0x1b,
9069c13a 3538 .global2_addr = 0x1c,
b91e055c 3539 .age_time_coeff = 3750,
1a3b39ec 3540 .g1_irqs = 9,
d6c5e6af 3541 .g2_irqs = 14,
e606ca36 3542 .atu_move_port_mask = 0x1f,
f3645652 3543 .pvt = true,
b3e05aa1 3544 .multi_chip = true,
443d5a1b 3545 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3546 .ops = &mv88e6190x_ops,
3547 },
3548
3549 [MV88E6191] = {
107fcc10 3550 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 3551 .family = MV88E6XXX_FAMILY_6390,
3552 .name = "Marvell 88E6191",
3553 .num_databases = 4096,
3554 .num_ports = 11, /* 10 + Z80 */
931d1822 3555 .max_vid = 8191,
1a3b39ec
AL		 3556 .port_base_addr = 0x0,
3557 .global1_addr = 0x1b,
9069c13a 3558 .global2_addr = 0x1c,
b91e055c 3559 .age_time_coeff = 3750,
443d5a1b 3560 .g1_irqs = 9,
d6c5e6af 3561 .g2_irqs = 14,
e606ca36 3562 .atu_move_port_mask = 0x1f,
f3645652 3563 .pvt = true,
b3e05aa1 3564 .multi_chip = true,
443d5a1b 3565 .tag_protocol = DSA_TAG_PROTO_DSA,
2cf4cefb 3566 .ops = &mv88e6191_ops,
1a3b39ec
AL		 3567 },
3568
f81ec90f 3569 [MV88E6240] = {
107fcc10 3570 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 3571 .family = MV88E6XXX_FAMILY_6352,
3572 .name = "Marvell 88E6240",
3573 .num_databases = 4096,
3574 .num_ports = 7,
3cf3c846 3575 .max_vid = 4095,
9dddd478 3576 .port_base_addr = 0x10,
a935c052 3577 .global1_addr = 0x1b,
9069c13a 3578 .global2_addr = 0x1c,
acddbd21 3579 .age_time_coeff = 15000,
dc30c35b 3580 .g1_irqs = 9,
d6c5e6af 3581 .g2_irqs = 10,
e606ca36 3582 .atu_move_port_mask = 0xf,
f3645652 3583 .pvt = true,
b3e05aa1 3584 .multi_chip = true,
443d5a1b 3585 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3586 .ops = &mv88e6240_ops,
f81ec90f
VD		 3587 },
3588
1a3b39ec 3589 [MV88E6290] = {
107fcc10 3590 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 3591 .family = MV88E6XXX_FAMILY_6390,
3592 .name = "Marvell 88E6290",
3593 .num_databases = 4096,
3594 .num_ports = 11, /* 10 + Z80 */
931d1822 3595 .max_vid = 8191,
1a3b39ec
AL		 3596 .port_base_addr = 0x0,
3597 .global1_addr = 0x1b,
9069c13a 3598 .global2_addr = 0x1c,
b91e055c 3599 .age_time_coeff = 3750,
1a3b39ec 3600 .g1_irqs = 9,
d6c5e6af 3601 .g2_irqs = 14,
e606ca36 3602 .atu_move_port_mask = 0x1f,
f3645652 3603 .pvt = true,
b3e05aa1 3604 .multi_chip = true,
443d5a1b 3605 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3606 .ops = &mv88e6290_ops,
3607 },
3608
f81ec90f 3609 [MV88E6320] = {
107fcc10 3610 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 3611 .family = MV88E6XXX_FAMILY_6320,
3612 .name = "Marvell 88E6320",
3613 .num_databases = 4096,
3614 .num_ports = 7,
3cf3c846 3615 .max_vid = 4095,
9dddd478 3616 .port_base_addr = 0x10,
a935c052 3617 .global1_addr = 0x1b,
9069c13a 3618 .global2_addr = 0x1c,
acddbd21 3619 .age_time_coeff = 15000,
dc30c35b 3620 .g1_irqs = 8,
e606ca36 3621 .atu_move_port_mask = 0xf,
f3645652 3622 .pvt = true,
b3e05aa1 3623 .multi_chip = true,
443d5a1b 3624 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3625 .ops = &mv88e6320_ops,
f81ec90f
VD		 3626 },
3627
3628 [MV88E6321] = {
107fcc10 3629 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 3630 .family = MV88E6XXX_FAMILY_6320,
3631 .name = "Marvell 88E6321",
3632 .num_databases = 4096,
3633 .num_ports = 7,
3cf3c846 3634 .max_vid = 4095,
9dddd478 3635 .port_base_addr = 0x10,
a935c052 3636 .global1_addr = 0x1b,
9069c13a 3637 .global2_addr = 0x1c,
acddbd21 3638 .age_time_coeff = 15000,
dc30c35b 3639 .g1_irqs = 8,
e606ca36 3640 .atu_move_port_mask = 0xf,
b3e05aa1 3641 .multi_chip = true,
443d5a1b 3642 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3643 .ops = &mv88e6321_ops,
f81ec90f
VD		 3644 },
3645
a75961d0 3646 [MV88E6341] = {
107fcc10 3647 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 3648 .family = MV88E6XXX_FAMILY_6341,
3649 .name = "Marvell 88E6341",
3650 .num_databases = 4096,
3651 .num_ports = 6,
3cf3c846 3652 .max_vid = 4095,
a75961d0
GC		 3653 .port_base_addr = 0x10,
3654 .global1_addr = 0x1b,
9069c13a 3655 .global2_addr = 0x1c,
a75961d0 3656 .age_time_coeff = 3750,
e606ca36 3657 .atu_move_port_mask = 0x1f,
d6c5e6af 3658 .g2_irqs = 10,
f3645652 3659 .pvt = true,
b3e05aa1 3660 .multi_chip = true,
a75961d0 3661 .tag_protocol = DSA_TAG_PROTO_EDSA,
a75961d0
GC		 3662 .ops = &mv88e6341_ops,
3663 },
3664
f81ec90f 3665 [MV88E6350] = {
107fcc10 3666 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 3667 .family = MV88E6XXX_FAMILY_6351,
3668 .name = "Marvell 88E6350",
3669 .num_databases = 4096,
3670 .num_ports = 7,
3cf3c846 3671 .max_vid = 4095,
9dddd478 3672 .port_base_addr = 0x10,
a935c052 3673 .global1_addr = 0x1b,
9069c13a 3674 .global2_addr = 0x1c,
acddbd21 3675 .age_time_coeff = 15000,
dc30c35b 3676 .g1_irqs = 9,
d6c5e6af 3677 .g2_irqs = 10,
e606ca36 3678 .atu_move_port_mask = 0xf,
f3645652 3679 .pvt = true,
b3e05aa1 3680 .multi_chip = true,
443d5a1b 3681 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3682 .ops = &mv88e6350_ops,
f81ec90f
VD		 3683 },
3684
3685 [MV88E6351] = {
107fcc10 3686 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 3687 .family = MV88E6XXX_FAMILY_6351,
3688 .name = "Marvell 88E6351",
3689 .num_databases = 4096,
3690 .num_ports = 7,
3cf3c846 3691 .max_vid = 4095,
9dddd478 3692 .port_base_addr = 0x10,
a935c052 3693 .global1_addr = 0x1b,
9069c13a 3694 .global2_addr = 0x1c,
acddbd21 3695 .age_time_coeff = 15000,
dc30c35b 3696 .g1_irqs = 9,
d6c5e6af 3697 .g2_irqs = 10,
e606ca36 3698 .atu_move_port_mask = 0xf,
f3645652 3699 .pvt = true,
b3e05aa1 3700 .multi_chip = true,
443d5a1b 3701 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3702 .ops = &mv88e6351_ops,
f81ec90f
VD		 3703 },
3704
3705 [MV88E6352] = {
107fcc10 3706 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 3707 .family = MV88E6XXX_FAMILY_6352,
3708 .name = "Marvell 88E6352",
3709 .num_databases = 4096,
3710 .num_ports = 7,
3cf3c846 3711 .max_vid = 4095,
9dddd478 3712 .port_base_addr = 0x10,
a935c052 3713 .global1_addr = 0x1b,
9069c13a 3714 .global2_addr = 0x1c,
acddbd21 3715 .age_time_coeff = 15000,
dc30c35b 3716 .g1_irqs = 9,
d6c5e6af 3717 .g2_irqs = 10,
e606ca36 3718 .atu_move_port_mask = 0xf,
f3645652 3719 .pvt = true,
b3e05aa1 3720 .multi_chip = true,
443d5a1b 3721 .tag_protocol = DSA_TAG_PROTO_EDSA,
b3469dd8 3722 .ops = &mv88e6352_ops,
f81ec90f 3723 },
1a3b39ec 3724 [MV88E6390] = {
107fcc10 3725 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 3726 .family = MV88E6XXX_FAMILY_6390,
3727 .name = "Marvell 88E6390",
3728 .num_databases = 4096,
3729 .num_ports = 11, /* 10 + Z80 */
931d1822 3730 .max_vid = 8191,
1a3b39ec
AL		 3731 .port_base_addr = 0x0,
3732 .global1_addr = 0x1b,
9069c13a 3733 .global2_addr = 0x1c,
b91e055c 3734 .age_time_coeff = 3750,
1a3b39ec 3735 .g1_irqs = 9,
d6c5e6af 3736 .g2_irqs = 14,
e606ca36 3737 .atu_move_port_mask = 0x1f,
f3645652 3738 .pvt = true,
b3e05aa1 3739 .multi_chip = true,
443d5a1b 3740 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3741 .ops = &mv88e6390_ops,
3742 },
3743 [MV88E6390X] = {
107fcc10 3744 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 3745 .family = MV88E6XXX_FAMILY_6390,
3746 .name = "Marvell 88E6390X",
3747 .num_databases = 4096,
3748 .num_ports = 11, /* 10 + Z80 */
931d1822 3749 .max_vid = 8191,
1a3b39ec
AL		 3750 .port_base_addr = 0x0,
3751 .global1_addr = 0x1b,
9069c13a 3752 .global2_addr = 0x1c,
b91e055c 3753 .age_time_coeff = 3750,
1a3b39ec 3754 .g1_irqs = 9,
d6c5e6af 3755 .g2_irqs = 14,
e606ca36 3756 .atu_move_port_mask = 0x1f,
f3645652 3757 .pvt = true,
b3e05aa1 3758 .multi_chip = true,
443d5a1b 3759 .tag_protocol = DSA_TAG_PROTO_DSA,
1a3b39ec
AL		 3760 .ops = &mv88e6390x_ops,
3761 },
f81ec90f
VD		 3762};
3763
5f7c0367 3764static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3765{
a439c061 3766 int i;
b9b37713 3767
5f7c0367
VD		 3768 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3769 if (mv88e6xxx_table[i].prod_num == prod_num)
3770 return &mv88e6xxx_table[i];
b9b37713 3771
b9b37713
VD		 3772 return NULL;
3773}
3774
fad09c73 3775static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3776{
3777 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3778 unsigned int prod_num, rev;
3779 u16 id;
3780 int err;
bc46a3d5 3781
8f6345b2 3782 mutex_lock(&chip->reg_lock);
107fcc10 3783 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
8f6345b2
VD		 3784 mutex_unlock(&chip->reg_lock);
3785 if (err)
3786 return err;
bc46a3d5 3787
107fcc10
VD		 3788 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3789 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 3790
3791 info = mv88e6xxx_lookup_info(prod_num);
3792 if (!info)
3793 return -ENODEV;
3794
caac8545 3795 /* Update the compatible info with the probed one */
fad09c73 3796 chip->info = info;
bc46a3d5 3797
ca070c10
VD		 3798 err = mv88e6xxx_g2_require(chip);
3799 if (err)
3800 return err;
3801
fad09c73
VD		 3802 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3803 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3804
3805 return 0;
3806}
3807
fad09c73 3808static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3809{
fad09c73 3810 struct mv88e6xxx_chip *chip;
469d729f 3811
fad09c73
VD		 3812 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3813 if (!chip)
469d729f
VD		 3814 return NULL;
3815
fad09c73 3816 chip->dev = dev;
469d729f 3817
fad09c73 3818 mutex_init(&chip->reg_lock);
a3c53be5 3819 INIT_LIST_HEAD(&chip->mdios);
469d729f 3820
fad09c73 3821 return chip;
469d729f
VD		 3822}
3823
fad09c73 3824static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3825 struct mii_bus *bus, int sw_addr)
3826{
914b32f6 3827 if (sw_addr == 0)
fad09c73 3828 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
b3e05aa1 3829 else if (chip->info->multi_chip)
fad09c73 3830 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3831 else
3832 return -EINVAL;
3833
fad09c73
VD		 3834 chip->bus = bus;
3835 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3836
3837 return 0;
3838}
3839
7b314362
AL		 3840static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3841{
04bed143 3842 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 3843
443d5a1b 3844 return chip->info->tag_protocol;
7b314362
AL		 3845}
3846
fcdce7d0
AL		 3847static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3848 struct device *host_dev, int sw_addr,
3849 void **priv)
a77d43f1 3850{
fad09c73 3851 struct mv88e6xxx_chip *chip;
a439c061 3852 struct mii_bus *bus;
b516d453 3853 int err;
a77d43f1 3854
a439c061 3855 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3856 if (!bus)
3857 return NULL;
3858
fad09c73
VD		 3859 chip = mv88e6xxx_alloc_chip(dsa_dev);
3860 if (!chip)
469d729f
VD		 3861 return NULL;
3862
caac8545 3863 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3864 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3865
fad09c73 3866 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3867 if (err)
3868 goto free;
3869
fad09c73 3870 err = mv88e6xxx_detect(chip);
bc46a3d5 3871 if (err)
469d729f 3872 goto free;
a439c061 3873
dc30c35b
AL		 3874 mutex_lock(&chip->reg_lock);
3875 err = mv88e6xxx_switch_reset(chip);
3876 mutex_unlock(&chip->reg_lock);
3877 if (err)
3878 goto free;
3879
e57e5e77
VD		 3880 mv88e6xxx_phy_init(chip);
3881
a3c53be5 3882 err = mv88e6xxx_mdios_register(chip, NULL);
b516d453 3883 if (err)
469d729f 3884 goto free;
b516d453 3885
fad09c73 3886 *priv = chip;
a439c061 3887
fad09c73 3888 return chip->info->name;
469d729f 3889free:
fad09c73 3890 devm_kfree(dsa_dev, chip);
469d729f
VD		 3891
3892 return NULL;
a77d43f1
AL		 3893}
3894
7df8fbdd
VD		 3895static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3896 const struct switchdev_obj_port_mdb *mdb,
3897 struct switchdev_trans *trans)
3898{
3899 /* We don't need any dynamic resource from the kernel (yet),
3900 * so skip the prepare phase.
3901 */
3902
3903 return 0;
3904}
3905
3906static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3907 const struct switchdev_obj_port_mdb *mdb,
3908 struct switchdev_trans *trans)
3909{
04bed143 3910 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3911
3912 mutex_lock(&chip->reg_lock);
3913 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3914 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
774439e5
VD		 3915 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
3916 port);
7df8fbdd
VD		 3917 mutex_unlock(&chip->reg_lock);
3918}
3919
3920static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3921 const struct switchdev_obj_port_mdb *mdb)
3922{
04bed143 3923 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3924 int err;
3925
3926 mutex_lock(&chip->reg_lock);
3927 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
27c0e600 3928 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
7df8fbdd
VD		 3929 mutex_unlock(&chip->reg_lock);
3930
3931 return err;
3932}
3933
3934static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3935 struct switchdev_obj_port_mdb *mdb,
438ff537 3936 switchdev_obj_dump_cb_t *cb)
7df8fbdd 3937{
04bed143 3938 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3939 int err;
3940
3941 mutex_lock(&chip->reg_lock);
3942 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3943 mutex_unlock(&chip->reg_lock);
3944
3945 return err;
3946}
3947
a82f67af 3948static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3949 .probe = mv88e6xxx_drv_probe,
7b314362 3950 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3951 .setup = mv88e6xxx_setup,
3952 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3953 .adjust_link = mv88e6xxx_adjust_link,
3954 .get_strings = mv88e6xxx_get_strings,
3955 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3956 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 3957 .port_enable = mv88e6xxx_port_enable,
3958 .port_disable = mv88e6xxx_port_disable,
f81ec90f
VD		 3959 .set_eee = mv88e6xxx_set_eee,
3960 .get_eee = mv88e6xxx_get_eee,
f8cd8753 3961 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3962 .get_eeprom = mv88e6xxx_get_eeprom,
3963 .set_eeprom = mv88e6xxx_set_eeprom,
3964 .get_regs_len = mv88e6xxx_get_regs_len,
3965 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3966 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3967 .port_bridge_join = mv88e6xxx_port_bridge_join,
3968 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3969 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3970 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3971 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3972 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3973 .port_vlan_add = mv88e6xxx_port_vlan_add,
3974 .port_vlan_del = mv88e6xxx_port_vlan_del,
3975 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3976 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3977 .port_fdb_add = mv88e6xxx_port_fdb_add,
3978 .port_fdb_del = mv88e6xxx_port_fdb_del,
3979 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3980 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3981 .port_mdb_add = mv88e6xxx_port_mdb_add,
3982 .port_mdb_del = mv88e6xxx_port_mdb_del,
3983 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
aec5ac88
VD		 3984 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
3985 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
f81ec90f
VD		 3986};
3987
ab3d408d
FF		 3988static struct dsa_switch_driver mv88e6xxx_switch_drv = {
3989 .ops = &mv88e6xxx_switch_ops,
3990};
3991
55ed0ce0 3992static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3993{
fad09c73 3994 struct device *dev = chip->dev;
b7e66a5f
VD		 3995 struct dsa_switch *ds;
3996
73b1204d 3997 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
b7e66a5f
VD		 3998 if (!ds)
3999 return -ENOMEM;
4000
fad09c73 4001 ds->priv = chip;
9d490b4e 4002 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 4003 ds->ageing_time_min = chip->info->age_time_coeff;
4004 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f
VD		 4005
4006 dev_set_drvdata(dev, ds);
4007
23c9ee49 4008 return dsa_register_switch(ds);
b7e66a5f
VD		 4009}
4010
fad09c73 4011static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 4012{
fad09c73 4013 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 4014}
4015
57d32310 4016static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 4017{
14c7b3c3 4018 struct device *dev = &mdiodev->dev;
f8cd8753 4019 struct device_node *np = dev->of_node;
caac8545 4020 const struct mv88e6xxx_info *compat_info;
fad09c73 4021 struct mv88e6xxx_chip *chip;
f8cd8753 4022 u32 eeprom_len;
52638f71 4023 int err;
14c7b3c3 4024
caac8545
VD		 4025 compat_info = of_device_get_match_data(dev);
4026 if (!compat_info)
4027 return -EINVAL;
4028
fad09c73
VD		 4029 chip = mv88e6xxx_alloc_chip(dev);
4030 if (!chip)
14c7b3c3
AL		 4031 return -ENOMEM;
4032
fad09c73 4033 chip->info = compat_info;
caac8545 4034
fad09c73 4035 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4036 if (err)
4037 return err;
14c7b3c3 4038
b4308f04
AL		 4039 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4040 if (IS_ERR(chip->reset))
4041 return PTR_ERR(chip->reset);
4042
fad09c73 4043 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4044 if (err)
4045 return err;
14c7b3c3 4046
e57e5e77
VD		 4047 mv88e6xxx_phy_init(chip);
4048
ee4dc2e7 4049 if (chip->info->ops->get_eeprom &&
f8cd8753 4050 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4051 chip->eeprom_len = eeprom_len;
f8cd8753 4052
dc30c35b
AL		 4053 mutex_lock(&chip->reg_lock);
4054 err = mv88e6xxx_switch_reset(chip);
4055 mutex_unlock(&chip->reg_lock);
4056 if (err)
4057 goto out;
4058
4059 chip->irq = of_irq_get(np, 0);
4060 if (chip->irq == -EPROBE_DEFER) {
4061 err = chip->irq;
4062 goto out;
4063 }
4064
4065 if (chip->irq > 0) {
4066 /* Has to be performed before the MDIO bus is created,
4067 * because the PHYs will link there interrupts to these
4068 * interrupt controllers
4069 */
4070 mutex_lock(&chip->reg_lock);
4071 err = mv88e6xxx_g1_irq_setup(chip);
4072 mutex_unlock(&chip->reg_lock);
4073
4074 if (err)
4075 goto out;
4076
d6c5e6af 4077 if (chip->info->g2_irqs > 0) {
dc30c35b
AL		 4078 err = mv88e6xxx_g2_irq_setup(chip);
4079 if (err)
4080 goto out_g1_irq;
4081 }
4082 }
4083
a3c53be5 4084 err = mv88e6xxx_mdios_register(chip, np);
b516d453 4085 if (err)
dc30c35b 4086 goto out_g2_irq;
b516d453 4087
55ed0ce0 4088 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 4089 if (err)
4090 goto out_mdio;
83c0afae 4091
98e67308 4092 return 0;
dc30c35b
AL		 4093
4094out_mdio:
a3c53be5 4095 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4096out_g2_irq:
d6c5e6af 4097 if (chip->info->g2_irqs > 0 && chip->irq > 0)
dc30c35b
AL		 4098 mv88e6xxx_g2_irq_free(chip);
4099out_g1_irq:
61f7c3f8
AL		 4100 if (chip->irq > 0) {
4101 mutex_lock(&chip->reg_lock);
46712644 4102 mv88e6xxx_g1_irq_free(chip);
61f7c3f8
AL		 4103 mutex_unlock(&chip->reg_lock);
4104 }
dc30c35b
AL		 4105out:
4106 return err;
98e67308 4107}
14c7b3c3
AL		 4108
4109static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4110{
4111 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 4112 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 4113
930188ce 4114 mv88e6xxx_phy_destroy(chip);
fad09c73 4115 mv88e6xxx_unregister_switch(chip);
a3c53be5 4116 mv88e6xxx_mdios_unregister(chip);
dc30c35b 4117
46712644 4118 if (chip->irq > 0) {
d6c5e6af 4119 if (chip->info->g2_irqs > 0)
46712644
AL		 4120 mv88e6xxx_g2_irq_free(chip);
4121 mv88e6xxx_g1_irq_free(chip);
4122 }
14c7b3c3
AL		 4123}
4124
4125static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4126 {
4127 .compatible = "marvell,mv88e6085",
4128 .data = &mv88e6xxx_table[MV88E6085],
4129 },
1a3b39ec
AL		 4130 {
4131 .compatible = "marvell,mv88e6190",
4132 .data = &mv88e6xxx_table[MV88E6190],
4133 },
14c7b3c3
AL		 4134 { /* sentinel */ },
4135};
4136
4137MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4138
4139static struct mdio_driver mv88e6xxx_driver = {
4140 .probe = mv88e6xxx_probe,
4141 .remove = mv88e6xxx_remove,
4142 .mdiodrv.driver = {
4143 .name = "mv88e6085",
4144 .of_match_table = mv88e6xxx_of_match,
4145 },
4146};
4147
4148static int __init mv88e6xxx_init(void)
4149{
ab3d408d 4150 register_switch_driver(&mv88e6xxx_switch_drv);
14c7b3c3
AL		 4151 return mdio_driver_register(&mv88e6xxx_driver);
4152}
98e67308
BH		 4153module_init(mv88e6xxx_init);
4154
4155static void __exit mv88e6xxx_cleanup(void)
4156{
14c7b3c3 4157 mdio_driver_unregister(&mv88e6xxx_driver);
ab3d408d 4158 unregister_switch_driver(&mv88e6xxx_switch_drv);
98e67308
BH		 4159}
4160module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4161
4162MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4163MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4164MODULE_LICENSE("GPL");
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