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[mirror_ubuntu-jammy-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
91da11f8 2/*
0d3cd4b6
VD		 3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
91da11f8
LB		 5 * Copyright (c) 2008 Marvell Semiconductor
6 *
14c7b3c3
AL		 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
4333d619
VD		 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
91da11f8
LB		 11 */
12
19fb7f69 13#include <linux/bitfield.h>
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
dc30c35b
AL		 18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
dc30c35b 26#include <linux/of_irq.h>
b516d453 27#include <linux/of_mdio.h>
877b7cb0 28#include <linux/platform_data/mv88e6xxx.h>
91da11f8 29#include <linux/netdevice.h>
c8c1b39a 30#include <linux/gpio/consumer.h>
c9a2356f 31#include <linux/phylink.h>
c8f0b869 32#include <net/dsa.h>
ec561276 33
4d5f2ba7 34#include "chip.h"
9dd43aa2 35#include "devlink.h"
a935c052 36#include "global1.h"
ec561276 37#include "global2.h"
c6fe0ad2 38#include "hwtstamp.h"
10fa5bfc 39#include "phy.h"
18abed21 40#include "port.h"
2fa8d3af 41#include "ptp.h"
6d91782f 42#include "serdes.h"
e7ba0fad 43#include "smi.h"
91da11f8 44
fad09c73 45static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 46{
fad09c73
VD		 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 49 dump_stack();
50 }
51}
52
ec561276 53int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 54{
55 int err;
56
fad09c73 57 assert_reg_lock(chip);
914b32f6 58
fad09c73 59 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 60 if (err)
61 return err;
62
fad09c73 63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 64 addr, reg, *val);
65
66 return 0;
67}
68
ec561276 69int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 70{
914b32f6
VD		 71 int err;
72
fad09c73 73 assert_reg_lock(chip);
91da11f8 74
fad09c73 75 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 76 if (err)
77 return err;
78
fad09c73 79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 80 addr, reg, val);
81
914b32f6
VD		 82 return 0;
83}
84
683f2244
VD		 85int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
86 u16 mask, u16 val)
87{
88 u16 data;
89 int err;
90 int i;
91
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
95 if (err)
96 return err;
97
98 if ((data & mask) == val)
99 return 0;
100
101 usleep_range(1000, 2000);
102 }
103
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
105 return -ETIMEDOUT;
106}
107
19fb7f69
VD		 108int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
109 int bit, int val)
110{
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
113}
114
10fa5bfc 115struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 116{
117 struct mv88e6xxx_mdio_bus *mdio_bus;
118
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
120 list);
121 if (!mdio_bus)
122 return NULL;
123
124 return mdio_bus->bus;
125}
126
dc30c35b
AL		 127static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
128{
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
131
132 chip->g1_irq.masked |= (1 << n);
133}
134
135static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
136{
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked &= ~(1 << n);
141}
142
294d711e 143static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
dc30c35b 144{
dc30c35b
AL		 145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
147 unsigned int n;
148 u16 reg;
7c0db24c 149 u16 ctl1;
dc30c35b
AL		 150 int err;
151
c9acece0 152 mv88e6xxx_reg_lock(chip);
82466921 153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
c9acece0 154 mv88e6xxx_reg_unlock(chip);
dc30c35b
AL		 155
156 if (err)
157 goto out;
158
7c0db24c
JDA		 159 do {
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
163 n);
164 handle_nested_irq(sub_irq);
165 ++nhandled;
166 }
dc30c35b 167 }
7c0db24c 168
c9acece0 169 mv88e6xxx_reg_lock(chip);
7c0db24c
JDA		 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
171 if (err)
172 goto unlock;
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
174unlock:
c9acece0 175 mv88e6xxx_reg_unlock(chip);
7c0db24c
JDA		 176 if (err)
177 goto out;
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
180
dc30c35b
AL		 181out:
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
183}
184
294d711e
AL		 185static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
186{
187 struct mv88e6xxx_chip *chip = dev_id;
188
189 return mv88e6xxx_g1_irq_thread_work(chip);
190}
191
dc30c35b
AL		 192static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
193{
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
195
c9acece0 196 mv88e6xxx_reg_lock(chip);
dc30c35b
AL		 197}
198
199static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
200{
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
203 u16 reg;
204 int err;
205
d77f4321 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 207 if (err)
208 goto out;
209
210 reg &= ~mask;
211 reg |= (~chip->g1_irq.masked & mask);
212
d77f4321 213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 214 if (err)
215 goto out;
216
217out:
c9acece0 218 mv88e6xxx_reg_unlock(chip);
dc30c35b
AL		 219}
220
6eb15e21 221static const struct irq_chip mv88e6xxx_g1_irq_chip = {
dc30c35b
AL		 222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
227};
228
229static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
230 unsigned int irq,
231 irq_hw_number_t hwirq)
232{
233 struct mv88e6xxx_chip *chip = d->host_data;
234
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
238
239 return 0;
240}
241
242static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
245};
246
3d82475a 247/* To be called with reg_lock held */
294d711e 248static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
dc30c35b
AL		 249{
250 int irq, virq;
3460a577
AL		 251 u16 mask;
252
d77f4321 253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3d5fdba1 254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577 256
5edef2f2 257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 259 irq_dispose_mapping(virq);
260 }
261
a3db3d3a 262 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 263}
264
294d711e
AL		 265static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
266{
3d82475a
UKK		 267 /*
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
270 */
294d711e 271 free_irq(chip->irq, chip);
3d82475a 272
c9acece0 273 mv88e6xxx_reg_lock(chip);
3d82475a 274 mv88e6xxx_g1_irq_free_common(chip);
c9acece0 275 mv88e6xxx_reg_unlock(chip);
294d711e
AL		 276}
277
278static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
dc30c35b 279{
3dd0ef05
AL		 280 int err, irq, virq;
281 u16 reg, mask;
dc30c35b
AL		 282
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
288 return -ENOMEM;
289
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
292
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
295
d77f4321 296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 297 if (err)
3dd0ef05 298 goto out_mapping;
dc30c35b 299
3dd0ef05 300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 301
d77f4321 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 303 if (err)
3dd0ef05 304 goto out_disable;
dc30c35b
AL		 305
306 /* Reading the interrupt status clears (most of) them */
82466921 307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 308 if (err)
3dd0ef05 309 goto out_disable;
dc30c35b 310
dc30c35b
AL		 311 return 0;
312
3dd0ef05 313out_disable:
3d5fdba1 314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 316
317out_mapping:
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
321 }
322
323 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 324
325 return err;
326}
327
294d711e
AL		 328static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
329{
f6d9758b
AL		 330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
294d711e
AL		 332 int err;
333
334 err = mv88e6xxx_g1_irq_setup_common(chip);
335 if (err)
336 return err;
337
f6d9758b
AL		 338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
341 */
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
343
3095383a
AL		 344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
346
c9acece0 347 mv88e6xxx_reg_unlock(chip);
294d711e
AL		 348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
0340376e 350 IRQF_ONESHOT | IRQF_SHARED,
3095383a 351 chip->irq_name, chip);
c9acece0 352 mv88e6xxx_reg_lock(chip);
294d711e
AL		 353 if (err)
354 mv88e6xxx_g1_irq_free_common(chip);
355
356 return err;
357}
358
359static void mv88e6xxx_irq_poll(struct kthread_work *work)
360{
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
363 irq_poll_work.work);
364 mv88e6xxx_g1_irq_thread_work(chip);
365
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
368}
369
370static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
371{
372 int err;
373
374 err = mv88e6xxx_g1_irq_setup_common(chip);
375 if (err)
376 return err;
377
378 kthread_init_delayed_work(&chip->irq_poll_work,
379 mv88e6xxx_irq_poll);
380
3f8b8696 381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
294d711e
AL		 382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
384
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
387
388 return 0;
389}
390
391static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
392{
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
3d82475a 395
c9acece0 396 mv88e6xxx_reg_lock(chip);
3d82475a 397 mv88e6xxx_g1_irq_free_common(chip);
c9acece0 398 mv88e6xxx_reg_unlock(chip);
294d711e
AL		 399}
400
64d47d50
RK		 401static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
403{
404 int err;
405
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
408 interface);
409 if (err && err != -EOPNOTSUPP)
410 return err;
411 }
412
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
415 interface);
416 if (err && err != -EOPNOTSUPP)
417 return err;
418 }
419
420 return 0;
421}
422
a5a6858b
RK		 423static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
d78343d2
VD		 426{
427 int err;
428
429 if (!chip->info->ops->port_set_link)
430 return 0;
431
432 /* Port's MAC control must not be changed unless the link is down */
43c8e0ae 433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
d78343d2
VD		 434 if (err)
435 return err;
436
f365c6f7
RK		 437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
439 speed, duplex);
d78343d2
VD		 440 if (err && err != -EOPNOTSUPP)
441 goto restore_link;
442 }
443
7cbbee05
AL		 444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
446
54186b91
AL		 447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
449 if (err)
450 goto restore_link;
451 }
452
64d47d50 453 err = mv88e6xxx_port_config_interface(chip, port, mode);
d78343d2
VD		 454restore_link:
455 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 457
458 return err;
459}
460
d700ec41
MV		 461static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
462{
463 struct mv88e6xxx_chip *chip = ds->priv;
464
465 return port < chip->info->num_internal_phys;
466}
467
5d5b231d
RK		 468static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
469{
470 u16 reg;
471 int err;
472
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
474 if (err) {
475 dev_err(chip->dev,
476 "p%d: %s: failed to read port status\n",
477 port, __func__);
478 return err;
479 }
480
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
482}
483
a5a6858b
RK		 484static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
486{
487 struct mv88e6xxx_chip *chip = ds->priv;
193c5b26 488 int lane;
a5a6858b
RK		 489 int err;
490
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 493 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
a5a6858b
RK		 494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
495 state);
496 else
497 err = -EOPNOTSUPP;
498 mv88e6xxx_reg_unlock(chip);
499
500 return err;
501}
502
503static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
504 unsigned int mode,
505 phy_interface_t interface,
506 const unsigned long *advertise)
507{
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
193c5b26 509 int lane;
a5a6858b
RK		 510
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 513 if (lane >= 0)
a5a6858b
RK		 514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
516 }
517
518 return 0;
519}
520
521static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
522{
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
525 int err = 0;
193c5b26 526 int lane;
a5a6858b
RK		 527
528 ops = chip->info->ops;
529
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 533 if (lane >= 0)
a5a6858b
RK		 534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
536
537 if (err)
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
539 }
540}
541
542static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
543 unsigned int mode,
544 int speed, int duplex)
545{
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
193c5b26 547 int lane;
a5a6858b
RK		 548
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 551 if (lane >= 0)
a5a6858b
RK		 552 return ops->serdes_pcs_link_up(chip, port, lane,
553 speed, duplex);
554 }
555
556 return 0;
557}
558
6c422e34
RK		 559static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
560 unsigned long *mask,
561 struct phylink_link_state *state)
562{
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
569 }
570}
571
572static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
573 unsigned long *mask,
574 struct phylink_link_state *state)
575{
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
578 */
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
581
582 mv88e6065_phylink_validate(chip, port, mask, state);
583}
584
e3af71a3
MB		 585static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
586 unsigned long *mask,
587 struct phylink_link_state *state)
588{
589 if (port >= 5)
590 phylink_set(mask, 2500baseX_Full);
591
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
595
596 mv88e6065_phylink_validate(chip, port, mask, state);
597}
598
6c422e34
RK		 599static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
600 unsigned long *mask,
601 struct phylink_link_state *state)
602{
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
606
607 mv88e6065_phylink_validate(chip, port, mask, state);
608}
609
610static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
611 unsigned long *mask,
612 struct phylink_link_state *state)
613{
ec26016b 614 if (port >= 9) {
6c422e34 615 phylink_set(mask, 2500baseX_Full);
ec26016b
AL		 616 phylink_set(mask, 2500baseT_Full);
617 }
6c422e34
RK		 618
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
622
623 mv88e6065_phylink_validate(chip, port, mask, state);
624}
625
626static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
627 unsigned long *mask,
628 struct phylink_link_state *state)
629{
630 if (port >= 9) {
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
633 }
634
635 mv88e6390_phylink_validate(chip, port, mask, state);
636}
637
de776d0d
PS		 638static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
639 unsigned long *mask,
640 struct phylink_link_state *state)
641{
642 if (port == 0 || port == 9 || port == 10) {
643 phylink_set(mask, 10000baseT_Full);
644 phylink_set(mask, 10000baseKR_Full);
645 phylink_set(mask, 10000baseCR_Full);
646 phylink_set(mask, 10000baseSR_Full);
647 phylink_set(mask, 10000baseLR_Full);
648 phylink_set(mask, 10000baseLRM_Full);
649 phylink_set(mask, 10000baseER_Full);
650 phylink_set(mask, 5000baseT_Full);
651 phylink_set(mask, 2500baseX_Full);
652 phylink_set(mask, 2500baseT_Full);
653 }
654
655 phylink_set(mask, 1000baseT_Full);
656 phylink_set(mask, 1000baseX_Full);
657
658 mv88e6065_phylink_validate(chip, port, mask, state);
659}
660
c9a2356f
RK		 661static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
662 unsigned long *supported,
663 struct phylink_link_state *state)
664{
6c422e34
RK		 665 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
666 struct mv88e6xxx_chip *chip = ds->priv;
667
668 /* Allow all the expected bits */
669 phylink_set(mask, Autoneg);
670 phylink_set(mask, Pause);
671 phylink_set_port_modes(mask);
672
673 if (chip->info->ops->phylink_validate)
674 chip->info->ops->phylink_validate(chip, port, mask, state);
675
676 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
677 bitmap_and(state->advertising, state->advertising, mask,
678 __ETHTOOL_LINK_MODE_MASK_NBITS);
679
680 /* We can only operate at 2500BaseX or 1000BaseX. If requested
681 * to advertise both, only report advertising at 2500BaseX.
682 */
683 phylink_helper_basex_speed(state);
c9a2356f
RK		 684}
685
c9a2356f
RK		 686static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
687 unsigned int mode,
688 const struct phylink_link_state *state)
689{
690 struct mv88e6xxx_chip *chip = ds->priv;
fad58190 691 struct mv88e6xxx_port *p;
64d47d50 692 int err;
c9a2356f 693
fad58190
RK		 694 p = &chip->ports[port];
695
64d47d50
RK		 696 /* FIXME: is this the correct test? If we're in fixed mode on an
697 * internal port, why should we process this any different from
698 * PHY mode? On the other hand, the port may be automedia between
699 * an internal PHY and the serdes...
700 */
d700ec41 701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
c9a2356f
RK		 702 return;
703
c9acece0 704 mv88e6xxx_reg_lock(chip);
fad58190
RK		 705 /* In inband mode, the link may come up at any time while the link
706 * is not forced down. Force the link down while we reconfigure the
707 * interface mode.
64d47d50 708 */
fad58190
RK		 709 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
710 chip->info->ops->port_set_link)
711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
712
64d47d50 713 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
a5a6858b
RK		 714 if (err && err != -EOPNOTSUPP)
715 goto err_unlock;
716
717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
718 state->advertising);
719 /* FIXME: we should restart negotiation if something changed - which
720 * is something we get if we convert to using phylinks PCS operations.
721 */
722 if (err > 0)
723 err = 0;
724
fad58190
RK		 725 /* Undo the forced down state above after completing configuration
726 * irrespective of its state on entry, which allows the link to come up.
727 */
728 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
729 chip->info->ops->port_set_link)
730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
731
732 p->interface = state->interface;
733
a5a6858b 734err_unlock:
c9acece0 735 mv88e6xxx_reg_unlock(chip);
c9a2356f
RK		 736
737 if (err && err != -EOPNOTSUPP)
64d47d50 738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
c9a2356f
RK		 739}
740
30c4a5b0
RK		 741static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
742 unsigned int mode,
743 phy_interface_t interface)
c9a2356f
RK		 744{
745 struct mv88e6xxx_chip *chip = ds->priv;
30c4a5b0
RK		 746 const struct mv88e6xxx_ops *ops;
747 int err = 0;
c9a2356f 748
30c4a5b0 749 ops = chip->info->ops;
c9a2356f 750
5d5b231d 751 mv88e6xxx_reg_lock(chip);
34b5e6a3 752 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
4efe7662
CP		 753 mode == MLO_AN_FIXED) && ops->port_sync_link)
754 err = ops->port_sync_link(chip, port, mode, false);
5d5b231d 755 mv88e6xxx_reg_unlock(chip);
c9a2356f 756
5d5b231d
RK		 757 if (err)
758 dev_err(chip->dev,
759 "p%d: failed to force MAC link down\n", port);
c9a2356f
RK		 760}
761
762static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
763 unsigned int mode, phy_interface_t interface,
5b502a7b
RK		 764 struct phy_device *phydev,
765 int speed, int duplex,
766 bool tx_pause, bool rx_pause)
c9a2356f 767{
30c4a5b0
RK		 768 struct mv88e6xxx_chip *chip = ds->priv;
769 const struct mv88e6xxx_ops *ops;
770 int err = 0;
771
772 ops = chip->info->ops;
773
5d5b231d 774 mv88e6xxx_reg_lock(chip);
34b5e6a3 775 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
30c4a5b0
RK		 776 /* FIXME: for an automedia port, should we force the link
777 * down here - what if the link comes up due to "other" media
778 * while we're bringing the port up, how is the exclusivity
a5a6858b 779 * handled in the Marvell hardware? E.g. port 2 on 88E6390
30c4a5b0
RK		 780 * shared between internal PHY and Serdes.
781 */
a5a6858b
RK		 782 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
783 duplex);
784 if (err)
785 goto error;
786
f365c6f7
RK		 787 if (ops->port_set_speed_duplex) {
788 err = ops->port_set_speed_duplex(chip, port,
789 speed, duplex);
30c4a5b0
RK		 790 if (err && err != -EOPNOTSUPP)
791 goto error;
792 }
793
4efe7662
CP		 794 if (ops->port_sync_link)
795 err = ops->port_sync_link(chip, port, mode, true);
5d5b231d 796 }
30c4a5b0 797error:
5d5b231d 798 mv88e6xxx_reg_unlock(chip);
30c4a5b0 799
5d5b231d
RK		 800 if (err && err != -EOPNOTSUPP)
801 dev_err(ds->dev,
802 "p%d: failed to configure MAC link up\n", port);
c9a2356f
RK		 803}
804
a605a0fe 805static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 806{
a605a0fe
AL		 807 if (!chip->info->ops->stats_snapshot)
808 return -EOPNOTSUPP;
91da11f8 809
a605a0fe 810 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 811}
812
e413e7e1 813static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 814 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
815 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
816 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
817 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
818 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
819 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
820 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
821 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
822 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
823 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
824 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
825 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
826 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
827 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
828 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
829 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
830 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
831 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
832 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
833 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
834 { "single", 4, 0x14, STATS_TYPE_BANK0, },
835 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
836 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
837 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
838 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
839 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
840 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
841 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
842 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
843 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
844 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
845 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
846 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
847 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
848 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
849 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
850 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
851 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
852 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
853 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
854 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
855 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
856 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
857 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
858 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
859 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
860 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
861 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
862 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
863 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
864 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
865 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
866 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
867 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
868 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
869 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
870 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
871 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
872 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 873};
874
fad09c73 875static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 876 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 877 int port, u16 bank1_select,
878 u16 histogram)
80c4627b 879{
80c4627b
AL		 880 u32 low;
881 u32 high = 0;
dfafe449 882 u16 reg = 0;
0e7b9925 883 int err;
80c4627b
AL		 884 u64 value;
885
f5e2ed02 886 switch (s->type) {
dfafe449 887 case STATS_TYPE_PORT:
0e7b9925
AL		 888 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
889 if (err)
6c3442f5 890 return U64_MAX;
80c4627b 891
0e7b9925 892 low = reg;
cda9f4aa 893 if (s->size == 4) {
0e7b9925
AL		 894 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
895 if (err)
6c3442f5 896 return U64_MAX;
84b3fd1f 897 low |= ((u32)reg) << 16;
80c4627b 898 }
f5e2ed02 899 break;
dfafe449 900 case STATS_TYPE_BANK1:
e0d8b615 901 reg = bank1_select;
df561f66 902 fallthrough;
dfafe449 903 case STATS_TYPE_BANK0:
e0d8b615 904 reg |= s->reg | histogram;
7f9ef3af 905 mv88e6xxx_g1_stats_read(chip, reg, &low);
cda9f4aa 906 if (s->size == 8)
7f9ef3af 907 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 908 break;
909 default:
6c3442f5 910 return U64_MAX;
80c4627b 911 }
6e46e2d8 912 value = (((u64)high) << 32) | low;
80c4627b
AL		 913 return value;
914}
915
436fe17d
AL		 916static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
917 uint8_t *data, int types)
91da11f8 918{
f5e2ed02
AL		 919 struct mv88e6xxx_hw_stat *stat;
920 int i, j;
91da11f8 921
f5e2ed02
AL		 922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
923 stat = &mv88e6xxx_hw_stats[i];
dfafe449 924 if (stat->type & types) {
f5e2ed02
AL		 925 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
926 ETH_GSTRING_LEN);
927 j++;
928 }
91da11f8 929 }
436fe17d
AL		 930
931 return j;
e413e7e1
AL		 932}
933
436fe17d
AL		 934static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
935 uint8_t *data)
dfafe449 936{
436fe17d
AL		 937 return mv88e6xxx_stats_get_strings(chip, data,
938 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
dfafe449
AL		 939}
940
1f71836f
RV		 941static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
942 uint8_t *data)
943{
944 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
945}
946
436fe17d
AL		 947static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
948 uint8_t *data)
dfafe449 949{
436fe17d
AL		 950 return mv88e6xxx_stats_get_strings(chip, data,
951 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
dfafe449
AL		 952}
953
65f60e45
AL		 954static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
955 "atu_member_violation",
956 "atu_miss_violation",
957 "atu_full_violation",
958 "vtu_member_violation",
959 "vtu_miss_violation",
960};
961
962static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
963{
964 unsigned int i;
965
966 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
967 strlcpy(data + i * ETH_GSTRING_LEN,
968 mv88e6xxx_atu_vtu_stats_strings[i],
969 ETH_GSTRING_LEN);
970}
971
dfafe449 972static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
89f09048 973 u32 stringset, uint8_t *data)
e413e7e1 974{
04bed143 975 struct mv88e6xxx_chip *chip = ds->priv;
436fe17d 976 int count = 0;
dfafe449 977
89f09048
FF		 978 if (stringset != ETH_SS_STATS)
979 return;
980
c9acece0 981 mv88e6xxx_reg_lock(chip);
c6c8cd5e 982
dfafe449 983 if (chip->info->ops->stats_get_strings)
436fe17d
AL		 984 count = chip->info->ops->stats_get_strings(chip, data);
985
986 if (chip->info->ops->serdes_get_strings) {
987 data += count * ETH_GSTRING_LEN;
65f60e45 988 count = chip->info->ops->serdes_get_strings(chip, port, data);
436fe17d 989 }
c6c8cd5e 990
65f60e45
AL		 991 data += count * ETH_GSTRING_LEN;
992 mv88e6xxx_atu_vtu_get_strings(data);
993
c9acece0 994 mv88e6xxx_reg_unlock(chip);
dfafe449
AL		 995}
996
997static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
998 int types)
999{
f5e2ed02
AL		 1000 struct mv88e6xxx_hw_stat *stat;
1001 int i, j;
1002
1003 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1004 stat = &mv88e6xxx_hw_stats[i];
dfafe449 1005 if (stat->type & types)
f5e2ed02
AL		 1006 j++;
1007 }
1008 return j;
e413e7e1
AL		 1009}
1010
dfafe449
AL		 1011static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1012{
1013 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1014 STATS_TYPE_PORT);
1015}
1016
1f71836f
RV		 1017static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1018{
1019 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1020}
1021
dfafe449
AL		 1022static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1023{
1024 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1025 STATS_TYPE_BANK1);
1026}
1027
89f09048 1028static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
dfafe449
AL		 1029{
1030 struct mv88e6xxx_chip *chip = ds->priv;
436fe17d
AL		 1031 int serdes_count = 0;
1032 int count = 0;
dfafe449 1033
89f09048
FF		 1034 if (sset != ETH_SS_STATS)
1035 return 0;
1036
c9acece0 1037 mv88e6xxx_reg_lock(chip);
dfafe449 1038 if (chip->info->ops->stats_get_sset_count)
436fe17d
AL		 1039 count = chip->info->ops->stats_get_sset_count(chip);
1040 if (count < 0)
1041 goto out;
1042
1043 if (chip->info->ops->serdes_get_sset_count)
1044 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1045 port);
65f60e45 1046 if (serdes_count < 0) {
436fe17d 1047 count = serdes_count;
65f60e45
AL		 1048 goto out;
1049 }
1050 count += serdes_count;
1051 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1052
436fe17d 1053out:
c9acece0 1054 mv88e6xxx_reg_unlock(chip);
dfafe449 1055
436fe17d 1056 return count;
dfafe449
AL		 1057}
1058
436fe17d
AL		 1059static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1060 uint64_t *data, int types,
1061 u16 bank1_select, u16 histogram)
052f947f
AL		 1062{
1063 struct mv88e6xxx_hw_stat *stat;
1064 int i, j;
1065
1066 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1067 stat = &mv88e6xxx_hw_stats[i];
1068 if (stat->type & types) {
c9acece0 1069 mv88e6xxx_reg_lock(chip);
e0d8b615
AL		 1070 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1071 bank1_select,
1072 histogram);
c9acece0 1073 mv88e6xxx_reg_unlock(chip);
377cda13 1074
052f947f
AL		 1075 j++;
1076 }
1077 }
436fe17d 1078 return j;
052f947f
AL		 1079}
1080
436fe17d
AL		 1081static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1082 uint64_t *data)
052f947f
AL		 1083{
1084 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 1085 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 1086 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 1087}
1088
1f71836f
RV		 1089static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1090 uint64_t *data)
1091{
1092 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1093 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1094}
1095
436fe17d
AL		 1096static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1097 uint64_t *data)
052f947f
AL		 1098{
1099 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 1100 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 1101 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1102 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 1103}
1104
436fe17d
AL		 1105static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1106 uint64_t *data)
e0d8b615
AL		 1107{
1108 return mv88e6xxx_stats_get_stats(chip, port, data,
1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 1110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1111 0);
052f947f
AL		 1112}
1113
65f60e45
AL		 1114static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1115 uint64_t *data)
1116{
1117 *data++ = chip->ports[port].atu_member_violation;
1118 *data++ = chip->ports[port].atu_miss_violation;
1119 *data++ = chip->ports[port].atu_full_violation;
1120 *data++ = chip->ports[port].vtu_member_violation;
1121 *data++ = chip->ports[port].vtu_miss_violation;
1122}
1123
052f947f
AL		 1124static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1125 uint64_t *data)
1126{
436fe17d
AL		 1127 int count = 0;
1128
052f947f 1129 if (chip->info->ops->stats_get_stats)
436fe17d
AL		 1130 count = chip->info->ops->stats_get_stats(chip, port, data);
1131
c9acece0 1132 mv88e6xxx_reg_lock(chip);
436fe17d
AL		 1133 if (chip->info->ops->serdes_get_stats) {
1134 data += count;
65f60e45 1135 count = chip->info->ops->serdes_get_stats(chip, port, data);
436fe17d 1136 }
65f60e45
AL		 1137 data += count;
1138 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
c9acece0 1139 mv88e6xxx_reg_unlock(chip);
052f947f
AL		 1140}
1141
f81ec90f
VD		 1142static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1143 uint64_t *data)
e413e7e1 1144{
04bed143 1145 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1146 int ret;
f5e2ed02 1147
c9acece0 1148 mv88e6xxx_reg_lock(chip);
f5e2ed02 1149
a605a0fe 1150 ret = mv88e6xxx_stats_snapshot(chip, port);
c9acece0 1151 mv88e6xxx_reg_unlock(chip);
377cda13
AL		 1152
1153 if (ret < 0)
f5e2ed02 1154 return;
052f947f
AL		 1155
1156 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1157
e413e7e1
AL		 1158}
1159
f81ec90f 1160static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3 1161{
0d30bbd0
AL		 1162 struct mv88e6xxx_chip *chip = ds->priv;
1163 int len;
1164
1165 len = 32 * sizeof(u16);
1166 if (chip->info->ops->serdes_get_regs_len)
1167 len += chip->info->ops->serdes_get_regs_len(chip, port);
1168
1169 return len;
a1ab91f3
GR		 1170}
1171
f81ec90f
VD		 1172static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1173 struct ethtool_regs *regs, void *_p)
a1ab91f3 1174{
04bed143 1175 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1176 int err;
1177 u16 reg;
a1ab91f3
GR		 1178 u16 *p = _p;
1179 int i;
1180
a5f39326 1181 regs->version = chip->info->prod_num;
a1ab91f3
GR		 1182
1183 memset(p, 0xff, 32 * sizeof(u16));
1184
c9acece0 1185 mv88e6xxx_reg_lock(chip);
23062513 1186
a1ab91f3 1187 for (i = 0; i < 32; i++) {
a1ab91f3 1188
0e7b9925
AL		 1189 err = mv88e6xxx_port_read(chip, port, i, &reg);
1190 if (!err)
1191 p[i] = reg;
a1ab91f3 1192 }
23062513 1193
0d30bbd0
AL		 1194 if (chip->info->ops->serdes_get_regs)
1195 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1196
c9acece0 1197 mv88e6xxx_reg_unlock(chip);
a1ab91f3
GR		 1198}
1199
08f50061
VD		 1200static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1201 struct ethtool_eee *e)
68b8f60c 1202{
5480db69
VD		 1203 /* Nothing to do on the port's MAC */
1204 return 0;
11b3b45d
GR		 1205}
1206
08f50061
VD		 1207static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1208 struct ethtool_eee *e)
11b3b45d 1209{
5480db69
VD		 1210 /* Nothing to do on the port's MAC */
1211 return 0;
11b3b45d
GR		 1212}
1213
9dc8b13e 1214/* Mask of the local ports allowed to receive frames from a given fabric port */
e5887a2a 1215static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 1216{
9dc8b13e
VD		 1217 struct dsa_switch *ds = chip->ds;
1218 struct dsa_switch_tree *dst = ds->dst;
e5887a2a 1219 struct net_device *br;
9dc8b13e
VD		 1220 struct dsa_port *dp;
1221 bool found = false;
e5887a2a 1222 u16 pvlan;
b7666efe 1223
ce5df689
VO		 1224 /* dev is a physical switch */
1225 if (dev <= dst->last_switch) {
1226 list_for_each_entry(dp, &dst->ports, list) {
1227 if (dp->ds->index == dev && dp->index == port) {
1228 /* dp might be a DSA link or a user port, so it
1229 * might or might not have a bridge_dev
1230 * pointer. Use the "found" variable for both
1231 * cases.
1232 */
1233 br = dp->bridge_dev;
1234 found = true;
1235 break;
1236 }
1237 }
1238 /* dev is a virtual bridge */
1239 } else {
1240 list_for_each_entry(dp, &dst->ports, list) {
1241 if (dp->bridge_num < 0)
1242 continue;
1243
1244 if (dp->bridge_num + 1 + dst->last_switch != dev)
1245 continue;
1246
1247 br = dp->bridge_dev;
9dc8b13e
VD		 1248 found = true;
1249 break;
1250 }
1251 }
e5887a2a 1252
ce5df689 1253 /* Prevent frames from unknown switch or virtual bridge */
9dc8b13e 1254 if (!found)
e5887a2a
VD		 1255 return 0;
1256
1257 /* Frames from DSA links and CPU ports can egress any local port */
9dc8b13e 1258 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
e5887a2a
VD		 1259 return mv88e6xxx_port_mask(chip);
1260
e5887a2a
VD		 1261 pvlan = 0;
1262
1263 /* Frames from user ports can egress any local DSA links and CPU ports,
1264 * as well as any local member of their bridge group.
1265 */
9dc8b13e
VD		 1266 list_for_each_entry(dp, &dst->ports, list)
1267 if (dp->ds == ds &&
1268 (dp->type == DSA_PORT_TYPE_CPU ||
1269 dp->type == DSA_PORT_TYPE_DSA ||
1270 (br && dp->bridge_dev == br)))
1271 pvlan |= BIT(dp->index);
e5887a2a
VD		 1272
1273 return pvlan;
1274}
1275
240ea3ef 1276static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 1277{
1278 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 1279
1280 /* prevent frames from going back out of the port they came in on */
1281 output_ports &= ~BIT(port);
facd95b2 1282
5a7921f4 1283 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1284}
1285
f81ec90f
VD		 1286static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1287 u8 state)
facd95b2 1288{
04bed143 1289 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 1290 int err;
facd95b2 1291
c9acece0 1292 mv88e6xxx_reg_lock(chip);
f894c29c 1293 err = mv88e6xxx_port_set_state(chip, port, state);
c9acece0 1294 mv88e6xxx_reg_unlock(chip);
553eb544
VD		 1295
1296 if (err)
774439e5 1297 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 1298}
1299
93e18d61
VD		 1300static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1301{
1302 int err;
1303
1304 if (chip->info->ops->ieee_pri_map) {
1305 err = chip->info->ops->ieee_pri_map(chip);
1306 if (err)
1307 return err;
1308 }
1309
1310 if (chip->info->ops->ip_pri_map) {
1311 err = chip->info->ops->ip_pri_map(chip);
1312 if (err)
1313 return err;
1314 }
1315
1316 return 0;
1317}
1318
c7f047b6
VD		 1319static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1320{
c5f51765 1321 struct dsa_switch *ds = chip->ds;
c7f047b6
VD		 1322 int target, port;
1323 int err;
1324
1325 if (!chip->info->global2_addr)
1326 return 0;
1327
1328 /* Initialize the routing port to the 32 possible target devices */
1329 for (target = 0; target < 32; target++) {
c5f51765
VD		 1330 port = dsa_routing_port(ds, target);
1331 if (port == ds->num_ports)
1332 port = 0x1f;
c7f047b6
VD		 1333
1334 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1335 if (err)
1336 return err;
1337 }
1338
02317e68
VD		 1339 if (chip->info->ops->set_cascade_port) {
1340 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1341 err = chip->info->ops->set_cascade_port(chip, port);
1342 if (err)
1343 return err;
1344 }
1345
23c98919
VD		 1346 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1347 if (err)
1348 return err;
1349
c7f047b6
VD		 1350 return 0;
1351}
1352
b28f872d
VD		 1353static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1354{
1355 /* Clear all trunk masks and mapping */
1356 if (chip->info->global2_addr)
1357 return mv88e6xxx_g2_trunk_clear(chip);
1358
1359 return 0;
1360}
1361
9e5baf9b
VD		 1362static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1363{
1364 if (chip->info->ops->rmu_disable)
1365 return chip->info->ops->rmu_disable(chip);
1366
1367 return 0;
1368}
1369
9e907d73
VD		 1370static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1371{
1372 if (chip->info->ops->pot_clear)
1373 return chip->info->ops->pot_clear(chip);
1374
1375 return 0;
1376}
1377
51c901a7
VD		 1378static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1379{
1380 if (chip->info->ops->mgmt_rsvd2cpu)
1381 return chip->info->ops->mgmt_rsvd2cpu(chip);
1382
1383 return 0;
1384}
1385
a2ac29d2
VD		 1386static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1387{
c3a7d4ad
VD		 1388 int err;
1389
daefc943
VD		 1390 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1391 if (err)
1392 return err;
1393
49506a9b
RV		 1394 /* The chips that have a "learn2all" bit in Global1, ATU
1395 * Control are precisely those whose port registers have a
1396 * Message Port bit in Port Control 1 and hence implement
1397 * ->port_setup_message_port.
1398 */
1399 if (chip->info->ops->port_setup_message_port) {
1400 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1401 if (err)
1402 return err;
1403 }
c3a7d4ad 1404
a2ac29d2
VD		 1405 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1406}
1407
cd8da8bb
VD		 1408static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1409{
1410 int port;
1411 int err;
1412
1413 if (!chip->info->ops->irl_init_all)
1414 return 0;
1415
1416 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1417 /* Disable ingress rate limiting by resetting all per port
1418 * ingress rate limit resources to their initial state.
1419 */
1420 err = chip->info->ops->irl_init_all(chip, port);
1421 if (err)
1422 return err;
1423 }
1424
1425 return 0;
1426}
1427
04a69a17
VD		 1428static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1429{
1430 if (chip->info->ops->set_switch_mac) {
1431 u8 addr[ETH_ALEN];
1432
1433 eth_random_addr(addr);
1434
1435 return chip->info->ops->set_switch_mac(chip, addr);
1436 }
1437
1438 return 0;
1439}
1440
17a1594e
VD		 1441static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1442{
57e661aa
TW		 1443 struct dsa_switch_tree *dst = chip->ds->dst;
1444 struct dsa_switch *ds;
1445 struct dsa_port *dp;
17a1594e
VD		 1446 u16 pvlan = 0;
1447
1448 if (!mv88e6xxx_has_pvt(chip))
d14939be 1449 return 0;
17a1594e
VD		 1450
1451 /* Skip the local source device, which uses in-chip port VLAN */
57e661aa 1452 if (dev != chip->ds->index) {
aec5ac88 1453 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e 1454
57e661aa
TW		 1455 ds = dsa_switch_find(dst->index, dev);
1456 dp = ds ? dsa_to_port(ds, port) : NULL;
1457 if (dp && dp->lag_dev) {
1458 /* As the PVT is used to limit flooding of
1459 * FORWARD frames, which use the LAG ID as the
1460 * source port, we must translate dev/port to
1461 * the special "LAG device" in the PVT, using
1462 * the LAG ID as the port number.
1463 */
78e70dbc 1464 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
57e661aa
TW		 1465 port = dsa_lag_id(dst, dp->lag_dev);
1466 }
1467 }
1468
17a1594e
VD		 1469 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1470}
1471
81228996
VD		 1472static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1473{
17a1594e
VD		 1474 int dev, port;
1475 int err;
1476
81228996
VD		 1477 if (!mv88e6xxx_has_pvt(chip))
1478 return 0;
1479
1480 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1481 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1482 */
17a1594e
VD		 1483 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1484 if (err)
1485 return err;
1486
1487 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1488 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1489 err = mv88e6xxx_pvt_map(chip, dev, port);
1490 if (err)
1491 return err;
1492 }
1493 }
1494
1495 return 0;
81228996
VD		 1496}
1497
749efcb8
VD		 1498static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1499{
1500 struct mv88e6xxx_chip *chip = ds->priv;
1501 int err;
1502
ffcec3f2
TW		 1503 if (dsa_to_port(ds, port)->lag_dev)
1504 /* Hardware is incapable of fast-aging a LAG through a
1505 * regular ATU move operation. Until we have something
1506 * more fancy in place this is a no-op.
1507 */
1508 return;
1509
c9acece0 1510 mv88e6xxx_reg_lock(chip);
e606ca36 1511 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
c9acece0 1512 mv88e6xxx_reg_unlock(chip);
749efcb8
VD		 1513
1514 if (err)
774439e5 1515 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 1516}
1517
b486d7c9
VD		 1518static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1519{
e545f865 1520 if (!mv88e6xxx_max_vid(chip))
b486d7c9
VD		 1521 return 0;
1522
1523 return mv88e6xxx_g1_vtu_flush(chip);
1524}
1525
34065c58
TW		 1526static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1527 struct mv88e6xxx_vtu_entry *entry)
f1394b78 1528{
34065c58
TW		 1529 int err;
1530
f1394b78
VD		 1531 if (!chip->info->ops->vtu_getnext)
1532 return -EOPNOTSUPP;
1533
34065c58
TW		 1534 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1535 entry->valid = false;
1536
1537 err = chip->info->ops->vtu_getnext(chip, entry);
1538
1539 if (entry->vid != vid)
1540 entry->valid = false;
1541
1542 return err;
f1394b78
VD		 1543}
1544
d89ef4b8
TW		 1545static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1546 int (*cb)(struct mv88e6xxx_chip *chip,
1547 const struct mv88e6xxx_vtu_entry *entry,
1548 void *priv),
1549 void *priv)
1550{
1551 struct mv88e6xxx_vtu_entry entry = {
1552 .vid = mv88e6xxx_max_vid(chip),
1553 .valid = false,
1554 };
1555 int err;
1556
1557 if (!chip->info->ops->vtu_getnext)
1558 return -EOPNOTSUPP;
1559
1560 do {
1561 err = chip->info->ops->vtu_getnext(chip, &entry);
1562 if (err)
1563 return err;
1564
1565 if (!entry.valid)
1566 break;
1567
1568 err = cb(chip, &entry, priv);
1569 if (err)
1570 return err;
1571 } while (entry.vid < mv88e6xxx_max_vid(chip));
1572
1573 return 0;
1574}
1575
0ad5daf6
VD		 1576static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1577 struct mv88e6xxx_vtu_entry *entry)
1578{
1579 if (!chip->info->ops->vtu_loadpurge)
1580 return -EOPNOTSUPP;
1581
1582 return chip->info->ops->vtu_loadpurge(chip, entry);
1583}
1584
d89ef4b8
TW		 1585static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1586 const struct mv88e6xxx_vtu_entry *entry,
1587 void *_fid_bitmap)
1588{
1589 unsigned long *fid_bitmap = _fid_bitmap;
1590
1591 set_bit(entry->fid, fid_bitmap);
1592 return 0;
1593}
1594
90b6dbdf 1595int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
3285f9e8 1596{
2db9ce1f 1597 int i, err;
90b6dbdf 1598 u16 fid;
3285f9e8
VD		 1599
1600 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1601
2db9ce1f 1602 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1603 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
90b6dbdf 1604 err = mv88e6xxx_port_get_fid(chip, i, &fid);
2db9ce1f
VD		 1605 if (err)
1606 return err;
1607
90b6dbdf 1608 set_bit(fid, fid_bitmap);
2db9ce1f
VD		 1609 }
1610
3285f9e8 1611 /* Set every FID bit used by the VLAN entries */
d89ef4b8 1612 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
90b6dbdf
AL		 1613}
1614
1615static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1616{
1617 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1618 int err;
1619
1620 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1621 if (err)
1622 return err;
1623
3285f9e8
VD		 1624 /* The reset value 0x000 is used to indicate that multiple address
1625 * databases are not needed. Return the next positive available.
1626 */
1627 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1628 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1629 return -ENOSPC;
1630
1631 /* Clear the database */
daefc943 1632 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1633}
1634
da9c359e 1635static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
b7a9e0da 1636 u16 vid)
da9c359e 1637{
04bed143 1638 struct mv88e6xxx_chip *chip = ds->priv;
425d2d37 1639 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1640 int i, err;
1641
db06ae41
AL		 1642 /* DSA and CPU ports have to be members of multiple vlans */
1643 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1644 return 0;
1645
34065c58 1646 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
b7a9e0da
VO		 1647 if (err)
1648 return err;
da9c359e 1649
b7a9e0da
VO		 1650 if (!vlan.valid)
1651 return 0;
da9c359e 1652
b7a9e0da
VO		 1653 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1654 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1655 continue;
da9c359e 1656
b7a9e0da
VO		 1657 if (!dsa_to_port(ds, i)->slave)
1658 continue;
66e2809d 1659
b7a9e0da
VO		 1660 if (vlan.member[i] ==
1661 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1662 continue;
da9c359e 1663
b7a9e0da
VO		 1664 if (dsa_to_port(ds, i)->bridge_dev ==
1665 dsa_to_port(ds, port)->bridge_dev)
1666 break; /* same bridge, check next VLAN */
da9c359e 1667
b7a9e0da
VO		 1668 if (!dsa_to_port(ds, i)->bridge_dev)
1669 continue;
66e2809d 1670
b7a9e0da
VO		 1671 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1672 port, vlan.vid, i,
1673 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1674 return -EOPNOTSUPP;
1675 }
da9c359e 1676
7095a4c4 1677 return 0;
da9c359e
VD		 1678}
1679
f81ec90f 1680static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
89153ed6
VO		 1681 bool vlan_filtering,
1682 struct netlink_ext_ack *extack)
214cdb99 1683{
04bed143 1684 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1685 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1686 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1687 int err;
214cdb99 1688
bae33f2b
VO		 1689 if (!mv88e6xxx_max_vid(chip))
1690 return -EOPNOTSUPP;
54d77b5b 1691
c9acece0 1692 mv88e6xxx_reg_lock(chip);
385a0995 1693 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
c9acece0 1694 mv88e6xxx_reg_unlock(chip);
214cdb99 1695
0e7b9925 1696 return err;
214cdb99
VD		 1697}
1698
57d32310
VD		 1699static int
1700mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
80e02360 1701 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1702{
04bed143 1703 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1704 int err;
1705
e545f865 1706 if (!mv88e6xxx_max_vid(chip))
54d77b5b
VD		 1707 return -EOPNOTSUPP;
1708
da9c359e
VD		 1709 /* If the requested port doesn't belong to the same bridge as the VLAN
1710 * members, do not support it (yet) and fallback to software VLAN.
1711 */
7095a4c4 1712 mv88e6xxx_reg_lock(chip);
b7a9e0da 1713 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
7095a4c4 1714 mv88e6xxx_reg_unlock(chip);
da9c359e 1715
7095a4c4 1716 return err;
76e398a6
VD		 1717}
1718
a4c93ae1
AL		 1719static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1720 const unsigned char *addr, u16 vid,
1721 u8 state)
1722{
a4c93ae1 1723 struct mv88e6xxx_atu_entry entry;
5ef8d249
VD		 1724 struct mv88e6xxx_vtu_entry vlan;
1725 u16 fid;
a4c93ae1
AL		 1726 int err;
1727
1728 /* Null VLAN ID corresponds to the port private database */
5ef8d249
VD		 1729 if (vid == 0) {
1730 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1731 if (err)
1732 return err;
1733 } else {
34065c58 1734 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
5ef8d249
VD		 1735 if (err)
1736 return err;
1737
1738 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
34065c58 1739 if (!vlan.valid)
5ef8d249
VD		 1740 return -EOPNOTSUPP;
1741
1742 fid = vlan.fid;
1743 }
a4c93ae1 1744
d8291a95 1745 entry.state = 0;
a4c93ae1
AL		 1746 ether_addr_copy(entry.mac, addr);
1747 eth_addr_dec(entry.mac);
1748
5ef8d249 1749 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
a4c93ae1
AL		 1750 if (err)
1751 return err;
1752
1753 /* Initialize a fresh ATU entry if it isn't found */
d8291a95 1754 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
a4c93ae1
AL		 1755 memset(&entry, 0, sizeof(entry));
1756 ether_addr_copy(entry.mac, addr);
1757 }
1758
1759 /* Purge the ATU entry only if no port is using it anymore */
d8291a95 1760 if (!state) {
a4c93ae1
AL		 1761 entry.portvec &= ~BIT(port);
1762 if (!entry.portvec)
d8291a95 1763 entry.state = 0;
a4c93ae1 1764 } else {
f72f2fb8
DQ		 1765 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1766 entry.portvec = BIT(port);
1767 else
1768 entry.portvec |= BIT(port);
1769
a4c93ae1
AL		 1770 entry.state = state;
1771 }
1772
5ef8d249 1773 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
a4c93ae1
AL		 1774}
1775
da7dc875
VD		 1776static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1777 const struct mv88e6xxx_policy *policy)
1778{
1779 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1780 enum mv88e6xxx_policy_action action = policy->action;
1781 const u8 *addr = policy->addr;
1782 u16 vid = policy->vid;
1783 u8 state;
1784 int err;
1785 int id;
1786
1787 if (!chip->info->ops->port_set_policy)
1788 return -EOPNOTSUPP;
1789
1790 switch (mapping) {
1791 case MV88E6XXX_POLICY_MAPPING_DA:
1792 case MV88E6XXX_POLICY_MAPPING_SA:
1793 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1794 state = 0; /* Dissociate the port and address */
1795 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1796 is_multicast_ether_addr(addr))
1797 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1798 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1799 is_unicast_ether_addr(addr))
1800 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1801 else
1802 return -EOPNOTSUPP;
1803
1804 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1805 state);
1806 if (err)
1807 return err;
1808 break;
1809 default:
1810 return -EOPNOTSUPP;
1811 }
1812
1813 /* Skip the port's policy clearing if the mapping is still in use */
1814 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1815 idr_for_each_entry(&chip->policies, policy, id)
1816 if (policy->port == port &&
1817 policy->mapping == mapping &&
1818 policy->action != action)
1819 return 0;
1820
1821 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1822}
1823
1824static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1825 struct ethtool_rx_flow_spec *fs)
1826{
1827 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1828 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1829 enum mv88e6xxx_policy_mapping mapping;
1830 enum mv88e6xxx_policy_action action;
1831 struct mv88e6xxx_policy *policy;
1832 u16 vid = 0;
1833 u8 *addr;
1834 int err;
1835 int id;
1836
1837 if (fs->location != RX_CLS_LOC_ANY)
1838 return -EINVAL;
1839
1840 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1841 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1842 else
1843 return -EOPNOTSUPP;
1844
1845 switch (fs->flow_type & ~FLOW_EXT) {
1846 case ETHER_FLOW:
1847 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1848 is_zero_ether_addr(mac_mask->h_source)) {
1849 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1850 addr = mac_entry->h_dest;
1851 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1852 !is_zero_ether_addr(mac_mask->h_source)) {
1853 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1854 addr = mac_entry->h_source;
1855 } else {
1856 /* Cannot support DA and SA mapping in the same rule */
1857 return -EOPNOTSUPP;
1858 }
1859 break;
1860 default:
1861 return -EOPNOTSUPP;
1862 }
1863
1864 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
04844280 1865 if (fs->m_ext.vlan_tci != htons(0xffff))
da7dc875
VD		 1866 return -EOPNOTSUPP;
1867 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1868 }
1869
1870 idr_for_each_entry(&chip->policies, policy, id) {
1871 if (policy->port == port && policy->mapping == mapping &&
1872 policy->action == action && policy->vid == vid &&
1873 ether_addr_equal(policy->addr, addr))
1874 return -EEXIST;
1875 }
1876
1877 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1878 if (!policy)
1879 return -ENOMEM;
1880
1881 fs->location = 0;
1882 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1883 GFP_KERNEL);
1884 if (err) {
1885 devm_kfree(chip->dev, policy);
1886 return err;
1887 }
1888
1889 memcpy(&policy->fs, fs, sizeof(*fs));
1890 ether_addr_copy(policy->addr, addr);
1891 policy->mapping = mapping;
1892 policy->action = action;
1893 policy->port = port;
1894 policy->vid = vid;
1895
1896 err = mv88e6xxx_policy_apply(chip, port, policy);
1897 if (err) {
1898 idr_remove(&chip->policies, fs->location);
1899 devm_kfree(chip->dev, policy);
1900 return err;
1901 }
1902
1903 return 0;
1904}
1905
1906static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1907 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1908{
1909 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1910 struct mv88e6xxx_chip *chip = ds->priv;
1911 struct mv88e6xxx_policy *policy;
1912 int err;
1913 int id;
1914
1915 mv88e6xxx_reg_lock(chip);
1916
1917 switch (rxnfc->cmd) {
1918 case ETHTOOL_GRXCLSRLCNT:
1919 rxnfc->data = 0;
1920 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1921 rxnfc->rule_cnt = 0;
1922 idr_for_each_entry(&chip->policies, policy, id)
1923 if (policy->port == port)
1924 rxnfc->rule_cnt++;
1925 err = 0;
1926 break;
1927 case ETHTOOL_GRXCLSRULE:
1928 err = -ENOENT;
1929 policy = idr_find(&chip->policies, fs->location);
1930 if (policy) {
1931 memcpy(fs, &policy->fs, sizeof(*fs));
1932 err = 0;
1933 }
1934 break;
1935 case ETHTOOL_GRXCLSRLALL:
1936 rxnfc->data = 0;
1937 rxnfc->rule_cnt = 0;
1938 idr_for_each_entry(&chip->policies, policy, id)
1939 if (policy->port == port)
1940 rule_locs[rxnfc->rule_cnt++] = id;
1941 err = 0;
1942 break;
1943 default:
1944 err = -EOPNOTSUPP;
1945 break;
1946 }
1947
1948 mv88e6xxx_reg_unlock(chip);
1949
1950 return err;
1951}
1952
1953static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1954 struct ethtool_rxnfc *rxnfc)
1955{
1956 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1957 struct mv88e6xxx_chip *chip = ds->priv;
1958 struct mv88e6xxx_policy *policy;
1959 int err;
1960
1961 mv88e6xxx_reg_lock(chip);
1962
1963 switch (rxnfc->cmd) {
1964 case ETHTOOL_SRXCLSRLINS:
1965 err = mv88e6xxx_policy_insert(chip, port, fs);
1966 break;
1967 case ETHTOOL_SRXCLSRLDEL:
1968 err = -ENOENT;
1969 policy = idr_remove(&chip->policies, fs->location);
1970 if (policy) {
1971 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1972 err = mv88e6xxx_policy_apply(chip, port, policy);
1973 devm_kfree(chip->dev, policy);
1974 }
1975 break;
1976 default:
1977 err = -EOPNOTSUPP;
1978 break;
1979 }
1980
1981 mv88e6xxx_reg_unlock(chip);
1982
1983 return err;
1984}
1985
87fa886e
AL		 1986static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1987 u16 vid)
1988{
87fa886e 1989 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
0806dd46
TW		 1990 u8 broadcast[ETH_ALEN];
1991
1992 eth_broadcast_addr(broadcast);
87fa886e
AL		 1993
1994 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1995}
1996
1997static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1998{
1999 int port;
2000 int err;
2001
2002 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
8d1d8298
TW		 2003 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2004 struct net_device *brport;
2005
2006 if (dsa_is_unused_port(chip->ds, port))
2007 continue;
2008
2009 brport = dsa_port_to_bridge_port(dp);
2010 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2011 /* Skip bridged user ports where broadcast
2012 * flooding is disabled.
2013 */
2014 continue;
2015
87fa886e
AL		 2016 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2017 if (err)
2018 return err;
2019 }
2020
2021 return 0;
2022}
2023
8d1d8298
TW		 2024struct mv88e6xxx_port_broadcast_sync_ctx {
2025 int port;
2026 bool flood;
2027};
2028
2029static int
2030mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2031 const struct mv88e6xxx_vtu_entry *vlan,
2032 void *_ctx)
2033{
2034 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2035 u8 broadcast[ETH_ALEN];
2036 u8 state;
2037
2038 if (ctx->flood)
2039 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2040 else
2041 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2042
2043 eth_broadcast_addr(broadcast);
2044
2045 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2046 vlan->vid, state);
2047}
2048
2049static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2050 bool flood)
2051{
2052 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2053 .port = port,
2054 .flood = flood,
2055 };
2056 struct mv88e6xxx_vtu_entry vid0 = {
2057 .vid = 0,
2058 };
2059 int err;
2060
2061 /* Update the port's private database... */
2062 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2063 if (err)
2064 return err;
2065
2066 /* ...and the database for all VLANs. */
2067 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2068 &ctx);
2069}
2070
b1ac6fb4 2071static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
933b4425 2072 u16 vid, u8 member, bool warn)
0d3b33e6 2073{
b1ac6fb4 2074 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
b4e47c0f 2075 struct mv88e6xxx_vtu_entry vlan;
b1ac6fb4 2076 int i, err;
0d3b33e6 2077
34065c58 2078 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
87fa886e
AL		 2079 if (err)
2080 return err;
2081
34065c58 2082 if (!vlan.valid) {
b1ac6fb4
VD		 2083 memset(&vlan, 0, sizeof(vlan));
2084
2085 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2086 if (err)
2087 return err;
2088
2089 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2090 if (i == port)
2091 vlan.member[i] = member;
2092 else
2093 vlan.member[i] = non_member;
2094
2095 vlan.vid = vid;
2096 vlan.valid = true;
2097
2098 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2099 if (err)
2100 return err;
2101
2102 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2103 if (err)
2104 return err;
2105 } else if (vlan.member[port] != member) {
2106 vlan.member[port] = member;
2107
2108 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2109 if (err)
2110 return err;
933b4425 2111 } else if (warn) {
b1ac6fb4
VD		 2112 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2113 port, vid);
2114 }
2115
2116 return 0;
76e398a6
VD		 2117}
2118
1958d581 2119static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 2120 const struct switchdev_obj_port_vlan *vlan,
2121 struct netlink_ext_ack *extack)
76e398a6 2122{
04bed143 2123 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 2124 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2125 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
933b4425 2126 bool warn;
c91498e1 2127 u8 member;
1958d581 2128 int err;
76e398a6 2129
b8b79c41
EG		 2130 if (!vlan->vid)
2131 return 0;
2132
1958d581
VO		 2133 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2134 if (err)
2135 return err;
54d77b5b 2136
c91498e1 2137 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 2138 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 2139 else if (untagged)
7ec60d6e 2140 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 2141 else
7ec60d6e 2142 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 2143
933b4425
RK		 2144 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2145 * and then the CPU port. Do not warn for duplicates for the CPU port.
2146 */
2147 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2148
c9acece0 2149 mv88e6xxx_reg_lock(chip);
76e398a6 2150
1958d581
VO		 2151 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2152 if (err) {
b7a9e0da
VO		 2153 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2154 vlan->vid, untagged ? 'u' : 't');
1958d581
VO		 2155 goto out;
2156 }
76e398a6 2157
1958d581
VO		 2158 if (pvid) {
2159 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid);
2160 if (err) {
2161 dev_err(ds->dev, "p%d: failed to set PVID %d\n",
2162 port, vlan->vid);
2163 goto out;
2164 }
2165 }
2166out:
c9acece0 2167 mv88e6xxx_reg_unlock(chip);
1958d581
VO		 2168
2169 return err;
0d3b33e6
VD		 2170}
2171
52109892
VD		 2172static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2173 int port, u16 vid)
7dad08d7 2174{
b4e47c0f 2175 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 2176 int i, err;
2177
52109892 2178 if (!vid)
c92c7413 2179 return 0;
52109892 2180
34065c58 2181 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
7dad08d7 2182 if (err)
76e398a6 2183 return err;
7dad08d7 2184
52109892
VD		 2185 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2186 * tell switchdev that this VLAN is likely handled in software.
2187 */
34065c58 2188 if (!vlan.valid ||
52109892 2189 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2190 return -EOPNOTSUPP;
7dad08d7 2191
7ec60d6e 2192 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 2193
2194 /* keep the VLAN unless all ports are excluded */
f02bdffc 2195 vlan.valid = false;
370b4ffb 2196 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 2197 if (vlan.member[i] !=
2198 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2199 vlan.valid = true;
7dad08d7
VD		 2200 break;
2201 }
2202 }
2203
0ad5daf6 2204 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2205 if (err)
2206 return err;
2207
e606ca36 2208 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 2209}
2210
f81ec90f
VD		 2211static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2212 const struct switchdev_obj_port_vlan *vlan)
76e398a6 2213{
04bed143 2214 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6 2215 int err = 0;
b7a9e0da 2216 u16 pvid;
76e398a6 2217
e545f865 2218 if (!mv88e6xxx_max_vid(chip))
54d77b5b
VD		 2219 return -EOPNOTSUPP;
2220
c9acece0 2221 mv88e6xxx_reg_lock(chip);
76e398a6 2222
77064f37 2223 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 2224 if (err)
2225 goto unlock;
2226
b7a9e0da
VO		 2227 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2228 if (err)
2229 goto unlock;
2230
2231 if (vlan->vid == pvid) {
2232 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 2233 if (err)
2234 goto unlock;
76e398a6
VD		 2235 }
2236
7dad08d7 2237unlock:
c9acece0 2238 mv88e6xxx_reg_unlock(chip);
7dad08d7
VD		 2239
2240 return err;
2241}
2242
1b6dd556
AS		 2243static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2244 const unsigned char *addr, u16 vid)
87820510 2245{
04bed143 2246 struct mv88e6xxx_chip *chip = ds->priv;
1b6dd556 2247 int err;
87820510 2248
c9acece0 2249 mv88e6xxx_reg_lock(chip);
1b6dd556
AS		 2250 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2251 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
c9acece0 2252 mv88e6xxx_reg_unlock(chip);
1b6dd556
AS		 2253
2254 return err;
87820510
VD		 2255}
2256
f81ec90f 2257static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 2258 const unsigned char *addr, u16 vid)
87820510 2259{
04bed143 2260 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2261 int err;
87820510 2262
c9acece0 2263 mv88e6xxx_reg_lock(chip);
d8291a95 2264 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
c9acece0 2265 mv88e6xxx_reg_unlock(chip);
87820510 2266
83dabd1f 2267 return err;
87820510
VD		 2268}
2269
83dabd1f
VD		 2270static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2271 u16 fid, u16 vid, int port,
2bedde1a 2272 dsa_fdb_dump_cb_t *cb, void *data)
74b6ba0d 2273{
dabc1a96 2274 struct mv88e6xxx_atu_entry addr;
2bedde1a 2275 bool is_static;
74b6ba0d
VD		 2276 int err;
2277
d8291a95 2278 addr.state = 0;
dabc1a96 2279 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 2280
2281 do {
dabc1a96 2282 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 2283 if (err)
83dabd1f 2284 return err;
74b6ba0d 2285
d8291a95 2286 if (!addr.state)
74b6ba0d
VD		 2287 break;
2288
01bd96c8 2289 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 2290 continue;
2291
2bedde1a
AS		 2292 if (!is_unicast_ether_addr(addr.mac))
2293 continue;
83dabd1f 2294
2bedde1a
AS		 2295 is_static = (addr.state ==
2296 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2297 err = cb(addr.mac, vid, is_static, data);
83dabd1f
VD		 2298 if (err)
2299 return err;
74b6ba0d
VD		 2300 } while (!is_broadcast_ether_addr(addr.mac));
2301
2302 return err;
2303}
2304
d89ef4b8
TW		 2305struct mv88e6xxx_port_db_dump_vlan_ctx {
2306 int port;
2307 dsa_fdb_dump_cb_t *cb;
2308 void *data;
2309};
2310
2311static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2312 const struct mv88e6xxx_vtu_entry *entry,
2313 void *_data)
2314{
2315 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2316
2317 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2318 ctx->port, ctx->cb, ctx->data);
2319}
2320
83dabd1f 2321static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2bedde1a 2322 dsa_fdb_dump_cb_t *cb, void *data)
f33475bd 2323{
d89ef4b8
TW		 2324 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2325 .port = port,
2326 .cb = cb,
2327 .data = data,
2328 };
2db9ce1f 2329 u16 fid;
f33475bd
VD		 2330 int err;
2331
2db9ce1f 2332 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2333 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2334 if (err)
83dabd1f 2335 return err;
2db9ce1f 2336
2bedde1a 2337 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2db9ce1f 2338 if (err)
83dabd1f 2339 return err;
2db9ce1f 2340
d89ef4b8 2341 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
83dabd1f
VD		 2342}
2343
2344static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 2345 dsa_fdb_dump_cb_t *cb, void *data)
83dabd1f 2346{
04bed143 2347 struct mv88e6xxx_chip *chip = ds->priv;
fcf15367
VD		 2348 int err;
2349
c9acece0 2350 mv88e6xxx_reg_lock(chip);
fcf15367 2351 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
c9acece0 2352 mv88e6xxx_reg_unlock(chip);
83dabd1f 2353
fcf15367 2354 return err;
f33475bd
VD		 2355}
2356
240ea3ef
VD		 2357static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2358 struct net_device *br)
e79a8bcb 2359{
ef2025ec
VD		 2360 struct dsa_switch *ds = chip->ds;
2361 struct dsa_switch_tree *dst = ds->dst;
2362 struct dsa_port *dp;
240ea3ef 2363 int err;
466dfa07 2364
ef2025ec
VD		 2365 list_for_each_entry(dp, &dst->ports, list) {
2366 if (dp->bridge_dev == br) {
2367 if (dp->ds == ds) {
2368 /* This is a local bridge group member,
2369 * remap its Port VLAN Map.
2370 */
2371 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2372 if (err)
2373 return err;
2374 } else {
2375 /* This is an external bridge group member,
2376 * remap its cross-chip Port VLAN Table entry.
2377 */
2378 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2379 dp->index);
e96a6e02
VD		 2380 if (err)
2381 return err;
2382 }
2383 }
2384 }
2385
240ea3ef
VD		 2386 return 0;
2387}
2388
2389static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2390 struct net_device *br)
2391{
2392 struct mv88e6xxx_chip *chip = ds->priv;
2393 int err;
2394
c9acece0 2395 mv88e6xxx_reg_lock(chip);
240ea3ef 2396 err = mv88e6xxx_bridge_map(chip, br);
c9acece0 2397 mv88e6xxx_reg_unlock(chip);
a6692754 2398
466dfa07 2399 return err;
e79a8bcb
VD		 2400}
2401
f123f2fb
VD		 2402static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2403 struct net_device *br)
66d9cd0f 2404{
04bed143 2405 struct mv88e6xxx_chip *chip = ds->priv;
466dfa07 2406
c9acece0 2407 mv88e6xxx_reg_lock(chip);
240ea3ef
VD		 2408 if (mv88e6xxx_bridge_map(chip, br) ||
2409 mv88e6xxx_port_vlan_map(chip, port))
2410 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
c9acece0 2411 mv88e6xxx_reg_unlock(chip);
66d9cd0f
VD		 2412}
2413
f66a6a69
VO		 2414static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2415 int tree_index, int sw_index,
aec5ac88
VD		 2416 int port, struct net_device *br)
2417{
2418 struct mv88e6xxx_chip *chip = ds->priv;
2419 int err;
2420
f66a6a69
VO		 2421 if (tree_index != ds->dst->index)
2422 return 0;
2423
c9acece0 2424 mv88e6xxx_reg_lock(chip);
f66a6a69 2425 err = mv88e6xxx_pvt_map(chip, sw_index, port);
c9acece0 2426 mv88e6xxx_reg_unlock(chip);
aec5ac88
VD		 2427
2428 return err;
2429}
2430
f66a6a69
VO		 2431static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2432 int tree_index, int sw_index,
aec5ac88
VD		 2433 int port, struct net_device *br)
2434{
2435 struct mv88e6xxx_chip *chip = ds->priv;
2436
f66a6a69
VO		 2437 if (tree_index != ds->dst->index)
2438 return;
2439
c9acece0 2440 mv88e6xxx_reg_lock(chip);
f66a6a69 2441 if (mv88e6xxx_pvt_map(chip, sw_index, port))
aec5ac88 2442 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
c9acece0 2443 mv88e6xxx_reg_unlock(chip);
aec5ac88
VD		 2444}
2445
ce5df689
VO		 2446/* Treat the software bridge as a virtual single-port switch behind the
2447 * CPU and map in the PVT. First dst->last_switch elements are taken by
2448 * physical switches, so start from beyond that range.
2449 */
2450static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2451 int bridge_num)
2452{
2453 u8 dev = bridge_num + ds->dst->last_switch + 1;
2454 struct mv88e6xxx_chip *chip = ds->priv;
2455 int err;
2456
2457 mv88e6xxx_reg_lock(chip);
2458 err = mv88e6xxx_pvt_map(chip, dev, 0);
2459 mv88e6xxx_reg_unlock(chip);
2460
2461 return err;
2462}
2463
2464static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port,
2465 struct net_device *br,
2466 int bridge_num)
2467{
2468 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num);
2469}
2470
2471static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port,
2472 struct net_device *br,
2473 int bridge_num)
2474{
2475 int err;
2476
2477 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num);
2478 if (err) {
2479 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n",
2480 ERR_PTR(err));
2481 }
2482}
2483
17e708ba
VD		 2484static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2485{
2486 if (chip->info->ops->reset)
2487 return chip->info->ops->reset(chip);
2488
2489 return 0;
2490}
2491
309eca6d
VD		 2492static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2493{
2494 struct gpio_desc *gpiod = chip->reset;
2495
2496 /* If there is a GPIO connected to the reset pin, toggle it */
2497 if (gpiod) {
2498 gpiod_set_value_cansleep(gpiod, 1);
2499 usleep_range(10000, 20000);
2500 gpiod_set_value_cansleep(gpiod, 0);
2501 usleep_range(10000, 20000);
a3dcb3e7
AL		 2502
2503 mv88e6xxx_g1_wait_eeprom_done(chip);
309eca6d
VD		 2504 }
2505}
2506
4ac4b5a6 2507static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2508{
4ac4b5a6 2509 int i, err;
552238b5 2510
4ac4b5a6 2511 /* Set all ports to the Disabled state */
370b4ffb 2512 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 2513 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 2514 if (err)
2515 return err;
552238b5
VD		 2516 }
2517
4ac4b5a6
VD		 2518 /* Wait for transmit queues to drain,
2519 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2520 */
552238b5
VD		 2521 usleep_range(2000, 4000);
2522
4ac4b5a6
VD		 2523 return 0;
2524}
2525
2526static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2527{
4ac4b5a6
VD		 2528 int err;
2529
2530 err = mv88e6xxx_disable_ports(chip);
2531 if (err)
2532 return err;
2533
309eca6d 2534 mv88e6xxx_hardware_reset(chip);
552238b5 2535
17e708ba 2536 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2537}
2538
4314557c 2539static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 2540 enum mv88e6xxx_frame_mode frame,
2541 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 2542{
2543 int err;
2544
4314557c
VD		 2545 if (!chip->info->ops->port_set_frame_mode)
2546 return -EOPNOTSUPP;
2547
2548 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 2549 if (err)
2550 return err;
2551
4314557c
VD		 2552 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2553 if (err)
2554 return err;
2555
2556 if (chip->info->ops->port_set_ether_type)
2557 return chip->info->ops->port_set_ether_type(chip, port, etype);
2558
2559 return 0;
56995cbc
AL		 2560}
2561
4314557c 2562static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 2563{
4314557c 2564 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 2565 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 2566 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 2567}
56995cbc 2568
4314557c
VD		 2569static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2570{
2571 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 2572 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 2573 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 2574}
56995cbc 2575
4314557c
VD		 2576static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2577{
2578 return mv88e6xxx_set_port_mode(chip, port,
2579 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 2580 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2581 ETH_P_EDSA);
4314557c 2582}
56995cbc 2583
4314557c
VD		 2584static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2585{
2586 if (dsa_is_dsa_port(chip->ds, port))
2587 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2588
2b3e9891 2589 if (dsa_is_user_port(chip->ds, port))
4314557c 2590 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 2591
4314557c 2592 /* Setup CPU port mode depending on its supported tag format */
670bb80f 2593 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
4314557c 2594 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2595
670bb80f 2596 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
4314557c 2597 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 2598
4314557c 2599 return -EINVAL;
56995cbc
AL		 2600}
2601
601aeed3 2602static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 2603{
601aeed3 2604 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 2605
601aeed3 2606 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 2607}
56995cbc 2608
601aeed3 2609static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 2610{
a8b659e7 2611 int err;
56995cbc 2612
a8b659e7 2613 if (chip->info->ops->port_set_ucast_flood) {
7b9f16fe 2614 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
a8b659e7
VO		 2615 if (err)
2616 return err;
2617 }
2618 if (chip->info->ops->port_set_mcast_flood) {
7b9f16fe 2619 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
a8b659e7
VO		 2620 if (err)
2621 return err;
2622 }
ea698f4f 2623
407308f6 2624 return 0;
ea698f4f
VD		 2625}
2626
45de77ff
VD		 2627static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2628{
2629 struct mv88e6xxx_port *mvp = dev_id;
2630 struct mv88e6xxx_chip *chip = mvp->chip;
2631 irqreturn_t ret = IRQ_NONE;
2632 int port = mvp->port;
193c5b26 2633 int lane;
45de77ff
VD		 2634
2635 mv88e6xxx_reg_lock(chip);
2636 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 2637 if (lane >= 0)
45de77ff
VD		 2638 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2639 mv88e6xxx_reg_unlock(chip);
2640
2641 return ret;
2642}
2643
2644static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
193c5b26 2645 int lane)
45de77ff
VD		 2646{
2647 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2648 unsigned int irq;
2649 int err;
2650
2651 /* Nothing to request if this SERDES port has no IRQ */
2652 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2653 if (!irq)
2654 return 0;
2655
e6f2f6b8
AL		 2656 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2657 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2658
45de77ff
VD		 2659 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2660 mv88e6xxx_reg_unlock(chip);
2661 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
e6f2f6b8
AL		 2662 IRQF_ONESHOT, dev_id->serdes_irq_name,
2663 dev_id);
45de77ff
VD		 2664 mv88e6xxx_reg_lock(chip);
2665 if (err)
2666 return err;
2667
2668 dev_id->serdes_irq = irq;
2669
2670 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2671}
2672
2673static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
193c5b26 2674 int lane)
45de77ff
VD		 2675{
2676 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2677 unsigned int irq = dev_id->serdes_irq;
2678 int err;
2679
2680 /* Nothing to free if no IRQ has been requested */
2681 if (!irq)
2682 return 0;
2683
2684 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2685
2686 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2687 mv88e6xxx_reg_unlock(chip);
2688 free_irq(irq, dev_id);
2689 mv88e6xxx_reg_lock(chip);
2690
2691 dev_id->serdes_irq = 0;
2692
2693 return err;
2694}
2695
6d91782f
AL		 2696static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2697 bool on)
2698{
193c5b26 2699 int lane;
fc0bc019 2700 int err;
04aca993 2701
dc272f60 2702 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 2703 if (lane < 0)
fc0bc019
VD		 2704 return 0;
2705
2706 if (on) {
dc272f60 2707 err = mv88e6xxx_serdes_power_up(chip, port, lane);
fc0bc019
VD		 2708 if (err)
2709 return err;
2710
45de77ff 2711 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
fc0bc019 2712 } else {
45de77ff
VD		 2713 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2714 if (err)
2715 return err;
fc0bc019 2716
dc272f60 2717 err = mv88e6xxx_serdes_power_down(chip, port, lane);
fc0bc019
VD		 2718 }
2719
2720 return err;
6d91782f
AL		 2721}
2722
2fda45f0
MB		 2723static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2724 enum mv88e6xxx_egress_direction direction,
2725 int port)
2726{
2727 int err;
2728
2729 if (!chip->info->ops->set_egress_port)
2730 return -EOPNOTSUPP;
2731
2732 err = chip->info->ops->set_egress_port(chip, direction, port);
2733 if (err)
2734 return err;
2735
2736 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2737 chip->ingress_dest_port = port;
2738 else
2739 chip->egress_dest_port = port;
2740
2741 return 0;
2742}
2743
fa371c80
VD		 2744static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2745{
2746 struct dsa_switch *ds = chip->ds;
2747 int upstream_port;
2748 int err;
2749
07073c79 2750 upstream_port = dsa_upstream_port(ds, port);
fa371c80
VD		 2751 if (chip->info->ops->port_set_upstream_port) {
2752 err = chip->info->ops->port_set_upstream_port(chip, port,
2753 upstream_port);
2754 if (err)
2755 return err;
2756 }
2757
0ea54dda
VD		 2758 if (port == upstream_port) {
2759 if (chip->info->ops->set_cpu_port) {
2760 err = chip->info->ops->set_cpu_port(chip,
2761 upstream_port);
2762 if (err)
2763 return err;
2764 }
2765
2fda45f0 2766 err = mv88e6xxx_set_egress_port(chip,
5c74c54c
IT		 2767 MV88E6XXX_EGRESS_DIR_INGRESS,
2768 upstream_port);
2fda45f0
MB		 2769 if (err && err != -EOPNOTSUPP)
2770 return err;
5c74c54c 2771
2fda45f0 2772 err = mv88e6xxx_set_egress_port(chip,
5c74c54c
IT		 2773 MV88E6XXX_EGRESS_DIR_EGRESS,
2774 upstream_port);
2fda45f0
MB		 2775 if (err && err != -EOPNOTSUPP)
2776 return err;
0ea54dda
VD		 2777 }
2778
fa371c80
VD		 2779 return 0;
2780}
2781
fad09c73 2782static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2783{
fad09c73 2784 struct dsa_switch *ds = chip->ds;
0e7b9925 2785 int err;
54d792f2 2786 u16 reg;
d827e88a 2787
7b898469
AL		 2788 chip->ports[port].chip = chip;
2789 chip->ports[port].port = port;
2790
d78343d2
VD		 2791 /* MAC Forcing register: don't force link, speed, duplex or flow control
2792 * state to any particular values on physical ports, but force the CPU
2793 * port and all DSA ports to their maximum bandwidth and full duplex.
2794 */
2795 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2796 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2797 SPEED_MAX, DUPLEX_FULL,
54186b91 2798 PAUSE_OFF,
d78343d2
VD		 2799 PHY_INTERFACE_MODE_NA);
2800 else
2801 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2802 SPEED_UNFORCED, DUPLEX_UNFORCED,
54186b91 2803 PAUSE_ON,
d78343d2
VD		 2804 PHY_INTERFACE_MODE_NA);
2805 if (err)
2806 return err;
54d792f2
AL		 2807
2808 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2809 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2810 * tunneling, determine priority by looking at 802.1p and IP
2811 * priority fields (IP prio has precedence), and set STP state
2812 * to Forwarding.
2813 *
2814 * If this is the CPU link, use DSA or EDSA tagging depending
2815 * on which tagging mode was configured.
2816 *
2817 * If this is a link to another switch, use DSA tagging mode.
2818 *
2819 * If this is the upstream port for this switch, enable
2820 * forwarding of unknown unicasts and multicasts.
2821 */
a89b433b
VD		 2822 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2823 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2824 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2825 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 2826 if (err)
2827 return err;
6083ce71 2828
601aeed3 2829 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 2830 if (err)
2831 return err;
54d792f2 2832
601aeed3 2833 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 2834 if (err)
2835 return err;
2836
8efdda4a 2837 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2838 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2839 * untagged frames on this port, do a destination address lookup on all
2840 * received packets as usual, disable ARP mirroring and don't send a
2841 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2842 */
a23b2961
AL		 2843 err = mv88e6xxx_port_set_map_da(chip, port);
2844 if (err)
2845 return err;
8efdda4a 2846
fa371c80
VD		 2847 err = mv88e6xxx_setup_upstream_port(chip, port);
2848 if (err)
2849 return err;
54d792f2 2850
a23b2961 2851 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 2852 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 2853 if (err)
2854 return err;
2855
cd782656
VD		 2856 if (chip->info->ops->port_set_jumbo_size) {
2857 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
5f436666
AL		 2858 if (err)
2859 return err;
2860 }
2861
041bd545
TW		 2862 /* Port Association Vector: disable automatic address learning
2863 * on all user ports since they start out in standalone
2864 * mode. When joining a bridge, learning will be configured to
2865 * match the bridge port settings. Enable learning on all
2866 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2867 * learning process.
2868 *
2869 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2870 * and RefreshLocked. I.e. setup standard automatic learning.
54d792f2 2871 */
041bd545 2872 if (dsa_is_user_port(ds, port))
65fa4027 2873 reg = 0;
041bd545
TW		 2874 else
2875 reg = 1 << port;
4c7ea3c0 2876
2a4614e4
VD		 2877 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2878 reg);
0e7b9925
AL		 2879 if (err)
2880 return err;
54d792f2
AL		 2881
2882 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 2883 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2884 0x0000);
0e7b9925
AL		 2885 if (err)
2886 return err;
54d792f2 2887
0898432c
VD		 2888 if (chip->info->ops->port_pause_limit) {
2889 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 2890 if (err)
2891 return err;
b35d322a 2892 }
54d792f2 2893
c8c94891
VD		 2894 if (chip->info->ops->port_disable_learn_limit) {
2895 err = chip->info->ops->port_disable_learn_limit(chip, port);
2896 if (err)
2897 return err;
2898 }
2899
9dbfb4e1
VD		 2900 if (chip->info->ops->port_disable_pri_override) {
2901 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 2902 if (err)
2903 return err;
ef0a7318 2904 }
2bbb33be 2905
ef0a7318
AL		 2906 if (chip->info->ops->port_tag_remap) {
2907 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2908 if (err)
2909 return err;
54d792f2
AL		 2910 }
2911
ef70b111
AL		 2912 if (chip->info->ops->port_egress_rate_limiting) {
2913 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2914 if (err)
2915 return err;
54d792f2
AL		 2916 }
2917
121b8fe2
HF		 2918 if (chip->info->ops->port_setup_message_port) {
2919 err = chip->info->ops->port_setup_message_port(chip, port);
2920 if (err)
2921 return err;
2922 }
d827e88a 2923
207afda1 2924 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2925 * database, and allow bidirectional communication between the
2926 * CPU and DSA port(s), and the other ports.
d827e88a 2927 */
b4e48c50 2928 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2929 if (err)
2930 return err;
2db9ce1f 2931
240ea3ef 2932 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 2933 if (err)
2934 return err;
d827e88a
GR		 2935
2936 /* Default VLAN ID and priority: don't set a default VLAN
2937 * ID, and set the default packet priority to zero.
2938 */
b7929fb3 2939 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 2940}
2941
2a550aec
AL		 2942static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2943{
2944 struct mv88e6xxx_chip *chip = ds->priv;
2945
2946 if (chip->info->ops->port_set_jumbo_size)
2947 return 10240;
1baf0fac
CP		 2948 else if (chip->info->ops->set_max_frame_size)
2949 return 1632;
2a550aec
AL		 2950 return 1522;
2951}
2952
2953static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2954{
2955 struct mv88e6xxx_chip *chip = ds->priv;
2956 int ret = 0;
2957
2958 mv88e6xxx_reg_lock(chip);
2959 if (chip->info->ops->port_set_jumbo_size)
2960 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
1baf0fac
CP		 2961 else if (chip->info->ops->set_max_frame_size)
2962 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2a550aec
AL		 2963 else
2964 if (new_mtu > 1522)
2965 ret = -EINVAL;
2966 mv88e6xxx_reg_unlock(chip);
2967
2968 return ret;
2969}
2970
04aca993
AL		 2971static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2972 struct phy_device *phydev)
2973{
2974 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 2975 int err;
04aca993 2976
c9acece0 2977 mv88e6xxx_reg_lock(chip);
523a8904 2978 err = mv88e6xxx_serdes_power(chip, port, true);
c9acece0 2979 mv88e6xxx_reg_unlock(chip);
04aca993
AL		 2980
2981 return err;
2982}
2983
75104db0 2984static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
04aca993
AL		 2985{
2986 struct mv88e6xxx_chip *chip = ds->priv;
2987
c9acece0 2988 mv88e6xxx_reg_lock(chip);
523a8904
VD		 2989 if (mv88e6xxx_serdes_power(chip, port, false))
2990 dev_err(chip->dev, "failed to power off SERDES\n");
c9acece0 2991 mv88e6xxx_reg_unlock(chip);
04aca993
AL		 2992}
2993
2cfcd964
VD		 2994static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2995 unsigned int ageing_time)
2996{
04bed143 2997 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2998 int err;
2999
c9acece0 3000 mv88e6xxx_reg_lock(chip);
720c6343 3001 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
c9acece0 3002 mv88e6xxx_reg_unlock(chip);
2cfcd964
VD		 3003
3004 return err;
3005}
3006
447b1bb8 3007static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
acdaffcc 3008{
552238b5 3009 int err;
54d792f2 3010
de227387 3011 /* Initialize the statistics unit */
447b1bb8
VD		 3012 if (chip->info->ops->stats_set_histogram) {
3013 err = chip->info->ops->stats_set_histogram(chip);
3014 if (err)
3015 return err;
3016 }
de227387 3017
40cff8fc 3018 return mv88e6xxx_g1_stats_clear(chip);
9729934c
VD		 3019}
3020
ea89098e
AL		 3021/* Check if the errata has already been applied. */
3022static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3023{
3024 int port;
3025 int err;
3026 u16 val;
3027
3028 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
60907013 3029 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
ea89098e
AL		 3030 if (err) {
3031 dev_err(chip->dev,
3032 "Error reading hidden register: %d\n", err);
3033 return false;
3034 }
3035 if (val != 0x01c0)
3036 return false;
3037 }
3038
3039 return true;
3040}
3041
3042/* The 6390 copper ports have an errata which require poking magic
3043 * values into undocumented hidden registers and then performing a
3044 * software reset.
3045 */
3046static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3047{
3048 int port;
3049 int err;
3050
3051 if (mv88e6390_setup_errata_applied(chip))
3052 return 0;
3053
3054 /* Set the ports into blocking mode */
3055 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3056 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3057 if (err)
3058 return err;
3059 }
3060
3061 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
60907013 3062 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
ea89098e
AL		 3063 if (err)
3064 return err;
3065 }
3066
3067 return mv88e6xxx_software_reset(chip);
3068}
3069
23e8b470
AL		 3070static void mv88e6xxx_teardown(struct dsa_switch *ds)
3071{
3072 mv88e6xxx_teardown_devlink_params(ds);
e0c69ca7 3073 dsa_devlink_resources_unregister(ds);
fd292c18 3074 mv88e6xxx_teardown_devlink_regions_global(ds);
23e8b470
AL		 3075}
3076
f81ec90f 3077static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3078{
04bed143 3079 struct mv88e6xxx_chip *chip = ds->priv;
2d2e1dd2 3080 u8 cmode;
08a01261 3081 int err;
a1a6a4d1
VD		 3082 int i;
3083
fad09c73 3084 chip->ds = ds;
a3c53be5 3085 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 3086
ce5df689
VO		 3087 /* Since virtual bridges are mapped in the PVT, the number we support
3088 * depends on the physical switch topology. We need to let DSA figure
3089 * that out and therefore we cannot set this at dsa_register_switch()
3090 * time.
3091 */
3092 if (mv88e6xxx_has_pvt(chip))
3093 ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3094 ds->dst->last_switch - 1;
3095
c9acece0 3096 mv88e6xxx_reg_lock(chip);
08a01261 3097
ea89098e
AL		 3098 if (chip->info->ops->setup_errata) {
3099 err = chip->info->ops->setup_errata(chip);
3100 if (err)
3101 goto unlock;
3102 }
3103
2d2e1dd2
AL		 3104 /* Cache the cmode of each port. */
3105 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3106 if (chip->info->ops->port_get_cmode) {
3107 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3108 if (err)
e29129fc 3109 goto unlock;
2d2e1dd2
AL		 3110
3111 chip->ports[i].cmode = cmode;
3112 }
3113 }
3114
9729934c 3115 /* Setup Switch Port Registers */
370b4ffb 3116 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
b759f528
VD		 3117 if (dsa_is_unused_port(ds, i))
3118 continue;
3119
c857486a 3120 /* Prevent the use of an invalid port. */
b759f528 3121 if (mv88e6xxx_is_invalid_port(chip, i)) {
c857486a
HF		 3122 dev_err(chip->dev, "port %d is invalid\n", i);
3123 err = -EINVAL;
3124 goto unlock;
3125 }
3126
9729934c
VD		 3127 err = mv88e6xxx_setup_port(chip, i);
3128 if (err)
3129 goto unlock;
3130 }
3131
cd8da8bb
VD		 3132 err = mv88e6xxx_irl_setup(chip);
3133 if (err)
3134 goto unlock;
3135
04a69a17
VD		 3136 err = mv88e6xxx_mac_setup(chip);
3137 if (err)
3138 goto unlock;
3139
1b17aedf
VD		 3140 err = mv88e6xxx_phy_setup(chip);
3141 if (err)
3142 goto unlock;
3143
b486d7c9
VD		 3144 err = mv88e6xxx_vtu_setup(chip);
3145 if (err)
3146 goto unlock;
3147
81228996
VD		 3148 err = mv88e6xxx_pvt_setup(chip);
3149 if (err)
3150 goto unlock;
3151
a2ac29d2
VD		 3152 err = mv88e6xxx_atu_setup(chip);
3153 if (err)
3154 goto unlock;
3155
87fa886e
AL		 3156 err = mv88e6xxx_broadcast_setup(chip, 0);
3157 if (err)
3158 goto unlock;
3159
9e907d73
VD		 3160 err = mv88e6xxx_pot_setup(chip);
3161 if (err)
3162 goto unlock;
3163
9e5baf9b
VD		 3164 err = mv88e6xxx_rmu_setup(chip);
3165 if (err)
3166 goto unlock;
3167
51c901a7
VD		 3168 err = mv88e6xxx_rsvd2cpu_setup(chip);
3169 if (err)
3170 goto unlock;
6e55f698 3171
b28f872d
VD		 3172 err = mv88e6xxx_trunk_setup(chip);
3173 if (err)
3174 goto unlock;
3175
c7f047b6
VD		 3176 err = mv88e6xxx_devmap_setup(chip);
3177 if (err)
3178 goto unlock;
3179
93e18d61
VD		 3180 err = mv88e6xxx_pri_setup(chip);
3181 if (err)
3182 goto unlock;
3183
c6fe0ad2 3184 /* Setup PTP Hardware Clock and timestamping */
2fa8d3af
BS		 3185 if (chip->info->ptp_support) {
3186 err = mv88e6xxx_ptp_setup(chip);
3187 if (err)
3188 goto unlock;
c6fe0ad2
BS		 3189
3190 err = mv88e6xxx_hwtstamp_setup(chip);
3191 if (err)
3192 goto unlock;
2fa8d3af
BS		 3193 }
3194
447b1bb8
VD		 3195 err = mv88e6xxx_stats_setup(chip);
3196 if (err)
3197 goto unlock;
3198
6b17e864 3199unlock:
c9acece0 3200 mv88e6xxx_reg_unlock(chip);
db687a56 3201
e0c69ca7
AL		 3202 if (err)
3203 return err;
3204
3205 /* Have to be called without holding the register lock, since
3206 * they take the devlink lock, and we later take the locks in
3207 * the reverse order when getting/setting parameters or
3208 * resource occupancy.
23e8b470 3209 */
e0c69ca7
AL		 3210 err = mv88e6xxx_setup_devlink_resources(ds);
3211 if (err)
3212 return err;
3213
3214 err = mv88e6xxx_setup_devlink_params(ds);
3215 if (err)
bfb25542
AL		 3216 goto out_resources;
3217
fd292c18 3218 err = mv88e6xxx_setup_devlink_regions_global(ds);
bfb25542
AL		 3219 if (err)
3220 goto out_params;
3221
3222 return 0;
3223
3224out_params:
3225 mv88e6xxx_teardown_devlink_params(ds);
3226out_resources:
3227 dsa_devlink_resources_unregister(ds);
e0c69ca7
AL		 3228
3229 return err;
54d792f2
AL		 3230}
3231
fd292c18
VO		 3232static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3233{
3234 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3235}
3236
3237static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3238{
3239 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3240}
3241
1fe976d3
PR		 3242/* prod_id for switch families which do not have a PHY model number */
3243static const u16 family_prod_id_table[] = {
3244 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3245 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
c5d015b0 3246 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
1fe976d3
PR		 3247};
3248
e57e5e77 3249static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 3250{
0dd12d54
AL		 3251 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3252 struct mv88e6xxx_chip *chip = mdio_bus->chip;
1fe976d3 3253 u16 prod_id;
e57e5e77
VD		 3254 u16 val;
3255 int err;
fd3a0ee4 3256
ee26a228
AL		 3257 if (!chip->info->ops->phy_read)
3258 return -EOPNOTSUPP;
3259
c9acece0 3260 mv88e6xxx_reg_lock(chip);
ee26a228 3261 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
c9acece0 3262 mv88e6xxx_reg_unlock(chip);
e57e5e77 3263
1fe976d3
PR		 3264 /* Some internal PHYs don't have a model number. */
3265 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3266 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3267 prod_id = family_prod_id_table[chip->info->family];
3268 if (prod_id)
3269 val |= prod_id >> 4;
da9f3301
AL		 3270 }
3271
e57e5e77 3272 return err ? err : val;
fd3a0ee4
AL		 3273}
3274
e57e5e77 3275static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 3276{
0dd12d54
AL		 3277 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3278 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 3279 int err;
fd3a0ee4 3280
ee26a228
AL		 3281 if (!chip->info->ops->phy_write)
3282 return -EOPNOTSUPP;
3283
c9acece0 3284 mv88e6xxx_reg_lock(chip);
ee26a228 3285 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
c9acece0 3286 mv88e6xxx_reg_unlock(chip);
e57e5e77
VD		 3287
3288 return err;
fd3a0ee4
AL		 3289}
3290
fad09c73 3291static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 3292 struct device_node *np,
3293 bool external)
b516d453
AL		 3294{
3295 static int index;
0dd12d54 3296 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 3297 struct mii_bus *bus;
3298 int err;
3299
2510babc 3300 if (external) {
c9acece0 3301 mv88e6xxx_reg_lock(chip);
2510babc 3302 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
c9acece0 3303 mv88e6xxx_reg_unlock(chip);
2510babc
AL		 3304
3305 if (err)
3306 return err;
3307 }
3308
0dd12d54 3309 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 3310 if (!bus)
3311 return -ENOMEM;
3312
0dd12d54 3313 mdio_bus = bus->priv;
a3c53be5 3314 mdio_bus->bus = bus;
0dd12d54 3315 mdio_bus->chip = chip;
a3c53be5
AL		 3316 INIT_LIST_HEAD(&mdio_bus->list);
3317 mdio_bus->external = external;
0dd12d54 3318
b516d453
AL		 3319 if (np) {
3320 bus->name = np->full_name;
f7ce9103 3321 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
b516d453
AL		 3322 } else {
3323 bus->name = "mv88e6xxx SMI";
3324 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3325 }
3326
3327 bus->read = mv88e6xxx_mdio_read;
3328 bus->write = mv88e6xxx_mdio_write;
fad09c73 3329 bus->parent = chip->dev;
b516d453 3330
6f88284f
AL		 3331 if (!external) {
3332 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3333 if (err)
3334 return err;
3335 }
3336
00e798c7 3337 err = of_mdiobus_register(bus, np);
b516d453 3338 if (err) {
fad09c73 3339 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
6f88284f 3340 mv88e6xxx_g2_irq_mdio_free(chip, bus);
a3c53be5 3341 return err;
b516d453 3342 }
a3c53be5
AL		 3343
3344 if (external)
3345 list_add_tail(&mdio_bus->list, &chip->mdios);
3346 else
3347 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 3348
3349 return 0;
a3c53be5 3350}
b516d453 3351
3126aeec
AL		 3352static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3353
3354{
3355 struct mv88e6xxx_mdio_bus *mdio_bus;
3356 struct mii_bus *bus;
3357
3358 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3359 bus = mdio_bus->bus;
3360
6f88284f
AL		 3361 if (!mdio_bus->external)
3362 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3363
3126aeec
AL		 3364 mdiobus_unregister(bus);
3365 }
3366}
3367
a3c53be5
AL		 3368static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3369 struct device_node *np)
3370{
a3c53be5
AL		 3371 struct device_node *child;
3372 int err;
3373
3374 /* Always register one mdio bus for the internal/default mdio
3375 * bus. This maybe represented in the device tree, but is
3376 * optional.
3377 */
3378 child = of_get_child_by_name(np, "mdio");
3379 err = mv88e6xxx_mdio_register(chip, child, false);
3380 if (err)
3381 return err;
3382
3383 /* Walk the device tree, and see if there are any other nodes
3384 * which say they are compatible with the external mdio
3385 * bus.
3386 */
3387 for_each_available_child_of_node(np, child) {
ceb96fae
AL		 3388 if (of_device_is_compatible(
3389 child, "marvell,mv88e6xxx-mdio-external")) {
a3c53be5 3390 err = mv88e6xxx_mdio_register(chip, child, true);
3126aeec
AL		 3391 if (err) {
3392 mv88e6xxx_mdios_unregister(chip);
78e42040 3393 of_node_put(child);
a3c53be5 3394 return err;
3126aeec 3395 }
a3c53be5
AL		 3396 }
3397 }
3398
3399 return 0;
b516d453
AL		 3400}
3401
855b1932
VD		 3402static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3403{
04bed143 3404 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3405
3406 return chip->eeprom_len;
3407}
3408
855b1932
VD		 3409static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3410 struct ethtool_eeprom *eeprom, u8 *data)
3411{
04bed143 3412 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3413 int err;
3414
ee4dc2e7
VD		 3415 if (!chip->info->ops->get_eeprom)
3416 return -EOPNOTSUPP;
855b1932 3417
c9acece0 3418 mv88e6xxx_reg_lock(chip);
ee4dc2e7 3419 err = chip->info->ops->get_eeprom(chip, eeprom, data);
c9acece0 3420 mv88e6xxx_reg_unlock(chip);
855b1932
VD		 3421
3422 if (err)
3423 return err;
3424
3425 eeprom->magic = 0xc3ec4951;
3426
3427 return 0;
3428}
3429
855b1932
VD		 3430static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3431 struct ethtool_eeprom *eeprom, u8 *data)
3432{
04bed143 3433 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3434 int err;
3435
ee4dc2e7
VD		 3436 if (!chip->info->ops->set_eeprom)
3437 return -EOPNOTSUPP;
3438
855b1932
VD		 3439 if (eeprom->magic != 0xc3ec4951)
3440 return -EINVAL;
3441
c9acece0 3442 mv88e6xxx_reg_lock(chip);
ee4dc2e7 3443 err = chip->info->ops->set_eeprom(chip, eeprom, data);
c9acece0 3444 mv88e6xxx_reg_unlock(chip);
855b1932
VD		 3445
3446 return err;
3447}
3448
b3469dd8 3449static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3450 /* MV88E6XXX_FAMILY_6097 */
93e18d61
VD		 3451 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3452 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3453 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3454 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 3455 .phy_read = mv88e6185_phy_ppu_read,
3456 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 3457 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3458 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3459 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3460 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3461 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3462 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3463 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3464 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3465 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3466 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3467 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3468 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3469 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3470 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3471 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3472 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3473 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3474 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3475 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3476 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3477 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3478 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3479 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3480 .pot_clear = mv88e6xxx_g2_pot_clear,
a199d8b6
VD		 3481 .ppu_enable = mv88e6185_g1_ppu_enable,
3482 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3483 .reset = mv88e6185_g1_reset,
9e5baf9b 3484 .rmu_disable = mv88e6085_g1_rmu_disable,
f1394b78 3485 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3486 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3487 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3488 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 3489};
3490
3491static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3492 /* MV88E6XXX_FAMILY_6095 */
93e18d61
VD		 3493 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3494 .ip_pri_map = mv88e6085_g1_ip_pri_map,
b073d4e2 3495 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 3496 .phy_read = mv88e6185_phy_ppu_read,
3497 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 3498 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3499 .port_sync_link = mv88e6185_port_sync_link,
f365c6f7 3500 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
56995cbc 3501 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a8b659e7
VO		 3502 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3503 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
a23b2961 3504 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2d2e1dd2 3505 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3506 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3507 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3508 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3509 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3510 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3511 .stats_get_stats = mv88e6095_stats_get_stats,
51c901a7 3512 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
f5be107c
CP		 3513 .serdes_power = mv88e6185_serdes_power,
3514 .serdes_get_lane = mv88e6185_serdes_get_lane,
3515 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
a199d8b6
VD		 3516 .ppu_enable = mv88e6185_g1_ppu_enable,
3517 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3518 .reset = mv88e6185_g1_reset,
f1394b78 3519 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3520 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
6c422e34 3521 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3522 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 3523};
3524
7d381a02 3525static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3526 /* MV88E6XXX_FAMILY_6097 */
93e18d61
VD		 3527 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3528 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3529 .irl_init_all = mv88e6352_g2_irl_init_all,
7d381a02
SE		 3530 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3531 .phy_read = mv88e6xxx_g2_smi_phy_read,
3532 .phy_write = mv88e6xxx_g2_smi_phy_write,
3533 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3534 .port_sync_link = mv88e6185_port_sync_link,
f365c6f7 3535 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3536 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3537 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3538 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3539 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3540 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3541 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 3542 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3545 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3546 .port_setup_message_port = mv88e6xxx_setup_message_port,
7d381a02 3547 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3548 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
7d381a02
SE		 3549 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3550 .stats_get_strings = mv88e6095_stats_get_strings,
3551 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3552 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3553 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 3554 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3555 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
f5be107c
CP		 3556 .serdes_power = mv88e6185_serdes_power,
3557 .serdes_get_lane = mv88e6185_serdes_get_lane,
3558 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
5c19bc8b
CP		 3559 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3560 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3561 .serdes_irq_status = mv88e6097_serdes_irq_status,
9e907d73 3562 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3563 .reset = mv88e6352_g1_reset,
9e5baf9b 3564 .rmu_disable = mv88e6085_g1_rmu_disable,
f1394b78 3565 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3566 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3567 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3568 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
7d381a02
SE		 3569};
3570
b3469dd8 3571static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3572 /* MV88E6XXX_FAMILY_6165 */
93e18d61
VD		 3573 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3574 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3575 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3576 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 3577 .phy_read = mv88e6xxx_g2_smi_phy_read,
3578 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3579 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3580 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3581 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
56995cbc 3582 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a8b659e7
VO		 3583 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3584 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
c8c94891 3585 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3586 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3587 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3588 .port_setup_message_port = mv88e6xxx_setup_message_port,
0ac64c39 3589 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3590 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3591 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3592 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3593 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3594 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3595 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3596 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3597 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3598 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3599 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3600 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3601 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3602 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3603 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3604 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3605 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 3606};
3607
3608static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3609 /* MV88E6XXX_FAMILY_6185 */
93e18d61
VD		 3610 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3611 .ip_pri_map = mv88e6085_g1_ip_pri_map,
b073d4e2 3612 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 3613 .phy_read = mv88e6185_phy_ppu_read,
3614 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 3615 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3616 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3617 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3618 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3619 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3620 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3621 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
56995cbc 3622 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 3623 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 3624 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3625 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3626 .port_pause_limit = mv88e6097_port_pause_limit,
54186b91 3627 .port_set_pause = mv88e6185_port_set_pause,
2d2e1dd2 3628 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3629 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3630 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3631 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3632 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3633 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3634 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3635 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3636 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3637 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3638 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6 3639 .ppu_enable = mv88e6185_g1_ppu_enable,
02317e68 3640 .set_cascade_port = mv88e6185_g1_set_cascade_port,
a199d8b6 3641 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3642 .reset = mv88e6185_g1_reset,
f1394b78 3643 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3644 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
6c422e34 3645 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3646};
3647
990e27b0
VD		 3648static const struct mv88e6xxx_ops mv88e6141_ops = {
3649 /* MV88E6XXX_FAMILY_6341 */
93e18d61
VD		 3650 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3651 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3652 .irl_init_all = mv88e6352_g2_irl_init_all,
990e27b0
VD		 3653 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3654 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3655 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3656 .phy_read = mv88e6xxx_g2_smi_phy_read,
3657 .phy_write = mv88e6xxx_g2_smi_phy_write,
3658 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3659 .port_sync_link = mv88e6xxx_port_sync_link,
990e27b0 3660 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 3661 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
7cbbee05 3662 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
990e27b0 3663 .port_tag_remap = mv88e6095_port_tag_remap,
7da467d8 3664 .port_set_policy = mv88e6352_port_set_policy,
990e27b0 3665 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3666 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3667 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
990e27b0 3668 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3669 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 3670 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3671 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 3672 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3673 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3674 .port_get_cmode = mv88e6352_port_get_cmode,
7a3007d2 3675 .port_set_cmode = mv88e6341_port_set_cmode,
121b8fe2 3676 .port_setup_message_port = mv88e6xxx_setup_message_port,
990e27b0 3677 .stats_snapshot = mv88e6390_g1_stats_snapshot,
11527f3c 3678 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
990e27b0
VD		 3679 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3680 .stats_get_strings = mv88e6320_stats_get_strings,
3681 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3682 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3683 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 3684 .watchdog_ops = &mv88e6390_watchdog_ops,
3685 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3686 .pot_clear = mv88e6xxx_g2_pot_clear,
990e27b0 3687 .reset = mv88e6352_g1_reset,
37094887 3688 .rmu_disable = mv88e6390_g1_rmu_disable,
c07fff34
MB		 3689 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3690 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3691 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
d3cf7d8f
MB		 3693 .serdes_power = mv88e6390_serdes_power,
3694 .serdes_get_lane = mv88e6341_serdes_get_lane,
a5a6858b
RK		 3695 /* Check status register pause & lpa register */
3696 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3697 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3698 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3699 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 3700 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 3701 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 3702 .serdes_irq_status = mv88e6390_serdes_irq_status,
a73ccd61 3703 .gpio_ops = &mv88e6352_gpio_ops,
a03b98d6
MB		 3704 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3705 .serdes_get_strings = mv88e6390_serdes_get_strings,
3706 .serdes_get_stats = mv88e6390_serdes_get_stats,
953b0dcb
MB		 3707 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3708 .serdes_get_regs = mv88e6390_serdes_get_regs,
e3af71a3 3709 .phylink_validate = mv88e6341_phylink_validate,
990e27b0
VD		 3710};
3711
b3469dd8 3712static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3713 /* MV88E6XXX_FAMILY_6165 */
93e18d61
VD		 3714 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3715 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3716 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3717 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 3718 .phy_read = mv88e6xxx_g2_smi_phy_read,
3719 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3720 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3721 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3722 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3723 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3724 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3725 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3726 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3727 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3728 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3729 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3730 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3731 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3732 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3733 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3734 .port_setup_message_port = mv88e6xxx_setup_message_port,
a6da21bb 3735 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3736 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3737 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3738 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3739 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3740 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3741 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3742 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3743 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3744 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3745 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3746 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3747 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3748 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3749 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
a469a612 3750 .avb_ops = &mv88e6165_avb_ops,
dfa54348 3751 .ptp_ops = &mv88e6165_ptp_ops,
6c422e34 3752 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3753};
3754
3755static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3756 /* MV88E6XXX_FAMILY_6165 */
93e18d61
VD		 3757 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3758 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3759 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3760 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3761 .phy_read = mv88e6165_phy_read,
3762 .phy_write = mv88e6165_phy_write,
08ef7f10 3763 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3764 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3765 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
c8c94891 3766 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3767 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3768 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3769 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3770 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3771 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3772 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3773 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3774 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3775 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3776 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3777 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3778 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3779 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3780 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3781 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3782 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3783 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3784 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
a469a612 3785 .avb_ops = &mv88e6165_avb_ops,
dfa54348 3786 .ptp_ops = &mv88e6165_ptp_ops,
6c422e34 3787 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3788};
3789
3790static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3791 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 3792 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3793 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3794 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3795 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3796 .phy_read = mv88e6xxx_g2_smi_phy_read,
3797 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3798 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3799 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 3800 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 3801 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3802 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3803 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3804 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3805 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3806 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3807 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3808 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3809 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3810 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3811 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3812 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 3813 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3814 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3815 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3816 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3817 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3818 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3819 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3820 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3821 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3822 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3823 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3824 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3825 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3826 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3827 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3828 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3829 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3830};
3831
3832static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3833 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 3834 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3835 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3836 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3837 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3838 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3839 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3840 .phy_read = mv88e6xxx_g2_smi_phy_read,
3841 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3842 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3843 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 3844 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 3845 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 3846 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 3847 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 3848 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3849 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3850 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3851 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3852 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3853 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3854 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3855 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3857 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 3858 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3859 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3860 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3861 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3862 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3863 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3864 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3865 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3866 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3867 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3868 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3869 .reset = mv88e6352_g1_reset,
9e5baf9b 3870 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 3871 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3872 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3873 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3874 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 3875 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 3876 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3877 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3878 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3879 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 3880 .serdes_power = mv88e6352_serdes_power,
d3f88a24
AL		 3881 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3882 .serdes_get_regs = mv88e6352_serdes_get_regs,
a73ccd61 3883 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 3884 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 3885};
3886
3887static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3888 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 3889 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3890 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3891 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3892 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3893 .phy_read = mv88e6xxx_g2_smi_phy_read,
3894 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3895 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3896 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 3897 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 3898 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3899 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3900 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3901 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3902 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3903 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3904 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3905 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3906 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3907 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3908 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3909 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 3910 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3911 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3912 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3913 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3914 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3915 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3916 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3917 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3918 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3919 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3920 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3921 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3922 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3923 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3924 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3925 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3926 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3927};
3928
3929static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 3930 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 3931 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3932 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3933 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3934 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3935 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3936 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3937 .phy_read = mv88e6xxx_g2_smi_phy_read,
3938 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3939 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3940 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 3941 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 3942 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 3943 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 3944 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 3945 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3946 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3947 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3948 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3949 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3950 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3951 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3952 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3953 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3954 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 3955 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3956 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3957 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3958 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3959 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3960 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3961 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3962 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3963 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3964 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3965 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3966 .reset = mv88e6352_g1_reset,
9e5baf9b 3967 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 3968 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3969 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3970 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3971 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 3972 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 3973 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3974 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3975 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3976 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 3977 .serdes_power = mv88e6352_serdes_power,
4241ef52 3978 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
61a46b41 3979 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
907b9b9f 3980 .serdes_irq_status = mv88e6352_serdes_irq_status,
d3f88a24
AL		 3981 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3982 .serdes_get_regs = mv88e6352_serdes_get_regs,
a73ccd61 3983 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 3984 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 3985};
3986
3987static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 3988 /* MV88E6XXX_FAMILY_6185 */
93e18d61
VD		 3989 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3990 .ip_pri_map = mv88e6085_g1_ip_pri_map,
b073d4e2 3991 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 3992 .phy_read = mv88e6185_phy_ppu_read,
3993 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 3994 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3995 .port_sync_link = mv88e6185_port_sync_link,
f365c6f7 3996 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
56995cbc 3997 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a8b659e7
VO		 3998 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3999 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
ef70b111 4000 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 4001 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
54186b91 4002 .port_set_pause = mv88e6185_port_set_pause,
2d2e1dd2 4003 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 4004 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4005 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 4006 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4007 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4008 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4009 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4010 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4011 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4012 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4013 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
f5be107c
CP		 4014 .serdes_power = mv88e6185_serdes_power,
4015 .serdes_get_lane = mv88e6185_serdes_get_lane,
4016 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
02317e68 4017 .set_cascade_port = mv88e6185_g1_set_cascade_port,
a199d8b6
VD		 4018 .ppu_enable = mv88e6185_g1_ppu_enable,
4019 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 4020 .reset = mv88e6185_g1_reset,
f1394b78 4021 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 4022 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
6c422e34 4023 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 4024 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 4025};
4026
1a3b39ec 4027static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 4028 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4029 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4030 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4031 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4032 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4033 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4034 .phy_read = mv88e6xxx_g2_smi_phy_read,
4035 .phy_write = mv88e6xxx_g2_smi_phy_write,
4036 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4037 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4038 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4039 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4040 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4041 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4042 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4043 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4044 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4045 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4046 .port_set_ether_type = mv88e6351_port_set_ether_type,
e8b34c67 4047 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
0898432c 4048 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4049 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4050 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4051 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4052 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4053 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4054 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4055 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4056 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4057 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4058 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4059 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4060 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4061 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4062 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4063 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4064 .reset = mv88e6352_g1_reset,
9e5baf9b 4065 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4066 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4067 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4068 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4069 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4070 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4071 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4072 /* Check status register pause & lpa register */
4073 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4074 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4075 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4076 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4077 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4078 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4079 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4080 .serdes_get_strings = mv88e6390_serdes_get_strings,
4081 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4082 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4083 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4084 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 4085 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4086};
4087
4088static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 4089 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4090 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4091 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4092 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4093 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4094 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4095 .phy_read = mv88e6xxx_g2_smi_phy_read,
4096 .phy_write = mv88e6xxx_g2_smi_phy_write,
4097 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4098 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4099 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4100 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
7cbbee05 4101 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
ef0a7318 4102 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4103 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4104 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4105 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4106 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4107 .port_set_ether_type = mv88e6351_port_set_ether_type,
e8b34c67 4108 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
0898432c 4109 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4110 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4111 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4112 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4113 .port_set_cmode = mv88e6390x_port_set_cmode,
121b8fe2 4114 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4115 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4116 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4117 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4118 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4119 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4120 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4121 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4122 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4123 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4124 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4125 .reset = mv88e6352_g1_reset,
9e5baf9b 4126 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4127 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4128 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4129 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4130 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
d3cf7d8f 4131 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4132 .serdes_get_lane = mv88e6390x_serdes_get_lane,
a5a6858b
RK		 4133 /* Check status register pause & lpa register */
4134 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4135 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4136 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4137 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4138 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4139 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4140 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4141 .serdes_get_strings = mv88e6390_serdes_get_strings,
4142 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4143 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4144 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4145 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 4146 .phylink_validate = mv88e6390x_phylink_validate,
1a3b39ec
AL		 4147};
4148
4149static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 4150 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4151 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4152 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4153 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4154 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4155 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4156 .phy_read = mv88e6xxx_g2_smi_phy_read,
4157 .phy_write = mv88e6xxx_g2_smi_phy_write,
4158 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4159 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4160 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4161 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4162 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4163 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 4164 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4165 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4166 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4167 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 4168 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4169 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4170 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4171 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4172 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4173 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4174 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4175 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4176 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4177 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4178 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4179 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4180 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4181 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4182 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4183 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4184 .reset = mv88e6352_g1_reset,
9e5baf9b 4185 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4186 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4187 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4188 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4189 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4190 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4191 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4192 /* Check status register pause & lpa register */
4193 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4194 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4195 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4196 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4197 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4198 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4199 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4200 .serdes_get_strings = mv88e6390_serdes_get_strings,
4201 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4202 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4203 .serdes_get_regs = mv88e6390_serdes_get_regs,
6d2ac8ee
AL		 4204 .avb_ops = &mv88e6390_avb_ops,
4205 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4206 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4207};
4208
b3469dd8 4209static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 4210 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 4211 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4212 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4213 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4214 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4215 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4216 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4217 .phy_read = mv88e6xxx_g2_smi_phy_read,
4218 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4219 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4220 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 4221 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4222 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 4223 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 4224 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4225 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4226 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4227 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4228 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4229 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4230 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4231 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4232 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4233 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4234 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4235 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4236 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4237 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4238 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4239 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4240 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4241 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4242 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4243 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4244 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4245 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4246 .reset = mv88e6352_g1_reset,
9e5baf9b 4247 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 4248 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4249 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4250 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4251 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 4252 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 4253 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4254 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4255 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4256 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 4257 .serdes_power = mv88e6352_serdes_power,
4241ef52 4258 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
61a46b41 4259 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
907b9b9f 4260 .serdes_irq_status = mv88e6352_serdes_irq_status,
d3f88a24
AL		 4261 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4262 .serdes_get_regs = mv88e6352_serdes_get_regs,
a73ccd61 4263 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4264 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4265 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4266 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 4267};
4268
1f71836f
RV		 4269static const struct mv88e6xxx_ops mv88e6250_ops = {
4270 /* MV88E6XXX_FAMILY_6250 */
4271 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4272 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4273 .irl_init_all = mv88e6352_g2_irl_init_all,
4274 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4275 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4276 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4277 .phy_read = mv88e6xxx_g2_smi_phy_read,
4278 .phy_write = mv88e6xxx_g2_smi_phy_write,
4279 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4280 .port_sync_link = mv88e6xxx_port_sync_link,
1f71836f 4281 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4282 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
1f71836f
RV		 4283 .port_tag_remap = mv88e6095_port_tag_remap,
4284 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4285 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4286 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
1f71836f
RV		 4287 .port_set_ether_type = mv88e6351_port_set_ether_type,
4288 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4289 .port_pause_limit = mv88e6097_port_pause_limit,
4290 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
1f71836f
RV		 4291 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4292 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4293 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4294 .stats_get_strings = mv88e6250_stats_get_strings,
4295 .stats_get_stats = mv88e6250_stats_get_stats,
4296 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4297 .set_egress_port = mv88e6095_g1_set_egress_port,
4298 .watchdog_ops = &mv88e6250_watchdog_ops,
4299 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4300 .pot_clear = mv88e6xxx_g2_pot_clear,
4301 .reset = mv88e6250_g1_reset,
67c9ed1c 4302 .vtu_getnext = mv88e6185_g1_vtu_getnext,
b28f3f3c 4303 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
71509614
HF		 4304 .avb_ops = &mv88e6352_avb_ops,
4305 .ptp_ops = &mv88e6250_ptp_ops,
1f71836f
RV		 4306 .phylink_validate = mv88e6065_phylink_validate,
4307};
4308
1a3b39ec 4309static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 4310 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4311 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4312 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4313 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4314 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4315 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4316 .phy_read = mv88e6xxx_g2_smi_phy_read,
4317 .phy_write = mv88e6xxx_g2_smi_phy_write,
4318 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4319 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4320 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4321 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4322 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4323 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4324 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4325 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4326 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4327 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4328 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 4329 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4330 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4331 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4332 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4333 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4334 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4335 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4336 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4337 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4338 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4339 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4340 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4341 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4342 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4343 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4344 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4345 .reset = mv88e6352_g1_reset,
9e5baf9b 4346 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4347 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4348 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4349 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4350 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4351 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4352 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4353 /* Check status register pause & lpa register */
4354 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4355 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4356 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4357 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4358 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4359 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4360 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4361 .serdes_get_strings = mv88e6390_serdes_get_strings,
4362 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4363 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4364 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4365 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4366 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4367 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4368 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4369};
4370
b3469dd8 4371static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 4372 /* MV88E6XXX_FAMILY_6320 */
93e18d61
VD		 4373 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4374 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4375 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4376 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4377 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4378 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4379 .phy_read = mv88e6xxx_g2_smi_phy_read,
4380 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4381 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4382 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 4383 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4384 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4385 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4386 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4387 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4388 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4389 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4390 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4391 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4392 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4393 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4394 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4395 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4396 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4397 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4398 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4399 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 4400 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 4401 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4402 .set_egress_port = mv88e6095_g1_set_egress_port,
9c7f37e5 4403 .watchdog_ops = &mv88e6390_watchdog_ops,
51c901a7 4404 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4405 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4406 .reset = mv88e6352_g1_reset,
f1394b78 4407 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 4408 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
a73ccd61 4409 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4410 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4411 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4412 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4413};
4414
4415static const struct mv88e6xxx_ops mv88e6321_ops = {
bd807204 4416 /* MV88E6XXX_FAMILY_6320 */
93e18d61
VD		 4417 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4418 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4419 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4420 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4421 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4423 .phy_read = mv88e6xxx_g2_smi_phy_read,
4424 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4425 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4426 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 4427 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4428 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4429 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4430 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4431 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4432 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4433 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4434 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4435 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4436 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4437 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4438 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4439 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4440 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4441 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4442 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4443 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 4444 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 4445 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4446 .set_egress_port = mv88e6095_g1_set_egress_port,
9c7f37e5 4447 .watchdog_ops = &mv88e6390_watchdog_ops,
17e708ba 4448 .reset = mv88e6352_g1_reset,
f1394b78 4449 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 4450 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
a73ccd61 4451 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4452 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4453 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4454 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4455};
4456
16e329ae
VD		 4457static const struct mv88e6xxx_ops mv88e6341_ops = {
4458 /* MV88E6XXX_FAMILY_6341 */
93e18d61
VD		 4459 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4460 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4461 .irl_init_all = mv88e6352_g2_irl_init_all,
16e329ae
VD		 4462 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4463 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4464 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4465 .phy_read = mv88e6xxx_g2_smi_phy_read,
4466 .phy_write = mv88e6xxx_g2_smi_phy_write,
4467 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4468 .port_sync_link = mv88e6xxx_port_sync_link,
16e329ae 4469 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4470 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
7cbbee05 4471 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
16e329ae 4472 .port_tag_remap = mv88e6095_port_tag_remap,
7da467d8 4473 .port_set_policy = mv88e6352_port_set_policy,
16e329ae 4474 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4475 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4476 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
16e329ae 4477 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4478 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 4479 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4480 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 4481 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4482 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4483 .port_get_cmode = mv88e6352_port_get_cmode,
7a3007d2 4484 .port_set_cmode = mv88e6341_port_set_cmode,
121b8fe2 4485 .port_setup_message_port = mv88e6xxx_setup_message_port,
16e329ae 4486 .stats_snapshot = mv88e6390_g1_stats_snapshot,
11527f3c 4487 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
16e329ae
VD		 4488 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4489 .stats_get_strings = mv88e6320_stats_get_strings,
4490 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4491 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4492 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 4493 .watchdog_ops = &mv88e6390_watchdog_ops,
4494 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4495 .pot_clear = mv88e6xxx_g2_pot_clear,
16e329ae 4496 .reset = mv88e6352_g1_reset,
37094887 4497 .rmu_disable = mv88e6390_g1_rmu_disable,
c07fff34
MB		 4498 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4499 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4500 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4501 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
d3cf7d8f
MB		 4502 .serdes_power = mv88e6390_serdes_power,
4503 .serdes_get_lane = mv88e6341_serdes_get_lane,
a5a6858b
RK		 4504 /* Check status register pause & lpa register */
4505 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4506 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4507 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4508 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4509 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4510 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4511 .serdes_irq_status = mv88e6390_serdes_irq_status,
a73ccd61 4512 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4513 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4514 .ptp_ops = &mv88e6352_ptp_ops,
a03b98d6
MB		 4515 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4516 .serdes_get_strings = mv88e6390_serdes_get_strings,
4517 .serdes_get_stats = mv88e6390_serdes_get_stats,
953b0dcb
MB		 4518 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4519 .serdes_get_regs = mv88e6390_serdes_get_regs,
e3af71a3 4520 .phylink_validate = mv88e6341_phylink_validate,
16e329ae
VD		 4521};
4522
b3469dd8 4523static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 4524 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 4525 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4526 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4527 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 4528 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4529 .phy_read = mv88e6xxx_g2_smi_phy_read,
4530 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4531 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4532 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 4533 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4534 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4535 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4536 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4537 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4538 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4539 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4540 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4541 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4542 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4545 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4546 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4547 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4548 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4549 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4550 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4551 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4552 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4553 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4554 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4555 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4556 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4557 .reset = mv88e6352_g1_reset,
23e8b470
AL		 4558 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4559 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4560 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4561 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 4562 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4563};
4564
4565static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 4566 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 4567 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4568 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4569 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 4570 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4571 .phy_read = mv88e6xxx_g2_smi_phy_read,
4572 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4573 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4574 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 4575 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4576 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4577 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4578 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4579 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4580 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4581 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4582 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4583 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4584 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4585 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4586 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4587 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4588 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4589 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4590 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4591 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4592 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4593 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4594 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4595 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4596 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4597 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4598 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4599 .reset = mv88e6352_g1_reset,
23e8b470
AL		 4600 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4601 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4602 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4603 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
0d632c3d 4604 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4605 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4606 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4607};
4608
4609static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 4610 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 4611 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4612 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4613 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4614 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4615 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4616 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4617 .phy_read = mv88e6xxx_g2_smi_phy_read,
4618 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4619 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4620 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 4621 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4622 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 4623 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 4624 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4625 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4626 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4627 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4628 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4629 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4630 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4631 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4632 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4633 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4634 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4635 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4636 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4637 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4638 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4639 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4640 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4641 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4642 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4643 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4644 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4645 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4646 .reset = mv88e6352_g1_reset,
9e5baf9b 4647 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 4648 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4649 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4650 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4651 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 4652 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 4653 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4654 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4655 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4656 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 4657 .serdes_power = mv88e6352_serdes_power,
4241ef52 4658 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
61a46b41 4659 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
907b9b9f 4660 .serdes_irq_status = mv88e6352_serdes_irq_status,
a73ccd61 4661 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4662 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4663 .ptp_ops = &mv88e6352_ptp_ops,
cda9f4aa
AL		 4664 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4665 .serdes_get_strings = mv88e6352_serdes_get_strings,
4666 .serdes_get_stats = mv88e6352_serdes_get_stats,
d3f88a24
AL		 4667 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4668 .serdes_get_regs = mv88e6352_serdes_get_regs,
6c422e34 4669 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 4670};
4671
1a3b39ec 4672static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 4673 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4674 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4675 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4676 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4677 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4678 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4679 .phy_read = mv88e6xxx_g2_smi_phy_read,
4680 .phy_write = mv88e6xxx_g2_smi_phy_write,
4681 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4682 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4683 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4684 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4685 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4686 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4687 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4688 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4689 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4690 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4691 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4692 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4693 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4694 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4695 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4696 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4697 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4698 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4699 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4700 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4701 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4702 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4703 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4704 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4705 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4706 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4707 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4708 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4709 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4710 .reset = mv88e6352_g1_reset,
9e5baf9b 4711 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4712 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4713 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4714 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4715 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4716 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4717 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4718 /* Check status register pause & lpa register */
4719 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4720 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4721 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4722 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4723 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4724 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4725 .serdes_irq_status = mv88e6390_serdes_irq_status,
a73ccd61 4726 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4727 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4728 .ptp_ops = &mv88e6352_ptp_ops,
0df95287
NY		 4729 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4730 .serdes_get_strings = mv88e6390_serdes_get_strings,
4731 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4732 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4733 .serdes_get_regs = mv88e6390_serdes_get_regs,
6c422e34 4734 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4735};
4736
4737static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 4738 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4739 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4740 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4741 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4742 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4743 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4744 .phy_read = mv88e6xxx_g2_smi_phy_read,
4745 .phy_write = mv88e6xxx_g2_smi_phy_write,
4746 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4747 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4748 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4749 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
7cbbee05 4750 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
ef0a7318 4751 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4752 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4753 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4754 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4755 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4756 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4757 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4758 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4759 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4760 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4761 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4762 .port_get_cmode = mv88e6352_port_get_cmode,
b3dce4da 4763 .port_set_cmode = mv88e6390x_port_set_cmode,
121b8fe2 4764 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4765 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4766 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4767 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4768 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4769 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4770 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4771 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4772 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4773 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4774 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4775 .reset = mv88e6352_g1_reset,
9e5baf9b 4776 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4777 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4778 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4779 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4780 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
d3cf7d8f 4781 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4782 .serdes_get_lane = mv88e6390x_serdes_get_lane,
a5a6858b
RK		 4783 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4784 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4785 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4786 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4787 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4788 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4789 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4790 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4791 .serdes_get_strings = mv88e6390_serdes_get_strings,
4792 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4793 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4794 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4795 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4796 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4797 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4798 .phylink_validate = mv88e6390x_phylink_validate,
1a3b39ec
AL		 4799};
4800
de776d0d
PS		 4801static const struct mv88e6xxx_ops mv88e6393x_ops = {
4802 /* MV88E6XXX_FAMILY_6393 */
4803 .setup_errata = mv88e6393x_serdes_setup_errata,
4804 .irl_init_all = mv88e6390_g2_irl_init_all,
4805 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4806 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4807 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4808 .phy_read = mv88e6xxx_g2_smi_phy_read,
4809 .phy_write = mv88e6xxx_g2_smi_phy_write,
4810 .port_set_link = mv88e6xxx_port_set_link,
4811 .port_sync_link = mv88e6xxx_port_sync_link,
4812 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4813 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4814 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4815 .port_tag_remap = mv88e6390_port_tag_remap,
6584b260 4816 .port_set_policy = mv88e6393x_port_set_policy,
de776d0d
PS		 4817 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4818 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4819 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4820 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4821 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4822 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4823 .port_pause_limit = mv88e6390_port_pause_limit,
4824 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4825 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4826 .port_get_cmode = mv88e6352_port_get_cmode,
4827 .port_set_cmode = mv88e6393x_port_set_cmode,
4828 .port_setup_message_port = mv88e6xxx_setup_message_port,
4829 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4830 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4831 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4832 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4833 .stats_get_strings = mv88e6320_stats_get_strings,
4834 .stats_get_stats = mv88e6390_stats_get_stats,
4835 /* .set_cpu_port is missing because this family does not support a global
4836 * CPU port, only per port CPU port which is set via
4837 * .port_set_upstream_port method.
4838 */
4839 .set_egress_port = mv88e6393x_set_egress_port,
4840 .watchdog_ops = &mv88e6390_watchdog_ops,
4841 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4842 .pot_clear = mv88e6xxx_g2_pot_clear,
4843 .reset = mv88e6352_g1_reset,
4844 .rmu_disable = mv88e6390_g1_rmu_disable,
4845 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4846 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4847 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4848 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4849 .serdes_power = mv88e6393x_serdes_power,
4850 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4851 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4852 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4853 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4854 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4855 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4856 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4857 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4858 /* TODO: serdes stats */
4859 .gpio_ops = &mv88e6352_gpio_ops,
4860 .avb_ops = &mv88e6390_avb_ops,
4861 .ptp_ops = &mv88e6352_ptp_ops,
4862 .phylink_validate = mv88e6393x_phylink_validate,
4863};
4864
f81ec90f
VD		 4865static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4866 [MV88E6085] = {
107fcc10 4867 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 4868 .family = MV88E6XXX_FAMILY_6097,
4869 .name = "Marvell 88E6085",
4870 .num_databases = 4096,
d9ea5620 4871 .num_macs = 8192,
f81ec90f 4872 .num_ports = 10,
bc393155 4873 .num_internal_phys = 5,
3cf3c846 4874 .max_vid = 4095,
9dddd478 4875 .port_base_addr = 0x10,
9255bacd 4876 .phy_base_addr = 0x0,
a935c052 4877 .global1_addr = 0x1b,
9069c13a 4878 .global2_addr = 0x1c,
acddbd21 4879 .age_time_coeff = 15000,
dc30c35b 4880 .g1_irqs = 8,
d6c5e6af 4881 .g2_irqs = 10,
e606ca36 4882 .atu_move_port_mask = 0xf,
f3645652 4883 .pvt = true,
b3e05aa1 4884 .multi_chip = true,
b3469dd8 4885 .ops = &mv88e6085_ops,
f81ec90f
VD		 4886 },
4887
4888 [MV88E6095] = {
107fcc10 4889 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 4890 .family = MV88E6XXX_FAMILY_6095,
4891 .name = "Marvell 88E6095/88E6095F",
4892 .num_databases = 256,
d9ea5620 4893 .num_macs = 8192,
f81ec90f 4894 .num_ports = 11,
bc393155 4895 .num_internal_phys = 0,
3cf3c846 4896 .max_vid = 4095,
9dddd478 4897 .port_base_addr = 0x10,
9255bacd 4898 .phy_base_addr = 0x0,
a935c052 4899 .global1_addr = 0x1b,
9069c13a 4900 .global2_addr = 0x1c,
acddbd21 4901 .age_time_coeff = 15000,
dc30c35b 4902 .g1_irqs = 8,
e606ca36 4903 .atu_move_port_mask = 0xf,
b3e05aa1 4904 .multi_chip = true,
b3469dd8 4905 .ops = &mv88e6095_ops,
f81ec90f
VD		 4906 },
4907
7d381a02 4908 [MV88E6097] = {
107fcc10 4909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 4910 .family = MV88E6XXX_FAMILY_6097,
4911 .name = "Marvell 88E6097/88E6097F",
4912 .num_databases = 4096,
d9ea5620 4913 .num_macs = 8192,
7d381a02 4914 .num_ports = 11,
bc393155 4915 .num_internal_phys = 8,
3cf3c846 4916 .max_vid = 4095,
7d381a02 4917 .port_base_addr = 0x10,
9255bacd 4918 .phy_base_addr = 0x0,
7d381a02 4919 .global1_addr = 0x1b,
9069c13a 4920 .global2_addr = 0x1c,
7d381a02 4921 .age_time_coeff = 15000,
c534178b 4922 .g1_irqs = 8,
d6c5e6af 4923 .g2_irqs = 10,
e606ca36 4924 .atu_move_port_mask = 0xf,
f3645652 4925 .pvt = true,
b3e05aa1 4926 .multi_chip = true,
670bb80f 4927 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
7d381a02
SE		 4928 .ops = &mv88e6097_ops,
4929 },
4930
f81ec90f 4931 [MV88E6123] = {
107fcc10 4932 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 4933 .family = MV88E6XXX_FAMILY_6165,
4934 .name = "Marvell 88E6123",
4935 .num_databases = 4096,
d9ea5620 4936 .num_macs = 1024,
f81ec90f 4937 .num_ports = 3,
bc393155 4938 .num_internal_phys = 5,
3cf3c846 4939 .max_vid = 4095,
9dddd478 4940 .port_base_addr = 0x10,
9255bacd 4941 .phy_base_addr = 0x0,
a935c052 4942 .global1_addr = 0x1b,
9069c13a 4943 .global2_addr = 0x1c,
acddbd21 4944 .age_time_coeff = 15000,
dc30c35b 4945 .g1_irqs = 9,
d6c5e6af 4946 .g2_irqs = 10,
e606ca36 4947 .atu_move_port_mask = 0xf,
f3645652 4948 .pvt = true,
b3e05aa1 4949 .multi_chip = true,
670bb80f 4950 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 4951 .ops = &mv88e6123_ops,
f81ec90f
VD		 4952 },
4953
4954 [MV88E6131] = {
107fcc10 4955 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 4956 .family = MV88E6XXX_FAMILY_6185,
4957 .name = "Marvell 88E6131",
4958 .num_databases = 256,
d9ea5620 4959 .num_macs = 8192,
f81ec90f 4960 .num_ports = 8,
bc393155 4961 .num_internal_phys = 0,
3cf3c846 4962 .max_vid = 4095,
9dddd478 4963 .port_base_addr = 0x10,
9255bacd 4964 .phy_base_addr = 0x0,
a935c052 4965 .global1_addr = 0x1b,
9069c13a 4966 .global2_addr = 0x1c,
acddbd21 4967 .age_time_coeff = 15000,
dc30c35b 4968 .g1_irqs = 9,
e606ca36 4969 .atu_move_port_mask = 0xf,
b3e05aa1 4970 .multi_chip = true,
b3469dd8 4971 .ops = &mv88e6131_ops,
f81ec90f
VD		 4972 },
4973
990e27b0 4974 [MV88E6141] = {
107fcc10 4975 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0 4976 .family = MV88E6XXX_FAMILY_6341,
79a68b26 4977 .name = "Marvell 88E6141",
990e27b0 4978 .num_databases = 4096,
d9ea5620 4979 .num_macs = 2048,
990e27b0 4980 .num_ports = 6,
bc393155 4981 .num_internal_phys = 5,
a73ccd61 4982 .num_gpio = 11,
3cf3c846 4983 .max_vid = 4095,
990e27b0 4984 .port_base_addr = 0x10,
9255bacd 4985 .phy_base_addr = 0x10,
990e27b0 4986 .global1_addr = 0x1b,
9069c13a 4987 .global2_addr = 0x1c,
990e27b0
VD		 4988 .age_time_coeff = 3750,
4989 .atu_move_port_mask = 0x1f,
adfccf11 4990 .g1_irqs = 9,
d6c5e6af 4991 .g2_irqs = 10,
f3645652 4992 .pvt = true,
b3e05aa1 4993 .multi_chip = true,
670bb80f 4994 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
990e27b0
VD		 4995 .ops = &mv88e6141_ops,
4996 },
4997
f81ec90f 4998 [MV88E6161] = {
107fcc10 4999 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 5000 .family = MV88E6XXX_FAMILY_6165,
5001 .name = "Marvell 88E6161",
5002 .num_databases = 4096,
d9ea5620 5003 .num_macs = 1024,
f81ec90f 5004 .num_ports = 6,
bc393155 5005 .num_internal_phys = 5,
3cf3c846 5006 .max_vid = 4095,
9dddd478 5007 .port_base_addr = 0x10,
9255bacd 5008 .phy_base_addr = 0x0,
a935c052 5009 .global1_addr = 0x1b,
9069c13a 5010 .global2_addr = 0x1c,
acddbd21 5011 .age_time_coeff = 15000,
dc30c35b 5012 .g1_irqs = 9,
d6c5e6af 5013 .g2_irqs = 10,
e606ca36 5014 .atu_move_port_mask = 0xf,
f3645652 5015 .pvt = true,
b3e05aa1 5016 .multi_chip = true,
670bb80f 5017 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
dfa54348 5018 .ptp_support = true,
b3469dd8 5019 .ops = &mv88e6161_ops,
f81ec90f
VD		 5020 },
5021
5022 [MV88E6165] = {
107fcc10 5023 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 5024 .family = MV88E6XXX_FAMILY_6165,
5025 .name = "Marvell 88E6165",
5026 .num_databases = 4096,
d9ea5620 5027 .num_macs = 8192,
f81ec90f 5028 .num_ports = 6,
bc393155 5029 .num_internal_phys = 0,
3cf3c846 5030 .max_vid = 4095,
9dddd478 5031 .port_base_addr = 0x10,
9255bacd 5032 .phy_base_addr = 0x0,
a935c052 5033 .global1_addr = 0x1b,
9069c13a 5034 .global2_addr = 0x1c,
acddbd21 5035 .age_time_coeff = 15000,
dc30c35b 5036 .g1_irqs = 9,
d6c5e6af 5037 .g2_irqs = 10,
e606ca36 5038 .atu_move_port_mask = 0xf,
f3645652 5039 .pvt = true,
b3e05aa1 5040 .multi_chip = true,
dfa54348 5041 .ptp_support = true,
b3469dd8 5042 .ops = &mv88e6165_ops,
f81ec90f
VD		 5043 },
5044
5045 [MV88E6171] = {
107fcc10 5046 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 5047 .family = MV88E6XXX_FAMILY_6351,
5048 .name = "Marvell 88E6171",
5049 .num_databases = 4096,
d9ea5620 5050 .num_macs = 8192,
f81ec90f 5051 .num_ports = 7,
bc393155 5052 .num_internal_phys = 5,
3cf3c846 5053 .max_vid = 4095,
9dddd478 5054 .port_base_addr = 0x10,
9255bacd 5055 .phy_base_addr = 0x0,
a935c052 5056 .global1_addr = 0x1b,
9069c13a 5057 .global2_addr = 0x1c,
acddbd21 5058 .age_time_coeff = 15000,
dc30c35b 5059 .g1_irqs = 9,
d6c5e6af 5060 .g2_irqs = 10,
e606ca36 5061 .atu_move_port_mask = 0xf,
f3645652 5062 .pvt = true,
b3e05aa1 5063 .multi_chip = true,
670bb80f 5064 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5065 .ops = &mv88e6171_ops,
f81ec90f
VD		 5066 },
5067
5068 [MV88E6172] = {
107fcc10 5069 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 5070 .family = MV88E6XXX_FAMILY_6352,
5071 .name = "Marvell 88E6172",
5072 .num_databases = 4096,
d9ea5620 5073 .num_macs = 8192,
f81ec90f 5074 .num_ports = 7,
bc393155 5075 .num_internal_phys = 5,
a73ccd61 5076 .num_gpio = 15,
3cf3c846 5077 .max_vid = 4095,
9dddd478 5078 .port_base_addr = 0x10,
9255bacd 5079 .phy_base_addr = 0x0,
a935c052 5080 .global1_addr = 0x1b,
9069c13a 5081 .global2_addr = 0x1c,
acddbd21 5082 .age_time_coeff = 15000,
dc30c35b 5083 .g1_irqs = 9,
d6c5e6af 5084 .g2_irqs = 10,
e606ca36 5085 .atu_move_port_mask = 0xf,
f3645652 5086 .pvt = true,
b3e05aa1 5087 .multi_chip = true,
670bb80f 5088 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5089 .ops = &mv88e6172_ops,
f81ec90f
VD		 5090 },
5091
5092 [MV88E6175] = {
107fcc10 5093 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 5094 .family = MV88E6XXX_FAMILY_6351,
5095 .name = "Marvell 88E6175",
5096 .num_databases = 4096,
d9ea5620 5097 .num_macs = 8192,
f81ec90f 5098 .num_ports = 7,
bc393155 5099 .num_internal_phys = 5,
3cf3c846 5100 .max_vid = 4095,
9dddd478 5101 .port_base_addr = 0x10,
9255bacd 5102 .phy_base_addr = 0x0,
a935c052 5103 .global1_addr = 0x1b,
9069c13a 5104 .global2_addr = 0x1c,
acddbd21 5105 .age_time_coeff = 15000,
dc30c35b 5106 .g1_irqs = 9,
d6c5e6af 5107 .g2_irqs = 10,
e606ca36 5108 .atu_move_port_mask = 0xf,
f3645652 5109 .pvt = true,
b3e05aa1 5110 .multi_chip = true,
670bb80f 5111 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5112 .ops = &mv88e6175_ops,
f81ec90f
VD		 5113 },
5114
5115 [MV88E6176] = {
107fcc10 5116 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 5117 .family = MV88E6XXX_FAMILY_6352,
5118 .name = "Marvell 88E6176",
5119 .num_databases = 4096,
d9ea5620 5120 .num_macs = 8192,
f81ec90f 5121 .num_ports = 7,
bc393155 5122 .num_internal_phys = 5,
a73ccd61 5123 .num_gpio = 15,
3cf3c846 5124 .max_vid = 4095,
9dddd478 5125 .port_base_addr = 0x10,
9255bacd 5126 .phy_base_addr = 0x0,
a935c052 5127 .global1_addr = 0x1b,
9069c13a 5128 .global2_addr = 0x1c,
acddbd21 5129 .age_time_coeff = 15000,
dc30c35b 5130 .g1_irqs = 9,
d6c5e6af 5131 .g2_irqs = 10,
e606ca36 5132 .atu_move_port_mask = 0xf,
f3645652 5133 .pvt = true,
b3e05aa1 5134 .multi_chip = true,
670bb80f 5135 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5136 .ops = &mv88e6176_ops,
f81ec90f
VD		 5137 },
5138
5139 [MV88E6185] = {
107fcc10 5140 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 5141 .family = MV88E6XXX_FAMILY_6185,
5142 .name = "Marvell 88E6185",
5143 .num_databases = 256,
d9ea5620 5144 .num_macs = 8192,
f81ec90f 5145 .num_ports = 10,
bc393155 5146 .num_internal_phys = 0,
3cf3c846 5147 .max_vid = 4095,
9dddd478 5148 .port_base_addr = 0x10,
9255bacd 5149 .phy_base_addr = 0x0,
a935c052 5150 .global1_addr = 0x1b,
9069c13a 5151 .global2_addr = 0x1c,
acddbd21 5152 .age_time_coeff = 15000,
dc30c35b 5153 .g1_irqs = 8,
e606ca36 5154 .atu_move_port_mask = 0xf,
b3e05aa1 5155 .multi_chip = true,
670bb80f 5156 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5157 .ops = &mv88e6185_ops,
f81ec90f
VD		 5158 },
5159
1a3b39ec 5160 [MV88E6190] = {
107fcc10 5161 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 5162 .family = MV88E6XXX_FAMILY_6390,
5163 .name = "Marvell 88E6190",
5164 .num_databases = 4096,
d9ea5620 5165 .num_macs = 16384,
1a3b39ec 5166 .num_ports = 11, /* 10 + Z80 */
95150f29 5167 .num_internal_phys = 9,
a73ccd61 5168 .num_gpio = 16,
931d1822 5169 .max_vid = 8191,
1a3b39ec 5170 .port_base_addr = 0x0,
9255bacd 5171 .phy_base_addr = 0x0,
1a3b39ec 5172 .global1_addr = 0x1b,
9069c13a 5173 .global2_addr = 0x1c,
b91e055c 5174 .age_time_coeff = 3750,
1a3b39ec 5175 .g1_irqs = 9,
d6c5e6af 5176 .g2_irqs = 14,
f3645652 5177 .pvt = true,
b3e05aa1 5178 .multi_chip = true,
e606ca36 5179 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 5180 .ops = &mv88e6190_ops,
5181 },
5182
5183 [MV88E6190X] = {
107fcc10 5184 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 5185 .family = MV88E6XXX_FAMILY_6390,
5186 .name = "Marvell 88E6190X",
5187 .num_databases = 4096,
d9ea5620 5188 .num_macs = 16384,
1a3b39ec 5189 .num_ports = 11, /* 10 + Z80 */
95150f29 5190 .num_internal_phys = 9,
a73ccd61 5191 .num_gpio = 16,
931d1822 5192 .max_vid = 8191,
1a3b39ec 5193 .port_base_addr = 0x0,
9255bacd 5194 .phy_base_addr = 0x0,
1a3b39ec 5195 .global1_addr = 0x1b,
9069c13a 5196 .global2_addr = 0x1c,
b91e055c 5197 .age_time_coeff = 3750,
1a3b39ec 5198 .g1_irqs = 9,
d6c5e6af 5199 .g2_irqs = 14,
e606ca36 5200 .atu_move_port_mask = 0x1f,
f3645652 5201 .pvt = true,
b3e05aa1 5202 .multi_chip = true,
1a3b39ec
AL		 5203 .ops = &mv88e6190x_ops,
5204 },
5205
5206 [MV88E6191] = {
107fcc10 5207 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 5208 .family = MV88E6XXX_FAMILY_6390,
5209 .name = "Marvell 88E6191",
5210 .num_databases = 4096,
d9ea5620 5211 .num_macs = 16384,
1a3b39ec 5212 .num_ports = 11, /* 10 + Z80 */
95150f29 5213 .num_internal_phys = 9,
931d1822 5214 .max_vid = 8191,
1a3b39ec 5215 .port_base_addr = 0x0,
9255bacd 5216 .phy_base_addr = 0x0,
1a3b39ec 5217 .global1_addr = 0x1b,
9069c13a 5218 .global2_addr = 0x1c,
b91e055c 5219 .age_time_coeff = 3750,
443d5a1b 5220 .g1_irqs = 9,
d6c5e6af 5221 .g2_irqs = 14,
e606ca36 5222 .atu_move_port_mask = 0x1f,
f3645652 5223 .pvt = true,
b3e05aa1 5224 .multi_chip = true,
2fa8d3af 5225 .ptp_support = true,
2cf4cefb 5226 .ops = &mv88e6191_ops,
1a3b39ec
AL		 5227 },
5228
de776d0d
PS		 5229 [MV88E6191X] = {
5230 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5231 .family = MV88E6XXX_FAMILY_6393,
5232 .name = "Marvell 88E6191X",
5233 .num_databases = 4096,
5234 .num_ports = 11, /* 10 + Z80 */
5235 .num_internal_phys = 9,
5236 .max_vid = 8191,
5237 .port_base_addr = 0x0,
5238 .phy_base_addr = 0x0,
5239 .global1_addr = 0x1b,
5240 .global2_addr = 0x1c,
5241 .age_time_coeff = 3750,
5242 .g1_irqs = 10,
5243 .g2_irqs = 14,
5244 .atu_move_port_mask = 0x1f,
5245 .pvt = true,
5246 .multi_chip = true,
de776d0d
PS		 5247 .ptp_support = true,
5248 .ops = &mv88e6393x_ops,
5249 },
5250
5251 [MV88E6193X] = {
5252 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5253 .family = MV88E6XXX_FAMILY_6393,
5254 .name = "Marvell 88E6193X",
5255 .num_databases = 4096,
5256 .num_ports = 11, /* 10 + Z80 */
5257 .num_internal_phys = 9,
5258 .max_vid = 8191,
5259 .port_base_addr = 0x0,
5260 .phy_base_addr = 0x0,
5261 .global1_addr = 0x1b,
5262 .global2_addr = 0x1c,
5263 .age_time_coeff = 3750,
5264 .g1_irqs = 10,
5265 .g2_irqs = 14,
5266 .atu_move_port_mask = 0x1f,
5267 .pvt = true,
5268 .multi_chip = true,
de776d0d
PS		 5269 .ptp_support = true,
5270 .ops = &mv88e6393x_ops,
5271 },
5272
49022647
HF		 5273 [MV88E6220] = {
5274 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5275 .family = MV88E6XXX_FAMILY_6250,
5276 .name = "Marvell 88E6220",
5277 .num_databases = 64,
5278
5279 /* Ports 2-4 are not routed to pins
5280 * => usable ports 0, 1, 5, 6
5281 */
5282 .num_ports = 7,
5283 .num_internal_phys = 2,
c857486a 5284 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
49022647
HF		 5285 .max_vid = 4095,
5286 .port_base_addr = 0x08,
5287 .phy_base_addr = 0x00,
5288 .global1_addr = 0x0f,
5289 .global2_addr = 0x07,
5290 .age_time_coeff = 15000,
5291 .g1_irqs = 9,
5292 .g2_irqs = 10,
5293 .atu_move_port_mask = 0xf,
5294 .dual_chip = true,
71509614 5295 .ptp_support = true,
49022647
HF		 5296 .ops = &mv88e6250_ops,
5297 },
5298
f81ec90f 5299 [MV88E6240] = {
107fcc10 5300 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 5301 .family = MV88E6XXX_FAMILY_6352,
5302 .name = "Marvell 88E6240",
5303 .num_databases = 4096,
d9ea5620 5304 .num_macs = 8192,
f81ec90f 5305 .num_ports = 7,
bc393155 5306 .num_internal_phys = 5,
a73ccd61 5307 .num_gpio = 15,
3cf3c846 5308 .max_vid = 4095,
9dddd478 5309 .port_base_addr = 0x10,
9255bacd 5310 .phy_base_addr = 0x0,
a935c052 5311 .global1_addr = 0x1b,
9069c13a 5312 .global2_addr = 0x1c,
acddbd21 5313 .age_time_coeff = 15000,
dc30c35b 5314 .g1_irqs = 9,
d6c5e6af 5315 .g2_irqs = 10,
e606ca36 5316 .atu_move_port_mask = 0xf,
f3645652 5317 .pvt = true,
b3e05aa1 5318 .multi_chip = true,
670bb80f 5319 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5320 .ptp_support = true,
b3469dd8 5321 .ops = &mv88e6240_ops,
f81ec90f
VD		 5322 },
5323
1f71836f
RV		 5324 [MV88E6250] = {
5325 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5326 .family = MV88E6XXX_FAMILY_6250,
5327 .name = "Marvell 88E6250",
5328 .num_databases = 64,
5329 .num_ports = 7,
5330 .num_internal_phys = 5,
5331 .max_vid = 4095,
5332 .port_base_addr = 0x08,
5333 .phy_base_addr = 0x00,
5334 .global1_addr = 0x0f,
5335 .global2_addr = 0x07,
5336 .age_time_coeff = 15000,
5337 .g1_irqs = 9,
5338 .g2_irqs = 10,
5339 .atu_move_port_mask = 0xf,
5340 .dual_chip = true,
71509614 5341 .ptp_support = true,
1f71836f
RV		 5342 .ops = &mv88e6250_ops,
5343 },
5344
1a3b39ec 5345 [MV88E6290] = {
107fcc10 5346 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 5347 .family = MV88E6XXX_FAMILY_6390,
5348 .name = "Marvell 88E6290",
5349 .num_databases = 4096,
5350 .num_ports = 11, /* 10 + Z80 */
95150f29 5351 .num_internal_phys = 9,
a73ccd61 5352 .num_gpio = 16,
931d1822 5353 .max_vid = 8191,
1a3b39ec 5354 .port_base_addr = 0x0,
9255bacd 5355 .phy_base_addr = 0x0,
1a3b39ec 5356 .global1_addr = 0x1b,
9069c13a 5357 .global2_addr = 0x1c,
b91e055c 5358 .age_time_coeff = 3750,
1a3b39ec 5359 .g1_irqs = 9,
d6c5e6af 5360 .g2_irqs = 14,
e606ca36 5361 .atu_move_port_mask = 0x1f,
f3645652 5362 .pvt = true,
b3e05aa1 5363 .multi_chip = true,
2fa8d3af 5364 .ptp_support = true,
1a3b39ec
AL		 5365 .ops = &mv88e6290_ops,
5366 },
5367
f81ec90f 5368 [MV88E6320] = {
107fcc10 5369 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 5370 .family = MV88E6XXX_FAMILY_6320,
5371 .name = "Marvell 88E6320",
5372 .num_databases = 4096,
d9ea5620 5373 .num_macs = 8192,
f81ec90f 5374 .num_ports = 7,
bc393155 5375 .num_internal_phys = 5,
a73ccd61 5376 .num_gpio = 15,
3cf3c846 5377 .max_vid = 4095,
9dddd478 5378 .port_base_addr = 0x10,
9255bacd 5379 .phy_base_addr = 0x0,
a935c052 5380 .global1_addr = 0x1b,
9069c13a 5381 .global2_addr = 0x1c,
acddbd21 5382 .age_time_coeff = 15000,
dc30c35b 5383 .g1_irqs = 8,
bc393155 5384 .g2_irqs = 10,
e606ca36 5385 .atu_move_port_mask = 0xf,
f3645652 5386 .pvt = true,
b3e05aa1 5387 .multi_chip = true,
670bb80f 5388 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5389 .ptp_support = true,
b3469dd8 5390 .ops = &mv88e6320_ops,
f81ec90f
VD		 5391 },
5392
5393 [MV88E6321] = {
107fcc10 5394 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 5395 .family = MV88E6XXX_FAMILY_6320,
5396 .name = "Marvell 88E6321",
5397 .num_databases = 4096,
d9ea5620 5398 .num_macs = 8192,
f81ec90f 5399 .num_ports = 7,
bc393155 5400 .num_internal_phys = 5,
a73ccd61 5401 .num_gpio = 15,
3cf3c846 5402 .max_vid = 4095,
9dddd478 5403 .port_base_addr = 0x10,
9255bacd 5404 .phy_base_addr = 0x0,
a935c052 5405 .global1_addr = 0x1b,
9069c13a 5406 .global2_addr = 0x1c,
acddbd21 5407 .age_time_coeff = 15000,
dc30c35b 5408 .g1_irqs = 8,
bc393155 5409 .g2_irqs = 10,
e606ca36 5410 .atu_move_port_mask = 0xf,
b3e05aa1 5411 .multi_chip = true,
670bb80f 5412 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5413 .ptp_support = true,
b3469dd8 5414 .ops = &mv88e6321_ops,
f81ec90f
VD		 5415 },
5416
a75961d0 5417 [MV88E6341] = {
107fcc10 5418 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 5419 .family = MV88E6XXX_FAMILY_6341,
5420 .name = "Marvell 88E6341",
5421 .num_databases = 4096,
d9ea5620 5422 .num_macs = 2048,
bc393155 5423 .num_internal_phys = 5,
a75961d0 5424 .num_ports = 6,
a73ccd61 5425 .num_gpio = 11,
3cf3c846 5426 .max_vid = 4095,
a75961d0 5427 .port_base_addr = 0x10,
9255bacd 5428 .phy_base_addr = 0x10,
a75961d0 5429 .global1_addr = 0x1b,
9069c13a 5430 .global2_addr = 0x1c,
a75961d0 5431 .age_time_coeff = 3750,
e606ca36 5432 .atu_move_port_mask = 0x1f,
adfccf11 5433 .g1_irqs = 9,
d6c5e6af 5434 .g2_irqs = 10,
f3645652 5435 .pvt = true,
b3e05aa1 5436 .multi_chip = true,
670bb80f 5437 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5438 .ptp_support = true,
a75961d0
GC		 5439 .ops = &mv88e6341_ops,
5440 },
5441
f81ec90f 5442 [MV88E6350] = {
107fcc10 5443 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 5444 .family = MV88E6XXX_FAMILY_6351,
5445 .name = "Marvell 88E6350",
5446 .num_databases = 4096,
d9ea5620 5447 .num_macs = 8192,
f81ec90f 5448 .num_ports = 7,
bc393155 5449 .num_internal_phys = 5,
3cf3c846 5450 .max_vid = 4095,
9dddd478 5451 .port_base_addr = 0x10,
9255bacd 5452 .phy_base_addr = 0x0,
a935c052 5453 .global1_addr = 0x1b,
9069c13a 5454 .global2_addr = 0x1c,
acddbd21 5455 .age_time_coeff = 15000,
dc30c35b 5456 .g1_irqs = 9,
d6c5e6af 5457 .g2_irqs = 10,
e606ca36 5458 .atu_move_port_mask = 0xf,
f3645652 5459 .pvt = true,
b3e05aa1 5460 .multi_chip = true,
670bb80f 5461 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5462 .ops = &mv88e6350_ops,
f81ec90f
VD		 5463 },
5464
5465 [MV88E6351] = {
107fcc10 5466 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 5467 .family = MV88E6XXX_FAMILY_6351,
5468 .name = "Marvell 88E6351",
5469 .num_databases = 4096,
d9ea5620 5470 .num_macs = 8192,
f81ec90f 5471 .num_ports = 7,
bc393155 5472 .num_internal_phys = 5,
3cf3c846 5473 .max_vid = 4095,
9dddd478 5474 .port_base_addr = 0x10,
9255bacd 5475 .phy_base_addr = 0x0,
a935c052 5476 .global1_addr = 0x1b,
9069c13a 5477 .global2_addr = 0x1c,
acddbd21 5478 .age_time_coeff = 15000,
dc30c35b 5479 .g1_irqs = 9,
d6c5e6af 5480 .g2_irqs = 10,
e606ca36 5481 .atu_move_port_mask = 0xf,
f3645652 5482 .pvt = true,
b3e05aa1 5483 .multi_chip = true,
670bb80f 5484 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5485 .ops = &mv88e6351_ops,
f81ec90f
VD		 5486 },
5487
5488 [MV88E6352] = {
107fcc10 5489 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 5490 .family = MV88E6XXX_FAMILY_6352,
5491 .name = "Marvell 88E6352",
5492 .num_databases = 4096,
d9ea5620 5493 .num_macs = 8192,
f81ec90f 5494 .num_ports = 7,
bc393155 5495 .num_internal_phys = 5,
a73ccd61 5496 .num_gpio = 15,
3cf3c846 5497 .max_vid = 4095,
9dddd478 5498 .port_base_addr = 0x10,
9255bacd 5499 .phy_base_addr = 0x0,
a935c052 5500 .global1_addr = 0x1b,
9069c13a 5501 .global2_addr = 0x1c,
acddbd21 5502 .age_time_coeff = 15000,
dc30c35b 5503 .g1_irqs = 9,
d6c5e6af 5504 .g2_irqs = 10,
e606ca36 5505 .atu_move_port_mask = 0xf,
f3645652 5506 .pvt = true,
b3e05aa1 5507 .multi_chip = true,
670bb80f 5508 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5509 .ptp_support = true,
b3469dd8 5510 .ops = &mv88e6352_ops,
f81ec90f 5511 },
1a3b39ec 5512 [MV88E6390] = {
107fcc10 5513 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 5514 .family = MV88E6XXX_FAMILY_6390,
5515 .name = "Marvell 88E6390",
5516 .num_databases = 4096,
d9ea5620 5517 .num_macs = 16384,
1a3b39ec 5518 .num_ports = 11, /* 10 + Z80 */
95150f29 5519 .num_internal_phys = 9,
a73ccd61 5520 .num_gpio = 16,
931d1822 5521 .max_vid = 8191,
1a3b39ec 5522 .port_base_addr = 0x0,
9255bacd 5523 .phy_base_addr = 0x0,
1a3b39ec 5524 .global1_addr = 0x1b,
9069c13a 5525 .global2_addr = 0x1c,
b91e055c 5526 .age_time_coeff = 3750,
1a3b39ec 5527 .g1_irqs = 9,
d6c5e6af 5528 .g2_irqs = 14,
e606ca36 5529 .atu_move_port_mask = 0x1f,
f3645652 5530 .pvt = true,
b3e05aa1 5531 .multi_chip = true,
670bb80f 5532 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
2fa8d3af 5533 .ptp_support = true,
1a3b39ec
AL		 5534 .ops = &mv88e6390_ops,
5535 },
5536 [MV88E6390X] = {
107fcc10 5537 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 5538 .family = MV88E6XXX_FAMILY_6390,
5539 .name = "Marvell 88E6390X",
5540 .num_databases = 4096,
d9ea5620 5541 .num_macs = 16384,
1a3b39ec 5542 .num_ports = 11, /* 10 + Z80 */
95150f29 5543 .num_internal_phys = 9,
a73ccd61 5544 .num_gpio = 16,
931d1822 5545 .max_vid = 8191,
1a3b39ec 5546 .port_base_addr = 0x0,
9255bacd 5547 .phy_base_addr = 0x0,
1a3b39ec 5548 .global1_addr = 0x1b,
9069c13a 5549 .global2_addr = 0x1c,
b91e055c 5550 .age_time_coeff = 3750,
1a3b39ec 5551 .g1_irqs = 9,
d6c5e6af 5552 .g2_irqs = 14,
e606ca36 5553 .atu_move_port_mask = 0x1f,
f3645652 5554 .pvt = true,
b3e05aa1 5555 .multi_chip = true,
670bb80f 5556 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
2fa8d3af 5557 .ptp_support = true,
1a3b39ec
AL		 5558 .ops = &mv88e6390x_ops,
5559 },
de776d0d
PS		 5560
5561 [MV88E6393X] = {
5562 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5563 .family = MV88E6XXX_FAMILY_6393,
5564 .name = "Marvell 88E6393X",
5565 .num_databases = 4096,
5566 .num_ports = 11, /* 10 + Z80 */
5567 .num_internal_phys = 9,
5568 .max_vid = 8191,
5569 .port_base_addr = 0x0,
5570 .phy_base_addr = 0x0,
5571 .global1_addr = 0x1b,
5572 .global2_addr = 0x1c,
5573 .age_time_coeff = 3750,
5574 .g1_irqs = 10,
5575 .g2_irqs = 14,
5576 .atu_move_port_mask = 0x1f,
5577 .pvt = true,
5578 .multi_chip = true,
de776d0d
PS		 5579 .ptp_support = true,
5580 .ops = &mv88e6393x_ops,
5581 },
f81ec90f
VD		 5582};
5583
5f7c0367 5584static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 5585{
a439c061 5586 int i;
b9b37713 5587
5f7c0367
VD		 5588 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5589 if (mv88e6xxx_table[i].prod_num == prod_num)
5590 return &mv88e6xxx_table[i];
b9b37713 5591
b9b37713
VD		 5592 return NULL;
5593}
5594
fad09c73 5595static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 5596{
5597 const struct mv88e6xxx_info *info;
8f6345b2
VD		 5598 unsigned int prod_num, rev;
5599 u16 id;
5600 int err;
bc46a3d5 5601
c9acece0 5602 mv88e6xxx_reg_lock(chip);
107fcc10 5603 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
c9acece0 5604 mv88e6xxx_reg_unlock(chip);
8f6345b2
VD		 5605 if (err)
5606 return err;
bc46a3d5 5607
107fcc10
VD		 5608 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5609 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 5610
5611 info = mv88e6xxx_lookup_info(prod_num);
5612 if (!info)
5613 return -ENODEV;
5614
caac8545 5615 /* Update the compatible info with the probed one */
fad09c73 5616 chip->info = info;
bc46a3d5 5617
fad09c73
VD		 5618 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5619 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 5620
5621 return 0;
5622}
5623
fad09c73 5624static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 5625{
fad09c73 5626 struct mv88e6xxx_chip *chip;
469d729f 5627
fad09c73
VD		 5628 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5629 if (!chip)
469d729f
VD		 5630 return NULL;
5631
fad09c73 5632 chip->dev = dev;
469d729f 5633
fad09c73 5634 mutex_init(&chip->reg_lock);
a3c53be5 5635 INIT_LIST_HEAD(&chip->mdios);
da7dc875 5636 idr_init(&chip->policies);
469d729f 5637
fad09c73 5638 return chip;
469d729f
VD		 5639}
5640
5ed4e3eb 5641static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4d776482
FF		 5642 int port,
5643 enum dsa_tag_protocol m)
7b314362 5644{
04bed143 5645 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 5646
670bb80f 5647 return chip->tag_protocol;
7b314362
AL		 5648}
5649
9a99bef5
TW		 5650static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5651 enum dsa_tag_protocol proto)
5652{
5653 struct mv88e6xxx_chip *chip = ds->priv;
5654 enum dsa_tag_protocol old_protocol;
5655 int err;
5656
5657 switch (proto) {
5658 case DSA_TAG_PROTO_EDSA:
5659 switch (chip->info->edsa_support) {
5660 case MV88E6XXX_EDSA_UNSUPPORTED:
5661 return -EPROTONOSUPPORT;
5662 case MV88E6XXX_EDSA_UNDOCUMENTED:
5663 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5664 fallthrough;
5665 case MV88E6XXX_EDSA_SUPPORTED:
5666 break;
5667 }
5668 break;
5669 case DSA_TAG_PROTO_DSA:
5670 break;
5671 default:
5672 return -EPROTONOSUPPORT;
5673 }
5674
5675 old_protocol = chip->tag_protocol;
5676 chip->tag_protocol = proto;
5677
5678 mv88e6xxx_reg_lock(chip);
5679 err = mv88e6xxx_setup_port_mode(chip, port);
5680 mv88e6xxx_reg_unlock(chip);
5681
5682 if (err)
5683 chip->tag_protocol = old_protocol;
5684
5685 return err;
5686}
5687
a52b2da7
VO		 5688static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5689 const struct switchdev_obj_port_mdb *mdb)
7df8fbdd 5690{
04bed143 5691 struct mv88e6xxx_chip *chip = ds->priv;
a52b2da7 5692 int err;
7df8fbdd 5693
c9acece0 5694 mv88e6xxx_reg_lock(chip);
a52b2da7
VO		 5695 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5696 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
c9acece0 5697 mv88e6xxx_reg_unlock(chip);
a52b2da7
VO		 5698
5699 return err;
7df8fbdd
VD		 5700}
5701
5702static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5703 const struct switchdev_obj_port_mdb *mdb)
5704{
04bed143 5705 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 5706 int err;
5707
c9acece0 5708 mv88e6xxx_reg_lock(chip);
d8291a95 5709 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
c9acece0 5710 mv88e6xxx_reg_unlock(chip);
7df8fbdd
VD		 5711
5712 return err;
5713}
5714
f0942e00
IT		 5715static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5716 struct dsa_mall_mirror_tc_entry *mirror,
5717 bool ingress)
5718{
5719 enum mv88e6xxx_egress_direction direction = ingress ?
5720 MV88E6XXX_EGRESS_DIR_INGRESS :
5721 MV88E6XXX_EGRESS_DIR_EGRESS;
5722 struct mv88e6xxx_chip *chip = ds->priv;
5723 bool other_mirrors = false;
5724 int i;
5725 int err;
5726
f0942e00
IT		 5727 mutex_lock(&chip->reg_lock);
5728 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5729 mirror->to_local_port) {
5730 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5731 other_mirrors |= ingress ?
5732 chip->ports[i].mirror_ingress :
5733 chip->ports[i].mirror_egress;
5734
5735 /* Can't change egress port when other mirror is active */
5736 if (other_mirrors) {
5737 err = -EBUSY;
5738 goto out;
5739 }
5740
2fda45f0
MB		 5741 err = mv88e6xxx_set_egress_port(chip, direction,
5742 mirror->to_local_port);
f0942e00
IT		 5743 if (err)
5744 goto out;
5745 }
5746
5747 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5748out:
5749 mutex_unlock(&chip->reg_lock);
5750
5751 return err;
5752}
5753
5754static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5755 struct dsa_mall_mirror_tc_entry *mirror)
5756{
5757 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5758 MV88E6XXX_EGRESS_DIR_INGRESS :
5759 MV88E6XXX_EGRESS_DIR_EGRESS;
5760 struct mv88e6xxx_chip *chip = ds->priv;
5761 bool other_mirrors = false;
5762 int i;
5763
5764 mutex_lock(&chip->reg_lock);
5765 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5766 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5767
5768 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5769 other_mirrors |= mirror->ingress ?
5770 chip->ports[i].mirror_ingress :
5771 chip->ports[i].mirror_egress;
5772
5773 /* Reset egress port when no other mirror is active */
5774 if (!other_mirrors) {
2fda45f0
MB		 5775 if (mv88e6xxx_set_egress_port(chip, direction,
5776 dsa_upstream_port(ds, port)))
f0942e00
IT		 5777 dev_err(ds->dev, "failed to set egress port\n");
5778 }
5779
5780 mutex_unlock(&chip->reg_lock);
5781}
5782
a8b659e7
VO		 5783static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5784 struct switchdev_brport_flags flags,
5785 struct netlink_ext_ack *extack)
5786{
5787 struct mv88e6xxx_chip *chip = ds->priv;
5788 const struct mv88e6xxx_ops *ops;
5789
8d1d8298
TW		 5790 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5791 BR_BCAST_FLOOD))
a8b659e7
VO		 5792 return -EINVAL;
5793
5794 ops = chip->info->ops;
5795
5796 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5797 return -EINVAL;
5798
5799 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5800 return -EINVAL;
5801
5802 return 0;
5803}
5804
5805static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5806 struct switchdev_brport_flags flags,
5807 struct netlink_ext_ack *extack)
4f85901f
RK		 5808{
5809 struct mv88e6xxx_chip *chip = ds->priv;
5810 int err = -EOPNOTSUPP;
5811
c9acece0 5812 mv88e6xxx_reg_lock(chip);
a8b659e7 5813
041bd545
TW		 5814 if (flags.mask & BR_LEARNING) {
5815 bool learning = !!(flags.val & BR_LEARNING);
5816 u16 pav = learning ? (1 << port) : 0;
5817
5818 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5819 if (err)
5820 goto out;
041bd545
TW		 5821 }
5822
a8b659e7
VO		 5823 if (flags.mask & BR_FLOOD) {
5824 bool unicast = !!(flags.val & BR_FLOOD);
5825
5826 err = chip->info->ops->port_set_ucast_flood(chip, port,
5827 unicast);
5828 if (err)
5829 goto out;
5830 }
5831
5832 if (flags.mask & BR_MCAST_FLOOD) {
5833 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5834
5835 err = chip->info->ops->port_set_mcast_flood(chip, port,
5836 multicast);
5837 if (err)
5838 goto out;
5839 }
5840
8d1d8298
TW		 5841 if (flags.mask & BR_BCAST_FLOOD) {
5842 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5843
5844 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5845 if (err)
5846 goto out;
5847 }
5848
a8b659e7
VO		 5849out:
5850 mv88e6xxx_reg_unlock(chip);
5851
5852 return err;
5853}
5854
57e661aa
TW		 5855static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5856 struct net_device *lag,
5857 struct netdev_lag_upper_info *info)
5858{
b80dc51b 5859 struct mv88e6xxx_chip *chip = ds->priv;
57e661aa
TW		 5860 struct dsa_port *dp;
5861 int id, members = 0;
5862
b80dc51b
TW		 5863 if (!mv88e6xxx_has_lag(chip))
5864 return false;
5865
57e661aa
TW		 5866 id = dsa_lag_id(ds->dst, lag);
5867 if (id < 0 || id >= ds->num_lag_ids)
5868 return false;
5869
5870 dsa_lag_foreach_port(dp, ds->dst, lag)
5871 /* Includes the port joining the LAG */
5872 members++;
5873
5874 if (members > 8)
5875 return false;
5876
5877 /* We could potentially relax this to include active
5878 * backup in the future.
5879 */
5880 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5881 return false;
5882
5883 /* Ideally we would also validate that the hash type matches
5884 * the hardware. Alas, this is always set to unknown on team
5885 * interfaces.
5886 */
5887 return true;
5888}
5889
5890static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5891{
5892 struct mv88e6xxx_chip *chip = ds->priv;
5893 struct dsa_port *dp;
5894 u16 map = 0;
5895 int id;
5896
5897 id = dsa_lag_id(ds->dst, lag);
5898
5899 /* Build the map of all ports to distribute flows destined for
5900 * this LAG. This can be either a local user port, or a DSA
5901 * port if the LAG port is on a remote chip.
5902 */
5903 dsa_lag_foreach_port(dp, ds->dst, lag)
5904 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5905
5906 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5907}
5908
5909static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5910 /* Row number corresponds to the number of active members in a
5911 * LAG. Each column states which of the eight hash buckets are
5912 * mapped to the column:th port in the LAG.
5913 *
5914 * Example: In a LAG with three active ports, the second port
5915 * ([2][1]) would be selected for traffic mapped to buckets
5916 * 3,4,5 (0x38).
5917 */
5918 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
5919 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
5920 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
5921 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
5922 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
5923 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
5924 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
5925 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
5926};
5927
5928static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
5929 int num_tx, int nth)
5930{
5931 u8 active = 0;
5932 int i;
5933
5934 num_tx = num_tx <= 8 ? num_tx : 8;
5935 if (nth < num_tx)
5936 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
5937
5938 for (i = 0; i < 8; i++) {
5939 if (BIT(i) & active)
5940 mask[i] |= BIT(port);
5941 }
5942}
5943
5944static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
5945{
5946 struct mv88e6xxx_chip *chip = ds->priv;
5947 unsigned int id, num_tx;
5948 struct net_device *lag;
5949 struct dsa_port *dp;
5950 int i, err, nth;
5951 u16 mask[8];
5952 u16 ivec;
5953
5954 /* Assume no port is a member of any LAG. */
5955 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
5956
5957 /* Disable all masks for ports that _are_ members of a LAG. */
5958 list_for_each_entry(dp, &ds->dst->ports, list) {
5959 if (!dp->lag_dev || dp->ds != ds)
5960 continue;
5961
5962 ivec &= ~BIT(dp->index);
5963 }
5964
5965 for (i = 0; i < 8; i++)
5966 mask[i] = ivec;
5967
5968 /* Enable the correct subset of masks for all LAG ports that
5969 * are in the Tx set.
5970 */
5971 dsa_lags_foreach_id(id, ds->dst) {
5972 lag = dsa_lag_dev(ds->dst, id);
5973 if (!lag)
5974 continue;
5975
5976 num_tx = 0;
5977 dsa_lag_foreach_port(dp, ds->dst, lag) {
5978 if (dp->lag_tx_enabled)
5979 num_tx++;
5980 }
5981
5982 if (!num_tx)
5983 continue;
5984
5985 nth = 0;
5986 dsa_lag_foreach_port(dp, ds->dst, lag) {
5987 if (!dp->lag_tx_enabled)
5988 continue;
5989
5990 if (dp->ds == ds)
5991 mv88e6xxx_lag_set_port_mask(mask, dp->index,
5992 num_tx, nth);
5993
5994 nth++;
5995 }
5996 }
5997
5998 for (i = 0; i < 8; i++) {
5999 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6000 if (err)
6001 return err;
6002 }
6003
6004 return 0;
6005}
6006
6007static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6008 struct net_device *lag)
6009{
6010 int err;
6011
6012 err = mv88e6xxx_lag_sync_masks(ds);
6013
6014 if (!err)
6015 err = mv88e6xxx_lag_sync_map(ds, lag);
6016
6017 return err;
6018}
6019
6020static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6021{
6022 struct mv88e6xxx_chip *chip = ds->priv;
6023 int err;
6024
6025 mv88e6xxx_reg_lock(chip);
6026 err = mv88e6xxx_lag_sync_masks(ds);
6027 mv88e6xxx_reg_unlock(chip);
6028 return err;
6029}
6030
6031static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6032 struct net_device *lag,
6033 struct netdev_lag_upper_info *info)
6034{
6035 struct mv88e6xxx_chip *chip = ds->priv;
6036 int err, id;
6037
6038 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6039 return -EOPNOTSUPP;
6040
6041 id = dsa_lag_id(ds->dst, lag);
6042
6043 mv88e6xxx_reg_lock(chip);
6044
6045 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6046 if (err)
6047 goto err_unlock;
6048
6049 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6050 if (err)
6051 goto err_clear_trunk;
6052
6053 mv88e6xxx_reg_unlock(chip);
6054 return 0;
6055
6056err_clear_trunk:
6057 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6058err_unlock:
6059 mv88e6xxx_reg_unlock(chip);
6060 return err;
6061}
6062
6063static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6064 struct net_device *lag)
6065{
6066 struct mv88e6xxx_chip *chip = ds->priv;
6067 int err_sync, err_trunk;
6068
6069 mv88e6xxx_reg_lock(chip);
6070 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6071 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6072 mv88e6xxx_reg_unlock(chip);
6073 return err_sync ? : err_trunk;
6074}
6075
6076static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6077 int port)
6078{
6079 struct mv88e6xxx_chip *chip = ds->priv;
6080 int err;
6081
6082 mv88e6xxx_reg_lock(chip);
6083 err = mv88e6xxx_lag_sync_masks(ds);
6084 mv88e6xxx_reg_unlock(chip);
6085 return err;
6086}
6087
6088static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6089 int port, struct net_device *lag,
6090 struct netdev_lag_upper_info *info)
6091{
6092 struct mv88e6xxx_chip *chip = ds->priv;
6093 int err;
6094
6095 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6096 return -EOPNOTSUPP;
6097
6098 mv88e6xxx_reg_lock(chip);
6099
6100 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6101 if (err)
6102 goto unlock;
6103
6104 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6105
6106unlock:
6107 mv88e6xxx_reg_unlock(chip);
6108 return err;
6109}
6110
6111static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6112 int port, struct net_device *lag)
6113{
6114 struct mv88e6xxx_chip *chip = ds->priv;
6115 int err_sync, err_pvt;
6116
6117 mv88e6xxx_reg_lock(chip);
6118 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6119 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6120 mv88e6xxx_reg_unlock(chip);
6121 return err_sync ? : err_pvt;
6122}
6123
a82f67af 6124static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
7b314362 6125 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
9a99bef5 6126 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
f81ec90f 6127 .setup = mv88e6xxx_setup,
23e8b470 6128 .teardown = mv88e6xxx_teardown,
fd292c18
VO		 6129 .port_setup = mv88e6xxx_port_setup,
6130 .port_teardown = mv88e6xxx_port_teardown,
c9a2356f 6131 .phylink_validate = mv88e6xxx_validate,
a5a6858b 6132 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
c9a2356f 6133 .phylink_mac_config = mv88e6xxx_mac_config,
a5a6858b 6134 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
c9a2356f
RK		 6135 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6136 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
f81ec90f
VD		 6137 .get_strings = mv88e6xxx_get_strings,
6138 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6139 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 6140 .port_enable = mv88e6xxx_port_enable,
6141 .port_disable = mv88e6xxx_port_disable,
2a550aec
AL		 6142 .port_max_mtu = mv88e6xxx_get_max_mtu,
6143 .port_change_mtu = mv88e6xxx_change_mtu,
08f50061
VD		 6144 .get_mac_eee = mv88e6xxx_get_mac_eee,
6145 .set_mac_eee = mv88e6xxx_set_mac_eee,
f8cd8753 6146 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 6147 .get_eeprom = mv88e6xxx_get_eeprom,
6148 .set_eeprom = mv88e6xxx_set_eeprom,
6149 .get_regs_len = mv88e6xxx_get_regs_len,
6150 .get_regs = mv88e6xxx_get_regs,
da7dc875
VD		 6151 .get_rxnfc = mv88e6xxx_get_rxnfc,
6152 .set_rxnfc = mv88e6xxx_set_rxnfc,
2cfcd964 6153 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 6154 .port_bridge_join = mv88e6xxx_port_bridge_join,
6155 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
a8b659e7
VO		 6156 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6157 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
f81ec90f 6158 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 6159 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f 6160 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
f81ec90f
VD		 6161 .port_vlan_add = mv88e6xxx_port_vlan_add,
6162 .port_vlan_del = mv88e6xxx_port_vlan_del,
f81ec90f
VD		 6163 .port_fdb_add = mv88e6xxx_port_fdb_add,
6164 .port_fdb_del = mv88e6xxx_port_fdb_del,
6165 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 6166 .port_mdb_add = mv88e6xxx_port_mdb_add,
6167 .port_mdb_del = mv88e6xxx_port_mdb_del,
f0942e00
IT		 6168 .port_mirror_add = mv88e6xxx_port_mirror_add,
6169 .port_mirror_del = mv88e6xxx_port_mirror_del,
aec5ac88
VD		 6170 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6171 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
c6fe0ad2
BS		 6172 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6173 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6174 .port_txtstamp = mv88e6xxx_port_txtstamp,
6175 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6176 .get_ts_info = mv88e6xxx_get_ts_info,
23e8b470
AL		 6177 .devlink_param_get = mv88e6xxx_devlink_param_get,
6178 .devlink_param_set = mv88e6xxx_devlink_param_set,
93157307 6179 .devlink_info_get = mv88e6xxx_devlink_info_get,
57e661aa
TW		 6180 .port_lag_change = mv88e6xxx_port_lag_change,
6181 .port_lag_join = mv88e6xxx_port_lag_join,
6182 .port_lag_leave = mv88e6xxx_port_lag_leave,
6183 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6184 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6185 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
ce5df689
VO		 6186 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload,
6187 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload,
f81ec90f
VD		 6188};
6189
55ed0ce0 6190static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 6191{
fad09c73 6192 struct device *dev = chip->dev;
b7e66a5f
VD		 6193 struct dsa_switch *ds;
6194
7e99e347 6195 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
b7e66a5f
VD		 6196 if (!ds)
6197 return -ENOMEM;
6198
7e99e347
VD		 6199 ds->dev = dev;
6200 ds->num_ports = mv88e6xxx_num_ports(chip);
fad09c73 6201 ds->priv = chip;
877b7cb0 6202 ds->dev = dev;
9d490b4e 6203 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 6204 ds->ageing_time_min = chip->info->age_time_coeff;
6205 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f 6206
57e661aa
TW		 6207 /* Some chips support up to 32, but that requires enabling the
6208 * 5-bit port mode, which we do not support. 640k^W16 ought to
6209 * be enough for anyone.
6210 */
b80dc51b 6211 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
57e661aa 6212
b7e66a5f
VD		 6213 dev_set_drvdata(dev, ds);
6214
23c9ee49 6215 return dsa_register_switch(ds);
b7e66a5f
VD		 6216}
6217
fad09c73 6218static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 6219{
fad09c73 6220 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 6221}
6222
877b7cb0
AL		 6223static const void *pdata_device_get_match_data(struct device *dev)
6224{
6225 const struct of_device_id *matches = dev->driver->of_match_table;
6226 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6227
6228 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6229 matches++) {
6230 if (!strcmp(pdata->compatible, matches->compatible))
6231 return matches->data;
6232 }
6233 return NULL;
6234}
6235
bcd3d9d9
MR		 6236/* There is no suspend to RAM support at DSA level yet, the switch configuration
6237 * would be lost after a power cycle so prevent it to be suspended.
6238 */
6239static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6240{
6241 return -EOPNOTSUPP;
6242}
6243
6244static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6245{
6246 return 0;
6247}
6248
6249static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6250
57d32310 6251static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 6252{
877b7cb0 6253 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7ddae24f 6254 const struct mv88e6xxx_info *compat_info = NULL;
14c7b3c3 6255 struct device *dev = &mdiodev->dev;
f8cd8753 6256 struct device_node *np = dev->of_node;
fad09c73 6257 struct mv88e6xxx_chip *chip;
877b7cb0 6258 int port;
52638f71 6259 int err;
14c7b3c3 6260
7bb8c996
AL		 6261 if (!np && !pdata)
6262 return -EINVAL;
6263
877b7cb0
AL		 6264 if (np)
6265 compat_info = of_device_get_match_data(dev);
6266
6267 if (pdata) {
6268 compat_info = pdata_device_get_match_data(dev);
6269
6270 if (!pdata->netdev)
6271 return -EINVAL;
6272
6273 for (port = 0; port < DSA_MAX_PORTS; port++) {
6274 if (!(pdata->enabled_ports & (1 << port)))
6275 continue;
6276 if (strcmp(pdata->cd.port_names[port], "cpu"))
6277 continue;
6278 pdata->cd.netdev[port] = &pdata->netdev->dev;
6279 break;
6280 }
6281 }
6282
caac8545
VD		 6283 if (!compat_info)
6284 return -EINVAL;
6285
fad09c73 6286 chip = mv88e6xxx_alloc_chip(dev);
877b7cb0
AL		 6287 if (!chip) {
6288 err = -ENOMEM;
6289 goto out;
6290 }
14c7b3c3 6291
fad09c73 6292 chip->info = compat_info;
caac8545 6293
fad09c73 6294 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab 6295 if (err)
877b7cb0 6296 goto out;
14c7b3c3 6297
b4308f04 6298 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
877b7cb0
AL		 6299 if (IS_ERR(chip->reset)) {
6300 err = PTR_ERR(chip->reset);
6301 goto out;
6302 }
7b75e49d
BS		 6303 if (chip->reset)
6304 usleep_range(1000, 2000);
b4308f04 6305
fad09c73 6306 err = mv88e6xxx_detect(chip);
bc46a3d5 6307 if (err)
877b7cb0 6308 goto out;
14c7b3c3 6309
670bb80f
TW		 6310 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6311 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6312 else
6313 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6314
e57e5e77
VD		 6315 mv88e6xxx_phy_init(chip);
6316
00baabe5
AL		 6317 if (chip->info->ops->get_eeprom) {
6318 if (np)
6319 of_property_read_u32(np, "eeprom-length",
6320 &chip->eeprom_len);
6321 else
6322 chip->eeprom_len = pdata->eeprom_len;
6323 }
f8cd8753 6324
c9acece0 6325 mv88e6xxx_reg_lock(chip);
dc30c35b 6326 err = mv88e6xxx_switch_reset(chip);
c9acece0 6327 mv88e6xxx_reg_unlock(chip);
dc30c35b
AL		 6328 if (err)
6329 goto out;
6330
a27415de
AL		 6331 if (np) {
6332 chip->irq = of_irq_get(np, 0);
6333 if (chip->irq == -EPROBE_DEFER) {
6334 err = chip->irq;
6335 goto out;
6336 }
dc30c35b
AL		 6337 }
6338
a27415de
AL		 6339 if (pdata)
6340 chip->irq = pdata->irq;
6341
294d711e 6342 /* Has to be performed before the MDIO bus is created, because
a708767e 6343 * the PHYs will link their interrupts to these interrupt
294d711e
AL		 6344 * controllers
6345 */
c9acece0 6346 mv88e6xxx_reg_lock(chip);
294d711e 6347 if (chip->irq > 0)
dc30c35b 6348 err = mv88e6xxx_g1_irq_setup(chip);
294d711e
AL		 6349 else
6350 err = mv88e6xxx_irq_poll_setup(chip);
c9acece0 6351 mv88e6xxx_reg_unlock(chip);
0977644c 6352
294d711e
AL		 6353 if (err)
6354 goto out;
62eb1162 6355
294d711e
AL		 6356 if (chip->info->g2_irqs > 0) {
6357 err = mv88e6xxx_g2_irq_setup(chip);
62eb1162 6358 if (err)
294d711e 6359 goto out_g1_irq;
dc30c35b
AL		 6360 }
6361
294d711e
AL		 6362 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6363 if (err)
6364 goto out_g2_irq;
6365
6366 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6367 if (err)
6368 goto out_g1_atu_prob_irq;
6369
a3c53be5 6370 err = mv88e6xxx_mdios_register(chip, np);
b516d453 6371 if (err)
62eb1162 6372 goto out_g1_vtu_prob_irq;
b516d453 6373
55ed0ce0 6374 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 6375 if (err)
6376 goto out_mdio;
83c0afae 6377
98e67308 6378 return 0;
dc30c35b
AL		 6379
6380out_mdio:
a3c53be5 6381 mv88e6xxx_mdios_unregister(chip);
62eb1162 6382out_g1_vtu_prob_irq:
294d711e 6383 mv88e6xxx_g1_vtu_prob_irq_free(chip);
0977644c 6384out_g1_atu_prob_irq:
294d711e 6385 mv88e6xxx_g1_atu_prob_irq_free(chip);
dc30c35b 6386out_g2_irq:
294d711e 6387 if (chip->info->g2_irqs > 0)
dc30c35b
AL		 6388 mv88e6xxx_g2_irq_free(chip);
6389out_g1_irq:
294d711e 6390 if (chip->irq > 0)
46712644 6391 mv88e6xxx_g1_irq_free(chip);
294d711e
AL		 6392 else
6393 mv88e6xxx_irq_poll_free(chip);
dc30c35b 6394out:
877b7cb0
AL		 6395 if (pdata)
6396 dev_put(pdata->netdev);
6397
dc30c35b 6398 return err;
98e67308 6399}
14c7b3c3
AL		 6400
6401static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6402{
6403 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
0650bf52
VO		 6404 struct mv88e6xxx_chip *chip;
6405
6406 if (!ds)
6407 return;
6408
6409 chip = ds->priv;
14c7b3c3 6410
c6fe0ad2
BS		 6411 if (chip->info->ptp_support) {
6412 mv88e6xxx_hwtstamp_free(chip);
2fa8d3af 6413 mv88e6xxx_ptp_free(chip);
c6fe0ad2 6414 }
2fa8d3af 6415
930188ce 6416 mv88e6xxx_phy_destroy(chip);
fad09c73 6417 mv88e6xxx_unregister_switch(chip);
a3c53be5 6418 mv88e6xxx_mdios_unregister(chip);
dc30c35b 6419
76f38f1f
AL		 6420 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6421 mv88e6xxx_g1_atu_prob_irq_free(chip);
6422
6423 if (chip->info->g2_irqs > 0)
6424 mv88e6xxx_g2_irq_free(chip);
6425
76f38f1f 6426 if (chip->irq > 0)
46712644 6427 mv88e6xxx_g1_irq_free(chip);
76f38f1f
AL		 6428 else
6429 mv88e6xxx_irq_poll_free(chip);
0650bf52
VO		 6430
6431 dev_set_drvdata(&mdiodev->dev, NULL);
6432}
6433
6434static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
6435{
6436 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6437
6438 if (!ds)
6439 return;
6440
6441 dsa_switch_shutdown(ds);
6442
6443 dev_set_drvdata(&mdiodev->dev, NULL);
14c7b3c3
AL		 6444}
6445
6446static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 6447 {
6448 .compatible = "marvell,mv88e6085",
6449 .data = &mv88e6xxx_table[MV88E6085],
6450 },
1a3b39ec
AL		 6451 {
6452 .compatible = "marvell,mv88e6190",
6453 .data = &mv88e6xxx_table[MV88E6190],
6454 },
1f71836f
RV		 6455 {
6456 .compatible = "marvell,mv88e6250",
6457 .data = &mv88e6xxx_table[MV88E6250],
6458 },
14c7b3c3
AL		 6459 { /* sentinel */ },
6460};
6461
6462MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6463
6464static struct mdio_driver mv88e6xxx_driver = {
6465 .probe = mv88e6xxx_probe,
6466 .remove = mv88e6xxx_remove,
0650bf52 6467 .shutdown = mv88e6xxx_shutdown,
14c7b3c3
AL		 6468 .mdiodrv.driver = {
6469 .name = "mv88e6085",
6470 .of_match_table = mv88e6xxx_of_match,
bcd3d9d9 6471 .pm = &mv88e6xxx_pm_ops,
14c7b3c3
AL		 6472 },
6473};
6474
7324d50e 6475mdio_module_driver(mv88e6xxx_driver);
3d825ede
BH		 6476
6477MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6478MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6479MODULE_LICENSE("GPL");
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