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net: dsa: mv88e6xxx: Don't modify RGMII delays when not RGMII mode
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
dc30c35b
AL		 21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
19b2f97e 24#include <linux/jiffies.h>
91da11f8 25#include <linux/list.h>
14c7b3c3 26#include <linux/mdio.h>
2bbba277 27#include <linux/module.h>
caac8545 28#include <linux/of_device.h>
dc30c35b 29#include <linux/of_irq.h>
b516d453 30#include <linux/of_mdio.h>
91da11f8 31#include <linux/netdevice.h>
c8c1b39a 32#include <linux/gpio/consumer.h>
91da11f8 33#include <linux/phy.h>
c8f0b869 34#include <net/dsa.h>
1f36faf2 35#include <net/switchdev.h>
ec561276 36
91da11f8 37#include "mv88e6xxx.h"
a935c052 38#include "global1.h"
ec561276 39#include "global2.h"
18abed21 40#include "port.h"
91da11f8 41
fad09c73 42static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 43{
fad09c73
VD		 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 46 dump_stack();
47 }
48}
49
914b32f6
VD		 50/* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 60 */
914b32f6 61
fad09c73 62static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 63 int addr, int reg, u16 *val)
64{
fad09c73 65 if (!chip->smi_ops)
914b32f6
VD		 66 return -EOPNOTSUPP;
67
fad09c73 68 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 69}
70
fad09c73 71static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 72 int addr, int reg, u16 val)
73{
fad09c73 74 if (!chip->smi_ops)
914b32f6
VD		 75 return -EOPNOTSUPP;
76
fad09c73 77 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 78}
79
fad09c73 80static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 81 int addr, int reg, u16 *val)
82{
83 int ret;
84
fad09c73 85 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92}
93
fad09c73 94static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 95 int addr, int reg, u16 val)
96{
97 int ret;
98
fad09c73 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 100 if (ret < 0)
101 return ret;
102
103 return 0;
104}
105
c08026ab 106static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
914b32f6
VD		 107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109};
110
fad09c73 111static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 112{
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
fad09c73 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 118 if (ret < 0)
119 return ret;
120
cca8b133 121 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 122 return 0;
123 }
124
125 return -ETIMEDOUT;
126}
127
fad09c73 128static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 129 int addr, int reg, u16 *val)
91da11f8
LB		 130{
131 int ret;
132
3675c8d7 133 /* Wait for the bus to become free. */
fad09c73 134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Transmit the read command. */
fad09c73 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 141 if (ret < 0)
142 return ret;
143
3675c8d7 144 /* Wait for the read command to complete. */
fad09c73 145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 146 if (ret < 0)
147 return ret;
148
3675c8d7 149 /* Read the data. */
fad09c73 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 151 if (ret < 0)
152 return ret;
153
914b32f6 154 *val = ret & 0xffff;
91da11f8 155
914b32f6 156 return 0;
8d6d09e7
GR		 157}
158
fad09c73 159static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 160 int addr, int reg, u16 val)
91da11f8
LB		 161{
162 int ret;
163
3675c8d7 164 /* Wait for the bus to become free. */
fad09c73 165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 166 if (ret < 0)
167 return ret;
168
3675c8d7 169 /* Transmit the data to write. */
fad09c73 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Transmit the write command. */
fad09c73 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 177 if (ret < 0)
178 return ret;
179
3675c8d7 180 /* Wait for the write command to complete. */
fad09c73 181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 182 if (ret < 0)
183 return ret;
184
185 return 0;
186}
187
c08026ab 188static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
914b32f6
VD		 189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191};
192
ec561276 193int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 194{
195 int err;
196
fad09c73 197 assert_reg_lock(chip);
914b32f6 198
fad09c73 199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 200 if (err)
201 return err;
202
fad09c73 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 204 addr, reg, *val);
205
206 return 0;
207}
208
ec561276 209int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 210{
914b32f6
VD		 211 int err;
212
fad09c73 213 assert_reg_lock(chip);
91da11f8 214
fad09c73 215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 216 if (err)
217 return err;
218
fad09c73 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 220 addr, reg, val);
221
914b32f6
VD		 222 return 0;
223}
224
e57e5e77
VD		 225static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227{
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
b3469dd8 230 if (!chip->info->ops->phy_read)
e57e5e77
VD		 231 return -EOPNOTSUPP;
232
b3469dd8 233 return chip->info->ops->phy_read(chip, addr, reg, val);
e57e5e77
VD		 234}
235
236static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
b3469dd8 241 if (!chip->info->ops->phy_write)
e57e5e77
VD		 242 return -EOPNOTSUPP;
243
b3469dd8 244 return chip->info->ops->phy_write(chip, addr, reg, val);
e57e5e77
VD		 245}
246
09cb7dfd
VD		 247static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248{
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253}
254
255static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256{
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265}
266
267static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269{
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283}
284
285static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287{
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301}
302
303static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304{
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
309static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310{
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313}
314
dc30c35b
AL		 315static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316{
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321}
322
323static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324{
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329}
330
331static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332{
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356}
357
358static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359{
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363}
364
365static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366{
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383out:
384 mutex_unlock(&chip->reg_lock);
385}
386
387static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393};
394
395static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398{
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406}
407
408static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411};
412
413static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414{
415 int irq, virq;
416
417 for (irq = 0; irq < 16; irq++) {
418 virq = irq_find_mapping(chip->g2_irq.domain, irq);
419 irq_dispose_mapping(virq);
420 }
421
422 irq_domain_remove(chip->g2_irq.domain);
423}
424
425static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
426{
427 int err, irq;
428 u16 reg;
429
430 chip->g1_irq.nirqs = chip->info->g1_irqs;
431 chip->g1_irq.domain = irq_domain_add_simple(
432 NULL, chip->g1_irq.nirqs, 0,
433 &mv88e6xxx_g1_irq_domain_ops, chip);
434 if (!chip->g1_irq.domain)
435 return -ENOMEM;
436
437 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
438 irq_create_mapping(chip->g1_irq.domain, irq);
439
440 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
441 chip->g1_irq.masked = ~0;
442
443 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
444 if (err)
445 goto out;
446
447 reg &= ~GENMASK(chip->g1_irq.nirqs, 0);
448
449 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
450 if (err)
451 goto out;
452
453 /* Reading the interrupt status clears (most of) them */
454 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
455 if (err)
456 goto out;
457
458 err = request_threaded_irq(chip->irq, NULL,
459 mv88e6xxx_g1_irq_thread_fn,
460 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
461 dev_name(chip->dev), chip);
462 if (err)
463 goto out;
464
465 return 0;
466
467out:
468 mv88e6xxx_g1_irq_free(chip);
469
470 return err;
471}
472
ec561276 473int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 474{
6441e669 475 int i;
2d79af6e 476
6441e669 477 for (i = 0; i < 16; i++) {
2d79af6e
VD		 478 u16 val;
479 int err;
480
481 err = mv88e6xxx_read(chip, addr, reg, &val);
482 if (err)
483 return err;
484
485 if (!(val & mask))
486 return 0;
487
488 usleep_range(1000, 2000);
489 }
490
30853553 491 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 492 return -ETIMEDOUT;
493}
494
f22ab641 495/* Indirect write to single pointer-data register with an Update bit */
ec561276 496int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 497{
498 u16 val;
0f02b4f7 499 int err;
f22ab641
VD		 500
501 /* Wait until the previous operation is completed */
0f02b4f7
AL		 502 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
503 if (err)
504 return err;
f22ab641
VD		 505
506 /* Set the Update bit to trigger a write operation */
507 val = BIT(15) | update;
508
509 return mv88e6xxx_write(chip, addr, reg, val);
510}
511
a935c052 512static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
914b32f6
VD		 513{
514 u16 val;
a935c052 515 int i, err;
914b32f6 516
a935c052 517 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
914b32f6
VD		 518 if (err)
519 return err;
520
a935c052
VD		 521 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
522 val & ~GLOBAL_CONTROL_PPU_ENABLE);
523 if (err)
524 return err;
2e5f0320 525
6441e669 526 for (i = 0; i < 16; i++) {
a935c052
VD		 527 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
528 if (err)
529 return err;
48ace4ef 530
19b2f97e 531 usleep_range(1000, 2000);
a935c052 532 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
85686581 533 return 0;
2e5f0320
LB		 534 }
535
536 return -ETIMEDOUT;
537}
538
fad09c73 539static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 540{
a935c052
VD		 541 u16 val;
542 int i, err;
2e5f0320 543
a935c052
VD		 544 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
545 if (err)
546 return err;
48ace4ef 547
a935c052
VD		 548 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
549 val | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 550 if (err)
551 return err;
2e5f0320 552
6441e669 553 for (i = 0; i < 16; i++) {
a935c052
VD		 554 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
555 if (err)
556 return err;
48ace4ef 557
19b2f97e 558 usleep_range(1000, 2000);
a935c052 559 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
85686581 560 return 0;
2e5f0320
LB		 561 }
562
563 return -ETIMEDOUT;
564}
565
566static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
567{
fad09c73 568 struct mv88e6xxx_chip *chip;
2e5f0320 569
fad09c73 570 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 571
fad09c73 572 mutex_lock(&chip->reg_lock);
762eb67b 573
fad09c73
VD		 574 if (mutex_trylock(&chip->ppu_mutex)) {
575 if (mv88e6xxx_ppu_enable(chip) == 0)
576 chip->ppu_disabled = 0;
577 mutex_unlock(&chip->ppu_mutex);
2e5f0320 578 }
762eb67b 579
fad09c73 580 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 581}
582
583static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
584{
fad09c73 585 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 586
fad09c73 587 schedule_work(&chip->ppu_work);
2e5f0320
LB		 588}
589
fad09c73 590static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 591{
2e5f0320
LB		 592 int ret;
593
fad09c73 594 mutex_lock(&chip->ppu_mutex);
2e5f0320 595
3675c8d7 596 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 597 * we can access the PHY registers. If it was already
598 * disabled, cancel the timer that is going to re-enable
599 * it.
600 */
fad09c73
VD		 601 if (!chip->ppu_disabled) {
602 ret = mv88e6xxx_ppu_disable(chip);
85686581 603 if (ret < 0) {
fad09c73 604 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 605 return ret;
606 }
fad09c73 607 chip->ppu_disabled = 1;
2e5f0320 608 } else {
fad09c73 609 del_timer(&chip->ppu_timer);
85686581 610 ret = 0;
2e5f0320
LB		 611 }
612
613 return ret;
614}
615
fad09c73 616static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 617{
3675c8d7 618 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 619 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
620 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 621}
622
fad09c73 623static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 624{
fad09c73
VD		 625 mutex_init(&chip->ppu_mutex);
626 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
68497a87
WY		 627 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
628 (unsigned long)chip);
2e5f0320
LB		 629}
630
930188ce
AL		 631static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
632{
633 del_timer_sync(&chip->ppu_timer);
634}
635
e57e5e77
VD		 636static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
637 int reg, u16 *val)
2e5f0320 638{
e57e5e77 639 int err;
2e5f0320 640
e57e5e77
VD		 641 err = mv88e6xxx_ppu_access_get(chip);
642 if (!err) {
643 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 644 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 645 }
646
e57e5e77 647 return err;
2e5f0320
LB		 648}
649
e57e5e77
VD		 650static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
651 int reg, u16 val)
2e5f0320 652{
e57e5e77 653 int err;
2e5f0320 654
e57e5e77
VD		 655 err = mv88e6xxx_ppu_access_get(chip);
656 if (!err) {
657 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 658 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 659 }
660
e57e5e77 661 return err;
2e5f0320 662}
2e5f0320 663
fad09c73 664static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 665{
fad09c73 666 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 667}
668
fad09c73 669static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 670{
fad09c73 671 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 672}
673
fad09c73 674static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 675{
fad09c73 676 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 677}
678
fad09c73 679static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 680{
fad09c73 681 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 682}
683
fad09c73 684static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 685{
fad09c73 686 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 687}
688
fad09c73 689static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 690{
fad09c73 691 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 692}
693
fad09c73 694static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 695{
fad09c73 696 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 697}
698
fad09c73 699static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 700{
fad09c73 701 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 702}
703
d78343d2
VD		 704static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
705 int link, int speed, int duplex,
706 phy_interface_t mode)
707{
708 int err;
709
710 if (!chip->info->ops->port_set_link)
711 return 0;
712
713 /* Port's MAC control must not be changed unless the link is down */
714 err = chip->info->ops->port_set_link(chip, port, 0);
715 if (err)
716 return err;
717
718 if (chip->info->ops->port_set_speed) {
719 err = chip->info->ops->port_set_speed(chip, port, speed);
720 if (err && err != -EOPNOTSUPP)
721 goto restore_link;
722 }
723
724 if (chip->info->ops->port_set_duplex) {
725 err = chip->info->ops->port_set_duplex(chip, port, duplex);
726 if (err && err != -EOPNOTSUPP)
727 goto restore_link;
728 }
729
730 if (chip->info->ops->port_set_rgmii_delay) {
731 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
732 if (err && err != -EOPNOTSUPP)
733 goto restore_link;
734 }
735
736 err = 0;
737restore_link:
738 if (chip->info->ops->port_set_link(chip, port, link))
739 netdev_err(chip->ds->ports[port].netdev,
740 "failed to restore MAC's link\n");
741
742 return err;
743}
744
dea87024
AL		 745/* We expect the switch to perform auto negotiation if there is a real
746 * phy. However, in the case of a fixed link phy, we force the port
747 * settings from the fixed link settings.
748 */
f81ec90f
VD		 749static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
750 struct phy_device *phydev)
dea87024 751{
04bed143 752 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925 753 int err;
dea87024
AL		 754
755 if (!phy_is_pseudo_fixed_link(phydev))
756 return;
757
fad09c73 758 mutex_lock(&chip->reg_lock);
d78343d2
VD		 759 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
760 phydev->duplex, phydev->interface);
fad09c73 761 mutex_unlock(&chip->reg_lock);
d78343d2
VD		 762
763 if (err && err != -EOPNOTSUPP)
764 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
dea87024
AL		 765}
766
fad09c73 767static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8 768{
a935c052
VD		 769 u16 val;
770 int i, err;
91da11f8
LB		 771
772 for (i = 0; i < 10; i++) {
a935c052
VD		 773 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
774 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 775 return 0;
776 }
777
778 return -ETIMEDOUT;
779}
780
fad09c73 781static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 782{
a935c052 783 int err;
91da11f8 784
fad09c73 785 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 786 port = (port + 1) << 5;
787
3675c8d7 788 /* Snapshot the hardware statistics counters for this port. */
a935c052
VD		 789 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
790 GLOBAL_STATS_OP_CAPTURE_PORT |
791 GLOBAL_STATS_OP_HIST_RX_TX | port);
792 if (err)
793 return err;
91da11f8 794
3675c8d7 795 /* Wait for the snapshotting to complete. */
a935c052 796 return _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 797}
798
fad09c73 799static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 800 int stat, u32 *val)
91da11f8 801{
a935c052
VD		 802 u32 value;
803 u16 reg;
804 int err;
91da11f8
LB		 805
806 *val = 0;
807
a935c052
VD		 808 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
809 GLOBAL_STATS_OP_READ_CAPTURED |
810 GLOBAL_STATS_OP_HIST_RX_TX | stat);
811 if (err)
91da11f8
LB		 812 return;
813
a935c052
VD		 814 err = _mv88e6xxx_stats_wait(chip);
815 if (err)
91da11f8
LB		 816 return;
817
a935c052
VD		 818 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
819 if (err)
91da11f8
LB		 820 return;
821
a935c052 822 value = reg << 16;
91da11f8 823
a935c052
VD		 824 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
825 if (err)
91da11f8
LB		 826 return;
827
a935c052 828 *val = value | reg;
91da11f8
LB		 829}
830
e413e7e1 831static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 832 { "in_good_octets", 8, 0x00, BANK0, },
833 { "in_bad_octets", 4, 0x02, BANK0, },
834 { "in_unicast", 4, 0x04, BANK0, },
835 { "in_broadcasts", 4, 0x06, BANK0, },
836 { "in_multicasts", 4, 0x07, BANK0, },
837 { "in_pause", 4, 0x16, BANK0, },
838 { "in_undersize", 4, 0x18, BANK0, },
839 { "in_fragments", 4, 0x19, BANK0, },
840 { "in_oversize", 4, 0x1a, BANK0, },
841 { "in_jabber", 4, 0x1b, BANK0, },
842 { "in_rx_error", 4, 0x1c, BANK0, },
843 { "in_fcs_error", 4, 0x1d, BANK0, },
844 { "out_octets", 8, 0x0e, BANK0, },
845 { "out_unicast", 4, 0x10, BANK0, },
846 { "out_broadcasts", 4, 0x13, BANK0, },
847 { "out_multicasts", 4, 0x12, BANK0, },
848 { "out_pause", 4, 0x15, BANK0, },
849 { "excessive", 4, 0x11, BANK0, },
850 { "collisions", 4, 0x1e, BANK0, },
851 { "deferred", 4, 0x05, BANK0, },
852 { "single", 4, 0x14, BANK0, },
853 { "multiple", 4, 0x17, BANK0, },
854 { "out_fcs_error", 4, 0x03, BANK0, },
855 { "late", 4, 0x1f, BANK0, },
856 { "hist_64bytes", 4, 0x08, BANK0, },
857 { "hist_65_127bytes", 4, 0x09, BANK0, },
858 { "hist_128_255bytes", 4, 0x0a, BANK0, },
859 { "hist_256_511bytes", 4, 0x0b, BANK0, },
860 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
861 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
862 { "sw_in_discards", 4, 0x10, PORT, },
863 { "sw_in_filtered", 2, 0x12, PORT, },
864 { "sw_out_filtered", 2, 0x13, PORT, },
865 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
866 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
867 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
868 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
869 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
870 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
871 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
872 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
873 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
874 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
875 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
876 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
877 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
878 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
879 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
880 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
881 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
882 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
883 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
884 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
885 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
886 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
887 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
888 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
889 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
890 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 891};
892
fad09c73 893static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 894 struct mv88e6xxx_hw_stat *stat)
e413e7e1 895{
f5e2ed02
AL		 896 switch (stat->type) {
897 case BANK0:
e413e7e1 898 return true;
f5e2ed02 899 case BANK1:
fad09c73 900 return mv88e6xxx_6320_family(chip);
f5e2ed02 901 case PORT:
fad09c73
VD		 902 return mv88e6xxx_6095_family(chip) ||
903 mv88e6xxx_6185_family(chip) ||
904 mv88e6xxx_6097_family(chip) ||
905 mv88e6xxx_6165_family(chip) ||
906 mv88e6xxx_6351_family(chip) ||
907 mv88e6xxx_6352_family(chip);
91da11f8 908 }
f5e2ed02 909 return false;
91da11f8
LB		 910}
911
fad09c73 912static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 913 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 914 int port)
915{
80c4627b
AL		 916 u32 low;
917 u32 high = 0;
0e7b9925
AL		 918 int err;
919 u16 reg;
80c4627b
AL		 920 u64 value;
921
f5e2ed02
AL		 922 switch (s->type) {
923 case PORT:
0e7b9925
AL		 924 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
925 if (err)
80c4627b
AL		 926 return UINT64_MAX;
927
0e7b9925 928 low = reg;
80c4627b 929 if (s->sizeof_stat == 4) {
0e7b9925
AL		 930 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
931 if (err)
80c4627b 932 return UINT64_MAX;
0e7b9925 933 high = reg;
80c4627b 934 }
f5e2ed02
AL		 935 break;
936 case BANK0:
937 case BANK1:
fad09c73 938 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 939 if (s->sizeof_stat == 8)
fad09c73 940 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 941 }
942 value = (((u64)high) << 16) | low;
943 return value;
944}
945
f81ec90f
VD		 946static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
947 uint8_t *data)
91da11f8 948{
04bed143 949 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 950 struct mv88e6xxx_hw_stat *stat;
951 int i, j;
91da11f8 952
f5e2ed02
AL		 953 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
954 stat = &mv88e6xxx_hw_stats[i];
fad09c73 955 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 956 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
957 ETH_GSTRING_LEN);
958 j++;
959 }
91da11f8 960 }
e413e7e1
AL		 961}
962
f81ec90f 963static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 964{
04bed143 965 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 966 struct mv88e6xxx_hw_stat *stat;
967 int i, j;
968
969 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
970 stat = &mv88e6xxx_hw_stats[i];
fad09c73 971 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 972 j++;
973 }
974 return j;
e413e7e1
AL		 975}
976
f81ec90f
VD		 977static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
978 uint64_t *data)
e413e7e1 979{
04bed143 980 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 981 struct mv88e6xxx_hw_stat *stat;
982 int ret;
983 int i, j;
984
fad09c73 985 mutex_lock(&chip->reg_lock);
f5e2ed02 986
fad09c73 987 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 988 if (ret < 0) {
fad09c73 989 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 990 return;
991 }
992 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
993 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 994 if (mv88e6xxx_has_stat(chip, stat)) {
995 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 996 j++;
997 }
998 }
999
fad09c73 1000 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 1001}
1002
f81ec90f 1003static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 1004{
1005 return 32 * sizeof(u16);
1006}
1007
f81ec90f
VD		 1008static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1009 struct ethtool_regs *regs, void *_p)
a1ab91f3 1010{
04bed143 1011 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1012 int err;
1013 u16 reg;
a1ab91f3
GR		 1014 u16 *p = _p;
1015 int i;
1016
1017 regs->version = 0;
1018
1019 memset(p, 0xff, 32 * sizeof(u16));
1020
fad09c73 1021 mutex_lock(&chip->reg_lock);
23062513 1022
a1ab91f3 1023 for (i = 0; i < 32; i++) {
a1ab91f3 1024
0e7b9925
AL		 1025 err = mv88e6xxx_port_read(chip, port, i, &reg);
1026 if (!err)
1027 p[i] = reg;
a1ab91f3 1028 }
23062513 1029
fad09c73 1030 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 1031}
1032
fad09c73 1033static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 1034{
a935c052 1035 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1036}
1037
f81ec90f
VD		 1038static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1039 struct ethtool_eee *e)
11b3b45d 1040{
04bed143 1041 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1042 u16 reg;
1043 int err;
11b3b45d 1044
fad09c73 1045 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1046 return -EOPNOTSUPP;
1047
fad09c73 1048 mutex_lock(&chip->reg_lock);
2f40c698 1049
9c93829c
VD		 1050 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1051 if (err)
2f40c698 1052 goto out;
11b3b45d
GR		 1053
1054 e->eee_enabled = !!(reg & 0x0200);
1055 e->tx_lpi_enabled = !!(reg & 0x0100);
1056
0e7b9925 1057 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
9c93829c 1058 if (err)
2f40c698 1059 goto out;
11b3b45d 1060
cca8b133 1061 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1062out:
fad09c73 1063 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 1064
1065 return err;
11b3b45d
GR		 1066}
1067
f81ec90f
VD		 1068static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1069 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 1070{
04bed143 1071 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 1072 u16 reg;
1073 int err;
11b3b45d 1074
fad09c73 1075 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 1076 return -EOPNOTSUPP;
1077
fad09c73 1078 mutex_lock(&chip->reg_lock);
11b3b45d 1079
9c93829c
VD		 1080 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1081 if (err)
2f40c698
AL		 1082 goto out;
1083
9c93829c 1084 reg &= ~0x0300;
2f40c698
AL		 1085 if (e->eee_enabled)
1086 reg |= 0x0200;
1087 if (e->tx_lpi_enabled)
1088 reg |= 0x0100;
1089
9c93829c 1090 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 1091out:
fad09c73 1092 mutex_unlock(&chip->reg_lock);
2f40c698 1093
9c93829c 1094 return err;
11b3b45d
GR		 1095}
1096
fad09c73 1097static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2 1098{
a935c052
VD		 1099 u16 val;
1100 int err;
facd95b2 1101
6dc10bbc 1102 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
a935c052
VD		 1103 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1104 if (err)
1105 return err;
fad09c73 1106 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 1107 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
a935c052
VD		 1108 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1109 if (err)
1110 return err;
11ea809f 1111
a935c052
VD		 1112 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1113 (val & 0xfff) | ((fid << 8) & 0xf000));
1114 if (err)
1115 return err;
11ea809f
VD		 1116
1117 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1118 cmd |= fid & 0xf;
b426e5f7
VD		 1119 }
1120
a935c052
VD		 1121 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1122 if (err)
1123 return err;
facd95b2 1124
fad09c73 1125 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1126}
1127
fad09c73 1128static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1129 struct mv88e6xxx_atu_entry *entry)
1130{
1131 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1132
1133 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1134 unsigned int mask, shift;
1135
1136 if (entry->trunk) {
1137 data |= GLOBAL_ATU_DATA_TRUNK;
1138 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1139 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1140 } else {
1141 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1142 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1143 }
1144
1145 data |= (entry->portv_trunkid << shift) & mask;
1146 }
1147
a935c052 1148 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
37705b73
VD		 1149}
1150
fad09c73 1151static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1152 struct mv88e6xxx_atu_entry *entry,
1153 bool static_too)
facd95b2 1154{
7fb5e755
VD		 1155 int op;
1156 int err;
facd95b2 1157
fad09c73 1158 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1159 if (err)
1160 return err;
facd95b2 1161
fad09c73 1162 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1163 if (err)
1164 return err;
1165
1166 if (entry->fid) {
7fb5e755
VD		 1167 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1168 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1169 } else {
1170 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1171 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1172 }
1173
fad09c73 1174 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1175}
1176
fad09c73 1177static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1178 u16 fid, bool static_too)
7fb5e755
VD		 1179{
1180 struct mv88e6xxx_atu_entry entry = {
1181 .fid = fid,
1182 .state = 0, /* EntryState bits must be 0 */
1183 };
70cc99d1 1184
fad09c73 1185 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1186}
1187
fad09c73 1188static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1189 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1190{
1191 struct mv88e6xxx_atu_entry entry = {
1192 .trunk = false,
1193 .fid = fid,
1194 };
1195
1196 /* EntryState bits must be 0xF */
1197 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1198
1199 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1200 entry.portv_trunkid = (to_port & 0x0f) << 4;
1201 entry.portv_trunkid |= from_port & 0x0f;
1202
fad09c73 1203 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1204}
1205
fad09c73 1206static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1207 int port, bool static_too)
9f4d55d2
VD		 1208{
1209 /* Destination port 0xF means remove the entries */
fad09c73 1210 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1211}
1212
fad09c73 1213static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1214{
fad09c73 1215 struct net_device *bridge = chip->ports[port].bridge_dev;
fad09c73 1216 struct dsa_switch *ds = chip->ds;
b7666efe 1217 u16 output_ports = 0;
b7666efe
VD		 1218 int i;
1219
1220 /* allow CPU port or DSA link(s) to send frames to every port */
1221 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
5a7921f4 1222 output_ports = ~0;
b7666efe 1223 } else {
370b4ffb 1224 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b7666efe 1225 /* allow sending frames to every group member */
fad09c73 1226 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1227 output_ports |= BIT(i);
1228
1229 /* allow sending frames to CPU port and DSA link(s) */
1230 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1231 output_ports |= BIT(i);
1232 }
1233 }
1234
1235 /* prevent frames from going back out of the port they came in on */
1236 output_ports &= ~BIT(port);
facd95b2 1237
5a7921f4 1238 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1239}
1240
f81ec90f
VD		 1241static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1242 u8 state)
facd95b2 1243{
04bed143 1244 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1245 int stp_state;
553eb544 1246 int err;
facd95b2
GR		 1247
1248 switch (state) {
1249 case BR_STATE_DISABLED:
cca8b133 1250 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1251 break;
1252 case BR_STATE_BLOCKING:
1253 case BR_STATE_LISTENING:
cca8b133 1254 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1255 break;
1256 case BR_STATE_LEARNING:
cca8b133 1257 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1258 break;
1259 case BR_STATE_FORWARDING:
1260 default:
cca8b133 1261 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1262 break;
1263 }
1264
fad09c73 1265 mutex_lock(&chip->reg_lock);
e28def33 1266 err = mv88e6xxx_port_set_state(chip, port, stp_state);
fad09c73 1267 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1268
1269 if (err)
e28def33 1270 netdev_err(ds->ports[port].netdev, "failed to update state\n");
facd95b2
GR		 1271}
1272
749efcb8
VD		 1273static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1274{
1275 struct mv88e6xxx_chip *chip = ds->priv;
1276 int err;
1277
1278 mutex_lock(&chip->reg_lock);
1279 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1280 mutex_unlock(&chip->reg_lock);
1281
1282 if (err)
1283 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1284}
1285
fad09c73 1286static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1287{
a935c052 1288 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1289}
1290
fad09c73 1291static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864 1292{
a935c052 1293 int err;
6b17e864 1294
a935c052
VD		 1295 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1296 if (err)
1297 return err;
6b17e864 1298
fad09c73 1299 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1300}
1301
fad09c73 1302static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1303{
1304 int ret;
1305
fad09c73 1306 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1307 if (ret < 0)
1308 return ret;
1309
fad09c73 1310 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1311}
1312
fad09c73 1313static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1314 struct mv88e6xxx_vtu_entry *entry,
b8fee957
VD		 1315 unsigned int nibble_offset)
1316{
b8fee957 1317 u16 regs[3];
a935c052 1318 int i, err;
b8fee957
VD		 1319
1320 for (i = 0; i < 3; ++i) {
a935c052 1321 u16 *reg = &regs[i];
b8fee957 1322
a935c052
VD		 1323 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1324 if (err)
1325 return err;
b8fee957
VD		 1326 }
1327
370b4ffb 1328 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b8fee957
VD		 1329 unsigned int shift = (i % 4) * 4 + nibble_offset;
1330 u16 reg = regs[i / 4];
1331
1332 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1333 }
1334
1335 return 0;
1336}
1337
fad09c73 1338static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1339 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1340{
fad09c73 1341 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1342}
1343
fad09c73 1344static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
b4e47c0f 1345 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1346{
fad09c73 1347 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1348}
1349
fad09c73 1350static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1351 struct mv88e6xxx_vtu_entry *entry,
7dad08d7
VD		 1352 unsigned int nibble_offset)
1353{
7dad08d7 1354 u16 regs[3] = { 0 };
a935c052 1355 int i, err;
7dad08d7 1356
370b4ffb 1357 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7dad08d7
VD		 1358 unsigned int shift = (i % 4) * 4 + nibble_offset;
1359 u8 data = entry->data[i];
1360
1361 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1362 }
1363
1364 for (i = 0; i < 3; ++i) {
a935c052
VD		 1365 u16 reg = regs[i];
1366
1367 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1368 if (err)
1369 return err;
7dad08d7
VD		 1370 }
1371
1372 return 0;
1373}
1374
fad09c73 1375static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1376 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1377{
fad09c73 1378 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1379}
1380
fad09c73 1381static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
b4e47c0f 1382 struct mv88e6xxx_vtu_entry *entry)
15d7d7d4 1383{
fad09c73 1384 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1385}
1386
fad09c73 1387static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1388{
a935c052
VD		 1389 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1390 vid & GLOBAL_VTU_VID_MASK);
36d04ba1
VD		 1391}
1392
fad09c73 1393static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b4e47c0f 1394 struct mv88e6xxx_vtu_entry *entry)
b8fee957 1395{
b4e47c0f 1396 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1397 u16 val;
1398 int err;
b8fee957 1399
a935c052
VD		 1400 err = _mv88e6xxx_vtu_wait(chip);
1401 if (err)
1402 return err;
b8fee957 1403
a935c052
VD		 1404 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1405 if (err)
1406 return err;
b8fee957 1407
a935c052
VD		 1408 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1409 if (err)
1410 return err;
b8fee957 1411
a935c052
VD		 1412 next.vid = val & GLOBAL_VTU_VID_MASK;
1413 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
b8fee957
VD		 1414
1415 if (next.valid) {
a935c052
VD		 1416 err = mv88e6xxx_vtu_data_read(chip, &next);
1417 if (err)
1418 return err;
b8fee957 1419
6dc10bbc 1420 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
a935c052
VD		 1421 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1422 if (err)
1423 return err;
b8fee957 1424
a935c052 1425 next.fid = val & GLOBAL_VTU_FID_MASK;
fad09c73 1426 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1427 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1428 * VTU DBNum[3:0] are located in VTU Operation 3:0
1429 */
a935c052
VD		 1430 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1431 if (err)
1432 return err;
11ea809f 1433
a935c052
VD		 1434 next.fid = (val & 0xf00) >> 4;
1435 next.fid |= val & 0xf;
2e7bd5ef 1436 }
b8fee957 1437
fad09c73 1438 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
a935c052
VD		 1439 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1440 if (err)
1441 return err;
b8fee957 1442
a935c052 1443 next.sid = val & GLOBAL_VTU_SID_MASK;
b8fee957
VD		 1444 }
1445 }
1446
1447 *entry = next;
1448 return 0;
1449}
1450
f81ec90f
VD		 1451static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1452 struct switchdev_obj_port_vlan *vlan,
1453 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1454{
04bed143 1455 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1456 struct mv88e6xxx_vtu_entry next;
ceff5eff
VD		 1457 u16 pvid;
1458 int err;
1459
fad09c73 1460 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1461 return -EOPNOTSUPP;
1462
fad09c73 1463 mutex_lock(&chip->reg_lock);
ceff5eff 1464
77064f37 1465 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
ceff5eff
VD		 1466 if (err)
1467 goto unlock;
1468
fad09c73 1469 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1470 if (err)
1471 goto unlock;
1472
1473 do {
fad09c73 1474 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1475 if (err)
1476 break;
1477
1478 if (!next.valid)
1479 break;
1480
1481 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1482 continue;
1483
1484 /* reinit and dump this VLAN obj */
57d32310
VD		 1485 vlan->vid_begin = next.vid;
1486 vlan->vid_end = next.vid;
ceff5eff
VD		 1487 vlan->flags = 0;
1488
1489 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1490 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1491
1492 if (next.vid == pvid)
1493 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1494
1495 err = cb(&vlan->obj);
1496 if (err)
1497 break;
1498 } while (next.vid < GLOBAL_VTU_VID_MASK);
1499
1500unlock:
fad09c73 1501 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1502
1503 return err;
1504}
1505
fad09c73 1506static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1507 struct mv88e6xxx_vtu_entry *entry)
7dad08d7 1508{
11ea809f 1509 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7 1510 u16 reg = 0;
a935c052 1511 int err;
7dad08d7 1512
a935c052
VD		 1513 err = _mv88e6xxx_vtu_wait(chip);
1514 if (err)
1515 return err;
7dad08d7
VD		 1516
1517 if (!entry->valid)
1518 goto loadpurge;
1519
1520 /* Write port member tags */
a935c052
VD		 1521 err = mv88e6xxx_vtu_data_write(chip, entry);
1522 if (err)
1523 return err;
7dad08d7 1524
fad09c73 1525 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1526 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1527 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1528 if (err)
1529 return err;
b426e5f7 1530 }
7dad08d7 1531
6dc10bbc 1532 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
7dad08d7 1533 reg = entry->fid & GLOBAL_VTU_FID_MASK;
a935c052
VD		 1534 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1535 if (err)
1536 return err;
fad09c73 1537 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1538 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1539 * VTU DBNum[3:0] are located in VTU Operation 3:0
1540 */
1541 op |= (entry->fid & 0xf0) << 8;
1542 op |= entry->fid & 0xf;
7dad08d7
VD		 1543 }
1544
1545 reg = GLOBAL_VTU_VID_VALID;
1546loadpurge:
1547 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
a935c052
VD		 1548 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1549 if (err)
1550 return err;
7dad08d7 1551
fad09c73 1552 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1553}
1554
fad09c73 1555static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
b4e47c0f 1556 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1557{
b4e47c0f 1558 struct mv88e6xxx_vtu_entry next = { 0 };
a935c052
VD		 1559 u16 val;
1560 int err;
0d3b33e6 1561
a935c052
VD		 1562 err = _mv88e6xxx_vtu_wait(chip);
1563 if (err)
1564 return err;
0d3b33e6 1565
a935c052
VD		 1566 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1567 sid & GLOBAL_VTU_SID_MASK);
1568 if (err)
1569 return err;
0d3b33e6 1570
a935c052
VD		 1571 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1572 if (err)
1573 return err;
0d3b33e6 1574
a935c052
VD		 1575 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1576 if (err)
1577 return err;
0d3b33e6 1578
a935c052 1579 next.sid = val & GLOBAL_VTU_SID_MASK;
0d3b33e6 1580
a935c052
VD		 1581 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1582 if (err)
1583 return err;
0d3b33e6 1584
a935c052 1585 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
0d3b33e6
VD		 1586
1587 if (next.valid) {
a935c052
VD		 1588 err = mv88e6xxx_stu_data_read(chip, &next);
1589 if (err)
1590 return err;
0d3b33e6
VD		 1591 }
1592
1593 *entry = next;
1594 return 0;
1595}
1596
fad09c73 1597static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
b4e47c0f 1598 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6
VD		 1599{
1600 u16 reg = 0;
a935c052 1601 int err;
0d3b33e6 1602
a935c052
VD		 1603 err = _mv88e6xxx_vtu_wait(chip);
1604 if (err)
1605 return err;
0d3b33e6
VD		 1606
1607 if (!entry->valid)
1608 goto loadpurge;
1609
1610 /* Write port states */
a935c052
VD		 1611 err = mv88e6xxx_stu_data_write(chip, entry);
1612 if (err)
1613 return err;
0d3b33e6
VD		 1614
1615 reg = GLOBAL_VTU_VID_VALID;
1616loadpurge:
a935c052
VD		 1617 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1618 if (err)
1619 return err;
0d3b33e6
VD		 1620
1621 reg = entry->sid & GLOBAL_VTU_SID_MASK;
a935c052
VD		 1622 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1623 if (err)
1624 return err;
0d3b33e6 1625
fad09c73 1626 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1627}
1628
fad09c73 1629static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1630{
1631 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
b4e47c0f 1632 struct mv88e6xxx_vtu_entry vlan;
2db9ce1f 1633 int i, err;
3285f9e8
VD		 1634
1635 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1636
2db9ce1f 1637 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1638 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
b4e48c50 1639 err = mv88e6xxx_port_get_fid(chip, i, fid);
2db9ce1f
VD		 1640 if (err)
1641 return err;
1642
1643 set_bit(*fid, fid_bitmap);
1644 }
1645
3285f9e8 1646 /* Set every FID bit used by the VLAN entries */
fad09c73 1647 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1648 if (err)
1649 return err;
1650
1651 do {
fad09c73 1652 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1653 if (err)
1654 return err;
1655
1656 if (!vlan.valid)
1657 break;
1658
1659 set_bit(vlan.fid, fid_bitmap);
1660 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1661
1662 /* The reset value 0x000 is used to indicate that multiple address
1663 * databases are not needed. Return the next positive available.
1664 */
1665 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1666 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1667 return -ENOSPC;
1668
1669 /* Clear the database */
fad09c73 1670 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1671}
1672
fad09c73 1673static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1674 struct mv88e6xxx_vtu_entry *entry)
0d3b33e6 1675{
fad09c73 1676 struct dsa_switch *ds = chip->ds;
b4e47c0f 1677 struct mv88e6xxx_vtu_entry vlan = {
0d3b33e6
VD		 1678 .valid = true,
1679 .vid = vid,
1680 };
3285f9e8
VD		 1681 int i, err;
1682
fad09c73 1683 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1684 if (err)
1685 return err;
0d3b33e6 1686
3d131f07 1687 /* exclude all ports except the CPU and DSA ports */
370b4ffb 1688 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
3d131f07
VD		 1689 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1690 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1691 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1692
fad09c73
VD		 1693 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1694 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
b4e47c0f 1695 struct mv88e6xxx_vtu_entry vstp;
0d3b33e6
VD		 1696
1697 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1698 * implemented, only one STU entry is needed to cover all VTU
1699 * entries. Thus, validate the SID 0.
1700 */
1701 vlan.sid = 0;
fad09c73 1702 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1703 if (err)
1704 return err;
1705
1706 if (vstp.sid != vlan.sid || !vstp.valid) {
1707 memset(&vstp, 0, sizeof(vstp));
1708 vstp.valid = true;
1709 vstp.sid = vlan.sid;
1710
fad09c73 1711 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1712 if (err)
1713 return err;
1714 }
0d3b33e6
VD		 1715 }
1716
1717 *entry = vlan;
1718 return 0;
1719}
1720
fad09c73 1721static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
b4e47c0f 1722 struct mv88e6xxx_vtu_entry *entry, bool creat)
2fb5ef09
VD		 1723{
1724 int err;
1725
1726 if (!vid)
1727 return -EINVAL;
1728
fad09c73 1729 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1730 if (err)
1731 return err;
1732
fad09c73 1733 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1734 if (err)
1735 return err;
1736
1737 if (entry->vid != vid || !entry->valid) {
1738 if (!creat)
1739 return -EOPNOTSUPP;
1740 /* -ENOENT would've been more appropriate, but switchdev expects
1741 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1742 */
1743
fad09c73 1744 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1745 }
1746
1747 return err;
1748}
1749
da9c359e
VD		 1750static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1751 u16 vid_begin, u16 vid_end)
1752{
04bed143 1753 struct mv88e6xxx_chip *chip = ds->priv;
b4e47c0f 1754 struct mv88e6xxx_vtu_entry vlan;
da9c359e
VD		 1755 int i, err;
1756
1757 if (!vid_begin)
1758 return -EOPNOTSUPP;
1759
fad09c73 1760 mutex_lock(&chip->reg_lock);
da9c359e 1761
fad09c73 1762 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1763 if (err)
1764 goto unlock;
1765
1766 do {
fad09c73 1767 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1768 if (err)
1769 goto unlock;
1770
1771 if (!vlan.valid)
1772 break;
1773
1774 if (vlan.vid > vid_end)
1775 break;
1776
370b4ffb 1777 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
da9c359e
VD		 1778 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1779 continue;
1780
1781 if (vlan.data[i] ==
1782 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1783 continue;
1784
fad09c73
VD		 1785 if (chip->ports[i].bridge_dev ==
1786 chip->ports[port].bridge_dev)
da9c359e
VD		 1787 break; /* same bridge, check next VLAN */
1788
c8b09808 1789 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1790 "hardware VLAN %d already used by %s\n",
1791 vlan.vid,
fad09c73 1792 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1793 err = -EOPNOTSUPP;
1794 goto unlock;
1795 }
1796 } while (vlan.vid < vid_end);
1797
1798unlock:
fad09c73 1799 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1800
1801 return err;
1802}
1803
f81ec90f
VD		 1804static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1805 bool vlan_filtering)
214cdb99 1806{
04bed143 1807 struct mv88e6xxx_chip *chip = ds->priv;
385a0995 1808 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
214cdb99 1809 PORT_CONTROL_2_8021Q_DISABLED;
0e7b9925 1810 int err;
214cdb99 1811
fad09c73 1812 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1813 return -EOPNOTSUPP;
1814
fad09c73 1815 mutex_lock(&chip->reg_lock);
385a0995 1816 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
fad09c73 1817 mutex_unlock(&chip->reg_lock);
214cdb99 1818
0e7b9925 1819 return err;
214cdb99
VD		 1820}
1821
57d32310
VD		 1822static int
1823mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1824 const struct switchdev_obj_port_vlan *vlan,
1825 struct switchdev_trans *trans)
76e398a6 1826{
04bed143 1827 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1828 int err;
1829
fad09c73 1830 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1831 return -EOPNOTSUPP;
1832
da9c359e
VD		 1833 /* If the requested port doesn't belong to the same bridge as the VLAN
1834 * members, do not support it (yet) and fallback to software VLAN.
1835 */
1836 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1837 vlan->vid_end);
1838 if (err)
1839 return err;
1840
76e398a6
VD		 1841 /* We don't need any dynamic resource from the kernel (yet),
1842 * so skip the prepare phase.
1843 */
1844 return 0;
1845}
1846
fad09c73 1847static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1848 u16 vid, bool untagged)
0d3b33e6 1849{
b4e47c0f 1850 struct mv88e6xxx_vtu_entry vlan;
0d3b33e6
VD		 1851 int err;
1852
fad09c73 1853 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1854 if (err)
76e398a6 1855 return err;
0d3b33e6 1856
0d3b33e6
VD		 1857 vlan.data[port] = untagged ?
1858 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1859 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1860
fad09c73 1861 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1862}
1863
f81ec90f
VD		 1864static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1865 const struct switchdev_obj_port_vlan *vlan,
1866 struct switchdev_trans *trans)
76e398a6 1867{
04bed143 1868 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1869 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1870 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1871 u16 vid;
76e398a6 1872
fad09c73 1873 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1874 return;
1875
fad09c73 1876 mutex_lock(&chip->reg_lock);
76e398a6 1877
4d5770b3 1878 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1879 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1880 netdev_err(ds->ports[port].netdev,
1881 "failed to add VLAN %d%c\n",
4d5770b3 1882 vid, untagged ? 'u' : 't');
76e398a6 1883
77064f37 1884 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
c8b09808 1885 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1886 vlan->vid_end);
0d3b33e6 1887
fad09c73 1888 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1889}
1890
fad09c73 1891static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1892 int port, u16 vid)
7dad08d7 1893{
fad09c73 1894 struct dsa_switch *ds = chip->ds;
b4e47c0f 1895 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 1896 int i, err;
1897
fad09c73 1898 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1899 if (err)
76e398a6 1900 return err;
7dad08d7 1901
2fb5ef09
VD		 1902 /* Tell switchdev if this VLAN is handled in software */
1903 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1904 return -EOPNOTSUPP;
7dad08d7
VD		 1905
1906 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1907
1908 /* keep the VLAN unless all ports are excluded */
f02bdffc 1909 vlan.valid = false;
370b4ffb 1910 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
3d131f07 1911 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1912 continue;
1913
1914 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1915 vlan.valid = true;
7dad08d7
VD		 1916 break;
1917 }
1918 }
1919
fad09c73 1920 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1921 if (err)
1922 return err;
1923
fad09c73 1924 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1925}
1926
f81ec90f
VD		 1927static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1928 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1929{
04bed143 1930 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1931 u16 pvid, vid;
1932 int err = 0;
1933
fad09c73 1934 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1935 return -EOPNOTSUPP;
1936
fad09c73 1937 mutex_lock(&chip->reg_lock);
76e398a6 1938
77064f37 1939 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 1940 if (err)
1941 goto unlock;
1942
76e398a6 1943 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1944 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1945 if (err)
1946 goto unlock;
1947
1948 if (vid == pvid) {
77064f37 1949 err = mv88e6xxx_port_set_pvid(chip, port, 0);
76e398a6
VD		 1950 if (err)
1951 goto unlock;
1952 }
1953 }
1954
7dad08d7 1955unlock:
fad09c73 1956 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 1957
1958 return err;
1959}
1960
fad09c73 1961static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 1962 const unsigned char *addr)
defb05b9 1963{
a935c052 1964 int i, err;
defb05b9
GR		 1965
1966 for (i = 0; i < 3; i++) {
a935c052
VD		 1967 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
1968 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1969 if (err)
1970 return err;
defb05b9
GR		 1971 }
1972
1973 return 0;
1974}
1975
fad09c73 1976static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 1977 unsigned char *addr)
defb05b9 1978{
a935c052
VD		 1979 u16 val;
1980 int i, err;
defb05b9
GR		 1981
1982 for (i = 0; i < 3; i++) {
a935c052
VD		 1983 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
1984 if (err)
1985 return err;
1986
1987 addr[i * 2] = val >> 8;
1988 addr[i * 2 + 1] = val & 0xff;
defb05b9
GR		 1989 }
1990
1991 return 0;
1992}
1993
fad09c73 1994static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 1995 struct mv88e6xxx_atu_entry *entry)
defb05b9 1996{
6630e236
VD		 1997 int ret;
1998
fad09c73 1999 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2000 if (ret < 0)
2001 return ret;
2002
fad09c73 2003 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2004 if (ret < 0)
2005 return ret;
2006
fad09c73 2007 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2008 if (ret < 0)
87820510
VD		 2009 return ret;
2010
fad09c73 2011 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2012}
87820510 2013
88472939
VD		 2014static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2015 struct mv88e6xxx_atu_entry *entry);
2016
2017static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2018 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2019{
2020 struct mv88e6xxx_atu_entry next;
2021 int err;
2022
2023 eth_broadcast_addr(next.mac);
2024
2025 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2026 if (err)
2027 return err;
2028
2029 do {
2030 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2031 if (err)
2032 return err;
2033
2034 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2035 break;
2036
2037 if (ether_addr_equal(next.mac, addr)) {
2038 *entry = next;
2039 return 0;
2040 }
2041 } while (!is_broadcast_ether_addr(next.mac));
2042
2043 memset(entry, 0, sizeof(*entry));
2044 entry->fid = fid;
2045 ether_addr_copy(entry->mac, addr);
2046
2047 return 0;
2048}
2049
83dabd1f
VD		 2050static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2051 const unsigned char *addr, u16 vid,
2052 u8 state)
fd231c82 2053{
b4e47c0f 2054 struct mv88e6xxx_vtu_entry vlan;
88472939 2055 struct mv88e6xxx_atu_entry entry;
3285f9e8
VD		 2056 int err;
2057
2db9ce1f
VD		 2058 /* Null VLAN ID corresponds to the port private database */
2059 if (vid == 0)
b4e48c50 2060 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2db9ce1f 2061 else
fad09c73 2062 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2063 if (err)
2064 return err;
fd231c82 2065
88472939
VD		 2066 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2067 if (err)
2068 return err;
2069
2070 /* Purge the ATU entry only if no port is using it anymore */
2071 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2072 entry.portv_trunkid &= ~BIT(port);
2073 if (!entry.portv_trunkid)
2074 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2075 } else {
2076 entry.portv_trunkid |= BIT(port);
2077 entry.state = state;
fd231c82
VD		 2078 }
2079
fad09c73 2080 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2081}
2082
f81ec90f
VD		 2083static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2084 const struct switchdev_obj_port_fdb *fdb,
2085 struct switchdev_trans *trans)
146a3206
VD		 2086{
2087 /* We don't need any dynamic resource from the kernel (yet),
2088 * so skip the prepare phase.
2089 */
2090 return 0;
2091}
2092
f81ec90f
VD		 2093static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2094 const struct switchdev_obj_port_fdb *fdb,
2095 struct switchdev_trans *trans)
87820510 2096{
04bed143 2097 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2098
fad09c73 2099 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2100 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2101 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2102 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2103 mutex_unlock(&chip->reg_lock);
87820510
VD		 2104}
2105
f81ec90f
VD		 2106static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2107 const struct switchdev_obj_port_fdb *fdb)
87820510 2108{
04bed143 2109 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2110 int err;
87820510 2111
fad09c73 2112 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2113 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2114 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2115 mutex_unlock(&chip->reg_lock);
87820510 2116
83dabd1f 2117 return err;
87820510
VD		 2118}
2119
fad09c73 2120static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2121 struct mv88e6xxx_atu_entry *entry)
6630e236 2122{
1d194046 2123 struct mv88e6xxx_atu_entry next = { 0 };
a935c052
VD		 2124 u16 val;
2125 int err;
1d194046
VD		 2126
2127 next.fid = fid;
defb05b9 2128
a935c052
VD		 2129 err = _mv88e6xxx_atu_wait(chip);
2130 if (err)
2131 return err;
6630e236 2132
a935c052
VD		 2133 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2134 if (err)
2135 return err;
6630e236 2136
a935c052
VD		 2137 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2138 if (err)
2139 return err;
6630e236 2140
a935c052
VD		 2141 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2142 if (err)
2143 return err;
6630e236 2144
a935c052 2145 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
1d194046
VD		 2146 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2147 unsigned int mask, shift;
2148
a935c052 2149 if (val & GLOBAL_ATU_DATA_TRUNK) {
1d194046
VD		 2150 next.trunk = true;
2151 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2152 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2153 } else {
2154 next.trunk = false;
2155 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2156 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2157 }
2158
a935c052 2159 next.portv_trunkid = (val & mask) >> shift;
1d194046 2160 }
cdf09697 2161
1d194046 2162 *entry = next;
cdf09697
DM		 2163 return 0;
2164}
2165
83dabd1f
VD		 2166static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2167 u16 fid, u16 vid, int port,
2168 struct switchdev_obj *obj,
2169 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2170{
2171 struct mv88e6xxx_atu_entry addr = {
2172 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2173 };
2174 int err;
2175
fad09c73 2176 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2177 if (err)
2178 return err;
2179
2180 do {
fad09c73 2181 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2182 if (err)
83dabd1f 2183 return err;
74b6ba0d
VD		 2184
2185 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2186 break;
2187
83dabd1f
VD		 2188 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2189 continue;
2190
2191 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2192 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2193
83dabd1f
VD		 2194 if (!is_unicast_ether_addr(addr.mac))
2195 continue;
2196
2197 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2198 fdb->vid = vid;
2199 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2200 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2201 fdb->ndm_state = NUD_NOARP;
2202 else
2203 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2204 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2205 struct switchdev_obj_port_mdb *mdb;
2206
2207 if (!is_multicast_ether_addr(addr.mac))
2208 continue;
2209
2210 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2211 mdb->vid = vid;
2212 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2213 } else {
2214 return -EOPNOTSUPP;
74b6ba0d 2215 }
83dabd1f
VD		 2216
2217 err = cb(obj);
2218 if (err)
2219 return err;
74b6ba0d
VD		 2220 } while (!is_broadcast_ether_addr(addr.mac));
2221
2222 return err;
2223}
2224
83dabd1f
VD		 2225static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2226 struct switchdev_obj *obj,
2227 int (*cb)(struct switchdev_obj *obj))
f33475bd 2228{
b4e47c0f 2229 struct mv88e6xxx_vtu_entry vlan = {
f33475bd
VD		 2230 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2231 };
2db9ce1f 2232 u16 fid;
f33475bd
VD		 2233 int err;
2234
2db9ce1f 2235 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2236 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2237 if (err)
83dabd1f 2238 return err;
2db9ce1f 2239
83dabd1f 2240 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2241 if (err)
83dabd1f 2242 return err;
2db9ce1f 2243
74b6ba0d 2244 /* Dump VLANs' Filtering Information Databases */
fad09c73 2245 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2246 if (err)
83dabd1f 2247 return err;
f33475bd
VD		 2248
2249 do {
fad09c73 2250 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2251 if (err)
83dabd1f 2252 return err;
f33475bd
VD		 2253
2254 if (!vlan.valid)
2255 break;
2256
83dabd1f
VD		 2257 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2258 obj, cb);
f33475bd 2259 if (err)
83dabd1f 2260 return err;
f33475bd
VD		 2261 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2262
83dabd1f
VD		 2263 return err;
2264}
2265
2266static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2267 struct switchdev_obj_port_fdb *fdb,
2268 int (*cb)(struct switchdev_obj *obj))
2269{
04bed143 2270 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2271 int err;
2272
2273 mutex_lock(&chip->reg_lock);
2274 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2275 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2276
2277 return err;
2278}
2279
f81ec90f
VD		 2280static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2281 struct net_device *bridge)
e79a8bcb 2282{
04bed143 2283 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2284 int i, err = 0;
466dfa07 2285
fad09c73 2286 mutex_lock(&chip->reg_lock);
466dfa07 2287
b7666efe 2288 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2289 chip->ports[port].bridge_dev = bridge;
b7666efe 2290
370b4ffb 2291 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
fad09c73
VD		 2292 if (chip->ports[i].bridge_dev == bridge) {
2293 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2294 if (err)
2295 break;
2296 }
2297 }
2298
fad09c73 2299 mutex_unlock(&chip->reg_lock);
a6692754 2300
466dfa07 2301 return err;
e79a8bcb
VD		 2302}
2303
f81ec90f 2304static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2305{
04bed143 2306 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2307 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2308 int i;
466dfa07 2309
fad09c73 2310 mutex_lock(&chip->reg_lock);
466dfa07 2311
b7666efe 2312 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2313 chip->ports[port].bridge_dev = NULL;
b7666efe 2314
370b4ffb 2315 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
fad09c73
VD		 2316 if (i == port || chip->ports[i].bridge_dev == bridge)
2317 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2318 netdev_warn(ds->ports[i].netdev,
2319 "failed to remap\n");
b7666efe 2320
fad09c73 2321 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2322}
2323
fad09c73 2324static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2325{
fad09c73 2326 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2327 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2328 struct gpio_desc *gpiod = chip->reset;
552238b5 2329 unsigned long timeout;
0e7b9925 2330 u16 reg;
a935c052 2331 int err;
552238b5
VD		 2332 int i;
2333
2334 /* Set all ports to the disabled state. */
370b4ffb 2335 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
e28def33
VD		 2336 err = mv88e6xxx_port_set_state(chip, i,
2337 PORT_CONTROL_STATE_DISABLED);
0e7b9925
AL		 2338 if (err)
2339 return err;
552238b5
VD		 2340 }
2341
2342 /* Wait for transmit queues to drain. */
2343 usleep_range(2000, 4000);
2344
2345 /* If there is a gpio connected to the reset pin, toggle it */
2346 if (gpiod) {
2347 gpiod_set_value_cansleep(gpiod, 1);
2348 usleep_range(10000, 20000);
2349 gpiod_set_value_cansleep(gpiod, 0);
2350 usleep_range(10000, 20000);
2351 }
2352
2353 /* Reset the switch. Keep the PPU active if requested. The PPU
2354 * needs to be active to support indirect phy register access
2355 * through global registers 0x18 and 0x19.
2356 */
2357 if (ppu_active)
a935c052 2358 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
552238b5 2359 else
a935c052 2360 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
0e7b9925
AL		 2361 if (err)
2362 return err;
552238b5
VD		 2363
2364 /* Wait up to one second for reset to complete. */
2365 timeout = jiffies + 1 * HZ;
2366 while (time_before(jiffies, timeout)) {
a935c052
VD		 2367 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2368 if (err)
2369 return err;
552238b5 2370
a935c052 2371 if ((reg & is_reset) == is_reset)
552238b5
VD		 2372 break;
2373 usleep_range(1000, 2000);
2374 }
2375 if (time_after(jiffies, timeout))
0e7b9925 2376 err = -ETIMEDOUT;
552238b5 2377 else
0e7b9925 2378 err = 0;
552238b5 2379
0e7b9925 2380 return err;
552238b5
VD		 2381}
2382
09cb7dfd 2383static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2384{
09cb7dfd
VD		 2385 u16 val;
2386 int err;
13a7ebb3 2387
09cb7dfd
VD		 2388 /* Clear Power Down bit */
2389 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2390 if (err)
2391 return err;
13a7ebb3 2392
09cb7dfd
VD		 2393 if (val & BMCR_PDOWN) {
2394 val &= ~BMCR_PDOWN;
2395 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2396 }
2397
09cb7dfd 2398 return err;
13a7ebb3
PU		 2399}
2400
fad09c73 2401static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2402{
fad09c73 2403 struct dsa_switch *ds = chip->ds;
0e7b9925 2404 int err;
54d792f2 2405 u16 reg;
d827e88a 2406
d78343d2
VD		 2407 /* MAC Forcing register: don't force link, speed, duplex or flow control
2408 * state to any particular values on physical ports, but force the CPU
2409 * port and all DSA ports to their maximum bandwidth and full duplex.
2410 */
2411 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2412 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2413 SPEED_MAX, DUPLEX_FULL,
2414 PHY_INTERFACE_MODE_NA);
2415 else
2416 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2417 SPEED_UNFORCED, DUPLEX_UNFORCED,
2418 PHY_INTERFACE_MODE_NA);
2419 if (err)
2420 return err;
54d792f2
AL		 2421
2422 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2423 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2424 * tunneling, determine priority by looking at 802.1p and IP
2425 * priority fields (IP prio has precedence), and set STP state
2426 * to Forwarding.
2427 *
2428 * If this is the CPU link, use DSA or EDSA tagging depending
2429 * on which tagging mode was configured.
2430 *
2431 * If this is a link to another switch, use DSA tagging mode.
2432 *
2433 * If this is the upstream port for this switch, enable
2434 * forwarding of unknown unicasts and multicasts.
2435 */
2436 reg = 0;
fad09c73
VD		 2437 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2438 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2439 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2440 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2441 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2442 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2443 PORT_CONTROL_STATE_FORWARDING;
2444 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2445 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2446 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2447 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2448 else
2449 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2450 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2451 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2452 }
6083ce71 2453 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2454 if (mv88e6xxx_6095_family(chip) ||
2455 mv88e6xxx_6185_family(chip))
6083ce71 2456 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2457 if (mv88e6xxx_6352_family(chip) ||
2458 mv88e6xxx_6351_family(chip) ||
2459 mv88e6xxx_6165_family(chip) ||
2460 mv88e6xxx_6097_family(chip) ||
2461 mv88e6xxx_6320_family(chip)) {
54d792f2 2462 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2463 }
2464
54d792f2
AL		 2465 if (port == dsa_upstream_port(ds))
2466 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2467 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2468 }
2469 if (reg) {
0e7b9925
AL		 2470 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2471 if (err)
2472 return err;
54d792f2
AL		 2473 }
2474
13a7ebb3
PU		 2475 /* If this port is connected to a SerDes, make sure the SerDes is not
2476 * powered down.
2477 */
09cb7dfd 2478 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
0e7b9925
AL		 2479 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2480 if (err)
2481 return err;
2482 reg &= PORT_STATUS_CMODE_MASK;
2483 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2484 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2485 (reg == PORT_STATUS_CMODE_SGMII)) {
2486 err = mv88e6xxx_serdes_power_on(chip);
2487 if (err < 0)
2488 return err;
13a7ebb3
PU		 2489 }
2490 }
2491
8efdda4a 2492 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2493 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2494 * untagged frames on this port, do a destination address lookup on all
2495 * received packets as usual, disable ARP mirroring and don't send a
2496 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2497 */
2498 reg = 0;
fad09c73
VD		 2499 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2500 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2501 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2502 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2503 reg = PORT_CONTROL_2_MAP_DA;
2504
fad09c73
VD		 2505 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2506 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2507 reg |= PORT_CONTROL_2_JUMBO_10240;
2508
fad09c73 2509 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2510 /* Set the upstream port this port should use */
2511 reg |= dsa_upstream_port(ds);
2512 /* enable forwarding of unknown multicast addresses to
2513 * the upstream port
2514 */
2515 if (port == dsa_upstream_port(ds))
2516 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2517 }
2518
46fbe5e5 2519 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2520
54d792f2 2521 if (reg) {
0e7b9925
AL		 2522 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2523 if (err)
2524 return err;
54d792f2
AL		 2525 }
2526
2527 /* Port Association Vector: when learning source addresses
2528 * of packets, add the address to the address database using
2529 * a port bitmap that has only the bit for this port set and
2530 * the other bits clear.
2531 */
4c7ea3c0 2532 reg = 1 << port;
996ecb82
VD		 2533 /* Disable learning for CPU port */
2534 if (dsa_is_cpu_port(ds, port))
65fa4027 2535 reg = 0;
4c7ea3c0 2536
0e7b9925
AL		 2537 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2538 if (err)
2539 return err;
54d792f2
AL		 2540
2541 /* Egress rate control 2: disable egress rate control. */
0e7b9925
AL		 2542 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2543 if (err)
2544 return err;
54d792f2 2545
fad09c73
VD		 2546 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2547 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2548 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2549 /* Do not limit the period of time that this port can
2550 * be paused for by the remote end or the period of
2551 * time that this port can pause the remote end.
2552 */
0e7b9925
AL		 2553 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2554 if (err)
2555 return err;
54d792f2
AL		 2556
2557 /* Port ATU control: disable limiting the number of
2558 * address database entries that this port is allowed
2559 * to use.
2560 */
0e7b9925
AL		 2561 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2562 0x0000);
54d792f2
AL		 2563 /* Priority Override: disable DA, SA and VTU priority
2564 * override.
2565 */
0e7b9925
AL		 2566 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2567 0x0000);
2568 if (err)
2569 return err;
54d792f2
AL		 2570
2571 /* Port Ethertype: use the Ethertype DSA Ethertype
2572 * value.
2573 */
2bbb33be 2574 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
0e7b9925
AL		 2575 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2576 ETH_P_EDSA);
2577 if (err)
2578 return err;
2bbb33be
AL		 2579 }
2580
54d792f2
AL		 2581 /* Tag Remap: use an identity 802.1p prio -> switch
2582 * prio mapping.
2583 */
0e7b9925
AL		 2584 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2585 0x3210);
2586 if (err)
2587 return err;
54d792f2
AL		 2588
2589 /* Tag Remap 2: use an identity 802.1p prio -> switch
2590 * prio mapping.
2591 */
0e7b9925
AL		 2592 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2593 0x7654);
2594 if (err)
2595 return err;
54d792f2
AL		 2596 }
2597
1bc261fa 2598 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2599 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2600 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2601 mv88e6xxx_6320_family(chip)) {
0e7b9925
AL		 2602 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2603 0x0001);
2604 if (err)
2605 return err;
1bc261fa 2606 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
0e7b9925
AL		 2607 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2608 0x0000);
2609 if (err)
2610 return err;
54d792f2
AL		 2611 }
2612
366f0a0f
GR		 2613 /* Port Control 1: disable trunking, disable sending
2614 * learning messages to this port.
d827e88a 2615 */
0e7b9925
AL		 2616 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2617 if (err)
2618 return err;
d827e88a 2619
207afda1 2620 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2621 * database, and allow bidirectional communication between the
2622 * CPU and DSA port(s), and the other ports.
d827e88a 2623 */
b4e48c50 2624 err = mv88e6xxx_port_set_fid(chip, port, 0);
0e7b9925
AL		 2625 if (err)
2626 return err;
2db9ce1f 2627
0e7b9925
AL		 2628 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2629 if (err)
2630 return err;
d827e88a
GR		 2631
2632 /* Default VLAN ID and priority: don't set a default VLAN
2633 * ID, and set the default packet priority to zero.
2634 */
0e7b9925 2635 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
dbde9e66
AL		 2636}
2637
aa0938c6 2638static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3b4caa1b
VD		 2639{
2640 int err;
2641
a935c052 2642 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
3b4caa1b
VD		 2643 if (err)
2644 return err;
2645
a935c052 2646 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
3b4caa1b
VD		 2647 if (err)
2648 return err;
2649
a935c052
VD		 2650 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2651 if (err)
2652 return err;
2653
2654 return 0;
3b4caa1b
VD		 2655}
2656
acddbd21
VD		 2657static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2658 unsigned int msecs)
2659{
2660 const unsigned int coeff = chip->info->age_time_coeff;
2661 const unsigned int min = 0x01 * coeff;
2662 const unsigned int max = 0xff * coeff;
2663 u8 age_time;
2664 u16 val;
2665 int err;
2666
2667 if (msecs < min || msecs > max)
2668 return -ERANGE;
2669
2670 /* Round to nearest multiple of coeff */
2671 age_time = (msecs + coeff / 2) / coeff;
2672
a935c052 2673 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
acddbd21
VD		 2674 if (err)
2675 return err;
2676
2677 /* AgeTime is 11:4 bits */
2678 val &= ~0xff0;
2679 val |= age_time << 4;
2680
a935c052 2681 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
acddbd21
VD		 2682}
2683
2cfcd964
VD		 2684static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2685 unsigned int ageing_time)
2686{
04bed143 2687 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2688 int err;
2689
2690 mutex_lock(&chip->reg_lock);
2691 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2692 mutex_unlock(&chip->reg_lock);
2693
2694 return err;
2695}
2696
9729934c 2697static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2698{
fad09c73 2699 struct dsa_switch *ds = chip->ds;
b0745e87 2700 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2701 u16 reg;
552238b5 2702 int err;
54d792f2 2703
119477bd
VD		 2704 /* Enable the PHY Polling Unit if present, don't discard any packets,
2705 * and mask all interrupt sources.
2706 */
dc30c35b
AL		 2707 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2708 if (err < 0)
2709 return err;
2710
2711 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
fad09c73
VD		 2712 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2713 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2714 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2715
a935c052 2716 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
119477bd
VD		 2717 if (err)
2718 return err;
2719
b0745e87
VD		 2720 /* Configure the upstream port, and configure it as the port to which
2721 * ingress and egress and ARP monitor frames are to be sent.
2722 */
2723 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2724 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2725 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
a935c052 2726 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
b0745e87
VD		 2727 if (err)
2728 return err;
2729
50484ff4 2730 /* Disable remote management, and set the switch's DSA device number. */
a935c052
VD		 2731 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2732 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2733 (ds->index & 0x1f));
50484ff4
VD		 2734 if (err)
2735 return err;
2736
acddbd21
VD		 2737 /* Clear all the VTU and STU entries */
2738 err = _mv88e6xxx_vtu_stu_flush(chip);
2739 if (err < 0)
2740 return err;
2741
54d792f2
AL		 2742 /* Set the default address aging time to 5 minutes, and
2743 * enable address learn messages to be sent to all message
2744 * ports.
2745 */
a935c052
VD		 2746 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2747 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2748 if (err)
08a01261 2749 return err;
54d792f2 2750
acddbd21
VD		 2751 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2752 if (err)
9729934c
VD		 2753 return err;
2754
2755 /* Clear all ATU entries */
2756 err = _mv88e6xxx_atu_flush(chip, 0, true);
2757 if (err)
2758 return err;
2759
54d792f2 2760 /* Configure the IP ToS mapping registers. */
a935c052 2761 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2762 if (err)
08a01261 2763 return err;
a935c052 2764 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2765 if (err)
08a01261 2766 return err;
a935c052 2767 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2768 if (err)
08a01261 2769 return err;
a935c052 2770 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2771 if (err)
08a01261 2772 return err;
a935c052 2773 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2774 if (err)
08a01261 2775 return err;
a935c052 2776 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2777 if (err)
08a01261 2778 return err;
a935c052 2779 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2780 if (err)
08a01261 2781 return err;
a935c052 2782 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2783 if (err)
08a01261 2784 return err;
54d792f2
AL		 2785
2786 /* Configure the IEEE 802.1p priority mapping register. */
a935c052 2787 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2788 if (err)
08a01261 2789 return err;
54d792f2 2790
9729934c 2791 /* Clear the statistics counters for all ports */
a935c052
VD		 2792 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2793 GLOBAL_STATS_OP_FLUSH_ALL);
9729934c
VD		 2794 if (err)
2795 return err;
2796
2797 /* Wait for the flush to complete. */
2798 err = _mv88e6xxx_stats_wait(chip);
2799 if (err)
2800 return err;
2801
2802 return 0;
2803}
2804
f81ec90f 2805static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2806{
04bed143 2807 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2808 int err;
a1a6a4d1
VD		 2809 int i;
2810
fad09c73
VD		 2811 chip->ds = ds;
2812 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2813
fad09c73 2814 mutex_lock(&chip->reg_lock);
08a01261 2815
9729934c 2816 /* Setup Switch Port Registers */
370b4ffb 2817 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
9729934c
VD		 2818 err = mv88e6xxx_setup_port(chip, i);
2819 if (err)
2820 goto unlock;
2821 }
2822
2823 /* Setup Switch Global 1 Registers */
2824 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2825 if (err)
2826 goto unlock;
2827
9729934c
VD		 2828 /* Setup Switch Global 2 Registers */
2829 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2830 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2831 if (err)
2832 goto unlock;
2833 }
08a01261 2834
6b17e864 2835unlock:
fad09c73 2836 mutex_unlock(&chip->reg_lock);
db687a56 2837
48ace4ef 2838 return err;
54d792f2
AL		 2839}
2840
3b4caa1b
VD		 2841static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2842{
04bed143 2843 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2844 int err;
2845
b073d4e2
VD		 2846 if (!chip->info->ops->set_switch_mac)
2847 return -EOPNOTSUPP;
3b4caa1b 2848
b073d4e2
VD		 2849 mutex_lock(&chip->reg_lock);
2850 err = chip->info->ops->set_switch_mac(chip, addr);
3b4caa1b
VD		 2851 mutex_unlock(&chip->reg_lock);
2852
2853 return err;
2854}
2855
e57e5e77 2856static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2857{
fad09c73 2858 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2859 u16 val;
2860 int err;
fd3a0ee4 2861
370b4ffb 2862 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2863 return 0xffff;
fd3a0ee4 2864
fad09c73 2865 mutex_lock(&chip->reg_lock);
e57e5e77 2866 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2867 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2868
2869 return err ? err : val;
fd3a0ee4
AL		 2870}
2871
e57e5e77 2872static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2873{
fad09c73 2874 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2875 int err;
fd3a0ee4 2876
370b4ffb 2877 if (phy >= mv88e6xxx_num_ports(chip))
158bc065 2878 return 0xffff;
fd3a0ee4 2879
fad09c73 2880 mutex_lock(&chip->reg_lock);
e57e5e77 2881 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2882 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2883
2884 return err;
fd3a0ee4
AL		 2885}
2886
fad09c73 2887static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2888 struct device_node *np)
2889{
2890 static int index;
2891 struct mii_bus *bus;
2892 int err;
2893
b516d453 2894 if (np)
fad09c73 2895 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2896
fad09c73 2897 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2898 if (!bus)
2899 return -ENOMEM;
2900
fad09c73 2901 bus->priv = (void *)chip;
b516d453
AL		 2902 if (np) {
2903 bus->name = np->full_name;
2904 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2905 } else {
2906 bus->name = "mv88e6xxx SMI";
2907 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2908 }
2909
2910 bus->read = mv88e6xxx_mdio_read;
2911 bus->write = mv88e6xxx_mdio_write;
fad09c73 2912 bus->parent = chip->dev;
b516d453 2913
fad09c73
VD		 2914 if (chip->mdio_np)
2915 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2916 else
2917 err = mdiobus_register(bus);
2918 if (err) {
fad09c73 2919 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 2920 goto out;
2921 }
fad09c73 2922 chip->mdio_bus = bus;
b516d453
AL		 2923
2924 return 0;
2925
2926out:
fad09c73
VD		 2927 if (chip->mdio_np)
2928 of_node_put(chip->mdio_np);
b516d453
AL		 2929
2930 return err;
2931}
2932
fad09c73 2933static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 2934
2935{
fad09c73 2936 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 2937
2938 mdiobus_unregister(bus);
2939
fad09c73
VD		 2940 if (chip->mdio_np)
2941 of_node_put(chip->mdio_np);
b516d453
AL		 2942}
2943
c22995c5
GR		 2944#ifdef CONFIG_NET_DSA_HWMON
2945
2946static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2947{
04bed143 2948 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 2949 u16 val;
c22995c5 2950 int ret;
c22995c5
GR		 2951
2952 *temp = 0;
2953
fad09c73 2954 mutex_lock(&chip->reg_lock);
c22995c5 2955
9c93829c 2956 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 2957 if (ret < 0)
2958 goto error;
2959
2960 /* Enable temperature sensor */
9c93829c 2961 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 2962 if (ret < 0)
2963 goto error;
2964
9c93829c 2965 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 2966 if (ret < 0)
2967 goto error;
2968
2969 /* Wait for temperature to stabilize */
2970 usleep_range(10000, 12000);
2971
9c93829c
VD		 2972 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
2973 if (ret < 0)
c22995c5 2974 goto error;
c22995c5
GR		 2975
2976 /* Disable temperature sensor */
9c93829c 2977 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 2978 if (ret < 0)
2979 goto error;
2980
2981 *temp = ((val & 0x1f) - 5) * 5;
2982
2983error:
9c93829c 2984 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 2985 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 2986 return ret;
2987}
2988
2989static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2990{
04bed143 2991 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2992 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 2993 u16 val;
c22995c5
GR		 2994 int ret;
2995
2996 *temp = 0;
2997
9c93829c
VD		 2998 mutex_lock(&chip->reg_lock);
2999 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3000 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3001 if (ret < 0)
3002 return ret;
3003
9c93829c 3004 *temp = (val & 0xff) - 25;
c22995c5
GR		 3005
3006 return 0;
3007}
3008
f81ec90f 3009static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3010{
04bed143 3011 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3012
fad09c73 3013 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3014 return -EOPNOTSUPP;
3015
fad09c73 3016 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3017 return mv88e63xx_get_temp(ds, temp);
3018
3019 return mv88e61xx_get_temp(ds, temp);
3020}
3021
f81ec90f 3022static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3023{
04bed143 3024 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3025 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3026 u16 val;
c22995c5
GR		 3027 int ret;
3028
fad09c73 3029 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3030 return -EOPNOTSUPP;
3031
3032 *temp = 0;
3033
9c93829c
VD		 3034 mutex_lock(&chip->reg_lock);
3035 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3036 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3037 if (ret < 0)
3038 return ret;
3039
9c93829c 3040 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3041
3042 return 0;
3043}
3044
f81ec90f 3045static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3046{
04bed143 3047 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3048 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3049 u16 val;
3050 int err;
c22995c5 3051
fad09c73 3052 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3053 return -EOPNOTSUPP;
3054
9c93829c
VD		 3055 mutex_lock(&chip->reg_lock);
3056 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3057 if (err)
3058 goto unlock;
c22995c5 3059 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3060 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3061 (val & 0xe0ff) | (temp << 8));
3062unlock:
3063 mutex_unlock(&chip->reg_lock);
3064
3065 return err;
c22995c5
GR		 3066}
3067
f81ec90f 3068static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3069{
04bed143 3070 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3071 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3072 u16 val;
c22995c5
GR		 3073 int ret;
3074
fad09c73 3075 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3076 return -EOPNOTSUPP;
3077
3078 *alarm = false;
3079
9c93829c
VD		 3080 mutex_lock(&chip->reg_lock);
3081 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3082 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3083 if (ret < 0)
3084 return ret;
3085
9c93829c 3086 *alarm = !!(val & 0x40);
c22995c5
GR		 3087
3088 return 0;
3089}
3090#endif /* CONFIG_NET_DSA_HWMON */
3091
855b1932
VD		 3092static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3093{
04bed143 3094 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3095
3096 return chip->eeprom_len;
3097}
3098
855b1932
VD		 3099static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3100 struct ethtool_eeprom *eeprom, u8 *data)
3101{
04bed143 3102 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3103 int err;
3104
ee4dc2e7
VD		 3105 if (!chip->info->ops->get_eeprom)
3106 return -EOPNOTSUPP;
855b1932 3107
ee4dc2e7
VD		 3108 mutex_lock(&chip->reg_lock);
3109 err = chip->info->ops->get_eeprom(chip, eeprom, data);
855b1932
VD		 3110 mutex_unlock(&chip->reg_lock);
3111
3112 if (err)
3113 return err;
3114
3115 eeprom->magic = 0xc3ec4951;
3116
3117 return 0;
3118}
3119
855b1932
VD		 3120static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3121 struct ethtool_eeprom *eeprom, u8 *data)
3122{
04bed143 3123 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3124 int err;
3125
ee4dc2e7
VD		 3126 if (!chip->info->ops->set_eeprom)
3127 return -EOPNOTSUPP;
3128
855b1932
VD		 3129 if (eeprom->magic != 0xc3ec4951)
3130 return -EINVAL;
3131
3132 mutex_lock(&chip->reg_lock);
ee4dc2e7 3133 err = chip->info->ops->set_eeprom(chip, eeprom, data);
855b1932
VD		 3134 mutex_unlock(&chip->reg_lock);
3135
3136 return err;
3137}
3138
b3469dd8 3139static const struct mv88e6xxx_ops mv88e6085_ops = {
b073d4e2 3140 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3141 .phy_read = mv88e6xxx_phy_ppu_read,
3142 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3143 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3144 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3145 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3146};
3147
3148static const struct mv88e6xxx_ops mv88e6095_ops = {
b073d4e2 3149 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3150 .phy_read = mv88e6xxx_phy_ppu_read,
3151 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3152 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3153 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3154 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3155};
3156
3157static const struct mv88e6xxx_ops mv88e6123_ops = {
b073d4e2 3158 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3159 .phy_read = mv88e6xxx_read,
3160 .phy_write = mv88e6xxx_write,
08ef7f10 3161 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3162 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3163 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3164};
3165
3166static const struct mv88e6xxx_ops mv88e6131_ops = {
b073d4e2 3167 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3168 .phy_read = mv88e6xxx_phy_ppu_read,
3169 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3170 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3171 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3172 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3173};
3174
3175static const struct mv88e6xxx_ops mv88e6161_ops = {
b073d4e2 3176 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3177 .phy_read = mv88e6xxx_read,
3178 .phy_write = mv88e6xxx_write,
08ef7f10 3179 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3180 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3181 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3182};
3183
3184static const struct mv88e6xxx_ops mv88e6165_ops = {
b073d4e2 3185 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3186 .phy_read = mv88e6xxx_read,
3187 .phy_write = mv88e6xxx_write,
08ef7f10 3188 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3189 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3190 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3191};
3192
3193static const struct mv88e6xxx_ops mv88e6171_ops = {
b073d4e2 3194 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3195 .phy_read = mv88e6xxx_g2_smi_phy_read,
3196 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3197 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3198 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3199 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3200};
3201
3202static const struct mv88e6xxx_ops mv88e6172_ops = {
ee4dc2e7
VD		 3203 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3204 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3205 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3206 .phy_read = mv88e6xxx_g2_smi_phy_read,
3207 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3208 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3209 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3210 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3211 .port_set_speed = mv88e6352_port_set_speed,
b3469dd8
VD		 3212};
3213
3214static const struct mv88e6xxx_ops mv88e6175_ops = {
b073d4e2 3215 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3216 .phy_read = mv88e6xxx_g2_smi_phy_read,
3217 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3218 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3219 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3220 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3221};
3222
3223static const struct mv88e6xxx_ops mv88e6176_ops = {
ee4dc2e7
VD		 3224 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3225 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3226 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3227 .phy_read = mv88e6xxx_g2_smi_phy_read,
3228 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3229 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3230 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3231 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3232 .port_set_speed = mv88e6352_port_set_speed,
b3469dd8
VD		 3233};
3234
3235static const struct mv88e6xxx_ops mv88e6185_ops = {
b073d4e2 3236 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
b3469dd8
VD		 3237 .phy_read = mv88e6xxx_phy_ppu_read,
3238 .phy_write = mv88e6xxx_phy_ppu_write,
08ef7f10 3239 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3240 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3241 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3242};
3243
3244static const struct mv88e6xxx_ops mv88e6240_ops = {
ee4dc2e7
VD		 3245 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3246 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3247 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3248 .phy_read = mv88e6xxx_g2_smi_phy_read,
3249 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3250 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3251 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3252 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3253 .port_set_speed = mv88e6352_port_set_speed,
b3469dd8
VD		 3254};
3255
3256static const struct mv88e6xxx_ops mv88e6320_ops = {
ee4dc2e7
VD		 3257 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3258 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3259 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3260 .phy_read = mv88e6xxx_g2_smi_phy_read,
3261 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3262 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3263 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3264 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3265};
3266
3267static const struct mv88e6xxx_ops mv88e6321_ops = {
ee4dc2e7
VD		 3268 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3269 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3270 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3271 .phy_read = mv88e6xxx_g2_smi_phy_read,
3272 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3273 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3274 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3275 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3276};
3277
3278static const struct mv88e6xxx_ops mv88e6350_ops = {
b073d4e2 3279 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3280 .phy_read = mv88e6xxx_g2_smi_phy_read,
3281 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3282 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3283 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3284 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3285};
3286
3287static const struct mv88e6xxx_ops mv88e6351_ops = {
b073d4e2 3288 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3289 .phy_read = mv88e6xxx_g2_smi_phy_read,
3290 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3291 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3292 .port_set_duplex = mv88e6xxx_port_set_duplex,
96a2b40c 3293 .port_set_speed = mv88e6185_port_set_speed,
b3469dd8
VD		 3294};
3295
3296static const struct mv88e6xxx_ops mv88e6352_ops = {
ee4dc2e7
VD		 3297 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3298 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3299 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3300 .phy_read = mv88e6xxx_g2_smi_phy_read,
3301 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3302 .port_set_link = mv88e6xxx_port_set_link,
7f1ae07b 3303 .port_set_duplex = mv88e6xxx_port_set_duplex,
a0a0f622 3304 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
96a2b40c 3305 .port_set_speed = mv88e6352_port_set_speed,
b3469dd8
VD		 3306};
3307
f81ec90f
VD		 3308static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3309 [MV88E6085] = {
3310 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3311 .family = MV88E6XXX_FAMILY_6097,
3312 .name = "Marvell 88E6085",
3313 .num_databases = 4096,
3314 .num_ports = 10,
9dddd478 3315 .port_base_addr = 0x10,
a935c052 3316 .global1_addr = 0x1b,
acddbd21 3317 .age_time_coeff = 15000,
dc30c35b 3318 .g1_irqs = 8,
f81ec90f 3319 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
b3469dd8 3320 .ops = &mv88e6085_ops,
f81ec90f
VD		 3321 },
3322
3323 [MV88E6095] = {
3324 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3325 .family = MV88E6XXX_FAMILY_6095,
3326 .name = "Marvell 88E6095/88E6095F",
3327 .num_databases = 256,
3328 .num_ports = 11,
9dddd478 3329 .port_base_addr = 0x10,
a935c052 3330 .global1_addr = 0x1b,
acddbd21 3331 .age_time_coeff = 15000,
dc30c35b 3332 .g1_irqs = 8,
f81ec90f 3333 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
b3469dd8 3334 .ops = &mv88e6095_ops,
f81ec90f
VD		 3335 },
3336
3337 [MV88E6123] = {
3338 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3339 .family = MV88E6XXX_FAMILY_6165,
3340 .name = "Marvell 88E6123",
3341 .num_databases = 4096,
3342 .num_ports = 3,
9dddd478 3343 .port_base_addr = 0x10,
a935c052 3344 .global1_addr = 0x1b,
acddbd21 3345 .age_time_coeff = 15000,
dc30c35b 3346 .g1_irqs = 9,
f81ec90f 3347 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3348 .ops = &mv88e6123_ops,
f81ec90f
VD		 3349 },
3350
3351 [MV88E6131] = {
3352 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3353 .family = MV88E6XXX_FAMILY_6185,
3354 .name = "Marvell 88E6131",
3355 .num_databases = 256,
3356 .num_ports = 8,
9dddd478 3357 .port_base_addr = 0x10,
a935c052 3358 .global1_addr = 0x1b,
acddbd21 3359 .age_time_coeff = 15000,
dc30c35b 3360 .g1_irqs = 9,
f81ec90f 3361 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3362 .ops = &mv88e6131_ops,
f81ec90f
VD		 3363 },
3364
3365 [MV88E6161] = {
3366 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3367 .family = MV88E6XXX_FAMILY_6165,
3368 .name = "Marvell 88E6161",
3369 .num_databases = 4096,
3370 .num_ports = 6,
9dddd478 3371 .port_base_addr = 0x10,
a935c052 3372 .global1_addr = 0x1b,
acddbd21 3373 .age_time_coeff = 15000,
dc30c35b 3374 .g1_irqs = 9,
f81ec90f 3375 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3376 .ops = &mv88e6161_ops,
f81ec90f
VD		 3377 },
3378
3379 [MV88E6165] = {
3380 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3381 .family = MV88E6XXX_FAMILY_6165,
3382 .name = "Marvell 88E6165",
3383 .num_databases = 4096,
3384 .num_ports = 6,
9dddd478 3385 .port_base_addr = 0x10,
a935c052 3386 .global1_addr = 0x1b,
acddbd21 3387 .age_time_coeff = 15000,
dc30c35b 3388 .g1_irqs = 9,
f81ec90f 3389 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
b3469dd8 3390 .ops = &mv88e6165_ops,
f81ec90f
VD		 3391 },
3392
3393 [MV88E6171] = {
3394 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3395 .family = MV88E6XXX_FAMILY_6351,
3396 .name = "Marvell 88E6171",
3397 .num_databases = 4096,
3398 .num_ports = 7,
9dddd478 3399 .port_base_addr = 0x10,
a935c052 3400 .global1_addr = 0x1b,
acddbd21 3401 .age_time_coeff = 15000,
dc30c35b 3402 .g1_irqs = 9,
f81ec90f 3403 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3404 .ops = &mv88e6171_ops,
f81ec90f
VD		 3405 },
3406
3407 [MV88E6172] = {
3408 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3409 .family = MV88E6XXX_FAMILY_6352,
3410 .name = "Marvell 88E6172",
3411 .num_databases = 4096,
3412 .num_ports = 7,
9dddd478 3413 .port_base_addr = 0x10,
a935c052 3414 .global1_addr = 0x1b,
acddbd21 3415 .age_time_coeff = 15000,
dc30c35b 3416 .g1_irqs = 9,
f81ec90f 3417 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3418 .ops = &mv88e6172_ops,
f81ec90f
VD		 3419 },
3420
3421 [MV88E6175] = {
3422 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3423 .family = MV88E6XXX_FAMILY_6351,
3424 .name = "Marvell 88E6175",
3425 .num_databases = 4096,
3426 .num_ports = 7,
9dddd478 3427 .port_base_addr = 0x10,
a935c052 3428 .global1_addr = 0x1b,
acddbd21 3429 .age_time_coeff = 15000,
dc30c35b 3430 .g1_irqs = 9,
f81ec90f 3431 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3432 .ops = &mv88e6175_ops,
f81ec90f
VD		 3433 },
3434
3435 [MV88E6176] = {
3436 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3437 .family = MV88E6XXX_FAMILY_6352,
3438 .name = "Marvell 88E6176",
3439 .num_databases = 4096,
3440 .num_ports = 7,
9dddd478 3441 .port_base_addr = 0x10,
a935c052 3442 .global1_addr = 0x1b,
acddbd21 3443 .age_time_coeff = 15000,
dc30c35b 3444 .g1_irqs = 9,
f81ec90f 3445 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3446 .ops = &mv88e6176_ops,
f81ec90f
VD		 3447 },
3448
3449 [MV88E6185] = {
3450 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3451 .family = MV88E6XXX_FAMILY_6185,
3452 .name = "Marvell 88E6185",
3453 .num_databases = 256,
3454 .num_ports = 10,
9dddd478 3455 .port_base_addr = 0x10,
a935c052 3456 .global1_addr = 0x1b,
acddbd21 3457 .age_time_coeff = 15000,
dc30c35b 3458 .g1_irqs = 8,
f81ec90f 3459 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
b3469dd8 3460 .ops = &mv88e6185_ops,
f81ec90f
VD		 3461 },
3462
3463 [MV88E6240] = {
3464 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3465 .family = MV88E6XXX_FAMILY_6352,
3466 .name = "Marvell 88E6240",
3467 .num_databases = 4096,
3468 .num_ports = 7,
9dddd478 3469 .port_base_addr = 0x10,
a935c052 3470 .global1_addr = 0x1b,
acddbd21 3471 .age_time_coeff = 15000,
dc30c35b 3472 .g1_irqs = 9,
f81ec90f 3473 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3474 .ops = &mv88e6240_ops,
f81ec90f
VD		 3475 },
3476
3477 [MV88E6320] = {
3478 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3479 .family = MV88E6XXX_FAMILY_6320,
3480 .name = "Marvell 88E6320",
3481 .num_databases = 4096,
3482 .num_ports = 7,
9dddd478 3483 .port_base_addr = 0x10,
a935c052 3484 .global1_addr = 0x1b,
acddbd21 3485 .age_time_coeff = 15000,
dc30c35b 3486 .g1_irqs = 8,
f81ec90f 3487 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3488 .ops = &mv88e6320_ops,
f81ec90f
VD		 3489 },
3490
3491 [MV88E6321] = {
3492 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3493 .family = MV88E6XXX_FAMILY_6320,
3494 .name = "Marvell 88E6321",
3495 .num_databases = 4096,
3496 .num_ports = 7,
9dddd478 3497 .port_base_addr = 0x10,
a935c052 3498 .global1_addr = 0x1b,
acddbd21 3499 .age_time_coeff = 15000,
dc30c35b 3500 .g1_irqs = 8,
f81ec90f 3501 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
b3469dd8 3502 .ops = &mv88e6321_ops,
f81ec90f
VD		 3503 },
3504
3505 [MV88E6350] = {
3506 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3507 .family = MV88E6XXX_FAMILY_6351,
3508 .name = "Marvell 88E6350",
3509 .num_databases = 4096,
3510 .num_ports = 7,
9dddd478 3511 .port_base_addr = 0x10,
a935c052 3512 .global1_addr = 0x1b,
acddbd21 3513 .age_time_coeff = 15000,
dc30c35b 3514 .g1_irqs = 9,
f81ec90f 3515 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3516 .ops = &mv88e6350_ops,
f81ec90f
VD		 3517 },
3518
3519 [MV88E6351] = {
3520 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3521 .family = MV88E6XXX_FAMILY_6351,
3522 .name = "Marvell 88E6351",
3523 .num_databases = 4096,
3524 .num_ports = 7,
9dddd478 3525 .port_base_addr = 0x10,
a935c052 3526 .global1_addr = 0x1b,
acddbd21 3527 .age_time_coeff = 15000,
dc30c35b 3528 .g1_irqs = 9,
f81ec90f 3529 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
b3469dd8 3530 .ops = &mv88e6351_ops,
f81ec90f
VD		 3531 },
3532
3533 [MV88E6352] = {
3534 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3535 .family = MV88E6XXX_FAMILY_6352,
3536 .name = "Marvell 88E6352",
3537 .num_databases = 4096,
3538 .num_ports = 7,
9dddd478 3539 .port_base_addr = 0x10,
a935c052 3540 .global1_addr = 0x1b,
acddbd21 3541 .age_time_coeff = 15000,
dc30c35b 3542 .g1_irqs = 9,
f81ec90f 3543 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
b3469dd8 3544 .ops = &mv88e6352_ops,
f81ec90f
VD		 3545 },
3546};
3547
5f7c0367 3548static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3549{
a439c061 3550 int i;
b9b37713 3551
5f7c0367
VD		 3552 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3553 if (mv88e6xxx_table[i].prod_num == prod_num)
3554 return &mv88e6xxx_table[i];
b9b37713 3555
b9b37713
VD		 3556 return NULL;
3557}
3558
fad09c73 3559static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3560{
3561 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3562 unsigned int prod_num, rev;
3563 u16 id;
3564 int err;
bc46a3d5 3565
8f6345b2
VD		 3566 mutex_lock(&chip->reg_lock);
3567 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3568 mutex_unlock(&chip->reg_lock);
3569 if (err)
3570 return err;
bc46a3d5
VD		 3571
3572 prod_num = (id & 0xfff0) >> 4;
3573 rev = id & 0x000f;
3574
3575 info = mv88e6xxx_lookup_info(prod_num);
3576 if (!info)
3577 return -ENODEV;
3578
caac8545 3579 /* Update the compatible info with the probed one */
fad09c73 3580 chip->info = info;
bc46a3d5 3581
ca070c10
VD		 3582 err = mv88e6xxx_g2_require(chip);
3583 if (err)
3584 return err;
3585
fad09c73
VD		 3586 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3587 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3588
3589 return 0;
3590}
3591
fad09c73 3592static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3593{
fad09c73 3594 struct mv88e6xxx_chip *chip;
469d729f 3595
fad09c73
VD		 3596 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3597 if (!chip)
469d729f
VD		 3598 return NULL;
3599
fad09c73 3600 chip->dev = dev;
469d729f 3601
fad09c73 3602 mutex_init(&chip->reg_lock);
469d729f 3603
fad09c73 3604 return chip;
469d729f
VD		 3605}
3606
e57e5e77
VD		 3607static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3608{
b3469dd8 3609 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
e57e5e77 3610 mv88e6xxx_ppu_state_init(chip);
e57e5e77
VD		 3611}
3612
930188ce
AL		 3613static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3614{
b3469dd8 3615 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
930188ce 3616 mv88e6xxx_ppu_state_destroy(chip);
930188ce
AL		 3617}
3618
fad09c73 3619static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3620 struct mii_bus *bus, int sw_addr)
3621{
3622 /* ADDR[0] pin is unavailable externally and considered zero */
3623 if (sw_addr & 0x1)
3624 return -EINVAL;
3625
914b32f6 3626 if (sw_addr == 0)
fad09c73 3627 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3628 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3629 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3630 else
3631 return -EINVAL;
3632
fad09c73
VD		 3633 chip->bus = bus;
3634 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3635
3636 return 0;
3637}
3638
7b314362
AL		 3639static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3640{
04bed143 3641 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be
AL		 3642
3643 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3644 return DSA_TAG_PROTO_EDSA;
3645
3646 return DSA_TAG_PROTO_DSA;
7b314362
AL		 3647}
3648
fcdce7d0
AL		 3649static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3650 struct device *host_dev, int sw_addr,
3651 void **priv)
a77d43f1 3652{
fad09c73 3653 struct mv88e6xxx_chip *chip;
a439c061 3654 struct mii_bus *bus;
b516d453 3655 int err;
a77d43f1 3656
a439c061 3657 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3658 if (!bus)
3659 return NULL;
3660
fad09c73
VD		 3661 chip = mv88e6xxx_alloc_chip(dsa_dev);
3662 if (!chip)
469d729f
VD		 3663 return NULL;
3664
caac8545 3665 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3666 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3667
fad09c73 3668 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3669 if (err)
3670 goto free;
3671
fad09c73 3672 err = mv88e6xxx_detect(chip);
bc46a3d5 3673 if (err)
469d729f 3674 goto free;
a439c061 3675
dc30c35b
AL		 3676 mutex_lock(&chip->reg_lock);
3677 err = mv88e6xxx_switch_reset(chip);
3678 mutex_unlock(&chip->reg_lock);
3679 if (err)
3680 goto free;
3681
e57e5e77
VD		 3682 mv88e6xxx_phy_init(chip);
3683
fad09c73 3684 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3685 if (err)
469d729f 3686 goto free;
b516d453 3687
fad09c73 3688 *priv = chip;
a439c061 3689
fad09c73 3690 return chip->info->name;
469d729f 3691free:
fad09c73 3692 devm_kfree(dsa_dev, chip);
469d729f
VD		 3693
3694 return NULL;
a77d43f1
AL		 3695}
3696
7df8fbdd
VD		 3697static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3698 const struct switchdev_obj_port_mdb *mdb,
3699 struct switchdev_trans *trans)
3700{
3701 /* We don't need any dynamic resource from the kernel (yet),
3702 * so skip the prepare phase.
3703 */
3704
3705 return 0;
3706}
3707
3708static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3709 const struct switchdev_obj_port_mdb *mdb,
3710 struct switchdev_trans *trans)
3711{
04bed143 3712 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3713
3714 mutex_lock(&chip->reg_lock);
3715 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3716 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3717 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3718 mutex_unlock(&chip->reg_lock);
3719}
3720
3721static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3722 const struct switchdev_obj_port_mdb *mdb)
3723{
04bed143 3724 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3725 int err;
3726
3727 mutex_lock(&chip->reg_lock);
3728 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3729 GLOBAL_ATU_DATA_STATE_UNUSED);
3730 mutex_unlock(&chip->reg_lock);
3731
3732 return err;
3733}
3734
3735static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3736 struct switchdev_obj_port_mdb *mdb,
3737 int (*cb)(struct switchdev_obj *obj))
3738{
04bed143 3739 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3740 int err;
3741
3742 mutex_lock(&chip->reg_lock);
3743 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3744 mutex_unlock(&chip->reg_lock);
3745
3746 return err;
3747}
3748
9d490b4e 3749static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3750 .probe = mv88e6xxx_drv_probe,
7b314362 3751 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3752 .setup = mv88e6xxx_setup,
3753 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3754 .adjust_link = mv88e6xxx_adjust_link,
3755 .get_strings = mv88e6xxx_get_strings,
3756 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3757 .get_sset_count = mv88e6xxx_get_sset_count,
3758 .set_eee = mv88e6xxx_set_eee,
3759 .get_eee = mv88e6xxx_get_eee,
3760#ifdef CONFIG_NET_DSA_HWMON
3761 .get_temp = mv88e6xxx_get_temp,
3762 .get_temp_limit = mv88e6xxx_get_temp_limit,
3763 .set_temp_limit = mv88e6xxx_set_temp_limit,
3764 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3765#endif
f8cd8753 3766 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3767 .get_eeprom = mv88e6xxx_get_eeprom,
3768 .set_eeprom = mv88e6xxx_set_eeprom,
3769 .get_regs_len = mv88e6xxx_get_regs_len,
3770 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3771 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3772 .port_bridge_join = mv88e6xxx_port_bridge_join,
3773 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3774 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 3775 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f
VD		 3776 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3777 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3778 .port_vlan_add = mv88e6xxx_port_vlan_add,
3779 .port_vlan_del = mv88e6xxx_port_vlan_del,
3780 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3781 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3782 .port_fdb_add = mv88e6xxx_port_fdb_add,
3783 .port_fdb_del = mv88e6xxx_port_fdb_del,
3784 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3785 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3786 .port_mdb_add = mv88e6xxx_port_mdb_add,
3787 .port_mdb_del = mv88e6xxx_port_mdb_del,
3788 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 3789};
3790
fad09c73 3791static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3792 struct device_node *np)
3793{
fad09c73 3794 struct device *dev = chip->dev;
b7e66a5f
VD		 3795 struct dsa_switch *ds;
3796
3797 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3798 if (!ds)
3799 return -ENOMEM;
3800
3801 ds->dev = dev;
fad09c73 3802 ds->priv = chip;
9d490b4e 3803 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 3804
3805 dev_set_drvdata(dev, ds);
3806
3807 return dsa_register_switch(ds, np);
3808}
3809
fad09c73 3810static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3811{
fad09c73 3812 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3813}
3814
57d32310 3815static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3816{
14c7b3c3 3817 struct device *dev = &mdiodev->dev;
f8cd8753 3818 struct device_node *np = dev->of_node;
caac8545 3819 const struct mv88e6xxx_info *compat_info;
fad09c73 3820 struct mv88e6xxx_chip *chip;
f8cd8753 3821 u32 eeprom_len;
52638f71 3822 int err;
14c7b3c3 3823
caac8545
VD		 3824 compat_info = of_device_get_match_data(dev);
3825 if (!compat_info)
3826 return -EINVAL;
3827
fad09c73
VD		 3828 chip = mv88e6xxx_alloc_chip(dev);
3829 if (!chip)
14c7b3c3
AL		 3830 return -ENOMEM;
3831
fad09c73 3832 chip->info = compat_info;
caac8545 3833
fad09c73 3834 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3835 if (err)
3836 return err;
14c7b3c3 3837
fad09c73 3838 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3839 if (err)
3840 return err;
14c7b3c3 3841
e57e5e77
VD		 3842 mv88e6xxx_phy_init(chip);
3843
fad09c73
VD		 3844 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3845 if (IS_ERR(chip->reset))
3846 return PTR_ERR(chip->reset);
52638f71 3847
ee4dc2e7 3848 if (chip->info->ops->get_eeprom &&
f8cd8753 3849 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3850 chip->eeprom_len = eeprom_len;
f8cd8753 3851
dc30c35b
AL		 3852 mutex_lock(&chip->reg_lock);
3853 err = mv88e6xxx_switch_reset(chip);
3854 mutex_unlock(&chip->reg_lock);
3855 if (err)
3856 goto out;
3857
3858 chip->irq = of_irq_get(np, 0);
3859 if (chip->irq == -EPROBE_DEFER) {
3860 err = chip->irq;
3861 goto out;
3862 }
3863
3864 if (chip->irq > 0) {
3865 /* Has to be performed before the MDIO bus is created,
3866 * because the PHYs will link there interrupts to these
3867 * interrupt controllers
3868 */
3869 mutex_lock(&chip->reg_lock);
3870 err = mv88e6xxx_g1_irq_setup(chip);
3871 mutex_unlock(&chip->reg_lock);
3872
3873 if (err)
3874 goto out;
3875
3876 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
3877 err = mv88e6xxx_g2_irq_setup(chip);
3878 if (err)
3879 goto out_g1_irq;
3880 }
3881 }
3882
fad09c73 3883 err = mv88e6xxx_mdio_register(chip, np);
b516d453 3884 if (err)
dc30c35b 3885 goto out_g2_irq;
b516d453 3886
fad09c73 3887 err = mv88e6xxx_register_switch(chip, np);
dc30c35b
AL		 3888 if (err)
3889 goto out_mdio;
83c0afae 3890
98e67308 3891 return 0;
dc30c35b
AL		 3892
3893out_mdio:
3894 mv88e6xxx_mdio_unregister(chip);
3895out_g2_irq:
3896 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
3897 mv88e6xxx_g2_irq_free(chip);
3898out_g1_irq:
3899 mv88e6xxx_g1_irq_free(chip);
3900out:
3901 return err;
98e67308 3902}
14c7b3c3
AL		 3903
3904static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3905{
3906 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 3907 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 3908
930188ce 3909 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 3910 mv88e6xxx_unregister_switch(chip);
3911 mv88e6xxx_mdio_unregister(chip);
dc30c35b
AL		 3912
3913 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
3914 mv88e6xxx_g2_irq_free(chip);
3915 mv88e6xxx_g1_irq_free(chip);
14c7b3c3
AL		 3916}
3917
3918static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 3919 {
3920 .compatible = "marvell,mv88e6085",
3921 .data = &mv88e6xxx_table[MV88E6085],
3922 },
14c7b3c3
AL		 3923 { /* sentinel */ },
3924};
3925
3926MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3927
3928static struct mdio_driver mv88e6xxx_driver = {
3929 .probe = mv88e6xxx_probe,
3930 .remove = mv88e6xxx_remove,
3931 .mdiodrv.driver = {
3932 .name = "mv88e6085",
3933 .of_match_table = mv88e6xxx_of_match,
3934 },
3935};
3936
3937static int __init mv88e6xxx_init(void)
3938{
9d490b4e 3939 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 3940 return mdio_driver_register(&mv88e6xxx_driver);
3941}
98e67308
BH		 3942module_init(mv88e6xxx_init);
3943
3944static void __exit mv88e6xxx_cleanup(void)
3945{
14c7b3c3 3946 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 3947 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 3948}
3949module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3950
3951MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3952MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3953MODULE_LICENSE("GPL");
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