[mirror_ubuntu-kernels.git] / drivers / net / dsa / mv88e6xxx / chip.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Marvell 88E6xxx Ethernet switch single-chip definition
 *
 * Copyright (c) 2008 Marvell Semiconductor
 */

#ifndef _MV88E6XXX_CHIP_H
#define _MV88E6XXX_CHIP_H

#include <linux/if_vlan.h>
#include <linux/irq.h>
#include <linux/gpio/consumer.h>
#include <linux/kthread.h>
#include <linux/phy.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/timecounter.h>
#include <net/dsa.h>

#define MV88E6XXX_N_FID		4096

/* PVT limits for 4-bit port and 5-bit switch */
#define MV88E6XXX_MAX_PVT_SWITCHES	32
#define MV88E6XXX_MAX_PVT_PORTS		16

#define MV88E6XXX_MAX_GPIO	16

enum mv88e6xxx_egress_mode {
	MV88E6XXX_EGRESS_MODE_UNMODIFIED,
	MV88E6XXX_EGRESS_MODE_UNTAGGED,
	MV88E6XXX_EGRESS_MODE_TAGGED,
	MV88E6XXX_EGRESS_MODE_ETHERTYPE,
};

enum mv88e6xxx_frame_mode {
	MV88E6XXX_FRAME_MODE_NORMAL,
	MV88E6XXX_FRAME_MODE_DSA,
	MV88E6XXX_FRAME_MODE_PROVIDER,
	MV88E6XXX_FRAME_MODE_ETHERTYPE,
};

/* List of supported models */
enum mv88e6xxx_model {
	MV88E6085,
	MV88E6095,
	MV88E6097,
	MV88E6123,
	MV88E6131,
	MV88E6141,
	MV88E6161,
	MV88E6165,
	MV88E6171,
	MV88E6172,
	MV88E6175,
	MV88E6176,
	MV88E6185,
	MV88E6190,
	MV88E6190X,
	MV88E6191,
	MV88E6240,
	MV88E6290,
	MV88E6320,
	MV88E6321,
	MV88E6341,
	MV88E6350,
	MV88E6351,
	MV88E6352,
	MV88E6390,
	MV88E6390X,
};

enum mv88e6xxx_family {
	MV88E6XXX_FAMILY_NONE,
	MV88E6XXX_FAMILY_6065,	/* 6031 6035 6061 6065 */
	MV88E6XXX_FAMILY_6095,	/* 6092 6095 */
	MV88E6XXX_FAMILY_6097,	/* 6046 6085 6096 6097 */
	MV88E6XXX_FAMILY_6165,	/* 6123 6161 6165 */
	MV88E6XXX_FAMILY_6185,	/* 6108 6121 6122 6131 6152 6155 6182 6185 */
	MV88E6XXX_FAMILY_6320,	/* 6320 6321 */
	MV88E6XXX_FAMILY_6341,	/* 6141 6341 */
	MV88E6XXX_FAMILY_6351,	/* 6171 6175 6350 6351 */
	MV88E6XXX_FAMILY_6352,	/* 6172 6176 6240 6352 */
	MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
};

struct mv88e6xxx_ops;

struct mv88e6xxx_info {
	enum mv88e6xxx_family family;
	u16 prod_num;
	const char *name;
	unsigned int num_databases;
	unsigned int num_ports;
	unsigned int num_internal_phys;
	unsigned int num_gpio;
	unsigned int max_vid;
	unsigned int port_base_addr;
	unsigned int phy_base_addr;
	unsigned int global1_addr;
	unsigned int global2_addr;
	unsigned int age_time_coeff;
	unsigned int g1_irqs;
	unsigned int g2_irqs;
	bool pvt;

	/* Multi-chip Addressing Mode.
	 * Some chips respond to only 2 registers of its own SMI device address
	 * when it is non-zero, and use indirect access to internal registers.
	 */
	bool multi_chip;
	enum dsa_tag_protocol tag_protocol;

	/* Mask for FromPort and ToPort value of PortVec used in ATU Move
	 * operation. 0 means that the ATU Move operation is not supported.
	 */
	u8 atu_move_port_mask;
	const struct mv88e6xxx_ops *ops;

	/* Supports PTP */
	bool ptp_support;
};

struct mv88e6xxx_atu_entry {
	u8	state;
	bool	trunk;
	u16	portvec;
	u8	mac[ETH_ALEN];
};

struct mv88e6xxx_vtu_entry {
	u16	vid;
	u16	fid;
	u8	sid;
	bool	valid;
	u8	member[DSA_MAX_PORTS];
	u8	state[DSA_MAX_PORTS];
};

struct mv88e6xxx_bus_ops;
struct mv88e6xxx_irq_ops;
struct mv88e6xxx_gpio_ops;
struct mv88e6xxx_avb_ops;
struct mv88e6xxx_ptp_ops;

struct mv88e6xxx_irq {
	u16 masked;
	struct irq_chip chip;
	struct irq_domain *domain;
	unsigned int nirqs;
};

/* state flags for mv88e6xxx_port_hwtstamp::state */
enum {
	MV88E6XXX_HWTSTAMP_ENABLED,
	MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
};

struct mv88e6xxx_port_hwtstamp {
	/* Port index */
	int port_id;

	/* Timestamping state */
	unsigned long state;

	/* Resources for receive timestamping */
	struct sk_buff_head rx_queue;
	struct sk_buff_head rx_queue2;

	/* Resources for transmit timestamping */
	unsigned long tx_tstamp_start;
	struct sk_buff *tx_skb;
	u16 tx_seq_id;

	/* Current timestamp configuration */
	struct hwtstamp_config tstamp_config;
};

struct mv88e6xxx_port {
	struct mv88e6xxx_chip *chip;
	int port;
	u64 serdes_stats[2];
	u64 atu_member_violation;
	u64 atu_miss_violation;
	u64 atu_full_violation;
	u64 vtu_member_violation;
	u64 vtu_miss_violation;
	u8 cmode;
	int serdes_irq;
};

struct mv88e6xxx_chip {
	const struct mv88e6xxx_info *info;

	/* The dsa_switch this private structure is related to */
	struct dsa_switch *ds;

	/* The device this structure is associated to */
	struct device *dev;

	/* This mutex protects the access to the switch registers */
	struct mutex reg_lock;

	/* The MII bus and the address on the bus that is used to
	 * communication with the switch
	 */
	const struct mv88e6xxx_bus_ops *smi_ops;
	struct mii_bus *bus;
	int sw_addr;

	/* Handles automatic disabling and re-enabling of the PHY
	 * polling unit.
	 */
	const struct mv88e6xxx_bus_ops *phy_ops;
	struct mutex		ppu_mutex;
	int			ppu_disabled;
	struct work_struct	ppu_work;
	struct timer_list	ppu_timer;

	/* This mutex serialises access to the statistics unit.
	 * Hold this mutex over snapshot + dump sequences.
	 */
	struct mutex	stats_mutex;

	/* A switch may have a GPIO line tied to its reset pin. Parse
	 * this from the device tree, and use it before performing
	 * switch soft reset.
	 */
	struct gpio_desc *reset;

	/* set to size of eeprom if supported by the switch */
	u32 eeprom_len;

	/* List of mdio busses */
	struct list_head mdios;

	/* There can be two interrupt controllers, which are chained
	 * off a GPIO as interrupt source
	 */
	struct mv88e6xxx_irq g1_irq;
	struct mv88e6xxx_irq g2_irq;
	int irq;
	int device_irq;
	int watchdog_irq;

	int atu_prob_irq;
	int vtu_prob_irq;
	struct kthread_worker *kworker;
	struct kthread_delayed_work irq_poll_work;

	/* GPIO resources */
	u8 gpio_data[2];

	/* This cyclecounter abstracts the switch PTP time.
	 * reg_lock must be held for any operation that read()s.
	 */
	struct cyclecounter	tstamp_cc;
	struct timecounter	tstamp_tc;
	struct delayed_work	overflow_work;

	struct ptp_clock	*ptp_clock;
	struct ptp_clock_info	ptp_clock_info;
	struct delayed_work	tai_event_work;
	struct ptp_pin_desc	pin_config[MV88E6XXX_MAX_GPIO];
	u16 trig_config;
	u16 evcap_config;
	u16 enable_count;

	/* Per-port timestamping resources. */
	struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];

	/* Array of port structures. */
	struct mv88e6xxx_port ports[DSA_MAX_PORTS];
};

struct mv88e6xxx_bus_ops {
	int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
	int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
};

struct mv88e6xxx_mdio_bus {
	struct mii_bus *bus;
	struct mv88e6xxx_chip *chip;
	struct list_head list;
	bool external;
};

struct mv88e6xxx_ops {
	/* Switch Setup Errata, called early in the switch setup to
	 * allow any errata actions to be performed
	 */
	int (*setup_errata)(struct mv88e6xxx_chip *chip);

	int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
	int (*ip_pri_map)(struct mv88e6xxx_chip *chip);

	/* Ingress Rate Limit unit (IRL) operations */
	int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);

	int (*get_eeprom)(struct mv88e6xxx_chip *chip,
			  struct ethtool_eeprom *eeprom, u8 *data);
	int (*set_eeprom)(struct mv88e6xxx_chip *chip,
			  struct ethtool_eeprom *eeprom, u8 *data);

	int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);

	int (*phy_read)(struct mv88e6xxx_chip *chip,
			struct mii_bus *bus,
			int addr, int reg, u16 *val);
	int (*phy_write)(struct mv88e6xxx_chip *chip,
			 struct mii_bus *bus,
			 int addr, int reg, u16 val);

	/* Priority Override Table operations */
	int (*pot_clear)(struct mv88e6xxx_chip *chip);

	/* PHY Polling Unit (PPU) operations */
	int (*ppu_enable)(struct mv88e6xxx_chip *chip);
	int (*ppu_disable)(struct mv88e6xxx_chip *chip);

	/* Switch Software Reset */
	int (*reset)(struct mv88e6xxx_chip *chip);

	/* RGMII Receive/Transmit Timing Control
	 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
	 */
	int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
				    phy_interface_t mode);

#define LINK_FORCED_DOWN	0
#define LINK_FORCED_UP		1
#define LINK_UNFORCED		-2

	/* Port's MAC link state
	 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
	 * or LINK_UNFORCED for normal link detection.
	 */
	int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);

#define DUPLEX_UNFORCED		-2

	/* Port's MAC duplex mode
	 *
	 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
	 * or DUPLEX_UNFORCED for normal duplex detection.
	 */
	int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);

#define PAUSE_ON		1
#define PAUSE_OFF		0

	/* Enable/disable sending Pause */
	int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
			      int pause);

#define SPEED_MAX		INT_MAX
#define SPEED_UNFORCED		-2

	/* Port's MAC speed (in Mbps)
	 *
	 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
	 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
	 */
	int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);

	/* What interface mode should be used for maximum speed? */
	phy_interface_t (*port_max_speed_mode)(int port);

	int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);

	int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
				   enum mv88e6xxx_frame_mode mode);
	int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
				      bool unicast, bool multicast);
	int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
				   u16 etype);
	int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
				   size_t size);

	int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
	int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
				u8 out);
	int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
	int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);

	/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
	 * Some chips allow this to be configured on specific ports.
	 */
	int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
			      phy_interface_t mode);
	int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);

	/* Some devices have a per port register indicating what is
	 * the upstream port this port should forward to.
	 */
	int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
				      int upstream_port);
	/* Return the port link state, as required by phylink */
	int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
			       struct phylink_link_state *state);

	/* Snapshot the statistics for a port. The statistics can then
	 * be read back a leisure but still with a consistent view.
	 */
	int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);

	/* Set the histogram mode for statistics, when the control registers
	 * are separated out of the STATS_OP register.
	 */
	int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);

	/* Return the number of strings describing statistics */
	int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
	int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
	int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
			       uint64_t *data);
	int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
	int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);

#define MV88E6XXX_CASCADE_PORT_NONE		0xe
#define MV88E6XXX_CASCADE_PORT_MULTIPLE		0xf

	int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);

	const struct mv88e6xxx_irq_ops *watchdog_ops;

	int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);

	/* Power on/off a SERDES interface */
	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);

	/* SERDES interrupt handling */
	int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port);
	void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port);

	/* Statistics from the SERDES interface */
	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
	int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
				  uint8_t *data);
	int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
				uint64_t *data);

	/* VLAN Translation Unit operations */
	int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
			   struct mv88e6xxx_vtu_entry *entry);
	int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
			     struct mv88e6xxx_vtu_entry *entry);

	/* GPIO operations */
	const struct mv88e6xxx_gpio_ops *gpio_ops;

	/* Interface to the AVB/PTP registers */
	const struct mv88e6xxx_avb_ops *avb_ops;

	/* Remote Management Unit operations */
	int (*rmu_disable)(struct mv88e6xxx_chip *chip);

	/* Precision Time Protocol operations */
	const struct mv88e6xxx_ptp_ops *ptp_ops;

	/* Phylink */
	void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
				 unsigned long *mask,
				 struct phylink_link_state *state);
};

struct mv88e6xxx_irq_ops {
	/* Action to be performed when the interrupt happens */
	int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
	/* Setup the hardware to generate the interrupt */
	int (*irq_setup)(struct mv88e6xxx_chip *chip);
	/* Reset the hardware to stop generating the interrupt */
	void (*irq_free)(struct mv88e6xxx_chip *chip);
};

struct mv88e6xxx_gpio_ops {
	/* Get/set data on GPIO pin */
	int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
	int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
			int value);

	/* get/set GPIO direction */
	int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
	int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
		       bool input);

	/* get/set GPIO pin control */
	int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
			int *func);
	int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
			int func);
};

struct mv88e6xxx_avb_ops {
	/* Access port-scoped Precision Time Protocol registers */
	int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
			     u16 *data, int len);
	int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
			      u16 data);

	/* Access global Precision Time Protocol registers */
	int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
			int len);
	int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);

	/* Access global Time Application Interface registers */
	int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
			int len);
	int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
};

struct mv88e6xxx_ptp_ops {
	u64 (*clock_read)(const struct cyclecounter *cc);
	int (*ptp_enable)(struct ptp_clock_info *ptp,
			  struct ptp_clock_request *rq, int on);
	int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
			  enum ptp_pin_function func, unsigned int chan);
	void (*event_work)(struct work_struct *ugly);
	int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
	int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
	int (*global_enable)(struct mv88e6xxx_chip *chip);
	int (*global_disable)(struct mv88e6xxx_chip *chip);
	int n_ext_ts;
	int arr0_sts_reg;
	int arr1_sts_reg;
	int dep_sts_reg;
	u32 rx_filters;
};

#define STATS_TYPE_PORT		BIT(0)
#define STATS_TYPE_BANK0	BIT(1)
#define STATS_TYPE_BANK1	BIT(2)

struct mv88e6xxx_hw_stat {
	char string[ETH_GSTRING_LEN];
	size_t size;
	int reg;
	int type;
};

static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
{
	return chip->info->pvt;
}

static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
{
	return chip->info->num_databases;
}

static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
{
	return chip->info->num_ports;
}

static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
{
	return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
}

static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
{
	return chip->info->num_gpio;
}

int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
		     u16 update);
int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
			     int speed, int duplex, int pause,
			     phy_interface_t mode);
struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);

#endif /* _MV88E6XXX_CHIP_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
91da11f8	2	/*
4d5f2ba7	3	* Marvell 88E6xxx Ethernet switch single-chip definition
0d3cd4b6	4	*
91da11f8	5	* Copyright (c) 2008 Marvell Semiconductor
91da11f8 LB	6	*/
91da11f8 LB	7
4d5f2ba7 VD	8	#ifndef _MV88E6XXX_CHIP_H
4d5f2ba7 VD	9	#define _MV88E6XXX_CHIP_H
91da11f8	10
194fea7b	11	#include <linux/if_vlan.h>
dc30c35b	12	#include <linux/irq.h>
52638f71	13	#include <linux/gpio/consumer.h>
294d711e	14	#include <linux/kthread.h>
4d56a29f	15	#include <linux/phy.h>
2fa8d3af BS	16	#include <linux/ptp_clock_kernel.h>
2fa8d3af BS	17	#include <linux/timecounter.h>
c6e970a0	18	#include <net/dsa.h>
194fea7b	19
3285f9e8 VD	20	#define MV88E6XXX_N_FID 4096
3285f9e8 VD	21
17a1594e VD	22	/* PVT limits for 4-bit port and 5-bit switch */
	23	#define MV88E6XXX_MAX_PVT_SWITCHES 32
	24	#define MV88E6XXX_MAX_PVT_PORTS 16
	25
a73ccd61 BS	26	#define MV88E6XXX_MAX_GPIO 16
a73ccd61 BS	27
31bef4e9 VD	28	enum mv88e6xxx_egress_mode {
	29	MV88E6XXX_EGRESS_MODE_UNMODIFIED,
	30	MV88E6XXX_EGRESS_MODE_UNTAGGED,
	31	MV88E6XXX_EGRESS_MODE_TAGGED,
	32	MV88E6XXX_EGRESS_MODE_ETHERTYPE,
	33	};
	34
56995cbc AL	35	enum mv88e6xxx_frame_mode {
	36	MV88E6XXX_FRAME_MODE_NORMAL,
	37	MV88E6XXX_FRAME_MODE_DSA,
	38	MV88E6XXX_FRAME_MODE_PROVIDER,
	39	MV88E6XXX_FRAME_MODE_ETHERTYPE,
	40	};
	41
f81ec90f VD	42	/* List of supported models */
	43	enum mv88e6xxx_model {
	44	MV88E6085,
	45	MV88E6095,
7d381a02	46	MV88E6097,
f81ec90f VD	47	MV88E6123,
f81ec90f VD	48	MV88E6131,
1558727a	49	MV88E6141,
f81ec90f VD	50	MV88E6161,
	51	MV88E6165,
	52	MV88E6171,
	53	MV88E6172,
	54	MV88E6175,
	55	MV88E6176,
	56	MV88E6185,
1a3b39ec AL	57	MV88E6190,
	58	MV88E6190X,
	59	MV88E6191,
f81ec90f	60	MV88E6240,
1a3b39ec	61	MV88E6290,
f81ec90f VD	62	MV88E6320,
f81ec90f VD	63	MV88E6321,
a75961d0	64	MV88E6341,
f81ec90f VD	65	MV88E6350,
	66	MV88E6351,
	67	MV88E6352,
1a3b39ec AL	68	MV88E6390,
1a3b39ec AL	69	MV88E6390X,
f81ec90f VD	70	};
f81ec90f VD	71
22356476 VD	72	enum mv88e6xxx_family {
	73	MV88E6XXX_FAMILY_NONE,
	74	MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
	75	MV88E6XXX_FAMILY_6095, /* 6092 6095 */
	76	MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
	77	MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
	78	MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
	79	MV88E6XXX_FAMILY_6320, /* 6320 6321 */
a75961d0	80	MV88E6XXX_FAMILY_6341, /* 6141 6341 */
22356476 VD	81	MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
22356476 VD	82	MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
1a3b39ec	83	MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
22356476 VD	84	};
22356476 VD	85
c0e4dadb AL	86	struct mv88e6xxx_ops;
c0e4dadb AL	87
f6271e67	88	struct mv88e6xxx_info {
22356476	89	enum mv88e6xxx_family family;
f6271e67 VD	90	u16 prod_num;
f6271e67 VD	91	const char *name;
cd5a2c82	92	unsigned int num_databases;
009a2b98	93	unsigned int num_ports;
bc393155	94	unsigned int num_internal_phys;
a73ccd61	95	unsigned int num_gpio;
3cf3c846	96	unsigned int max_vid;
9dddd478	97	unsigned int port_base_addr;
9255bacd	98	unsigned int phy_base_addr;
a935c052	99	unsigned int global1_addr;
9069c13a	100	unsigned int global2_addr;
acddbd21	101	unsigned int age_time_coeff;
dc30c35b	102	unsigned int g1_irqs;
d6c5e6af	103	unsigned int g2_irqs;
f3645652	104	bool pvt;
b3e05aa1 VD	105
	106	/* Multi-chip Addressing Mode.
	107	* Some chips respond to only 2 registers of its own SMI device address
	108	* when it is non-zero, and use indirect access to internal registers.
	109	*/
	110	bool multi_chip;
443d5a1b	111	enum dsa_tag_protocol tag_protocol;
e606ca36 VD	112
	113	/* Mask for FromPort and ToPort value of PortVec used in ATU Move
	114	* operation. 0 means that the ATU Move operation is not supported.
	115	*/
	116	u8 atu_move_port_mask;
b3469dd8	117	const struct mv88e6xxx_ops *ops;
2fa8d3af BS	118
	119	/* Supports PTP */
	120	bool ptp_support;
b9b37713 VD	121	};
b9b37713 VD	122
fd231c82	123	struct mv88e6xxx_atu_entry {
fd231c82 VD	124	u8 state;
fd231c82 VD	125	bool trunk;
01bd96c8	126	u16 portvec;
fd231c82 VD	127	u8 mac[ETH_ALEN];
	128	};
	129
b4e47c0f	130	struct mv88e6xxx_vtu_entry {
b8fee957 VD	131	u16 vid;
b8fee957 VD	132	u16 fid;
b8fee957 VD	133	u8 sid;
b8fee957 VD	134	bool valid;
bd00e053 VD	135	u8 member[DSA_MAX_PORTS];
bd00e053 VD	136	u8 state[DSA_MAX_PORTS];
b8fee957 VD	137	};
b8fee957 VD	138
c08026ab	139	struct mv88e6xxx_bus_ops;
fcd25166	140	struct mv88e6xxx_irq_ops;
a73ccd61	141	struct mv88e6xxx_gpio_ops;
0d632c3d	142	struct mv88e6xxx_avb_ops;
6d2ac8ee	143	struct mv88e6xxx_ptp_ops;
914b32f6	144
dc30c35b AL	145	struct mv88e6xxx_irq {
	146	u16 masked;
	147	struct irq_chip chip;
	148	struct irq_domain *domain;
	149	unsigned int nirqs;
	150	};
	151
c6fe0ad2 BS	152	/* state flags for mv88e6xxx_port_hwtstamp::state */
	153	enum {
	154	MV88E6XXX_HWTSTAMP_ENABLED,
	155	MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
	156	};
	157
	158	struct mv88e6xxx_port_hwtstamp {
	159	/* Port index */
	160	int port_id;
	161
	162	/* Timestamping state */
	163	unsigned long state;
	164
	165	/* Resources for receive timestamping */
	166	struct sk_buff_head rx_queue;
	167	struct sk_buff_head rx_queue2;
	168
	169	/* Resources for transmit timestamping */
	170	unsigned long tx_tstamp_start;
	171	struct sk_buff *tx_skb;
	172	u16 tx_seq_id;
	173
	174	/* Current timestamp configuration */
	175	struct hwtstamp_config tstamp_config;
	176	};
	177
cda9f4aa	178	struct mv88e6xxx_port {
7b898469 AL	179	struct mv88e6xxx_chip *chip;
7b898469 AL	180	int port;
cda9f4aa	181	u64 serdes_stats[2];
65f60e45 AL	182	u64 atu_member_violation;
	183	u64 atu_miss_violation;
	184	u64 atu_full_violation;
	185	u64 vtu_member_violation;
	186	u64 vtu_miss_violation;
2d2e1dd2	187	u8 cmode;
efd1ba6a	188	int serdes_irq;
cda9f4aa AL	189	};
cda9f4aa AL	190
fad09c73	191	struct mv88e6xxx_chip {
f6271e67 VD	192	const struct mv88e6xxx_info *info;
f6271e67 VD	193
7543a6d5 AL	194	/* The dsa_switch this private structure is related to */
	195	struct dsa_switch *ds;
	196
158bc065 AL	197	/* The device this structure is associated to */
	198	struct device *dev;
	199
9f8b3ee1 VD	200	/* This mutex protects the access to the switch registers */
9f8b3ee1 VD	201	struct mutex reg_lock;
91da11f8	202
a77d43f1 AL	203	/* The MII bus and the address on the bus that is used to
	204	* communication with the switch
	205	*/
c08026ab	206	const struct mv88e6xxx_bus_ops *smi_ops;
a77d43f1 AL	207	struct mii_bus *bus;
	208	int sw_addr;
	209
3675c8d7	210	/* Handles automatic disabling and re-enabling of the PHY
2e5f0320 LB	211	* polling unit.
2e5f0320 LB	212	*/
c08026ab	213	const struct mv88e6xxx_bus_ops *phy_ops;
2e5f0320 LB	214	struct mutex ppu_mutex;
	215	int ppu_disabled;
	216	struct work_struct ppu_work;
	217	struct timer_list ppu_timer;
2e5f0320	218
3675c8d7	219	/* This mutex serialises access to the statistics unit.
91da11f8 LB	220	* Hold this mutex over snapshot + dump sequences.
	221	*/
	222	struct mutex stats_mutex;
3ad50cca	223
52638f71 AL	224	/* A switch may have a GPIO line tied to its reset pin. Parse
	225	* this from the device tree, and use it before performing
	226	* switch soft reset.
	227	*/
	228	struct gpio_desc *reset;
f8cd8753 AL	229
f8cd8753 AL	230	/* set to size of eeprom if supported by the switch */
00baabe5	231	u32 eeprom_len;
b516d453	232
a3c53be5 AL	233	/* List of mdio busses */
a3c53be5 AL	234	struct list_head mdios;
dc30c35b AL	235
	236	/* There can be two interrupt controllers, which are chained
	237	* off a GPIO as interrupt source
	238	*/
	239	struct mv88e6xxx_irq g1_irq;
	240	struct mv88e6xxx_irq g2_irq;
	241	int irq;
8e757eba	242	int device_irq;
fcd25166	243	int watchdog_irq;
cda9f4aa	244
0977644c	245	int atu_prob_irq;
62eb1162	246	int vtu_prob_irq;
294d711e AL	247	struct kthread_worker *kworker;
294d711e AL	248	struct kthread_delayed_work irq_poll_work;
2fa8d3af	249
a73ccd61 BS	250	/* GPIO resources */
	251	u8 gpio_data[2];
	252
2fa8d3af BS	253	/* This cyclecounter abstracts the switch PTP time.
	254	* reg_lock must be held for any operation that read()s.
	255	*/
	256	struct cyclecounter tstamp_cc;
	257	struct timecounter tstamp_tc;
	258	struct delayed_work overflow_work;
	259
	260	struct ptp_clock *ptp_clock;
	261	struct ptp_clock_info ptp_clock_info;
4eb3be29 BS	262	struct delayed_work tai_event_work;
	263	struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
	264	u16 trig_config;
	265	u16 evcap_config;
e2294a8b	266	u16 enable_count;
c6fe0ad2 BS	267
	268	/* Per-port timestamping resources. */
	269	struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
cda9f4aa AL	270
	271	/* Array of port structures. */
	272	struct mv88e6xxx_port ports[DSA_MAX_PORTS];
91da11f8 LB	273	};
91da11f8 LB	274
c08026ab	275	struct mv88e6xxx_bus_ops {
fad09c73 VD	276	int (read)(struct mv88e6xxx_chip chip, int addr, int reg, u16 *val);
fad09c73 VD	277	int (write)(struct mv88e6xxx_chip chip, int addr, int reg, u16 val);
914b32f6 VD	278	};
914b32f6 VD	279
0dd12d54	280	struct mv88e6xxx_mdio_bus {
a3c53be5	281	struct mii_bus *bus;
0dd12d54	282	struct mv88e6xxx_chip *chip;
a3c53be5 AL	283	struct list_head list;
a3c53be5 AL	284	bool external;
0dd12d54 AL	285	};
0dd12d54 AL	286
b3469dd8	287	struct mv88e6xxx_ops {
ea89098e AL	288	/* Switch Setup Errata, called early in the switch setup to
	289	* allow any errata actions to be performed
	290	*/
	291	int (setup_errata)(struct mv88e6xxx_chip chip);
	292
93e18d61 VD	293	int (ieee_pri_map)(struct mv88e6xxx_chip chip);
	294	int (ip_pri_map)(struct mv88e6xxx_chip chip);
	295
cd8da8bb VD	296	/* Ingress Rate Limit unit (IRL) operations */
	297	int (irl_init_all)(struct mv88e6xxx_chip chip, int port);
	298
ee4dc2e7 VD	299	int (get_eeprom)(struct mv88e6xxx_chip chip,
	300	struct ethtool_eeprom eeprom, u8 data);
	301	int (set_eeprom)(struct mv88e6xxx_chip chip,
	302	struct ethtool_eeprom eeprom, u8 data);
	303
b073d4e2 VD	304	int (set_switch_mac)(struct mv88e6xxx_chip chip, u8 *addr);
b073d4e2 VD	305
ee26a228 AL	306	int (phy_read)(struct mv88e6xxx_chip chip,
	307	struct mii_bus *bus,
	308	int addr, int reg, u16 *val);
	309	int (phy_write)(struct mv88e6xxx_chip chip,
	310	struct mii_bus *bus,
	311	int addr, int reg, u16 val);
08ef7f10	312
9e907d73 VD	313	/* Priority Override Table operations */
	314	int (pot_clear)(struct mv88e6xxx_chip chip);
	315
a199d8b6 VD	316	/* PHY Polling Unit (PPU) operations */
	317	int (ppu_enable)(struct mv88e6xxx_chip chip);
	318	int (ppu_disable)(struct mv88e6xxx_chip chip);
	319
17e708ba VD	320	/* Switch Software Reset */
	321	int (reset)(struct mv88e6xxx_chip chip);
	322
a0a0f622 VD	323	/* RGMII Receive/Transmit Timing Control
	324	* Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
	325	*/
	326	int (port_set_rgmii_delay)(struct mv88e6xxx_chip chip, int port,
	327	phy_interface_t mode);
	328
08ef7f10 VD	329	#define LINK_FORCED_DOWN 0
	330	#define LINK_FORCED_UP 1
	331	#define LINK_UNFORCED -2
	332
	333	/* Port's MAC link state
	334	* Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
	335	* or LINK_UNFORCED for normal link detection.
	336	*/
	337	int (port_set_link)(struct mv88e6xxx_chip chip, int port, int link);
7f1ae07b VD	338
	339	#define DUPLEX_UNFORCED -2
	340
	341	/* Port's MAC duplex mode
	342	*
	343	* Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
	344	* or DUPLEX_UNFORCED for normal duplex detection.
	345	*/
	346	int (port_set_duplex)(struct mv88e6xxx_chip chip, int port, int dup);
96a2b40c	347
54186b91 AL	348	#define PAUSE_ON 1
	349	#define PAUSE_OFF 0
	350
	351	/* Enable/disable sending Pause */
	352	int (port_set_pause)(struct mv88e6xxx_chip chip, int port,
	353	int pause);
	354
96a2b40c VD	355	#define SPEED_MAX INT_MAX
	356	#define SPEED_UNFORCED -2
	357
	358	/* Port's MAC speed (in Mbps)
	359	*
	360	* Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
	361	* Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
	362	*/
	363	int (port_set_speed)(struct mv88e6xxx_chip chip, int port, int speed);
a605a0fe	364
7cbbee05 AL	365	/* What interface mode should be used for maximum speed? */
	366	phy_interface_t (*port_max_speed_mode)(int port);
	367
ef0a7318 AL	368	int (port_tag_remap)(struct mv88e6xxx_chip chip, int port);
ef0a7318 AL	369
56995cbc AL	370	int (port_set_frame_mode)(struct mv88e6xxx_chip chip, int port,
56995cbc AL	371	enum mv88e6xxx_frame_mode mode);
601aeed3 VD	372	int (port_set_egress_floods)(struct mv88e6xxx_chip chip, int port,
601aeed3 VD	373	bool unicast, bool multicast);
56995cbc AL	374	int (port_set_ether_type)(struct mv88e6xxx_chip chip, int port,
56995cbc AL	375	u16 etype);
cd782656 VD	376	int (port_set_jumbo_size)(struct mv88e6xxx_chip chip, int port,
cd782656 VD	377	size_t size);
56995cbc	378
ef70b111	379	int (port_egress_rate_limiting)(struct mv88e6xxx_chip chip, int port);
0898432c VD	380	int (port_pause_limit)(struct mv88e6xxx_chip chip, int port, u8 in,
0898432c VD	381	u8 out);
c8c94891	382	int (port_disable_learn_limit)(struct mv88e6xxx_chip chip, int port);
9dbfb4e1	383	int (port_disable_pri_override)(struct mv88e6xxx_chip chip, int port);
ef70b111	384
f39908d3 AL	385	/* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
	386	* Some chips allow this to be configured on specific ports.
	387	*/
	388	int (port_set_cmode)(struct mv88e6xxx_chip chip, int port,
	389	phy_interface_t mode);
2d2e1dd2	390	int (port_get_cmode)(struct mv88e6xxx_chip chip, int port, u8 *cmode);
f39908d3	391
a23b2961 AL	392	/* Some devices have a per port register indicating what is
	393	* the upstream port this port should forward to.
	394	*/
	395	int (port_set_upstream_port)(struct mv88e6xxx_chip chip, int port,
	396	int upstream_port);
6c422e34 RK	397	/* Return the port link state, as required by phylink */
	398	int (port_link_state)(struct mv88e6xxx_chip chip, int port,
	399	struct phylink_link_state *state);
a23b2961	400
a605a0fe AL	401	/* Snapshot the statistics for a port. The statistics can then
	402	* be read back a leisure but still with a consistent view.
	403	*/
	404	int (stats_snapshot)(struct mv88e6xxx_chip chip, int port);
de227387 AL	405
	406	/* Set the histogram mode for statistics, when the control registers
	407	* are separated out of the STATS_OP register.
	408	*/
	409	int (stats_set_histogram)(struct mv88e6xxx_chip chip);
b3469dd8	410
dfafe449 AL	411	/* Return the number of strings describing statistics */
dfafe449 AL	412	int (stats_get_sset_count)(struct mv88e6xxx_chip chip);
436fe17d AL	413	int (stats_get_strings)(struct mv88e6xxx_chip chip, uint8_t *data);
	414	int (stats_get_stats)(struct mv88e6xxx_chip chip, int port,
	415	uint64_t *data);
fa8d1179 VD	416	int (set_cpu_port)(struct mv88e6xxx_chip chip, int port);
fa8d1179 VD	417	int (set_egress_port)(struct mv88e6xxx_chip chip, int port);
02317e68 VD	418
	419	#define MV88E6XXX_CASCADE_PORT_NONE 0xe
	420	#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
	421
	422	int (set_cascade_port)(struct mv88e6xxx_chip chip, int port);
	423
fcd25166	424	const struct mv88e6xxx_irq_ops *watchdog_ops;
6e55f698	425
6e55f698	426	int (mgmt_rsvd2cpu)(struct mv88e6xxx_chip chip);
f1394b78	427
6d91782f AL	428	/* Power on/off a SERDES interface */
	429	int (serdes_power)(struct mv88e6xxx_chip chip, int port, bool on);
	430
efd1ba6a AL	431	/* SERDES interrupt handling */
	432	int (serdes_irq_setup)(struct mv88e6xxx_chip chip, int port);
	433	void (serdes_irq_free)(struct mv88e6xxx_chip chip, int port);
	434
436fe17d AL	435	/* Statistics from the SERDES interface */
436fe17d AL	436	int (serdes_get_sset_count)(struct mv88e6xxx_chip chip, int port);
65f60e45 AL	437	int (serdes_get_strings)(struct mv88e6xxx_chip chip, int port,
	438	uint8_t *data);
	439	int (serdes_get_stats)(struct mv88e6xxx_chip chip, int port,
	440	uint64_t *data);
436fe17d	441
f1394b78 VD	442	/* VLAN Translation Unit operations */
	443	int (vtu_getnext)(struct mv88e6xxx_chip chip,
	444	struct mv88e6xxx_vtu_entry *entry);
0ad5daf6 VD	445	int (vtu_loadpurge)(struct mv88e6xxx_chip chip,
0ad5daf6 VD	446	struct mv88e6xxx_vtu_entry *entry);
0d632c3d	447
a73ccd61 BS	448	/* GPIO operations */
	449	const struct mv88e6xxx_gpio_ops *gpio_ops;
	450
0d632c3d BS	451	/* Interface to the AVB/PTP registers */
0d632c3d BS	452	const struct mv88e6xxx_avb_ops *avb_ops;
9e5baf9b VD	453
	454	/* Remote Management Unit operations */
	455	int (rmu_disable)(struct mv88e6xxx_chip chip);
6d2ac8ee AL	456
	457	/* Precision Time Protocol operations */
	458	const struct mv88e6xxx_ptp_ops *ptp_ops;
6c422e34 RK	459
	460	/* Phylink */
	461	void (phylink_validate)(struct mv88e6xxx_chip chip, int port,
	462	unsigned long *mask,
	463	struct phylink_link_state *state);
f5e2ed02 AL	464	};
f5e2ed02 AL	465
fcd25166 AL	466	struct mv88e6xxx_irq_ops {
	467	/* Action to be performed when the interrupt happens */
	468	int (irq_action)(struct mv88e6xxx_chip chip, int irq);
	469	/* Setup the hardware to generate the interrupt */
	470	int (irq_setup)(struct mv88e6xxx_chip chip);
	471	/* Reset the hardware to stop generating the interrupt */
	472	void (irq_free)(struct mv88e6xxx_chip chip);
	473	};
	474
a73ccd61 BS	475	struct mv88e6xxx_gpio_ops {
	476	/* Get/set data on GPIO pin */
	477	int (get_data)(struct mv88e6xxx_chip chip, unsigned int pin);
	478	int (set_data)(struct mv88e6xxx_chip chip, unsigned int pin,
	479	int value);
	480
	481	/* get/set GPIO direction */
	482	int (get_dir)(struct mv88e6xxx_chip chip, unsigned int pin);
	483	int (set_dir)(struct mv88e6xxx_chip chip, unsigned int pin,
	484	bool input);
	485
	486	/* get/set GPIO pin control */
	487	int (get_pctl)(struct mv88e6xxx_chip chip, unsigned int pin,
	488	int *func);
	489	int (set_pctl)(struct mv88e6xxx_chip chip, unsigned int pin,
	490	int func);
	491	};
	492
0d632c3d BS	493	struct mv88e6xxx_avb_ops {
	494	/* Access port-scoped Precision Time Protocol registers */
	495	int (port_ptp_read)(struct mv88e6xxx_chip chip, int port, int addr,
	496	u16 *data, int len);
	497	int (port_ptp_write)(struct mv88e6xxx_chip chip, int port, int addr,
	498	u16 data);
	499
	500	/* Access global Precision Time Protocol registers */
	501	int (ptp_read)(struct mv88e6xxx_chip chip, int addr, u16 *data,
	502	int len);
	503	int (ptp_write)(struct mv88e6xxx_chip chip, int addr, u16 data);
	504
	505	/* Access global Time Application Interface registers */
	506	int (tai_read)(struct mv88e6xxx_chip chip, int addr, u16 *data,
	507	int len);
	508	int (tai_write)(struct mv88e6xxx_chip chip, int addr, u16 data);
	509	};
	510
6d2ac8ee AL	511	struct mv88e6xxx_ptp_ops {
	512	u64 (clock_read)(const struct cyclecounter cc);
	513	int (ptp_enable)(struct ptp_clock_info ptp,
	514	struct ptp_clock_request *rq, int on);
	515	int (ptp_verify)(struct ptp_clock_info ptp, unsigned int pin,
	516	enum ptp_pin_function func, unsigned int chan);
	517	void (event_work)(struct work_struct ugly);
ffc705de AL	518	int (port_enable)(struct mv88e6xxx_chip chip, int port);
ffc705de AL	519	int (port_disable)(struct mv88e6xxx_chip chip, int port);
e2294a8b AL	520	int (global_enable)(struct mv88e6xxx_chip chip);
e2294a8b AL	521	int (global_disable)(struct mv88e6xxx_chip chip);
6d2ac8ee	522	int n_ext_ts;
ffc705de AL	523	int arr0_sts_reg;
	524	int arr1_sts_reg;
	525	int dep_sts_reg;
48cb5e03	526	u32 rx_filters;
6d2ac8ee AL	527	};
6d2ac8ee AL	528
dfafe449 AL	529	#define STATS_TYPE_PORT BIT(0)
	530	#define STATS_TYPE_BANK0 BIT(1)
	531	#define STATS_TYPE_BANK1 BIT(2)
	532
91da11f8 LB	533	struct mv88e6xxx_hw_stat {
91da11f8 LB	534	char string[ETH_GSTRING_LEN];
cda9f4aa	535	size_t size;
91da11f8	536	int reg;
dfafe449	537	int type;
91da11f8 LB	538	};
91da11f8 LB	539
f3645652 VD	540	static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
	541	{
	542	return chip->info->pvt;
	543	}
	544
de33376b VD	545	static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
	546	{
	547	return chip->info->num_databases;
	548	}
	549
370b4ffb VD	550	static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
	551	{
	552	return chip->info->num_ports;
	553	}
	554
4d294af2 VD	555	static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
	556	{
	557	return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
	558	}
	559
a73ccd61 BS	560	static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
	561	{
	562	return chip->info->num_gpio;
	563	}
	564
ec561276 VD	565	int mv88e6xxx_read(struct mv88e6xxx_chip chip, int addr, int reg, u16 val);
	566	int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
	567	int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
	568	u16 update);
	569	int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
72d8b4fd HK	570	int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
	571	int speed, int duplex, int pause,
	572	phy_interface_t mode);
10fa5bfc	573	struct mii_bus mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip chip);
4d5f2ba7 VD	574
4d5f2ba7 VD	575	#endif /* _MV88E6XXX_CHIP_H */