[mirror_ubuntu-focal-kernel.git] / drivers / net / dsa / mv88e6xxx / global2.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Marvell 88E6xxx Switch Global 2 Registers support
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 */

#ifndef _MV88E6XXX_GLOBAL2_H
#define _MV88E6XXX_GLOBAL2_H

#include "chip.h"

/* Offset 0x00: Interrupt Source Register */
#define MV88E6XXX_G2_INT_SRC			0x00
#define MV88E6XXX_G2_INT_SRC_WDOG		0x8000
#define MV88E6XXX_G2_INT_SRC_JAM_LIMIT		0x4000
#define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH	0x2000
#define MV88E6XXX_G2_INT_SRC_WAKE_EVENT		0x1000
#define MV88E6352_G2_INT_SRC_SERDES		0x0800
#define MV88E6352_G2_INT_SRC_PHY		0x001f
#define MV88E6390_G2_INT_SRC_PHY		0x07fe

#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG	15

/* Offset 0x01: Interrupt Mask Register */
#define MV88E6XXX_G2_INT_MASK			0x01
#define MV88E6XXX_G2_INT_MASK_WDOG		0x8000
#define MV88E6XXX_G2_INT_MASK_JAM_LIMIT		0x4000
#define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH	0x2000
#define MV88E6XXX_G2_INT_MASK_WAKE_EVENT	0x1000
#define MV88E6352_G2_INT_MASK_SERDES		0x0800
#define MV88E6352_G2_INT_MASK_PHY		0x001f
#define MV88E6390_G2_INT_MASK_PHY		0x07fe

/* Offset 0x02: MGMT Enable Register 2x */
#define MV88E6XXX_G2_MGMT_EN_2X		0x02

/* Offset 0x03: MGMT Enable Register 0x */
#define MV88E6XXX_G2_MGMT_EN_0X		0x03

/* Offset 0x04: Flow Control Delay Register */
#define MV88E6XXX_G2_FLOW_CTL	0x04

/* Offset 0x05: Switch Management Register */
#define MV88E6XXX_G2_SWITCH_MGMT			0x05
#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA	0x8000
#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS		0x4000
#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG		0x2000
#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI	0x0080
#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU		0x0008

/* Offset 0x06: Device Mapping Table Register */
#define MV88E6XXX_G2_DEVICE_MAPPING		0x06
#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE	0x8000
#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK	0x1f00
#define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK	0x000f
#define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK	0x001f

/* Offset 0x07: Trunk Mask Table Register */
#define MV88E6XXX_G2_TRUNK_MASK			0x07
#define MV88E6XXX_G2_TRUNK_MASK_UPDATE		0x8000
#define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK	0x7000
#define MV88E6XXX_G2_TRUNK_MASK_HASH		0x0800

/* Offset 0x08: Trunk Mapping Table Register */
#define MV88E6XXX_G2_TRUNK_MAPPING		0x08
#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE	0x8000
#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK	0x7800

/* Offset 0x09: Ingress Rate Command Register */
#define MV88E6XXX_G2_IRL_CMD			0x09
#define MV88E6XXX_G2_IRL_CMD_BUSY		0x8000
#define MV88E6352_G2_IRL_CMD_OP_MASK		0x7000
#define MV88E6352_G2_IRL_CMD_OP_NOOP		0x0000
#define MV88E6352_G2_IRL_CMD_OP_INIT_ALL	0x1000
#define MV88E6352_G2_IRL_CMD_OP_INIT_RES	0x2000
#define MV88E6352_G2_IRL_CMD_OP_WRITE_REG	0x3000
#define MV88E6352_G2_IRL_CMD_OP_READ_REG	0x4000
#define MV88E6390_G2_IRL_CMD_OP_MASK		0x6000
#define MV88E6390_G2_IRL_CMD_OP_READ_REG	0x0000
#define MV88E6390_G2_IRL_CMD_OP_INIT_ALL	0x2000
#define MV88E6390_G2_IRL_CMD_OP_INIT_RES	0x4000
#define MV88E6390_G2_IRL_CMD_OP_WRITE_REG	0x6000
#define MV88E6352_G2_IRL_CMD_PORT_MASK		0x0f00
#define MV88E6390_G2_IRL_CMD_PORT_MASK		0x1f00
#define MV88E6XXX_G2_IRL_CMD_RES_MASK		0x00e0
#define MV88E6XXX_G2_IRL_CMD_REG_MASK		0x000f

/* Offset 0x0A: Ingress Rate Data Register */
#define MV88E6XXX_G2_IRL_DATA		0x0a
#define MV88E6XXX_G2_IRL_DATA_MASK	0xffff

/* Offset 0x0B: Cross-chip Port VLAN Register */
#define MV88E6XXX_G2_PVT_ADDR			0x0b
#define MV88E6XXX_G2_PVT_ADDR_BUSY		0x8000
#define MV88E6XXX_G2_PVT_ADDR_OP_MASK		0x7000
#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES	0x1000
#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN	0x3000
#define MV88E6XXX_G2_PVT_ADDR_OP_READ		0x4000
#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK		0x01ff

/* Offset 0x0C: Cross-chip Port VLAN Data Register */
#define MV88E6XXX_G2_PVT_DATA		0x0c
#define MV88E6XXX_G2_PVT_DATA_MASK	0x7f

/* Offset 0x0D: Switch MAC/WoL/WoF Register */
#define MV88E6XXX_G2_SWITCH_MAC			0x0d
#define MV88E6XXX_G2_SWITCH_MAC_UPDATE		0x8000
#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK	0x1f00
#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK	0x00ff

/* Offset 0x0E: ATU Stats Register */
#define MV88E6XXX_G2_ATU_STATS		0x0e

/* Offset 0x0F: Priority Override Table */
#define MV88E6XXX_G2_PRIO_OVERRIDE		0x0f
#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE	0x8000
#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET	0x1000
#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK	0x0f00
#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN	0x0080
#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK	0x0030
#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN	0x0008
#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK	0x0007

/* Offset 0x14: EEPROM Command */
#define MV88E6XXX_G2_EEPROM_CMD			0x14
#define MV88E6XXX_G2_EEPROM_CMD_BUSY		0x8000
#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK		0x7000
#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE	0x3000
#define MV88E6XXX_G2_EEPROM_CMD_OP_READ		0x4000
#define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD		0x6000
#define MV88E6XXX_G2_EEPROM_CMD_RUNNING		0x0800
#define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN	0x0400
#define MV88E6352_G2_EEPROM_CMD_ADDR_MASK	0x00ff
#define MV88E6390_G2_EEPROM_CMD_DATA_MASK	0x00ff

/* Offset 0x15: EEPROM Data */
#define MV88E6352_G2_EEPROM_DATA	0x15
#define MV88E6352_G2_EEPROM_DATA_MASK	0xffff

/* Offset 0x15: EEPROM Addr */
#define MV88E6390_G2_EEPROM_ADDR	0x15
#define MV88E6390_G2_EEPROM_ADDR_MASK	0xffff

/* Offset 0x16: AVB Command Register */
#define MV88E6352_G2_AVB_CMD			0x16
#define MV88E6352_G2_AVB_CMD_BUSY		0x8000
#define MV88E6352_G2_AVB_CMD_OP_READ		0x4000
#define MV88E6352_G2_AVB_CMD_OP_READ_INCR	0x6000
#define MV88E6352_G2_AVB_CMD_OP_WRITE		0x3000
#define MV88E6390_G2_AVB_CMD_OP_READ		0x0000
#define MV88E6390_G2_AVB_CMD_OP_READ_INCR	0x4000
#define MV88E6390_G2_AVB_CMD_OP_WRITE		0x6000
#define MV88E6352_G2_AVB_CMD_PORT_MASK		0x0f00
#define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL	0xe
#define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL	0xf
#define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL	0xf
#define MV88E6390_G2_AVB_CMD_PORT_MASK		0x1f00
#define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL	0x1e
#define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL	0x1f
#define MV88E6352_G2_AVB_CMD_BLOCK_PTP		0
#define MV88E6352_G2_AVB_CMD_BLOCK_AVB		1
#define MV88E6352_G2_AVB_CMD_BLOCK_QAV		2
#define MV88E6352_G2_AVB_CMD_BLOCK_QVB		3
#define MV88E6352_G2_AVB_CMD_BLOCK_MASK		0x00e0
#define MV88E6352_G2_AVB_CMD_ADDR_MASK		0x001f

/* Offset 0x17: AVB Data Register */
#define MV88E6352_G2_AVB_DATA		0x17

/* Offset 0x18: SMI PHY Command Register */
#define MV88E6XXX_G2_SMI_PHY_CMD			0x18
#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY			0x8000
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK		0x6000
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL		0x0000
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL		0x2000
#define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP		0x4000
#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK		0x1000
#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45		0x0000
#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22		0x1000
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK		0x0c00
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA	0x0400
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA	0x0800
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR	0x0000
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA	0x0400
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC	0x0800
#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA	0x0c00
#define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK		0x03e0
#define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK		0x001f
#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK		0x03ff

/* Offset 0x19: SMI PHY Data Register */
#define MV88E6XXX_G2_SMI_PHY_DATA	0x19

/* Offset 0x1A: Scratch and Misc. Register */
#define MV88E6XXX_G2_SCRATCH_MISC_MISC		0x1a
#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE	0x8000
#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK	0x7f00
#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK	0x00ff

/* Offset 0x1B: Watch Dog Control Register */
#define MV88E6352_G2_WDOG_CTL			0x1b
#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT	0x0080
#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT	0x0040
#define MV88E6352_G2_WDOG_CTL_QC_ENABLE		0x0020
#define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY	0x0010
#define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE	0x0008
#define MV88E6352_G2_WDOG_CTL_FORCE_IRQ		0x0004
#define MV88E6352_G2_WDOG_CTL_HISTORY		0x0002
#define MV88E6352_G2_WDOG_CTL_SWRESET		0x0001

/* Offset 0x1B: Watch Dog Control Register */
#define MV88E6390_G2_WDOG_CTL				0x1b
#define MV88E6390_G2_WDOG_CTL_UPDATE			0x8000
#define MV88E6390_G2_WDOG_CTL_PTR_MASK			0x7f00
#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE		0x0000
#define MV88E6390_G2_WDOG_CTL_PTR_INT_STS		0x1000
#define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE		0x1100
#define MV88E6390_G2_WDOG_CTL_PTR_EVENT			0x1200
#define MV88E6390_G2_WDOG_CTL_PTR_HISTORY		0x1300
#define MV88E6390_G2_WDOG_CTL_DATA_MASK			0x00ff
#define MV88E6390_G2_WDOG_CTL_CUT_THROUGH		0x0008
#define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER		0x0004
#define MV88E6390_G2_WDOG_CTL_EGRESS			0x0002
#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ			0x0001

/* Offset 0x1C: QoS Weights Register */
#define MV88E6XXX_G2_QOS_WEIGHTS		0x1c
#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE		0x8000
#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK	0x3f00
#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK	0x7f00
#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK	0x00ff

/* Offset 0x1D: Misc Register */
#define MV88E6XXX_G2_MISC		0x1d
#define MV88E6XXX_G2_MISC_5_BIT_PORT	0x4000
#define MV88E6352_G2_NOEGR_POLICY	0x2000
#define MV88E6390_G2_LAG_ID_4		0x2000

/* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
/* Offset 0x02: Misc Configuration */
#define MV88E6352_G2_SCRATCH_MISC_CFG		0x02
#define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI	0x80
/* Offset 0x60-0x61: GPIO Configuration */
#define MV88E6352_G2_SCRATCH_GPIO_CFG0		0x60
#define MV88E6352_G2_SCRATCH_GPIO_CFG1		0x61
/* Offset 0x62-0x63: GPIO Direction */
#define MV88E6352_G2_SCRATCH_GPIO_DIR0		0x62
#define MV88E6352_G2_SCRATCH_GPIO_DIR1		0x63
#define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT	0
#define MV88E6352_G2_SCRATCH_GPIO_DIR_IN	1
/* Offset 0x64-0x65: GPIO Data */
#define MV88E6352_G2_SCRATCH_GPIO_DATA0		0x64
#define MV88E6352_G2_SCRATCH_GPIO_DATA1		0x65
/* Offset 0x68-0x6F: GPIO Pin Control */
#define MV88E6352_G2_SCRATCH_GPIO_PCTL0		0x68
#define MV88E6352_G2_SCRATCH_GPIO_PCTL1		0x69
#define MV88E6352_G2_SCRATCH_GPIO_PCTL2		0x6A
#define MV88E6352_G2_SCRATCH_GPIO_PCTL3		0x6B
#define MV88E6352_G2_SCRATCH_GPIO_PCTL4		0x6C
#define MV88E6352_G2_SCRATCH_GPIO_PCTL5		0x6D
#define MV88E6352_G2_SCRATCH_GPIO_PCTL6		0x6E
#define MV88E6352_G2_SCRATCH_GPIO_PCTL7		0x6F
#define MV88E6352_G2_SCRATCH_CONFIG_DATA0	0x70
#define MV88E6352_G2_SCRATCH_CONFIG_DATA1	0x71
#define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU	BIT(2)
#define MV88E6352_G2_SCRATCH_CONFIG_DATA2	0x72
#define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK	0x3

#define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO	0
#define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG	1
#define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ	2

#ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2

static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
{
	return 0;
}

int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update);
int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);

int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);

int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
			      struct mii_bus *bus,
			      int addr, int reg, u16 *val);
int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
			       struct mii_bus *bus,
			       int addr, int reg, u16 val);
int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);

int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
			     struct ethtool_eeprom *eeprom, u8 *data);
int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
			     struct ethtool_eeprom *eeprom, u8 *data);

int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
			      struct ethtool_eeprom *eeprom, u8 *data);
int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
			      struct ethtool_eeprom *eeprom, u8 *data);

int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
			   int src_port, u16 data);
int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
				struct mii_bus *bus);
void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
				struct mii_bus *bus);

int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);

int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
				      int port);

extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;

extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;

extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;

int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
				      bool external);

#else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */

static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
{
	if (chip->info->global2_addr) {
		dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
		return -EOPNOTSUPP;
	}

	return 0;
}

static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,
					    int port)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,
					    int port)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
					    struct mii_bus *bus,
					    int addr, int reg, u16 *val)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
					     struct mii_bus *bus,
					     int addr, int reg, u16 val)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip,
					      u8 *addr)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
					   struct ethtool_eeprom *eeprom,
					   u8 *data)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
					   struct ethtool_eeprom *eeprom,
					   u8 *data)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
					    struct ethtool_eeprom *eeprom,
					    u8 *data)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
					    struct ethtool_eeprom *eeprom,
					    u8 *data)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
					 int src_dev, int src_port, u16 data)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
{
	return -EOPNOTSUPP;
}

static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
{
}

static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
					      struct mii_bus *bus)
{
	return 0;
}

static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
					      struct mii_bus *bus)
{
}

static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
{
	return -EOPNOTSUPP;
}

static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};

static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {};
static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {};
static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {};

static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {};

static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
						    bool external)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
{
	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
						    int target, int port)
{
	return -EOPNOTSUPP;
}

#endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */

#endif /* _MV88E6XXX_GLOBAL2_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
ec561276	2	/*
1d90016d	3	* Marvell 88E6xxx Switch Global 2 Registers support
ec561276 VD	4	*
	5	* Copyright (c) 2008 Marvell Semiconductor
	6	*
4333d619 VD	7	* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
4333d619 VD	8	* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
ec561276 VD	9	*/
	10
	11	#ifndef _MV88E6XXX_GLOBAL2_H
	12	#define _MV88E6XXX_GLOBAL2_H
	13
4d5f2ba7	14	#include "chip.h"
ec561276	15
1d90016d	16	/* Offset 0x00: Interrupt Source Register */
d6c5e6af VD	17	#define MV88E6XXX_G2_INT_SRC 0x00
	18	#define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
	19	#define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
	20	#define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
	21	#define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
	22	#define MV88E6352_G2_INT_SRC_SERDES 0x0800
	23	#define MV88E6352_G2_INT_SRC_PHY 0x001f
	24	#define MV88E6390_G2_INT_SRC_PHY 0x07fe
	25
1d90016d VD	26	#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15
	27
	28	/* Offset 0x01: Interrupt Mask Register */
d6c5e6af VD	29	#define MV88E6XXX_G2_INT_MASK 0x01
	30	#define MV88E6XXX_G2_INT_MASK_WDOG 0x8000
	31	#define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000
	32	#define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000
	33	#define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000
	34	#define MV88E6352_G2_INT_MASK_SERDES 0x0800
	35	#define MV88E6352_G2_INT_MASK_PHY 0x001f
	36	#define MV88E6390_G2_INT_MASK_PHY 0x07fe
6bff47be VD	37
	38	/* Offset 0x02: MGMT Enable Register 2x */
	39	#define MV88E6XXX_G2_MGMT_EN_2X 0x02
	40
	41	/* Offset 0x03: MGMT Enable Register 0x */
	42	#define MV88E6XXX_G2_MGMT_EN_0X 0x03
	43
1d90016d VD	44	/* Offset 0x04: Flow Control Delay Register */
1d90016d VD	45	#define MV88E6XXX_G2_FLOW_CTL 0x04
6bff47be VD	46
	47	/* Offset 0x05: Switch Management Register */
	48	#define MV88E6XXX_G2_SWITCH_MGMT 0x05
	49	#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000
	50	#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000
	51	#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
	52	#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
	53	#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
067e474a VD	54
	55	/* Offset 0x06: Device Mapping Table Register */
	56	#define MV88E6XXX_G2_DEVICE_MAPPING 0x06
	57	#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000
	58	#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00
c7f047b6 VD	59	#define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f
c7f047b6 VD	60	#define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f
56dc7347 VD	61
	62	/* Offset 0x07: Trunk Mask Table Register */
	63	#define MV88E6XXX_G2_TRUNK_MASK 0x07
	64	#define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000
	65	#define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000
	66	#define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800
	67
	68	/* Offset 0x08: Trunk Mapping Table Register */
	69	#define MV88E6XXX_G2_TRUNK_MAPPING 0x08
	70	#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000
	71	#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800
cd8da8bb VD	72
	73	/* Offset 0x09: Ingress Rate Command Register */
	74	#define MV88E6XXX_G2_IRL_CMD 0x09
	75	#define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000
	76	#define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000
	77	#define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000
	78	#define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000
	79	#define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000
	80	#define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000
	81	#define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000
	82	#define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000
	83	#define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000
	84	#define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000
	85	#define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000
	86	#define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000
	87	#define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00
	88	#define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00
	89	#define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0
	90	#define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f
	91
	92	/* Offset 0x0A: Ingress Rate Data Register */
	93	#define MV88E6XXX_G2_IRL_DATA 0x0a
	94	#define MV88E6XXX_G2_IRL_DATA_MASK 0xffff
	95
67d1ea8e VD	96	/* Offset 0x0B: Cross-chip Port VLAN Register */
	97	#define MV88E6XXX_G2_PVT_ADDR 0x0b
	98	#define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000
	99	#define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000
	100	#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000
	101	#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000
	102	#define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000
	103	#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff
	104
	105	/* Offset 0x0C: Cross-chip Port VLAN Data Register */
	106	#define MV88E6XXX_G2_PVT_DATA 0x0c
	107	#define MV88E6XXX_G2_PVT_DATA_MASK 0x7f
	108
ed44152f VD	109	/* Offset 0x0D: Switch MAC/WoL/WoF Register */
	110	#define MV88E6XXX_G2_SWITCH_MAC 0x0d
	111	#define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000
	112	#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00
	113	#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff
	114
1d90016d VD	115	/* Offset 0x0E: ATU Stats Register */
	116	#define MV88E6XXX_G2_ATU_STATS 0x0e
	117
	118	/* Offset 0x0F: Priority Override Table */
	119	#define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f
	120	#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000
	121	#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000
	122	#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
	123	#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080
	124	#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
	125	#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008
	126	#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007
7fc8c9d5 VD	127
	128	/* Offset 0x14: EEPROM Command */
	129	#define MV88E6XXX_G2_EEPROM_CMD 0x14
	130	#define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000
	131	#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000
	132	#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000
	133	#define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000
	134	#define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000
	135	#define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800
	136	#define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400
	137	#define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff
	138	#define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff
	139
	140	/* Offset 0x15: EEPROM Data */
	141	#define MV88E6352_G2_EEPROM_DATA 0x15
	142	#define MV88E6352_G2_EEPROM_DATA_MASK 0xffff
	143
	144	/* Offset 0x15: EEPROM Addr */
	145	#define MV88E6390_G2_EEPROM_ADDR 0x15
	146	#define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff
	147
1d90016d	148	/* Offset 0x16: AVB Command Register */
0d632c3d BS	149	#define MV88E6352_G2_AVB_CMD 0x16
	150	#define MV88E6352_G2_AVB_CMD_BUSY 0x8000
	151	#define MV88E6352_G2_AVB_CMD_OP_READ 0x4000
	152	#define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000
	153	#define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000
	154	#define MV88E6390_G2_AVB_CMD_OP_READ 0x0000
	155	#define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000
	156	#define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000
	157	#define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00
	158	#define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe
a469a612	159	#define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
0d632c3d BS	160	#define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
	161	#define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00
	162	#define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e
	163	#define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f
	164	#define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0
	165	#define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1
	166	#define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2
	167	#define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3
	168	#define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0
	169	#define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f
1d90016d VD	170
	171	/* Offset 0x17: AVB Data Register */
	172	#define MV88E6352_G2_AVB_DATA 0x17
d23a83f2	173
e289ef0d VD	174	/* Offset 0x18: SMI PHY Command Register */
	175	#define MV88E6XXX_G2_SMI_PHY_CMD 0x18
	176	#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000
	177	#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000
	178	#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000
	179	#define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000
	180	#define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000
	181	#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000
	182	#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000
	183	#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000
	184	#define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00
	185	#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400
	186	#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800
	187	#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000
	188	#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400
	189	#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800
	190	#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00
	191	#define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0
	192	#define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f
	193	#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff
	194
	195	/* Offset 0x19: SMI PHY Data Register */
	196	#define MV88E6XXX_G2_SMI_PHY_DATA 0x19
	197
1d90016d VD	198	/* Offset 0x1A: Scratch and Misc. Register */
	199	#define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a
	200	#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000
	201	#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00
	202	#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
3b19df73 VD	203
	204	/* Offset 0x1B: Watch Dog Control Register */
	205	#define MV88E6352_G2_WDOG_CTL 0x1b
	206	#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080
	207	#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040
	208	#define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020
	209	#define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010
	210	#define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
	211	#define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004
	212	#define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002
	213	#define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001
	214
	215	/* Offset 0x1B: Watch Dog Control Register */
	216	#define MV88E6390_G2_WDOG_CTL 0x1b
	217	#define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000
	218	#define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00
	219	#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000
	220	#define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000
	221	#define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100
	222	#define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200
	223	#define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300
	224	#define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff
	225	#define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008
	226	#define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004
	227	#define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002
	228	#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001
	229
1d90016d VD	230	/* Offset 0x1C: QoS Weights Register */
	231	#define MV88E6XXX_G2_QOS_WEIGHTS 0x1c
	232	#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000
	233	#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00
	234	#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00
	235	#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff
	236
	237	/* Offset 0x1D: Misc Register */
	238	#define MV88E6XXX_G2_MISC 0x1d
	239	#define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000
	240	#define MV88E6352_G2_NOEGR_POLICY 0x2000
	241	#define MV88E6390_G2_LAG_ID_4 0x2000
d23a83f2	242
a73ccd61 BS	243	/* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
	244	/* Offset 0x02: Misc Configuration */
	245	#define MV88E6352_G2_SCRATCH_MISC_CFG 0x02
	246	#define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80
	247	/* Offset 0x60-0x61: GPIO Configuration */
	248	#define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60
	249	#define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61
	250	/* Offset 0x62-0x63: GPIO Direction */
	251	#define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62
	252	#define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63
	253	#define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0
	254	#define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1
	255	/* Offset 0x64-0x65: GPIO Data */
	256	#define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64
	257	#define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65
	258	/* Offset 0x68-0x6F: GPIO Pin Control */
	259	#define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68
	260	#define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69
	261	#define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A
	262	#define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B
	263	#define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C
	264	#define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D
	265	#define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E
	266	#define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F
2510babc AL	267	#define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70
	268	#define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71
	269	#define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2)
	270	#define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72
	271	#define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3
a73ccd61 BS	272
	273	#define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0
	274	#define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1
	275	#define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2
	276
ca070c10 VD	277	#ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
	278
	279	static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
	280	{
	281	return 0;
	282	}
	283
b000be95 BS	284	int mv88e6xxx_g2_read(struct mv88e6xxx_chip chip, int reg, u16 val);
	285	int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
	286	int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update);
	287	int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
	288
cd8da8bb VD	289	int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
	290	int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
	291
ee26a228 AL	292	int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
	293	struct mii_bus *bus,
	294	int addr, int reg, u16 *val);
	295	int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
	296	struct mii_bus *bus,
	297	int addr, int reg, u16 val);
ec561276	298	int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip chip, u8 addr);
98fc3c6f VD	299
	300	int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
	301	struct ethtool_eeprom eeprom, u8 data);
	302	int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
	303	struct ethtool_eeprom eeprom, u8 data);
	304
ec561276 VD	305	int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
	306	struct ethtool_eeprom eeprom, u8 data);
	307	int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
	308	struct ethtool_eeprom eeprom, u8 data);
98fc3c6f	309
17a1594e VD	310	int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
17a1594e VD	311	int src_port, u16 data);
81228996 VD	312	int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
81228996 VD	313
dc30c35b AL	314	int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
dc30c35b AL	315	void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
51c901a7	316
6f88284f AL	317	int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
	318	struct mii_bus *bus);
	319	void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
	320	struct mii_bus *bus);
	321
51c901a7 VD	322	int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
51c901a7 VD	323	int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
ec561276	324
9e907d73 VD	325	int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
9e907d73 VD	326
b28f872d VD	327	int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
b28f872d VD	328
c7f047b6 VD	329	int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
	330	int port);
	331
fcd25166	332	extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
61303736	333	extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
fcd25166	334
a469a612	335	extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
0d632c3d BS	336	extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
	337	extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
	338
a73ccd61 BS	339	extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
a73ccd61 BS	340
2510babc AL	341	int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
	342	bool external);
	343
ca070c10 VD	344	#else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
	345
	346	static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
	347	{
9069c13a	348	if (chip->info->global2_addr) {
ca070c10 VD	349	dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
	350	return -EOPNOTSUPP;
	351	}
	352
	353	return 0;
	354	}
	355
46182452	356	static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip chip, int reg, u16 val)
b000be95 BS	357	{
	358	return -EOPNOTSUPP;
	359	}
	360
46182452	361	static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
b000be95 BS	362	{
	363	return -EOPNOTSUPP;
	364	}
	365
46182452	366	static inline int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
b000be95 BS	367	{
	368	return -EOPNOTSUPP;
	369	}
	370
46182452	371	static inline int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
b000be95 BS	372	{
	373	return -EOPNOTSUPP;
	374	}
	375
cd8da8bb VD	376	static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,
	377	int port)
	378	{
	379	return -EOPNOTSUPP;
	380	}
	381
	382	static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,
	383	int port)
	384	{
	385	return -EOPNOTSUPP;
	386	}
	387
ca070c10	388	static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
ee26a228	389	struct mii_bus *bus,
ca070c10 VD	390	int addr, int reg, u16 *val)
	391	{
	392	return -EOPNOTSUPP;
	393	}
	394
	395	static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
ee26a228	396	struct mii_bus *bus,
ca070c10 VD	397	int addr, int reg, u16 val)
	398	{
	399	return -EOPNOTSUPP;
	400	}
	401
	402	static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip,
	403	u8 *addr)
	404	{
	405	return -EOPNOTSUPP;
	406	}
	407
98fc3c6f VD	408	static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
	409	struct ethtool_eeprom *eeprom,
	410	u8 *data)
	411	{
	412	return -EOPNOTSUPP;
	413	}
	414
	415	static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
	416	struct ethtool_eeprom *eeprom,
	417	u8 *data)
	418	{
	419	return -EOPNOTSUPP;
	420	}
	421
ca070c10 VD	422	static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
	423	struct ethtool_eeprom *eeprom,
	424	u8 *data)
	425	{
	426	return -EOPNOTSUPP;
	427	}
	428
	429	static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
	430	struct ethtool_eeprom *eeprom,
	431	u8 *data)
	432	{
	433	return -EOPNOTSUPP;
	434	}
	435
59b2c314 AB	436	static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
59b2c314 AB	437	int src_dev, int src_port, u16 data)
17a1594e VD	438	{
	439	return -EOPNOTSUPP;
	440	}
	441
59b2c314	442	static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
81228996 VD	443	{
	444	return -EOPNOTSUPP;
	445	}
	446
dc30c35b AL	447	static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
	448	{
	449	return -EOPNOTSUPP;
	450	}
	451
	452	static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
	453	{
	454	}
	455
6f88284f AL	456	static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
	457	struct mii_bus *bus)
	458	{
	459	return 0;
	460	}
	461
	462	static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
	463	struct mii_bus *bus)
	464	{
	465	}
	466
51c901a7 VD	467	static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
	468	{
	469	return -EOPNOTSUPP;
	470	}
	471
	472	static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
6e55f698 AL	473	{
	474	return -EOPNOTSUPP;
	475	}
	476
9e907d73 VD	477	static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
	478	{
	479	return -EOPNOTSUPP;
	480	}
	481
fcd25166	482	static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
61303736	483	static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
fcd25166	484
a469a612	485	static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {};
0d632c3d BS	486	static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {};
	487	static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {};
	488
a73ccd61 BS	489	static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {};
a73ccd61 BS	490
2510babc AL	491	static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
	492	bool external)
	493	{
	494	return -EOPNOTSUPP;
	495	}
	496
b28f872d VD	497	static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
	498	{
	499	return -EOPNOTSUPP;
	500	}
	501
c7f047b6 VD	502	static inline int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
	503	int target, int port)
	504	{
	505	return -EOPNOTSUPP;
	506	}
	507
ca070c10 VD	508	#endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
ca070c10 VD	509
ec561276	510	#endif /* _MV88E6XXX_GLOBAL2_H */